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-rw-r--r--recipes-bsp/u-boot/u-boot-2019.07/0003-dts-Add-initial-support-for-bcm2838.patch333
1 files changed, 0 insertions, 333 deletions
diff --git a/recipes-bsp/u-boot/u-boot-2019.07/0003-dts-Add-initial-support-for-bcm2838.patch b/recipes-bsp/u-boot/u-boot-2019.07/0003-dts-Add-initial-support-for-bcm2838.patch
deleted file mode 100644
index b6b8ca7..0000000
--- a/recipes-bsp/u-boot/u-boot-2019.07/0003-dts-Add-initial-support-for-bcm2838.patch
+++ /dev/null
@@ -1,333 +0,0 @@
1From 9a6dca219480423f6c9dd5804e5890d434cc11b8 Mon Sep 17 00:00:00 2001
2From: Andrei Gherzan <andrei@balena.io>
3Date: Wed, 17 Jul 2019 15:32:46 +0100
4Subject: [PATCH 03/12] dts: Add initial support for bcm2838
5
6Signed-off-by: Andrei Gherzan <andrei@balena.io>
7Upstream-status: Pending
8---
9 arch/arm/dts/Makefile | 3 +-
10 arch/arm/dts/bcm2838-rpi-4-b.dts | 52 +++++++
11 arch/arm/dts/bcm2838.dtsi | 237 +++++++++++++++++++++++++++++++
12 3 files changed, 291 insertions(+), 1 deletion(-)
13 create mode 100644 arch/arm/dts/bcm2838-rpi-4-b.dts
14 create mode 100644 arch/arm/dts/bcm2838.dtsi
15
16diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
17index 20dbc2ff84..fdb55f7fde 100644
18--- a/arch/arm/dts/Makefile
19+++ b/arch/arm/dts/Makefile
20@@ -749,7 +749,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
21 bcm2837-rpi-3-a-plus.dtb \
22 bcm2837-rpi-3-b.dtb \
23 bcm2837-rpi-3-b-plus.dtb \
24- bcm2837-rpi-cm3-io3.dtb
25+ bcm2837-rpi-cm3-io3.dtb \
26+ bcm2838-rpi-4-b.dtb
27
28 dtb-$(CONFIG_ARCH_BCM63158) += \
29 bcm963158.dtb
30diff --git a/arch/arm/dts/bcm2838-rpi-4-b.dts b/arch/arm/dts/bcm2838-rpi-4-b.dts
31new file mode 100644
32index 0000000000..fa7fcfed9d
33--- /dev/null
34+++ b/arch/arm/dts/bcm2838-rpi-4-b.dts
35@@ -0,0 +1,52 @@
36+/dts-v1/;
37+#include "bcm2838.dtsi"
38+
39+/ {
40+ compatible = "raspberrypi,4-model-b","brcm,bcm2838","brcm,bcm2837";
41+ model = "Raspberry Pi 4 Model B";
42+
43+ memory {
44+ reg = <0 0 0x0>;
45+ };
46+
47+ leds {
48+ act {
49+ gpios = <&gpio 47 0>;
50+ };
51+ };
52+};
53+
54+/* uart0 communicates with the BT module */
55+&uart0 {
56+ pinctrl-names = "default";
57+ pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
58+ status = "okay";
59+};
60+
61+/* uart1 is mapped to the pin header */
62+&uart1 {
63+ pinctrl-names = "default";
64+ pinctrl-0 = <&uart1_pins>;
65+ status = "okay";
66+};
67+
68+&sdhci {
69+ status = "disabled";
70+};
71+
72+&sdhost {
73+ status = "disabled";
74+};
75+
76+&emmc2 {
77+ compatible = "brcm,bcm2711-emmc2";
78+ status = "okay";
79+};
80+
81+&gpio {
82+ uart1_pins: uart1_pins {
83+ brcm,pins;
84+ brcm,function;
85+ brcm,pull;
86+ };
87+};
88diff --git a/arch/arm/dts/bcm2838.dtsi b/arch/arm/dts/bcm2838.dtsi
89new file mode 100644
90index 0000000000..19b2d7b905
91--- /dev/null
92+++ b/arch/arm/dts/bcm2838.dtsi
93@@ -0,0 +1,237 @@
94+#include "bcm283x.dtsi"
95+#include <dt-bindings/interrupt-controller/arm-gic.h>
96+#include <dt-bindings/power/raspberrypi-power.h>
97+
98+/ {
99+ compatible = "brcm,bcm2838";
100+
101+ #address-cells = <2>;
102+ #size-cells = <1>;
103+
104+ interrupt-parent = <&gic>;
105+
106+ soc {
107+ ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
108+ <0x7c000000 0x0 0xfc000000 0x02000000>,
109+ <0x40000000 0x0 0xff800000 0x00800000>;
110+ dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
111+
112+ gic: gic400@40041000 {
113+ interrupt-controller;
114+ #interrupt-cells = <3>;
115+ compatible = "arm,gic-400";
116+ reg = <0x40041000 0x1000>,
117+ <0x40042000 0x2000>,
118+ <0x40044000 0x2000>,
119+ <0x40046000 0x2000>;
120+ };
121+
122+ thermal: thermal@7d5d2200 {
123+ compatible = "brcm,avs-tmon-bcm2838";
124+ reg = <0x7d5d2200 0x2c>;
125+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
126+ interrupt-names = "tmon";
127+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
128+ #thermal-sensor-cells = <0>;
129+ status = "okay";
130+ };
131+
132+ spi@7e204000 {
133+ reg = <0x7e204000 0x0200>;
134+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
135+ };
136+
137+ pixelvalve@7e206000 {
138+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
139+ };
140+
141+ pixelvalve@7e207000 {
142+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
143+ };
144+
145+ hvs@7e400000 {
146+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
147+ };
148+
149+ emmc2: emmc2@7e340000 {
150+ compatible = "brcm,bcm2711-emmc2";
151+ status = "okay";
152+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
153+ clocks = <&clocks BCM2838_CLOCK_EMMC2>;
154+ reg = <0x7e340000 0x100>;
155+ };
156+
157+ pixelvalve@7e807000 {
158+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
159+ };
160+
161+ };
162+
163+ arm-pmu {
164+ /*
165+ * N.B. the A72 PMU support only exists in arch/arm64, hence
166+ * the fallback to the A53 version.
167+ */
168+ compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
169+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
170+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
171+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
172+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
173+ };
174+
175+ timer {
176+ compatible = "arm,armv7-timer";
177+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
178+ IRQ_TYPE_LEVEL_LOW)>,
179+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
180+ IRQ_TYPE_LEVEL_LOW)>,
181+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
182+ IRQ_TYPE_LEVEL_LOW)>,
183+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
184+ IRQ_TYPE_LEVEL_LOW)>;
185+ arm,cpu-registers-not-fw-configured;
186+ always-on;
187+ };
188+
189+ cpus: cpus {
190+ #address-cells = <1>;
191+ #size-cells = <0>;
192+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
193+
194+ cpu0: cpu@0 {
195+ device_type = "cpu";
196+ compatible = "arm,cortex-a72";
197+ reg = <0>;
198+ enable-method = "spin-table";
199+ cpu-release-addr = <0x0 0x000000d8>;
200+ };
201+
202+ cpu1: cpu@1 {
203+ device_type = "cpu";
204+ compatible = "arm,cortex-a72";
205+ reg = <1>;
206+ enable-method = "spin-table";
207+ cpu-release-addr = <0x0 0x000000e0>;
208+ };
209+
210+ cpu2: cpu@2 {
211+ device_type = "cpu";
212+ compatible = "arm,cortex-a72";
213+ reg = <2>;
214+ enable-method = "spin-table";
215+ cpu-release-addr = <0x0 0x000000e8>;
216+ };
217+
218+ cpu3: cpu@3 {
219+ device_type = "cpu";
220+ compatible = "arm,cortex-a72";
221+ reg = <3>;
222+ enable-method = "spin-table";
223+ cpu-release-addr = <0x0 0x000000f0>;
224+ };
225+ };
226+};
227+
228+&clk_osc {
229+ clock-frequency = <54000000>;
230+};
231+
232+&clocks {
233+ compatible = "brcm,bcm2838-cprman";
234+};
235+
236+&cpu_thermal {
237+ coefficients = <(-487) 410040>;
238+};
239+
240+&dsi0 {
241+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
242+};
243+
244+&dsi1 {
245+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
246+};
247+
248+&gpio {
249+ compatible = "brcm,bcm2838-gpio", "brcm,bcm2835-gpio";
250+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
251+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
252+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
253+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
254+};
255+
256+&vec {
257+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
258+};
259+
260+&usb {
261+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
262+};
263+
264+&hdmi {
265+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
266+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
267+};
268+
269+&uart1 {
270+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
271+};
272+
273+&spi1 {
274+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
275+};
276+
277+&spi2 {
278+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
279+};
280+
281+&i2c0 {
282+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
283+};
284+
285+&i2c1 {
286+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
287+};
288+
289+&i2c2 {
290+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
291+};
292+
293+&mailbox {
294+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
295+};
296+
297+&sdhost {
298+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
299+};
300+
301+&uart0 {
302+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
303+};
304+
305+&dma {
306+ reg = <0x7e007000 0xb00>;
307+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
308+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
309+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
310+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
311+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
312+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
313+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
314+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 7 */
315+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 8 */
316+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 9 */
317+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* dmalite 10 */
318+ interrupt-names = "dma0",
319+ "dma1",
320+ "dma2",
321+ "dma3",
322+ "dma4",
323+ "dma5",
324+ "dma6",
325+ "dma7",
326+ "dma8",
327+ "dma9",
328+ "dma10";
329+ brcm,dma-channel-mask = <0x07f5>;
330+};
331--
3322.22.0
333
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-14 07:09:20 +0000