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diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr46934.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr46934.patch
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+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr46934.patch
@@ -0,0 +1,393 @@
1Upstream-Status:Backport
22011-09-19 chengbin <bin.cheng@arm.com>
3
4 Backport r174035 from mainline
5 2011-05-22 Tom de Vries <tom@codesourcery.com>
6
7 PR middle-end/48689
8 * fold-const.c (fold_checksum_tree): Guard TREE_CHAIN use with
9 CODE_CONTAINS_STRUCT (TS_COMMON).
10
11 Backport r172297 from mainline
12 2011-04-11 Chung-Lin Tang <cltang@codesourcery.com>
13 Richard Earnshaw <rearnsha@arm.com>
14
15 PR target/48250
16 * config/arm/arm.c (arm_legitimize_reload_address): Update cases
17 to use sign-magnitude offsets. Reject unsupported unaligned
18 cases. Add detailed description in comments.
19 * config/arm/arm.md (reload_outdf): Disable for ARM mode; change
20 condition from TARGET_32BIT to TARGET_ARM.
21
22 Backport r171978 from mainline
23 2011-04-05 Tom de Vries <tom@codesourcery.com>
24
25 PR target/43920
26 * config/arm/arm.h (BRANCH_COST): Set to 1 for Thumb-2 when optimizing
27 for size.
28
29 Backport r171632 from mainline
30 2011-03-28 Richard Sandiford <richard.sandiford@linaro.org>
31
32 * builtins.c (expand_builtin_memset_args): Use gen_int_mode
33 instead of GEN_INT.
34
35 Backport r171379 from mainline
36 2011-03-23 Chung-Lin Tang <cltang@codesourcery.com>
37
38 PR target/46934
39 * config/arm/arm.md (casesi): Use the gen_int_mode() function
40 to subtract lower bound instead of GEN_INT().
41
42 Backport r171251 from mainline
43 2011-03-21 Daniel Jacobowitz <dan@codesourcery.com>
44
45 * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test
46 for barrier handlers.
47
48 Backport r171096 from mainline
49 2011-03-17 Chung-Lin Tang <cltang@codesourcery.com>
50
51 PR target/43872
52 * config/arm/arm.c (arm_get_frame_offsets): Adjust early
53 return condition with !cfun->calls_alloca.
54
55Index: gcc-4_6-branch/gcc/builtins.c
56===================================================================
57--- gcc-4_6-branch.orig/gcc/builtins.c 2011-10-17 17:45:32.050502963 -0700
58+++ gcc-4_6-branch/gcc/builtins.c 2011-10-17 17:46:11.154696878 -0700
59@@ -3972,6 +3972,7 @@
60 {
61 tree fndecl, fn;
62 enum built_in_function fcode;
63+ enum machine_mode val_mode;
64 char c;
65 unsigned int dest_align;
66 rtx dest_mem, dest_addr, len_rtx;
67@@ -4006,14 +4007,14 @@
68
69 len_rtx = expand_normal (len);
70 dest_mem = get_memory_rtx (dest, len);
71+ val_mode = TYPE_MODE (unsigned_char_type_node);
72
73 if (TREE_CODE (val) != INTEGER_CST)
74 {
75 rtx val_rtx;
76
77 val_rtx = expand_normal (val);
78- val_rtx = convert_to_mode (TYPE_MODE (unsigned_char_type_node),
79- val_rtx, 0);
80+ val_rtx = convert_to_mode (val_mode, val_rtx, 0);
81
82 /* Assume that we can memset by pieces if we can store
83 * the coefficients by pieces (in the required modes).
84@@ -4024,8 +4025,7 @@
85 builtin_memset_read_str, &c, dest_align,
86 true))
87 {
88- val_rtx = force_reg (TYPE_MODE (unsigned_char_type_node),
89- val_rtx);
90+ val_rtx = force_reg (val_mode, val_rtx);
91 store_by_pieces (dest_mem, tree_low_cst (len, 1),
92 builtin_memset_gen_str, val_rtx, dest_align,
93 true, 0);
94@@ -4051,7 +4051,8 @@
95 true))
96 store_by_pieces (dest_mem, tree_low_cst (len, 1),
97 builtin_memset_read_str, &c, dest_align, true, 0);
98- else if (!set_storage_via_setmem (dest_mem, len_rtx, GEN_INT (c),
99+ else if (!set_storage_via_setmem (dest_mem, len_rtx,
100+ gen_int_mode (c, val_mode),
101 dest_align, expected_align,
102 expected_size))
103 goto do_libcall;
104Index: gcc-4_6-branch/gcc/config/arm/arm.c
105===================================================================
106--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2011-10-17 17:45:41.914551883 -0700
107+++ gcc-4_6-branch/gcc/config/arm/arm.c 2011-10-17 17:48:35.447412371 -0700
108@@ -6406,23 +6406,126 @@
109 HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
110 HOST_WIDE_INT low, high;
111
112- if (mode == DImode || (mode == DFmode && TARGET_SOFT_FLOAT))
113- low = ((val & 0xf) ^ 0x8) - 0x8;
114- else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)
115- /* Need to be careful, -256 is not a valid offset. */
116- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
117- else if (mode == SImode
118- || (mode == SFmode && TARGET_SOFT_FLOAT)
119- || ((mode == HImode || mode == QImode) && ! arm_arch4))
120- /* Need to be careful, -4096 is not a valid offset. */
121- low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);
122- else if ((mode == HImode || mode == QImode) && arm_arch4)
123- /* Need to be careful, -256 is not a valid offset. */
124- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
125- else if (GET_MODE_CLASS (mode) == MODE_FLOAT
126- && TARGET_HARD_FLOAT && TARGET_FPA)
127- /* Need to be careful, -1024 is not a valid offset. */
128- low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);
129+ /* Detect coprocessor load/stores. */
130+ bool coproc_p = ((TARGET_HARD_FLOAT
131+ && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
132+ && (mode == SFmode || mode == DFmode
133+ || (mode == DImode && TARGET_MAVERICK)))
134+ || (TARGET_REALLY_IWMMXT
135+ && VALID_IWMMXT_REG_MODE (mode))
136+ || (TARGET_NEON
137+ && (VALID_NEON_DREG_MODE (mode)
138+ || VALID_NEON_QREG_MODE (mode))));
139+
140+ /* For some conditions, bail out when lower two bits are unaligned. */
141+ if ((val & 0x3) != 0
142+ /* Coprocessor load/store indexes are 8-bits + '00' appended. */
143+ && (coproc_p
144+ /* For DI, and DF under soft-float: */
145+ || ((mode == DImode || mode == DFmode)
146+ /* Without ldrd, we use stm/ldm, which does not
147+ fair well with unaligned bits. */
148+ && (! TARGET_LDRD
149+ /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
150+ || TARGET_THUMB2))))
151+ return false;
152+
153+ /* When breaking down a [reg+index] reload address into [(reg+high)+low],
154+ of which the (reg+high) gets turned into a reload add insn,
155+ we try to decompose the index into high/low values that can often
156+ also lead to better reload CSE.
157+ For example:
158+ ldr r0, [r2, #4100] // Offset too large
159+ ldr r1, [r2, #4104] // Offset too large
160+
161+ is best reloaded as:
162+ add t1, r2, #4096
163+ ldr r0, [t1, #4]
164+ add t2, r2, #4096
165+ ldr r1, [t2, #8]
166+
167+ which post-reload CSE can simplify in most cases to eliminate the
168+ second add instruction:
169+ add t1, r2, #4096
170+ ldr r0, [t1, #4]
171+ ldr r1, [t1, #8]
172+
173+ The idea here is that we want to split out the bits of the constant
174+ as a mask, rather than as subtracting the maximum offset that the
175+ respective type of load/store used can handle.
176+
177+ When encountering negative offsets, we can still utilize it even if
178+ the overall offset is positive; sometimes this may lead to an immediate
179+ that can be constructed with fewer instructions.
180+ For example:
181+ ldr r0, [r2, #0x3FFFFC]
182+
183+ This is best reloaded as:
184+ add t1, r2, #0x400000
185+ ldr r0, [t1, #-4]
186+
187+ The trick for spotting this for a load insn with N bits of offset
188+ (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
189+ negative offset that is going to make bit N and all the bits below
190+ it become zero in the remainder part.
191+
192+ The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
193+ to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
194+ used in most cases of ARM load/store instructions. */
195+
196+#define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
197+ (((VAL) & ((1 << (N)) - 1)) \
198+ ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
199+ : 0)
200+
201+ if (coproc_p)
202+ low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
203+ else if (GET_MODE_SIZE (mode) == 8)
204+ {
205+ if (TARGET_LDRD)
206+ low = (TARGET_THUMB2
207+ ? SIGN_MAG_LOW_ADDR_BITS (val, 10)
208+ : SIGN_MAG_LOW_ADDR_BITS (val, 8));
209+ else
210+ /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
211+ to access doublewords. The supported load/store offsets are
212+ -8, -4, and 4, which we try to produce here. */
213+ low = ((val & 0xf) ^ 0x8) - 0x8;
214+ }
215+ else if (GET_MODE_SIZE (mode) < 8)
216+ {
217+ /* NEON element load/stores do not have an offset. */
218+ if (TARGET_NEON_FP16 && mode == HFmode)
219+ return false;
220+
221+ if (TARGET_THUMB2)
222+ {
223+ /* Thumb-2 has an asymmetrical index range of (-256,4096).
224+ Try the wider 12-bit range first, and re-try if the result
225+ is out of range. */
226+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
227+ if (low < -255)
228+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
229+ }
230+ else
231+ {
232+ if (mode == HImode || mode == HFmode)
233+ {
234+ if (arm_arch4)
235+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
236+ else
237+ {
238+ /* The storehi/movhi_bytes fallbacks can use only
239+ [-4094,+4094] of the full ldrb/strb index range. */
240+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
241+ if (low == 4095 || low == -4095)
242+ return false;
243+ }
244+ }
245+ else
246+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
247+ }
248+ }
249 else
250 return false;
251
252@@ -15415,7 +15518,10 @@
253 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
254 /* A leaf function does not need any stack alignment if it has nothing
255 on the stack. */
256- if (leaf && frame_size == 0)
257+ if (leaf && frame_size == 0
258+ /* However if it calls alloca(), we have a dynamically allocated
259+ block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
260+ && ! cfun->calls_alloca)
261 {
262 offsets->outgoing_args = offsets->soft_frame;
263 offsets->locals_base = offsets->soft_frame;
264Index: gcc-4_6-branch/gcc/config/arm/arm.h
265===================================================================
266--- gcc-4_6-branch.orig/gcc/config/arm/arm.h 2011-10-17 17:45:41.910551858 -0700
267+++ gcc-4_6-branch/gcc/config/arm/arm.h 2011-10-17 17:48:35.447412371 -0700
268@@ -2041,7 +2041,8 @@
269 /* Try to generate sequences that don't involve branches, we can then use
270 conditional instructions */
271 #define BRANCH_COST(speed_p, predictable_p) \
272- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
273+ (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
274+ : (optimize > 0 ? 2 : 0))
275
276 /* Position Independent Code. */
277 /* We decide which register to use based on the compilation options and
278Index: gcc-4_6-branch/gcc/config/arm/arm.md
279===================================================================
280--- gcc-4_6-branch.orig/gcc/config/arm/arm.md 2011-10-17 17:46:11.002696119 -0700
281+++ gcc-4_6-branch/gcc/config/arm/arm.md 2011-10-17 17:46:11.202697111 -0700
282@@ -6187,7 +6187,7 @@
283 [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
284 (match_operand:DF 1 "s_register_operand" "r")
285 (match_operand:SI 2 "s_register_operand" "=&r")]
286- "TARGET_32BIT"
287+ "TARGET_THUMB2"
288 "
289 {
290 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
291@@ -8359,7 +8359,8 @@
292 rtx reg = gen_reg_rtx (SImode);
293
294 emit_insn (gen_addsi3 (reg, operands[0],
295- GEN_INT (-INTVAL (operands[1]))));
296+ gen_int_mode (-INTVAL (operands[1]),
297+ SImode)));
298 operands[0] = reg;
299 }
300
301Index: gcc-4_6-branch/gcc/config/arm/unwind-arm.c
302===================================================================
303--- gcc-4_6-branch.orig/gcc/config/arm/unwind-arm.c 2011-10-17 17:45:41.390549278 -0700
304+++ gcc-4_6-branch/gcc/config/arm/unwind-arm.c 2011-10-17 17:46:11.000000000 -0700
305@@ -1196,8 +1196,6 @@
306 ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
307
308 if (data[0] & uint32_highbit)
309- phase2_call_unexpected_after_unwind = 1;
310- else
311 {
312 data += rtti_count + 1;
313 /* Setup for entry to the handler. */
314@@ -1207,6 +1205,8 @@
315 _Unwind_SetGR (context, 0, (_uw) ucbp);
316 return _URC_INSTALL_CONTEXT;
317 }
318+ else
319+ phase2_call_unexpected_after_unwind = 1;
320 }
321 if (data[0] & uint32_highbit)
322 data++;
323Index: gcc-4_6-branch/gcc/fold-const.c
324===================================================================
325--- gcc-4_6-branch.orig/gcc/fold-const.c 2011-10-17 17:45:32.050502963 -0700
326+++ gcc-4_6-branch/gcc/fold-const.c 2011-10-17 17:46:11.178696990 -0700
327@@ -13788,7 +13788,8 @@
328 if (TREE_CODE_CLASS (code) != tcc_type
329 && TREE_CODE_CLASS (code) != tcc_declaration
330 && code != TREE_LIST
331- && code != SSA_NAME)
332+ && code != SSA_NAME
333+ && CODE_CONTAINS_STRUCT (code, TS_COMMON))
334 fold_checksum_tree (TREE_CHAIN (expr), ctx, ht);
335 switch (TREE_CODE_CLASS (code))
336 {
337Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c
338===================================================================
339--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr40887.c 2011-06-24 08:13:47.000000000 -0700
340+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c 2011-10-17 17:46:11.182697014 -0700
341@@ -1,5 +1,6 @@
342 /* { dg-options "-O2 -march=armv5te" } */
343 /* { dg-final { scan-assembler "blx" } } */
344+/* { dg-prune-output "switch .* conflicts with" } */
345
346 int (*indirect_func)();
347
348Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c
349===================================================================
350--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr42575.c 2011-06-24 08:13:47.000000000 -0700
351+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c 2011-10-17 17:46:11.182697014 -0700
352@@ -1,4 +1,4 @@
353-/* { dg-options "-O2 -march=armv7-a" } */
354+/* { dg-options "-O2" } */
355 /* Make sure RA does good job allocating registers and avoids
356 unnecessary moves. */
357 /* { dg-final { scan-assembler-not "mov" } } */
358Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c
359===================================================================
360--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr43698.c 2011-06-24 08:13:47.000000000 -0700
361+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c 2011-10-17 17:46:11.182697014 -0700
362@@ -1,5 +1,5 @@
363 /* { dg-do run } */
364-/* { dg-options "-Os -march=armv7-a" } */
365+/* { dg-options "-Os" } */
366 #include <stdint.h>
367 #include <stdlib.h>
368
369Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c
370===================================================================
371--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr44788.c 2011-06-24 08:13:47.000000000 -0700
372+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c 2011-10-17 17:46:11.182697014 -0700
373@@ -1,6 +1,6 @@
374 /* { dg-do compile } */
375 /* { dg-require-effective-target arm_thumb2_ok } */
376-/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
377+/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -mfpu=vfp3 -mfloat-abi=softfp" } */
378
379 void joint_decode(float* mlt_buffer1, int t) {
380 int i;
381Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c
382===================================================================
383--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/sync-1.c 2011-06-24 08:13:47.000000000 -0700
384+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c 2011-10-17 17:46:11.182697014 -0700
385@@ -1,5 +1,6 @@
386-/* { dg-do run } */
387-/* { dg-options "-O2 -march=armv7-a" } */
388+
389+/* { dg-do run { target sync_int_long } } */
390+/* { dg-options "-O2" } */
391
392 volatile int mem;
393
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