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Diffstat (limited to 'toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch')
-rw-r--r-- | toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch | 147 |
1 files changed, 0 insertions, 147 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch deleted file mode 100644 index 02f8e5177..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch +++ /dev/null | |||
@@ -1,147 +0,0 @@ | |||
1 | 2011-10-19 Andrew Stubbs <ams@codesourcery.com> | ||
2 | |||
3 | Backport from FSF: | ||
4 | |||
5 | 2011-09-09 Andrew Stubbs <ams@codesourcery.com> | ||
6 | |||
7 | gcc/ | ||
8 | * config/arm/arm-cores.def (generic-armv7-a): New architecture. | ||
9 | * config/arm/arm-tables.opt: Regenerate. | ||
10 | * config/arm/arm-tune.md: Regenerate. | ||
11 | * config/arm/arm.c (arm_file_start): Output .arch directive when | ||
12 | user passes -mcpu=generic-*. | ||
13 | (arm_issue_rate): Add genericv7a support. | ||
14 | * config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec. | ||
15 | (ASM_CPU_SPEC): New define. | ||
16 | * config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec). | ||
17 | * config/arm/semi.h (ASM_SPEC): Likewise. | ||
18 | * doc/invoke.texi (ARM Options): Document -mcpu=generic-* | ||
19 | and -mtune=generic-*. | ||
20 | |||
21 | === modified file 'gcc/config/arm/arm-cores.def' | ||
22 | --- old/gcc/config/arm/arm-cores.def 2011-06-14 16:00:30 +0000 | ||
23 | +++ new/gcc/config/arm/arm-cores.def 2011-10-19 16:46:51 +0000 | ||
24 | @@ -124,6 +124,7 @@ | ||
25 | ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e) | ||
26 | ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2) | ||
27 | ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2) | ||
28 | +ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex) | ||
29 | ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5) | ||
30 | ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) | ||
31 | ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) | ||
32 | @@ -135,3 +136,4 @@ | ||
33 | ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex) | ||
34 | ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex) | ||
35 | ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex) | ||
36 | + | ||
37 | |||
38 | === modified file 'gcc/config/arm/arm-tune.md' | ||
39 | --- old/gcc/config/arm/arm-tune.md 2011-06-14 14:37:30 +0000 | ||
40 | +++ new/gcc/config/arm/arm-tune.md 2011-10-19 16:46:51 +0000 | ||
41 | @@ -1,5 +1,5 @@ | ||
42 | ;; -*- buffer-read-only: t -*- | ||
43 | ;; Generated automatically by gentune.sh from arm-cores.def | ||
44 | (define_attr "tune" | ||
45 | - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0" | ||
46 | + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0" | ||
47 | (const (symbol_ref "((enum attr_tune) arm_tune)"))) | ||
48 | |||
49 | === modified file 'gcc/config/arm/arm.c' | ||
50 | --- old/gcc/config/arm/arm.c 2011-10-11 02:31:01 +0000 | ||
51 | +++ new/gcc/config/arm/arm.c 2011-10-19 16:46:51 +0000 | ||
52 | @@ -22185,6 +22185,8 @@ | ||
53 | const char *fpu_name; | ||
54 | if (arm_selected_arch) | ||
55 | asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name); | ||
56 | + else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0) | ||
57 | + asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8); | ||
58 | else | ||
59 | asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name); | ||
60 | |||
61 | @@ -23717,6 +23719,7 @@ | ||
62 | case cortexr4: | ||
63 | case cortexr4f: | ||
64 | case cortexr5: | ||
65 | + case genericv7a: | ||
66 | case cortexa5: | ||
67 | case cortexa8: | ||
68 | case cortexa9: | ||
69 | |||
70 | === modified file 'gcc/config/arm/arm.h' | ||
71 | --- old/gcc/config/arm/arm.h 2011-09-05 14:32:11 +0000 | ||
72 | +++ new/gcc/config/arm/arm.h 2011-10-19 16:46:51 +0000 | ||
73 | @@ -198,6 +198,7 @@ | ||
74 | Do not define this macro if it does not need to do anything. */ | ||
75 | #define EXTRA_SPECS \ | ||
76 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | ||
77 | + { "asm_cpu_spec", ASM_CPU_SPEC }, \ | ||
78 | SUBTARGET_EXTRA_SPECS | ||
79 | |||
80 | #ifndef SUBTARGET_EXTRA_SPECS | ||
81 | @@ -2278,4 +2279,8 @@ | ||
82 | instruction. */ | ||
83 | #define MAX_LDM_STM_OPS 4 | ||
84 | |||
85 | +#define ASM_CPU_SPEC \ | ||
86 | + " %{mcpu=generic-*:-march=%*;" \ | ||
87 | + " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}" | ||
88 | + | ||
89 | #endif /* ! GCC_ARM_H */ | ||
90 | |||
91 | === modified file 'gcc/config/arm/elf.h' | ||
92 | --- old/gcc/config/arm/elf.h 2009-06-21 19:48:15 +0000 | ||
93 | +++ new/gcc/config/arm/elf.h 2011-10-19 16:46:51 +0000 | ||
94 | @@ -56,8 +56,7 @@ | ||
95 | #define ASM_SPEC "\ | ||
96 | %{mbig-endian:-EB} \ | ||
97 | %{mlittle-endian:-EL} \ | ||
98 | -%{mcpu=*:-mcpu=%*} \ | ||
99 | -%{march=*:-march=%*} \ | ||
100 | +%(asm_cpu_spec) \ | ||
101 | %{mapcs-*:-mapcs-%*} \ | ||
102 | %(subtarget_asm_float_spec) \ | ||
103 | %{mthumb-interwork:-mthumb-interwork} \ | ||
104 | |||
105 | === modified file 'gcc/config/arm/semi.h' | ||
106 | --- old/gcc/config/arm/semi.h 2007-08-02 09:49:31 +0000 | ||
107 | +++ new/gcc/config/arm/semi.h 2011-10-19 16:46:51 +0000 | ||
108 | @@ -65,8 +65,7 @@ | ||
109 | #define ASM_SPEC "\ | ||
110 | %{fpic|fpie: -k} %{fPIC|fPIE: -k} \ | ||
111 | %{mbig-endian:-EB} \ | ||
112 | -%{mcpu=*:-mcpu=%*} \ | ||
113 | -%{march=*:-march=%*} \ | ||
114 | +%(arm_cpu_spec) \ | ||
115 | %{mapcs-float:-mfloat} \ | ||
116 | %{msoft-float:-mfloat-abi=soft} %{mhard-float:-mfloat-abi=hard} \ | ||
117 | %{mfloat-abi=*} %{mfpu=*} \ | ||
118 | |||
119 | === modified file 'gcc/doc/invoke.texi' | ||
120 | --- old/gcc/doc/invoke.texi 2011-08-13 08:32:32 +0000 | ||
121 | +++ new/gcc/doc/invoke.texi 2011-10-19 16:46:51 +0000 | ||
122 | @@ -10215,6 +10215,10 @@ | ||
123 | @samp{cortex-m0}, | ||
124 | @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. | ||
125 | |||
126 | +@option{-mcpu=generic-@var{arch}} is also permissible, and is | ||
127 | +equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. | ||
128 | +See @option{-mtune} for more information. | ||
129 | + | ||
130 | @item -mtune=@var{name} | ||
131 | @opindex mtune | ||
132 | This option is very similar to the @option{-mcpu=} option, except that | ||
133 | @@ -10226,6 +10230,13 @@ | ||
134 | For some ARM implementations better performance can be obtained by using | ||
135 | this option. | ||
136 | |||
137 | +@option{-mtune=generic-@var{arch}} specifies that GCC should tune the | ||
138 | +performance for a blend of processors within architecture @var{arch}. | ||
139 | +The aim is to generate code that run well on the current most popular | ||
140 | +processors, balancing between optimizations that benefit some CPUs in the | ||
141 | +range, and avoiding performance pitfalls of other CPUs. The effects of | ||
142 | +this option may change in future GCC versions as CPU models come and go. | ||
143 | + | ||
144 | @item -march=@var{name} | ||
145 | @opindex march | ||
146 | This specifies the name of the target ARM architecture. GCC uses this | ||
147 | |||