diff options
Diffstat (limited to 'toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch')
-rw-r--r-- | toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch | 151 |
1 files changed, 0 insertions, 151 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch deleted file mode 100644 index d10cf34654..0000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch +++ /dev/null | |||
@@ -1,151 +0,0 @@ | |||
1 | 2010-09-02 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
2 | * config/arm/predicates.md (arm_sync_memory_operand): New. | ||
3 | * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate | ||
4 | to arm_sync_memory_operand and constraint to Q. | ||
5 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
6 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
7 | (arm_sync_lock_test_and_setsi): Likewise. | ||
8 | (arm_sync_lock_test_and_set<mode>): Likewise. | ||
9 | (arm_sync_new_<sync_optab>si): Likewise. | ||
10 | (arm_sync_new_nandsi): Likewise. | ||
11 | (arm_sync_new_<sync_optab><mode>): Likewise. | ||
12 | (arm_sync_new_nand<mode>): Likewise. | ||
13 | (arm_sync_old_<sync_optab>si): Likewise. | ||
14 | (arm_sync_old_nandsi): Likewise. | ||
15 | (arm_sync_old_<sync_optab><mode>): Likewise. | ||
16 | (arm_sync_old_nand<mode>): Likewise. | ||
17 | |||
18 | 2010-09-09 Andrew Stubbs <ams@codesourcery.com> | ||
19 | |||
20 | Backport from mainline: | ||
21 | |||
22 | 2010-08-18 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
23 | |||
24 | === modified file 'gcc/config/arm/predicates.md' | ||
25 | --- old/gcc/config/arm/predicates.md 2010-09-09 14:11:34 +0000 | ||
26 | +++ new/gcc/config/arm/predicates.md 2010-09-09 15:18:16 +0000 | ||
27 | @@ -573,6 +573,11 @@ | ||
28 | (and (match_test "TARGET_32BIT") | ||
29 | (match_operand 0 "arm_di_operand")))) | ||
30 | |||
31 | +;; True if the operand is memory reference suitable for a ldrex/strex. | ||
32 | +(define_predicate "arm_sync_memory_operand" | ||
33 | + (and (match_operand 0 "memory_operand") | ||
34 | + (match_code "reg" "0"))) | ||
35 | + | ||
36 | ;; Predicates for parallel expanders based on mode. | ||
37 | (define_special_predicate "vect_par_constant_high" | ||
38 | (match_code "parallel") | ||
39 | |||
40 | === modified file 'gcc/config/arm/sync.md' | ||
41 | --- old/gcc/config/arm/sync.md 2010-09-09 15:03:00 +0000 | ||
42 | +++ new/gcc/config/arm/sync.md 2010-09-09 15:18:16 +0000 | ||
43 | @@ -280,7 +280,7 @@ | ||
44 | (define_insn "arm_sync_compare_and_swapsi" | ||
45 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
46 | (unspec_volatile:SI | ||
47 | - [(match_operand:SI 1 "memory_operand" "+m") | ||
48 | + [(match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
49 | (match_operand:SI 2 "s_register_operand" "r") | ||
50 | (match_operand:SI 3 "s_register_operand" "r")] | ||
51 | VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
52 | @@ -307,7 +307,7 @@ | ||
53 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
54 | (zero_extend:SI | ||
55 | (unspec_volatile:NARROW | ||
56 | - [(match_operand:NARROW 1 "memory_operand" "+m") | ||
57 | + [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q") | ||
58 | (match_operand:SI 2 "s_register_operand" "r") | ||
59 | (match_operand:SI 3 "s_register_operand" "r")] | ||
60 | VUNSPEC_SYNC_COMPARE_AND_SWAP))) | ||
61 | @@ -332,7 +332,7 @@ | ||
62 | |||
63 | (define_insn "arm_sync_lock_test_and_setsi" | ||
64 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
65 | - (match_operand:SI 1 "memory_operand" "+m")) | ||
66 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q")) | ||
67 | (set (match_dup 1) | ||
68 | (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] | ||
69 | VUNSPEC_SYNC_LOCK)) | ||
70 | @@ -353,7 +353,7 @@ | ||
71 | |||
72 | (define_insn "arm_sync_lock_test_and_set<mode>" | ||
73 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
74 | - (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m"))) | ||
75 | + (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))) | ||
76 | (set (match_dup 1) | ||
77 | (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] | ||
78 | VUNSPEC_SYNC_LOCK)) | ||
79 | @@ -375,7 +375,7 @@ | ||
80 | (define_insn "arm_sync_new_<sync_optab>si" | ||
81 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
82 | (unspec_volatile:SI [(syncop:SI | ||
83 | - (match_operand:SI 1 "memory_operand" "+m") | ||
84 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
85 | (match_operand:SI 2 "s_register_operand" "r")) | ||
86 | ] | ||
87 | VUNSPEC_SYNC_NEW_OP)) | ||
88 | @@ -400,7 +400,7 @@ | ||
89 | (define_insn "arm_sync_new_nandsi" | ||
90 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
91 | (unspec_volatile:SI [(not:SI (and:SI | ||
92 | - (match_operand:SI 1 "memory_operand" "+m") | ||
93 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
94 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
95 | ] | ||
96 | VUNSPEC_SYNC_NEW_OP)) | ||
97 | @@ -426,7 +426,7 @@ | ||
98 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
99 | (unspec_volatile:SI [(syncop:SI | ||
100 | (zero_extend:SI | ||
101 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
102 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
103 | (match_operand:SI 2 "s_register_operand" "r")) | ||
104 | ] | ||
105 | VUNSPEC_SYNC_NEW_OP)) | ||
106 | @@ -454,7 +454,7 @@ | ||
107 | [(not:SI | ||
108 | (and:SI | ||
109 | (zero_extend:SI | ||
110 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
111 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
112 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
113 | ] VUNSPEC_SYNC_NEW_OP)) | ||
114 | (set (match_dup 1) | ||
115 | @@ -478,7 +478,7 @@ | ||
116 | (define_insn "arm_sync_old_<sync_optab>si" | ||
117 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
118 | (unspec_volatile:SI [(syncop:SI | ||
119 | - (match_operand:SI 1 "memory_operand" "+m") | ||
120 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
121 | (match_operand:SI 2 "s_register_operand" "r")) | ||
122 | ] | ||
123 | VUNSPEC_SYNC_OLD_OP)) | ||
124 | @@ -504,7 +504,7 @@ | ||
125 | (define_insn "arm_sync_old_nandsi" | ||
126 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
127 | (unspec_volatile:SI [(not:SI (and:SI | ||
128 | - (match_operand:SI 1 "memory_operand" "+m") | ||
129 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
130 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
131 | ] | ||
132 | VUNSPEC_SYNC_OLD_OP)) | ||
133 | @@ -531,7 +531,7 @@ | ||
134 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
135 | (unspec_volatile:SI [(syncop:SI | ||
136 | (zero_extend:SI | ||
137 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
138 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
139 | (match_operand:SI 2 "s_register_operand" "r")) | ||
140 | ] | ||
141 | VUNSPEC_SYNC_OLD_OP)) | ||
142 | @@ -558,7 +558,7 @@ | ||
143 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
144 | (unspec_volatile:SI [(not:SI (and:SI | ||
145 | (zero_extend:SI | ||
146 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
147 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
148 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
149 | ] | ||
150 | VUNSPEC_SYNC_OLD_OP)) | ||
151 | |||