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-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch132
1 files changed, 0 insertions, 132 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch
deleted file mode 100644
index 5d489aab69..0000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch
+++ /dev/null
@@ -1,132 +0,0 @@
1 Backport from FSF mainline:
2
3 Mark Shinwell <shinwell@codesourcery.com>
4 Julian Brown <julian@codesourcery.com>
5
6 gcc/
7 * config/arm/thumb2.md (thumb2_movsi_insn): Split ldr and str
8 alternatives according to use of high and low regs.
9 * config/arm/vfp.md (thumb2_movsi_vfp): Likewise.
10 * config/arm/arm.h (CONDITIONAL_REGISTER_USAGE): Use high regs when
11 optimizing for size on Thumb-2.
12
132010-07-26 Julian Brown <julian@codesourcery.com>
14
15 Merge from Sourcery G++ 4.4:
16
17 http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html
18
19=== modified file 'gcc/config/arm/arm.h'
20--- old/gcc/config/arm/arm.h 2010-08-05 15:28:47 +0000
21+++ new/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000
22@@ -783,12 +783,11 @@
23 fixed_regs[regno] = call_used_regs[regno] = 1; \
24 } \
25 \
26- if (TARGET_THUMB && optimize_size) \
27- { \
28- /* When optimizing for size, it's better not to use \
29- the HI regs, because of the overhead of stacking \
30- them. */ \
31- /* ??? Is this still true for thumb2? */ \
32+ if (TARGET_THUMB1 && optimize_size) \
33+ { \
34+ /* When optimizing for size on Thumb-1, it's better not \
35+ to use the HI regs, because of the overhead of \
36+ stacking them. */ \
37 for (regno = FIRST_HI_REGNUM; \
38 regno <= LAST_HI_REGNUM; ++regno) \
39 fixed_regs[regno] = call_used_regs[regno] = 1; \
40
41=== modified file 'gcc/config/arm/thumb2.md'
42--- old/gcc/config/arm/thumb2.md 2010-04-02 07:32:00 +0000
43+++ new/gcc/config/arm/thumb2.md 2010-08-05 16:34:46 +0000
44@@ -223,9 +223,14 @@
45 (set_attr "neg_pool_range" "*,*,*,0,*")]
46 )
47
48+;; We have two alternatives here for memory loads (and similarly for stores)
49+;; to reflect the fact that the permissible constant pool ranges differ
50+;; between ldr instructions taking low regs and ldr instructions taking high
51+;; regs. The high register alternatives are not taken into account when
52+;; choosing register preferences in order to reflect their expense.
53 (define_insn "*thumb2_movsi_insn"
54- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
55- (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,rk"))]
56+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l, *hk,m,*m")
57+ (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))]
58 "TARGET_THUMB2 && ! TARGET_IWMMXT
59 && !(TARGET_HARD_FLOAT && TARGET_VFP)
60 && ( register_operand (operands[0], SImode)
61@@ -236,11 +241,13 @@
62 mvn%?\\t%0, #%B1
63 movw%?\\t%0, %1
64 ldr%?\\t%0, %1
65+ ldr%?\\t%0, %1
66+ str%?\\t%1, %0
67 str%?\\t%1, %0"
68- [(set_attr "type" "*,*,*,*,load1,store1")
69+ [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
70 (set_attr "predicable" "yes")
71- (set_attr "pool_range" "*,*,*,*,4096,*")
72- (set_attr "neg_pool_range" "*,*,*,*,0,*")]
73+ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
74+ (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
75 )
76
77 (define_insn "tls_load_dot_plus_four"
78
79=== modified file 'gcc/config/arm/vfp.md'
80--- old/gcc/config/arm/vfp.md 2010-07-30 14:17:05 +0000
81+++ new/gcc/config/arm/vfp.md 2010-08-05 16:34:46 +0000
82@@ -86,9 +86,11 @@
83 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
84 )
85
86+;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
87+;; high/low register alternatives for loads and stores here.
88 (define_insn "*thumb2_movsi_vfp"
89- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
90- (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
91+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m,*t,r, *t,*t, *Uv")
92+ (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk,r,*t,*t,*Uvi,*t"))]
93 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
94 && ( s_register_operand (operands[0], SImode)
95 || s_register_operand (operands[1], SImode))"
96@@ -102,25 +104,27 @@
97 case 3:
98 return \"movw%?\\t%0, %1\";
99 case 4:
100+ case 5:
101 return \"ldr%?\\t%0, %1\";
102- case 5:
103+ case 6:
104+ case 7:
105 return \"str%?\\t%1, %0\";
106- case 6:
107+ case 8:
108 return \"fmsr%?\\t%0, %1\\t%@ int\";
109- case 7:
110+ case 9:
111 return \"fmrs%?\\t%0, %1\\t%@ int\";
112- case 8:
113+ case 10:
114 return \"fcpys%?\\t%0, %1\\t%@ int\";
115- case 9: case 10:
116+ case 11: case 12:
117 return output_move_vfp (operands);
118 default:
119 gcc_unreachable ();
120 }
121 "
122 [(set_attr "predicable" "yes")
123- (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
124- (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
125- (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")]
126+ (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
127+ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
128+ (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
129 )
130
131
132
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