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-rw-r--r--recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch170
1 files changed, 170 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch
new file mode 100644
index 0000000000..4807195158
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch
@@ -0,0 +1,170 @@
1 Backport from FSF mainline:
2
3 Julian Brown <julian@codesourcery.com>
4 Mark Mitchell <mark@codesourcery.com>
5
6 gcc/
7 * config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid
8 sibling calls for Thumb-1.
9 * config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2.
10 * config/arm/arm.md (*call_symbol, *call_value_symbol): Use for
11 Thumb-2.
12 (*call_insn, *call_value_insn): Don't use for Thumb-2.
13 (sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use
14 for Thumb-2.
15 (return): New expander.
16 (*arm_return): New name for ARM return insn.
17 * config/arm/thumb2.md (*thumb2_return): New insn pattern.
18
192010-07-26 Julian Brown <julian@codesourcery.com>
20
21 Merge from Sourcery G++ 4.4:
22
23 2010-02-04 Daniel Jacobowitz <dan@codesourcery.com>
24
25=== modified file 'gcc/config/arm/arm.c'
26--- old/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000
27+++ new/gcc/config/arm/arm.c 2010-08-13 10:30:35 +0000
28@@ -4886,8 +4886,8 @@
29 return false;
30
31 /* Never tailcall something for which we have no decl, or if we
32- are in Thumb mode. */
33- if (decl == NULL || TARGET_THUMB)
34+ are generating code for Thumb-1. */
35+ if (decl == NULL || TARGET_THUMB1)
36 return false;
37
38 /* The PIC register is live on entry to VxWorks PLT entries, so we
39
40=== modified file 'gcc/config/arm/arm.h'
41--- old/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000
42+++ new/gcc/config/arm/arm.h 2010-08-13 10:30:35 +0000
43@@ -1833,11 +1833,8 @@
44
45 /* Determine if the epilogue should be output as RTL.
46 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
47-/* This is disabled for Thumb-2 because it will confuse the
48- conditional insn counter.
49- Do not use a return insn if we're avoiding ldm/stm instructions. */
50 #define USE_RETURN_INSN(ISCOND) \
51- ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
52+ ((TARGET_32BIT && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
53
54 /* Definitions for register eliminations.
55
56
57=== modified file 'gcc/config/arm/arm.md'
58--- old/gcc/config/arm/arm.md 2010-08-12 16:47:21 +0000
59+++ new/gcc/config/arm/arm.md 2010-08-13 10:30:35 +0000
60@@ -8798,7 +8798,7 @@
61 (match_operand 1 "" ""))
62 (use (match_operand 2 "" ""))
63 (clobber (reg:SI LR_REGNUM))]
64- "TARGET_ARM
65+ "TARGET_32BIT
66 && (GET_CODE (operands[0]) == SYMBOL_REF)
67 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
68 "*
69@@ -8814,7 +8814,7 @@
70 (match_operand:SI 2 "" "")))
71 (use (match_operand 3 "" ""))
72 (clobber (reg:SI LR_REGNUM))]
73- "TARGET_ARM
74+ "TARGET_32BIT
75 && (GET_CODE (operands[1]) == SYMBOL_REF)
76 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
77 "*
78@@ -8829,7 +8829,7 @@
79 (match_operand:SI 1 "" ""))
80 (use (match_operand 2 "" ""))
81 (clobber (reg:SI LR_REGNUM))]
82- "TARGET_THUMB
83+ "TARGET_THUMB1
84 && GET_CODE (operands[0]) == SYMBOL_REF
85 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
86 "bl\\t%a0"
87@@ -8843,7 +8843,7 @@
88 (match_operand 2 "" "")))
89 (use (match_operand 3 "" ""))
90 (clobber (reg:SI LR_REGNUM))]
91- "TARGET_THUMB
92+ "TARGET_THUMB1
93 && GET_CODE (operands[1]) == SYMBOL_REF
94 && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
95 "bl\\t%a1"
96@@ -8857,7 +8857,7 @@
97 (match_operand 1 "general_operand" ""))
98 (return)
99 (use (match_operand 2 "" ""))])]
100- "TARGET_ARM"
101+ "TARGET_32BIT"
102 "
103 {
104 if (operands[2] == NULL_RTX)
105@@ -8871,7 +8871,7 @@
106 (match_operand 2 "general_operand" "")))
107 (return)
108 (use (match_operand 3 "" ""))])]
109- "TARGET_ARM"
110+ "TARGET_32BIT"
111 "
112 {
113 if (operands[3] == NULL_RTX)
114@@ -8884,7 +8884,7 @@
115 (match_operand 1 "" ""))
116 (return)
117 (use (match_operand 2 "" ""))]
118- "TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF"
119+ "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF"
120 "*
121 return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\";
122 "
123@@ -8897,15 +8897,20 @@
124 (match_operand 2 "" "")))
125 (return)
126 (use (match_operand 3 "" ""))]
127- "TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF"
128+ "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF"
129 "*
130 return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\";
131 "
132 [(set_attr "type" "call")]
133 )
134
135+(define_expand "return"
136+ [(return)]
137+ "TARGET_32BIT && USE_RETURN_INSN (FALSE)"
138+ "")
139+
140 ;; Often the return insn will be the same as loading from memory, so set attr
141-(define_insn "return"
142+(define_insn "*arm_return"
143 [(return)]
144 "TARGET_ARM && USE_RETURN_INSN (FALSE)"
145 "*
146
147=== modified file 'gcc/config/arm/thumb2.md'
148--- old/gcc/config/arm/thumb2.md 2010-08-12 16:47:21 +0000
149+++ new/gcc/config/arm/thumb2.md 2010-08-13 10:30:35 +0000
150@@ -1054,6 +1054,19 @@
151 (set_attr "length" "20")]
152 )
153
154+;; Note: this is not predicable, to avoid issues with linker-generated
155+;; interworking stubs.
156+(define_insn "*thumb2_return"
157+ [(return)]
158+ "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
159+ "*
160+ {
161+ return output_return_instruction (const_true_rtx, TRUE, FALSE);
162+ }"
163+ [(set_attr "type" "load1")
164+ (set_attr "length" "12")]
165+)
166+
167 (define_insn_and_split "thumb2_eh_return"
168 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
169 VUNSPEC_EH_RETURN)
170
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