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diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch
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index 000000000..2e8e12d2a
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+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch
@@ -0,0 +1,209 @@
1 2011-07-14 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 * config/arm/arm.h (ARM_LEGITIMIZE_RELOAD_ADDRESS): Apply the
5 arm_legitimize_reload_address changes marked [*] below.
6
7 Backport from mainline:
8
9 2011-04-20 Chung-Lin Tang <cltang@codesourcery.com>
10
11 [*] config/arm/arm.c (arm_legitimize_reload_address): For NEON
12 quad-word modes, reduce to 9-bit index range when above 1016
13 limit.
14
15 2011-04-11 Chung-Lin Tang <cltang@codesourcery.com>
16 Richard Earnshaw <rearnsha@arm.com>
17
18 PR target/48250
19 [*] config/arm/arm.c (arm_legitimize_reload_address): Update cases
20 to use sign-magnitude offsets. Reject unsupported unaligned
21 cases. Add detailed description in comments.
22 * config/arm/arm.md (reload_outdf): Disable for ARM mode; change
23 condition from TARGET_32BIT to TARGET_ARM.
24
25=== modified file 'gcc/config/arm/arm.h'
26--- old/gcc/config/arm/arm.h 2011-04-20 10:07:36 +0000
27+++ new/gcc/config/arm/arm.h 2011-07-12 16:35:20 +0000
28@@ -1399,6 +1399,11 @@
29 ? GENERAL_REGS : NO_REGS) \
30 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
31
32+#define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
33+ (((VAL) & ((1 << (N)) - 1)) \
34+ ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
35+ : 0)
36+
37 /* Try a machine-dependent way of reloading an illegitimate address
38 operand. If we find one, push the reload and jump to WIN. This
39 macro is used in only one place: `find_reloads_address' in reload.c.
40@@ -1418,26 +1423,135 @@
41 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
42 HOST_WIDE_INT low, high; \
43 \
44- if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
45- low = ((val & 0xf) ^ 0x8) - 0x8; \
46- else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
47- /* Need to be careful, -256 is not a valid offset. */ \
48- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
49- else if (TARGET_REALLY_IWMMXT && MODE == SImode) \
50- /* Need to be careful, -1024 is not a valid offset. */ \
51- low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
52- else if (MODE == SImode \
53- || (MODE == SFmode && TARGET_SOFT_FLOAT) \
54- || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
55- /* Need to be careful, -4096 is not a valid offset. */ \
56- low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
57- else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
58- /* Need to be careful, -256 is not a valid offset. */ \
59- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
60- else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
61- && TARGET_HARD_FLOAT && TARGET_FPA) \
62- /* Need to be careful, -1024 is not a valid offset. */ \
63- low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
64+ /* Detect coprocessor load/stores. */ \
65+ bool coproc_p = ((TARGET_HARD_FLOAT \
66+ && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK) \
67+ && (mode == SFmode || mode == DFmode \
68+ || (mode == DImode && TARGET_MAVERICK))) \
69+ || (TARGET_REALLY_IWMMXT \
70+ && VALID_IWMMXT_REG_MODE (mode)) \
71+ || (TARGET_NEON \
72+ && (VALID_NEON_DREG_MODE (mode) \
73+ || VALID_NEON_QREG_MODE (mode)))); \
74+ \
75+ /* For some conditions, bail out when lower two bits are \
76+ unaligned. */ \
77+ if ((val & 0x3) != 0 \
78+ /* Coprocessor load/store indexes are 8-bits + '00' \
79+ appended. */ \
80+ && (coproc_p \
81+ /* For DI, and DF under soft-float: */ \
82+ || ((mode == DImode || mode == DFmode) \
83+ /* Without ldrd, we use stm/ldm, which does not \
84+ fair well with unaligned bits. */ \
85+ && (! TARGET_LDRD \
86+ /* Thumb-2 ldrd/strd is [-1020,+1020] in \
87+ steps of 4. */ \
88+ || TARGET_THUMB2)))) \
89+ break; \
90+ \
91+ /* When breaking down a [reg+index] reload address into \
92+ [(reg+high)+low], of which the (reg+high) gets turned into \
93+ a reload add insn, we try to decompose the index into \
94+ high/low values that can often also lead to better reload \
95+ CSE. For example: \
96+ ldr r0, [r2, #4100] // Offset too large \
97+ ldr r1, [r2, #4104] // Offset too large \
98+ \
99+ is best reloaded as: \
100+ add t1, r2, #4096 \
101+ ldr r0, [t1, #4] \
102+ add t2, r2, #4096 \
103+ ldr r1, [t2, #8] \
104+ \
105+ which post-reload CSE can simplify in most cases to eliminate \
106+ the second add instruction: \
107+ add t1, r2, #4096 \
108+ ldr r0, [t1, #4] \
109+ ldr r1, [t1, #8] \
110+ \
111+ The idea here is that we want to split out the bits of the \
112+ constant as a mask, rather than as subtracting the maximum \
113+ offset that the respective type of load/store used can \
114+ handle. \
115+ \
116+ When encountering negative offsets, we can still utilize it \
117+ even if the overall offset is positive; sometimes this may \
118+ lead to an immediate that can be constructed with fewer \
119+ instructions. For example: \
120+ ldr r0, [r2, #0x3FFFFC] \
121+ \
122+ This is best reloaded as: \
123+ add t1, r2, #0x400000 \
124+ ldr r0, [t1, #-4] \
125+ \
126+ The trick for spotting this for a load insn with N bits of \
127+ offset (i.e. bits N-1:0) is to look at bit N; if it is set, \
128+ then chose a negative offset that is going to make bit N and \
129+ all the bits below it become zero in the remainder part. \
130+ \
131+ The SIGN_MAG_LOW_ADDR_BITS macro below implements this, \
132+ with respect to sign-magnitude addressing (i.e. separate \
133+ +- bit, or 1's complement), used in most cases of ARM \
134+ load/store instructions. */ \
135+ \
136+ if (coproc_p) \
137+ { \
138+ low = SIGN_MAG_LOW_ADDR_BITS (val, 10); \
139+ \
140+ /* NEON quad-word load/stores are made of two double-word \
141+ accesses, so the valid index range is reduced by 8. \
142+ Treat as 9-bit range if we go over it. */ \
143+ if (TARGET_NEON && VALID_NEON_QREG_MODE (mode) && low >= 1016) \
144+ low = SIGN_MAG_LOW_ADDR_BITS (val, 9); \
145+ } \
146+ else if (GET_MODE_SIZE (mode) == 8) \
147+ { \
148+ if (TARGET_LDRD) \
149+ low = (TARGET_THUMB2 \
150+ ? SIGN_MAG_LOW_ADDR_BITS (val, 10) \
151+ : SIGN_MAG_LOW_ADDR_BITS (val, 8)); \
152+ else \
153+ /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib) \
154+ to access doublewords. The supported load/store offsets \
155+ are -8, -4, and 4, which we try to produce here. */ \
156+ low = ((val & 0xf) ^ 0x8) - 0x8; \
157+ } \
158+ else if (GET_MODE_SIZE (mode) < 8) \
159+ { \
160+ /* NEON element load/stores do not have an offset. */ \
161+ if (TARGET_NEON_FP16 && mode == HFmode) \
162+ break; \
163+ \
164+ if (TARGET_THUMB2) \
165+ { \
166+ /* Thumb-2 has an asymmetrical index range of (-256,4096). \
167+ Try the wider 12-bit range first, and re-try if the \
168+ result is out of range. */ \
169+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12); \
170+ if (low < -255) \
171+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8); \
172+ } \
173+ else \
174+ { \
175+ if (mode == HImode || mode == HFmode) \
176+ { \
177+ if (arm_arch4) \
178+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8); \
179+ else \
180+ { \
181+ /* The storehi/movhi_bytes fallbacks can use \
182+ only [-4094,+4094] of the full ldrb/strb \
183+ index range. */ \
184+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12); \
185+ if (low == 4095 || low == -4095) \
186+ break; \
187+ } \
188+ } \
189+ else \
190+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12); \
191+ } \
192+ } \
193 else \
194 break; \
195 \
196
197=== modified file 'gcc/config/arm/arm.md'
198--- old/gcc/config/arm/arm.md 2011-04-28 16:13:24 +0000
199+++ new/gcc/config/arm/arm.md 2011-07-12 16:35:20 +0000
200@@ -6167,7 +6167,7 @@
201 [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
202 (match_operand:DF 1 "s_register_operand" "r")
203 (match_operand:SI 2 "s_register_operand" "=&r")]
204- "TARGET_32BIT"
205+ "TARGET_THUMB2"
206 "
207 {
208 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
209
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