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authorKhem Raj <raj.khem@gmail.com>2012-05-15 14:45:57 -0700
committerKhem Raj <raj.khem@gmail.com>2012-05-15 14:48:59 -0700
commit6291c6fd1243d722e144466921064d47fb50428b (patch)
treea60d1cb9952db6786fcb60ce1accc596f5fba2ef /toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch
parent93898b626e2e169dea112c724ff9e7ed1b0e14eb (diff)
downloadmeta-openembedded-6291c6fd1243d722e144466921064d47fb50428b.tar.gz
gcc-4.5: Remove
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Diffstat (limited to 'toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch')
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch3565
1 files changed, 0 insertions, 3565 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch
deleted file mode 100644
index e795d54e0..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch
+++ /dev/null
@@ -1,3565 +0,0 @@
12010-09-16 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2010-09-01 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
6
7 * config/arm/neon-schedgen.ml (core): New type.
8 (allCores): List of supported cores.
9 (availability_table): Add supported cores.
10 (collate_bypasses): Accept core as a parameter.
11 (worst_case_latencies_and_bypasses): Accept core as a
12 parameter.
13 (emit_insn_reservations): Accept core as a parameter.
14 Use tuneStr and coreStr to get tune attribute and prefix
15 for functional units.
16 (emit_bypasses): Accept core name and use it.
17 (calculate_per_core_availability_table): New.
18 (filter_core): New.
19 (calculate_core_availability_table): New.
20 (main): Use calculate_core_availablity_table.
21 * config/arm/cortex-a8-neon.md: Update copyright year.
22 Regenerated from ml file and merged in.
23 (neon_mrrc, neon_mrc): Rename to cortex_a8_neon_mrrc and
24 cortex_a8_neon_mrc.
25
26 2010-09-10 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
27
28 * config/arm/neon-schedgen.ml (allCores): Add support for
29 Cortex-A9.
30 * config/arm/cortex-a9-neon.md: New and partially generated.
31 * config/arm/cortex-a9.md (cortex_a9_dp): Adjust for Neon.
32
33 2010-09-15 Chung-Lin Tang <cltang@codesourcery.com>
34
35 Issue #9441
36
37=== modified file 'gcc/config/arm/cortex-a8-neon.md'
38--- old/gcc/config/arm/cortex-a8-neon.md 2009-02-20 15:20:38 +0000
39+++ new/gcc/config/arm/cortex-a8-neon.md 2010-09-16 09:47:44 +0000
40@@ -182,12 +182,12 @@
41
42 ;; NEON -> core transfers.
43
44-(define_insn_reservation "neon_mrc" 20
45+(define_insn_reservation "cortex_a8_neon_mrc" 20
46 (and (eq_attr "tune" "cortexa8")
47 (eq_attr "neon_type" "neon_mrc"))
48 "cortex_a8_neon_ls")
49
50-(define_insn_reservation "neon_mrrc" 21
51+(define_insn_reservation "cortex_a8_neon_mrrc" 21
52 (and (eq_attr "tune" "cortexa8")
53 (eq_attr "neon_type" "neon_mrrc"))
54 "cortex_a8_neon_ls_2")
55@@ -196,48 +196,48 @@
56
57 ;; Instructions using this reservation read their source operands at N2, and
58 ;; produce a result at N3.
59-(define_insn_reservation "neon_int_1" 3
60+(define_insn_reservation "cortex_a8_neon_int_1" 3
61 (and (eq_attr "tune" "cortexa8")
62 (eq_attr "neon_type" "neon_int_1"))
63 "cortex_a8_neon_dp")
64
65 ;; Instructions using this reservation read their (D|Q)m operands at N1,
66 ;; their (D|Q)n operands at N2, and produce a result at N3.
67-(define_insn_reservation "neon_int_2" 3
68+(define_insn_reservation "cortex_a8_neon_int_2" 3
69 (and (eq_attr "tune" "cortexa8")
70 (eq_attr "neon_type" "neon_int_2"))
71 "cortex_a8_neon_dp")
72
73 ;; Instructions using this reservation read their source operands at N1, and
74 ;; produce a result at N3.
75-(define_insn_reservation "neon_int_3" 3
76+(define_insn_reservation "cortex_a8_neon_int_3" 3
77 (and (eq_attr "tune" "cortexa8")
78 (eq_attr "neon_type" "neon_int_3"))
79 "cortex_a8_neon_dp")
80
81 ;; Instructions using this reservation read their source operands at N2, and
82 ;; produce a result at N4.
83-(define_insn_reservation "neon_int_4" 4
84+(define_insn_reservation "cortex_a8_neon_int_4" 4
85 (and (eq_attr "tune" "cortexa8")
86 (eq_attr "neon_type" "neon_int_4"))
87 "cortex_a8_neon_dp")
88
89 ;; Instructions using this reservation read their (D|Q)m operands at N1,
90 ;; their (D|Q)n operands at N2, and produce a result at N4.
91-(define_insn_reservation "neon_int_5" 4
92+(define_insn_reservation "cortex_a8_neon_int_5" 4
93 (and (eq_attr "tune" "cortexa8")
94 (eq_attr "neon_type" "neon_int_5"))
95 "cortex_a8_neon_dp")
96
97 ;; Instructions using this reservation read their source operands at N1, and
98 ;; produce a result at N4.
99-(define_insn_reservation "neon_vqneg_vqabs" 4
100+(define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4
101 (and (eq_attr "tune" "cortexa8")
102 (eq_attr "neon_type" "neon_vqneg_vqabs"))
103 "cortex_a8_neon_dp")
104
105 ;; Instructions using this reservation produce a result at N3.
106-(define_insn_reservation "neon_vmov" 3
107+(define_insn_reservation "cortex_a8_neon_vmov" 3
108 (and (eq_attr "tune" "cortexa8")
109 (eq_attr "neon_type" "neon_vmov"))
110 "cortex_a8_neon_dp")
111@@ -245,7 +245,7 @@
112 ;; Instructions using this reservation read their (D|Q)n operands at N2,
113 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
114 ;; produce a result at N6.
115-(define_insn_reservation "neon_vaba" 6
116+(define_insn_reservation "cortex_a8_neon_vaba" 6
117 (and (eq_attr "tune" "cortexa8")
118 (eq_attr "neon_type" "neon_vaba"))
119 "cortex_a8_neon_dp")
120@@ -253,35 +253,35 @@
121 ;; Instructions using this reservation read their (D|Q)n operands at N2,
122 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
123 ;; produce a result at N6 on cycle 2.
124-(define_insn_reservation "neon_vaba_qqq" 7
125+(define_insn_reservation "cortex_a8_neon_vaba_qqq" 7
126 (and (eq_attr "tune" "cortexa8")
127 (eq_attr "neon_type" "neon_vaba_qqq"))
128 "cortex_a8_neon_dp_2")
129
130 ;; Instructions using this reservation read their (D|Q)m operands at N1,
131 ;; their (D|Q)d operands at N3, and produce a result at N6.
132-(define_insn_reservation "neon_vsma" 6
133+(define_insn_reservation "cortex_a8_neon_vsma" 6
134 (and (eq_attr "tune" "cortexa8")
135 (eq_attr "neon_type" "neon_vsma"))
136 "cortex_a8_neon_dp")
137
138 ;; Instructions using this reservation read their source operands at N2, and
139 ;; produce a result at N6.
140-(define_insn_reservation "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
141+(define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
142 (and (eq_attr "tune" "cortexa8")
143 (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
144 "cortex_a8_neon_dp")
145
146 ;; Instructions using this reservation read their source operands at N2, and
147 ;; produce a result at N6 on cycle 2.
148-(define_insn_reservation "neon_mul_qqq_8_16_32_ddd_32" 7
149+(define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7
150 (and (eq_attr "tune" "cortexa8")
151 (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
152 "cortex_a8_neon_dp_2")
153
154 ;; Instructions using this reservation read their (D|Q)n operands at N2,
155 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
156-(define_insn_reservation "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
157+(define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
158 (and (eq_attr "tune" "cortexa8")
159 (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
160 "cortex_a8_neon_dp_2")
161@@ -289,7 +289,7 @@
162 ;; Instructions using this reservation read their (D|Q)n operands at N2,
163 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
164 ;; produce a result at N6.
165-(define_insn_reservation "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
166+(define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
167 (and (eq_attr "tune" "cortexa8")
168 (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
169 "cortex_a8_neon_dp")
170@@ -297,7 +297,7 @@
171 ;; Instructions using this reservation read their (D|Q)n operands at N2,
172 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
173 ;; produce a result at N6 on cycle 2.
174-(define_insn_reservation "neon_mla_qqq_8_16" 7
175+(define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7
176 (and (eq_attr "tune" "cortexa8")
177 (eq_attr "neon_type" "neon_mla_qqq_8_16"))
178 "cortex_a8_neon_dp_2")
179@@ -305,7 +305,7 @@
180 ;; Instructions using this reservation read their (D|Q)n operands at N2,
181 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
182 ;; produce a result at N6 on cycle 2.
183-(define_insn_reservation "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
184+(define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
185 (and (eq_attr "tune" "cortexa8")
186 (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
187 "cortex_a8_neon_dp_2")
188@@ -313,21 +313,21 @@
189 ;; Instructions using this reservation read their (D|Q)n operands at N2,
190 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
191 ;; produce a result at N6 on cycle 4.
192-(define_insn_reservation "neon_mla_qqq_32_qqd_32_scalar" 9
193+(define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9
194 (and (eq_attr "tune" "cortexa8")
195 (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar"))
196 "cortex_a8_neon_dp_4")
197
198 ;; Instructions using this reservation read their (D|Q)n operands at N2,
199 ;; their (D|Q)m operands at N1, and produce a result at N6.
200-(define_insn_reservation "neon_mul_ddd_16_scalar_32_16_long_scalar" 6
201+(define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6
202 (and (eq_attr "tune" "cortexa8")
203 (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
204 "cortex_a8_neon_dp")
205
206 ;; Instructions using this reservation read their (D|Q)n operands at N2,
207 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4.
208-(define_insn_reservation "neon_mul_qqd_32_scalar" 9
209+(define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9
210 (and (eq_attr "tune" "cortexa8")
211 (eq_attr "neon_type" "neon_mul_qqd_32_scalar"))
212 "cortex_a8_neon_dp_4")
213@@ -335,84 +335,84 @@
214 ;; Instructions using this reservation read their (D|Q)n operands at N2,
215 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
216 ;; produce a result at N6.
217-(define_insn_reservation "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
218+(define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
219 (and (eq_attr "tune" "cortexa8")
220 (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
221 "cortex_a8_neon_dp")
222
223 ;; Instructions using this reservation read their source operands at N1, and
224 ;; produce a result at N3.
225-(define_insn_reservation "neon_shift_1" 3
226+(define_insn_reservation "cortex_a8_neon_shift_1" 3
227 (and (eq_attr "tune" "cortexa8")
228 (eq_attr "neon_type" "neon_shift_1"))
229 "cortex_a8_neon_dp")
230
231 ;; Instructions using this reservation read their source operands at N1, and
232 ;; produce a result at N4.
233-(define_insn_reservation "neon_shift_2" 4
234+(define_insn_reservation "cortex_a8_neon_shift_2" 4
235 (and (eq_attr "tune" "cortexa8")
236 (eq_attr "neon_type" "neon_shift_2"))
237 "cortex_a8_neon_dp")
238
239 ;; Instructions using this reservation read their source operands at N1, and
240 ;; produce a result at N3 on cycle 2.
241-(define_insn_reservation "neon_shift_3" 4
242+(define_insn_reservation "cortex_a8_neon_shift_3" 4
243 (and (eq_attr "tune" "cortexa8")
244 (eq_attr "neon_type" "neon_shift_3"))
245 "cortex_a8_neon_dp_2")
246
247 ;; Instructions using this reservation read their source operands at N1, and
248 ;; produce a result at N1.
249-(define_insn_reservation "neon_vshl_ddd" 1
250+(define_insn_reservation "cortex_a8_neon_vshl_ddd" 1
251 (and (eq_attr "tune" "cortexa8")
252 (eq_attr "neon_type" "neon_vshl_ddd"))
253 "cortex_a8_neon_dp")
254
255 ;; Instructions using this reservation read their source operands at N1, and
256 ;; produce a result at N4 on cycle 2.
257-(define_insn_reservation "neon_vqshl_vrshl_vqrshl_qqq" 5
258+(define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5
259 (and (eq_attr "tune" "cortexa8")
260 (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq"))
261 "cortex_a8_neon_dp_2")
262
263 ;; Instructions using this reservation read their (D|Q)m operands at N1,
264 ;; their (D|Q)d operands at N3, and produce a result at N6.
265-(define_insn_reservation "neon_vsra_vrsra" 6
266+(define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6
267 (and (eq_attr "tune" "cortexa8")
268 (eq_attr "neon_type" "neon_vsra_vrsra"))
269 "cortex_a8_neon_dp")
270
271 ;; Instructions using this reservation read their source operands at N2, and
272 ;; produce a result at N5.
273-(define_insn_reservation "neon_fp_vadd_ddd_vabs_dd" 5
274+(define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5
275 (and (eq_attr "tune" "cortexa8")
276 (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd"))
277 "cortex_a8_neon_fadd")
278
279 ;; Instructions using this reservation read their source operands at N2, and
280 ;; produce a result at N5 on cycle 2.
281-(define_insn_reservation "neon_fp_vadd_qqq_vabs_qq" 6
282+(define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6
283 (and (eq_attr "tune" "cortexa8")
284 (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq"))
285 "cortex_a8_neon_fadd_2")
286
287 ;; Instructions using this reservation read their source operands at N1, and
288 ;; produce a result at N5.
289-(define_insn_reservation "neon_fp_vsum" 5
290+(define_insn_reservation "cortex_a8_neon_fp_vsum" 5
291 (and (eq_attr "tune" "cortexa8")
292 (eq_attr "neon_type" "neon_fp_vsum"))
293 "cortex_a8_neon_fadd")
294
295 ;; Instructions using this reservation read their (D|Q)n operands at N2,
296 ;; their (D|Q)m operands at N1, and produce a result at N5.
297-(define_insn_reservation "neon_fp_vmul_ddd" 5
298+(define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5
299 (and (eq_attr "tune" "cortexa8")
300 (eq_attr "neon_type" "neon_fp_vmul_ddd"))
301 "cortex_a8_neon_dp")
302
303 ;; Instructions using this reservation read their (D|Q)n operands at N2,
304 ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2.
305-(define_insn_reservation "neon_fp_vmul_qqd" 6
306+(define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6
307 (and (eq_attr "tune" "cortexa8")
308 (eq_attr "neon_type" "neon_fp_vmul_qqd"))
309 "cortex_a8_neon_dp_2")
310@@ -420,7 +420,7 @@
311 ;; Instructions using this reservation read their (D|Q)n operands at N2,
312 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
313 ;; produce a result at N9.
314-(define_insn_reservation "neon_fp_vmla_ddd" 9
315+(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9
316 (and (eq_attr "tune" "cortexa8")
317 (eq_attr "neon_type" "neon_fp_vmla_ddd"))
318 "cortex_a8_neon_fmul_then_fadd")
319@@ -428,7 +428,7 @@
320 ;; Instructions using this reservation read their (D|Q)n operands at N2,
321 ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
322 ;; produce a result at N9 on cycle 2.
323-(define_insn_reservation "neon_fp_vmla_qqq" 10
324+(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10
325 (and (eq_attr "tune" "cortexa8")
326 (eq_attr "neon_type" "neon_fp_vmla_qqq"))
327 "cortex_a8_neon_fmul_then_fadd_2")
328@@ -436,7 +436,7 @@
329 ;; Instructions using this reservation read their (D|Q)n operands at N2,
330 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
331 ;; produce a result at N9.
332-(define_insn_reservation "neon_fp_vmla_ddd_scalar" 9
333+(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9
334 (and (eq_attr "tune" "cortexa8")
335 (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar"))
336 "cortex_a8_neon_fmul_then_fadd")
337@@ -444,869 +444,869 @@
338 ;; Instructions using this reservation read their (D|Q)n operands at N2,
339 ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
340 ;; produce a result at N9 on cycle 2.
341-(define_insn_reservation "neon_fp_vmla_qqq_scalar" 10
342+(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10
343 (and (eq_attr "tune" "cortexa8")
344 (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar"))
345 "cortex_a8_neon_fmul_then_fadd_2")
346
347 ;; Instructions using this reservation read their source operands at N2, and
348 ;; produce a result at N9.
349-(define_insn_reservation "neon_fp_vrecps_vrsqrts_ddd" 9
350+(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9
351 (and (eq_attr "tune" "cortexa8")
352 (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd"))
353 "cortex_a8_neon_fmul_then_fadd")
354
355 ;; Instructions using this reservation read their source operands at N2, and
356 ;; produce a result at N9 on cycle 2.
357-(define_insn_reservation "neon_fp_vrecps_vrsqrts_qqq" 10
358+(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10
359 (and (eq_attr "tune" "cortexa8")
360 (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq"))
361 "cortex_a8_neon_fmul_then_fadd_2")
362
363 ;; Instructions using this reservation read their source operands at N1, and
364 ;; produce a result at N2.
365-(define_insn_reservation "neon_bp_simple" 2
366+(define_insn_reservation "cortex_a8_neon_bp_simple" 2
367 (and (eq_attr "tune" "cortexa8")
368 (eq_attr "neon_type" "neon_bp_simple"))
369 "cortex_a8_neon_perm")
370
371 ;; Instructions using this reservation read their source operands at N1, and
372 ;; produce a result at N2 on cycle 2.
373-(define_insn_reservation "neon_bp_2cycle" 3
374+(define_insn_reservation "cortex_a8_neon_bp_2cycle" 3
375 (and (eq_attr "tune" "cortexa8")
376 (eq_attr "neon_type" "neon_bp_2cycle"))
377 "cortex_a8_neon_perm_2")
378
379 ;; Instructions using this reservation read their source operands at N1, and
380 ;; produce a result at N2 on cycle 3.
381-(define_insn_reservation "neon_bp_3cycle" 4
382+(define_insn_reservation "cortex_a8_neon_bp_3cycle" 4
383 (and (eq_attr "tune" "cortexa8")
384 (eq_attr "neon_type" "neon_bp_3cycle"))
385 "cortex_a8_neon_perm_3")
386
387 ;; Instructions using this reservation produce a result at N1.
388-(define_insn_reservation "neon_ldr" 1
389+(define_insn_reservation "cortex_a8_neon_ldr" 1
390 (and (eq_attr "tune" "cortexa8")
391 (eq_attr "neon_type" "neon_ldr"))
392 "cortex_a8_neon_ls")
393
394 ;; Instructions using this reservation read their source operands at N1.
395-(define_insn_reservation "neon_str" 0
396+(define_insn_reservation "cortex_a8_neon_str" 0
397 (and (eq_attr "tune" "cortexa8")
398 (eq_attr "neon_type" "neon_str"))
399 "cortex_a8_neon_ls")
400
401 ;; Instructions using this reservation produce a result at N1 on cycle 2.
402-(define_insn_reservation "neon_vld1_1_2_regs" 2
403+(define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2
404 (and (eq_attr "tune" "cortexa8")
405 (eq_attr "neon_type" "neon_vld1_1_2_regs"))
406 "cortex_a8_neon_ls_2")
407
408 ;; Instructions using this reservation produce a result at N1 on cycle 3.
409-(define_insn_reservation "neon_vld1_3_4_regs" 3
410+(define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3
411 (and (eq_attr "tune" "cortexa8")
412 (eq_attr "neon_type" "neon_vld1_3_4_regs"))
413 "cortex_a8_neon_ls_3")
414
415 ;; Instructions using this reservation produce a result at N2 on cycle 2.
416-(define_insn_reservation "neon_vld2_2_regs_vld1_vld2_all_lanes" 3
417+(define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3
418 (and (eq_attr "tune" "cortexa8")
419 (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
420 "cortex_a8_neon_ls_2")
421
422 ;; Instructions using this reservation produce a result at N2 on cycle 3.
423-(define_insn_reservation "neon_vld2_4_regs" 4
424+(define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4
425 (and (eq_attr "tune" "cortexa8")
426 (eq_attr "neon_type" "neon_vld2_4_regs"))
427 "cortex_a8_neon_ls_3")
428
429 ;; Instructions using this reservation produce a result at N2 on cycle 4.
430-(define_insn_reservation "neon_vld3_vld4" 5
431+(define_insn_reservation "cortex_a8_neon_vld3_vld4" 5
432 (and (eq_attr "tune" "cortexa8")
433 (eq_attr "neon_type" "neon_vld3_vld4"))
434 "cortex_a8_neon_ls_4")
435
436 ;; Instructions using this reservation read their source operands at N1.
437-(define_insn_reservation "neon_vst1_1_2_regs_vst2_2_regs" 0
438+(define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0
439 (and (eq_attr "tune" "cortexa8")
440 (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs"))
441 "cortex_a8_neon_ls_2")
442
443 ;; Instructions using this reservation read their source operands at N1.
444-(define_insn_reservation "neon_vst1_3_4_regs" 0
445+(define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0
446 (and (eq_attr "tune" "cortexa8")
447 (eq_attr "neon_type" "neon_vst1_3_4_regs"))
448 "cortex_a8_neon_ls_3")
449
450 ;; Instructions using this reservation read their source operands at N1.
451-(define_insn_reservation "neon_vst2_4_regs_vst3_vst4" 0
452+(define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0
453 (and (eq_attr "tune" "cortexa8")
454 (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4"))
455 "cortex_a8_neon_ls_4")
456
457 ;; Instructions using this reservation read their source operands at N1.
458-(define_insn_reservation "neon_vst3_vst4" 0
459+(define_insn_reservation "cortex_a8_neon_vst3_vst4" 0
460 (and (eq_attr "tune" "cortexa8")
461 (eq_attr "neon_type" "neon_vst3_vst4"))
462 "cortex_a8_neon_ls_4")
463
464 ;; Instructions using this reservation read their source operands at N1, and
465 ;; produce a result at N2 on cycle 3.
466-(define_insn_reservation "neon_vld1_vld2_lane" 4
467+(define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4
468 (and (eq_attr "tune" "cortexa8")
469 (eq_attr "neon_type" "neon_vld1_vld2_lane"))
470 "cortex_a8_neon_ls_3")
471
472 ;; Instructions using this reservation read their source operands at N1, and
473 ;; produce a result at N2 on cycle 5.
474-(define_insn_reservation "neon_vld3_vld4_lane" 6
475+(define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6
476 (and (eq_attr "tune" "cortexa8")
477 (eq_attr "neon_type" "neon_vld3_vld4_lane"))
478 "cortex_a8_neon_ls_5")
479
480 ;; Instructions using this reservation read their source operands at N1.
481-(define_insn_reservation "neon_vst1_vst2_lane" 0
482+(define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0
483 (and (eq_attr "tune" "cortexa8")
484 (eq_attr "neon_type" "neon_vst1_vst2_lane"))
485 "cortex_a8_neon_ls_2")
486
487 ;; Instructions using this reservation read their source operands at N1.
488-(define_insn_reservation "neon_vst3_vst4_lane" 0
489+(define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0
490 (and (eq_attr "tune" "cortexa8")
491 (eq_attr "neon_type" "neon_vst3_vst4_lane"))
492 "cortex_a8_neon_ls_3")
493
494 ;; Instructions using this reservation produce a result at N2 on cycle 2.
495-(define_insn_reservation "neon_vld3_vld4_all_lanes" 3
496+(define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3
497 (and (eq_attr "tune" "cortexa8")
498 (eq_attr "neon_type" "neon_vld3_vld4_all_lanes"))
499 "cortex_a8_neon_ls_3")
500
501 ;; Instructions using this reservation produce a result at N2.
502-(define_insn_reservation "neon_mcr" 2
503+(define_insn_reservation "cortex_a8_neon_mcr" 2
504 (and (eq_attr "tune" "cortexa8")
505 (eq_attr "neon_type" "neon_mcr"))
506 "cortex_a8_neon_perm")
507
508 ;; Instructions using this reservation produce a result at N2.
509-(define_insn_reservation "neon_mcr_2_mcrr" 2
510+(define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2
511 (and (eq_attr "tune" "cortexa8")
512 (eq_attr "neon_type" "neon_mcr_2_mcrr"))
513 "cortex_a8_neon_perm_2")
514
515 ;; Exceptions to the default latencies.
516
517-(define_bypass 1 "neon_mcr_2_mcrr"
518- "neon_int_1,\
519- neon_int_4,\
520- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
521- neon_mul_qqq_8_16_32_ddd_32,\
522- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
523- neon_mla_qqq_8_16,\
524- neon_fp_vadd_ddd_vabs_dd,\
525- neon_fp_vadd_qqq_vabs_qq,\
526- neon_fp_vmla_ddd,\
527- neon_fp_vmla_qqq,\
528- neon_fp_vrecps_vrsqrts_ddd,\
529- neon_fp_vrecps_vrsqrts_qqq")
530-
531-(define_bypass 1 "neon_mcr"
532- "neon_int_1,\
533- neon_int_4,\
534- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
535- neon_mul_qqq_8_16_32_ddd_32,\
536- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
537- neon_mla_qqq_8_16,\
538- neon_fp_vadd_ddd_vabs_dd,\
539- neon_fp_vadd_qqq_vabs_qq,\
540- neon_fp_vmla_ddd,\
541- neon_fp_vmla_qqq,\
542- neon_fp_vrecps_vrsqrts_ddd,\
543- neon_fp_vrecps_vrsqrts_qqq")
544-
545-(define_bypass 2 "neon_vld3_vld4_all_lanes"
546- "neon_int_1,\
547- neon_int_4,\
548- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
549- neon_mul_qqq_8_16_32_ddd_32,\
550- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
551- neon_mla_qqq_8_16,\
552- neon_fp_vadd_ddd_vabs_dd,\
553- neon_fp_vadd_qqq_vabs_qq,\
554- neon_fp_vmla_ddd,\
555- neon_fp_vmla_qqq,\
556- neon_fp_vrecps_vrsqrts_ddd,\
557- neon_fp_vrecps_vrsqrts_qqq")
558-
559-(define_bypass 5 "neon_vld3_vld4_lane"
560- "neon_int_1,\
561- neon_int_4,\
562- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
563- neon_mul_qqq_8_16_32_ddd_32,\
564- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
565- neon_mla_qqq_8_16,\
566- neon_fp_vadd_ddd_vabs_dd,\
567- neon_fp_vadd_qqq_vabs_qq,\
568- neon_fp_vmla_ddd,\
569- neon_fp_vmla_qqq,\
570- neon_fp_vrecps_vrsqrts_ddd,\
571- neon_fp_vrecps_vrsqrts_qqq")
572-
573-(define_bypass 3 "neon_vld1_vld2_lane"
574- "neon_int_1,\
575- neon_int_4,\
576- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
577- neon_mul_qqq_8_16_32_ddd_32,\
578- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
579- neon_mla_qqq_8_16,\
580- neon_fp_vadd_ddd_vabs_dd,\
581- neon_fp_vadd_qqq_vabs_qq,\
582- neon_fp_vmla_ddd,\
583- neon_fp_vmla_qqq,\
584- neon_fp_vrecps_vrsqrts_ddd,\
585- neon_fp_vrecps_vrsqrts_qqq")
586-
587-(define_bypass 4 "neon_vld3_vld4"
588- "neon_int_1,\
589- neon_int_4,\
590- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
591- neon_mul_qqq_8_16_32_ddd_32,\
592- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
593- neon_mla_qqq_8_16,\
594- neon_fp_vadd_ddd_vabs_dd,\
595- neon_fp_vadd_qqq_vabs_qq,\
596- neon_fp_vmla_ddd,\
597- neon_fp_vmla_qqq,\
598- neon_fp_vrecps_vrsqrts_ddd,\
599- neon_fp_vrecps_vrsqrts_qqq")
600-
601-(define_bypass 3 "neon_vld2_4_regs"
602- "neon_int_1,\
603- neon_int_4,\
604- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
605- neon_mul_qqq_8_16_32_ddd_32,\
606- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
607- neon_mla_qqq_8_16,\
608- neon_fp_vadd_ddd_vabs_dd,\
609- neon_fp_vadd_qqq_vabs_qq,\
610- neon_fp_vmla_ddd,\
611- neon_fp_vmla_qqq,\
612- neon_fp_vrecps_vrsqrts_ddd,\
613- neon_fp_vrecps_vrsqrts_qqq")
614-
615-(define_bypass 2 "neon_vld2_2_regs_vld1_vld2_all_lanes"
616- "neon_int_1,\
617- neon_int_4,\
618- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
619- neon_mul_qqq_8_16_32_ddd_32,\
620- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
621- neon_mla_qqq_8_16,\
622- neon_fp_vadd_ddd_vabs_dd,\
623- neon_fp_vadd_qqq_vabs_qq,\
624- neon_fp_vmla_ddd,\
625- neon_fp_vmla_qqq,\
626- neon_fp_vrecps_vrsqrts_ddd,\
627- neon_fp_vrecps_vrsqrts_qqq")
628-
629-(define_bypass 2 "neon_vld1_3_4_regs"
630- "neon_int_1,\
631- neon_int_4,\
632- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
633- neon_mul_qqq_8_16_32_ddd_32,\
634- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
635- neon_mla_qqq_8_16,\
636- neon_fp_vadd_ddd_vabs_dd,\
637- neon_fp_vadd_qqq_vabs_qq,\
638- neon_fp_vmla_ddd,\
639- neon_fp_vmla_qqq,\
640- neon_fp_vrecps_vrsqrts_ddd,\
641- neon_fp_vrecps_vrsqrts_qqq")
642-
643-(define_bypass 1 "neon_vld1_1_2_regs"
644- "neon_int_1,\
645- neon_int_4,\
646- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
647- neon_mul_qqq_8_16_32_ddd_32,\
648- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
649- neon_mla_qqq_8_16,\
650- neon_fp_vadd_ddd_vabs_dd,\
651- neon_fp_vadd_qqq_vabs_qq,\
652- neon_fp_vmla_ddd,\
653- neon_fp_vmla_qqq,\
654- neon_fp_vrecps_vrsqrts_ddd,\
655- neon_fp_vrecps_vrsqrts_qqq")
656-
657-(define_bypass 0 "neon_ldr"
658- "neon_int_1,\
659- neon_int_4,\
660- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
661- neon_mul_qqq_8_16_32_ddd_32,\
662- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
663- neon_mla_qqq_8_16,\
664- neon_fp_vadd_ddd_vabs_dd,\
665- neon_fp_vadd_qqq_vabs_qq,\
666- neon_fp_vmla_ddd,\
667- neon_fp_vmla_qqq,\
668- neon_fp_vrecps_vrsqrts_ddd,\
669- neon_fp_vrecps_vrsqrts_qqq")
670-
671-(define_bypass 3 "neon_bp_3cycle"
672- "neon_int_1,\
673- neon_int_4,\
674- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
675- neon_mul_qqq_8_16_32_ddd_32,\
676- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
677- neon_mla_qqq_8_16,\
678- neon_fp_vadd_ddd_vabs_dd,\
679- neon_fp_vadd_qqq_vabs_qq,\
680- neon_fp_vmla_ddd,\
681- neon_fp_vmla_qqq,\
682- neon_fp_vrecps_vrsqrts_ddd,\
683- neon_fp_vrecps_vrsqrts_qqq")
684-
685-(define_bypass 2 "neon_bp_2cycle"
686- "neon_int_1,\
687- neon_int_4,\
688- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
689- neon_mul_qqq_8_16_32_ddd_32,\
690- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
691- neon_mla_qqq_8_16,\
692- neon_fp_vadd_ddd_vabs_dd,\
693- neon_fp_vadd_qqq_vabs_qq,\
694- neon_fp_vmla_ddd,\
695- neon_fp_vmla_qqq,\
696- neon_fp_vrecps_vrsqrts_ddd,\
697- neon_fp_vrecps_vrsqrts_qqq")
698-
699-(define_bypass 1 "neon_bp_simple"
700- "neon_int_1,\
701- neon_int_4,\
702- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
703- neon_mul_qqq_8_16_32_ddd_32,\
704- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
705- neon_mla_qqq_8_16,\
706- neon_fp_vadd_ddd_vabs_dd,\
707- neon_fp_vadd_qqq_vabs_qq,\
708- neon_fp_vmla_ddd,\
709- neon_fp_vmla_qqq,\
710- neon_fp_vrecps_vrsqrts_ddd,\
711- neon_fp_vrecps_vrsqrts_qqq")
712-
713-(define_bypass 9 "neon_fp_vrecps_vrsqrts_qqq"
714- "neon_int_1,\
715- neon_int_4,\
716- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
717- neon_mul_qqq_8_16_32_ddd_32,\
718- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
719- neon_mla_qqq_8_16,\
720- neon_fp_vadd_ddd_vabs_dd,\
721- neon_fp_vadd_qqq_vabs_qq,\
722- neon_fp_vmla_ddd,\
723- neon_fp_vmla_qqq,\
724- neon_fp_vrecps_vrsqrts_ddd,\
725- neon_fp_vrecps_vrsqrts_qqq")
726-
727-(define_bypass 8 "neon_fp_vrecps_vrsqrts_ddd"
728- "neon_int_1,\
729- neon_int_4,\
730- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
731- neon_mul_qqq_8_16_32_ddd_32,\
732- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
733- neon_mla_qqq_8_16,\
734- neon_fp_vadd_ddd_vabs_dd,\
735- neon_fp_vadd_qqq_vabs_qq,\
736- neon_fp_vmla_ddd,\
737- neon_fp_vmla_qqq,\
738- neon_fp_vrecps_vrsqrts_ddd,\
739- neon_fp_vrecps_vrsqrts_qqq")
740-
741-(define_bypass 9 "neon_fp_vmla_qqq_scalar"
742- "neon_int_1,\
743- neon_int_4,\
744- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
745- neon_mul_qqq_8_16_32_ddd_32,\
746- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
747- neon_mla_qqq_8_16,\
748- neon_fp_vadd_ddd_vabs_dd,\
749- neon_fp_vadd_qqq_vabs_qq,\
750- neon_fp_vmla_ddd,\
751- neon_fp_vmla_qqq,\
752- neon_fp_vrecps_vrsqrts_ddd,\
753- neon_fp_vrecps_vrsqrts_qqq")
754-
755-(define_bypass 8 "neon_fp_vmla_ddd_scalar"
756- "neon_int_1,\
757- neon_int_4,\
758- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
759- neon_mul_qqq_8_16_32_ddd_32,\
760- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
761- neon_mla_qqq_8_16,\
762- neon_fp_vadd_ddd_vabs_dd,\
763- neon_fp_vadd_qqq_vabs_qq,\
764- neon_fp_vmla_ddd,\
765- neon_fp_vmla_qqq,\
766- neon_fp_vrecps_vrsqrts_ddd,\
767- neon_fp_vrecps_vrsqrts_qqq")
768-
769-(define_bypass 9 "neon_fp_vmla_qqq"
770- "neon_int_1,\
771- neon_int_4,\
772- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
773- neon_mul_qqq_8_16_32_ddd_32,\
774- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
775- neon_mla_qqq_8_16,\
776- neon_fp_vadd_ddd_vabs_dd,\
777- neon_fp_vadd_qqq_vabs_qq,\
778- neon_fp_vmla_ddd,\
779- neon_fp_vmla_qqq,\
780- neon_fp_vrecps_vrsqrts_ddd,\
781- neon_fp_vrecps_vrsqrts_qqq")
782-
783-(define_bypass 8 "neon_fp_vmla_ddd"
784- "neon_int_1,\
785- neon_int_4,\
786- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
787- neon_mul_qqq_8_16_32_ddd_32,\
788- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
789- neon_mla_qqq_8_16,\
790- neon_fp_vadd_ddd_vabs_dd,\
791- neon_fp_vadd_qqq_vabs_qq,\
792- neon_fp_vmla_ddd,\
793- neon_fp_vmla_qqq,\
794- neon_fp_vrecps_vrsqrts_ddd,\
795- neon_fp_vrecps_vrsqrts_qqq")
796-
797-(define_bypass 5 "neon_fp_vmul_qqd"
798- "neon_int_1,\
799- neon_int_4,\
800- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
801- neon_mul_qqq_8_16_32_ddd_32,\
802- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
803- neon_mla_qqq_8_16,\
804- neon_fp_vadd_ddd_vabs_dd,\
805- neon_fp_vadd_qqq_vabs_qq,\
806- neon_fp_vmla_ddd,\
807- neon_fp_vmla_qqq,\
808- neon_fp_vrecps_vrsqrts_ddd,\
809- neon_fp_vrecps_vrsqrts_qqq")
810-
811-(define_bypass 4 "neon_fp_vmul_ddd"
812- "neon_int_1,\
813- neon_int_4,\
814- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
815- neon_mul_qqq_8_16_32_ddd_32,\
816- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
817- neon_mla_qqq_8_16,\
818- neon_fp_vadd_ddd_vabs_dd,\
819- neon_fp_vadd_qqq_vabs_qq,\
820- neon_fp_vmla_ddd,\
821- neon_fp_vmla_qqq,\
822- neon_fp_vrecps_vrsqrts_ddd,\
823- neon_fp_vrecps_vrsqrts_qqq")
824-
825-(define_bypass 4 "neon_fp_vsum"
826- "neon_int_1,\
827- neon_int_4,\
828- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
829- neon_mul_qqq_8_16_32_ddd_32,\
830- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
831- neon_mla_qqq_8_16,\
832- neon_fp_vadd_ddd_vabs_dd,\
833- neon_fp_vadd_qqq_vabs_qq,\
834- neon_fp_vmla_ddd,\
835- neon_fp_vmla_qqq,\
836- neon_fp_vrecps_vrsqrts_ddd,\
837- neon_fp_vrecps_vrsqrts_qqq")
838-
839-(define_bypass 5 "neon_fp_vadd_qqq_vabs_qq"
840- "neon_int_1,\
841- neon_int_4,\
842- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
843- neon_mul_qqq_8_16_32_ddd_32,\
844- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
845- neon_mla_qqq_8_16,\
846- neon_fp_vadd_ddd_vabs_dd,\
847- neon_fp_vadd_qqq_vabs_qq,\
848- neon_fp_vmla_ddd,\
849- neon_fp_vmla_qqq,\
850- neon_fp_vrecps_vrsqrts_ddd,\
851- neon_fp_vrecps_vrsqrts_qqq")
852-
853-(define_bypass 4 "neon_fp_vadd_ddd_vabs_dd"
854- "neon_int_1,\
855- neon_int_4,\
856- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
857- neon_mul_qqq_8_16_32_ddd_32,\
858- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
859- neon_mla_qqq_8_16,\
860- neon_fp_vadd_ddd_vabs_dd,\
861- neon_fp_vadd_qqq_vabs_qq,\
862- neon_fp_vmla_ddd,\
863- neon_fp_vmla_qqq,\
864- neon_fp_vrecps_vrsqrts_ddd,\
865- neon_fp_vrecps_vrsqrts_qqq")
866-
867-(define_bypass 5 "neon_vsra_vrsra"
868- "neon_int_1,\
869- neon_int_4,\
870- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
871- neon_mul_qqq_8_16_32_ddd_32,\
872- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
873- neon_mla_qqq_8_16,\
874- neon_fp_vadd_ddd_vabs_dd,\
875- neon_fp_vadd_qqq_vabs_qq,\
876- neon_fp_vmla_ddd,\
877- neon_fp_vmla_qqq,\
878- neon_fp_vrecps_vrsqrts_ddd,\
879- neon_fp_vrecps_vrsqrts_qqq")
880-
881-(define_bypass 4 "neon_vqshl_vrshl_vqrshl_qqq"
882- "neon_int_1,\
883- neon_int_4,\
884- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
885- neon_mul_qqq_8_16_32_ddd_32,\
886- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
887- neon_mla_qqq_8_16,\
888- neon_fp_vadd_ddd_vabs_dd,\
889- neon_fp_vadd_qqq_vabs_qq,\
890- neon_fp_vmla_ddd,\
891- neon_fp_vmla_qqq,\
892- neon_fp_vrecps_vrsqrts_ddd,\
893- neon_fp_vrecps_vrsqrts_qqq")
894-
895-(define_bypass 0 "neon_vshl_ddd"
896- "neon_int_1,\
897- neon_int_4,\
898- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
899- neon_mul_qqq_8_16_32_ddd_32,\
900- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
901- neon_mla_qqq_8_16,\
902- neon_fp_vadd_ddd_vabs_dd,\
903- neon_fp_vadd_qqq_vabs_qq,\
904- neon_fp_vmla_ddd,\
905- neon_fp_vmla_qqq,\
906- neon_fp_vrecps_vrsqrts_ddd,\
907- neon_fp_vrecps_vrsqrts_qqq")
908-
909-(define_bypass 3 "neon_shift_3"
910- "neon_int_1,\
911- neon_int_4,\
912- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
913- neon_mul_qqq_8_16_32_ddd_32,\
914- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
915- neon_mla_qqq_8_16,\
916- neon_fp_vadd_ddd_vabs_dd,\
917- neon_fp_vadd_qqq_vabs_qq,\
918- neon_fp_vmla_ddd,\
919- neon_fp_vmla_qqq,\
920- neon_fp_vrecps_vrsqrts_ddd,\
921- neon_fp_vrecps_vrsqrts_qqq")
922-
923-(define_bypass 3 "neon_shift_2"
924- "neon_int_1,\
925- neon_int_4,\
926- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
927- neon_mul_qqq_8_16_32_ddd_32,\
928- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
929- neon_mla_qqq_8_16,\
930- neon_fp_vadd_ddd_vabs_dd,\
931- neon_fp_vadd_qqq_vabs_qq,\
932- neon_fp_vmla_ddd,\
933- neon_fp_vmla_qqq,\
934- neon_fp_vrecps_vrsqrts_ddd,\
935- neon_fp_vrecps_vrsqrts_qqq")
936-
937-(define_bypass 2 "neon_shift_1"
938- "neon_int_1,\
939- neon_int_4,\
940- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
941- neon_mul_qqq_8_16_32_ddd_32,\
942- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
943- neon_mla_qqq_8_16,\
944- neon_fp_vadd_ddd_vabs_dd,\
945- neon_fp_vadd_qqq_vabs_qq,\
946- neon_fp_vmla_ddd,\
947- neon_fp_vmla_qqq,\
948- neon_fp_vrecps_vrsqrts_ddd,\
949- neon_fp_vrecps_vrsqrts_qqq")
950-
951-(define_bypass 5 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"
952- "neon_int_1,\
953- neon_int_4,\
954- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
955- neon_mul_qqq_8_16_32_ddd_32,\
956- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
957- neon_mla_qqq_8_16,\
958- neon_fp_vadd_ddd_vabs_dd,\
959- neon_fp_vadd_qqq_vabs_qq,\
960- neon_fp_vmla_ddd,\
961- neon_fp_vmla_qqq,\
962- neon_fp_vrecps_vrsqrts_ddd,\
963- neon_fp_vrecps_vrsqrts_qqq")
964-
965-(define_bypass 8 "neon_mul_qqd_32_scalar"
966- "neon_int_1,\
967- neon_int_4,\
968- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
969- neon_mul_qqq_8_16_32_ddd_32,\
970- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
971- neon_mla_qqq_8_16,\
972- neon_fp_vadd_ddd_vabs_dd,\
973- neon_fp_vadd_qqq_vabs_qq,\
974- neon_fp_vmla_ddd,\
975- neon_fp_vmla_qqq,\
976- neon_fp_vrecps_vrsqrts_ddd,\
977- neon_fp_vrecps_vrsqrts_qqq")
978-
979-(define_bypass 5 "neon_mul_ddd_16_scalar_32_16_long_scalar"
980- "neon_int_1,\
981- neon_int_4,\
982- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
983- neon_mul_qqq_8_16_32_ddd_32,\
984- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
985- neon_mla_qqq_8_16,\
986- neon_fp_vadd_ddd_vabs_dd,\
987- neon_fp_vadd_qqq_vabs_qq,\
988- neon_fp_vmla_ddd,\
989- neon_fp_vmla_qqq,\
990- neon_fp_vrecps_vrsqrts_ddd,\
991- neon_fp_vrecps_vrsqrts_qqq")
992-
993-(define_bypass 8 "neon_mla_qqq_32_qqd_32_scalar"
994- "neon_int_1,\
995- neon_int_4,\
996- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
997- neon_mul_qqq_8_16_32_ddd_32,\
998- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
999- neon_mla_qqq_8_16,\
1000- neon_fp_vadd_ddd_vabs_dd,\
1001- neon_fp_vadd_qqq_vabs_qq,\
1002- neon_fp_vmla_ddd,\
1003- neon_fp_vmla_qqq,\
1004- neon_fp_vrecps_vrsqrts_ddd,\
1005- neon_fp_vrecps_vrsqrts_qqq")
1006-
1007-(define_bypass 6 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"
1008- "neon_int_1,\
1009- neon_int_4,\
1010- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1011- neon_mul_qqq_8_16_32_ddd_32,\
1012- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1013- neon_mla_qqq_8_16,\
1014- neon_fp_vadd_ddd_vabs_dd,\
1015- neon_fp_vadd_qqq_vabs_qq,\
1016- neon_fp_vmla_ddd,\
1017- neon_fp_vmla_qqq,\
1018- neon_fp_vrecps_vrsqrts_ddd,\
1019- neon_fp_vrecps_vrsqrts_qqq")
1020-
1021-(define_bypass 6 "neon_mla_qqq_8_16"
1022- "neon_int_1,\
1023- neon_int_4,\
1024- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1025- neon_mul_qqq_8_16_32_ddd_32,\
1026- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1027- neon_mla_qqq_8_16,\
1028- neon_fp_vadd_ddd_vabs_dd,\
1029- neon_fp_vadd_qqq_vabs_qq,\
1030- neon_fp_vmla_ddd,\
1031- neon_fp_vmla_qqq,\
1032- neon_fp_vrecps_vrsqrts_ddd,\
1033- neon_fp_vrecps_vrsqrts_qqq")
1034-
1035-(define_bypass 5 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"
1036- "neon_int_1,\
1037- neon_int_4,\
1038- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1039- neon_mul_qqq_8_16_32_ddd_32,\
1040- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1041- neon_mla_qqq_8_16,\
1042- neon_fp_vadd_ddd_vabs_dd,\
1043- neon_fp_vadd_qqq_vabs_qq,\
1044- neon_fp_vmla_ddd,\
1045- neon_fp_vmla_qqq,\
1046- neon_fp_vrecps_vrsqrts_ddd,\
1047- neon_fp_vrecps_vrsqrts_qqq")
1048-
1049-(define_bypass 6 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"
1050- "neon_int_1,\
1051- neon_int_4,\
1052- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1053- neon_mul_qqq_8_16_32_ddd_32,\
1054- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1055- neon_mla_qqq_8_16,\
1056- neon_fp_vadd_ddd_vabs_dd,\
1057- neon_fp_vadd_qqq_vabs_qq,\
1058- neon_fp_vmla_ddd,\
1059- neon_fp_vmla_qqq,\
1060- neon_fp_vrecps_vrsqrts_ddd,\
1061- neon_fp_vrecps_vrsqrts_qqq")
1062-
1063-(define_bypass 6 "neon_mul_qqq_8_16_32_ddd_32"
1064- "neon_int_1,\
1065- neon_int_4,\
1066- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1067- neon_mul_qqq_8_16_32_ddd_32,\
1068- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1069- neon_mla_qqq_8_16,\
1070- neon_fp_vadd_ddd_vabs_dd,\
1071- neon_fp_vadd_qqq_vabs_qq,\
1072- neon_fp_vmla_ddd,\
1073- neon_fp_vmla_qqq,\
1074- neon_fp_vrecps_vrsqrts_ddd,\
1075- neon_fp_vrecps_vrsqrts_qqq")
1076-
1077-(define_bypass 5 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"
1078- "neon_int_1,\
1079- neon_int_4,\
1080- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1081- neon_mul_qqq_8_16_32_ddd_32,\
1082- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1083- neon_mla_qqq_8_16,\
1084- neon_fp_vadd_ddd_vabs_dd,\
1085- neon_fp_vadd_qqq_vabs_qq,\
1086- neon_fp_vmla_ddd,\
1087- neon_fp_vmla_qqq,\
1088- neon_fp_vrecps_vrsqrts_ddd,\
1089- neon_fp_vrecps_vrsqrts_qqq")
1090-
1091-(define_bypass 5 "neon_vsma"
1092- "neon_int_1,\
1093- neon_int_4,\
1094- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1095- neon_mul_qqq_8_16_32_ddd_32,\
1096- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1097- neon_mla_qqq_8_16,\
1098- neon_fp_vadd_ddd_vabs_dd,\
1099- neon_fp_vadd_qqq_vabs_qq,\
1100- neon_fp_vmla_ddd,\
1101- neon_fp_vmla_qqq,\
1102- neon_fp_vrecps_vrsqrts_ddd,\
1103- neon_fp_vrecps_vrsqrts_qqq")
1104-
1105-(define_bypass 6 "neon_vaba_qqq"
1106- "neon_int_1,\
1107- neon_int_4,\
1108- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1109- neon_mul_qqq_8_16_32_ddd_32,\
1110- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1111- neon_mla_qqq_8_16,\
1112- neon_fp_vadd_ddd_vabs_dd,\
1113- neon_fp_vadd_qqq_vabs_qq,\
1114- neon_fp_vmla_ddd,\
1115- neon_fp_vmla_qqq,\
1116- neon_fp_vrecps_vrsqrts_ddd,\
1117- neon_fp_vrecps_vrsqrts_qqq")
1118-
1119-(define_bypass 5 "neon_vaba"
1120- "neon_int_1,\
1121- neon_int_4,\
1122- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1123- neon_mul_qqq_8_16_32_ddd_32,\
1124- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1125- neon_mla_qqq_8_16,\
1126- neon_fp_vadd_ddd_vabs_dd,\
1127- neon_fp_vadd_qqq_vabs_qq,\
1128- neon_fp_vmla_ddd,\
1129- neon_fp_vmla_qqq,\
1130- neon_fp_vrecps_vrsqrts_ddd,\
1131- neon_fp_vrecps_vrsqrts_qqq")
1132-
1133-(define_bypass 2 "neon_vmov"
1134- "neon_int_1,\
1135- neon_int_4,\
1136- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1137- neon_mul_qqq_8_16_32_ddd_32,\
1138- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1139- neon_mla_qqq_8_16,\
1140- neon_fp_vadd_ddd_vabs_dd,\
1141- neon_fp_vadd_qqq_vabs_qq,\
1142- neon_fp_vmla_ddd,\
1143- neon_fp_vmla_qqq,\
1144- neon_fp_vrecps_vrsqrts_ddd,\
1145- neon_fp_vrecps_vrsqrts_qqq")
1146-
1147-(define_bypass 3 "neon_vqneg_vqabs"
1148- "neon_int_1,\
1149- neon_int_4,\
1150- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1151- neon_mul_qqq_8_16_32_ddd_32,\
1152- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1153- neon_mla_qqq_8_16,\
1154- neon_fp_vadd_ddd_vabs_dd,\
1155- neon_fp_vadd_qqq_vabs_qq,\
1156- neon_fp_vmla_ddd,\
1157- neon_fp_vmla_qqq,\
1158- neon_fp_vrecps_vrsqrts_ddd,\
1159- neon_fp_vrecps_vrsqrts_qqq")
1160-
1161-(define_bypass 3 "neon_int_5"
1162- "neon_int_1,\
1163- neon_int_4,\
1164- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1165- neon_mul_qqq_8_16_32_ddd_32,\
1166- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1167- neon_mla_qqq_8_16,\
1168- neon_fp_vadd_ddd_vabs_dd,\
1169- neon_fp_vadd_qqq_vabs_qq,\
1170- neon_fp_vmla_ddd,\
1171- neon_fp_vmla_qqq,\
1172- neon_fp_vrecps_vrsqrts_ddd,\
1173- neon_fp_vrecps_vrsqrts_qqq")
1174-
1175-(define_bypass 3 "neon_int_4"
1176- "neon_int_1,\
1177- neon_int_4,\
1178- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1179- neon_mul_qqq_8_16_32_ddd_32,\
1180- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1181- neon_mla_qqq_8_16,\
1182- neon_fp_vadd_ddd_vabs_dd,\
1183- neon_fp_vadd_qqq_vabs_qq,\
1184- neon_fp_vmla_ddd,\
1185- neon_fp_vmla_qqq,\
1186- neon_fp_vrecps_vrsqrts_ddd,\
1187- neon_fp_vrecps_vrsqrts_qqq")
1188-
1189-(define_bypass 2 "neon_int_3"
1190- "neon_int_1,\
1191- neon_int_4,\
1192- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1193- neon_mul_qqq_8_16_32_ddd_32,\
1194- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1195- neon_mla_qqq_8_16,\
1196- neon_fp_vadd_ddd_vabs_dd,\
1197- neon_fp_vadd_qqq_vabs_qq,\
1198- neon_fp_vmla_ddd,\
1199- neon_fp_vmla_qqq,\
1200- neon_fp_vrecps_vrsqrts_ddd,\
1201- neon_fp_vrecps_vrsqrts_qqq")
1202-
1203-(define_bypass 2 "neon_int_2"
1204- "neon_int_1,\
1205- neon_int_4,\
1206- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1207- neon_mul_qqq_8_16_32_ddd_32,\
1208- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1209- neon_mla_qqq_8_16,\
1210- neon_fp_vadd_ddd_vabs_dd,\
1211- neon_fp_vadd_qqq_vabs_qq,\
1212- neon_fp_vmla_ddd,\
1213- neon_fp_vmla_qqq,\
1214- neon_fp_vrecps_vrsqrts_ddd,\
1215- neon_fp_vrecps_vrsqrts_qqq")
1216-
1217-(define_bypass 2 "neon_int_1"
1218- "neon_int_1,\
1219- neon_int_4,\
1220- neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1221- neon_mul_qqq_8_16_32_ddd_32,\
1222- neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1223- neon_mla_qqq_8_16,\
1224- neon_fp_vadd_ddd_vabs_dd,\
1225- neon_fp_vadd_qqq_vabs_qq,\
1226- neon_fp_vmla_ddd,\
1227- neon_fp_vmla_qqq,\
1228- neon_fp_vrecps_vrsqrts_ddd,\
1229- neon_fp_vrecps_vrsqrts_qqq")
1230+(define_bypass 1 "cortex_a8_neon_mcr_2_mcrr"
1231+ "cortex_a8_neon_int_1,\
1232+ cortex_a8_neon_int_4,\
1233+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1234+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1235+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1236+ cortex_a8_neon_mla_qqq_8_16,\
1237+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1238+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1239+ cortex_a8_neon_fp_vmla_ddd,\
1240+ cortex_a8_neon_fp_vmla_qqq,\
1241+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1242+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1243+
1244+(define_bypass 1 "cortex_a8_neon_mcr"
1245+ "cortex_a8_neon_int_1,\
1246+ cortex_a8_neon_int_4,\
1247+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1248+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1249+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1250+ cortex_a8_neon_mla_qqq_8_16,\
1251+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1252+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1253+ cortex_a8_neon_fp_vmla_ddd,\
1254+ cortex_a8_neon_fp_vmla_qqq,\
1255+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1256+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1257+
1258+(define_bypass 2 "cortex_a8_neon_vld3_vld4_all_lanes"
1259+ "cortex_a8_neon_int_1,\
1260+ cortex_a8_neon_int_4,\
1261+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1262+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1263+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1264+ cortex_a8_neon_mla_qqq_8_16,\
1265+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1266+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1267+ cortex_a8_neon_fp_vmla_ddd,\
1268+ cortex_a8_neon_fp_vmla_qqq,\
1269+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1270+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1271+
1272+(define_bypass 5 "cortex_a8_neon_vld3_vld4_lane"
1273+ "cortex_a8_neon_int_1,\
1274+ cortex_a8_neon_int_4,\
1275+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1276+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1277+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1278+ cortex_a8_neon_mla_qqq_8_16,\
1279+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1280+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1281+ cortex_a8_neon_fp_vmla_ddd,\
1282+ cortex_a8_neon_fp_vmla_qqq,\
1283+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1284+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1285+
1286+(define_bypass 3 "cortex_a8_neon_vld1_vld2_lane"
1287+ "cortex_a8_neon_int_1,\
1288+ cortex_a8_neon_int_4,\
1289+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1290+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1291+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1292+ cortex_a8_neon_mla_qqq_8_16,\
1293+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1294+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1295+ cortex_a8_neon_fp_vmla_ddd,\
1296+ cortex_a8_neon_fp_vmla_qqq,\
1297+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1298+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1299+
1300+(define_bypass 4 "cortex_a8_neon_vld3_vld4"
1301+ "cortex_a8_neon_int_1,\
1302+ cortex_a8_neon_int_4,\
1303+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1304+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1305+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1306+ cortex_a8_neon_mla_qqq_8_16,\
1307+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1308+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1309+ cortex_a8_neon_fp_vmla_ddd,\
1310+ cortex_a8_neon_fp_vmla_qqq,\
1311+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1312+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1313+
1314+(define_bypass 3 "cortex_a8_neon_vld2_4_regs"
1315+ "cortex_a8_neon_int_1,\
1316+ cortex_a8_neon_int_4,\
1317+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1318+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1319+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1320+ cortex_a8_neon_mla_qqq_8_16,\
1321+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1322+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1323+ cortex_a8_neon_fp_vmla_ddd,\
1324+ cortex_a8_neon_fp_vmla_qqq,\
1325+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1326+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1327+
1328+(define_bypass 2 "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes"
1329+ "cortex_a8_neon_int_1,\
1330+ cortex_a8_neon_int_4,\
1331+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1332+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1333+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1334+ cortex_a8_neon_mla_qqq_8_16,\
1335+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1336+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1337+ cortex_a8_neon_fp_vmla_ddd,\
1338+ cortex_a8_neon_fp_vmla_qqq,\
1339+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1340+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1341+
1342+(define_bypass 2 "cortex_a8_neon_vld1_3_4_regs"
1343+ "cortex_a8_neon_int_1,\
1344+ cortex_a8_neon_int_4,\
1345+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1346+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1347+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1348+ cortex_a8_neon_mla_qqq_8_16,\
1349+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1350+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1351+ cortex_a8_neon_fp_vmla_ddd,\
1352+ cortex_a8_neon_fp_vmla_qqq,\
1353+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1354+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1355+
1356+(define_bypass 1 "cortex_a8_neon_vld1_1_2_regs"
1357+ "cortex_a8_neon_int_1,\
1358+ cortex_a8_neon_int_4,\
1359+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1360+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1361+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1362+ cortex_a8_neon_mla_qqq_8_16,\
1363+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1364+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1365+ cortex_a8_neon_fp_vmla_ddd,\
1366+ cortex_a8_neon_fp_vmla_qqq,\
1367+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1368+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1369+
1370+(define_bypass 0 "cortex_a8_neon_ldr"
1371+ "cortex_a8_neon_int_1,\
1372+ cortex_a8_neon_int_4,\
1373+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1374+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1375+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1376+ cortex_a8_neon_mla_qqq_8_16,\
1377+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1378+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1379+ cortex_a8_neon_fp_vmla_ddd,\
1380+ cortex_a8_neon_fp_vmla_qqq,\
1381+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1382+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1383+
1384+(define_bypass 3 "cortex_a8_neon_bp_3cycle"
1385+ "cortex_a8_neon_int_1,\
1386+ cortex_a8_neon_int_4,\
1387+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1388+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1389+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1390+ cortex_a8_neon_mla_qqq_8_16,\
1391+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1392+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1393+ cortex_a8_neon_fp_vmla_ddd,\
1394+ cortex_a8_neon_fp_vmla_qqq,\
1395+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1396+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1397+
1398+(define_bypass 2 "cortex_a8_neon_bp_2cycle"
1399+ "cortex_a8_neon_int_1,\
1400+ cortex_a8_neon_int_4,\
1401+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1402+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1403+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1404+ cortex_a8_neon_mla_qqq_8_16,\
1405+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1406+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1407+ cortex_a8_neon_fp_vmla_ddd,\
1408+ cortex_a8_neon_fp_vmla_qqq,\
1409+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1410+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1411+
1412+(define_bypass 1 "cortex_a8_neon_bp_simple"
1413+ "cortex_a8_neon_int_1,\
1414+ cortex_a8_neon_int_4,\
1415+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1416+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1417+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1418+ cortex_a8_neon_mla_qqq_8_16,\
1419+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1420+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1421+ cortex_a8_neon_fp_vmla_ddd,\
1422+ cortex_a8_neon_fp_vmla_qqq,\
1423+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1424+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1425+
1426+(define_bypass 9 "cortex_a8_neon_fp_vrecps_vrsqrts_qqq"
1427+ "cortex_a8_neon_int_1,\
1428+ cortex_a8_neon_int_4,\
1429+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1430+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1431+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1432+ cortex_a8_neon_mla_qqq_8_16,\
1433+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1434+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1435+ cortex_a8_neon_fp_vmla_ddd,\
1436+ cortex_a8_neon_fp_vmla_qqq,\
1437+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1438+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1439+
1440+(define_bypass 8 "cortex_a8_neon_fp_vrecps_vrsqrts_ddd"
1441+ "cortex_a8_neon_int_1,\
1442+ cortex_a8_neon_int_4,\
1443+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1444+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1445+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1446+ cortex_a8_neon_mla_qqq_8_16,\
1447+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1448+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1449+ cortex_a8_neon_fp_vmla_ddd,\
1450+ cortex_a8_neon_fp_vmla_qqq,\
1451+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1452+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1453+
1454+(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq_scalar"
1455+ "cortex_a8_neon_int_1,\
1456+ cortex_a8_neon_int_4,\
1457+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1458+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1459+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1460+ cortex_a8_neon_mla_qqq_8_16,\
1461+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1462+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1463+ cortex_a8_neon_fp_vmla_ddd,\
1464+ cortex_a8_neon_fp_vmla_qqq,\
1465+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1466+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1467+
1468+(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd_scalar"
1469+ "cortex_a8_neon_int_1,\
1470+ cortex_a8_neon_int_4,\
1471+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1472+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1473+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1474+ cortex_a8_neon_mla_qqq_8_16,\
1475+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1476+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1477+ cortex_a8_neon_fp_vmla_ddd,\
1478+ cortex_a8_neon_fp_vmla_qqq,\
1479+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1480+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1481+
1482+(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq"
1483+ "cortex_a8_neon_int_1,\
1484+ cortex_a8_neon_int_4,\
1485+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1486+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1487+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1488+ cortex_a8_neon_mla_qqq_8_16,\
1489+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1490+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1491+ cortex_a8_neon_fp_vmla_ddd,\
1492+ cortex_a8_neon_fp_vmla_qqq,\
1493+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1494+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1495+
1496+(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd"
1497+ "cortex_a8_neon_int_1,\
1498+ cortex_a8_neon_int_4,\
1499+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1500+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1501+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1502+ cortex_a8_neon_mla_qqq_8_16,\
1503+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1504+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1505+ cortex_a8_neon_fp_vmla_ddd,\
1506+ cortex_a8_neon_fp_vmla_qqq,\
1507+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1508+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1509+
1510+(define_bypass 5 "cortex_a8_neon_fp_vmul_qqd"
1511+ "cortex_a8_neon_int_1,\
1512+ cortex_a8_neon_int_4,\
1513+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1514+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1515+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1516+ cortex_a8_neon_mla_qqq_8_16,\
1517+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1518+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1519+ cortex_a8_neon_fp_vmla_ddd,\
1520+ cortex_a8_neon_fp_vmla_qqq,\
1521+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1522+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1523+
1524+(define_bypass 4 "cortex_a8_neon_fp_vmul_ddd"
1525+ "cortex_a8_neon_int_1,\
1526+ cortex_a8_neon_int_4,\
1527+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1528+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1529+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1530+ cortex_a8_neon_mla_qqq_8_16,\
1531+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1532+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1533+ cortex_a8_neon_fp_vmla_ddd,\
1534+ cortex_a8_neon_fp_vmla_qqq,\
1535+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1536+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1537+
1538+(define_bypass 4 "cortex_a8_neon_fp_vsum"
1539+ "cortex_a8_neon_int_1,\
1540+ cortex_a8_neon_int_4,\
1541+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1542+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1543+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1544+ cortex_a8_neon_mla_qqq_8_16,\
1545+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1546+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1547+ cortex_a8_neon_fp_vmla_ddd,\
1548+ cortex_a8_neon_fp_vmla_qqq,\
1549+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1550+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1551+
1552+(define_bypass 5 "cortex_a8_neon_fp_vadd_qqq_vabs_qq"
1553+ "cortex_a8_neon_int_1,\
1554+ cortex_a8_neon_int_4,\
1555+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1556+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1557+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1558+ cortex_a8_neon_mla_qqq_8_16,\
1559+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1560+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1561+ cortex_a8_neon_fp_vmla_ddd,\
1562+ cortex_a8_neon_fp_vmla_qqq,\
1563+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1564+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1565+
1566+(define_bypass 4 "cortex_a8_neon_fp_vadd_ddd_vabs_dd"
1567+ "cortex_a8_neon_int_1,\
1568+ cortex_a8_neon_int_4,\
1569+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1570+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1571+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1572+ cortex_a8_neon_mla_qqq_8_16,\
1573+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1574+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1575+ cortex_a8_neon_fp_vmla_ddd,\
1576+ cortex_a8_neon_fp_vmla_qqq,\
1577+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1578+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1579+
1580+(define_bypass 5 "cortex_a8_neon_vsra_vrsra"
1581+ "cortex_a8_neon_int_1,\
1582+ cortex_a8_neon_int_4,\
1583+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1584+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1585+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1586+ cortex_a8_neon_mla_qqq_8_16,\
1587+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1588+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1589+ cortex_a8_neon_fp_vmla_ddd,\
1590+ cortex_a8_neon_fp_vmla_qqq,\
1591+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1592+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1593+
1594+(define_bypass 4 "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq"
1595+ "cortex_a8_neon_int_1,\
1596+ cortex_a8_neon_int_4,\
1597+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1598+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1599+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1600+ cortex_a8_neon_mla_qqq_8_16,\
1601+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1602+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1603+ cortex_a8_neon_fp_vmla_ddd,\
1604+ cortex_a8_neon_fp_vmla_qqq,\
1605+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1606+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1607+
1608+(define_bypass 0 "cortex_a8_neon_vshl_ddd"
1609+ "cortex_a8_neon_int_1,\
1610+ cortex_a8_neon_int_4,\
1611+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1612+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1613+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1614+ cortex_a8_neon_mla_qqq_8_16,\
1615+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1616+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1617+ cortex_a8_neon_fp_vmla_ddd,\
1618+ cortex_a8_neon_fp_vmla_qqq,\
1619+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1620+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1621+
1622+(define_bypass 3 "cortex_a8_neon_shift_3"
1623+ "cortex_a8_neon_int_1,\
1624+ cortex_a8_neon_int_4,\
1625+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1626+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1627+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1628+ cortex_a8_neon_mla_qqq_8_16,\
1629+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1630+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1631+ cortex_a8_neon_fp_vmla_ddd,\
1632+ cortex_a8_neon_fp_vmla_qqq,\
1633+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1634+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1635+
1636+(define_bypass 3 "cortex_a8_neon_shift_2"
1637+ "cortex_a8_neon_int_1,\
1638+ cortex_a8_neon_int_4,\
1639+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1640+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1641+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1642+ cortex_a8_neon_mla_qqq_8_16,\
1643+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1644+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1645+ cortex_a8_neon_fp_vmla_ddd,\
1646+ cortex_a8_neon_fp_vmla_qqq,\
1647+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1648+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1649+
1650+(define_bypass 2 "cortex_a8_neon_shift_1"
1651+ "cortex_a8_neon_int_1,\
1652+ cortex_a8_neon_int_4,\
1653+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1654+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1655+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1656+ cortex_a8_neon_mla_qqq_8_16,\
1657+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1658+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1659+ cortex_a8_neon_fp_vmla_ddd,\
1660+ cortex_a8_neon_fp_vmla_qqq,\
1661+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1662+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1663+
1664+(define_bypass 5 "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"
1665+ "cortex_a8_neon_int_1,\
1666+ cortex_a8_neon_int_4,\
1667+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1668+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1669+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1670+ cortex_a8_neon_mla_qqq_8_16,\
1671+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1672+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1673+ cortex_a8_neon_fp_vmla_ddd,\
1674+ cortex_a8_neon_fp_vmla_qqq,\
1675+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1676+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1677+
1678+(define_bypass 8 "cortex_a8_neon_mul_qqd_32_scalar"
1679+ "cortex_a8_neon_int_1,\
1680+ cortex_a8_neon_int_4,\
1681+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1682+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1683+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1684+ cortex_a8_neon_mla_qqq_8_16,\
1685+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1686+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1687+ cortex_a8_neon_fp_vmla_ddd,\
1688+ cortex_a8_neon_fp_vmla_qqq,\
1689+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1690+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1691+
1692+(define_bypass 5 "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar"
1693+ "cortex_a8_neon_int_1,\
1694+ cortex_a8_neon_int_4,\
1695+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1696+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1697+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1698+ cortex_a8_neon_mla_qqq_8_16,\
1699+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1700+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1701+ cortex_a8_neon_fp_vmla_ddd,\
1702+ cortex_a8_neon_fp_vmla_qqq,\
1703+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1704+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1705+
1706+(define_bypass 8 "cortex_a8_neon_mla_qqq_32_qqd_32_scalar"
1707+ "cortex_a8_neon_int_1,\
1708+ cortex_a8_neon_int_4,\
1709+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1710+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1711+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1712+ cortex_a8_neon_mla_qqq_8_16,\
1713+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1714+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1715+ cortex_a8_neon_fp_vmla_ddd,\
1716+ cortex_a8_neon_fp_vmla_qqq,\
1717+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1718+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1719+
1720+(define_bypass 6 "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"
1721+ "cortex_a8_neon_int_1,\
1722+ cortex_a8_neon_int_4,\
1723+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1724+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1725+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1726+ cortex_a8_neon_mla_qqq_8_16,\
1727+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1728+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1729+ cortex_a8_neon_fp_vmla_ddd,\
1730+ cortex_a8_neon_fp_vmla_qqq,\
1731+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1732+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1733+
1734+(define_bypass 6 "cortex_a8_neon_mla_qqq_8_16"
1735+ "cortex_a8_neon_int_1,\
1736+ cortex_a8_neon_int_4,\
1737+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1738+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1739+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1740+ cortex_a8_neon_mla_qqq_8_16,\
1741+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1742+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1743+ cortex_a8_neon_fp_vmla_ddd,\
1744+ cortex_a8_neon_fp_vmla_qqq,\
1745+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1746+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1747+
1748+(define_bypass 5 "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"
1749+ "cortex_a8_neon_int_1,\
1750+ cortex_a8_neon_int_4,\
1751+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1752+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1753+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1754+ cortex_a8_neon_mla_qqq_8_16,\
1755+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1756+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1757+ cortex_a8_neon_fp_vmla_ddd,\
1758+ cortex_a8_neon_fp_vmla_qqq,\
1759+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1760+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1761+
1762+(define_bypass 6 "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"
1763+ "cortex_a8_neon_int_1,\
1764+ cortex_a8_neon_int_4,\
1765+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1766+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1767+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1768+ cortex_a8_neon_mla_qqq_8_16,\
1769+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1770+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1771+ cortex_a8_neon_fp_vmla_ddd,\
1772+ cortex_a8_neon_fp_vmla_qqq,\
1773+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1774+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1775+
1776+(define_bypass 6 "cortex_a8_neon_mul_qqq_8_16_32_ddd_32"
1777+ "cortex_a8_neon_int_1,\
1778+ cortex_a8_neon_int_4,\
1779+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1780+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1781+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1782+ cortex_a8_neon_mla_qqq_8_16,\
1783+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1784+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1785+ cortex_a8_neon_fp_vmla_ddd,\
1786+ cortex_a8_neon_fp_vmla_qqq,\
1787+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1788+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1789+
1790+(define_bypass 5 "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"
1791+ "cortex_a8_neon_int_1,\
1792+ cortex_a8_neon_int_4,\
1793+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1794+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1795+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1796+ cortex_a8_neon_mla_qqq_8_16,\
1797+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1798+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1799+ cortex_a8_neon_fp_vmla_ddd,\
1800+ cortex_a8_neon_fp_vmla_qqq,\
1801+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1802+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1803+
1804+(define_bypass 5 "cortex_a8_neon_vsma"
1805+ "cortex_a8_neon_int_1,\
1806+ cortex_a8_neon_int_4,\
1807+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1808+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1809+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1810+ cortex_a8_neon_mla_qqq_8_16,\
1811+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1812+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1813+ cortex_a8_neon_fp_vmla_ddd,\
1814+ cortex_a8_neon_fp_vmla_qqq,\
1815+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1816+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1817+
1818+(define_bypass 6 "cortex_a8_neon_vaba_qqq"
1819+ "cortex_a8_neon_int_1,\
1820+ cortex_a8_neon_int_4,\
1821+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1822+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1823+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1824+ cortex_a8_neon_mla_qqq_8_16,\
1825+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1826+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1827+ cortex_a8_neon_fp_vmla_ddd,\
1828+ cortex_a8_neon_fp_vmla_qqq,\
1829+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1830+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1831+
1832+(define_bypass 5 "cortex_a8_neon_vaba"
1833+ "cortex_a8_neon_int_1,\
1834+ cortex_a8_neon_int_4,\
1835+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1836+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1837+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1838+ cortex_a8_neon_mla_qqq_8_16,\
1839+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1840+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1841+ cortex_a8_neon_fp_vmla_ddd,\
1842+ cortex_a8_neon_fp_vmla_qqq,\
1843+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1844+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1845+
1846+(define_bypass 2 "cortex_a8_neon_vmov"
1847+ "cortex_a8_neon_int_1,\
1848+ cortex_a8_neon_int_4,\
1849+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1850+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1851+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1852+ cortex_a8_neon_mla_qqq_8_16,\
1853+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1854+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1855+ cortex_a8_neon_fp_vmla_ddd,\
1856+ cortex_a8_neon_fp_vmla_qqq,\
1857+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1858+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1859+
1860+(define_bypass 3 "cortex_a8_neon_vqneg_vqabs"
1861+ "cortex_a8_neon_int_1,\
1862+ cortex_a8_neon_int_4,\
1863+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1864+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1865+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1866+ cortex_a8_neon_mla_qqq_8_16,\
1867+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1868+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1869+ cortex_a8_neon_fp_vmla_ddd,\
1870+ cortex_a8_neon_fp_vmla_qqq,\
1871+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1872+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1873+
1874+(define_bypass 3 "cortex_a8_neon_int_5"
1875+ "cortex_a8_neon_int_1,\
1876+ cortex_a8_neon_int_4,\
1877+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1878+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1879+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1880+ cortex_a8_neon_mla_qqq_8_16,\
1881+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1882+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1883+ cortex_a8_neon_fp_vmla_ddd,\
1884+ cortex_a8_neon_fp_vmla_qqq,\
1885+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1886+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1887+
1888+(define_bypass 3 "cortex_a8_neon_int_4"
1889+ "cortex_a8_neon_int_1,\
1890+ cortex_a8_neon_int_4,\
1891+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1892+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1893+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1894+ cortex_a8_neon_mla_qqq_8_16,\
1895+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1896+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1897+ cortex_a8_neon_fp_vmla_ddd,\
1898+ cortex_a8_neon_fp_vmla_qqq,\
1899+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1900+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1901+
1902+(define_bypass 2 "cortex_a8_neon_int_3"
1903+ "cortex_a8_neon_int_1,\
1904+ cortex_a8_neon_int_4,\
1905+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1906+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1907+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1908+ cortex_a8_neon_mla_qqq_8_16,\
1909+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1910+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1911+ cortex_a8_neon_fp_vmla_ddd,\
1912+ cortex_a8_neon_fp_vmla_qqq,\
1913+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1914+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1915+
1916+(define_bypass 2 "cortex_a8_neon_int_2"
1917+ "cortex_a8_neon_int_1,\
1918+ cortex_a8_neon_int_4,\
1919+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1920+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1921+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1922+ cortex_a8_neon_mla_qqq_8_16,\
1923+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1924+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1925+ cortex_a8_neon_fp_vmla_ddd,\
1926+ cortex_a8_neon_fp_vmla_qqq,\
1927+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1928+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1929+
1930+(define_bypass 2 "cortex_a8_neon_int_1"
1931+ "cortex_a8_neon_int_1,\
1932+ cortex_a8_neon_int_4,\
1933+ cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
1934+ cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\
1935+ cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
1936+ cortex_a8_neon_mla_qqq_8_16,\
1937+ cortex_a8_neon_fp_vadd_ddd_vabs_dd,\
1938+ cortex_a8_neon_fp_vadd_qqq_vabs_qq,\
1939+ cortex_a8_neon_fp_vmla_ddd,\
1940+ cortex_a8_neon_fp_vmla_qqq,\
1941+ cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\
1942+ cortex_a8_neon_fp_vrecps_vrsqrts_qqq")
1943
1944
1945=== added file 'gcc/config/arm/cortex-a9-neon.md'
1946--- old/gcc/config/arm/cortex-a9-neon.md 1970-01-01 00:00:00 +0000
1947+++ new/gcc/config/arm/cortex-a9-neon.md 2010-09-16 09:47:44 +0000
1948@@ -0,0 +1,1237 @@
1949+;; ARM Cortex-A9 pipeline description
1950+;; Copyright (C) 2010 Free Software Foundation, Inc.
1951+;;
1952+;; Neon pipeline description contributed by ARM Ltd.
1953+;;
1954+;; This file is part of GCC.
1955+;;
1956+;; GCC is free software; you can redistribute it and/or modify it
1957+;; under the terms of the GNU General Public License as published by
1958+;; the Free Software Foundation; either version 3, or (at your option)
1959+;; any later version.
1960+;;
1961+;; GCC is distributed in the hope that it will be useful, but
1962+;; WITHOUT ANY WARRANTY; without even the implied warranty of
1963+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1964+;; General Public License for more details.
1965+;;
1966+;; You should have received a copy of the GNU General Public License
1967+;; along with GCC; see the file COPYING3. If not see
1968+;; <http://www.gnu.org/licenses/>.
1969+
1970+
1971+(define_automaton "cortex_a9_neon")
1972+
1973+;; Only one instruction can be issued per cycle.
1974+(define_cpu_unit "cortex_a9_neon_issue_perm" "cortex_a9_neon")
1975+
1976+;; Only one data-processing instruction can be issued per cycle.
1977+(define_cpu_unit "cortex_a9_neon_issue_dp" "cortex_a9_neon")
1978+
1979+;; We need a special mutual exclusion (to be used in addition to
1980+;; cortex_a9_neon_issue_dp) for the case when an instruction such as
1981+;; vmla.f is forwarded from E5 of the floating-point multiply pipeline to
1982+;; E2 of the floating-point add pipeline. On the cycle previous to that
1983+;; forward we must prevent issue of any instruction to the floating-point
1984+;; add pipeline, but still allow issue of a data-processing instruction
1985+;; to any of the other pipelines.
1986+(define_cpu_unit "cortex_a9_neon_issue_fadd" "cortex_a9_neon")
1987+(define_cpu_unit "cortex_a9_neon_mcr" "cortex_a9_neon")
1988+
1989+
1990+;; Patterns of reservation.
1991+;; We model the NEON issue units as running in parallel with the core ones.
1992+;; We assume that multi-cycle NEON instructions get decomposed into
1993+;; micro-ops as they are issued into the NEON pipeline.
1994+
1995+(define_reservation "cortex_a9_neon_dp"
1996+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp")
1997+(define_reservation "cortex_a9_neon_dp_2"
1998+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
1999+ cortex_a9_neon_issue_dp")
2000+(define_reservation "cortex_a9_neon_dp_4"
2001+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
2002+ cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\
2003+ cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\
2004+ cortex_a9_neon_issue_dp")
2005+
2006+(define_reservation "cortex_a9_neon_fadd"
2007+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp + \
2008+ cortex_a9_neon_issue_fadd")
2009+(define_reservation "cortex_a9_neon_fadd_2"
2010+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
2011+ cortex_a9_neon_issue_fadd,\
2012+ cortex_a9_neon_issue_dp")
2013+
2014+(define_reservation "cortex_a9_neon_perm"
2015+ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm")
2016+(define_reservation "cortex_a9_neon_perm_2"
2017+ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm, \
2018+ cortex_a9_neon_issue_perm")
2019+(define_reservation "cortex_a9_neon_perm_3"
2020+ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
2021+ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
2022+ cortex_a9_neon_issue_perm")
2023+
2024+(define_reservation "cortex_a9_neon_ls"
2025+ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm+cortex_a9_ls")
2026+(define_reservation "cortex_a9_neon_ls_2"
2027+ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
2028+ cortex_a9_neon_issue_perm")
2029+(define_reservation "cortex_a9_neon_ls_3"
2030+ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
2031+ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
2032+ cortex_a9_neon_issue_perm")
2033+(define_reservation "cortex_a9_neon_ls_4"
2034+ "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\
2035+ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
2036+ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
2037+ cortex_a9_neon_issue_perm")
2038+(define_reservation "cortex_a9_neon_ls_5"
2039+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_perm,\
2040+ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
2041+ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
2042+ cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\
2043+ cortex_a9_neon_issue_perm")
2044+
2045+(define_reservation "cortex_a9_neon_fmul_then_fadd"
2046+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
2047+ nothing*3,\
2048+ cortex_a9_neon_issue_fadd")
2049+(define_reservation "cortex_a9_neon_fmul_then_fadd_2"
2050+ "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\
2051+ cortex_a9_neon_issue_dp,\
2052+ nothing*2,\
2053+ cortex_a9_neon_issue_fadd,\
2054+ cortex_a9_neon_issue_fadd")
2055+
2056+
2057+;; NEON -> core transfers.
2058+(define_insn_reservation "ca9_neon_mrc" 1
2059+ (and (eq_attr "tune" "cortexa9")
2060+ (eq_attr "neon_type" "neon_mrc"))
2061+ "ca9_issue_vfp_neon + cortex_a9_neon_mcr")
2062+
2063+(define_insn_reservation "ca9_neon_mrrc" 1
2064+ (and (eq_attr "tune" "cortexa9")
2065+ (eq_attr "neon_type" "neon_mrrc"))
2066+ "ca9_issue_vfp_neon + cortex_a9_neon_mcr")
2067+
2068+;; The remainder of this file is auto-generated by neon-schedgen.
2069+
2070+;; Instructions using this reservation read their source operands at N2, and
2071+;; produce a result at N3.
2072+(define_insn_reservation "cortex_a9_neon_int_1" 3
2073+ (and (eq_attr "tune" "cortexa9")
2074+ (eq_attr "neon_type" "neon_int_1"))
2075+ "cortex_a9_neon_dp")
2076+
2077+;; Instructions using this reservation read their (D|Q)m operands at N1,
2078+;; their (D|Q)n operands at N2, and produce a result at N3.
2079+(define_insn_reservation "cortex_a9_neon_int_2" 3
2080+ (and (eq_attr "tune" "cortexa9")
2081+ (eq_attr "neon_type" "neon_int_2"))
2082+ "cortex_a9_neon_dp")
2083+
2084+;; Instructions using this reservation read their source operands at N1, and
2085+;; produce a result at N3.
2086+(define_insn_reservation "cortex_a9_neon_int_3" 3
2087+ (and (eq_attr "tune" "cortexa9")
2088+ (eq_attr "neon_type" "neon_int_3"))
2089+ "cortex_a9_neon_dp")
2090+
2091+;; Instructions using this reservation read their source operands at N2, and
2092+;; produce a result at N4.
2093+(define_insn_reservation "cortex_a9_neon_int_4" 4
2094+ (and (eq_attr "tune" "cortexa9")
2095+ (eq_attr "neon_type" "neon_int_4"))
2096+ "cortex_a9_neon_dp")
2097+
2098+;; Instructions using this reservation read their (D|Q)m operands at N1,
2099+;; their (D|Q)n operands at N2, and produce a result at N4.
2100+(define_insn_reservation "cortex_a9_neon_int_5" 4
2101+ (and (eq_attr "tune" "cortexa9")
2102+ (eq_attr "neon_type" "neon_int_5"))
2103+ "cortex_a9_neon_dp")
2104+
2105+;; Instructions using this reservation read their source operands at N1, and
2106+;; produce a result at N4.
2107+(define_insn_reservation "cortex_a9_neon_vqneg_vqabs" 4
2108+ (and (eq_attr "tune" "cortexa9")
2109+ (eq_attr "neon_type" "neon_vqneg_vqabs"))
2110+ "cortex_a9_neon_dp")
2111+
2112+;; Instructions using this reservation produce a result at N3.
2113+(define_insn_reservation "cortex_a9_neon_vmov" 3
2114+ (and (eq_attr "tune" "cortexa9")
2115+ (eq_attr "neon_type" "neon_vmov"))
2116+ "cortex_a9_neon_dp")
2117+
2118+;; Instructions using this reservation read their (D|Q)n operands at N2,
2119+;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
2120+;; produce a result at N6.
2121+(define_insn_reservation "cortex_a9_neon_vaba" 6
2122+ (and (eq_attr "tune" "cortexa9")
2123+ (eq_attr "neon_type" "neon_vaba"))
2124+ "cortex_a9_neon_dp")
2125+
2126+;; Instructions using this reservation read their (D|Q)n operands at N2,
2127+;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
2128+;; produce a result at N6 on cycle 2.
2129+(define_insn_reservation "cortex_a9_neon_vaba_qqq" 7
2130+ (and (eq_attr "tune" "cortexa9")
2131+ (eq_attr "neon_type" "neon_vaba_qqq"))
2132+ "cortex_a9_neon_dp_2")
2133+
2134+;; Instructions using this reservation read their (D|Q)m operands at N1,
2135+;; their (D|Q)d operands at N3, and produce a result at N6.
2136+(define_insn_reservation "cortex_a9_neon_vsma" 6
2137+ (and (eq_attr "tune" "cortexa9")
2138+ (eq_attr "neon_type" "neon_vsma"))
2139+ "cortex_a9_neon_dp")
2140+
2141+;; Instructions using this reservation read their source operands at N2, and
2142+;; produce a result at N6.
2143+(define_insn_reservation "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6
2144+ (and (eq_attr "tune" "cortexa9")
2145+ (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"))
2146+ "cortex_a9_neon_dp")
2147+
2148+;; Instructions using this reservation read their source operands at N2, and
2149+;; produce a result at N6 on cycle 2.
2150+(define_insn_reservation "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" 7
2151+ (and (eq_attr "tune" "cortexa9")
2152+ (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32"))
2153+ "cortex_a9_neon_dp_2")
2154+
2155+;; Instructions using this reservation read their (D|Q)n operands at N2,
2156+;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
2157+(define_insn_reservation "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7
2158+ (and (eq_attr "tune" "cortexa9")
2159+ (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))
2160+ "cortex_a9_neon_dp_2")
2161+
2162+;; Instructions using this reservation read their (D|Q)n operands at N2,
2163+;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
2164+;; produce a result at N6.
2165+(define_insn_reservation "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6
2166+ (and (eq_attr "tune" "cortexa9")
2167+ (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"))
2168+ "cortex_a9_neon_dp")
2169+
2170+;; Instructions using this reservation read their (D|Q)n operands at N2,
2171+;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
2172+;; produce a result at N6 on cycle 2.
2173+(define_insn_reservation "cortex_a9_neon_mla_qqq_8_16" 7
2174+ (and (eq_attr "tune" "cortexa9")
2175+ (eq_attr "neon_type" "neon_mla_qqq_8_16"))
2176+ "cortex_a9_neon_dp_2")
2177+
2178+;; Instructions using this reservation read their (D|Q)n operands at N2,
2179+;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
2180+;; produce a result at N6 on cycle 2.
2181+(define_insn_reservation "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7
2182+ (and (eq_attr "tune" "cortexa9")
2183+ (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
2184+ "cortex_a9_neon_dp_2")
2185+
2186+;; Instructions using this reservation read their (D|Q)n operands at N2,
2187+;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
2188+;; produce a result at N6 on cycle 4.
2189+(define_insn_reservation "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" 9
2190+ (and (eq_attr "tune" "cortexa9")
2191+ (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar"))
2192+ "cortex_a9_neon_dp_4")
2193+
2194+;; Instructions using this reservation read their (D|Q)n operands at N2,
2195+;; their (D|Q)m operands at N1, and produce a result at N6.
2196+(define_insn_reservation "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" 6
2197+ (and (eq_attr "tune" "cortexa9")
2198+ (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar"))
2199+ "cortex_a9_neon_dp")
2200+
2201+;; Instructions using this reservation read their (D|Q)n operands at N2,
2202+;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4.
2203+(define_insn_reservation "cortex_a9_neon_mul_qqd_32_scalar" 9
2204+ (and (eq_attr "tune" "cortexa9")
2205+ (eq_attr "neon_type" "neon_mul_qqd_32_scalar"))
2206+ "cortex_a9_neon_dp_4")
2207+
2208+;; Instructions using this reservation read their (D|Q)n operands at N2,
2209+;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
2210+;; produce a result at N6.
2211+(define_insn_reservation "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6
2212+ (and (eq_attr "tune" "cortexa9")
2213+ (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"))
2214+ "cortex_a9_neon_dp")
2215+
2216+;; Instructions using this reservation read their source operands at N1, and
2217+;; produce a result at N3.
2218+(define_insn_reservation "cortex_a9_neon_shift_1" 3
2219+ (and (eq_attr "tune" "cortexa9")
2220+ (eq_attr "neon_type" "neon_shift_1"))
2221+ "cortex_a9_neon_dp")
2222+
2223+;; Instructions using this reservation read their source operands at N1, and
2224+;; produce a result at N4.
2225+(define_insn_reservation "cortex_a9_neon_shift_2" 4
2226+ (and (eq_attr "tune" "cortexa9")
2227+ (eq_attr "neon_type" "neon_shift_2"))
2228+ "cortex_a9_neon_dp")
2229+
2230+;; Instructions using this reservation read their source operands at N1, and
2231+;; produce a result at N3 on cycle 2.
2232+(define_insn_reservation "cortex_a9_neon_shift_3" 4
2233+ (and (eq_attr "tune" "cortexa9")
2234+ (eq_attr "neon_type" "neon_shift_3"))
2235+ "cortex_a9_neon_dp_2")
2236+
2237+;; Instructions using this reservation read their source operands at N1, and
2238+;; produce a result at N1.
2239+(define_insn_reservation "cortex_a9_neon_vshl_ddd" 1
2240+ (and (eq_attr "tune" "cortexa9")
2241+ (eq_attr "neon_type" "neon_vshl_ddd"))
2242+ "cortex_a9_neon_dp")
2243+
2244+;; Instructions using this reservation read their source operands at N1, and
2245+;; produce a result at N4 on cycle 2.
2246+(define_insn_reservation "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" 5
2247+ (and (eq_attr "tune" "cortexa9")
2248+ (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq"))
2249+ "cortex_a9_neon_dp_2")
2250+
2251+;; Instructions using this reservation read their (D|Q)m operands at N1,
2252+;; their (D|Q)d operands at N3, and produce a result at N6.
2253+(define_insn_reservation "cortex_a9_neon_vsra_vrsra" 6
2254+ (and (eq_attr "tune" "cortexa9")
2255+ (eq_attr "neon_type" "neon_vsra_vrsra"))
2256+ "cortex_a9_neon_dp")
2257+
2258+;; Instructions using this reservation read their source operands at N2, and
2259+;; produce a result at N5.
2260+(define_insn_reservation "cortex_a9_neon_fp_vadd_ddd_vabs_dd" 5
2261+ (and (eq_attr "tune" "cortexa9")
2262+ (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd"))
2263+ "cortex_a9_neon_fadd")
2264+
2265+;; Instructions using this reservation read their source operands at N2, and
2266+;; produce a result at N5 on cycle 2.
2267+(define_insn_reservation "cortex_a9_neon_fp_vadd_qqq_vabs_qq" 6
2268+ (and (eq_attr "tune" "cortexa9")
2269+ (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq"))
2270+ "cortex_a9_neon_fadd_2")
2271+
2272+;; Instructions using this reservation read their source operands at N1, and
2273+;; produce a result at N5.
2274+(define_insn_reservation "cortex_a9_neon_fp_vsum" 5
2275+ (and (eq_attr "tune" "cortexa9")
2276+ (eq_attr "neon_type" "neon_fp_vsum"))
2277+ "cortex_a9_neon_fadd")
2278+
2279+;; Instructions using this reservation read their (D|Q)n operands at N2,
2280+;; their (D|Q)m operands at N1, and produce a result at N5.
2281+(define_insn_reservation "cortex_a9_neon_fp_vmul_ddd" 5
2282+ (and (eq_attr "tune" "cortexa9")
2283+ (eq_attr "neon_type" "neon_fp_vmul_ddd"))
2284+ "cortex_a9_neon_dp")
2285+
2286+;; Instructions using this reservation read their (D|Q)n operands at N2,
2287+;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2.
2288+(define_insn_reservation "cortex_a9_neon_fp_vmul_qqd" 6
2289+ (and (eq_attr "tune" "cortexa9")
2290+ (eq_attr "neon_type" "neon_fp_vmul_qqd"))
2291+ "cortex_a9_neon_dp_2")
2292+
2293+;; Instructions using this reservation read their (D|Q)n operands at N2,
2294+;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
2295+;; produce a result at N9.
2296+(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd" 9
2297+ (and (eq_attr "tune" "cortexa9")
2298+ (eq_attr "neon_type" "neon_fp_vmla_ddd"))
2299+ "cortex_a9_neon_fmul_then_fadd")
2300+
2301+;; Instructions using this reservation read their (D|Q)n operands at N2,
2302+;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and
2303+;; produce a result at N9 on cycle 2.
2304+(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq" 10
2305+ (and (eq_attr "tune" "cortexa9")
2306+ (eq_attr "neon_type" "neon_fp_vmla_qqq"))
2307+ "cortex_a9_neon_fmul_then_fadd_2")
2308+
2309+;; Instructions using this reservation read their (D|Q)n operands at N2,
2310+;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
2311+;; produce a result at N9.
2312+(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd_scalar" 9
2313+ (and (eq_attr "tune" "cortexa9")
2314+ (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar"))
2315+ "cortex_a9_neon_fmul_then_fadd")
2316+
2317+;; Instructions using this reservation read their (D|Q)n operands at N2,
2318+;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and
2319+;; produce a result at N9 on cycle 2.
2320+(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq_scalar" 10
2321+ (and (eq_attr "tune" "cortexa9")
2322+ (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar"))
2323+ "cortex_a9_neon_fmul_then_fadd_2")
2324+
2325+;; Instructions using this reservation read their source operands at N2, and
2326+;; produce a result at N9.
2327+(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" 9
2328+ (and (eq_attr "tune" "cortexa9")
2329+ (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd"))
2330+ "cortex_a9_neon_fmul_then_fadd")
2331+
2332+;; Instructions using this reservation read their source operands at N2, and
2333+;; produce a result at N9 on cycle 2.
2334+(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" 10
2335+ (and (eq_attr "tune" "cortexa9")
2336+ (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq"))
2337+ "cortex_a9_neon_fmul_then_fadd_2")
2338+
2339+;; Instructions using this reservation read their source operands at N1, and
2340+;; produce a result at N2.
2341+(define_insn_reservation "cortex_a9_neon_bp_simple" 2
2342+ (and (eq_attr "tune" "cortexa9")
2343+ (eq_attr "neon_type" "neon_bp_simple"))
2344+ "cortex_a9_neon_perm")
2345+
2346+;; Instructions using this reservation read their source operands at N1, and
2347+;; produce a result at N2 on cycle 2.
2348+(define_insn_reservation "cortex_a9_neon_bp_2cycle" 3
2349+ (and (eq_attr "tune" "cortexa9")
2350+ (eq_attr "neon_type" "neon_bp_2cycle"))
2351+ "cortex_a9_neon_perm_2")
2352+
2353+;; Instructions using this reservation read their source operands at N1, and
2354+;; produce a result at N2 on cycle 3.
2355+(define_insn_reservation "cortex_a9_neon_bp_3cycle" 4
2356+ (and (eq_attr "tune" "cortexa9")
2357+ (eq_attr "neon_type" "neon_bp_3cycle"))
2358+ "cortex_a9_neon_perm_3")
2359+
2360+;; Instructions using this reservation produce a result at N1.
2361+(define_insn_reservation "cortex_a9_neon_ldr" 1
2362+ (and (eq_attr "tune" "cortexa9")
2363+ (eq_attr "neon_type" "neon_ldr"))
2364+ "cortex_a9_neon_ls")
2365+
2366+;; Instructions using this reservation read their source operands at N1.
2367+(define_insn_reservation "cortex_a9_neon_str" 0
2368+ (and (eq_attr "tune" "cortexa9")
2369+ (eq_attr "neon_type" "neon_str"))
2370+ "cortex_a9_neon_ls")
2371+
2372+;; Instructions using this reservation produce a result at N1 on cycle 2.
2373+(define_insn_reservation "cortex_a9_neon_vld1_1_2_regs" 2
2374+ (and (eq_attr "tune" "cortexa9")
2375+ (eq_attr "neon_type" "neon_vld1_1_2_regs"))
2376+ "cortex_a9_neon_ls_2")
2377+
2378+;; Instructions using this reservation produce a result at N1 on cycle 3.
2379+(define_insn_reservation "cortex_a9_neon_vld1_3_4_regs" 3
2380+ (and (eq_attr "tune" "cortexa9")
2381+ (eq_attr "neon_type" "neon_vld1_3_4_regs"))
2382+ "cortex_a9_neon_ls_3")
2383+
2384+;; Instructions using this reservation produce a result at N2 on cycle 2.
2385+(define_insn_reservation "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" 3
2386+ (and (eq_attr "tune" "cortexa9")
2387+ (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes"))
2388+ "cortex_a9_neon_ls_2")
2389+
2390+;; Instructions using this reservation produce a result at N2 on cycle 3.
2391+(define_insn_reservation "cortex_a9_neon_vld2_4_regs" 4
2392+ (and (eq_attr "tune" "cortexa9")
2393+ (eq_attr "neon_type" "neon_vld2_4_regs"))
2394+ "cortex_a9_neon_ls_3")
2395+
2396+;; Instructions using this reservation produce a result at N2 on cycle 4.
2397+(define_insn_reservation "cortex_a9_neon_vld3_vld4" 5
2398+ (and (eq_attr "tune" "cortexa9")
2399+ (eq_attr "neon_type" "neon_vld3_vld4"))
2400+ "cortex_a9_neon_ls_4")
2401+
2402+;; Instructions using this reservation read their source operands at N1.
2403+(define_insn_reservation "cortex_a9_neon_vst1_1_2_regs_vst2_2_regs" 0
2404+ (and (eq_attr "tune" "cortexa9")
2405+ (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs"))
2406+ "cortex_a9_neon_ls_2")
2407+
2408+;; Instructions using this reservation read their source operands at N1.
2409+(define_insn_reservation "cortex_a9_neon_vst1_3_4_regs" 0
2410+ (and (eq_attr "tune" "cortexa9")
2411+ (eq_attr "neon_type" "neon_vst1_3_4_regs"))
2412+ "cortex_a9_neon_ls_3")
2413+
2414+;; Instructions using this reservation read their source operands at N1.
2415+(define_insn_reservation "cortex_a9_neon_vst2_4_regs_vst3_vst4" 0
2416+ (and (eq_attr "tune" "cortexa9")
2417+ (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4"))
2418+ "cortex_a9_neon_ls_4")
2419+
2420+;; Instructions using this reservation read their source operands at N1.
2421+(define_insn_reservation "cortex_a9_neon_vst3_vst4" 0
2422+ (and (eq_attr "tune" "cortexa9")
2423+ (eq_attr "neon_type" "neon_vst3_vst4"))
2424+ "cortex_a9_neon_ls_4")
2425+
2426+;; Instructions using this reservation read their source operands at N1, and
2427+;; produce a result at N2 on cycle 3.
2428+(define_insn_reservation "cortex_a9_neon_vld1_vld2_lane" 4
2429+ (and (eq_attr "tune" "cortexa9")
2430+ (eq_attr "neon_type" "neon_vld1_vld2_lane"))
2431+ "cortex_a9_neon_ls_3")
2432+
2433+;; Instructions using this reservation read their source operands at N1, and
2434+;; produce a result at N2 on cycle 5.
2435+(define_insn_reservation "cortex_a9_neon_vld3_vld4_lane" 6
2436+ (and (eq_attr "tune" "cortexa9")
2437+ (eq_attr "neon_type" "neon_vld3_vld4_lane"))
2438+ "cortex_a9_neon_ls_5")
2439+
2440+;; Instructions using this reservation read their source operands at N1.
2441+(define_insn_reservation "cortex_a9_neon_vst1_vst2_lane" 0
2442+ (and (eq_attr "tune" "cortexa9")
2443+ (eq_attr "neon_type" "neon_vst1_vst2_lane"))
2444+ "cortex_a9_neon_ls_2")
2445+
2446+;; Instructions using this reservation read their source operands at N1.
2447+(define_insn_reservation "cortex_a9_neon_vst3_vst4_lane" 0
2448+ (and (eq_attr "tune" "cortexa9")
2449+ (eq_attr "neon_type" "neon_vst3_vst4_lane"))
2450+ "cortex_a9_neon_ls_3")
2451+
2452+;; Instructions using this reservation produce a result at N2 on cycle 2.
2453+(define_insn_reservation "cortex_a9_neon_vld3_vld4_all_lanes" 3
2454+ (and (eq_attr "tune" "cortexa9")
2455+ (eq_attr "neon_type" "neon_vld3_vld4_all_lanes"))
2456+ "cortex_a9_neon_ls_3")
2457+
2458+;; Instructions using this reservation produce a result at N2.
2459+(define_insn_reservation "cortex_a9_neon_mcr" 2
2460+ (and (eq_attr "tune" "cortexa9")
2461+ (eq_attr "neon_type" "neon_mcr"))
2462+ "cortex_a9_neon_perm")
2463+
2464+;; Instructions using this reservation produce a result at N2.
2465+(define_insn_reservation "cortex_a9_neon_mcr_2_mcrr" 2
2466+ (and (eq_attr "tune" "cortexa9")
2467+ (eq_attr "neon_type" "neon_mcr_2_mcrr"))
2468+ "cortex_a9_neon_perm_2")
2469+
2470+;; Exceptions to the default latencies.
2471+
2472+(define_bypass 1 "cortex_a9_neon_mcr_2_mcrr"
2473+ "cortex_a9_neon_int_1,\
2474+ cortex_a9_neon_int_4,\
2475+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2476+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2477+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2478+ cortex_a9_neon_mla_qqq_8_16,\
2479+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2480+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2481+ cortex_a9_neon_fp_vmla_ddd,\
2482+ cortex_a9_neon_fp_vmla_qqq,\
2483+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2484+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2485+
2486+(define_bypass 1 "cortex_a9_neon_mcr"
2487+ "cortex_a9_neon_int_1,\
2488+ cortex_a9_neon_int_4,\
2489+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2490+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2491+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2492+ cortex_a9_neon_mla_qqq_8_16,\
2493+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2494+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2495+ cortex_a9_neon_fp_vmla_ddd,\
2496+ cortex_a9_neon_fp_vmla_qqq,\
2497+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2498+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2499+
2500+(define_bypass 2 "cortex_a9_neon_vld3_vld4_all_lanes"
2501+ "cortex_a9_neon_int_1,\
2502+ cortex_a9_neon_int_4,\
2503+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2504+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2505+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2506+ cortex_a9_neon_mla_qqq_8_16,\
2507+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2508+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2509+ cortex_a9_neon_fp_vmla_ddd,\
2510+ cortex_a9_neon_fp_vmla_qqq,\
2511+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2512+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2513+
2514+(define_bypass 5 "cortex_a9_neon_vld3_vld4_lane"
2515+ "cortex_a9_neon_int_1,\
2516+ cortex_a9_neon_int_4,\
2517+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2518+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2519+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2520+ cortex_a9_neon_mla_qqq_8_16,\
2521+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2522+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2523+ cortex_a9_neon_fp_vmla_ddd,\
2524+ cortex_a9_neon_fp_vmla_qqq,\
2525+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2526+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2527+
2528+(define_bypass 3 "cortex_a9_neon_vld1_vld2_lane"
2529+ "cortex_a9_neon_int_1,\
2530+ cortex_a9_neon_int_4,\
2531+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2532+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2533+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2534+ cortex_a9_neon_mla_qqq_8_16,\
2535+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2536+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2537+ cortex_a9_neon_fp_vmla_ddd,\
2538+ cortex_a9_neon_fp_vmla_qqq,\
2539+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2540+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2541+
2542+(define_bypass 4 "cortex_a9_neon_vld3_vld4"
2543+ "cortex_a9_neon_int_1,\
2544+ cortex_a9_neon_int_4,\
2545+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2546+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2547+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2548+ cortex_a9_neon_mla_qqq_8_16,\
2549+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2550+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2551+ cortex_a9_neon_fp_vmla_ddd,\
2552+ cortex_a9_neon_fp_vmla_qqq,\
2553+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2554+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2555+
2556+(define_bypass 3 "cortex_a9_neon_vld2_4_regs"
2557+ "cortex_a9_neon_int_1,\
2558+ cortex_a9_neon_int_4,\
2559+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2560+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2561+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2562+ cortex_a9_neon_mla_qqq_8_16,\
2563+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2564+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2565+ cortex_a9_neon_fp_vmla_ddd,\
2566+ cortex_a9_neon_fp_vmla_qqq,\
2567+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2568+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2569+
2570+(define_bypass 2 "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes"
2571+ "cortex_a9_neon_int_1,\
2572+ cortex_a9_neon_int_4,\
2573+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2574+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2575+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2576+ cortex_a9_neon_mla_qqq_8_16,\
2577+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2578+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2579+ cortex_a9_neon_fp_vmla_ddd,\
2580+ cortex_a9_neon_fp_vmla_qqq,\
2581+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2582+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2583+
2584+(define_bypass 2 "cortex_a9_neon_vld1_3_4_regs"
2585+ "cortex_a9_neon_int_1,\
2586+ cortex_a9_neon_int_4,\
2587+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2588+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2589+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2590+ cortex_a9_neon_mla_qqq_8_16,\
2591+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2592+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2593+ cortex_a9_neon_fp_vmla_ddd,\
2594+ cortex_a9_neon_fp_vmla_qqq,\
2595+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2596+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2597+
2598+(define_bypass 1 "cortex_a9_neon_vld1_1_2_regs"
2599+ "cortex_a9_neon_int_1,\
2600+ cortex_a9_neon_int_4,\
2601+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2602+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2603+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2604+ cortex_a9_neon_mla_qqq_8_16,\
2605+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2606+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2607+ cortex_a9_neon_fp_vmla_ddd,\
2608+ cortex_a9_neon_fp_vmla_qqq,\
2609+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2610+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2611+
2612+(define_bypass 0 "cortex_a9_neon_ldr"
2613+ "cortex_a9_neon_int_1,\
2614+ cortex_a9_neon_int_4,\
2615+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2616+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2617+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2618+ cortex_a9_neon_mla_qqq_8_16,\
2619+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2620+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2621+ cortex_a9_neon_fp_vmla_ddd,\
2622+ cortex_a9_neon_fp_vmla_qqq,\
2623+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2624+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2625+
2626+(define_bypass 3 "cortex_a9_neon_bp_3cycle"
2627+ "cortex_a9_neon_int_1,\
2628+ cortex_a9_neon_int_4,\
2629+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2630+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2631+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2632+ cortex_a9_neon_mla_qqq_8_16,\
2633+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2634+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2635+ cortex_a9_neon_fp_vmla_ddd,\
2636+ cortex_a9_neon_fp_vmla_qqq,\
2637+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2638+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2639+
2640+(define_bypass 2 "cortex_a9_neon_bp_2cycle"
2641+ "cortex_a9_neon_int_1,\
2642+ cortex_a9_neon_int_4,\
2643+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2644+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2645+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2646+ cortex_a9_neon_mla_qqq_8_16,\
2647+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2648+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2649+ cortex_a9_neon_fp_vmla_ddd,\
2650+ cortex_a9_neon_fp_vmla_qqq,\
2651+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2652+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2653+
2654+(define_bypass 1 "cortex_a9_neon_bp_simple"
2655+ "cortex_a9_neon_int_1,\
2656+ cortex_a9_neon_int_4,\
2657+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2658+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2659+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2660+ cortex_a9_neon_mla_qqq_8_16,\
2661+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2662+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2663+ cortex_a9_neon_fp_vmla_ddd,\
2664+ cortex_a9_neon_fp_vmla_qqq,\
2665+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2666+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2667+
2668+(define_bypass 9 "cortex_a9_neon_fp_vrecps_vrsqrts_qqq"
2669+ "cortex_a9_neon_int_1,\
2670+ cortex_a9_neon_int_4,\
2671+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2672+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2673+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2674+ cortex_a9_neon_mla_qqq_8_16,\
2675+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2676+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2677+ cortex_a9_neon_fp_vmla_ddd,\
2678+ cortex_a9_neon_fp_vmla_qqq,\
2679+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2680+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2681+
2682+(define_bypass 8 "cortex_a9_neon_fp_vrecps_vrsqrts_ddd"
2683+ "cortex_a9_neon_int_1,\
2684+ cortex_a9_neon_int_4,\
2685+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2686+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2687+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2688+ cortex_a9_neon_mla_qqq_8_16,\
2689+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2690+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2691+ cortex_a9_neon_fp_vmla_ddd,\
2692+ cortex_a9_neon_fp_vmla_qqq,\
2693+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2694+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2695+
2696+(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq_scalar"
2697+ "cortex_a9_neon_int_1,\
2698+ cortex_a9_neon_int_4,\
2699+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2700+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2701+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2702+ cortex_a9_neon_mla_qqq_8_16,\
2703+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2704+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2705+ cortex_a9_neon_fp_vmla_ddd,\
2706+ cortex_a9_neon_fp_vmla_qqq,\
2707+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2708+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2709+
2710+(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd_scalar"
2711+ "cortex_a9_neon_int_1,\
2712+ cortex_a9_neon_int_4,\
2713+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2714+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2715+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2716+ cortex_a9_neon_mla_qqq_8_16,\
2717+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2718+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2719+ cortex_a9_neon_fp_vmla_ddd,\
2720+ cortex_a9_neon_fp_vmla_qqq,\
2721+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2722+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2723+
2724+(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq"
2725+ "cortex_a9_neon_int_1,\
2726+ cortex_a9_neon_int_4,\
2727+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2728+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2729+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2730+ cortex_a9_neon_mla_qqq_8_16,\
2731+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2732+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2733+ cortex_a9_neon_fp_vmla_ddd,\
2734+ cortex_a9_neon_fp_vmla_qqq,\
2735+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2736+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2737+
2738+(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd"
2739+ "cortex_a9_neon_int_1,\
2740+ cortex_a9_neon_int_4,\
2741+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2742+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2743+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2744+ cortex_a9_neon_mla_qqq_8_16,\
2745+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2746+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2747+ cortex_a9_neon_fp_vmla_ddd,\
2748+ cortex_a9_neon_fp_vmla_qqq,\
2749+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2750+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2751+
2752+(define_bypass 5 "cortex_a9_neon_fp_vmul_qqd"
2753+ "cortex_a9_neon_int_1,\
2754+ cortex_a9_neon_int_4,\
2755+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2756+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2757+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2758+ cortex_a9_neon_mla_qqq_8_16,\
2759+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2760+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2761+ cortex_a9_neon_fp_vmla_ddd,\
2762+ cortex_a9_neon_fp_vmla_qqq,\
2763+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2764+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2765+
2766+(define_bypass 4 "cortex_a9_neon_fp_vmul_ddd"
2767+ "cortex_a9_neon_int_1,\
2768+ cortex_a9_neon_int_4,\
2769+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2770+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2771+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2772+ cortex_a9_neon_mla_qqq_8_16,\
2773+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2774+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2775+ cortex_a9_neon_fp_vmla_ddd,\
2776+ cortex_a9_neon_fp_vmla_qqq,\
2777+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2778+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2779+
2780+(define_bypass 4 "cortex_a9_neon_fp_vsum"
2781+ "cortex_a9_neon_int_1,\
2782+ cortex_a9_neon_int_4,\
2783+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2784+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2785+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2786+ cortex_a9_neon_mla_qqq_8_16,\
2787+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2788+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2789+ cortex_a9_neon_fp_vmla_ddd,\
2790+ cortex_a9_neon_fp_vmla_qqq,\
2791+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2792+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2793+
2794+(define_bypass 5 "cortex_a9_neon_fp_vadd_qqq_vabs_qq"
2795+ "cortex_a9_neon_int_1,\
2796+ cortex_a9_neon_int_4,\
2797+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2798+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2799+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2800+ cortex_a9_neon_mla_qqq_8_16,\
2801+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2802+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2803+ cortex_a9_neon_fp_vmla_ddd,\
2804+ cortex_a9_neon_fp_vmla_qqq,\
2805+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2806+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2807+
2808+(define_bypass 4 "cortex_a9_neon_fp_vadd_ddd_vabs_dd"
2809+ "cortex_a9_neon_int_1,\
2810+ cortex_a9_neon_int_4,\
2811+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2812+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2813+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2814+ cortex_a9_neon_mla_qqq_8_16,\
2815+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2816+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2817+ cortex_a9_neon_fp_vmla_ddd,\
2818+ cortex_a9_neon_fp_vmla_qqq,\
2819+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2820+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2821+
2822+(define_bypass 5 "cortex_a9_neon_vsra_vrsra"
2823+ "cortex_a9_neon_int_1,\
2824+ cortex_a9_neon_int_4,\
2825+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2826+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2827+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2828+ cortex_a9_neon_mla_qqq_8_16,\
2829+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2830+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2831+ cortex_a9_neon_fp_vmla_ddd,\
2832+ cortex_a9_neon_fp_vmla_qqq,\
2833+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2834+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2835+
2836+(define_bypass 4 "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq"
2837+ "cortex_a9_neon_int_1,\
2838+ cortex_a9_neon_int_4,\
2839+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2840+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2841+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2842+ cortex_a9_neon_mla_qqq_8_16,\
2843+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2844+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2845+ cortex_a9_neon_fp_vmla_ddd,\
2846+ cortex_a9_neon_fp_vmla_qqq,\
2847+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2848+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2849+
2850+(define_bypass 0 "cortex_a9_neon_vshl_ddd"
2851+ "cortex_a9_neon_int_1,\
2852+ cortex_a9_neon_int_4,\
2853+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2854+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2855+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2856+ cortex_a9_neon_mla_qqq_8_16,\
2857+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2858+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2859+ cortex_a9_neon_fp_vmla_ddd,\
2860+ cortex_a9_neon_fp_vmla_qqq,\
2861+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2862+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2863+
2864+(define_bypass 3 "cortex_a9_neon_shift_3"
2865+ "cortex_a9_neon_int_1,\
2866+ cortex_a9_neon_int_4,\
2867+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2868+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2869+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2870+ cortex_a9_neon_mla_qqq_8_16,\
2871+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2872+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2873+ cortex_a9_neon_fp_vmla_ddd,\
2874+ cortex_a9_neon_fp_vmla_qqq,\
2875+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2876+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2877+
2878+(define_bypass 3 "cortex_a9_neon_shift_2"
2879+ "cortex_a9_neon_int_1,\
2880+ cortex_a9_neon_int_4,\
2881+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2882+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2883+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2884+ cortex_a9_neon_mla_qqq_8_16,\
2885+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2886+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2887+ cortex_a9_neon_fp_vmla_ddd,\
2888+ cortex_a9_neon_fp_vmla_qqq,\
2889+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2890+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2891+
2892+(define_bypass 2 "cortex_a9_neon_shift_1"
2893+ "cortex_a9_neon_int_1,\
2894+ cortex_a9_neon_int_4,\
2895+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2896+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2897+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2898+ cortex_a9_neon_mla_qqq_8_16,\
2899+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2900+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2901+ cortex_a9_neon_fp_vmla_ddd,\
2902+ cortex_a9_neon_fp_vmla_qqq,\
2903+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2904+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2905+
2906+(define_bypass 5 "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar"
2907+ "cortex_a9_neon_int_1,\
2908+ cortex_a9_neon_int_4,\
2909+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2910+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2911+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2912+ cortex_a9_neon_mla_qqq_8_16,\
2913+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2914+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2915+ cortex_a9_neon_fp_vmla_ddd,\
2916+ cortex_a9_neon_fp_vmla_qqq,\
2917+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2918+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2919+
2920+(define_bypass 8 "cortex_a9_neon_mul_qqd_32_scalar"
2921+ "cortex_a9_neon_int_1,\
2922+ cortex_a9_neon_int_4,\
2923+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2924+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2925+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2926+ cortex_a9_neon_mla_qqq_8_16,\
2927+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2928+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2929+ cortex_a9_neon_fp_vmla_ddd,\
2930+ cortex_a9_neon_fp_vmla_qqq,\
2931+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2932+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2933+
2934+(define_bypass 5 "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar"
2935+ "cortex_a9_neon_int_1,\
2936+ cortex_a9_neon_int_4,\
2937+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2938+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2939+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2940+ cortex_a9_neon_mla_qqq_8_16,\
2941+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2942+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2943+ cortex_a9_neon_fp_vmla_ddd,\
2944+ cortex_a9_neon_fp_vmla_qqq,\
2945+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2946+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2947+
2948+(define_bypass 8 "cortex_a9_neon_mla_qqq_32_qqd_32_scalar"
2949+ "cortex_a9_neon_int_1,\
2950+ cortex_a9_neon_int_4,\
2951+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2952+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2953+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2954+ cortex_a9_neon_mla_qqq_8_16,\
2955+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2956+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2957+ cortex_a9_neon_fp_vmla_ddd,\
2958+ cortex_a9_neon_fp_vmla_qqq,\
2959+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2960+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2961+
2962+(define_bypass 6 "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"
2963+ "cortex_a9_neon_int_1,\
2964+ cortex_a9_neon_int_4,\
2965+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2966+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2967+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2968+ cortex_a9_neon_mla_qqq_8_16,\
2969+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2970+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2971+ cortex_a9_neon_fp_vmla_ddd,\
2972+ cortex_a9_neon_fp_vmla_qqq,\
2973+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2974+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2975+
2976+(define_bypass 6 "cortex_a9_neon_mla_qqq_8_16"
2977+ "cortex_a9_neon_int_1,\
2978+ cortex_a9_neon_int_4,\
2979+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2980+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2981+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2982+ cortex_a9_neon_mla_qqq_8_16,\
2983+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2984+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2985+ cortex_a9_neon_fp_vmla_ddd,\
2986+ cortex_a9_neon_fp_vmla_qqq,\
2987+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
2988+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
2989+
2990+(define_bypass 5 "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long"
2991+ "cortex_a9_neon_int_1,\
2992+ cortex_a9_neon_int_4,\
2993+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
2994+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
2995+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
2996+ cortex_a9_neon_mla_qqq_8_16,\
2997+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
2998+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
2999+ cortex_a9_neon_fp_vmla_ddd,\
3000+ cortex_a9_neon_fp_vmla_qqq,\
3001+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3002+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3003+
3004+(define_bypass 6 "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"
3005+ "cortex_a9_neon_int_1,\
3006+ cortex_a9_neon_int_4,\
3007+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3008+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3009+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3010+ cortex_a9_neon_mla_qqq_8_16,\
3011+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3012+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3013+ cortex_a9_neon_fp_vmla_ddd,\
3014+ cortex_a9_neon_fp_vmla_qqq,\
3015+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3016+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3017+
3018+(define_bypass 6 "cortex_a9_neon_mul_qqq_8_16_32_ddd_32"
3019+ "cortex_a9_neon_int_1,\
3020+ cortex_a9_neon_int_4,\
3021+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3022+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3023+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3024+ cortex_a9_neon_mla_qqq_8_16,\
3025+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3026+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3027+ cortex_a9_neon_fp_vmla_ddd,\
3028+ cortex_a9_neon_fp_vmla_qqq,\
3029+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3030+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3031+
3032+(define_bypass 5 "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long"
3033+ "cortex_a9_neon_int_1,\
3034+ cortex_a9_neon_int_4,\
3035+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3036+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3037+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3038+ cortex_a9_neon_mla_qqq_8_16,\
3039+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3040+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3041+ cortex_a9_neon_fp_vmla_ddd,\
3042+ cortex_a9_neon_fp_vmla_qqq,\
3043+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3044+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3045+
3046+(define_bypass 5 "cortex_a9_neon_vsma"
3047+ "cortex_a9_neon_int_1,\
3048+ cortex_a9_neon_int_4,\
3049+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3050+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3051+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3052+ cortex_a9_neon_mla_qqq_8_16,\
3053+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3054+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3055+ cortex_a9_neon_fp_vmla_ddd,\
3056+ cortex_a9_neon_fp_vmla_qqq,\
3057+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3058+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3059+
3060+(define_bypass 6 "cortex_a9_neon_vaba_qqq"
3061+ "cortex_a9_neon_int_1,\
3062+ cortex_a9_neon_int_4,\
3063+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3064+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3065+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3066+ cortex_a9_neon_mla_qqq_8_16,\
3067+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3068+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3069+ cortex_a9_neon_fp_vmla_ddd,\
3070+ cortex_a9_neon_fp_vmla_qqq,\
3071+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3072+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3073+
3074+(define_bypass 5 "cortex_a9_neon_vaba"
3075+ "cortex_a9_neon_int_1,\
3076+ cortex_a9_neon_int_4,\
3077+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3078+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3079+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3080+ cortex_a9_neon_mla_qqq_8_16,\
3081+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3082+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3083+ cortex_a9_neon_fp_vmla_ddd,\
3084+ cortex_a9_neon_fp_vmla_qqq,\
3085+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3086+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3087+
3088+(define_bypass 2 "cortex_a9_neon_vmov"
3089+ "cortex_a9_neon_int_1,\
3090+ cortex_a9_neon_int_4,\
3091+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3092+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3093+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3094+ cortex_a9_neon_mla_qqq_8_16,\
3095+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3096+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3097+ cortex_a9_neon_fp_vmla_ddd,\
3098+ cortex_a9_neon_fp_vmla_qqq,\
3099+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3100+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3101+
3102+(define_bypass 3 "cortex_a9_neon_vqneg_vqabs"
3103+ "cortex_a9_neon_int_1,\
3104+ cortex_a9_neon_int_4,\
3105+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3106+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3107+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3108+ cortex_a9_neon_mla_qqq_8_16,\
3109+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3110+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3111+ cortex_a9_neon_fp_vmla_ddd,\
3112+ cortex_a9_neon_fp_vmla_qqq,\
3113+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3114+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3115+
3116+(define_bypass 3 "cortex_a9_neon_int_5"
3117+ "cortex_a9_neon_int_1,\
3118+ cortex_a9_neon_int_4,\
3119+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3120+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3121+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3122+ cortex_a9_neon_mla_qqq_8_16,\
3123+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3124+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3125+ cortex_a9_neon_fp_vmla_ddd,\
3126+ cortex_a9_neon_fp_vmla_qqq,\
3127+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3128+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3129+
3130+(define_bypass 3 "cortex_a9_neon_int_4"
3131+ "cortex_a9_neon_int_1,\
3132+ cortex_a9_neon_int_4,\
3133+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3134+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3135+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3136+ cortex_a9_neon_mla_qqq_8_16,\
3137+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3138+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3139+ cortex_a9_neon_fp_vmla_ddd,\
3140+ cortex_a9_neon_fp_vmla_qqq,\
3141+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3142+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3143+
3144+(define_bypass 2 "cortex_a9_neon_int_3"
3145+ "cortex_a9_neon_int_1,\
3146+ cortex_a9_neon_int_4,\
3147+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3148+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3149+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3150+ cortex_a9_neon_mla_qqq_8_16,\
3151+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3152+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3153+ cortex_a9_neon_fp_vmla_ddd,\
3154+ cortex_a9_neon_fp_vmla_qqq,\
3155+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3156+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3157+
3158+(define_bypass 2 "cortex_a9_neon_int_2"
3159+ "cortex_a9_neon_int_1,\
3160+ cortex_a9_neon_int_4,\
3161+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3162+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3163+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3164+ cortex_a9_neon_mla_qqq_8_16,\
3165+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3166+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3167+ cortex_a9_neon_fp_vmla_ddd,\
3168+ cortex_a9_neon_fp_vmla_qqq,\
3169+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3170+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3171+
3172+(define_bypass 2 "cortex_a9_neon_int_1"
3173+ "cortex_a9_neon_int_1,\
3174+ cortex_a9_neon_int_4,\
3175+ cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
3176+ cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\
3177+ cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
3178+ cortex_a9_neon_mla_qqq_8_16,\
3179+ cortex_a9_neon_fp_vadd_ddd_vabs_dd,\
3180+ cortex_a9_neon_fp_vadd_qqq_vabs_qq,\
3181+ cortex_a9_neon_fp_vmla_ddd,\
3182+ cortex_a9_neon_fp_vmla_qqq,\
3183+ cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\
3184+ cortex_a9_neon_fp_vrecps_vrsqrts_qqq")
3185+
3186
3187=== modified file 'gcc/config/arm/cortex-a9.md'
3188--- old/gcc/config/arm/cortex-a9.md 2010-08-24 13:15:54 +0000
3189+++ new/gcc/config/arm/cortex-a9.md 2010-09-16 09:47:44 +0000
3190@@ -80,8 +80,9 @@
3191 (define_insn_reservation "cortex_a9_dp" 2
3192 (and (eq_attr "tune" "cortexa9")
3193 (ior (eq_attr "type" "alu")
3194- (and (eq_attr "type" "alu_shift_reg, alu_shift")
3195- (eq_attr "insn" "mov"))))
3196+ (ior (and (eq_attr "type" "alu_shift_reg, alu_shift")
3197+ (eq_attr "insn" "mov"))
3198+ (eq_attr "neon_type" "none"))))
3199 "cortex_a9_p0_default|cortex_a9_p1_default")
3200
3201 ;; An instruction using the shifter will go down E1.
3202
3203=== modified file 'gcc/config/arm/neon-schedgen.ml'
3204--- old/gcc/config/arm/neon-schedgen.ml 2010-04-02 18:54:46 +0000
3205+++ new/gcc/config/arm/neon-schedgen.ml 2010-09-16 09:47:44 +0000
3206@@ -1,7 +1,6 @@
3207 (* Emission of the core of the Cortex-A8 NEON scheduling description.
3208 Copyright (C) 2007, 2010 Free Software Foundation, Inc.
3209 Contributed by CodeSourcery.
3210-
3211 This file is part of GCC.
3212
3213 GCC is free software; you can redistribute it and/or modify it under
3214@@ -21,7 +20,14 @@
3215
3216 (* This scheduling description generator works as follows.
3217 - Each group of instructions has source and destination requirements
3218- specified. The source requirements may be specified using
3219+ specified and a list of cores supported. This is then filtered
3220+ and per core scheduler descriptions are generated out.
3221+ The reservations generated are prefixed by the name of the
3222+ core and the check is performed on the basis of what the tuning
3223+ string is. Running this will generate Neon scheduler descriptions
3224+ for all cores supported.
3225+
3226+ The source requirements may be specified using
3227 Source (the stage at which all source operands not otherwise
3228 described are read), Source_m (the stage at which Rm operands are
3229 read), Source_n (likewise for Rn) and Source_d (likewise for Rd).
3230@@ -83,6 +89,17 @@
3231 | Ls of int
3232 | Fmul_then_fadd | Fmul_then_fadd_2
3233
3234+type core = CortexA8 | CortexA9
3235+let allCores = [CortexA8; CortexA9]
3236+let coreStr = function
3237+ CortexA8 -> "cortex_a8"
3238+ | CortexA9 -> "cortex_a9"
3239+
3240+let tuneStr = function
3241+ CortexA8 -> "cortexa8"
3242+ | CortexA9 -> "cortexa9"
3243+
3244+
3245 (* This table must be kept as short as possible by conflating
3246 entries with the same availability behavior.
3247
3248@@ -90,129 +107,136 @@
3249 Second components: availability requirements, in the order in which
3250 they should appear in the comments in the .md file.
3251 Third components: reservation info
3252+ Fourth components: List of supported cores.
3253 *)
3254 let availability_table = [
3255 (* NEON integer ALU instructions. *)
3256 (* vbit vbif vbsl vorr vbic vnot vcls vclz vcnt vadd vand vorr
3257 veor vbic vorn ddd qqq *)
3258- "neon_int_1", [Source n2; Dest n3], ALU;
3259+ "neon_int_1", [Source n2; Dest n3], ALU, allCores;
3260 (* vadd vsub qqd vsub ddd qqq *)
3261- "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU;
3262+ "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU, allCores;
3263 (* vsum vneg dd qq vadd vsub qdd *)
3264- "neon_int_3", [Source n1; Dest n3], ALU;
3265+ "neon_int_3", [Source n1; Dest n3], ALU, allCores;
3266 (* vabs vceqz vcgez vcbtz vclez vcltz vadh vradh vsbh vrsbh dqq *)
3267 (* vhadd vrhadd vqadd vtst ddd qqq *)
3268- "neon_int_4", [Source n2; Dest n4], ALU;
3269+ "neon_int_4", [Source n2; Dest n4], ALU, allCores;
3270 (* vabd qdd vhsub vqsub vabd vceq vcge vcgt vmax vmin vfmx vfmn ddd ddd *)
3271- "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU;
3272+ "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU, allCores;
3273 (* vqneg vqabs dd qq *)
3274- "neon_vqneg_vqabs", [Source n1; Dest n4], ALU;
3275+ "neon_vqneg_vqabs", [Source n1; Dest n4], ALU, allCores;
3276 (* vmov vmvn *)
3277- "neon_vmov", [Dest n3], ALU;
3278+ "neon_vmov", [Dest n3], ALU, allCores;
3279 (* vaba *)
3280- "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU;
3281+ "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU, allCores;
3282 "neon_vaba_qqq",
3283- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ALU_2cycle;
3284+ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)],
3285+ ALU_2cycle, allCores;
3286 (* vsma *)
3287- "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU;
3288+ "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU, allCores;
3289
3290 (* NEON integer multiply instructions. *)
3291 (* vmul, vqdmlh, vqrdmlh *)
3292 (* vmul, vqdmul, qdd 16/8 long 32/16 long *)
3293- "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], Mul;
3294- "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], Mul_2cycle;
3295+ "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6],
3296+ Mul, allCores;
3297+ "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)],
3298+ Mul_2cycle, allCores;
3299 (* vmul, vqdmul again *)
3300 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar",
3301- [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle;
3302+ [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle, allCores;
3303 (* vmla, vmls *)
3304 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long",
3305- [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul;
3306+ [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul, allCores;
3307 "neon_mla_qqq_8_16",
3308- [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
3309+ [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)],
3310+ Mul_2cycle, allCores;
3311 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long",
3312- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
3313+ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)],
3314+ Mul_2cycle, allCores;
3315 "neon_mla_qqq_32_qqd_32_scalar",
3316- [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], Mul_4cycle;
3317+ [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)],
3318+ Mul_4cycle, allCores;
3319 (* vmul, vqdmulh, vqrdmulh *)
3320 (* vmul, vqdmul *)
3321 "neon_mul_ddd_16_scalar_32_16_long_scalar",
3322- [Source_n n2; Source_m n1; Dest n6], Mul;
3323+ [Source_n n2; Source_m n1; Dest n6], Mul, allCores;
3324 "neon_mul_qqd_32_scalar",
3325- [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle;
3326+ [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle, allCores;
3327 (* vmla, vmls *)
3328 (* vmla, vmla, vqdmla, vqdmls *)
3329 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar",
3330- [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul;
3331+ [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul, allCores;
3332
3333 (* NEON integer shift instructions. *)
3334 (* vshr/vshl immediate, vshr_narrow, vshl_vmvh, vsli_vsri_ddd *)
3335- "neon_shift_1", [Source n1; Dest n3], Shift;
3336- (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow;
3337+ "neon_shift_1", [Source n1; Dest n3], Shift, allCores;
3338+ (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow, allCores;
3339 vqshl_vrshl_vqrshl_ddd *)
3340- "neon_shift_2", [Source n1; Dest n4], Shift;
3341+ "neon_shift_2", [Source n1; Dest n4], Shift, allCores;
3342 (* vsli, vsri and vshl for qqq *)
3343- "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle;
3344- "neon_vshl_ddd", [Source n1; Dest n1], Shift;
3345+ "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle, allCores;
3346+ "neon_vshl_ddd", [Source n1; Dest n1], Shift, allCores;
3347 "neon_vqshl_vrshl_vqrshl_qqq", [Source n1; Dest_n_after (1, n4)],
3348- Shift_2cycle;
3349- "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift;
3350+ Shift_2cycle, allCores;
3351+ "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift, allCores;
3352
3353 (* NEON floating-point instructions. *)
3354 (* vadd, vsub, vabd, vmul, vceq, vcge, vcgt, vcage, vcagt, vmax, vmin *)
3355 (* vabs, vneg, vceqz, vcgez, vcgtz, vclez, vcltz, vrecpe, vrsqrte, vcvt *)
3356- "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd;
3357+ "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd, allCores;
3358 "neon_fp_vadd_qqq_vabs_qq", [Source n2; Dest_n_after (1, n5)],
3359- Fadd_2cycle;
3360+ Fadd_2cycle, allCores;
3361 (* vsum, fvmx, vfmn *)
3362- "neon_fp_vsum", [Source n1; Dest n5], Fadd;
3363- "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul;
3364+ "neon_fp_vsum", [Source n1; Dest n5], Fadd, allCores;
3365+ "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul, allCores;
3366 "neon_fp_vmul_qqd", [Source_n n2; Source_m n1; Dest_n_after (1, n5)],
3367- Fmul_2cycle;
3368+ Fmul_2cycle, allCores;
3369 (* vmla, vmls *)
3370 "neon_fp_vmla_ddd",
3371- [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd;
3372+ [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd, allCores;
3373 "neon_fp_vmla_qqq",
3374 [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n9)],
3375- Fmul_then_fadd_2;
3376+ Fmul_then_fadd_2, allCores;
3377 "neon_fp_vmla_ddd_scalar",
3378- [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd;
3379+ [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd, allCores;
3380 "neon_fp_vmla_qqq_scalar",
3381 [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n9)],
3382- Fmul_then_fadd_2;
3383- "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd;
3384+ Fmul_then_fadd_2, allCores;
3385+ "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd, allCores;
3386 "neon_fp_vrecps_vrsqrts_qqq", [Source n2; Dest_n_after (1, n9)],
3387- Fmul_then_fadd_2;
3388+ Fmul_then_fadd_2, allCores;
3389
3390 (* NEON byte permute instructions. *)
3391 (* vmov; vtrn and vswp for dd; vzip for dd; vuzp for dd; vrev; vext for dd *)
3392- "neon_bp_simple", [Source n1; Dest n2], Permute 1;
3393- (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1};
3394+ "neon_bp_simple", [Source n1; Dest n2], Permute 1, allCores;
3395+ (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}, allCores;
3396 similarly for vtbx *)
3397- "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2;
3398+ "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2, allCores;
3399 (* all the rest *)
3400- "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3;
3401+ "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3, allCores;
3402
3403 (* NEON load/store instructions. *)
3404- "neon_ldr", [Dest n1], Ls 1;
3405- "neon_str", [Source n1], Ls 1;
3406- "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2;
3407- "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3;
3408- "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2;
3409- "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3;
3410- "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4;
3411- "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2;
3412- "neon_vst1_3_4_regs", [Source n1], Ls 3;
3413- "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4;
3414- "neon_vst3_vst4", [Source n1], Ls 4;
3415- "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3;
3416- "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5;
3417- "neon_vst1_vst2_lane", [Source n1], Ls 2;
3418- "neon_vst3_vst4_lane", [Source n1], Ls 3;
3419- "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3;
3420+ "neon_ldr", [Dest n1], Ls 1, allCores;
3421+ "neon_str", [Source n1], Ls 1, allCores;
3422+ "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2, allCores;
3423+ "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3, allCores;
3424+ "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2, allCores;
3425+ "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3, allCores;
3426+ "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4, allCores;
3427+ "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2, allCores;
3428+ "neon_vst1_3_4_regs", [Source n1], Ls 3, allCores;
3429+ "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4, allCores;
3430+ "neon_vst3_vst4", [Source n1], Ls 4, allCores;
3431+ "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3, allCores;
3432+ "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5, allCores;
3433+ "neon_vst1_vst2_lane", [Source n1], Ls 2, allCores;
3434+ "neon_vst3_vst4_lane", [Source n1], Ls 3, allCores;
3435+ "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3, allCores;
3436
3437 (* NEON register transfer instructions. *)
3438- "neon_mcr", [Dest n2], Permute 1;
3439- "neon_mcr_2_mcrr", [Dest n2], Permute 2;
3440+ "neon_mcr", [Dest n2], Permute 1, allCores;
3441+ "neon_mcr_2_mcrr", [Dest n2], Permute 2, allCores;
3442 (* MRC instructions are in the .tpl file. *)
3443 ]
3444
3445@@ -221,7 +245,7 @@
3446 required. (It is also possible that an entry in the table has no
3447 source requirements.) *)
3448 let calculate_sources =
3449- List.map (fun (name, avail, res) ->
3450+ List.map (fun (name, avail, res, cores) ->
3451 let earliest_stage =
3452 List.fold_left
3453 (fun cur -> fun info ->
3454@@ -331,7 +355,7 @@
3455 of one bypass from this producer to any particular consumer listed
3456 in LATENCIES.) Use a hash table to collate bypasses with the
3457 same latency and guard. *)
3458-let collate_bypasses (producer_name, _, _, _) largest latencies =
3459+let collate_bypasses (producer_name, _, _, _) largest latencies core =
3460 let ht = Hashtbl.create 42 in
3461 let keys = ref [] in
3462 List.iter (
3463@@ -350,7 +374,7 @@
3464 (if (try ignore (Hashtbl.find ht (guard, latency)); false
3465 with Not_found -> true) then
3466 keys := (guard, latency) :: !keys);
3467- Hashtbl.add ht (guard, latency) consumer
3468+ Hashtbl.add ht (guard, latency) ((coreStr core) ^ "_" ^ consumer)
3469 end
3470 ) latencies;
3471 (* The hash table now has bypasses collated so that ones with the
3472@@ -372,7 +396,7 @@
3473 the output in such a way that all bypasses with the same producer
3474 and latency are together, and so that bypasses with the worst-case
3475 latency are ignored. *)
3476-let worst_case_latencies_and_bypasses =
3477+let worst_case_latencies_and_bypasses core =
3478 let rec f (worst_acc, bypasses_acc) prev xs =
3479 match xs with
3480 [] -> (worst_acc, bypasses_acc)
3481@@ -400,7 +424,7 @@
3482 (* Having got the largest latency, collect all bypasses for
3483 this producer and filter out those with that larger
3484 latency. Record the others for later emission. *)
3485- let bypasses = collate_bypasses producer largest latencies in
3486+ let bypasses = collate_bypasses producer largest latencies core in
3487 (* Go on to process remaining producers, having noted
3488 the result for this one. *)
3489 f ((producer_name, producer_avail, largest,
3490@@ -444,14 +468,18 @@
3491 in
3492 f avail 0
3493
3494+
3495 (* Emit a define_insn_reservation for each producer. The latency
3496 written in will be its worst-case latency. *)
3497-let emit_insn_reservations =
3498- List.iter (
3499+let emit_insn_reservations core =
3500+ let corestring = coreStr core in
3501+ let tunestring = tuneStr core
3502+ in List.iter (
3503 fun (producer, avail, latency, reservation) ->
3504 write_comment producer avail;
3505- Printf.printf "(define_insn_reservation \"%s\" %d\n" producer latency;
3506- Printf.printf " (and (eq_attr \"tune\" \"cortexa8\")\n";
3507+ Printf.printf "(define_insn_reservation \"%s_%s\" %d\n"
3508+ corestring producer latency;
3509+ Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring;
3510 Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer;
3511 let str =
3512 match reservation with
3513@@ -467,7 +495,7 @@
3514 | Fmul_then_fadd -> "fmul_then_fadd"
3515 | Fmul_then_fadd_2 -> "fmul_then_fadd_2"
3516 in
3517- Printf.printf " \"cortex_a8_neon_%s\")\n\n" str
3518+ Printf.printf " \"%s_neon_%s\")\n\n" corestring str
3519 )
3520
3521 (* Given a guard description, return the name of the C function to
3522@@ -480,10 +508,12 @@
3523 | Guard_none -> assert false
3524
3525 (* Emit a define_bypass for each bypass. *)
3526-let emit_bypasses =
3527+let emit_bypasses core =
3528 List.iter (
3529 fun (producer, consumers, latency, guard) ->
3530- Printf.printf "(define_bypass %d \"%s\"\n" latency producer;
3531+ Printf.printf "(define_bypass %d \"%s_%s\"\n"
3532+ latency (coreStr core) producer;
3533+
3534 if guard = Guard_none then
3535 Printf.printf " \"%s\")\n\n" consumers
3536 else
3537@@ -493,11 +523,21 @@
3538 end
3539 )
3540
3541+
3542+let calculate_per_core_availability_table core availability_table =
3543+ let table = calculate_sources availability_table in
3544+ let worst_cases, bypasses = worst_case_latencies_and_bypasses core table in
3545+ emit_insn_reservations core (List.rev worst_cases);
3546+ Printf.printf ";; Exceptions to the default latencies.\n\n";
3547+ emit_bypasses core bypasses
3548+
3549+let calculate_core_availability_table core availability_table =
3550+let filter_core = List.filter (fun (_, _, _, cores)
3551+ -> List.exists ((=) core) cores)
3552+in calculate_per_core_availability_table core (filter_core availability_table)
3553+
3554+
3555 (* Program entry point. *)
3556 let main =
3557- let table = calculate_sources availability_table in
3558- let worst_cases, bypasses = worst_case_latencies_and_bypasses table in
3559- emit_insn_reservations (List.rev worst_cases);
3560- Printf.printf ";; Exceptions to the default latencies.\n\n";
3561- emit_bypasses bypasses
3562-
3563+ List.map (fun core -> calculate_core_availability_table
3564+ core availability_table) allCores
3565
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-20 05:45:31 +0000