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authorKoen Kooi <koen@dominion.thruhere.net>2010-11-02 22:03:58 +0100
committerKoen Kooi <koen@dominion.thruhere.net>2010-11-02 22:12:02 +0100
commitbe10a6b1321f250b1034c7d9d0a8ef18b296eef1 (patch)
tree9249025cbfbfbee4cc430d62b27f75301dd4dfde /recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch
parent93b28937ac67ba46d65f55637e42552e224aa7e2 (diff)
downloadmeta-openembedded-be10a6b1321f250b1034c7d9d0a8ef18b296eef1.tar.gz
angstrom-layers: meta-openembedded: replace poky gcc 4.5 sources with OE ones
This needs further investigation, but for now we can get the tested sources into the poky gcc harness Signed-off-by: Koen Kooi <k-kooi@ti.com>
Diffstat (limited to 'recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch')
-rw-r--r--recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch3094
1 files changed, 3094 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch
new file mode 100644
index 0000000000..ae417a18f5
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch
@@ -0,0 +1,3094 @@
12010-07-08 Sandra Loosemore <sandra@codesourcery.com>
2
3 Backport from upstream (originally from Sourcery G++ 4.4):
4
5 2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
6
7 gcc/
8 * config/arm/neon.md (vec_extractv2di): Correct error in register
9 numbering to reconcile with neon_vget_lanev2di.
10
11 2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
12
13 gcc/
14 * config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL
15 instead of an unspec.
16 (neon_expand_vector_init): Likewise.
17 * config/arm/neon.md (UNSPEC_VCOMBINE): Delete.
18 (UNSPEC_VDUP_LANE): Delete.
19 (UNSPEC VDUP_N): Delete.
20 (UNSPEC_VGET_HIGH): Delete.
21 (UNSPEC_VGET_LANE): Delete.
22 (UNSPEC_VGET_LOW): Delete.
23 (UNSPEC_VMVN): Delete.
24 (UNSPEC_VSET_LANE): Delete.
25 (V_double_vector_mode): New.
26 (vec_set<mode>_internal): Make code emitted match that for the
27 corresponding intrinsics.
28 (vec_setv2di_internal): Likewise.
29 (neon_vget_lanedi): Rewrite to expand into emit_move_insn.
30 (neon_vget_lanev2di): Rewrite to expand into vec_extractv2di.
31 (neon_vset_lane<mode>): Combine double and quad patterns and
32 expand into vec_set<mode>_internal instead of UNSPEC_VSET_LANE.
33 (neon_vset_lanedi): Rewrite to expand into emit_move_insn.
34 (neon_vdup_n<mode>): Rewrite RTL without unspec.
35 (neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn.
36 (neon_vdup_nv2di): Rewrite RTL without unspec and merge with
37 with neon_vdup_lanev2di, adjusting the pattern from the latter
38 to be predicable for consistency.
39 (neon_vdup_lane<mode>_internal): New.
40 (neon_vdup_lane<mode>): Turn into a define_expand and rewrite
41 to avoid using an unspec.
42 (neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec.
43 (neon_vdup_lanev2di): Turn into a define_expand.
44 (neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE.
45 (neon_vget_high<mode>): Replace with....
46 (neon_vget_highv16qi): New pattern using canonical RTL.
47 (neon_vget_highv8hi): Likewise.
48 (neon_vget_highv4si): Likewise.
49 (neon_vget_highv4sf): Likewise.
50 (neon_vget_highv2di): Likewise.
51 (neon_vget_low<mode>): Replace with....
52 (neon_vget_lowv16qi): New pattern using canonical RTL.
53 (neon_vget_lowv8hi): Likewise.
54 (neon_vget_lowv4si): Likewise.
55 (neon_vget_lowv4sf): Likewise.
56 (neon_vget_lowv2di): Likewise.
57
58 * config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress
59 test for this emitting vmov.
60 (Vset_lane): Likewise.
61 (Vdup_n): Likewise.
62 (Vmov_n): Likewise.
63
64 * doc/arm-neon-intrinsics.texi: Regenerated.
65
66 gcc/testsuite/
67 * gcc.target/arm/neon/vdup_ns64.c: Regenerated.
68 * gcc.target/arm/neon/vdup_nu64.c: Regenerated.
69 * gcc.target/arm/neon/vdupQ_ns64.c: Regenerated.
70 * gcc.target/arm/neon/vdupQ_nu64.c: Regenerated.
71 * gcc.target/arm/neon/vmov_ns64.c: Regenerated.
72 * gcc.target/arm/neon/vmov_nu64.c: Regenerated.
73 * gcc.target/arm/neon/vmovQ_ns64.c: Regenerated.
74 * gcc.target/arm/neon/vmovQ_nu64.c: Regenerated.
75 * gcc.target/arm/neon/vget_lanes64.c: Regenerated.
76 * gcc.target/arm/neon/vget_laneu64.c: Regenerated.
77 * gcc.target/arm/neon/vset_lanes64.c: Regenerated.
78 * gcc.target/arm/neon/vset_laneu64.c: Regenerated.
79 * gcc.target/arm/neon-vdup_ns64.c: New.
80 * gcc.target/arm/neon-vdup_nu64.c: New.
81 * gcc.target/arm/neon-vdupQ_ns64.c: New.
82 * gcc.target/arm/neon-vdupQ_nu64.c: New.
83 * gcc.target/arm/neon-vdupQ_lanes64.c: New.
84 * gcc.target/arm/neon-vdupQ_laneu64.c: New.
85 * gcc.target/arm/neon-vmov_ns64.c: New.
86 * gcc.target/arm/neon-vmov_nu64.c: New.
87 * gcc.target/arm/neon-vmovQ_ns64.c: New.
88 * gcc.target/arm/neon-vmovQ_nu64.c: New.
89 * gcc.target/arm/neon-vget_lanes64.c: New.
90 * gcc.target/arm/neon-vget_laneu64.c: New.
91 * gcc.target/arm/neon-vset_lanes64.c: New.
92 * gcc.target/arm/neon-vset_laneu64.c: New.
93
94 2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
95 Julian Brown <julian@codesourcery.com>
96
97 gcc/
98 * config/arm/neon.md (UNSPEC_VABA): Delete.
99 (UNSPEC_VABAL): Delete.
100 (UNSPEC_VABS): Delete.
101 (UNSPEC_VMUL_N): Delete.
102 (adddi3_neon): New.
103 (subdi3_neon): New.
104 (mul<mode>3add<mode>_neon): Make the pattern named.
105 (mul<mode>3neg<mode>add<mode>_neon): Likewise.
106 (neon_vadd<mode>): Replace with define_expand, and move the remaining
107 unspec parts...
108 (neon_vadd<mode>_unspec): ...to this.
109 (neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise.
110 (neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise.
111 (neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise.
112 (neon_vaba<mode>): Rewrite in terms of vabd.
113 (neon_vabal<mode>): Rewrite in terms of vabdl.
114 (neon_vabs<mode>): Rewrite without unspec.
115 * config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON.
116 (*arm_subdi3): Likewise.
117 * config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add
118 No_op attribute to disable assembly output checks.
119 * config/arm/arm_neon.h: Regenerated.
120 * doc/arm-neon-intrinsics.texi: Regenerated.
121
122 gcc/testsuite/
123 * gcc.target/arm/neon/vadds64.c: Regenerated.
124 * gcc.target/arm/neon/vaddu64.c: Regenerated.
125 * gcc.target/arm/neon/vsubs64.c: Regenerated.
126 * gcc.target/arm/neon/vsubu64.c: Regenerated.
127 * gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options.
128 * gcc.target/arm/neon-vmls-1.c: Likewise.
129 * gcc.target/arm/neon-vsubs64.c: New execution test.
130 * gcc.target/arm/neon-vsubu64.c: New execution test.
131 * gcc.target/arm/neon-vadds64.c: New execution test.
132 * gcc.target/arm/neon-vaddu64.c: New execution test.
133
134=== modified file 'gcc/config/arm/arm.c'
135--- old/gcc/config/arm/arm.c 2010-07-29 15:53:39 +0000
136+++ new/gcc/config/arm/arm.c 2010-07-29 15:59:12 +0000
137@@ -8110,8 +8110,7 @@
138 load. */
139
140 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
141- return gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
142- UNSPEC_VDUP_N);
143+ return gen_rtx_VEC_DUPLICATE (mode, x);
144 }
145
146 /* Generate code to load VALS, which is a PARALLEL containing only
147@@ -8207,8 +8206,7 @@
148 {
149 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
150 emit_insn (gen_rtx_SET (VOIDmode, target,
151- gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
152- UNSPEC_VDUP_N)));
153+ gen_rtx_VEC_DUPLICATE (mode, x)));
154 return;
155 }
156
157@@ -8217,7 +8215,7 @@
158 if (n_var == 1)
159 {
160 rtx copy = copy_rtx (vals);
161- rtvec ops;
162+ rtx index = GEN_INT (one_var);
163
164 /* Load constant part of vector, substitute neighboring value for
165 varying element. */
166@@ -8226,9 +8224,38 @@
167
168 /* Insert variable. */
169 x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
170- ops = gen_rtvec (3, x, target, GEN_INT (one_var));
171- emit_insn (gen_rtx_SET (VOIDmode, target,
172- gen_rtx_UNSPEC (mode, ops, UNSPEC_VSET_LANE)));
173+ switch (mode)
174+ {
175+ case V8QImode:
176+ emit_insn (gen_neon_vset_lanev8qi (target, x, target, index));
177+ break;
178+ case V16QImode:
179+ emit_insn (gen_neon_vset_lanev16qi (target, x, target, index));
180+ break;
181+ case V4HImode:
182+ emit_insn (gen_neon_vset_lanev4hi (target, x, target, index));
183+ break;
184+ case V8HImode:
185+ emit_insn (gen_neon_vset_lanev8hi (target, x, target, index));
186+ break;
187+ case V2SImode:
188+ emit_insn (gen_neon_vset_lanev2si (target, x, target, index));
189+ break;
190+ case V4SImode:
191+ emit_insn (gen_neon_vset_lanev4si (target, x, target, index));
192+ break;
193+ case V2SFmode:
194+ emit_insn (gen_neon_vset_lanev2sf (target, x, target, index));
195+ break;
196+ case V4SFmode:
197+ emit_insn (gen_neon_vset_lanev4sf (target, x, target, index));
198+ break;
199+ case V2DImode:
200+ emit_insn (gen_neon_vset_lanev2di (target, x, target, index));
201+ break;
202+ default:
203+ gcc_unreachable ();
204+ }
205 return;
206 }
207
208
209=== modified file 'gcc/config/arm/arm.md'
210--- old/gcc/config/arm/arm.md 2010-04-02 18:54:46 +0000
211+++ new/gcc/config/arm/arm.md 2010-07-29 15:59:12 +0000
212@@ -497,9 +497,10 @@
213 (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
214 (match_operand:DI 2 "s_register_operand" "r, 0")))
215 (clobber (reg:CC CC_REGNUM))]
216- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
217+ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"
218 "#"
219- "TARGET_32BIT && reload_completed"
220+ "TARGET_32BIT && reload_completed
221+ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))"
222 [(parallel [(set (reg:CC_C CC_REGNUM)
223 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
224 (match_dup 1)))
225@@ -997,7 +998,7 @@
226 (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0")
227 (match_operand:DI 2 "s_register_operand" "r,0,0")))
228 (clobber (reg:CC CC_REGNUM))]
229- "TARGET_32BIT"
230+ "TARGET_32BIT && !TARGET_NEON"
231 "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"
232 [(set_attr "conds" "clob")
233 (set_attr "length" "8")]
234@@ -1784,6 +1785,7 @@
235 [(match_operand:DI 1 "s_register_operand" "")
236 (match_operand:DI 2 "s_register_operand" "")]))]
237 "TARGET_32BIT && reload_completed
238+ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))
239 && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
240 [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
241 (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
242@@ -1857,11 +1859,19 @@
243 }"
244 )
245
246-(define_insn "anddi3"
247+(define_expand "anddi3"
248+ [(set (match_operand:DI 0 "s_register_operand" "")
249+ (and:DI (match_operand:DI 1 "s_register_operand" "")
250+ (match_operand:DI 2 "neon_inv_logic_op2" "")))]
251+ "TARGET_32BIT"
252+ ""
253+)
254+
255+(define_insn "*anddi3_insn"
256 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
257 (and:DI (match_operand:DI 1 "s_register_operand" "%0,r")
258 (match_operand:DI 2 "s_register_operand" "r,r")))]
259- "TARGET_32BIT && ! TARGET_IWMMXT"
260+ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
261 "#"
262 [(set_attr "length" "8")]
263 )
264@@ -2461,7 +2471,9 @@
265 (match_operand:DI 2 "s_register_operand" "r,0")))]
266 "TARGET_32BIT"
267 "#"
268- "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
269+ "TARGET_32BIT && reload_completed
270+ && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))
271+ && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
272 [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2)))
273 (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))]
274 "
275@@ -2585,11 +2597,19 @@
276 [(set_attr "conds" "set")]
277 )
278
279-(define_insn "iordi3"
280+(define_expand "iordi3"
281+ [(set (match_operand:DI 0 "s_register_operand" "")
282+ (ior:DI (match_operand:DI 1 "s_register_operand" "")
283+ (match_operand:DI 2 "neon_logic_op2" "")))]
284+ "TARGET_32BIT"
285+ ""
286+)
287+
288+(define_insn "*iordi3_insn"
289 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
290 (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r")
291 (match_operand:DI 2 "s_register_operand" "r,r")))]
292- "TARGET_32BIT && ! TARGET_IWMMXT"
293+ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
294 "#"
295 [(set_attr "length" "8")
296 (set_attr "predicable" "yes")]
297@@ -2715,11 +2735,19 @@
298 [(set_attr "conds" "set")]
299 )
300
301-(define_insn "xordi3"
302+(define_expand "xordi3"
303+ [(set (match_operand:DI 0 "s_register_operand" "")
304+ (xor:DI (match_operand:DI 1 "s_register_operand" "")
305+ (match_operand:DI 2 "s_register_operand" "")))]
306+ "TARGET_32BIT"
307+ ""
308+)
309+
310+(define_insn "*xordi3_insn"
311 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
312 (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r")
313 (match_operand:DI 2 "s_register_operand" "r,r")))]
314- "TARGET_32BIT && !TARGET_IWMMXT"
315+ "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
316 "#"
317 [(set_attr "length" "8")
318 (set_attr "predicable" "yes")]
319
320=== modified file 'gcc/config/arm/arm_neon.h'
321--- old/gcc/config/arm/arm_neon.h 2009-11-03 17:58:59 +0000
322+++ new/gcc/config/arm/arm_neon.h 2010-07-29 15:59:12 +0000
323@@ -414,12 +414,6 @@
324 return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1);
325 }
326
327-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
328-vadd_s64 (int64x1_t __a, int64x1_t __b)
329-{
330- return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1);
331-}
332-
333 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
334 vadd_f32 (float32x2_t __a, float32x2_t __b)
335 {
336@@ -444,6 +438,12 @@
337 return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
338 }
339
340+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
341+vadd_s64 (int64x1_t __a, int64x1_t __b)
342+{
343+ return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1);
344+}
345+
346 __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
347 vadd_u64 (uint64x1_t __a, uint64x1_t __b)
348 {
349@@ -1368,12 +1368,6 @@
350 return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1);
351 }
352
353-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
354-vsub_s64 (int64x1_t __a, int64x1_t __b)
355-{
356- return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1);
357-}
358-
359 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
360 vsub_f32 (float32x2_t __a, float32x2_t __b)
361 {
362@@ -1398,6 +1392,12 @@
363 return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
364 }
365
366+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
367+vsub_s64 (int64x1_t __a, int64x1_t __b)
368+{
369+ return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1);
370+}
371+
372 __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
373 vsub_u64 (uint64x1_t __a, uint64x1_t __b)
374 {
375@@ -5808,12 +5808,6 @@
376 return (int32x2_t)__builtin_neon_vget_lowv4si (__a);
377 }
378
379-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
380-vget_low_s64 (int64x2_t __a)
381-{
382- return (int64x1_t)__builtin_neon_vget_lowv2di (__a);
383-}
384-
385 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
386 vget_low_f32 (float32x4_t __a)
387 {
388@@ -5838,12 +5832,6 @@
389 return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a);
390 }
391
392-__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
393-vget_low_u64 (uint64x2_t __a)
394-{
395- return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
396-}
397-
398 __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
399 vget_low_p8 (poly8x16_t __a)
400 {
401@@ -5856,6 +5844,18 @@
402 return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a);
403 }
404
405+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
406+vget_low_s64 (int64x2_t __a)
407+{
408+ return (int64x1_t)__builtin_neon_vget_lowv2di (__a);
409+}
410+
411+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
412+vget_low_u64 (uint64x2_t __a)
413+{
414+ return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a);
415+}
416+
417 __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
418 vcvt_s32_f32 (float32x2_t __a)
419 {
420@@ -10386,12 +10386,6 @@
421 return (int32x2_t)__builtin_neon_vandv2si (__a, __b, 1);
422 }
423
424-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
425-vand_s64 (int64x1_t __a, int64x1_t __b)
426-{
427- return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1);
428-}
429-
430 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
431 vand_u8 (uint8x8_t __a, uint8x8_t __b)
432 {
433@@ -10410,6 +10404,12 @@
434 return (uint32x2_t)__builtin_neon_vandv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
435 }
436
437+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
438+vand_s64 (int64x1_t __a, int64x1_t __b)
439+{
440+ return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1);
441+}
442+
443 __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
444 vand_u64 (uint64x1_t __a, uint64x1_t __b)
445 {
446@@ -10482,12 +10482,6 @@
447 return (int32x2_t)__builtin_neon_vorrv2si (__a, __b, 1);
448 }
449
450-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
451-vorr_s64 (int64x1_t __a, int64x1_t __b)
452-{
453- return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1);
454-}
455-
456 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
457 vorr_u8 (uint8x8_t __a, uint8x8_t __b)
458 {
459@@ -10506,6 +10500,12 @@
460 return (uint32x2_t)__builtin_neon_vorrv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
461 }
462
463+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
464+vorr_s64 (int64x1_t __a, int64x1_t __b)
465+{
466+ return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1);
467+}
468+
469 __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
470 vorr_u64 (uint64x1_t __a, uint64x1_t __b)
471 {
472@@ -10578,12 +10578,6 @@
473 return (int32x2_t)__builtin_neon_veorv2si (__a, __b, 1);
474 }
475
476-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
477-veor_s64 (int64x1_t __a, int64x1_t __b)
478-{
479- return (int64x1_t)__builtin_neon_veordi (__a, __b, 1);
480-}
481-
482 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
483 veor_u8 (uint8x8_t __a, uint8x8_t __b)
484 {
485@@ -10602,6 +10596,12 @@
486 return (uint32x2_t)__builtin_neon_veorv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
487 }
488
489+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
490+veor_s64 (int64x1_t __a, int64x1_t __b)
491+{
492+ return (int64x1_t)__builtin_neon_veordi (__a, __b, 1);
493+}
494+
495 __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
496 veor_u64 (uint64x1_t __a, uint64x1_t __b)
497 {
498@@ -10674,12 +10674,6 @@
499 return (int32x2_t)__builtin_neon_vbicv2si (__a, __b, 1);
500 }
501
502-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
503-vbic_s64 (int64x1_t __a, int64x1_t __b)
504-{
505- return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1);
506-}
507-
508 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
509 vbic_u8 (uint8x8_t __a, uint8x8_t __b)
510 {
511@@ -10698,6 +10692,12 @@
512 return (uint32x2_t)__builtin_neon_vbicv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
513 }
514
515+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
516+vbic_s64 (int64x1_t __a, int64x1_t __b)
517+{
518+ return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1);
519+}
520+
521 __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
522 vbic_u64 (uint64x1_t __a, uint64x1_t __b)
523 {
524@@ -10770,12 +10770,6 @@
525 return (int32x2_t)__builtin_neon_vornv2si (__a, __b, 1);
526 }
527
528-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
529-vorn_s64 (int64x1_t __a, int64x1_t __b)
530-{
531- return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1);
532-}
533-
534 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
535 vorn_u8 (uint8x8_t __a, uint8x8_t __b)
536 {
537@@ -10794,6 +10788,12 @@
538 return (uint32x2_t)__builtin_neon_vornv2si ((int32x2_t) __a, (int32x2_t) __b, 0);
539 }
540
541+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
542+vorn_s64 (int64x1_t __a, int64x1_t __b)
543+{
544+ return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1);
545+}
546+
547 __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
548 vorn_u64 (uint64x1_t __a, uint64x1_t __b)
549 {
550
551=== modified file 'gcc/config/arm/neon.md'
552--- old/gcc/config/arm/neon.md 2009-11-11 14:23:03 +0000
553+++ new/gcc/config/arm/neon.md 2010-07-29 15:59:12 +0000
554@@ -22,17 +22,12 @@
555 (define_constants
556 [(UNSPEC_ASHIFT_SIGNED 65)
557 (UNSPEC_ASHIFT_UNSIGNED 66)
558- (UNSPEC_VABA 67)
559- (UNSPEC_VABAL 68)
560 (UNSPEC_VABD 69)
561 (UNSPEC_VABDL 70)
562- (UNSPEC_VABS 71)
563 (UNSPEC_VADD 72)
564 (UNSPEC_VADDHN 73)
565 (UNSPEC_VADDL 74)
566 (UNSPEC_VADDW 75)
567- (UNSPEC_VAND 76)
568- (UNSPEC_VBIC 77)
569 (UNSPEC_VBSL 78)
570 (UNSPEC_VCAGE 79)
571 (UNSPEC_VCAGT 80)
572@@ -40,18 +35,9 @@
573 (UNSPEC_VCGE 82)
574 (UNSPEC_VCGT 83)
575 (UNSPEC_VCLS 84)
576- (UNSPEC_VCLZ 85)
577- (UNSPEC_VCNT 86)
578- (UNSPEC_VCOMBINE 87)
579 (UNSPEC_VCVT 88)
580 (UNSPEC_VCVT_N 89)
581- (UNSPEC_VDUP_LANE 90)
582- (UNSPEC_VDUP_N 91)
583- (UNSPEC_VEOR 92)
584 (UNSPEC_VEXT 93)
585- (UNSPEC_VGET_HIGH 94)
586- (UNSPEC_VGET_LANE 95)
587- (UNSPEC_VGET_LOW 96)
588 (UNSPEC_VHADD 97)
589 (UNSPEC_VHSUB 98)
590 (UNSPEC_VLD1 99)
591@@ -86,10 +72,6 @@
592 (UNSPEC_VMULL 128)
593 (UNSPEC_VMUL_LANE 129)
594 (UNSPEC_VMULL_LANE 130)
595- (UNSPEC_VMUL_N 131)
596- (UNSPEC_VMVN 132)
597- (UNSPEC_VORN 133)
598- (UNSPEC_VORR 134)
599 (UNSPEC_VPADAL 135)
600 (UNSPEC_VPADD 136)
601 (UNSPEC_VPADDL 137)
602@@ -125,7 +107,6 @@
603 (UNSPEC_VREV64 167)
604 (UNSPEC_VRSQRTE 168)
605 (UNSPEC_VRSQRTS 169)
606- (UNSPEC_VSET_LANE 170)
607 (UNSPEC_VSHL 171)
608 (UNSPEC_VSHLL_N 172)
609 (UNSPEC_VSHL_N 173)
610@@ -335,6 +316,14 @@
611 (V4HI "V2SI") (V8HI "V4SI")
612 (V2SI "DI") (V4SI "V2DI")])
613
614+;; Double-sized modes with the same element size.
615+;; Used for neon_vdup_lane, where the second operand is double-sized
616+;; even when the first one is quad.
617+(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
618+ (V4SI "V2SI") (V4SF "V2SF")
619+ (V8QI "V8QI") (V4HI "V4HI")
620+ (V2SI "V2SI") (V2SF "V2SF")])
621+
622 ;; Mode of result of comparison operations (and bit-select operand 1).
623 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
624 (V4HI "V4HI") (V8HI "V8HI")
625@@ -688,7 +677,7 @@
626 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
627 operands[2] = GEN_INT (elt);
628
629- return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
630+ return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
631 }
632 [(set_attr "predicable" "yes")
633 (set_attr "neon_type" "neon_mcr")])
634@@ -714,7 +703,7 @@
635 operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
636 operands[2] = GEN_INT (elt);
637
638- return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
639+ return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
640 }
641 [(set_attr "predicable" "yes")
642 (set_attr "neon_type" "neon_mcr")]
643@@ -734,7 +723,7 @@
644
645 operands[0] = gen_rtx_REG (DImode, regno);
646
647- return "vmov%?.64\t%P0, %Q1, %R1";
648+ return "vmov%?\t%P0, %Q1, %R1";
649 }
650 [(set_attr "predicable" "yes")
651 (set_attr "neon_type" "neon_mcr_2_mcrr")]
652@@ -802,11 +791,11 @@
653 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
654 "TARGET_NEON"
655 {
656- int regno = REGNO (operands[1]) + INTVAL (operands[2]);
657+ int regno = REGNO (operands[1]) + 2 * INTVAL (operands[2]);
658
659 operands[1] = gen_rtx_REG (DImode, regno);
660
661- return "vmov%?.64\t%Q0, %R0, %P1";
662+ return "vmov%?\t%Q0, %R0, %P1 @ v2di";
663 }
664 [(set_attr "predicable" "yes")
665 (set_attr "neon_type" "neon_int_1")]
666@@ -823,11 +812,8 @@
667
668 ;; Doubleword and quadword arithmetic.
669
670-;; NOTE: vadd/vsub and some other instructions also support 64-bit integer
671-;; element size, which we could potentially use for "long long" operations. We
672-;; don't want to do this at present though, because moving values from the
673-;; vector unit to the ARM core is currently slow and 64-bit addition (etc.) is
674-;; easy to do with ARM instructions anyway.
675+;; NOTE: some other instructions also support 64-bit integer
676+;; element size, which we could potentially use for "long long" operations.
677
678 (define_insn "*add<mode>3_neon"
679 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
680@@ -843,6 +829,26 @@
681 (const_string "neon_int_1")))]
682 )
683
684+(define_insn "adddi3_neon"
685+ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
686+ (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0")
687+ (match_operand:DI 2 "s_register_operand" "w,r,0")))
688+ (clobber (reg:CC CC_REGNUM))]
689+ "TARGET_NEON"
690+{
691+ switch (which_alternative)
692+ {
693+ case 0: return "vadd.i64\t%P0, %P1, %P2";
694+ case 1: return "#";
695+ case 2: return "#";
696+ default: gcc_unreachable ();
697+ }
698+}
699+ [(set_attr "neon_type" "neon_int_1,*,*")
700+ (set_attr "conds" "*,clob,clob")
701+ (set_attr "length" "*,8,8")]
702+)
703+
704 (define_insn "*sub<mode>3_neon"
705 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
706 (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
707@@ -857,6 +863,27 @@
708 (const_string "neon_int_2")))]
709 )
710
711+(define_insn "subdi3_neon"
712+ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
713+ (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0")
714+ (match_operand:DI 2 "s_register_operand" "w,r,0,0")))
715+ (clobber (reg:CC CC_REGNUM))]
716+ "TARGET_NEON"
717+{
718+ switch (which_alternative)
719+ {
720+ case 0: return "vsub.i64\t%P0, %P1, %P2";
721+ case 1: /* fall through */
722+ case 2: /* fall through */
723+ case 3: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2";
724+ default: gcc_unreachable ();
725+ }
726+}
727+ [(set_attr "neon_type" "neon_int_2,*,*,*")
728+ (set_attr "conds" "*,clob,clob,clob")
729+ (set_attr "length" "*,8,8,8")]
730+)
731+
732 (define_insn "*mul<mode>3_neon"
733 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
734 (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
735@@ -878,7 +905,7 @@
736 (const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
737 )
738
739-(define_insn "*mul<mode>3add<mode>_neon"
740+(define_insn "mul<mode>3add<mode>_neon"
741 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
742 (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
743 (match_operand:VDQ 3 "s_register_operand" "w"))
744@@ -900,7 +927,7 @@
745 (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
746 )
747
748-(define_insn "*mul<mode>3neg<mode>add<mode>_neon"
749+(define_insn "mul<mode>3neg<mode>add<mode>_neon"
750 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
751 (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
752 (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
753@@ -940,10 +967,9 @@
754 )
755
756 (define_insn "iordi3_neon"
757- [(set (match_operand:DI 0 "s_register_operand" "=w,w")
758- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0")
759- (match_operand:DI 2 "neon_logic_op2" "w,Dl")]
760- UNSPEC_VORR))]
761+ [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
762+ (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
763+ (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))]
764 "TARGET_NEON"
765 {
766 switch (which_alternative)
767@@ -951,10 +977,13 @@
768 case 0: return "vorr\t%P0, %P1, %P2";
769 case 1: return neon_output_logic_immediate ("vorr", &operands[2],
770 DImode, 0, VALID_NEON_QREG_MODE (DImode));
771+ case 2: return "#";
772+ case 3: return "#";
773 default: gcc_unreachable ();
774 }
775 }
776- [(set_attr "neon_type" "neon_int_1")]
777+ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
778+ (set_attr "length" "*,*,8,8")]
779 )
780
781 ;; The concrete forms of the Neon immediate-logic instructions are vbic and
782@@ -980,10 +1009,9 @@
783 )
784
785 (define_insn "anddi3_neon"
786- [(set (match_operand:DI 0 "s_register_operand" "=w,w")
787- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0")
788- (match_operand:DI 2 "neon_inv_logic_op2" "w,DL")]
789- UNSPEC_VAND))]
790+ [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
791+ (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
792+ (match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))]
793 "TARGET_NEON"
794 {
795 switch (which_alternative)
796@@ -991,10 +1019,13 @@
797 case 0: return "vand\t%P0, %P1, %P2";
798 case 1: return neon_output_logic_immediate ("vand", &operands[2],
799 DImode, 1, VALID_NEON_QREG_MODE (DImode));
800+ case 2: return "#";
801+ case 3: return "#";
802 default: gcc_unreachable ();
803 }
804 }
805- [(set_attr "neon_type" "neon_int_1")]
806+ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
807+ (set_attr "length" "*,*,8,8")]
808 )
809
810 (define_insn "orn<mode>3_neon"
811@@ -1007,13 +1038,16 @@
812 )
813
814 (define_insn "orndi3_neon"
815- [(set (match_operand:DI 0 "s_register_operand" "=w")
816- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
817- (match_operand:DI 2 "s_register_operand" "w")]
818- UNSPEC_VORN))]
819+ [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
820+ (ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0")
821+ (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))]
822 "TARGET_NEON"
823- "vorn\t%P0, %P1, %P2"
824- [(set_attr "neon_type" "neon_int_1")]
825+ "@
826+ vorn\t%P0, %P1, %P2
827+ #
828+ #"
829+ [(set_attr "neon_type" "neon_int_1,*,*")
830+ (set_attr "length" "*,8,8")]
831 )
832
833 (define_insn "bic<mode>3_neon"
834@@ -1025,14 +1059,18 @@
835 [(set_attr "neon_type" "neon_int_1")]
836 )
837
838+;; Compare to *anddi_notdi_di.
839 (define_insn "bicdi3_neon"
840- [(set (match_operand:DI 0 "s_register_operand" "=w")
841- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
842- (match_operand:DI 2 "s_register_operand" "w")]
843- UNSPEC_VBIC))]
844+ [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
845+ (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0"))
846+ (match_operand:DI 1 "s_register_operand" "w,0,r")))]
847 "TARGET_NEON"
848- "vbic\t%P0, %P1, %P2"
849- [(set_attr "neon_type" "neon_int_1")]
850+ "@
851+ vbic\t%P0, %P1, %P2
852+ #
853+ #"
854+ [(set_attr "neon_type" "neon_int_1,*,*")
855+ (set_attr "length" "*,8,8")]
856 )
857
858 (define_insn "xor<mode>3"
859@@ -1045,13 +1083,16 @@
860 )
861
862 (define_insn "xordi3_neon"
863- [(set (match_operand:DI 0 "s_register_operand" "=w")
864- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
865- (match_operand:DI 2 "s_register_operand" "w")]
866- UNSPEC_VEOR))]
867+ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
868+ (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r")
869+ (match_operand:DI 2 "s_register_operand" "w,r,r")))]
870 "TARGET_NEON"
871- "veor\t%P0, %P1, %P2"
872- [(set_attr "neon_type" "neon_int_1")]
873+ "@
874+ veor\t%P0, %P1, %P2
875+ #
876+ #"
877+ [(set_attr "neon_type" "neon_int_1,*,*")
878+ (set_attr "length" "*,8,8")]
879 )
880
881 (define_insn "one_cmpl<mode>2"
882@@ -1711,11 +1752,37 @@
883
884 ; good for plain vadd, vaddq.
885
886-(define_insn "neon_vadd<mode>"
887+(define_expand "neon_vadd<mode>"
888+ [(match_operand:VDQX 0 "s_register_operand" "=w")
889+ (match_operand:VDQX 1 "s_register_operand" "w")
890+ (match_operand:VDQX 2 "s_register_operand" "w")
891+ (match_operand:SI 3 "immediate_operand" "i")]
892+ "TARGET_NEON"
893+{
894+ if (!<Is_float_mode> || flag_unsafe_math_optimizations)
895+ emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[2]));
896+ else
897+ emit_insn (gen_neon_vadd<mode>_unspec (operands[0], operands[1],
898+ operands[2]));
899+ DONE;
900+})
901+
902+; Note that NEON operations don't support the full IEEE 754 standard: in
903+; particular, denormal values are flushed to zero. This means that GCC cannot
904+; use those instructions for autovectorization, etc. unless
905+; -funsafe-math-optimizations is in effect (in which case flush-to-zero
906+; behaviour is permissible). Intrinsic operations (provided by the arm_neon.h
907+; header) must work in either case: if -funsafe-math-optimizations is given,
908+; intrinsics expand to "canonical" RTL where possible, otherwise intrinsics
909+; expand to unspecs (which may potentially limit the extent to which they might
910+; be optimized by generic code).
911+
912+; Used for intrinsics when flag_unsafe_math_optimizations is false.
913+
914+(define_insn "neon_vadd<mode>_unspec"
915 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
916 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
917- (match_operand:VDQX 2 "s_register_operand" "w")
918- (match_operand:SI 3 "immediate_operand" "i")]
919+ (match_operand:VDQX 2 "s_register_operand" "w")]
920 UNSPEC_VADD))]
921 "TARGET_NEON"
922 "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
923@@ -1788,6 +1855,8 @@
924 [(set_attr "neon_type" "neon_int_4")]
925 )
926
927+;; We cannot replace this unspec with mul<mode>3 because of the odd
928+;; polynomial multiplication case that can specified by operand 3.
929 (define_insn "neon_vmul<mode>"
930 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
931 (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
932@@ -1811,13 +1880,31 @@
933 (const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
934 )
935
936-(define_insn "neon_vmla<mode>"
937- [(set (match_operand:VDQW 0 "s_register_operand" "=w")
938- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
939- (match_operand:VDQW 2 "s_register_operand" "w")
940- (match_operand:VDQW 3 "s_register_operand" "w")
941- (match_operand:SI 4 "immediate_operand" "i")]
942- UNSPEC_VMLA))]
943+(define_expand "neon_vmla<mode>"
944+ [(match_operand:VDQW 0 "s_register_operand" "=w")
945+ (match_operand:VDQW 1 "s_register_operand" "0")
946+ (match_operand:VDQW 2 "s_register_operand" "w")
947+ (match_operand:VDQW 3 "s_register_operand" "w")
948+ (match_operand:SI 4 "immediate_operand" "i")]
949+ "TARGET_NEON"
950+{
951+ if (!<Is_float_mode> || flag_unsafe_math_optimizations)
952+ emit_insn (gen_mul<mode>3add<mode>_neon (operands[0], operands[1],
953+ operands[2], operands[3]));
954+ else
955+ emit_insn (gen_neon_vmla<mode>_unspec (operands[0], operands[1],
956+ operands[2], operands[3]));
957+ DONE;
958+})
959+
960+; Used for intrinsics when flag_unsafe_math_optimizations is false.
961+
962+(define_insn "neon_vmla<mode>_unspec"
963+ [(set (match_operand:VDQ 0 "s_register_operand" "=w")
964+ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0")
965+ (match_operand:VDQ 2 "s_register_operand" "w")
966+ (match_operand:VDQ 3 "s_register_operand" "w")]
967+ UNSPEC_VMLA))]
968 "TARGET_NEON"
969 "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
970 [(set (attr "neon_type")
971@@ -1850,13 +1937,31 @@
972 (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
973 )
974
975-(define_insn "neon_vmls<mode>"
976- [(set (match_operand:VDQW 0 "s_register_operand" "=w")
977- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
978- (match_operand:VDQW 2 "s_register_operand" "w")
979- (match_operand:VDQW 3 "s_register_operand" "w")
980- (match_operand:SI 4 "immediate_operand" "i")]
981- UNSPEC_VMLS))]
982+(define_expand "neon_vmls<mode>"
983+ [(match_operand:VDQW 0 "s_register_operand" "=w")
984+ (match_operand:VDQW 1 "s_register_operand" "0")
985+ (match_operand:VDQW 2 "s_register_operand" "w")
986+ (match_operand:VDQW 3 "s_register_operand" "w")
987+ (match_operand:SI 4 "immediate_operand" "i")]
988+ "TARGET_NEON"
989+{
990+ if (!<Is_float_mode> || flag_unsafe_math_optimizations)
991+ emit_insn (gen_mul<mode>3neg<mode>add<mode>_neon (operands[0],
992+ operands[1], operands[2], operands[3]));
993+ else
994+ emit_insn (gen_neon_vmls<mode>_unspec (operands[0], operands[1],
995+ operands[2], operands[3]));
996+ DONE;
997+})
998+
999+; Used for intrinsics when flag_unsafe_math_optimizations is false.
1000+
1001+(define_insn "neon_vmls<mode>_unspec"
1002+ [(set (match_operand:VDQ 0 "s_register_operand" "=w")
1003+ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0")
1004+ (match_operand:VDQ 2 "s_register_operand" "w")
1005+ (match_operand:VDQ 3 "s_register_operand" "w")]
1006+ UNSPEC_VMLS))]
1007 "TARGET_NEON"
1008 "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
1009 [(set (attr "neon_type")
1010@@ -1966,11 +2071,27 @@
1011 (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
1012 )
1013
1014-(define_insn "neon_vsub<mode>"
1015+(define_expand "neon_vsub<mode>"
1016+ [(match_operand:VDQX 0 "s_register_operand" "=w")
1017+ (match_operand:VDQX 1 "s_register_operand" "w")
1018+ (match_operand:VDQX 2 "s_register_operand" "w")
1019+ (match_operand:SI 3 "immediate_operand" "i")]
1020+ "TARGET_NEON"
1021+{
1022+ if (!<Is_float_mode> || flag_unsafe_math_optimizations)
1023+ emit_insn (gen_sub<mode>3 (operands[0], operands[1], operands[2]));
1024+ else
1025+ emit_insn (gen_neon_vsub<mode>_unspec (operands[0], operands[1],
1026+ operands[2]));
1027+ DONE;
1028+})
1029+
1030+; Used for intrinsics when flag_unsafe_math_optimizations is false.
1031+
1032+(define_insn "neon_vsub<mode>_unspec"
1033 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
1034 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")
1035- (match_operand:VDQX 2 "s_register_operand" "w")
1036- (match_operand:SI 3 "immediate_operand" "i")]
1037+ (match_operand:VDQX 2 "s_register_operand" "w")]
1038 UNSPEC_VSUB))]
1039 "TARGET_NEON"
1040 "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1041@@ -2153,11 +2274,11 @@
1042
1043 (define_insn "neon_vaba<mode>"
1044 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
1045- (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "0")
1046- (match_operand:VDQIW 2 "s_register_operand" "w")
1047- (match_operand:VDQIW 3 "s_register_operand" "w")
1048- (match_operand:SI 4 "immediate_operand" "i")]
1049- UNSPEC_VABA))]
1050+ (plus:VDQIW (match_operand:VDQIW 1 "s_register_operand" "0")
1051+ (unspec:VDQIW [(match_operand:VDQIW 2 "s_register_operand" "w")
1052+ (match_operand:VDQIW 3 "s_register_operand" "w")
1053+ (match_operand:SI 4 "immediate_operand" "i")]
1054+ UNSPEC_VABD)))]
1055 "TARGET_NEON"
1056 "vaba.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
1057 [(set (attr "neon_type")
1058@@ -2167,11 +2288,11 @@
1059
1060 (define_insn "neon_vabal<mode>"
1061 [(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
1062- (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
1063- (match_operand:VW 2 "s_register_operand" "w")
1064- (match_operand:VW 3 "s_register_operand" "w")
1065- (match_operand:SI 4 "immediate_operand" "i")]
1066- UNSPEC_VABAL))]
1067+ (plus:<V_widen> (match_operand:<V_widen> 1 "s_register_operand" "0")
1068+ (unspec:<V_widen> [(match_operand:VW 2 "s_register_operand" "w")
1069+ (match_operand:VW 3 "s_register_operand" "w")
1070+ (match_operand:SI 4 "immediate_operand" "i")]
1071+ UNSPEC_VABDL)))]
1072 "TARGET_NEON"
1073 "vabal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
1074 [(set_attr "neon_type" "neon_vaba")]
1075@@ -2302,22 +2423,15 @@
1076 (const_string "neon_fp_vrecps_vrsqrts_qqq")))]
1077 )
1078
1079-(define_insn "neon_vabs<mode>"
1080- [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1081- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w")
1082- (match_operand:SI 2 "immediate_operand" "i")]
1083- UNSPEC_VABS))]
1084+(define_expand "neon_vabs<mode>"
1085+ [(match_operand:VDQW 0 "s_register_operand" "")
1086+ (match_operand:VDQW 1 "s_register_operand" "")
1087+ (match_operand:SI 2 "immediate_operand" "")]
1088 "TARGET_NEON"
1089- "vabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
1090- [(set (attr "neon_type")
1091- (if_then_else (ior (ne (symbol_ref "<Is_float_mode>") (const_int 0))
1092- (ne (symbol_ref "<Is_float_mode>") (const_int 0)))
1093- (if_then_else
1094- (ne (symbol_ref "<Is_d_reg>") (const_int 0))
1095- (const_string "neon_fp_vadd_ddd_vabs_dd")
1096- (const_string "neon_fp_vadd_qqq_vabs_qq"))
1097- (const_string "neon_vqneg_vqabs")))]
1098-)
1099+{
1100+ emit_insn (gen_abs<mode>2 (operands[0], operands[1]));
1101+ DONE;
1102+})
1103
1104 (define_insn "neon_vqabs<mode>"
1105 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
1106@@ -2359,26 +2473,42 @@
1107 [(set_attr "neon_type" "neon_int_1")]
1108 )
1109
1110-(define_insn "neon_vclz<mode>"
1111+(define_insn "clz<mode>2"
1112 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
1113- (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
1114- (match_operand:SI 2 "immediate_operand" "i")]
1115- UNSPEC_VCLZ))]
1116+ (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")))]
1117 "TARGET_NEON"
1118 "vclz.<V_if_elem>\t%<V_reg>0, %<V_reg>1"
1119 [(set_attr "neon_type" "neon_int_1")]
1120 )
1121
1122-(define_insn "neon_vcnt<mode>"
1123+(define_expand "neon_vclz<mode>"
1124+ [(match_operand:VDQIW 0 "s_register_operand" "")
1125+ (match_operand:VDQIW 1 "s_register_operand" "")
1126+ (match_operand:SI 2 "immediate_operand" "")]
1127+ "TARGET_NEON"
1128+{
1129+ emit_insn (gen_clz<mode>2 (operands[0], operands[1]));
1130+ DONE;
1131+})
1132+
1133+(define_insn "popcount<mode>2"
1134 [(set (match_operand:VE 0 "s_register_operand" "=w")
1135- (unspec:VE [(match_operand:VE 1 "s_register_operand" "w")
1136- (match_operand:SI 2 "immediate_operand" "i")]
1137- UNSPEC_VCNT))]
1138+ (popcount:VE (match_operand:VE 1 "s_register_operand" "w")))]
1139 "TARGET_NEON"
1140 "vcnt.<V_sz_elem>\t%<V_reg>0, %<V_reg>1"
1141 [(set_attr "neon_type" "neon_int_1")]
1142 )
1143
1144+(define_expand "neon_vcnt<mode>"
1145+ [(match_operand:VE 0 "s_register_operand" "=w")
1146+ (match_operand:VE 1 "s_register_operand" "w")
1147+ (match_operand:SI 2 "immediate_operand" "i")]
1148+ "TARGET_NEON"
1149+{
1150+ emit_insn (gen_popcount<mode>2 (operands[0], operands[1]));
1151+ DONE;
1152+})
1153+
1154 (define_insn "neon_vrecpe<mode>"
1155 [(set (match_operand:V32 0 "s_register_operand" "=w")
1156 (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w")
1157@@ -2555,126 +2685,65 @@
1158 ; Operand 3 (info word) is ignored because it does nothing useful with 64-bit
1159 ; elements.
1160
1161-(define_insn "neon_vget_lanedi"
1162- [(set (match_operand:DI 0 "s_register_operand" "=r")
1163- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
1164- (match_operand:SI 2 "immediate_operand" "i")
1165- (match_operand:SI 3 "immediate_operand" "i")]
1166- UNSPEC_VGET_LANE))]
1167+(define_expand "neon_vget_lanedi"
1168+ [(match_operand:DI 0 "s_register_operand" "=r")
1169+ (match_operand:DI 1 "s_register_operand" "w")
1170+ (match_operand:SI 2 "immediate_operand" "i")
1171+ (match_operand:SI 3 "immediate_operand" "i")]
1172 "TARGET_NEON"
1173 {
1174 neon_lane_bounds (operands[2], 0, 1);
1175- return "vmov%?\t%Q0, %R0, %P1 @ di";
1176-}
1177- [(set_attr "predicable" "yes")
1178- (set_attr "neon_type" "neon_bp_simple")]
1179-)
1180+ emit_move_insn (operands[0], operands[1]);
1181+ DONE;
1182+})
1183
1184-(define_insn "neon_vget_lanev2di"
1185- [(set (match_operand:DI 0 "s_register_operand" "=r")
1186- (unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w")
1187- (match_operand:SI 2 "immediate_operand" "i")
1188- (match_operand:SI 3 "immediate_operand" "i")]
1189- UNSPEC_VGET_LANE))]
1190+(define_expand "neon_vget_lanev2di"
1191+ [(match_operand:DI 0 "s_register_operand" "=r")
1192+ (match_operand:V2DI 1 "s_register_operand" "w")
1193+ (match_operand:SI 2 "immediate_operand" "i")
1194+ (match_operand:SI 3 "immediate_operand" "i")]
1195 "TARGET_NEON"
1196 {
1197- rtx ops[2];
1198- unsigned int regno = REGNO (operands[1]);
1199- unsigned int elt = INTVAL (operands[2]);
1200-
1201 neon_lane_bounds (operands[2], 0, 2);
1202-
1203- ops[0] = operands[0];
1204- ops[1] = gen_rtx_REG (DImode, regno + 2 * elt);
1205- output_asm_insn ("vmov%?\t%Q0, %R0, %P1 @ v2di", ops);
1206-
1207- return "";
1208-}
1209- [(set_attr "predicable" "yes")
1210- (set_attr "neon_type" "neon_bp_simple")]
1211-)
1212-
1213-(define_insn "neon_vset_lane<mode>"
1214- [(set (match_operand:VD 0 "s_register_operand" "=w")
1215- (unspec:VD [(match_operand:<V_elem> 1 "s_register_operand" "r")
1216- (match_operand:VD 2 "s_register_operand" "0")
1217- (match_operand:SI 3 "immediate_operand" "i")]
1218- UNSPEC_VSET_LANE))]
1219+ emit_insn (gen_vec_extractv2di (operands[0], operands[1], operands[2]));
1220+ DONE;
1221+})
1222+
1223+(define_expand "neon_vset_lane<mode>"
1224+ [(match_operand:VDQ 0 "s_register_operand" "=w")
1225+ (match_operand:<V_elem> 1 "s_register_operand" "r")
1226+ (match_operand:VDQ 2 "s_register_operand" "0")
1227+ (match_operand:SI 3 "immediate_operand" "i")]
1228 "TARGET_NEON"
1229 {
1230+ unsigned int elt = INTVAL (operands[3]);
1231 neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
1232- return "vmov%?.<V_sz_elem>\t%P0[%c3], %1";
1233-}
1234- [(set_attr "predicable" "yes")
1235- (set_attr "neon_type" "neon_bp_simple")]
1236-)
1237+
1238+ if (BYTES_BIG_ENDIAN)
1239+ {
1240+ unsigned int reg_nelts
1241+ = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
1242+ elt ^= reg_nelts - 1;
1243+ }
1244+
1245+ emit_insn (gen_vec_set<mode>_internal (operands[0], operands[1],
1246+ GEN_INT (1 << elt), operands[2]));
1247+ DONE;
1248+})
1249
1250 ; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored.
1251
1252-(define_insn "neon_vset_lanedi"
1253- [(set (match_operand:DI 0 "s_register_operand" "=w")
1254- (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")
1255- (match_operand:DI 2 "s_register_operand" "0")
1256- (match_operand:SI 3 "immediate_operand" "i")]
1257- UNSPEC_VSET_LANE))]
1258+(define_expand "neon_vset_lanedi"
1259+ [(match_operand:DI 0 "s_register_operand" "=w")
1260+ (match_operand:DI 1 "s_register_operand" "r")
1261+ (match_operand:DI 2 "s_register_operand" "0")
1262+ (match_operand:SI 3 "immediate_operand" "i")]
1263 "TARGET_NEON"
1264 {
1265 neon_lane_bounds (operands[3], 0, 1);
1266- return "vmov%?\t%P0, %Q1, %R1 @ di";
1267-}
1268- [(set_attr "predicable" "yes")
1269- (set_attr "neon_type" "neon_bp_simple")]
1270-)
1271-
1272-(define_insn "neon_vset_lane<mode>"
1273- [(set (match_operand:VQ 0 "s_register_operand" "=w")
1274- (unspec:VQ [(match_operand:<V_elem> 1 "s_register_operand" "r")
1275- (match_operand:VQ 2 "s_register_operand" "0")
1276- (match_operand:SI 3 "immediate_operand" "i")]
1277- UNSPEC_VSET_LANE))]
1278- "TARGET_NEON"
1279-{
1280- rtx ops[4];
1281- unsigned int regno = REGNO (operands[0]);
1282- unsigned int halfelts = GET_MODE_NUNITS (<MODE>mode) / 2;
1283- unsigned int elt = INTVAL (operands[3]);
1284-
1285- neon_lane_bounds (operands[3], 0, halfelts * 2);
1286-
1287- ops[0] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
1288- ops[1] = operands[1];
1289- ops[2] = GEN_INT (elt % halfelts);
1290- output_asm_insn ("vmov%?.<V_sz_elem>\t%P0[%c2], %1", ops);
1291-
1292- return "";
1293-}
1294- [(set_attr "predicable" "yes")
1295- (set_attr "neon_type" "neon_bp_simple")]
1296-)
1297-
1298-(define_insn "neon_vset_lanev2di"
1299- [(set (match_operand:V2DI 0 "s_register_operand" "=w")
1300- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")
1301- (match_operand:V2DI 2 "s_register_operand" "0")
1302- (match_operand:SI 3 "immediate_operand" "i")]
1303- UNSPEC_VSET_LANE))]
1304- "TARGET_NEON"
1305-{
1306- rtx ops[2];
1307- unsigned int regno = REGNO (operands[0]);
1308- unsigned int elt = INTVAL (operands[3]);
1309-
1310- neon_lane_bounds (operands[3], 0, 2);
1311-
1312- ops[0] = gen_rtx_REG (DImode, regno + 2 * elt);
1313- ops[1] = operands[1];
1314- output_asm_insn ("vmov%?\t%P0, %Q1, %R1 @ v2di", ops);
1315-
1316- return "";
1317-}
1318- [(set_attr "predicable" "yes")
1319- (set_attr "neon_type" "neon_bp_simple")]
1320-)
1321+ emit_move_insn (operands[0], operands[1]);
1322+ DONE;
1323+})
1324
1325 (define_expand "neon_vcreate<mode>"
1326 [(match_operand:VDX 0 "s_register_operand" "")
1327@@ -2688,8 +2757,7 @@
1328
1329 (define_insn "neon_vdup_n<mode>"
1330 [(set (match_operand:VX 0 "s_register_operand" "=w")
1331- (unspec:VX [(match_operand:<V_elem> 1 "s_register_operand" "r")]
1332- UNSPEC_VDUP_N))]
1333+ (vec_duplicate:VX (match_operand:<V_elem> 1 "s_register_operand" "r")))]
1334 "TARGET_NEON"
1335 "vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
1336 ;; Assume this schedules like vmov.
1337@@ -2699,8 +2767,7 @@
1338
1339 (define_insn "neon_vdup_n<mode>"
1340 [(set (match_operand:V32 0 "s_register_operand" "=w,w")
1341- (unspec:V32 [(match_operand:<V_elem> 1 "s_register_operand" "r,t")]
1342- UNSPEC_VDUP_N))]
1343+ (vec_duplicate:V32 (match_operand:<V_elem> 1 "s_register_operand" "r,t")))]
1344 "TARGET_NEON"
1345 "@
1346 vdup%?.<V_sz_elem>\t%<V_reg>0, %1
1347@@ -2710,61 +2777,76 @@
1348 (set_attr "neon_type" "neon_bp_simple")]
1349 )
1350
1351-(define_insn "neon_vdup_ndi"
1352- [(set (match_operand:DI 0 "s_register_operand" "=w")
1353- (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
1354- UNSPEC_VDUP_N))]
1355+(define_expand "neon_vdup_ndi"
1356+ [(match_operand:DI 0 "s_register_operand" "=w")
1357+ (match_operand:DI 1 "s_register_operand" "r")]
1358 "TARGET_NEON"
1359- "vmov%?\t%P0, %Q1, %R1"
1360- [(set_attr "predicable" "yes")
1361- (set_attr "neon_type" "neon_bp_simple")]
1362+{
1363+ emit_move_insn (operands[0], operands[1]);
1364+ DONE;
1365+}
1366 )
1367
1368 (define_insn "neon_vdup_nv2di"
1369- [(set (match_operand:V2DI 0 "s_register_operand" "=w")
1370- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")]
1371- UNSPEC_VDUP_N))]
1372+ [(set (match_operand:V2DI 0 "s_register_operand" "=w,w")
1373+ (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))]
1374 "TARGET_NEON"
1375- "vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1"
1376+ "@
1377+ vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1
1378+ vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1"
1379 [(set_attr "predicable" "yes")
1380 (set_attr "length" "8")
1381 (set_attr "neon_type" "neon_bp_simple")]
1382 )
1383
1384-(define_insn "neon_vdup_lane<mode>"
1385- [(set (match_operand:VD 0 "s_register_operand" "=w")
1386- (unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
1387- (match_operand:SI 2 "immediate_operand" "i")]
1388- UNSPEC_VDUP_LANE))]
1389+(define_insn "neon_vdup_lane<mode>_internal"
1390+ [(set (match_operand:VDQW 0 "s_register_operand" "=w")
1391+ (vec_duplicate:VDQW
1392+ (vec_select:<V_elem>
1393+ (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
1394+ (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
1395 "TARGET_NEON"
1396 {
1397- neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<MODE>mode));
1398- return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
1399+ if (BYTES_BIG_ENDIAN)
1400+ {
1401+ int elt = INTVAL (operands[2]);
1402+ elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt;
1403+ operands[2] = GEN_INT (elt);
1404+ }
1405+ if (<Is_d_reg>)
1406+ return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
1407+ else
1408+ return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
1409 }
1410 ;; Assume this schedules like vmov.
1411 [(set_attr "neon_type" "neon_bp_simple")]
1412 )
1413
1414-(define_insn "neon_vdup_lane<mode>"
1415- [(set (match_operand:VQ 0 "s_register_operand" "=w")
1416- (unspec:VQ [(match_operand:<V_HALF> 1 "s_register_operand" "w")
1417- (match_operand:SI 2 "immediate_operand" "i")]
1418- UNSPEC_VDUP_LANE))]
1419+(define_expand "neon_vdup_lane<mode>"
1420+ [(match_operand:VDQW 0 "s_register_operand" "=w")
1421+ (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
1422+ (match_operand:SI 2 "immediate_operand" "i")]
1423 "TARGET_NEON"
1424 {
1425- neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_HALF>mode));
1426- return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
1427-}
1428- ;; Assume this schedules like vmov.
1429- [(set_attr "neon_type" "neon_bp_simple")]
1430-)
1431+ neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_double_vector_mode>mode));
1432+ if (BYTES_BIG_ENDIAN)
1433+ {
1434+ unsigned int elt = INTVAL (operands[2]);
1435+ unsigned int reg_nelts
1436+ = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<V_double_vector_mode>mode));
1437+ elt ^= reg_nelts - 1;
1438+ operands[2] = GEN_INT (elt);
1439+ }
1440+ emit_insn (gen_neon_vdup_lane<mode>_internal (operands[0], operands[1],
1441+ operands[2]));
1442+ DONE;
1443+})
1444
1445 ; Scalar index is ignored, since only zero is valid here.
1446 (define_expand "neon_vdup_lanedi"
1447- [(set (match_operand:DI 0 "s_register_operand" "=w")
1448- (unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
1449- (match_operand:SI 2 "immediate_operand" "i")]
1450- UNSPEC_VDUP_LANE))]
1451+ [(match_operand:DI 0 "s_register_operand" "=w")
1452+ (match_operand:DI 1 "s_register_operand" "w")
1453+ (match_operand:SI 2 "immediate_operand" "i")]
1454 "TARGET_NEON"
1455 {
1456 neon_lane_bounds (operands[2], 0, 1);
1457@@ -2772,20 +2854,17 @@
1458 DONE;
1459 })
1460
1461-; Likewise.
1462-(define_insn "neon_vdup_lanev2di"
1463- [(set (match_operand:V2DI 0 "s_register_operand" "=w")
1464- (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w")
1465- (match_operand:SI 2 "immediate_operand" "i")]
1466- UNSPEC_VDUP_LANE))]
1467+; Likewise for v2di, as the DImode second operand has only a single element.
1468+(define_expand "neon_vdup_lanev2di"
1469+ [(match_operand:V2DI 0 "s_register_operand" "=w")
1470+ (match_operand:DI 1 "s_register_operand" "w")
1471+ (match_operand:SI 2 "immediate_operand" "i")]
1472 "TARGET_NEON"
1473 {
1474 neon_lane_bounds (operands[2], 0, 1);
1475- return "vmov\t%e0, %P1\;vmov\t%f0, %P1";
1476-}
1477- [(set_attr "length" "8")
1478- (set_attr "neon_type" "neon_bp_simple")]
1479-)
1480+ emit_insn (gen_neon_vdup_nv2di (operands[0], operands[1]));
1481+ DONE;
1482+})
1483
1484 ;; In this insn, operand 1 should be low, and operand 2 the high part of the
1485 ;; dest vector.
1486@@ -2796,9 +2875,8 @@
1487
1488 (define_insn "neon_vcombine<mode>"
1489 [(set (match_operand:<V_DOUBLE> 0 "s_register_operand" "=w")
1490- (unspec:<V_DOUBLE> [(match_operand:VDX 1 "s_register_operand" "w")
1491- (match_operand:VDX 2 "s_register_operand" "w")]
1492- UNSPEC_VCOMBINE))]
1493+ (vec_concat:<V_DOUBLE> (match_operand:VDX 1 "s_register_operand" "w")
1494+ (match_operand:VDX 2 "s_register_operand" "w")))]
1495 "TARGET_NEON"
1496 {
1497 int dest = REGNO (operands[0]);
1498@@ -2838,27 +2916,171 @@
1499 (set_attr "neon_type" "neon_bp_simple")]
1500 )
1501
1502-(define_insn "neon_vget_high<mode>"
1503- [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
1504- (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
1505- UNSPEC_VGET_HIGH))]
1506- "TARGET_NEON"
1507-{
1508- int dest = REGNO (operands[0]);
1509- int src = REGNO (operands[1]);
1510-
1511- if (dest != src + 2)
1512- return "vmov\t%P0, %f1";
1513- else
1514- return "";
1515-}
1516- [(set_attr "neon_type" "neon_bp_simple")]
1517-)
1518-
1519-(define_insn "neon_vget_low<mode>"
1520- [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
1521- (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
1522- UNSPEC_VGET_LOW))]
1523+(define_insn "neon_vget_highv16qi"
1524+ [(set (match_operand:V8QI 0 "s_register_operand" "=w")
1525+ (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
1526+ (parallel [(const_int 8) (const_int 9)
1527+ (const_int 10) (const_int 11)
1528+ (const_int 12) (const_int 13)
1529+ (const_int 14) (const_int 15)])))]
1530+ "TARGET_NEON"
1531+{
1532+ int dest = REGNO (operands[0]);
1533+ int src = REGNO (operands[1]);
1534+
1535+ if (dest != src + 2)
1536+ return "vmov\t%P0, %f1";
1537+ else
1538+ return "";
1539+}
1540+ [(set_attr "neon_type" "neon_bp_simple")]
1541+)
1542+
1543+(define_insn "neon_vget_highv8hi"
1544+ [(set (match_operand:V4HI 0 "s_register_operand" "=w")
1545+ (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
1546+ (parallel [(const_int 4) (const_int 5)
1547+ (const_int 6) (const_int 7)])))]
1548+ "TARGET_NEON"
1549+{
1550+ int dest = REGNO (operands[0]);
1551+ int src = REGNO (operands[1]);
1552+
1553+ if (dest != src + 2)
1554+ return "vmov\t%P0, %f1";
1555+ else
1556+ return "";
1557+}
1558+ [(set_attr "neon_type" "neon_bp_simple")]
1559+)
1560+
1561+(define_insn "neon_vget_highv4si"
1562+ [(set (match_operand:V2SI 0 "s_register_operand" "=w")
1563+ (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
1564+ (parallel [(const_int 2) (const_int 3)])))]
1565+ "TARGET_NEON"
1566+{
1567+ int dest = REGNO (operands[0]);
1568+ int src = REGNO (operands[1]);
1569+
1570+ if (dest != src + 2)
1571+ return "vmov\t%P0, %f1";
1572+ else
1573+ return "";
1574+}
1575+ [(set_attr "neon_type" "neon_bp_simple")]
1576+)
1577+
1578+(define_insn "neon_vget_highv4sf"
1579+ [(set (match_operand:V2SF 0 "s_register_operand" "=w")
1580+ (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
1581+ (parallel [(const_int 2) (const_int 3)])))]
1582+ "TARGET_NEON"
1583+{
1584+ int dest = REGNO (operands[0]);
1585+ int src = REGNO (operands[1]);
1586+
1587+ if (dest != src + 2)
1588+ return "vmov\t%P0, %f1";
1589+ else
1590+ return "";
1591+}
1592+ [(set_attr "neon_type" "neon_bp_simple")]
1593+)
1594+
1595+(define_insn "neon_vget_highv2di"
1596+ [(set (match_operand:DI 0 "s_register_operand" "=w")
1597+ (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
1598+ (parallel [(const_int 1)])))]
1599+ "TARGET_NEON"
1600+{
1601+ int dest = REGNO (operands[0]);
1602+ int src = REGNO (operands[1]);
1603+
1604+ if (dest != src + 2)
1605+ return "vmov\t%P0, %f1";
1606+ else
1607+ return "";
1608+}
1609+ [(set_attr "neon_type" "neon_bp_simple")]
1610+)
1611+
1612+(define_insn "neon_vget_lowv16qi"
1613+ [(set (match_operand:V8QI 0 "s_register_operand" "=w")
1614+ (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
1615+ (parallel [(const_int 0) (const_int 1)
1616+ (const_int 2) (const_int 3)
1617+ (const_int 4) (const_int 5)
1618+ (const_int 6) (const_int 7)])))]
1619+ "TARGET_NEON"
1620+{
1621+ int dest = REGNO (operands[0]);
1622+ int src = REGNO (operands[1]);
1623+
1624+ if (dest != src)
1625+ return "vmov\t%P0, %e1";
1626+ else
1627+ return "";
1628+}
1629+ [(set_attr "neon_type" "neon_bp_simple")]
1630+)
1631+
1632+(define_insn "neon_vget_lowv8hi"
1633+ [(set (match_operand:V4HI 0 "s_register_operand" "=w")
1634+ (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
1635+ (parallel [(const_int 0) (const_int 1)
1636+ (const_int 2) (const_int 3)])))]
1637+ "TARGET_NEON"
1638+{
1639+ int dest = REGNO (operands[0]);
1640+ int src = REGNO (operands[1]);
1641+
1642+ if (dest != src)
1643+ return "vmov\t%P0, %e1";
1644+ else
1645+ return "";
1646+}
1647+ [(set_attr "neon_type" "neon_bp_simple")]
1648+)
1649+
1650+(define_insn "neon_vget_lowv4si"
1651+ [(set (match_operand:V2SI 0 "s_register_operand" "=w")
1652+ (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
1653+ (parallel [(const_int 0) (const_int 1)])))]
1654+ "TARGET_NEON"
1655+{
1656+ int dest = REGNO (operands[0]);
1657+ int src = REGNO (operands[1]);
1658+
1659+ if (dest != src)
1660+ return "vmov\t%P0, %e1";
1661+ else
1662+ return "";
1663+}
1664+ [(set_attr "neon_type" "neon_bp_simple")]
1665+)
1666+
1667+(define_insn "neon_vget_lowv4sf"
1668+ [(set (match_operand:V2SF 0 "s_register_operand" "=w")
1669+ (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
1670+ (parallel [(const_int 0) (const_int 1)])))]
1671+ "TARGET_NEON"
1672+{
1673+ int dest = REGNO (operands[0]);
1674+ int src = REGNO (operands[1]);
1675+
1676+ if (dest != src)
1677+ return "vmov\t%P0, %e1";
1678+ else
1679+ return "";
1680+}
1681+ [(set_attr "neon_type" "neon_bp_simple")]
1682+)
1683+
1684+(define_insn "neon_vget_lowv2di"
1685+ [(set (match_operand:DI 0 "s_register_operand" "=w")
1686+ (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
1687+ (parallel [(const_int 0)])))]
1688 "TARGET_NEON"
1689 {
1690 int dest = REGNO (operands[0]);
1691
1692=== modified file 'gcc/config/arm/neon.ml'
1693--- old/gcc/config/arm/neon.ml 2010-01-19 14:21:14 +0000
1694+++ new/gcc/config/arm/neon.ml 2010-07-29 15:59:12 +0000
1695@@ -709,7 +709,8 @@
1696 let ops =
1697 [
1698 (* Addition. *)
1699- Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64;
1700+ Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32;
1701+ Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64];
1702 Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64;
1703 Vadd, [], Long, "vaddl", elts_same_2, su_8_32;
1704 Vadd, [], Wide, "vaddw", elts_same_2, su_8_32;
1705@@ -758,7 +759,8 @@
1706 Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32];
1707
1708 (* Subtraction. *)
1709- Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64;
1710+ Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32;
1711+ Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64];
1712 Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64;
1713 Vsub, [], Long, "vsubl", elts_same_2, su_8_32;
1714 Vsub, [], Wide, "vsubw", elts_same_2, su_8_32;
1715@@ -967,7 +969,8 @@
1716 Use_operands [| Corereg; Dreg; Immed |],
1717 "vget_lane", get_lane, pf_su_8_32;
1718 Vget_lane,
1719- [InfoWord;
1720+ [No_op;
1721+ InfoWord;
1722 Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
1723 Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
1724 Use_operands [| Corereg; Dreg; Immed |],
1725@@ -989,7 +992,8 @@
1726 Instruction_name ["vmov"]],
1727 Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
1728 set_lane, pf_su_8_32;
1729- Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
1730+ Vset_lane, [No_op;
1731+ Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
1732 Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
1733 Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
1734 set_lane_notype, [S64; U64];
1735@@ -1017,7 +1021,8 @@
1736 Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
1737 pf_su_8_32;
1738 Vdup_n,
1739- [Instruction_name ["vmov"];
1740+ [No_op;
1741+ Instruction_name ["vmov"];
1742 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
1743 Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
1744 [S64; U64];
1745@@ -1028,7 +1033,8 @@
1746 Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
1747 pf_su_8_32;
1748 Vdup_n,
1749- [Instruction_name ["vmov"];
1750+ [No_op;
1751+ Instruction_name ["vmov"];
1752 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
1753 Use_operands [| Dreg; Corereg; Corereg |]]],
1754 Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1,
1755@@ -1043,7 +1049,8 @@
1756 Use_operands [| Dreg; Corereg |],
1757 "vmov_n", bits_1, pf_su_8_32;
1758 Vmov_n,
1759- [Builtin_name "vdup_n";
1760+ [No_op;
1761+ Builtin_name "vdup_n";
1762 Instruction_name ["vmov"];
1763 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
1764 Use_operands [| Dreg; Corereg |],
1765@@ -1056,7 +1063,8 @@
1766 Use_operands [| Qreg; Corereg |],
1767 "vmovQ_n", bits_1, pf_su_8_32;
1768 Vmov_n,
1769- [Builtin_name "vdupQ_n";
1770+ [No_op;
1771+ Builtin_name "vdupQ_n";
1772 Instruction_name ["vmov"];
1773 Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
1774 Use_operands [| Dreg; Corereg; Corereg |]]],
1775@@ -1613,23 +1621,28 @@
1776 store_3, [P16; F32; U16; U32; S16; S32];
1777
1778 (* Logical operations. And. *)
1779- Vand, [], All (3, Dreg), "vand", notype_2, su_8_64;
1780+ Vand, [], All (3, Dreg), "vand", notype_2, su_8_32;
1781+ Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64];
1782 Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64;
1783
1784 (* Or. *)
1785- Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_64;
1786+ Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32;
1787+ Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64];
1788 Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64;
1789
1790 (* Eor. *)
1791- Veor, [], All (3, Dreg), "veor", notype_2, su_8_64;
1792+ Veor, [], All (3, Dreg), "veor", notype_2, su_8_32;
1793+ Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64];
1794 Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64;
1795
1796 (* Bic (And-not). *)
1797- Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_64;
1798+ Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_32;
1799+ Vbic, [No_op], All (3, Dreg), "vbic", notype_2, [S64; U64];
1800 Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64;
1801
1802 (* Or-not. *)
1803- Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_64;
1804+ Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_32;
1805+ Vorn, [No_op], All (3, Dreg), "vorn", notype_2, [S64; U64];
1806 Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64;
1807 ]
1808
1809
1810=== modified file 'gcc/config/arm/predicates.md'
1811--- old/gcc/config/arm/predicates.md 2009-07-15 09:12:22 +0000
1812+++ new/gcc/config/arm/predicates.md 2010-07-29 15:59:12 +0000
1813@@ -499,13 +499,15 @@
1814 (define_predicate "imm_for_neon_logic_operand"
1815 (match_code "const_vector")
1816 {
1817- return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL);
1818+ return (TARGET_NEON
1819+ && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
1820 })
1821
1822 (define_predicate "imm_for_neon_inv_logic_operand"
1823 (match_code "const_vector")
1824 {
1825- return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL);
1826+ return (TARGET_NEON
1827+ && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
1828 })
1829
1830 (define_predicate "neon_logic_op2"
1831
1832=== modified file 'gcc/doc/arm-neon-intrinsics.texi'
1833--- old/gcc/doc/arm-neon-intrinsics.texi 2009-11-18 17:06:46 +0000
1834+++ new/gcc/doc/arm-neon-intrinsics.texi 2010-07-29 15:59:12 +0000
1835@@ -43,20 +43,18 @@
1836
1837
1838 @itemize @bullet
1839+@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
1840+@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
1841+@end itemize
1842+
1843+
1844+@itemize @bullet
1845 @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
1846-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
1847 @end itemize
1848
1849
1850 @itemize @bullet
1851 @item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
1852-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
1853-@end itemize
1854-
1855-
1856-@itemize @bullet
1857-@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
1858-@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
1859 @end itemize
1860
1861
1862@@ -1013,20 +1011,18 @@
1863
1864
1865 @itemize @bullet
1866+@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1867+@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1868+@end itemize
1869+
1870+
1871+@itemize @bullet
1872 @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1873-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
1874 @end itemize
1875
1876
1877 @itemize @bullet
1878 @item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1879-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
1880-@end itemize
1881-
1882-
1883-@itemize @bullet
1884-@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1885-@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1886 @end itemize
1887
1888
1889@@ -4750,13 +4746,11 @@
1890
1891 @itemize @bullet
1892 @item uint64_t vget_lane_u64 (uint64x1_t, const int)
1893-@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
1894 @end itemize
1895
1896
1897 @itemize @bullet
1898 @item int64_t vget_lane_s64 (int64x1_t, const int)
1899-@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
1900 @end itemize
1901
1902
1903@@ -4886,13 +4880,11 @@
1904
1905 @itemize @bullet
1906 @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
1907-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1908 @end itemize
1909
1910
1911 @itemize @bullet
1912 @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
1913-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1914 @end itemize
1915
1916
1917@@ -5081,13 +5073,11 @@
1918
1919 @itemize @bullet
1920 @item uint64x1_t vdup_n_u64 (uint64_t)
1921-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1922 @end itemize
1923
1924
1925 @itemize @bullet
1926 @item int64x1_t vdup_n_s64 (int64_t)
1927-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1928 @end itemize
1929
1930
1931@@ -5147,13 +5137,11 @@
1932
1933 @itemize @bullet
1934 @item uint64x2_t vdupq_n_u64 (uint64_t)
1935-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1936 @end itemize
1937
1938
1939 @itemize @bullet
1940 @item int64x2_t vdupq_n_s64 (int64_t)
1941-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1942 @end itemize
1943
1944
1945@@ -5213,13 +5201,11 @@
1946
1947 @itemize @bullet
1948 @item uint64x1_t vmov_n_u64 (uint64_t)
1949-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1950 @end itemize
1951
1952
1953 @itemize @bullet
1954 @item int64x1_t vmov_n_s64 (int64_t)
1955-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1956 @end itemize
1957
1958
1959@@ -5279,13 +5265,11 @@
1960
1961 @itemize @bullet
1962 @item uint64x2_t vmovq_n_u64 (uint64_t)
1963-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1964 @end itemize
1965
1966
1967 @itemize @bullet
1968 @item int64x2_t vmovq_n_s64 (int64_t)
1969-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
1970 @end itemize
1971
1972
1973@@ -5572,18 +5556,6 @@
1974
1975
1976 @itemize @bullet
1977-@item uint64x1_t vget_low_u64 (uint64x2_t)
1978-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
1979-@end itemize
1980-
1981-
1982-@itemize @bullet
1983-@item int64x1_t vget_low_s64 (int64x2_t)
1984-@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
1985-@end itemize
1986-
1987-
1988-@itemize @bullet
1989 @item float32x2_t vget_low_f32 (float32x4_t)
1990 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
1991 @end itemize
1992@@ -5601,6 +5573,16 @@
1993 @end itemize
1994
1995
1996+@itemize @bullet
1997+@item uint64x1_t vget_low_u64 (uint64x2_t)
1998+@end itemize
1999+
2000+
2001+@itemize @bullet
2002+@item int64x1_t vget_low_s64 (int64x2_t)
2003+@end itemize
2004+
2005+
2006
2007
2008 @subsubsection Conversions
2009@@ -9727,13 +9709,11 @@
2010
2011 @itemize @bullet
2012 @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
2013-@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
2014 @end itemize
2015
2016
2017 @itemize @bullet
2018 @item int64x1_t vand_s64 (int64x1_t, int64x1_t)
2019-@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
2020 @end itemize
2021
2022
2023@@ -9827,13 +9807,11 @@
2024
2025 @itemize @bullet
2026 @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
2027-@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
2028 @end itemize
2029
2030
2031 @itemize @bullet
2032 @item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
2033-@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
2034 @end itemize
2035
2036
2037@@ -9927,13 +9905,11 @@
2038
2039 @itemize @bullet
2040 @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
2041-@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
2042 @end itemize
2043
2044
2045 @itemize @bullet
2046 @item int64x1_t veor_s64 (int64x1_t, int64x1_t)
2047-@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
2048 @end itemize
2049
2050
2051@@ -10027,13 +10003,11 @@
2052
2053 @itemize @bullet
2054 @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
2055-@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
2056 @end itemize
2057
2058
2059 @itemize @bullet
2060 @item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
2061-@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
2062 @end itemize
2063
2064
2065@@ -10127,13 +10101,11 @@
2066
2067 @itemize @bullet
2068 @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
2069-@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
2070 @end itemize
2071
2072
2073 @itemize @bullet
2074 @item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
2075-@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
2076 @end itemize
2077
2078
2079
2080=== added file 'gcc/testsuite/gcc.target/arm/neon-vadds64.c'
2081--- old/gcc/testsuite/gcc.target/arm/neon-vadds64.c 1970-01-01 00:00:00 +0000
2082+++ new/gcc/testsuite/gcc.target/arm/neon-vadds64.c 2010-07-29 15:59:12 +0000
2083@@ -0,0 +1,21 @@
2084+/* Test the `vadd_s64' ARM Neon intrinsic. */
2085+
2086+/* { dg-do run } */
2087+/* { dg-require-effective-target arm_neon_hw } */
2088+/* { dg-options "-O0" } */
2089+/* { dg-add-options arm_neon } */
2090+
2091+#include "arm_neon.h"
2092+#include <stdlib.h>
2093+
2094+int main (void)
2095+{
2096+ int64x1_t out_int64x1_t = 0;
2097+ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
2098+ int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL;
2099+
2100+ out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
2101+ if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL)
2102+ abort();
2103+ return 0;
2104+}
2105
2106=== added file 'gcc/testsuite/gcc.target/arm/neon-vaddu64.c'
2107--- old/gcc/testsuite/gcc.target/arm/neon-vaddu64.c 1970-01-01 00:00:00 +0000
2108+++ new/gcc/testsuite/gcc.target/arm/neon-vaddu64.c 2010-07-29 15:59:12 +0000
2109@@ -0,0 +1,21 @@
2110+/* Test the `vadd_u64' ARM Neon intrinsic. */
2111+
2112+/* { dg-do run } */
2113+/* { dg-require-effective-target arm_neon_hw } */
2114+/* { dg-options "-O0" } */
2115+/* { dg-add-options arm_neon } */
2116+
2117+#include "arm_neon.h"
2118+#include <stdlib.h>
2119+
2120+int main (void)
2121+{
2122+ uint64x1_t out_uint64x1_t = 0;
2123+ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
2124+ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL;
2125+
2126+ out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2127+ if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL)
2128+ abort();
2129+ return 0;
2130+}
2131
2132=== added file 'gcc/testsuite/gcc.target/arm/neon-vands64.c'
2133--- old/gcc/testsuite/gcc.target/arm/neon-vands64.c 1970-01-01 00:00:00 +0000
2134+++ new/gcc/testsuite/gcc.target/arm/neon-vands64.c 2010-07-29 15:59:12 +0000
2135@@ -0,0 +1,21 @@
2136+/* Test the `vand_s64' ARM Neon intrinsic. */
2137+
2138+/* { dg-do run } */
2139+/* { dg-require-effective-target arm_neon_hw } */
2140+/* { dg-options "-O0" } */
2141+/* { dg-add-options arm_neon } */
2142+
2143+#include "arm_neon.h"
2144+#include <stdlib.h>
2145+
2146+int main (void)
2147+{
2148+ int64x1_t out_int64x1_t = 0;
2149+ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
2150+ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
2151+
2152+ out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
2153+ if (out_int64x1_t != (int64x1_t)0xdead000000000000LL)
2154+ abort();
2155+ return 0;
2156+}
2157
2158=== added file 'gcc/testsuite/gcc.target/arm/neon-vandu64.c'
2159--- old/gcc/testsuite/gcc.target/arm/neon-vandu64.c 1970-01-01 00:00:00 +0000
2160+++ new/gcc/testsuite/gcc.target/arm/neon-vandu64.c 2010-07-29 15:59:12 +0000
2161@@ -0,0 +1,21 @@
2162+/* Test the `vand_u64' ARM Neon intrinsic. */
2163+
2164+/* { dg-do run } */
2165+/* { dg-require-effective-target arm_neon_hw } */
2166+/* { dg-options "-O0" } */
2167+/* { dg-add-options arm_neon } */
2168+
2169+#include "arm_neon.h"
2170+#include <stdlib.h>
2171+
2172+int main (void)
2173+{
2174+ uint64x1_t out_uint64x1_t = 0;
2175+ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
2176+ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
2177+
2178+ out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2179+ if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL)
2180+ abort();
2181+ return 0;
2182+}
2183
2184=== added file 'gcc/testsuite/gcc.target/arm/neon-vbics64.c'
2185--- old/gcc/testsuite/gcc.target/arm/neon-vbics64.c 1970-01-01 00:00:00 +0000
2186+++ new/gcc/testsuite/gcc.target/arm/neon-vbics64.c 2010-07-29 15:59:12 +0000
2187@@ -0,0 +1,21 @@
2188+/* Test the `vbic_s64' ARM Neon intrinsic. */
2189+
2190+/* { dg-do run } */
2191+/* { dg-require-effective-target arm_neon_hw } */
2192+/* { dg-options "-O0" } */
2193+/* { dg-add-options arm_neon } */
2194+
2195+#include "arm_neon.h"
2196+#include <stdlib.h>
2197+
2198+int main (void)
2199+{
2200+ int64x1_t out_int64x1_t = 0;
2201+ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
2202+ int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL);
2203+
2204+ out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
2205+ if (out_int64x1_t != (int64x1_t)0xdead000000000000LL)
2206+ abort();
2207+ return 0;
2208+}
2209
2210=== added file 'gcc/testsuite/gcc.target/arm/neon-vbicu64.c'
2211--- old/gcc/testsuite/gcc.target/arm/neon-vbicu64.c 1970-01-01 00:00:00 +0000
2212+++ new/gcc/testsuite/gcc.target/arm/neon-vbicu64.c 2010-07-29 15:59:12 +0000
2213@@ -0,0 +1,21 @@
2214+/* Test the `vbic_u64' ARM Neon intrinsic. */
2215+
2216+/* { dg-do run } */
2217+/* { dg-require-effective-target arm_neon_hw } */
2218+/* { dg-options "-O0" } */
2219+/* { dg-add-options arm_neon } */
2220+
2221+#include "arm_neon.h"
2222+#include <stdlib.h>
2223+
2224+int main (void)
2225+{
2226+ uint64x1_t out_uint64x1_t = 0;
2227+ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
2228+ uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL);
2229+
2230+ out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2231+ if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL)
2232+ abort();
2233+ return 0;
2234+}
2235
2236=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c'
2237--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c 1970-01-01 00:00:00 +0000
2238+++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c 2010-07-29 15:59:12 +0000
2239@@ -0,0 +1,22 @@
2240+/* Test the `vdupq_lanes64' ARM Neon intrinsic. */
2241+
2242+/* { dg-do run } */
2243+/* { dg-require-effective-target arm_neon_hw } */
2244+/* { dg-options "-O0" } */
2245+/* { dg-add-options arm_neon } */
2246+
2247+#include "arm_neon.h"
2248+#include <stdlib.h>
2249+
2250+int main (void)
2251+{
2252+ int64x2_t out_int64x2_t = {0, 0};
2253+ int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
2254+
2255+ out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0);
2256+ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
2257+ abort();
2258+ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
2259+ abort();
2260+ return 0;
2261+}
2262
2263=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c'
2264--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c 1970-01-01 00:00:00 +0000
2265+++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c 2010-07-29 15:59:12 +0000
2266@@ -0,0 +1,22 @@
2267+/* Test the `vdupq_laneu64' ARM Neon intrinsic. */
2268+
2269+/* { dg-do run } */
2270+/* { dg-require-effective-target arm_neon_hw } */
2271+/* { dg-options "-O0" } */
2272+/* { dg-add-options arm_neon } */
2273+
2274+#include "arm_neon.h"
2275+#include <stdlib.h>
2276+
2277+int main (void)
2278+{
2279+ uint64x2_t out_uint64x2_t = {0, 0};
2280+ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
2281+
2282+ out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0);
2283+ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
2284+ abort();
2285+ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
2286+ abort();
2287+ return 0;
2288+}
2289
2290=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c'
2291--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c 1970-01-01 00:00:00 +0000
2292+++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c 2010-07-29 15:59:12 +0000
2293@@ -0,0 +1,22 @@
2294+/* Test the `vdupq_ns64' ARM Neon intrinsic. */
2295+
2296+/* { dg-do run } */
2297+/* { dg-require-effective-target arm_neon_hw } */
2298+/* { dg-options "-O0" } */
2299+/* { dg-add-options arm_neon } */
2300+
2301+#include "arm_neon.h"
2302+#include <stdlib.h>
2303+
2304+int main (void)
2305+{
2306+ int64x2_t out_int64x2_t = {0, 0};
2307+ int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
2308+
2309+ out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
2310+ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
2311+ abort();
2312+ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
2313+ abort();
2314+ return 0;
2315+}
2316
2317=== added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c'
2318--- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c 1970-01-01 00:00:00 +0000
2319+++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c 2010-07-29 15:59:12 +0000
2320@@ -0,0 +1,22 @@
2321+/* Test the `vdupq_nu64' ARM Neon intrinsic. */
2322+
2323+/* { dg-do run } */
2324+/* { dg-require-effective-target arm_neon_hw } */
2325+/* { dg-options "-O0" } */
2326+/* { dg-add-options arm_neon } */
2327+
2328+#include "arm_neon.h"
2329+#include <stdlib.h>
2330+
2331+int main (void)
2332+{
2333+ uint64x2_t out_uint64x2_t = {0, 0};
2334+ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
2335+
2336+ out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
2337+ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
2338+ abort();
2339+ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
2340+ abort();
2341+ return 0;
2342+}
2343
2344=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c'
2345--- old/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c 1970-01-01 00:00:00 +0000
2346+++ new/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c 2010-07-29 15:59:12 +0000
2347@@ -0,0 +1,20 @@
2348+/* Test the `vdup_ns64' ARM Neon intrinsic. */
2349+
2350+/* { dg-do run } */
2351+/* { dg-require-effective-target arm_neon_hw } */
2352+/* { dg-options "-O0" } */
2353+/* { dg-add-options arm_neon } */
2354+
2355+#include "arm_neon.h"
2356+#include <stdlib.h>
2357+
2358+int main (void)
2359+{
2360+ int64x1_t out_int64x1_t = 0;
2361+ int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
2362+
2363+ out_int64x1_t = vdup_n_s64 (arg0_int64_t);
2364+ if ((int64_t)out_int64x1_t != arg0_int64_t)
2365+ abort();
2366+ return 0;
2367+}
2368
2369=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c'
2370--- old/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c 1970-01-01 00:00:00 +0000
2371+++ new/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c 2010-07-29 15:59:12 +0000
2372@@ -0,0 +1,20 @@
2373+/* Test the `vdup_nu64' ARM Neon intrinsic. */
2374+
2375+/* { dg-do run } */
2376+/* { dg-require-effective-target arm_neon_hw } */
2377+/* { dg-options "-O0" } */
2378+/* { dg-add-options arm_neon } */
2379+
2380+#include "arm_neon.h"
2381+#include <stdlib.h>
2382+
2383+int main (void)
2384+{
2385+ uint64x1_t out_uint64x1_t = 0;
2386+ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
2387+
2388+ out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
2389+ if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
2390+ abort();
2391+ return 0;
2392+}
2393
2394=== added file 'gcc/testsuite/gcc.target/arm/neon-veors64.c'
2395--- old/gcc/testsuite/gcc.target/arm/neon-veors64.c 1970-01-01 00:00:00 +0000
2396+++ new/gcc/testsuite/gcc.target/arm/neon-veors64.c 2010-07-29 15:59:12 +0000
2397@@ -0,0 +1,21 @@
2398+/* Test the `veor_s64' ARM Neon intrinsic. */
2399+
2400+/* { dg-do run } */
2401+/* { dg-require-effective-target arm_neon_hw } */
2402+/* { dg-options "-O0" } */
2403+/* { dg-add-options arm_neon } */
2404+
2405+#include "arm_neon.h"
2406+#include <stdlib.h>
2407+
2408+int main (void)
2409+{
2410+ int64x1_t out_int64x1_t = 0;
2411+ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
2412+ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
2413+
2414+ out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
2415+ if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL)
2416+ abort();
2417+ return 0;
2418+}
2419
2420=== added file 'gcc/testsuite/gcc.target/arm/neon-veoru64.c'
2421--- old/gcc/testsuite/gcc.target/arm/neon-veoru64.c 1970-01-01 00:00:00 +0000
2422+++ new/gcc/testsuite/gcc.target/arm/neon-veoru64.c 2010-07-29 15:59:12 +0000
2423@@ -0,0 +1,21 @@
2424+/* Test the `veor_u64' ARM Neon intrinsic. */
2425+
2426+/* { dg-do run } */
2427+/* { dg-require-effective-target arm_neon_hw } */
2428+/* { dg-options "-O0" } */
2429+/* { dg-add-options arm_neon } */
2430+
2431+#include "arm_neon.h"
2432+#include <stdlib.h>
2433+
2434+int main (void)
2435+{
2436+ uint64x1_t out_uint64x1_t = 0;
2437+ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
2438+ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
2439+
2440+ out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2441+ if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL)
2442+ abort();
2443+ return 0;
2444+}
2445
2446=== added file 'gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c'
2447--- old/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c 1970-01-01 00:00:00 +0000
2448+++ new/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c 2010-07-29 15:59:12 +0000
2449@@ -0,0 +1,20 @@
2450+/* Test the `vget_lane_s64' ARM Neon intrinsic. */
2451+
2452+/* { dg-do run } */
2453+/* { dg-require-effective-target arm_neon_hw } */
2454+/* { dg-options "-O0" } */
2455+/* { dg-add-options arm_neon } */
2456+
2457+#include "arm_neon.h"
2458+#include <stdlib.h>
2459+
2460+int main (void)
2461+{
2462+ int64_t out_int64_t = 0;
2463+ int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
2464+
2465+ out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
2466+ if (out_int64_t != (int64_t)arg0_int64x1_t)
2467+ abort();
2468+ return 0;
2469+}
2470
2471=== added file 'gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c'
2472--- old/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c 1970-01-01 00:00:00 +0000
2473+++ new/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c 2010-07-29 15:59:12 +0000
2474@@ -0,0 +1,20 @@
2475+/* Test the `vget_lane_u64' ARM Neon intrinsic. */
2476+
2477+/* { dg-do run } */
2478+/* { dg-require-effective-target arm_neon_hw } */
2479+/* { dg-options "-O0" } */
2480+/* { dg-add-options arm_neon } */
2481+
2482+#include "arm_neon.h"
2483+#include <stdlib.h>
2484+
2485+int main (void)
2486+{
2487+ uint64_t out_uint64_t = 0;
2488+ uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
2489+
2490+ out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
2491+ if (out_uint64_t != (uint64_t)arg0_uint64x1_t)
2492+ abort();
2493+ return 0;
2494+}
2495
2496=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmla-1.c'
2497--- old/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2010-07-29 15:38:15 +0000
2498+++ new/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2010-07-29 15:59:12 +0000
2499@@ -1,5 +1,5 @@
2500 /* { dg-require-effective-target arm_neon_hw } */
2501-/* { dg-options "-O2 -ftree-vectorize" } */
2502+/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
2503 /* { dg-add-options arm_neon } */
2504 /* { dg-final { scan-assembler "vmla\\.f32" } } */
2505
2506
2507=== modified file 'gcc/testsuite/gcc.target/arm/neon-vmls-1.c'
2508--- old/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2010-07-29 15:38:15 +0000
2509+++ new/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2010-07-29 15:59:12 +0000
2510@@ -1,5 +1,5 @@
2511 /* { dg-require-effective-target arm_neon_hw } */
2512-/* { dg-options "-O2 -ftree-vectorize" } */
2513+/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
2514 /* { dg-add-options arm_neon } */
2515 /* { dg-final { scan-assembler "vmls\\.f32" } } */
2516
2517
2518=== added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c'
2519--- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c 1970-01-01 00:00:00 +0000
2520+++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c 2010-07-29 15:59:12 +0000
2521@@ -0,0 +1,22 @@
2522+/* Test the `vmovq_ns64' ARM Neon intrinsic. */
2523+
2524+/* { dg-do run } */
2525+/* { dg-require-effective-target arm_neon_hw } */
2526+/* { dg-options "-O0" } */
2527+/* { dg-add-options arm_neon } */
2528+
2529+#include "arm_neon.h"
2530+#include <stdlib.h>
2531+
2532+int main (void)
2533+{
2534+ int64x2_t out_int64x2_t = {0, 0};
2535+ int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
2536+
2537+ out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
2538+ if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
2539+ abort();
2540+ if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
2541+ abort();
2542+ return 0;
2543+}
2544
2545=== added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c'
2546--- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c 1970-01-01 00:00:00 +0000
2547+++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c 2010-07-29 15:59:12 +0000
2548@@ -0,0 +1,23 @@
2549+/* Test the `vmovq_nu64' ARM Neon intrinsic. */
2550+
2551+/* { dg-do run } */
2552+/* { dg-require-effective-target arm_neon_hw } */
2553+/* { dg-options "-O0" } */
2554+/* { dg-add-options arm_neon } */
2555+
2556+#include "arm_neon.h"
2557+#include <stdlib.h>
2558+
2559+int main (void)
2560+{
2561+ uint64x2_t out_uint64x2_t = {0, 0};
2562+ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
2563+
2564+ out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
2565+ if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
2566+ abort();
2567+ if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
2568+ abort();
2569+ return 0;
2570+}
2571+
2572
2573=== added file 'gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c'
2574--- old/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c 1970-01-01 00:00:00 +0000
2575+++ new/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c 2010-07-29 15:59:12 +0000
2576@@ -0,0 +1,20 @@
2577+/* Test the `vmov_ns64' ARM Neon intrinsic. */
2578+
2579+/* { dg-do run } */
2580+/* { dg-require-effective-target arm_neon_hw } */
2581+/* { dg-options "-O0" } */
2582+/* { dg-add-options arm_neon } */
2583+
2584+#include "arm_neon.h"
2585+#include <stdlib.h>
2586+
2587+int main (void)
2588+{
2589+ int64x1_t out_int64x1_t = 0;
2590+ int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
2591+
2592+ out_int64x1_t = vmov_n_s64 (arg0_int64_t);
2593+ if ((int64_t)out_int64x1_t != arg0_int64_t)
2594+ abort();
2595+ return 0;
2596+}
2597
2598=== added file 'gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c'
2599--- old/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c 1970-01-01 00:00:00 +0000
2600+++ new/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c 2010-07-29 15:59:12 +0000
2601@@ -0,0 +1,20 @@
2602+/* Test the `vmov_nu64' ARM Neon intrinsic. */
2603+
2604+/* { dg-do run } */
2605+/* { dg-require-effective-target arm_neon_hw } */
2606+/* { dg-options "-O0" } */
2607+/* { dg-add-options arm_neon } */
2608+
2609+#include "arm_neon.h"
2610+#include <stdlib.h>
2611+
2612+int main (void)
2613+{
2614+ uint64x1_t out_uint64x1_t = 0;
2615+ uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
2616+
2617+ out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
2618+ if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
2619+ abort();
2620+ return 0;
2621+}
2622
2623=== added file 'gcc/testsuite/gcc.target/arm/neon-vorns64.c'
2624--- old/gcc/testsuite/gcc.target/arm/neon-vorns64.c 1970-01-01 00:00:00 +0000
2625+++ new/gcc/testsuite/gcc.target/arm/neon-vorns64.c 2010-07-29 15:59:12 +0000
2626@@ -0,0 +1,21 @@
2627+/* Test the `vorn_s64' ARM Neon intrinsic. */
2628+
2629+/* { dg-do run } */
2630+/* { dg-require-effective-target arm_neon_hw } */
2631+/* { dg-options "-O0" } */
2632+/* { dg-add-options arm_neon } */
2633+
2634+#include "arm_neon.h"
2635+#include <stdlib.h>
2636+
2637+int main (void)
2638+{
2639+ int64x1_t out_int64x1_t = 0;
2640+ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
2641+ int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL);
2642+
2643+ out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
2644+ if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL)
2645+ abort();
2646+ return 0;
2647+}
2648
2649=== added file 'gcc/testsuite/gcc.target/arm/neon-vornu64.c'
2650--- old/gcc/testsuite/gcc.target/arm/neon-vornu64.c 1970-01-01 00:00:00 +0000
2651+++ new/gcc/testsuite/gcc.target/arm/neon-vornu64.c 2010-07-29 15:59:12 +0000
2652@@ -0,0 +1,21 @@
2653+/* Test the `vorn_u64' ARM Neon intrinsic. */
2654+
2655+/* { dg-do run } */
2656+/* { dg-require-effective-target arm_neon_hw } */
2657+/* { dg-options "-O0" } */
2658+/* { dg-add-options arm_neon } */
2659+
2660+#include "arm_neon.h"
2661+#include <stdlib.h>
2662+
2663+int main (void)
2664+{
2665+ uint64x1_t out_uint64x1_t = 0;
2666+ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
2667+ uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL);
2668+
2669+ out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2670+ if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL)
2671+ abort();
2672+ return 0;
2673+}
2674
2675=== added file 'gcc/testsuite/gcc.target/arm/neon-vorrs64.c'
2676--- old/gcc/testsuite/gcc.target/arm/neon-vorrs64.c 1970-01-01 00:00:00 +0000
2677+++ new/gcc/testsuite/gcc.target/arm/neon-vorrs64.c 2010-07-29 15:59:12 +0000
2678@@ -0,0 +1,21 @@
2679+/* Test the `vorr_s64' ARM Neon intrinsic. */
2680+
2681+/* { dg-do run } */
2682+/* { dg-require-effective-target arm_neon_hw } */
2683+/* { dg-options "-O0" } */
2684+/* { dg-add-options arm_neon } */
2685+
2686+#include "arm_neon.h"
2687+#include <stdlib.h>
2688+
2689+int main (void)
2690+{
2691+ int64x1_t out_int64x1_t = 0;
2692+ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
2693+ int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
2694+
2695+ out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
2696+ if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL)
2697+ abort();
2698+ return 0;
2699+}
2700
2701=== added file 'gcc/testsuite/gcc.target/arm/neon-vorru64.c'
2702--- old/gcc/testsuite/gcc.target/arm/neon-vorru64.c 1970-01-01 00:00:00 +0000
2703+++ new/gcc/testsuite/gcc.target/arm/neon-vorru64.c 2010-07-29 15:59:12 +0000
2704@@ -0,0 +1,21 @@
2705+/* Test the `vorr_u64' ARM Neon intrinsic. */
2706+
2707+/* { dg-do run } */
2708+/* { dg-require-effective-target arm_neon_hw } */
2709+/* { dg-options "-O0" } */
2710+/* { dg-add-options arm_neon } */
2711+
2712+#include "arm_neon.h"
2713+#include <stdlib.h>
2714+
2715+int main (void)
2716+{
2717+ uint64x1_t out_uint64x1_t = 0;
2718+ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
2719+ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
2720+
2721+ out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2722+ if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL)
2723+ abort();
2724+ return 0;
2725+}
2726
2727=== added file 'gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c'
2728--- old/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c 1970-01-01 00:00:00 +0000
2729+++ new/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c 2010-07-29 15:59:12 +0000
2730@@ -0,0 +1,21 @@
2731+/* Test the `vset_lane_s64' ARM Neon intrinsic. */
2732+
2733+/* { dg-do run } */
2734+/* { dg-require-effective-target arm_neon_hw } */
2735+/* { dg-options "-O0" } */
2736+/* { dg-add-options arm_neon } */
2737+
2738+#include "arm_neon.h"
2739+#include <stdlib.h>
2740+
2741+int main (void)
2742+{
2743+ int64x1_t out_int64x1_t = 0;
2744+ int64_t arg0_int64_t = 0xf00f00f00LL;
2745+ int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
2746+
2747+ out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
2748+ if ((int64_t)out_int64x1_t != arg0_int64_t)
2749+ abort();
2750+ return 0;
2751+}
2752
2753=== added file 'gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c'
2754--- old/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c 1970-01-01 00:00:00 +0000
2755+++ new/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c 2010-07-29 15:59:12 +0000
2756@@ -0,0 +1,21 @@
2757+/* Test the `vset_lane_s64' ARM Neon intrinsic. */
2758+
2759+/* { dg-do run } */
2760+/* { dg-require-effective-target arm_neon_hw } */
2761+/* { dg-options "-O0" } */
2762+/* { dg-add-options arm_neon } */
2763+
2764+#include "arm_neon.h"
2765+#include <stdlib.h>
2766+
2767+int main (void)
2768+{
2769+ uint64x1_t out_uint64x1_t = 0;
2770+ uint64_t arg0_uint64_t = 0xf00f00f00LL;
2771+ uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
2772+
2773+ out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
2774+ if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
2775+ abort();
2776+ return 0;
2777+}
2778
2779=== added file 'gcc/testsuite/gcc.target/arm/neon-vsubs64.c'
2780--- old/gcc/testsuite/gcc.target/arm/neon-vsubs64.c 1970-01-01 00:00:00 +0000
2781+++ new/gcc/testsuite/gcc.target/arm/neon-vsubs64.c 2010-07-29 15:59:12 +0000
2782@@ -0,0 +1,21 @@
2783+/* Test the `vsub_s64' ARM Neon intrinsic. */
2784+
2785+/* { dg-do run } */
2786+/* { dg-require-effective-target arm_neon_hw } */
2787+/* { dg-options "-O0" } */
2788+/* { dg-add-options arm_neon } */
2789+
2790+#include "arm_neon.h"
2791+#include <stdlib.h>
2792+
2793+int main (void)
2794+{
2795+ int64x1_t out_int64x1_t = 0;
2796+ int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL;
2797+ int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL;
2798+
2799+ out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
2800+ if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL)
2801+ abort();
2802+ return 0;
2803+}
2804
2805=== added file 'gcc/testsuite/gcc.target/arm/neon-vsubu64.c'
2806--- old/gcc/testsuite/gcc.target/arm/neon-vsubu64.c 1970-01-01 00:00:00 +0000
2807+++ new/gcc/testsuite/gcc.target/arm/neon-vsubu64.c 2010-07-29 15:59:12 +0000
2808@@ -0,0 +1,21 @@
2809+/* Test the `vsub_u64' ARM Neon intrinsic. */
2810+
2811+/* { dg-do run } */
2812+/* { dg-require-effective-target arm_neon_hw } */
2813+/* { dg-options "-O0" } */
2814+/* { dg-add-options arm_neon } */
2815+
2816+#include "arm_neon.h"
2817+#include <stdlib.h>
2818+
2819+int main (void)
2820+{
2821+ uint64x1_t out_uint64x1_t = 0;
2822+ uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL;
2823+ uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL;
2824+
2825+ out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2826+ if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL)
2827+ abort();
2828+ return 0;
2829+}
2830
2831=== modified file 'gcc/testsuite/gcc.target/arm/neon/vadds64.c'
2832--- old/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2010-07-29 15:38:15 +0000
2833+++ new/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2010-07-29 15:59:12 +0000
2834@@ -17,5 +17,4 @@
2835 out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
2836 }
2837
2838-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2839 /* { dg-final { cleanup-saved-temps } } */
2840
2841=== modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu64.c'
2842--- old/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2010-07-29 15:38:15 +0000
2843+++ new/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2010-07-29 15:59:12 +0000
2844@@ -17,5 +17,4 @@
2845 out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2846 }
2847
2848-/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2849 /* { dg-final { cleanup-saved-temps } } */
2850
2851=== modified file 'gcc/testsuite/gcc.target/arm/neon/vands64.c'
2852--- old/gcc/testsuite/gcc.target/arm/neon/vands64.c 2010-07-29 15:38:15 +0000
2853+++ new/gcc/testsuite/gcc.target/arm/neon/vands64.c 2010-07-29 15:59:12 +0000
2854@@ -17,5 +17,4 @@
2855 out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
2856 }
2857
2858-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2859 /* { dg-final { cleanup-saved-temps } } */
2860
2861=== modified file 'gcc/testsuite/gcc.target/arm/neon/vandu64.c'
2862--- old/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2010-07-29 15:38:15 +0000
2863+++ new/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2010-07-29 15:59:12 +0000
2864@@ -17,5 +17,4 @@
2865 out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2866 }
2867
2868-/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2869 /* { dg-final { cleanup-saved-temps } } */
2870
2871=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbics64.c'
2872--- old/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2010-07-29 15:38:15 +0000
2873+++ new/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2010-07-29 15:59:12 +0000
2874@@ -17,5 +17,4 @@
2875 out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
2876 }
2877
2878-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2879 /* { dg-final { cleanup-saved-temps } } */
2880
2881=== modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu64.c'
2882--- old/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2010-07-29 15:38:15 +0000
2883+++ new/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2010-07-29 15:59:12 +0000
2884@@ -17,5 +17,4 @@
2885 out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2886 }
2887
2888-/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2889 /* { dg-final { cleanup-saved-temps } } */
2890
2891=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c'
2892--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2010-07-29 15:38:15 +0000
2893+++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2010-07-29 15:59:12 +0000
2894@@ -16,6 +16,4 @@
2895 out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
2896 }
2897
2898-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2899-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2900 /* { dg-final { cleanup-saved-temps } } */
2901
2902=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c'
2903--- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2010-07-29 15:38:15 +0000
2904+++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2010-07-29 15:59:12 +0000
2905@@ -16,6 +16,4 @@
2906 out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
2907 }
2908
2909-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2910-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2911 /* { dg-final { cleanup-saved-temps } } */
2912
2913=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c'
2914--- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2010-07-29 15:38:15 +0000
2915+++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2010-07-29 15:59:12 +0000
2916@@ -16,5 +16,4 @@
2917 out_int64x1_t = vdup_n_s64 (arg0_int64_t);
2918 }
2919
2920-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2921 /* { dg-final { cleanup-saved-temps } } */
2922
2923=== modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c'
2924--- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2010-07-29 15:38:15 +0000
2925+++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2010-07-29 15:59:12 +0000
2926@@ -16,5 +16,4 @@
2927 out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
2928 }
2929
2930-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2931 /* { dg-final { cleanup-saved-temps } } */
2932
2933=== modified file 'gcc/testsuite/gcc.target/arm/neon/veors64.c'
2934--- old/gcc/testsuite/gcc.target/arm/neon/veors64.c 2010-07-29 15:38:15 +0000
2935+++ new/gcc/testsuite/gcc.target/arm/neon/veors64.c 2010-07-29 15:59:12 +0000
2936@@ -17,5 +17,4 @@
2937 out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
2938 }
2939
2940-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2941 /* { dg-final { cleanup-saved-temps } } */
2942
2943=== modified file 'gcc/testsuite/gcc.target/arm/neon/veoru64.c'
2944--- old/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2010-07-29 15:38:15 +0000
2945+++ new/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2010-07-29 15:59:12 +0000
2946@@ -17,5 +17,4 @@
2947 out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
2948 }
2949
2950-/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2951 /* { dg-final { cleanup-saved-temps } } */
2952
2953=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c'
2954--- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2010-07-29 15:38:15 +0000
2955+++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2010-07-29 15:59:12 +0000
2956@@ -16,5 +16,4 @@
2957 out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
2958 }
2959
2960-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2961 /* { dg-final { cleanup-saved-temps } } */
2962
2963=== modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c'
2964--- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2010-07-29 15:38:15 +0000
2965+++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2010-07-29 15:59:12 +0000
2966@@ -16,5 +16,4 @@
2967 out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
2968 }
2969
2970-/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2971 /* { dg-final { cleanup-saved-temps } } */
2972
2973=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c'
2974--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2010-07-29 15:38:15 +0000
2975+++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2010-07-29 15:59:12 +0000
2976@@ -16,6 +16,4 @@
2977 out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
2978 }
2979
2980-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2981-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2982 /* { dg-final { cleanup-saved-temps } } */
2983
2984=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c'
2985--- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2010-07-29 15:38:15 +0000
2986+++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2010-07-29 15:59:12 +0000
2987@@ -16,6 +16,4 @@
2988 out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
2989 }
2990
2991-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2992-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2993 /* { dg-final { cleanup-saved-temps } } */
2994
2995=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c'
2996--- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2010-07-29 15:38:15 +0000
2997+++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2010-07-29 15:59:12 +0000
2998@@ -16,5 +16,4 @@
2999 out_int64x1_t = vmov_n_s64 (arg0_int64_t);
3000 }
3001
3002-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3003 /* { dg-final { cleanup-saved-temps } } */
3004
3005=== modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c'
3006--- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2010-07-29 15:38:15 +0000
3007+++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2010-07-29 15:59:12 +0000
3008@@ -16,5 +16,4 @@
3009 out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
3010 }
3011
3012-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3013 /* { dg-final { cleanup-saved-temps } } */
3014
3015=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorns64.c'
3016--- old/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2010-07-29 15:38:15 +0000
3017+++ new/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2010-07-29 15:59:12 +0000
3018@@ -17,5 +17,4 @@
3019 out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
3020 }
3021
3022-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3023 /* { dg-final { cleanup-saved-temps } } */
3024
3025=== modified file 'gcc/testsuite/gcc.target/arm/neon/vornu64.c'
3026--- old/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2010-07-29 15:38:15 +0000
3027+++ new/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2010-07-29 15:59:12 +0000
3028@@ -17,5 +17,4 @@
3029 out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
3030 }
3031
3032-/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3033 /* { dg-final { cleanup-saved-temps } } */
3034
3035=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs64.c'
3036--- old/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2010-07-29 15:38:15 +0000
3037+++ new/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2010-07-29 15:59:12 +0000
3038@@ -17,5 +17,4 @@
3039 out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
3040 }
3041
3042-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3043 /* { dg-final { cleanup-saved-temps } } */
3044
3045=== modified file 'gcc/testsuite/gcc.target/arm/neon/vorru64.c'
3046--- old/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2010-07-29 15:38:15 +0000
3047+++ new/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2010-07-29 15:59:12 +0000
3048@@ -17,5 +17,4 @@
3049 out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
3050 }
3051
3052-/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3053 /* { dg-final { cleanup-saved-temps } } */
3054
3055=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c'
3056--- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2010-07-29 15:38:15 +0000
3057+++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2010-07-29 15:59:12 +0000
3058@@ -17,5 +17,4 @@
3059 out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
3060 }
3061
3062-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3063 /* { dg-final { cleanup-saved-temps } } */
3064
3065=== modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c'
3066--- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2010-07-29 15:38:15 +0000
3067+++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2010-07-29 15:59:12 +0000
3068@@ -17,5 +17,4 @@
3069 out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
3070 }
3071
3072-/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3073 /* { dg-final { cleanup-saved-temps } } */
3074
3075=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs64.c'
3076--- old/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2010-07-29 15:38:15 +0000
3077+++ new/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2010-07-29 15:59:12 +0000
3078@@ -17,5 +17,4 @@
3079 out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
3080 }
3081
3082-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3083 /* { dg-final { cleanup-saved-temps } } */
3084
3085=== modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu64.c'
3086--- old/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2010-07-29 15:38:15 +0000
3087+++ new/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2010-07-29 15:59:12 +0000
3088@@ -17,5 +17,4 @@
3089 out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
3090 }
3091
3092-/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3093 /* { dg-final { cleanup-saved-temps } } */
3094
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-10-24 14:38:48 +0000