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authorKhem Raj <raj.khem@gmail.com>2011-06-12 21:06:58 -0700
committerKoen Kooi <koen@dominion.thruhere.net>2011-06-13 09:51:40 +0200
commit8052751332dbd5bc35f854735e99d9bb20086c61 (patch)
tree5e5e73c79da424cd207846042fdc2836cd732d7e
parenteac31f4e3a684f58936aaf5438b5f2c421645a0a (diff)
downloadmeta-openembedded-8052751332dbd5bc35f854735e99d9bb20086c61.tar.gz
Add bbappend files for gcc 4.6.0 from oe-core
The bbappends add patches for linaro so with this we can enhance gcc 4.6.0 from oe-core and have patches that are in meta-oe on top of it. Add patches from for linaro 4.6 This obsoletes the need of having gcc 4.6 recipes in meta-oe Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Diffstat
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch51
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch63
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch32
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch653
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch126
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch177
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch140
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106740.patch294
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch254
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch6123
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch25
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch21
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch24
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch640
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch30
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch134
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch5027
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch329
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch120
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc5
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend3
-rw-r--r--meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend3
31 files changed, 14300 insertions, 1 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch
new file mode 100644
index 000000000..4c573f401
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch
@@ -0,0 +1,51 @@
12011-02-21 Andrew Stubbs <ams@codesourcery.com>
2 Julian Brown <julian@codesourcery.com>
3 Mark Shinwell <shinwell@codesourcery.com>
4
5 Forward-ported from Linaro GCC 4.5 (bzr99324).
6
7 gcc/
8 * config/arm/arm.h (arm_class_likely_spilled_p): Check against
9 LO_REGS only for Thumb-1.
10 (MODE_BASE_REG_CLASS): Restrict base registers to those which can
11 be used in short instructions when optimising for size on Thumb-2.
12
13=== modified file 'gcc/config/arm/arm.c'
14--- old/gcc/config/arm/arm.c 2011-01-29 03:20:57 +0000
15+++ new/gcc/config/arm/arm.c 2011-02-21 14:04:51 +0000
16@@ -22304,14 +22304,16 @@
17
18 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
19
20- We need to define this for LO_REGS on thumb. Otherwise we can end up
21- using r0-r4 for function arguments, r7 for the stack frame and don't
22- have enough left over to do doubleword arithmetic. */
23-
24+ We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
25+ using r0-r4 for function arguments, r7 for the stack frame and don't have
26+ enough left over to do doubleword arithmetic. For Thumb-2 all the
27+ potentially problematic instructions accept high registers so this is not
28+ necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
29+ that require many low registers. */
30 static bool
31 arm_class_likely_spilled_p (reg_class_t rclass)
32 {
33- if ((TARGET_THUMB && rclass == LO_REGS)
34+ if ((TARGET_THUMB1 && rclass == LO_REGS)
35 || rclass == CC_REG)
36 return true;
37
38
39=== modified file 'gcc/config/arm/arm.h'
40--- old/gcc/config/arm/arm.h 2011-01-29 03:20:57 +0000
41+++ new/gcc/config/arm/arm.h 2011-02-21 14:04:51 +0000
42@@ -1185,7 +1185,7 @@
43 when addressing quantities in QI or HI mode; if we don't know the
44 mode, then we must be conservative. */
45 #define MODE_BASE_REG_CLASS(MODE) \
46- (TARGET_32BIT ? CORE_REGS : \
47+ (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
48 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
49
50 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
51
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch
new file mode 100644
index 000000000..5271ffa6f
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch
@@ -0,0 +1,63 @@
12011-02-02 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 PR target/47551
5 * config/arm/arm.c (coproc_secondary_reload_class): Handle
6 structure modes. Don't check neon_vector_mem_operand for
7 vector or structure modes.
8
9 gcc/testsuite/
10 PR target/47551
11 * gcc.target/arm/neon-modes-2.c: New test.
12
13=== modified file 'gcc/config/arm/arm.c'
14--- old/gcc/config/arm/arm.c 2011-02-21 14:04:51 +0000
15+++ new/gcc/config/arm/arm.c 2011-03-02 11:38:43 +0000
16@@ -9139,11 +9139,14 @@
17 return GENERAL_REGS;
18 }
19
20+ /* The neon move patterns handle all legitimate vector and struct
21+ addresses. */
22 if (TARGET_NEON
23+ && MEM_P (x)
24 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
25- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
26- && neon_vector_mem_operand (x, 0))
27- return NO_REGS;
28+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
29+ || VALID_NEON_STRUCT_MODE (mode)))
30+ return NO_REGS;
31
32 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
33 return NO_REGS;
34
35=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-2.c'
36--- old/gcc/testsuite/gcc.target/arm/neon-modes-2.c 1970-01-01 00:00:00 +0000
37+++ new/gcc/testsuite/gcc.target/arm/neon-modes-2.c 2011-02-02 10:02:45 +0000
38@@ -0,0 +1,24 @@
39+/* { dg-do compile } */
40+/* { dg-require-effective-target arm_neon_ok } */
41+/* { dg-options "-O1" } */
42+/* { dg-add-options arm_neon } */
43+
44+#include "arm_neon.h"
45+
46+#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20)
47+#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1)
48+#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A)
49+
50+#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5)
51+
52+void
53+bar (uint32_t *ptr, int y)
54+{
55+ uint32x2x3_t MANY (SETUP);
56+ int *x = __builtin_alloca (y);
57+ int z[0x1000];
58+ foo (x, z);
59+ MANY (MODIFY);
60+ foo (x, z);
61+ MANY (STORE);
62+}
63
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch
new file mode 100644
index 000000000..465d09c1a
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch
@@ -0,0 +1,32 @@
12011-03-22 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-03-21 Daniel Jacobowitz <dan@codesourcery.com>
6
7 gcc/
8 * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test
9 for barrier handlers.
10
11=== modified file 'gcc/config/arm/unwind-arm.c'
12--- old/gcc/config/arm/unwind-arm.c 2009-10-30 14:55:10 +0000
13+++ new/gcc/config/arm/unwind-arm.c 2011-03-22 10:59:10 +0000
14@@ -1196,8 +1196,6 @@
15 ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
16
17 if (data[0] & uint32_highbit)
18- phase2_call_unexpected_after_unwind = 1;
19- else
20 {
21 data += rtti_count + 1;
22 /* Setup for entry to the handler. */
23@@ -1207,6 +1205,8 @@
24 _Unwind_SetGR (context, 0, (_uw) ucbp);
25 return _URC_INSTALL_CONTEXT;
26 }
27+ else
28+ phase2_call_unexpected_after_unwind = 1;
29 }
30 if (data[0] & uint32_highbit)
31 data++;
32
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch
new file mode 100644
index 000000000..4b0079e1d
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch
@@ -0,0 +1,653 @@
12011-03-27 Ira Rosen <ira.rosen@linaro.org>
2
3 gcc/
4 * doc/invoke.texi (max-stores-to-sink): Document.
5 * params.h (MAX_STORES_TO_SINK): Define.
6 * opts.c (finish_options): Set MAX_STORES_TO_SINK to 0
7 if either vectorization or if-conversion is disabled.
8 * tree-data-ref.c (dr_equal_offsets_p1): Moved and renamed from
9 tree-vect-data-refs.c vect_equal_offsets.
10 (dr_equal_offsets_p): New function.
11 (find_data_references_in_bb): Remove static.
12 * tree-data-ref.h (find_data_references_in_bb): Declare.
13 (dr_equal_offsets_p): Likewise.
14 * tree-vect-data-refs.c (vect_equal_offsets): Move to tree-data-ref.c.
15 (vect_drs_dependent_in_basic_block): Update calls to
16 vect_equal_offsets.
17 (vect_check_interleaving): Likewise.
18 * tree-ssa-phiopt.c: Include cfgloop.h and tree-data-ref.h.
19 (cond_if_else_store_replacement): Rename to...
20 (cond_if_else_store_replacement_1): ... this. Change arguments and
21 documentation.
22 (cond_if_else_store_replacement): New function.
23 * Makefile.in (tree-ssa-phiopt.o): Adjust dependencies.
24 * params.def (PARAM_MAX_STORES_TO_SINK): Define.
25
26 gcc/testsuite/
27 * gcc.dg/vect/vect-cselim-1.c: New test.
28 * gcc.dg/vect/vect-cselim-2.c: New test.
29
30=== modified file 'gcc/Makefile.in'
31--- old/gcc/Makefile.in 2011-03-26 09:20:34 +0000
32+++ new/gcc/Makefile.in 2011-04-18 11:31:29 +0000
33@@ -2422,7 +2422,8 @@
34 tree-ssa-phiopt.o : tree-ssa-phiopt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
35 $(TM_H) $(GGC_H) $(TREE_H) $(TM_P_H) $(BASIC_BLOCK_H) \
36 $(TREE_FLOW_H) $(TREE_PASS_H) $(TREE_DUMP_H) langhooks.h $(FLAGS_H) \
37- $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h
38+ $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h $(CFGLOOP_H) \
39+ $(TREE_DATA_REF_H)
40 tree-nrv.o : tree-nrv.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
41 $(TM_H) $(TREE_H) $(FUNCTION_H) $(BASIC_BLOCK_H) $(FLAGS_H) \
42 $(DIAGNOSTIC_H) $(TREE_FLOW_H) $(TIMEVAR_H) $(TREE_DUMP_H) $(TREE_PASS_H) \
43
44=== modified file 'gcc/doc/invoke.texi'
45--- old/gcc/doc/invoke.texi 2011-03-29 14:24:42 +0000
46+++ new/gcc/doc/invoke.texi 2011-04-18 11:31:29 +0000
47@@ -8909,6 +8909,11 @@
48 The maximum number of namespaces to consult for suggestions when C++
49 name lookup fails for an identifier. The default is 1000.
50
51+@item max-stores-to-sink
52+The maximum number of conditional stores paires that can be sunk. Set to 0
53+if either vectorization (@option{-ftree-vectorize}) or if-conversion
54+(@option{-ftree-loop-if-convert}) is disabled. The default is 2.
55+
56 @end table
57 @end table
58
59
60=== modified file 'gcc/opts.c'
61--- old/gcc/opts.c 2011-02-17 22:51:57 +0000
62+++ new/gcc/opts.c 2011-03-27 09:38:18 +0000
63@@ -823,6 +823,12 @@
64 opts->x_flag_split_stack = 0;
65 }
66 }
67+
68+ /* Set PARAM_MAX_STORES_TO_SINK to 0 if either vectorization or if-conversion
69+ is disabled. */
70+ if (!opts->x_flag_tree_vectorize || !opts->x_flag_tree_loop_if_convert)
71+ maybe_set_param_value (PARAM_MAX_STORES_TO_SINK, 0,
72+ opts->x_param_values, opts_set->x_param_values);
73 }
74
75 #define LEFT_COLUMN 27
76
77=== modified file 'gcc/params.def'
78--- old/gcc/params.def 2011-03-26 09:20:34 +0000
79+++ new/gcc/params.def 2011-04-18 11:31:29 +0000
80@@ -883,6 +883,13 @@
81 "name lookup fails",
82 1000, 0, 0)
83
84+/* Maximum number of conditional store pairs that can be sunk. */
85+DEFPARAM (PARAM_MAX_STORES_TO_SINK,
86+ "max-stores-to-sink",
87+ "Maximum number of conditional store pairs that can be sunk",
88+ 2, 0, 0)
89+
90+
91 /*
92 Local variables:
93 mode:c
94
95=== modified file 'gcc/params.h'
96--- old/gcc/params.h 2011-01-13 13:41:03 +0000
97+++ new/gcc/params.h 2011-03-27 09:38:18 +0000
98@@ -206,4 +206,6 @@
99 PARAM_VALUE (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO)
100 #define MIN_NONDEBUG_INSN_UID \
101 PARAM_VALUE (PARAM_MIN_NONDEBUG_INSN_UID)
102+#define MAX_STORES_TO_SINK \
103+ PARAM_VALUE (PARAM_MAX_STORES_TO_SINK)
104 #endif /* ! GCC_PARAMS_H */
105
106=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c'
107--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 1970-01-01 00:00:00 +0000
108+++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-03-27 09:38:18 +0000
109@@ -0,0 +1,86 @@
110+/* { dg-require-effective-target vect_int } */
111+
112+#include <stdarg.h>
113+#include "tree-vect.h"
114+
115+#define N 50
116+
117+typedef struct {
118+ short a;
119+ short b;
120+} data;
121+
122+data in1[N], in2[N], out[N];
123+short result[N*2] = {7,-7,9,-6,11,-5,13,-4,15,-3,17,-2,19,-1,21,0,23,1,25,2,27,3,29,4,31,5,33,6,35,7,37,8,39,9,41,10,43,11,45,12,47,13,49,14,51,15,53,16,55,17,57,18,59,19,61,20,63,21,65,22,67,23,69,24,71,25,73,26,75,27,77,28,79,29,81,30,83,31,85,32,87,33,89,34,91,35,93,36,95,37,97,38,99,39,101,40,103,41,105,42};
124+short out1[N], out2[N];
125+
126+__attribute__ ((noinline)) void
127+foo ()
128+{
129+ int i;
130+ short c, d;
131+
132+ /* Vectorizable with conditional store sinking. */
133+ for (i = 0; i < N; i++)
134+ {
135+ c = in1[i].b;
136+ d = in2[i].b;
137+
138+ if (c >= d)
139+ {
140+ out[i].b = c;
141+ out[i].a = d + 5;
142+ }
143+ else
144+ {
145+ out[i].b = d - 12;
146+ out[i].a = c + d;
147+ }
148+ }
149+
150+ /* Not vectorizable. */
151+ for (i = 0; i < N; i++)
152+ {
153+ c = in1[i].b;
154+ d = in2[i].b;
155+
156+ if (c >= d)
157+ {
158+ out1[i] = c;
159+ }
160+ else
161+ {
162+ out2[i] = c + d;
163+ }
164+ }
165+}
166+
167+int
168+main (void)
169+{
170+ int i;
171+
172+ check_vect ();
173+
174+ for (i = 0; i < N; i++)
175+ {
176+ in1[i].a = i;
177+ in1[i].b = i + 2;
178+ in2[i].a = 5;
179+ in2[i].b = i + 5;
180+ __asm__ volatile ("");
181+ }
182+
183+ foo ();
184+
185+ for (i = 0; i < N; i++)
186+ {
187+ if (out[i].a != result[2*i] || out[i].b != result[2*i+1])
188+ abort ();
189+ }
190+
191+ return 0;
192+}
193+
194+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
195+/* { dg-final { cleanup-tree-dump "vect" } } */
196
197=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-2.c'
198--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c 1970-01-01 00:00:00 +0000
199+++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c 2011-03-27 09:38:18 +0000
200@@ -0,0 +1,65 @@
201+/* { dg-require-effective-target vect_int } */
202+
203+#include <stdarg.h>
204+#include "tree-vect.h"
205+
206+#define N 50
207+
208+int a[N], b[N], in1[N], in2[N];
209+int result[2*N] = {5,-7,7,-6,9,-5,11,-4,13,-3,15,-2,17,-1,19,0,21,1,23,2,25,3,27,4,29,5,31,6,33,7,35,8,37,9,39,10,41,11,43,12,45,13,47,14,49,15,51,16,53,17,55,18,57,19,59,20,61,21,63,22,65,23,67,24,69,25,71,26,73,27,75,28,77,29,79,30,81,31,83,32,85,33,87,34,89,35,91,36,93,37,95,38,97,39,99,40,101,41,103,42};
210+
211+__attribute__ ((noinline)) void
212+foo (int *pa, int *pb)
213+{
214+ int i;
215+ int c, d;
216+
217+ /* Store sinking should not work here since the pointers may alias. */
218+ for (i = 0; i < N; i++)
219+ {
220+ c = in1[i];
221+ d = in2[i];
222+
223+ if (c >= d)
224+ {
225+ *pa = c;
226+ *pb = d + 5;
227+ }
228+ else
229+ {
230+ *pb = d - 12;
231+ *pa = c + d;
232+ }
233+
234+ pa++;
235+ pb++;
236+ }
237+}
238+
239+int
240+main (void)
241+{
242+ int i;
243+
244+ check_vect ();
245+
246+ for (i = 0; i < N; i++)
247+ {
248+ in1[i] = i;
249+ in2[i] = i + 5;
250+ __asm__ volatile ("");
251+ }
252+
253+ foo (a, b);
254+
255+ for (i = 0; i < N; i++)
256+ {
257+ if (a[i] != result[2*i] || b[i] != result[2*i+1])
258+ abort ();
259+ }
260+
261+ return 0;
262+}
263+
264+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
265+/* { dg-final { cleanup-tree-dump "vect" } } */
266
267=== modified file 'gcc/tree-data-ref.c'
268--- old/gcc/tree-data-ref.c 2011-02-05 01:39:20 +0000
269+++ new/gcc/tree-data-ref.c 2011-03-27 09:38:18 +0000
270@@ -991,6 +991,48 @@
271 return dr;
272 }
273
274+/* Check if OFFSET1 and OFFSET2 (DR_OFFSETs of some data-refs) are identical
275+ expressions. */
276+static bool
277+dr_equal_offsets_p1 (tree offset1, tree offset2)
278+{
279+ bool res;
280+
281+ STRIP_NOPS (offset1);
282+ STRIP_NOPS (offset2);
283+
284+ if (offset1 == offset2)
285+ return true;
286+
287+ if (TREE_CODE (offset1) != TREE_CODE (offset2)
288+ || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1)))
289+ return false;
290+
291+ res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 0),
292+ TREE_OPERAND (offset2, 0));
293+
294+ if (!res || !BINARY_CLASS_P (offset1))
295+ return res;
296+
297+ res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 1),
298+ TREE_OPERAND (offset2, 1));
299+
300+ return res;
301+}
302+
303+/* Check if DRA and DRB have equal offsets. */
304+bool
305+dr_equal_offsets_p (struct data_reference *dra,
306+ struct data_reference *drb)
307+{
308+ tree offset1, offset2;
309+
310+ offset1 = DR_OFFSET (dra);
311+ offset2 = DR_OFFSET (drb);
312+
313+ return dr_equal_offsets_p1 (offset1, offset2);
314+}
315+
316 /* Returns true if FNA == FNB. */
317
318 static bool
319@@ -4294,7 +4336,7 @@
320 DATAREFS. Returns chrec_dont_know when failing to analyze a
321 difficult case, returns NULL_TREE otherwise. */
322
323-static tree
324+tree
325 find_data_references_in_bb (struct loop *loop, basic_block bb,
326 VEC (data_reference_p, heap) **datarefs)
327 {
328
329=== modified file 'gcc/tree-data-ref.h'
330--- old/gcc/tree-data-ref.h 2011-01-25 21:24:23 +0000
331+++ new/gcc/tree-data-ref.h 2011-03-27 09:38:18 +0000
332@@ -426,10 +426,14 @@
333 extern void compute_all_dependences (VEC (data_reference_p, heap) *,
334 VEC (ddr_p, heap) **, VEC (loop_p, heap) *,
335 bool);
336+extern tree find_data_references_in_bb (struct loop *, basic_block,
337+ VEC (data_reference_p, heap) **);
338
339 extern void create_rdg_vertices (struct graph *, VEC (gimple, heap) *);
340 extern bool dr_may_alias_p (const struct data_reference *,
341 const struct data_reference *);
342+extern bool dr_equal_offsets_p (struct data_reference *,
343+ struct data_reference *);
344
345
346 /* Return true when the base objects of data references A and B are
347
348=== modified file 'gcc/tree-ssa-phiopt.c'
349--- old/gcc/tree-ssa-phiopt.c 2010-11-03 15:18:50 +0000
350+++ new/gcc/tree-ssa-phiopt.c 2011-03-27 09:38:18 +0000
351@@ -34,6 +34,8 @@
352 #include "langhooks.h"
353 #include "pointer-set.h"
354 #include "domwalk.h"
355+#include "cfgloop.h"
356+#include "tree-data-ref.h"
357
358 static unsigned int tree_ssa_phiopt (void);
359 static unsigned int tree_ssa_phiopt_worker (bool);
360@@ -1292,35 +1294,18 @@
361 return true;
362 }
363
364-/* Do the main work of conditional store replacement. We already know
365- that the recognized pattern looks like so:
366-
367- split:
368- if (cond) goto THEN_BB; else goto ELSE_BB (edge E1)
369- THEN_BB:
370- X = Y;
371- goto JOIN_BB;
372- ELSE_BB:
373- X = Z;
374- fallthrough (edge E0)
375- JOIN_BB:
376- some more
377-
378- We check that THEN_BB and ELSE_BB contain only one store
379- that the stores have a "simple" RHS. */
380+/* Do the main work of conditional store replacement. */
381
382 static bool
383-cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb,
384- basic_block join_bb)
385+cond_if_else_store_replacement_1 (basic_block then_bb, basic_block else_bb,
386+ basic_block join_bb, gimple then_assign,
387+ gimple else_assign)
388 {
389- gimple then_assign = last_and_only_stmt (then_bb);
390- gimple else_assign = last_and_only_stmt (else_bb);
391 tree lhs_base, lhs, then_rhs, else_rhs;
392 source_location then_locus, else_locus;
393 gimple_stmt_iterator gsi;
394 gimple newphi, new_stmt;
395
396- /* Check if then_bb and else_bb contain only one store each. */
397 if (then_assign == NULL
398 || !gimple_assign_single_p (then_assign)
399 || else_assign == NULL
400@@ -1385,6 +1370,190 @@
401 return true;
402 }
403
404+/* Conditional store replacement. We already know
405+ that the recognized pattern looks like so:
406+
407+ split:
408+ if (cond) goto THEN_BB; else goto ELSE_BB (edge E1)
409+ THEN_BB:
410+ ...
411+ X = Y;
412+ ...
413+ goto JOIN_BB;
414+ ELSE_BB:
415+ ...
416+ X = Z;
417+ ...
418+ fallthrough (edge E0)
419+ JOIN_BB:
420+ some more
421+
422+ We check that it is safe to sink the store to JOIN_BB by verifying that
423+ there are no read-after-write or write-after-write dependencies in
424+ THEN_BB and ELSE_BB. */
425+
426+static bool
427+cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb,
428+ basic_block join_bb)
429+{
430+ gimple then_assign = last_and_only_stmt (then_bb);
431+ gimple else_assign = last_and_only_stmt (else_bb);
432+ VEC (data_reference_p, heap) *then_datarefs, *else_datarefs;
433+ VEC (ddr_p, heap) *then_ddrs, *else_ddrs;
434+ gimple then_store, else_store;
435+ bool found, ok = false, res;
436+ struct data_dependence_relation *ddr;
437+ data_reference_p then_dr, else_dr;
438+ int i, j;
439+ tree then_lhs, else_lhs;
440+ VEC (gimple, heap) *then_stores, *else_stores;
441+ basic_block blocks[3];
442+
443+ if (MAX_STORES_TO_SINK == 0)
444+ return false;
445+
446+ /* Handle the case with single statement in THEN_BB and ELSE_BB. */
447+ if (then_assign && else_assign)
448+ return cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
449+ then_assign, else_assign);
450+
451+ /* Find data references. */
452+ then_datarefs = VEC_alloc (data_reference_p, heap, 1);
453+ else_datarefs = VEC_alloc (data_reference_p, heap, 1);
454+ if ((find_data_references_in_bb (NULL, then_bb, &then_datarefs)
455+ == chrec_dont_know)
456+ || !VEC_length (data_reference_p, then_datarefs)
457+ || (find_data_references_in_bb (NULL, else_bb, &else_datarefs)
458+ == chrec_dont_know)
459+ || !VEC_length (data_reference_p, else_datarefs))
460+ {
461+ free_data_refs (then_datarefs);
462+ free_data_refs (else_datarefs);
463+ return false;
464+ }
465+
466+ /* Find pairs of stores with equal LHS. */
467+ then_stores = VEC_alloc (gimple, heap, 1);
468+ else_stores = VEC_alloc (gimple, heap, 1);
469+ FOR_EACH_VEC_ELT (data_reference_p, then_datarefs, i, then_dr)
470+ {
471+ if (DR_IS_READ (then_dr))
472+ continue;
473+
474+ then_store = DR_STMT (then_dr);
475+ then_lhs = gimple_assign_lhs (then_store);
476+ found = false;
477+
478+ FOR_EACH_VEC_ELT (data_reference_p, else_datarefs, j, else_dr)
479+ {
480+ if (DR_IS_READ (else_dr))
481+ continue;
482+
483+ else_store = DR_STMT (else_dr);
484+ else_lhs = gimple_assign_lhs (else_store);
485+
486+ if (operand_equal_p (then_lhs, else_lhs, 0))
487+ {
488+ found = true;
489+ break;
490+ }
491+ }
492+
493+ if (!found)
494+ continue;
495+
496+ VEC_safe_push (gimple, heap, then_stores, then_store);
497+ VEC_safe_push (gimple, heap, else_stores, else_store);
498+ }
499+
500+ /* No pairs of stores found. */
501+ if (!VEC_length (gimple, then_stores)
502+ || VEC_length (gimple, then_stores) > (unsigned) MAX_STORES_TO_SINK)
503+ {
504+ free_data_refs (then_datarefs);
505+ free_data_refs (else_datarefs);
506+ VEC_free (gimple, heap, then_stores);
507+ VEC_free (gimple, heap, else_stores);
508+ return false;
509+ }
510+
511+ /* Compute and check data dependencies in both basic blocks. */
512+ then_ddrs = VEC_alloc (ddr_p, heap, 1);
513+ else_ddrs = VEC_alloc (ddr_p, heap, 1);
514+ compute_all_dependences (then_datarefs, &then_ddrs, NULL, false);
515+ compute_all_dependences (else_datarefs, &else_ddrs, NULL, false);
516+ blocks[0] = then_bb;
517+ blocks[1] = else_bb;
518+ blocks[2] = join_bb;
519+ renumber_gimple_stmt_uids_in_blocks (blocks, 3);
520+
521+ /* Check that there are no read-after-write or write-after-write dependencies
522+ in THEN_BB. */
523+ FOR_EACH_VEC_ELT (ddr_p, then_ddrs, i, ddr)
524+ {
525+ struct data_reference *dra = DDR_A (ddr);
526+ struct data_reference *drb = DDR_B (ddr);
527+
528+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
529+ && ((DR_IS_READ (dra) && DR_IS_WRITE (drb)
530+ && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb)))
531+ || (DR_IS_READ (drb) && DR_IS_WRITE (dra)
532+ && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra)))
533+ || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb))))
534+ {
535+ free_dependence_relations (then_ddrs);
536+ free_dependence_relations (else_ddrs);
537+ free_data_refs (then_datarefs);
538+ free_data_refs (else_datarefs);
539+ VEC_free (gimple, heap, then_stores);
540+ VEC_free (gimple, heap, else_stores);
541+ return false;
542+ }
543+ }
544+
545+ /* Check that there are no read-after-write or write-after-write dependencies
546+ in ELSE_BB. */
547+ FOR_EACH_VEC_ELT (ddr_p, else_ddrs, i, ddr)
548+ {
549+ struct data_reference *dra = DDR_A (ddr);
550+ struct data_reference *drb = DDR_B (ddr);
551+
552+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
553+ && ((DR_IS_READ (dra) && DR_IS_WRITE (drb)
554+ && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb)))
555+ || (DR_IS_READ (drb) && DR_IS_WRITE (dra)
556+ && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra)))
557+ || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb))))
558+ {
559+ free_dependence_relations (then_ddrs);
560+ free_dependence_relations (else_ddrs);
561+ free_data_refs (then_datarefs);
562+ free_data_refs (else_datarefs);
563+ VEC_free (gimple, heap, then_stores);
564+ VEC_free (gimple, heap, else_stores);
565+ return false;
566+ }
567+ }
568+
569+ /* Sink stores with same LHS. */
570+ FOR_EACH_VEC_ELT (gimple, then_stores, i, then_store)
571+ {
572+ else_store = VEC_index (gimple, else_stores, i);
573+ res = cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
574+ then_store, else_store);
575+ ok = ok || res;
576+ }
577+
578+ free_dependence_relations (then_ddrs);
579+ free_dependence_relations (else_ddrs);
580+ free_data_refs (then_datarefs);
581+ free_data_refs (else_datarefs);
582+ VEC_free (gimple, heap, then_stores);
583+ VEC_free (gimple, heap, else_stores);
584+
585+ return ok;
586+}
587+
588 /* Always do these optimizations if we have SSA
589 trees to work on. */
590 static bool
591
592=== modified file 'gcc/tree-vect-data-refs.c'
593--- old/gcc/tree-vect-data-refs.c 2011-02-25 11:18:14 +0000
594+++ new/gcc/tree-vect-data-refs.c 2011-03-27 09:38:18 +0000
595@@ -289,39 +289,6 @@
596 }
597 }
598
599-
600-/* Function vect_equal_offsets.
601-
602- Check if OFFSET1 and OFFSET2 are identical expressions. */
603-
604-static bool
605-vect_equal_offsets (tree offset1, tree offset2)
606-{
607- bool res;
608-
609- STRIP_NOPS (offset1);
610- STRIP_NOPS (offset2);
611-
612- if (offset1 == offset2)
613- return true;
614-
615- if (TREE_CODE (offset1) != TREE_CODE (offset2)
616- || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1)))
617- return false;
618-
619- res = vect_equal_offsets (TREE_OPERAND (offset1, 0),
620- TREE_OPERAND (offset2, 0));
621-
622- if (!res || !BINARY_CLASS_P (offset1))
623- return res;
624-
625- res = vect_equal_offsets (TREE_OPERAND (offset1, 1),
626- TREE_OPERAND (offset2, 1));
627-
628- return res;
629-}
630-
631-
632 /* Check dependence between DRA and DRB for basic block vectorization.
633 If the accesses share same bases and offsets, we can compare their initial
634 constant offsets to decide whether they differ or not. In case of a read-
635@@ -352,7 +319,7 @@
636 || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
637 || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
638 != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
639- || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb)))
640+ || !dr_equal_offsets_p (dra, drb))
641 return true;
642
643 /* Check the types. */
644@@ -402,7 +369,7 @@
645 || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
646 || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
647 != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
648- || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb))
649+ || !dr_equal_offsets_p (dra, drb)
650 || !tree_int_cst_compare (DR_INIT (dra), DR_INIT (drb))
651 || DR_IS_READ (dra) != DR_IS_READ (drb))
652 return false;
653
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch
new file mode 100644
index 000000000..017b1df7e
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch
@@ -0,0 +1,126 @@
12011-04-21 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2008-12-03 Daniel Jacobowitz <dan@codesourcery.com>
6
7 gcc/testsuite/
8 * gcc.dg/vect/vect-shift-3.c, gcc.dg/vect/vect-shift-4.c: New.
9 * lib/target-supports.exp (check_effective_target_vect_shift_char): New
10 function.
11
12=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c'
13--- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 1970-01-01 00:00:00 +0000
14+++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 2011-04-21 13:51:06 +0000
15@@ -0,0 +1,37 @@
16+/* { dg-require-effective-target vect_shift } */
17+/* { dg-require-effective-target vect_int } */
18+
19+#include "tree-vect.h"
20+
21+#define N 32
22+
23+unsigned short dst[N] __attribute__((aligned(N)));
24+unsigned short src[N] __attribute__((aligned(N)));
25+
26+__attribute__ ((noinline))
27+void array_shift(void)
28+{
29+ int i;
30+ for (i = 0; i < N; i++)
31+ dst[i] = src[i] >> 3;
32+}
33+
34+int main()
35+{
36+ volatile int i;
37+ check_vect ();
38+
39+ for (i = 0; i < N; i++)
40+ src[i] = i << 3;
41+
42+ array_shift ();
43+
44+ for (i = 0; i < N; i++)
45+ if (dst[i] != i)
46+ abort ();
47+
48+ return 0;
49+}
50+
51+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
52+/* { dg-final { cleanup-tree-dump "vect" } } */
53
54=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c'
55--- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 1970-01-01 00:00:00 +0000
56+++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 2011-04-21 13:51:06 +0000
57@@ -0,0 +1,37 @@
58+/* { dg-require-effective-target vect_shift_char } */
59+/* { dg-require-effective-target vect_int } */
60+
61+#include "tree-vect.h"
62+
63+#define N 32
64+
65+unsigned char dst[N] __attribute__((aligned(N)));
66+unsigned char src[N] __attribute__((aligned(N)));
67+
68+__attribute__ ((noinline))
69+void array_shift(void)
70+{
71+ int i;
72+ for (i = 0; i < N; i++)
73+ dst[i] = src[i] >> 3;
74+}
75+
76+int main()
77+{
78+ volatile int i;
79+ check_vect ();
80+
81+ for (i = 0; i < N; i++)
82+ src[i] = i << 3;
83+
84+ array_shift ();
85+
86+ for (i = 0; i < N; i++)
87+ if (dst[i] != i)
88+ abort ();
89+
90+ return 0;
91+}
92+
93+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
94+/* { dg-final { cleanup-tree-dump "vect" } } */
95
96=== modified file 'gcc/testsuite/lib/target-supports.exp'
97--- old/gcc/testsuite/lib/target-supports.exp 2011-02-19 15:31:15 +0000
98+++ new/gcc/testsuite/lib/target-supports.exp 2011-04-21 13:51:06 +0000
99@@ -2308,6 +2308,26 @@
100 }
101
102
103+# Return 1 if the target supports hardware vector shift operation for char.
104+
105+proc check_effective_target_vect_shift_char { } {
106+ global et_vect_shift_char_saved
107+
108+ if [info exists et_vect_shift_char_saved] {
109+ verbose "check_effective_target_vect_shift_char: using cached result" 2
110+ } else {
111+ set et_vect_shift_char_saved 0
112+ if { ([istarget powerpc*-*-*]
113+ && ![istarget powerpc-*-linux*paired*])
114+ || [check_effective_target_arm32] } {
115+ set et_vect_shift_char_saved 1
116+ }
117+ }
118+
119+ verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2
120+ return $et_vect_shift_char_saved
121+}
122+
123 # Return 1 if the target supports hardware vectors of long, 0 otherwise.
124 #
125 # This can change for different subtargets so do not cache the result.
126
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch
new file mode 100644
index 000000000..3dde3b29a
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch
@@ -0,0 +1,177 @@
12011-04-27 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from FSF:
4
5 2011-04-03 Richard Guenther <rguenther@suse.de>
6 Ira Rosen <ira.rosen@linaro.org>
7
8 gcc/
9 * tree-if-conv.c (memrefs_read_or_written_unconditionally): Strip all
10 non-variable offsets and compare the remaining bases of the two
11 accesses instead of looking for exact same data-ref.
12
13 gcc/testsuite/
14 * gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: New test.
15 * gcc.dg/vect/vect.exp: Run if-cvt-stores-vect* tests with
16 -ftree-loop-if-convert-stores.
17
18=== added file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c'
19--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 1970-01-01 00:00:00 +0000
20+++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-04-24 07:45:49 +0000
21@@ -0,0 +1,69 @@
22+/* { dg-require-effective-target vect_int } */
23+
24+#include <stdarg.h>
25+#include "tree-vect.h"
26+
27+#define N 50
28+
29+typedef struct {
30+ short a;
31+ short b;
32+} data;
33+
34+data in1[N], in2[N], out[N];
35+short result[N*2] = {10,-7,11,-6,12,-5,13,-4,14,-3,15,-2,16,-1,17,0,18,1,19,2,20,3,21,4,22,5,23,6,24,7,25,8,26,9,27,10,28,11,29,12,30,13,31,14,32,15,33,16,34,17,35,18,36,19,37,20,38,21,39,22,40,23,41,24,42,25,43,26,44,27,45,28,46,29,47,30,48,31,49,32,50,33,51,34,52,35,53,36,54,37,55,38,56,39,57,40,58,41,59,42};
36+short out1[N], out2[N];
37+
38+__attribute__ ((noinline)) void
39+foo ()
40+{
41+ int i;
42+ short c, d;
43+
44+ for (i = 0; i < N; i++)
45+ {
46+ c = in1[i].b;
47+ d = in2[i].b;
48+
49+ if (c >= d)
50+ {
51+ out[i].b = in1[i].a;
52+ out[i].a = d + 5;
53+ }
54+ else
55+ {
56+ out[i].b = d - 12;
57+ out[i].a = in2[i].a + d;
58+ }
59+ }
60+}
61+
62+int
63+main (void)
64+{
65+ int i;
66+
67+ check_vect ();
68+
69+ for (i = 0; i < N; i++)
70+ {
71+ in1[i].a = i;
72+ in1[i].b = i + 2;
73+ in2[i].a = 5;
74+ in2[i].b = i + 5;
75+ __asm__ volatile ("");
76+ }
77+
78+ foo ();
79+
80+ for (i = 0; i < N; i++)
81+ {
82+ if (out[i].a != result[2*i] || out[i].b != result[2*i+1])
83+ abort ();
84+ }
85+
86+ return 0;
87+}
88+
89+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
90+/* { dg-final { cleanup-tree-dump "vect" } } */
91
92=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
93--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2010-11-22 21:49:19 +0000
94+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-04-24 07:45:49 +0000
95@@ -210,6 +210,12 @@
96 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/ggc-*.\[cS\]]] \
97 "" $DEFAULT_VECTCFLAGS
98
99+# -ftree-loop-if-convert-stores
100+set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
101+lappend DEFAULT_VECTCFLAGS "-ftree-loop-if-convert-stores"
102+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/if-cvt-stores-vect-*.\[cS\]]] \
103+ "" $DEFAULT_VECTCFLAGS
104+
105 # With -O3.
106 # Don't allow IPA cloning, because it throws our counts out of whack.
107 set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
108
109=== modified file 'gcc/tree-if-conv.c'
110--- old/gcc/tree-if-conv.c 2011-02-23 16:49:52 +0000
111+++ new/gcc/tree-if-conv.c 2011-04-24 07:45:49 +0000
112@@ -464,8 +464,8 @@
113 /* Returns true when the memory references of STMT are read or written
114 unconditionally. In other words, this function returns true when
115 for every data reference A in STMT there exist other accesses to
116- the same data reference with predicates that add up (OR-up) to the
117- true predicate: this ensures that the data reference A is touched
118+ a data reference with the same base with predicates that add up (OR-up) to
119+ the true predicate: this ensures that the data reference A is touched
120 (read or written) on every iteration of the if-converted loop. */
121
122 static bool
123@@ -489,21 +489,38 @@
124 continue;
125
126 for (j = 0; VEC_iterate (data_reference_p, drs, j, b); j++)
127- if (DR_STMT (b) != stmt
128- && same_data_refs (a, b))
129- {
130- tree cb = bb_predicate (gimple_bb (DR_STMT (b)));
131-
132- if (DR_RW_UNCONDITIONALLY (b) == 1
133- || is_true_predicate (cb)
134- || is_true_predicate (ca = fold_or_predicates (EXPR_LOCATION (cb),
135- ca, cb)))
136- {
137- DR_RW_UNCONDITIONALLY (a) = 1;
138- DR_RW_UNCONDITIONALLY (b) = 1;
139- found = true;
140- break;
141- }
142+ {
143+ tree ref_base_a = DR_REF (a);
144+ tree ref_base_b = DR_REF (b);
145+
146+ if (DR_STMT (b) == stmt)
147+ continue;
148+
149+ while (TREE_CODE (ref_base_a) == COMPONENT_REF
150+ || TREE_CODE (ref_base_a) == IMAGPART_EXPR
151+ || TREE_CODE (ref_base_a) == REALPART_EXPR)
152+ ref_base_a = TREE_OPERAND (ref_base_a, 0);
153+
154+ while (TREE_CODE (ref_base_b) == COMPONENT_REF
155+ || TREE_CODE (ref_base_b) == IMAGPART_EXPR
156+ || TREE_CODE (ref_base_b) == REALPART_EXPR)
157+ ref_base_b = TREE_OPERAND (ref_base_b, 0);
158+
159+ if (!operand_equal_p (ref_base_a, ref_base_b, 0))
160+ {
161+ tree cb = bb_predicate (gimple_bb (DR_STMT (b)));
162+
163+ if (DR_RW_UNCONDITIONALLY (b) == 1
164+ || is_true_predicate (cb)
165+ || is_true_predicate (ca
166+ = fold_or_predicates (EXPR_LOCATION (cb), ca, cb)))
167+ {
168+ DR_RW_UNCONDITIONALLY (a) = 1;
169+ DR_RW_UNCONDITIONALLY (b) = 1;
170+ found = true;
171+ break;
172+ }
173+ }
174 }
175
176 if (!found)
177
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch
new file mode 100644
index 000000000..2c14ceb8c
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch
@@ -0,0 +1,140 @@
12011-05-02 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from FSF:
4
5 2011-03-27 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * config/arm/arm.c (arm_autovectorize_vector_sizes): New function.
9 (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.
10
11 gcc/testsuite/
12 * gcc.dg/vect/vect-outer-5.c: Reduce the distance between data
13 accesses to preserve the meaning of the test for doubleword vectors.
14 * gcc.dg/vect/no-vfa-pr29145.c: Likewise.
15 * gcc.dg/vect/slp-3.c: Reduce the loop bound for the same reason.
16
17=== modified file 'gcc/config/arm/arm.c'
18--- old/gcc/config/arm/arm.c 2011-03-02 11:38:43 +0000
19+++ new/gcc/config/arm/arm.c 2011-04-28 11:46:58 +0000
20@@ -250,6 +250,7 @@
21 bool is_packed);
22 static void arm_conditional_register_usage (void);
23 static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
24+static unsigned int arm_autovectorize_vector_sizes (void);
25
26
27 /* Table of machine attributes. */
28@@ -395,6 +396,9 @@
29 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
30 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
31 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
32+#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
33+#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
34+ arm_autovectorize_vector_sizes
35
36 #undef TARGET_MACHINE_DEPENDENT_REORG
37 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
38@@ -23511,6 +23515,12 @@
39 }
40 }
41
42+static unsigned int
43+arm_autovectorize_vector_sizes (void)
44+{
45+ return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0;
46+}
47+
48 static bool
49 arm_vector_alignment_reachable (const_tree type, bool is_packed)
50 {
51
52=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c'
53--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2010-10-04 14:59:30 +0000
54+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2011-04-28 11:46:58 +0000
55@@ -8,7 +8,7 @@
56 void with_restrict(int * __restrict p)
57 {
58 int i;
59- int *q = p - 2;
60+ int *q = p - 1;
61
62 for (i = 0; i < 1000; ++i) {
63 p[i] = q[i];
64@@ -19,7 +19,7 @@
65 void without_restrict(int * p)
66 {
67 int i;
68- int *q = p - 2;
69+ int *q = p - 1;
70
71 for (i = 0; i < 1000; ++i) {
72 p[i] = q[i];
73@@ -38,8 +38,8 @@
74 a[i] = b[i] = i;
75 }
76
77- with_restrict(a + 2);
78- without_restrict(b + 2);
79+ with_restrict(a + 1);
80+ without_restrict(b + 1);
81
82 for (i = 0; i < 1002; ++i) {
83 if (a[i] != b[i])
84
85=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c'
86--- old/gcc/testsuite/gcc.dg/vect/slp-3.c 2010-11-22 12:16:52 +0000
87+++ new/gcc/testsuite/gcc.dg/vect/slp-3.c 2011-04-28 11:46:58 +0000
88@@ -4,9 +4,9 @@
89 #include <stdarg.h>
90 #include "tree-vect.h"
91
92-#define N 8
93+#define N 12
94
95-unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
96+unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
97
98 int
99 main1 ()
100@@ -101,7 +101,7 @@
101 }
102
103 /* SLP with unrolling by 8. */
104- for (i = 0; i < N/2; i++)
105+ for (i = 0; i < N/4; i++)
106 {
107 out[i*9] = in[i*9];
108 out[i*9 + 1] = in[i*9 + 1];
109@@ -115,7 +115,7 @@
110 }
111
112 /* check results: */
113- for (i = 0; i < N/2; i++)
114+ for (i = 0; i < N/4; i++)
115 {
116 if (out[i*9] != in[i*9]
117 || out[i*9 + 1] != in[i*9 + 1]
118
119=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c'
120--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2010-11-22 12:16:52 +0000
121+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2011-04-28 11:46:58 +0000
122@@ -17,7 +17,7 @@
123 float B[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
124 float C[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
125 float D[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
126- float E[4] = {0,1,2,480};
127+ float E[4] = {0,480,960,1440};
128 float s;
129
130 int i, j;
131@@ -55,7 +55,7 @@
132 s = 0;
133 for (j=0; j<N; j+=4)
134 s += C[j];
135- B[i+3] = B[i] + s;
136+ B[i+1] = B[i] + s;
137 }
138
139 /* check results: */
140
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106740.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106740.patch
new file mode 100644
index 000000000..11a1da670
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106740.patch
@@ -0,0 +1,294 @@
12011-05-04 Richard Sandiford <richard.sandiford@linaro.org>
2
3 Backport from mainline:
4
5 2011-03-29 Richard Sandiford <richard.sandiford@linaro.org>
6
7 PR debug/48190
8 * dwarf2out.c (dw_loc_list_node): Add resolved_addr and replaced.
9 (cached_dw_loc_list_def): New structure.
10 (cached_dw_loc_list): New typedef.
11 (cached_dw_loc_list_table): New variable.
12 (cached_dw_loc_list_table_hash): New function.
13 (cached_dw_loc_list_table_eq): Likewise.
14 (add_location_or_const_value_attribute): Take a bool cache_p.
15 Cache the list when the parameter is true.
16 (gen_formal_parameter_die): Update caller.
17 (gen_variable_die): Likewise.
18 (dwarf2out_finish): Likewise.
19 (dwarf2out_abstract_function): Nullify cached_dw_loc_list_table
20 while generating debug info for the decl.
21 (dwarf2out_function_decl): Clear cached_dw_loc_list_table.
22 (dwarf2out_init): Initialize cached_dw_loc_list_table.
23 (resolve_addr): Cache the result of resolving a chain of
24 location lists.
25
26=== modified file 'gcc/dwarf2out.c'
27--- old/gcc/dwarf2out.c 2011-03-29 22:47:59 +0000
28+++ new/gcc/dwarf2out.c 2011-05-04 13:20:12 +0000
29@@ -4427,6 +4427,11 @@
30 const char *section; /* Section this loclist is relative to */
31 dw_loc_descr_ref expr;
32 hashval_t hash;
33+ /* True if all addresses in this and subsequent lists are known to be
34+ resolved. */
35+ bool resolved_addr;
36+ /* True if this list has been replaced by dw_loc_next. */
37+ bool replaced;
38 bool emitted;
39 } dw_loc_list_node;
40
41@@ -6087,6 +6092,19 @@
42 /* Table of decl location linked lists. */
43 static GTY ((param_is (var_loc_list))) htab_t decl_loc_table;
44
45+/* A cached location list. */
46+struct GTY (()) cached_dw_loc_list_def {
47+ /* The DECL_UID of the decl that this entry describes. */
48+ unsigned int decl_id;
49+
50+ /* The cached location list. */
51+ dw_loc_list_ref loc_list;
52+};
53+typedef struct cached_dw_loc_list_def cached_dw_loc_list;
54+
55+/* Table of cached location lists. */
56+static GTY ((param_is (cached_dw_loc_list))) htab_t cached_dw_loc_list_table;
57+
58 /* A pointer to the base of a list of references to DIE's that
59 are uniquely identified by their tag, presence/absence of
60 children DIE's, and list of attribute/value pairs. */
61@@ -6434,7 +6452,7 @@
62 static void insert_double (double_int, unsigned char *);
63 static void insert_float (const_rtx, unsigned char *);
64 static rtx rtl_for_decl_location (tree);
65-static bool add_location_or_const_value_attribute (dw_die_ref, tree,
66+static bool add_location_or_const_value_attribute (dw_die_ref, tree, bool,
67 enum dwarf_attribute);
68 static bool tree_add_const_value_attribute (dw_die_ref, tree);
69 static bool tree_add_const_value_attribute_for_decl (dw_die_ref, tree);
70@@ -8168,6 +8186,24 @@
71 htab_find_with_hash (decl_loc_table, decl, DECL_UID (decl));
72 }
73
74+/* Returns a hash value for X (which really is a cached_dw_loc_list_list). */
75+
76+static hashval_t
77+cached_dw_loc_list_table_hash (const void *x)
78+{
79+ return (hashval_t) ((const cached_dw_loc_list *) x)->decl_id;
80+}
81+
82+/* Return nonzero if decl_id of cached_dw_loc_list X is the same as
83+ UID of decl *Y. */
84+
85+static int
86+cached_dw_loc_list_table_eq (const void *x, const void *y)
87+{
88+ return (((const cached_dw_loc_list *) x)->decl_id
89+ == DECL_UID ((const_tree) y));
90+}
91+
92 /* Equate a DIE to a particular declaration. */
93
94 static void
95@@ -16965,15 +17001,22 @@
96 these things can crop up in other ways also.) Note that one type of
97 constant value which can be passed into an inlined function is a constant
98 pointer. This can happen for example if an actual argument in an inlined
99- function call evaluates to a compile-time constant address. */
100+ function call evaluates to a compile-time constant address.
101+
102+ CACHE_P is true if it is worth caching the location list for DECL,
103+ so that future calls can reuse it rather than regenerate it from scratch.
104+ This is true for BLOCK_NONLOCALIZED_VARS in inlined subroutines,
105+ since we will need to refer to them each time the function is inlined. */
106
107 static bool
108-add_location_or_const_value_attribute (dw_die_ref die, tree decl,
109+add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p,
110 enum dwarf_attribute attr)
111 {
112 rtx rtl;
113 dw_loc_list_ref list;
114 var_loc_list *loc_list;
115+ cached_dw_loc_list *cache;
116+ void **slot;
117
118 if (TREE_CODE (decl) == ERROR_MARK)
119 return false;
120@@ -17010,7 +17053,33 @@
121 && add_const_value_attribute (die, rtl))
122 return true;
123 }
124- list = loc_list_from_tree (decl, decl_by_reference_p (decl) ? 0 : 2);
125+ /* If this decl is from BLOCK_NONLOCALIZED_VARS, we might need its
126+ list several times. See if we've already cached the contents. */
127+ list = NULL;
128+ if (loc_list == NULL || cached_dw_loc_list_table == NULL)
129+ cache_p = false;
130+ if (cache_p)
131+ {
132+ cache = (cached_dw_loc_list *)
133+ htab_find_with_hash (cached_dw_loc_list_table, decl, DECL_UID (decl));
134+ if (cache)
135+ list = cache->loc_list;
136+ }
137+ if (list == NULL)
138+ {
139+ list = loc_list_from_tree (decl, decl_by_reference_p (decl) ? 0 : 2);
140+ /* It is usually worth caching this result if the decl is from
141+ BLOCK_NONLOCALIZED_VARS and if the list has at least two elements. */
142+ if (cache_p && list && list->dw_loc_next)
143+ {
144+ slot = htab_find_slot_with_hash (cached_dw_loc_list_table, decl,
145+ DECL_UID (decl), INSERT);
146+ cache = ggc_alloc_cleared_cached_dw_loc_list ();
147+ cache->decl_id = DECL_UID (decl);
148+ cache->loc_list = list;
149+ *slot = cache;
150+ }
151+ }
152 if (list)
153 {
154 add_AT_location_description (die, attr, list);
155@@ -18702,7 +18771,7 @@
156 equate_decl_number_to_die (node, parm_die);
157 if (! DECL_ABSTRACT (node_or_origin))
158 add_location_or_const_value_attribute (parm_die, node_or_origin,
159- DW_AT_location);
160+ node == NULL, DW_AT_location);
161
162 break;
163
164@@ -18887,6 +18956,7 @@
165 tree context;
166 int was_abstract;
167 htab_t old_decl_loc_table;
168+ htab_t old_cached_dw_loc_list_table;
169
170 /* Make sure we have the actual abstract inline, not a clone. */
171 decl = DECL_ORIGIN (decl);
172@@ -18901,6 +18971,8 @@
173 get locations in abstract instantces. */
174 old_decl_loc_table = decl_loc_table;
175 decl_loc_table = NULL;
176+ old_cached_dw_loc_list_table = cached_dw_loc_list_table;
177+ cached_dw_loc_list_table = NULL;
178
179 /* Be sure we've emitted the in-class declaration DIE (if any) first, so
180 we don't get confused by DECL_ABSTRACT. */
181@@ -18925,6 +18997,7 @@
182
183 current_function_decl = save_fn;
184 decl_loc_table = old_decl_loc_table;
185+ cached_dw_loc_list_table = old_cached_dw_loc_list_table;
186 pop_cfun ();
187 }
188
189@@ -19709,9 +19782,8 @@
190 && !TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl_or_origin)))
191 defer_location (decl_or_origin, var_die);
192 else
193- add_location_or_const_value_attribute (var_die,
194- decl_or_origin,
195- DW_AT_location);
196+ add_location_or_const_value_attribute (var_die, decl_or_origin,
197+ decl == NULL, DW_AT_location);
198 add_pubname (decl_or_origin, var_die);
199 }
200 else
201@@ -21498,6 +21570,7 @@
202 dwarf2out_decl (decl);
203
204 htab_empty (decl_loc_table);
205+ htab_empty (cached_dw_loc_list_table);
206 }
207
208 /* Output a marker (i.e. a label) for the beginning of the generated code for
209@@ -22230,6 +22303,11 @@
210 decl_loc_table = htab_create_ggc (10, decl_loc_table_hash,
211 decl_loc_table_eq, NULL);
212
213+ /* Allocate the cached_dw_loc_list_table. */
214+ cached_dw_loc_list_table
215+ = htab_create_ggc (10, cached_dw_loc_list_table_hash,
216+ cached_dw_loc_list_table_eq, NULL);
217+
218 /* Allocate the initial hunk of the decl_scope_table. */
219 decl_scope_table = VEC_alloc (tree, gc, 256);
220
221@@ -22870,30 +22948,53 @@
222 {
223 dw_die_ref c;
224 dw_attr_ref a;
225- dw_loc_list_ref *curr;
226+ dw_loc_list_ref *curr, *start, loc;
227 unsigned ix;
228
229 FOR_EACH_VEC_ELT (dw_attr_node, die->die_attr, ix, a)
230 switch (AT_class (a))
231 {
232 case dw_val_class_loc_list:
233- curr = AT_loc_list_ptr (a);
234- while (*curr)
235+ start = curr = AT_loc_list_ptr (a);
236+ loc = *curr;
237+ gcc_assert (loc);
238+ /* The same list can be referenced more than once. See if we have
239+ already recorded the result from a previous pass. */
240+ if (loc->replaced)
241+ *curr = loc->dw_loc_next;
242+ else if (!loc->resolved_addr)
243 {
244- if (!resolve_addr_in_expr ((*curr)->expr))
245+ /* As things stand, we do not expect or allow one die to
246+ reference a suffix of another die's location list chain.
247+ References must be identical or completely separate.
248+ There is therefore no need to cache the result of this
249+ pass on any list other than the first; doing so
250+ would lead to unnecessary writes. */
251+ while (*curr)
252 {
253- dw_loc_list_ref next = (*curr)->dw_loc_next;
254- if (next && (*curr)->ll_symbol)
255+ gcc_assert (!(*curr)->replaced && !(*curr)->resolved_addr);
256+ if (!resolve_addr_in_expr ((*curr)->expr))
257 {
258- gcc_assert (!next->ll_symbol);
259- next->ll_symbol = (*curr)->ll_symbol;
260+ dw_loc_list_ref next = (*curr)->dw_loc_next;
261+ if (next && (*curr)->ll_symbol)
262+ {
263+ gcc_assert (!next->ll_symbol);
264+ next->ll_symbol = (*curr)->ll_symbol;
265+ }
266+ *curr = next;
267 }
268- *curr = next;
269+ else
270+ curr = &(*curr)->dw_loc_next;
271 }
272+ if (loc == *start)
273+ loc->resolved_addr = 1;
274 else
275- curr = &(*curr)->dw_loc_next;
276+ {
277+ loc->replaced = 1;
278+ loc->dw_loc_next = *start;
279+ }
280 }
281- if (!AT_loc_list (a))
282+ if (!*start)
283 {
284 remove_AT (die, a->dw_attr);
285 ix--;
286@@ -23322,6 +23423,7 @@
287 add_location_or_const_value_attribute (
288 VEC_index (deferred_locations, deferred_locations_list, i)->die,
289 VEC_index (deferred_locations, deferred_locations_list, i)->variable,
290+ false,
291 DW_AT_location);
292 }
293
294
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch
new file mode 100644
index 000000000..84f6f6498
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch
@@ -0,0 +1,254 @@
12011-04-26 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-04-15 Maxim Kuvyrkov <maxim@codesourcery.com>
6
7 gcc/
8 * combine.c (subst, combine_simlify_rtx): Add new argument, use it
9 to track processing of conditionals. Update all callers.
10 (try_combine, simplify_if_then_else): Update.
11
12 2011-04-25 Maxim Kuvyrkov <maxim@codesourcery.com>
13 Eric Botcazou <ebotcazou@adacore.com>
14
15 gcc/
16 * combine.c (combine_simplify_rtx): Avoid mis-simplifying conditionals
17 for STORE_FLAG_VALUE==-1 case.
18
19=== modified file 'gcc/combine.c'
20--- old/gcc/combine.c 2011-02-15 19:46:26 +0000
21+++ new/gcc/combine.c 2011-04-26 17:03:58 +0000
22@@ -391,8 +391,8 @@
23 static void undo_all (void);
24 static void undo_commit (void);
25 static rtx *find_split_point (rtx *, rtx, bool);
26-static rtx subst (rtx, rtx, rtx, int, int);
27-static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
28+static rtx subst (rtx, rtx, rtx, int, int, int);
29+static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
30 static rtx simplify_if_then_else (rtx);
31 static rtx simplify_set (rtx);
32 static rtx simplify_logical (rtx);
33@@ -3086,12 +3086,12 @@
34 if (i1)
35 {
36 subst_low_luid = DF_INSN_LUID (i1);
37- i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
38+ i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
39 }
40 else
41 {
42 subst_low_luid = DF_INSN_LUID (i2);
43- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
44+ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
45 }
46 }
47
48@@ -3103,7 +3103,7 @@
49 self-referential RTL when we will be substituting I1SRC for I1DEST
50 later. Likewise if I0 feeds into I2, either directly or indirectly
51 through I1, and I0DEST is in I0SRC. */
52- newpat = subst (PATTERN (i3), i2dest, i2src, 0,
53+ newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
54 (i1_feeds_i2_n && i1dest_in_i1src)
55 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
56 && i0dest_in_i0src));
57@@ -3142,7 +3142,7 @@
58 copy of I1SRC each time we substitute it, in order to avoid creating
59 self-referential RTL when we will be substituting I0SRC for I0DEST
60 later. */
61- newpat = subst (newpat, i1dest, i1src, 0,
62+ newpat = subst (newpat, i1dest, i1src, 0, 0,
63 i0_feeds_i1_n && i0dest_in_i0src);
64 substed_i1 = 1;
65
66@@ -3172,7 +3172,7 @@
67
68 n_occurrences = 0;
69 subst_low_luid = DF_INSN_LUID (i0);
70- newpat = subst (newpat, i0dest, i0src, 0, 0);
71+ newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
72 substed_i0 = 1;
73 }
74
75@@ -3234,7 +3234,7 @@
76 {
77 rtx t = i1pat;
78 if (i0_feeds_i1_n)
79- t = subst (t, i0dest, i0src, 0, 0);
80+ t = subst (t, i0dest, i0src, 0, 0, 0);
81
82 XVECEXP (newpat, 0, --total_sets) = t;
83 }
84@@ -3242,10 +3242,10 @@
85 {
86 rtx t = i2pat;
87 if (i1_feeds_i2_n)
88- t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
89+ t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
90 i0_feeds_i1_n && i0dest_in_i0src);
91 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
92- t = subst (t, i0dest, i0src, 0, 0);
93+ t = subst (t, i0dest, i0src, 0, 0, 0);
94
95 XVECEXP (newpat, 0, --total_sets) = t;
96 }
97@@ -4914,11 +4914,13 @@
98
99 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
100
101+ IN_COND is nonzero if we are on top level of the condition.
102+
103 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
104 by copying if `n_occurrences' is nonzero. */
105
106 static rtx
107-subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
108+subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
109 {
110 enum rtx_code code = GET_CODE (x);
111 enum machine_mode op0_mode = VOIDmode;
112@@ -4979,7 +4981,7 @@
113 && GET_CODE (XVECEXP (x, 0, 0)) == SET
114 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
115 {
116- new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
117+ new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
118
119 /* If this substitution failed, this whole thing fails. */
120 if (GET_CODE (new_rtx) == CLOBBER
121@@ -4996,7 +4998,7 @@
122 && GET_CODE (dest) != CC0
123 && GET_CODE (dest) != PC)
124 {
125- new_rtx = subst (dest, from, to, 0, unique_copy);
126+ new_rtx = subst (dest, from, to, 0, 0, unique_copy);
127
128 /* If this substitution failed, this whole thing fails. */
129 if (GET_CODE (new_rtx) == CLOBBER
130@@ -5042,8 +5044,8 @@
131 }
132 else
133 {
134- new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
135- unique_copy);
136+ new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
137+ unique_copy);
138
139 /* If this substitution failed, this whole thing
140 fails. */
141@@ -5120,7 +5122,9 @@
142 && (code == SUBREG || code == STRICT_LOW_PART
143 || code == ZERO_EXTRACT))
144 || code == SET)
145- && i == 0), unique_copy);
146+ && i == 0),
147+ code == IF_THEN_ELSE && i == 0,
148+ unique_copy);
149
150 /* If we found that we will have to reject this combination,
151 indicate that by returning the CLOBBER ourselves, rather than
152@@ -5177,7 +5181,7 @@
153 /* If X is sufficiently simple, don't bother trying to do anything
154 with it. */
155 if (code != CONST_INT && code != REG && code != CLOBBER)
156- x = combine_simplify_rtx (x, op0_mode, in_dest);
157+ x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
158
159 if (GET_CODE (x) == code)
160 break;
161@@ -5197,10 +5201,12 @@
162 expression.
163
164 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
165- if we are inside a SET_DEST. */
166+ if we are inside a SET_DEST. IN_COND is nonzero if we are on the top level
167+ of a condition. */
168
169 static rtx
170-combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
171+combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
172+ int in_cond)
173 {
174 enum rtx_code code = GET_CODE (x);
175 enum machine_mode mode = GET_MODE (x);
176@@ -5255,8 +5261,8 @@
177 false arms to store-flag values. Be careful to use copy_rtx
178 here since true_rtx or false_rtx might share RTL with x as a
179 result of the if_then_else_cond call above. */
180- true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
181- false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
182+ true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
183+ false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
184
185 /* If true_rtx and false_rtx are not general_operands, an if_then_else
186 is unlikely to be simpler. */
187@@ -5600,7 +5606,7 @@
188 {
189 /* Try to simplify the expression further. */
190 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
191- temp = combine_simplify_rtx (tor, mode, in_dest);
192+ temp = combine_simplify_rtx (tor, mode, in_dest, 0);
193
194 /* If we could, great. If not, do not go ahead with the IOR
195 replacement, since PLUS appears in many special purpose
196@@ -5693,7 +5699,16 @@
197 ZERO_EXTRACT is indeed appropriate, it will be placed back by
198 the call to make_compound_operation in the SET case. */
199
200- if (STORE_FLAG_VALUE == 1
201+ if (in_cond)
202+ /* Don't apply below optimizations if the caller would
203+ prefer a comparison rather than a value.
204+ E.g., for the condition in an IF_THEN_ELSE most targets need
205+ an explicit comparison. */
206+ {
207+ ;
208+ }
209+
210+ else if (STORE_FLAG_VALUE == 1
211 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
212 && op1 == const0_rtx
213 && mode == GET_MODE (op0)
214@@ -5739,7 +5754,10 @@
215
216 /* If STORE_FLAG_VALUE is -1, we have cases similar to
217 those above. */
218- if (STORE_FLAG_VALUE == -1
219+ if (in_cond)
220+ ;
221+
222+ else if (STORE_FLAG_VALUE == -1
223 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
224 && op1 == const0_rtx
225 && (num_sign_bit_copies (op0, mode)
226@@ -5937,11 +5955,11 @@
227 if (reg_mentioned_p (from, true_rtx))
228 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
229 from, true_val),
230- pc_rtx, pc_rtx, 0, 0);
231+ pc_rtx, pc_rtx, 0, 0, 0);
232 if (reg_mentioned_p (from, false_rtx))
233 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
234 from, false_val),
235- pc_rtx, pc_rtx, 0, 0);
236+ pc_rtx, pc_rtx, 0, 0, 0);
237
238 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
239 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
240@@ -6158,11 +6176,11 @@
241 {
242 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
243 cond_op0, cond_op1),
244- pc_rtx, pc_rtx, 0, 0);
245+ pc_rtx, pc_rtx, 0, 0, 0);
246 temp = simplify_gen_binary (MULT, m, temp,
247 simplify_gen_binary (MULT, m, c1,
248 const_true_rtx));
249- temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
250+ temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
251 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
252
253 if (extend_op != UNKNOWN)
254
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch
new file mode 100644
index 000000000..d14f06c3f
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch
@@ -0,0 +1,6123 @@
12011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/testsuite/
4 From Richard Earnshaw <rearnsha@arm.com>
5
6 PR target/46329
7 * gcc.target/arm/pr46329.c: New test.
8
9 gcc/
10 PR target/46329
11 * config/arm/arm.c (arm_legitimate_constant_p_1): Return false
12 for all Neon struct constants.
13
142011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
15
16 gcc/
17 * targhooks.h (default_legitimate_constant_p); Declare.
18 * targhooks.c (default_legitimate_constant_p): New function.
19
20 Backport from mainline:
21 2011-04-21 Richard Sandiford <richard.sandiford@linaro.org>
22
23 * target.def (legitimate_constant_p): New hook.
24 * doc/tm.texi.in (LEGITIMATE_CONSTANT_P): Replace with...
25 (TARGET_LEGITIMATE_CONSTANT_P): ...this.
26 * doc/tm.texi: Regenerate.
27 * calls.c (precompute_register_parameters): Replace uses of
28 LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p.
29 (emit_library_call_value_1): Likewise.
30 * expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn)
31 (compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise.
32 * recog.c (general_operand, immediate_operand): Likewise.
33 * reload.c (find_reloads_toplev, find_reloads_address_part): Likewise.
34 * reload1.c (init_eliminable_invariants): Likewise.
35
36 * config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete.
37 * config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise.
38 (THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise.
39 * config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define.
40 (arm_legitimate_constant_p_1, thumb_legitimate_constant_p)
41 (arm_legitimate_constant_p): New functions.
42 (arm_cannot_force_const_mem): Make static.
43
442011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
45
46 gcc/
47 Backport from mainline:
48
49 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
50
51 * hooks.h (hook_bool_mode_uhwi_false): Declare.
52 * hooks.c (hook_bool_mode_uhwi_false): New function.
53 * target.def (array_mode_supported_p): New hook.
54 * doc/tm.texi.in (TARGET_ARRAY_MODE_SUPPORTED_P): Add @hook.
55 * doc/tm.texi: Regenerate.
56 * stor-layout.c (mode_for_array): New function.
57 (layout_type): Use it.
58 * config/arm/arm.c (arm_array_mode_supported_p): New function.
59 (TARGET_ARRAY_MODE_SUPPORTED_P): Define.
60
612011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
62
63 gcc/
64 Backport from mainline:
65
66 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
67
68 * config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
69 size of a '%A' memory reference.
70 (T_DREG, T_QREG): New neon_builtin_type_bits.
71 (arm_init_neon_builtins): Assert that the load and store operands
72 are neon_struct_operands.
73 (locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
74 (NEON_ARG_MEMORY): New builtin_arg.
75 (neon_dereference_pointer): New function.
76 (arm_expand_neon_args): Add a neon_builtin_type_bits argument.
77 Handle NEON_ARG_MEMORY.
78 (arm_expand_neon_builtin): Update after above interface changes.
79 Use NEON_ARG_MEMORY for loads and stores.
80 * config/arm/predicates.md (neon_struct_operand): New predicate.
81 * config/arm/iterators.md (V_two_elem): Tweak formatting.
82 (V_three_elem): Use BLKmode for accesses that have no associated mode.
83 (V_four_elem): Tweak formatting.
84 * config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
85 (neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
86 (neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
87 (neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
88 (neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
89 (neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
90 (neon_vst4<mode>): Replace pointer operand with a memory operand.
91 Use %A in the output template.
92 (neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
93 (neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
94 (neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
95 the width of the memory access. Remove post-increment.
96 * config/arm/neon-testgen.ml: Allow addresses to have an alignment.
97
98 gcc/testsuite/
99 Backport from mainline:
100
101 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
102
103 * gcc.target/arm/neon-vld3-1.c: New test.
104 * gcc.target/arm/neon-vst3-1.c: New test.
105 * gcc.target/arm/neon/v*.c: Regenerate.
106
1072011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
108
109 gcc/
110 Backport from mainline:
111
112 2011-03-30 Richard Sandiford <richard.sandiford@linaro.org>
113 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
114
115 PR target/43590
116 * config/arm/neon.md (neon_vld3qa<mode>, neon_vld4qa<mode>): Remove
117 operand 1 and reshuffle the operands to match.
118 (neon_vld3<mode>, neon_vld4<mode>): Update accordingly.
119
120=== modified file 'gcc/calls.c'
121--- old/gcc/calls.c 2011-03-03 21:56:58 +0000
122+++ new/gcc/calls.c 2011-05-03 15:17:25 +0000
123@@ -684,7 +684,7 @@
124 /* If the value is a non-legitimate constant, force it into a
125 pseudo now. TLS symbols sometimes need a call to resolve. */
126 if (CONSTANT_P (args[i].value)
127- && !LEGITIMATE_CONSTANT_P (args[i].value))
128+ && !targetm.legitimate_constant_p (args[i].mode, args[i].value))
129 args[i].value = force_reg (args[i].mode, args[i].value);
130
131 /* If we are to promote the function arg to a wider mode,
132@@ -3447,7 +3447,8 @@
133
134 /* Make sure it is a reasonable operand for a move or push insn. */
135 if (!REG_P (addr) && !MEM_P (addr)
136- && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr)))
137+ && !(CONSTANT_P (addr)
138+ && targetm.legitimate_constant_p (Pmode, addr)))
139 addr = force_operand (addr, NULL_RTX);
140
141 argvec[count].value = addr;
142@@ -3488,7 +3489,7 @@
143
144 /* Make sure it is a reasonable operand for a move or push insn. */
145 if (!REG_P (val) && !MEM_P (val)
146- && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val)))
147+ && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val)))
148 val = force_operand (val, NULL_RTX);
149
150 if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1))
151
152=== modified file 'gcc/config/arm/arm-protos.h'
153--- old/gcc/config/arm/arm-protos.h 2011-01-29 03:20:57 +0000
154+++ new/gcc/config/arm/arm-protos.h 2011-05-03 15:17:25 +0000
155@@ -81,7 +81,6 @@
156 extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
157 bool);
158 extern bool arm_tls_referenced_p (rtx);
159-extern bool arm_cannot_force_const_mem (rtx);
160
161 extern int cirrus_memory_offset (rtx);
162 extern int arm_coproc_mem_operand (rtx, bool);
163
164=== modified file 'gcc/config/arm/arm.c'
165--- old/gcc/config/arm/arm.c 2011-04-28 11:46:58 +0000
166+++ new/gcc/config/arm/arm.c 2011-05-03 15:18:07 +0000
167@@ -143,6 +143,8 @@
168 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
169 tree);
170 static bool arm_have_conditional_execution (void);
171+static bool arm_cannot_force_const_mem (rtx);
172+static bool arm_legitimate_constant_p (enum machine_mode, rtx);
173 static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
174 static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
175 static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
176@@ -241,6 +243,8 @@
177 static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
178 static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
179 static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *);
180+static bool arm_array_mode_supported_p (enum machine_mode,
181+ unsigned HOST_WIDE_INT);
182 static enum machine_mode arm_preferred_simd_mode (enum machine_mode);
183 static bool arm_class_likely_spilled_p (reg_class_t);
184 static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
185@@ -394,6 +398,8 @@
186 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
187 #undef TARGET_VECTOR_MODE_SUPPORTED_P
188 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
189+#undef TARGET_ARRAY_MODE_SUPPORTED_P
190+#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
191 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
192 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
193 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
194@@ -523,6 +529,9 @@
195 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
196 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
197
198+#undef TARGET_LEGITIMATE_CONSTANT_P
199+#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
200+
201 #undef TARGET_CANNOT_FORCE_CONST_MEM
202 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
203
204@@ -6539,9 +6548,47 @@
205 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
206 }
207
208+/* Implement TARGET_LEGITIMATE_CONSTANT_P.
209+
210+ On the ARM, allow any integer (invalid ones are removed later by insn
211+ patterns), nice doubles and symbol_refs which refer to the function's
212+ constant pool XXX.
213+
214+ When generating pic allow anything. */
215+
216+static bool
217+arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
218+{
219+ /* At present, we have no support for Neon structure constants, so forbid
220+ them here. It might be possible to handle simple cases like 0 and -1
221+ in future. */
222+ if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
223+ return false;
224+
225+ return flag_pic || !label_mentioned_p (x);
226+}
227+
228+static bool
229+thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
230+{
231+ return (GET_CODE (x) == CONST_INT
232+ || GET_CODE (x) == CONST_DOUBLE
233+ || CONSTANT_ADDRESS_P (x)
234+ || flag_pic);
235+}
236+
237+static bool
238+arm_legitimate_constant_p (enum machine_mode mode, rtx x)
239+{
240+ return (!arm_cannot_force_const_mem (x)
241+ && (TARGET_32BIT
242+ ? arm_legitimate_constant_p_1 (mode, x)
243+ : thumb_legitimate_constant_p (mode, x)));
244+}
245+
246 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
247
248-bool
249+static bool
250 arm_cannot_force_const_mem (rtx x)
251 {
252 rtx base, offset;
253@@ -16598,7 +16645,7 @@
254 {
255 rtx addr;
256 bool postinc = FALSE;
257- unsigned align, modesize, align_bits;
258+ unsigned align, memsize, align_bits;
259
260 gcc_assert (GET_CODE (x) == MEM);
261 addr = XEXP (x, 0);
262@@ -16613,12 +16660,12 @@
263 instruction (for some alignments) as an aid to the memory subsystem
264 of the target. */
265 align = MEM_ALIGN (x) >> 3;
266- modesize = GET_MODE_SIZE (GET_MODE (x));
267+ memsize = INTVAL (MEM_SIZE (x));
268
269 /* Only certain alignment specifiers are supported by the hardware. */
270- if (modesize == 16 && (align % 32) == 0)
271+ if (memsize == 16 && (align % 32) == 0)
272 align_bits = 256;
273- else if ((modesize == 8 || modesize == 16) && (align % 16) == 0)
274+ else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
275 align_bits = 128;
276 else if ((align % 8) == 0)
277 align_bits = 64;
278@@ -18278,12 +18325,14 @@
279 T_V2SI = 0x0004,
280 T_V2SF = 0x0008,
281 T_DI = 0x0010,
282+ T_DREG = 0x001F,
283 T_V16QI = 0x0020,
284 T_V8HI = 0x0040,
285 T_V4SI = 0x0080,
286 T_V4SF = 0x0100,
287 T_V2DI = 0x0200,
288 T_TI = 0x0400,
289+ T_QREG = 0x07E0,
290 T_EI = 0x0800,
291 T_OI = 0x1000
292 };
293@@ -18929,10 +18978,9 @@
294 if (is_load && k == 1)
295 {
296 /* Neon load patterns always have the memory operand
297- (a SImode pointer) in the operand 1 position. We
298- want a const pointer to the element type in that
299- position. */
300- gcc_assert (insn_data[icode].operand[k].mode == SImode);
301+ in the operand 1 position. */
302+ gcc_assert (insn_data[icode].operand[k].predicate
303+ == neon_struct_operand);
304
305 switch (1 << j)
306 {
307@@ -18967,10 +19015,9 @@
308 else if (is_store && k == 0)
309 {
310 /* Similarly, Neon store patterns use operand 0 as
311- the memory location to store to (a SImode pointer).
312- Use a pointer to the element type of the store in
313- that position. */
314- gcc_assert (insn_data[icode].operand[k].mode == SImode);
315+ the memory location to store to. */
316+ gcc_assert (insn_data[icode].operand[k].predicate
317+ == neon_struct_operand);
318
319 switch (1 << j)
320 {
321@@ -19290,12 +19337,13 @@
322 }
323
324 static enum insn_code
325-locate_neon_builtin_icode (int fcode, neon_itype *itype)
326+locate_neon_builtin_icode (int fcode, neon_itype *itype,
327+ enum neon_builtin_type_bits *type_bit)
328 {
329 neon_builtin_datum key
330 = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
331 neon_builtin_datum *found;
332- int idx;
333+ int idx, type, ntypes;
334
335 key.base_fcode = fcode;
336 found = (neon_builtin_datum *)
337@@ -19308,20 +19356,84 @@
338 if (itype)
339 *itype = found->itype;
340
341+ if (type_bit)
342+ {
343+ ntypes = 0;
344+ for (type = 0; type < T_MAX; type++)
345+ if (found->bits & (1 << type))
346+ {
347+ if (ntypes == idx)
348+ break;
349+ ntypes++;
350+ }
351+ gcc_assert (type < T_MAX);
352+ *type_bit = (enum neon_builtin_type_bits) (1 << type);
353+ }
354 return found->codes[idx];
355 }
356
357 typedef enum {
358 NEON_ARG_COPY_TO_REG,
359 NEON_ARG_CONSTANT,
360+ NEON_ARG_MEMORY,
361 NEON_ARG_STOP
362 } builtin_arg;
363
364 #define NEON_MAX_BUILTIN_ARGS 5
365
366+/* EXP is a pointer argument to a Neon load or store intrinsic. Derive
367+ and return an expression for the accessed memory.
368+
369+ The intrinsic function operates on a block of registers that has
370+ mode REG_MODE. This block contains vectors of type TYPE_BIT.
371+ The function references the memory at EXP in mode MEM_MODE;
372+ this mode may be BLKmode if no more suitable mode is available. */
373+
374+static tree
375+neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
376+ enum machine_mode reg_mode,
377+ enum neon_builtin_type_bits type_bit)
378+{
379+ HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
380+ tree elem_type, upper_bound, array_type;
381+
382+ /* Work out the size of the register block in bytes. */
383+ reg_size = GET_MODE_SIZE (reg_mode);
384+
385+ /* Work out the size of each vector in bytes. */
386+ gcc_assert (type_bit & (T_DREG | T_QREG));
387+ vector_size = (type_bit & T_QREG ? 16 : 8);
388+
389+ /* Work out how many vectors there are. */
390+ gcc_assert (reg_size % vector_size == 0);
391+ nvectors = reg_size / vector_size;
392+
393+ /* Work out how many elements are being loaded or stored.
394+ MEM_MODE == REG_MODE implies a one-to-one mapping between register
395+ and memory elements; anything else implies a lane load or store. */
396+ if (mem_mode == reg_mode)
397+ nelems = vector_size * nvectors;
398+ else
399+ nelems = nvectors;
400+
401+ /* Work out the type of each element. */
402+ gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
403+ elem_type = TREE_TYPE (TREE_TYPE (exp));
404+
405+ /* Create a type that describes the full access. */
406+ upper_bound = build_int_cst (size_type_node, nelems - 1);
407+ array_type = build_array_type (elem_type, build_index_type (upper_bound));
408+
409+ /* Dereference EXP using that type. */
410+ exp = convert (build_pointer_type (array_type), exp);
411+ return fold_build2 (MEM_REF, array_type, exp,
412+ build_int_cst (TREE_TYPE (exp), 0));
413+}
414+
415 /* Expand a Neon builtin. */
416 static rtx
417 arm_expand_neon_args (rtx target, int icode, int have_retval,
418+ enum neon_builtin_type_bits type_bit,
419 tree exp, ...)
420 {
421 va_list ap;
422@@ -19330,7 +19442,9 @@
423 rtx op[NEON_MAX_BUILTIN_ARGS];
424 enum machine_mode tmode = insn_data[icode].operand[0].mode;
425 enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
426+ enum machine_mode other_mode;
427 int argc = 0;
428+ int opno;
429
430 if (have_retval
431 && (!target
432@@ -19348,26 +19462,46 @@
433 break;
434 else
435 {
436+ opno = argc + have_retval;
437+ mode[argc] = insn_data[icode].operand[opno].mode;
438 arg[argc] = CALL_EXPR_ARG (exp, argc);
439+ if (thisarg == NEON_ARG_MEMORY)
440+ {
441+ other_mode = insn_data[icode].operand[1 - opno].mode;
442+ arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
443+ other_mode, type_bit);
444+ }
445 op[argc] = expand_normal (arg[argc]);
446- mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
447
448 switch (thisarg)
449 {
450 case NEON_ARG_COPY_TO_REG:
451 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
452- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
453+ if (!(*insn_data[icode].operand[opno].predicate)
454 (op[argc], mode[argc]))
455 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
456 break;
457
458 case NEON_ARG_CONSTANT:
459 /* FIXME: This error message is somewhat unhelpful. */
460- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
461+ if (!(*insn_data[icode].operand[opno].predicate)
462 (op[argc], mode[argc]))
463 error ("argument must be a constant");
464 break;
465
466+ case NEON_ARG_MEMORY:
467+ gcc_assert (MEM_P (op[argc]));
468+ PUT_MODE (op[argc], mode[argc]);
469+ /* ??? arm_neon.h uses the same built-in functions for signed
470+ and unsigned accesses, casting where necessary. This isn't
471+ alias safe. */
472+ set_mem_alias_set (op[argc], 0);
473+ if (!(*insn_data[icode].operand[opno].predicate)
474+ (op[argc], mode[argc]))
475+ op[argc] = (replace_equiv_address
476+ (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
477+ break;
478+
479 case NEON_ARG_STOP:
480 gcc_unreachable ();
481 }
482@@ -19446,14 +19580,15 @@
483 arm_expand_neon_builtin (int fcode, tree exp, rtx target)
484 {
485 neon_itype itype;
486- enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
487+ enum neon_builtin_type_bits type_bit;
488+ enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
489
490 switch (itype)
491 {
492 case NEON_UNOP:
493 case NEON_CONVERT:
494 case NEON_DUPLANE:
495- return arm_expand_neon_args (target, icode, 1, exp,
496+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
497 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
498
499 case NEON_BINOP:
500@@ -19463,90 +19598,90 @@
501 case NEON_SCALARMULH:
502 case NEON_SHIFTINSERT:
503 case NEON_LOGICBINOP:
504- return arm_expand_neon_args (target, icode, 1, exp,
505+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
506 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
507 NEON_ARG_STOP);
508
509 case NEON_TERNOP:
510- return arm_expand_neon_args (target, icode, 1, exp,
511+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
512 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
513 NEON_ARG_CONSTANT, NEON_ARG_STOP);
514
515 case NEON_GETLANE:
516 case NEON_FIXCONV:
517 case NEON_SHIFTIMM:
518- return arm_expand_neon_args (target, icode, 1, exp,
519+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
520 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
521 NEON_ARG_STOP);
522
523 case NEON_CREATE:
524- return arm_expand_neon_args (target, icode, 1, exp,
525+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
526 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
527
528 case NEON_DUP:
529 case NEON_SPLIT:
530 case NEON_REINTERP:
531- return arm_expand_neon_args (target, icode, 1, exp,
532+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
533 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
534
535 case NEON_COMBINE:
536 case NEON_VTBL:
537- return arm_expand_neon_args (target, icode, 1, exp,
538+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
539 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
540
541 case NEON_RESULTPAIR:
542- return arm_expand_neon_args (target, icode, 0, exp,
543+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
544 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
545 NEON_ARG_STOP);
546
547 case NEON_LANEMUL:
548 case NEON_LANEMULL:
549 case NEON_LANEMULH:
550- return arm_expand_neon_args (target, icode, 1, exp,
551+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
552 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
553 NEON_ARG_CONSTANT, NEON_ARG_STOP);
554
555 case NEON_LANEMAC:
556- return arm_expand_neon_args (target, icode, 1, exp,
557+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
558 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
559 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
560
561 case NEON_SHIFTACC:
562- return arm_expand_neon_args (target, icode, 1, exp,
563+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
564 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
565 NEON_ARG_CONSTANT, NEON_ARG_STOP);
566
567 case NEON_SCALARMAC:
568- return arm_expand_neon_args (target, icode, 1, exp,
569+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
570 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
571 NEON_ARG_CONSTANT, NEON_ARG_STOP);
572
573 case NEON_SELECT:
574 case NEON_VTBX:
575- return arm_expand_neon_args (target, icode, 1, exp,
576+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
577 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
578 NEON_ARG_STOP);
579
580 case NEON_LOAD1:
581 case NEON_LOADSTRUCT:
582- return arm_expand_neon_args (target, icode, 1, exp,
583- NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
584+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
585+ NEON_ARG_MEMORY, NEON_ARG_STOP);
586
587 case NEON_LOAD1LANE:
588 case NEON_LOADSTRUCTLANE:
589- return arm_expand_neon_args (target, icode, 1, exp,
590- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
591+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
592+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
593 NEON_ARG_STOP);
594
595 case NEON_STORE1:
596 case NEON_STORESTRUCT:
597- return arm_expand_neon_args (target, icode, 0, exp,
598- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
599+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
600+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
601
602 case NEON_STORE1LANE:
603 case NEON_STORESTRUCTLANE:
604- return arm_expand_neon_args (target, icode, 0, exp,
605- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
606+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
607+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
608 NEON_ARG_STOP);
609 }
610
611@@ -22267,6 +22402,20 @@
612 return false;
613 }
614
615+/* Implements target hook array_mode_supported_p. */
616+
617+static bool
618+arm_array_mode_supported_p (enum machine_mode mode,
619+ unsigned HOST_WIDE_INT nelems)
620+{
621+ if (TARGET_NEON
622+ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
623+ && (nelems >= 2 && nelems <= 4))
624+ return true;
625+
626+ return false;
627+}
628+
629 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
630 registers when autovectorizing for Neon, at least until multiple vector
631 widths are supported properly by the middle-end. */
632
633=== modified file 'gcc/config/arm/arm.h'
634--- old/gcc/config/arm/arm.h 2011-02-21 14:04:51 +0000
635+++ new/gcc/config/arm/arm.h 2011-05-03 15:17:25 +0000
636@@ -1775,27 +1775,6 @@
637 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
638 #endif
639
640-/* Nonzero if the constant value X is a legitimate general operand.
641- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
642-
643- On the ARM, allow any integer (invalid ones are removed later by insn
644- patterns), nice doubles and symbol_refs which refer to the function's
645- constant pool XXX.
646-
647- When generating pic allow anything. */
648-#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
649-
650-#define THUMB_LEGITIMATE_CONSTANT_P(X) \
651- ( GET_CODE (X) == CONST_INT \
652- || GET_CODE (X) == CONST_DOUBLE \
653- || CONSTANT_ADDRESS_P (X) \
654- || flag_pic)
655-
656-#define LEGITIMATE_CONSTANT_P(X) \
657- (!arm_cannot_force_const_mem (X) \
658- && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
659- : THUMB_LEGITIMATE_CONSTANT_P (X)))
660-
661 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
662 #define SUBTARGET_NAME_ENCODING_LENGTHS
663 #endif
664
665=== modified file 'gcc/config/arm/iterators.md'
666--- old/gcc/config/arm/iterators.md 2010-09-21 13:11:03 +0000
667+++ new/gcc/config/arm/iterators.md 2011-05-03 15:14:56 +0000
668@@ -194,24 +194,22 @@
669
670 ;; Mode of pair of elements for each vector mode, to define transfer
671 ;; size for structure lane/dup loads and stores.
672-(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
673- (V4HI "SI") (V8HI "SI")
674+(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
675+ (V4HI "SI") (V8HI "SI")
676 (V2SI "V2SI") (V4SI "V2SI")
677 (V2SF "V2SF") (V4SF "V2SF")
678 (DI "V2DI") (V2DI "V2DI")])
679
680 ;; Similar, for three elements.
681-;; ??? Should we define extra modes so that sizes of all three-element
682-;; accesses can be accurately represented?
683-(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI")
684- (V4HI "V4HI") (V8HI "V4HI")
685- (V2SI "V4SI") (V4SI "V4SI")
686- (V2SF "V4SF") (V4SF "V4SF")
687- (DI "EI") (V2DI "EI")])
688+(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
689+ (V4HI "BLK") (V8HI "BLK")
690+ (V2SI "BLK") (V4SI "BLK")
691+ (V2SF "BLK") (V4SF "BLK")
692+ (DI "EI") (V2DI "EI")])
693
694 ;; Similar, for four elements.
695 (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
696- (V4HI "V4HI") (V8HI "V4HI")
697+ (V4HI "V4HI") (V8HI "V4HI")
698 (V2SI "V4SI") (V4SI "V4SI")
699 (V2SF "V4SF") (V4SF "V4SF")
700 (DI "OI") (V2DI "OI")])
701
702=== modified file 'gcc/config/arm/neon-testgen.ml'
703--- old/gcc/config/arm/neon-testgen.ml 2010-05-24 18:36:31 +0000
704+++ new/gcc/config/arm/neon-testgen.ml 2011-05-03 15:14:56 +0000
705@@ -177,7 +177,7 @@
706 let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
707 "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
708 | (PtrTo elt | CstPtrTo elt) ->
709- "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]"
710+ "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
711 | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
712 | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
713 | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
714
715=== modified file 'gcc/config/arm/neon.md'
716--- old/gcc/config/arm/neon.md 2011-01-03 20:52:22 +0000
717+++ new/gcc/config/arm/neon.md 2011-05-03 15:14:56 +0000
718@@ -4247,16 +4247,16 @@
719
720 (define_insn "neon_vld1<mode>"
721 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
722- (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))]
723+ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
724 UNSPEC_VLD1))]
725 "TARGET_NEON"
726- "vld1.<V_sz_elem>\t%h0, [%1]"
727+ "vld1.<V_sz_elem>\t%h0, %A1"
728 [(set_attr "neon_type" "neon_vld1_1_2_regs")]
729 )
730
731 (define_insn "neon_vld1_lane<mode>"
732 [(set (match_operand:VDX 0 "s_register_operand" "=w")
733- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
734+ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
735 (match_operand:VDX 2 "s_register_operand" "0")
736 (match_operand:SI 3 "immediate_operand" "i")]
737 UNSPEC_VLD1_LANE))]
738@@ -4267,9 +4267,9 @@
739 if (lane < 0 || lane >= max)
740 error ("lane out of range");
741 if (max == 1)
742- return "vld1.<V_sz_elem>\t%P0, [%1]";
743+ return "vld1.<V_sz_elem>\t%P0, %A1";
744 else
745- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
746+ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
747 }
748 [(set (attr "neon_type")
749 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
750@@ -4279,7 +4279,7 @@
751
752 (define_insn "neon_vld1_lane<mode>"
753 [(set (match_operand:VQX 0 "s_register_operand" "=w")
754- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
755+ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
756 (match_operand:VQX 2 "s_register_operand" "0")
757 (match_operand:SI 3 "immediate_operand" "i")]
758 UNSPEC_VLD1_LANE))]
759@@ -4298,9 +4298,9 @@
760 }
761 operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
762 if (max == 2)
763- return "vld1.<V_sz_elem>\t%P0, [%1]";
764+ return "vld1.<V_sz_elem>\t%P0, %A1";
765 else
766- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
767+ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
768 }
769 [(set (attr "neon_type")
770 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
771@@ -4310,14 +4310,14 @@
772
773 (define_insn "neon_vld1_dup<mode>"
774 [(set (match_operand:VDX 0 "s_register_operand" "=w")
775- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
776+ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
777 UNSPEC_VLD1_DUP))]
778 "TARGET_NEON"
779 {
780 if (GET_MODE_NUNITS (<MODE>mode) > 1)
781- return "vld1.<V_sz_elem>\t{%P0[]}, [%1]";
782+ return "vld1.<V_sz_elem>\t{%P0[]}, %A1";
783 else
784- return "vld1.<V_sz_elem>\t%h0, [%1]";
785+ return "vld1.<V_sz_elem>\t%h0, %A1";
786 }
787 [(set (attr "neon_type")
788 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
789@@ -4327,14 +4327,14 @@
790
791 (define_insn "neon_vld1_dup<mode>"
792 [(set (match_operand:VQX 0 "s_register_operand" "=w")
793- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
794+ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
795 UNSPEC_VLD1_DUP))]
796 "TARGET_NEON"
797 {
798 if (GET_MODE_NUNITS (<MODE>mode) > 2)
799- return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
800+ return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
801 else
802- return "vld1.<V_sz_elem>\t%h0, [%1]";
803+ return "vld1.<V_sz_elem>\t%h0, %A1";
804 }
805 [(set (attr "neon_type")
806 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
807@@ -4343,15 +4343,15 @@
808 )
809
810 (define_insn "neon_vst1<mode>"
811- [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r"))
812+ [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
813 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
814 UNSPEC_VST1))]
815 "TARGET_NEON"
816- "vst1.<V_sz_elem>\t%h1, [%0]"
817+ "vst1.<V_sz_elem>\t%h1, %A0"
818 [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
819
820 (define_insn "neon_vst1_lane<mode>"
821- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
822+ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
823 (vec_select:<V_elem>
824 (match_operand:VDX 1 "s_register_operand" "w")
825 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
826@@ -4362,9 +4362,9 @@
827 if (lane < 0 || lane >= max)
828 error ("lane out of range");
829 if (max == 1)
830- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
831+ return "vst1.<V_sz_elem>\t{%P1}, %A0";
832 else
833- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
834+ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
835 }
836 [(set (attr "neon_type")
837 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
838@@ -4372,7 +4372,7 @@
839 (const_string "neon_vst1_vst2_lane")))])
840
841 (define_insn "neon_vst1_lane<mode>"
842- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
843+ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
844 (vec_select:<V_elem>
845 (match_operand:VQX 1 "s_register_operand" "w")
846 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
847@@ -4391,24 +4391,24 @@
848 }
849 operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
850 if (max == 2)
851- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
852+ return "vst1.<V_sz_elem>\t{%P1}, %A0";
853 else
854- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
855+ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
856 }
857 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
858 )
859
860 (define_insn "neon_vld2<mode>"
861 [(set (match_operand:TI 0 "s_register_operand" "=w")
862- (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r"))
863+ (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
864 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
865 UNSPEC_VLD2))]
866 "TARGET_NEON"
867 {
868 if (<V_sz_elem> == 64)
869- return "vld1.64\t%h0, [%1]";
870+ return "vld1.64\t%h0, %A1";
871 else
872- return "vld2.<V_sz_elem>\t%h0, [%1]";
873+ return "vld2.<V_sz_elem>\t%h0, %A1";
874 }
875 [(set (attr "neon_type")
876 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
877@@ -4418,16 +4418,16 @@
878
879 (define_insn "neon_vld2<mode>"
880 [(set (match_operand:OI 0 "s_register_operand" "=w")
881- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
882+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
883 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
884 UNSPEC_VLD2))]
885 "TARGET_NEON"
886- "vld2.<V_sz_elem>\t%h0, [%1]"
887+ "vld2.<V_sz_elem>\t%h0, %A1"
888 [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
889
890 (define_insn "neon_vld2_lane<mode>"
891 [(set (match_operand:TI 0 "s_register_operand" "=w")
892- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
893+ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
894 (match_operand:TI 2 "s_register_operand" "0")
895 (match_operand:SI 3 "immediate_operand" "i")
896 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
897@@ -4444,7 +4444,7 @@
898 ops[1] = gen_rtx_REG (DImode, regno + 2);
899 ops[2] = operands[1];
900 ops[3] = operands[3];
901- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
902+ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
903 return "";
904 }
905 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
906@@ -4452,7 +4452,7 @@
907
908 (define_insn "neon_vld2_lane<mode>"
909 [(set (match_operand:OI 0 "s_register_operand" "=w")
910- (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
911+ (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
912 (match_operand:OI 2 "s_register_operand" "0")
913 (match_operand:SI 3 "immediate_operand" "i")
914 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
915@@ -4474,7 +4474,7 @@
916 ops[1] = gen_rtx_REG (DImode, regno + 4);
917 ops[2] = operands[1];
918 ops[3] = GEN_INT (lane);
919- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
920+ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
921 return "";
922 }
923 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
924@@ -4482,15 +4482,15 @@
925
926 (define_insn "neon_vld2_dup<mode>"
927 [(set (match_operand:TI 0 "s_register_operand" "=w")
928- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
929+ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
930 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
931 UNSPEC_VLD2_DUP))]
932 "TARGET_NEON"
933 {
934 if (GET_MODE_NUNITS (<MODE>mode) > 1)
935- return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
936+ return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
937 else
938- return "vld1.<V_sz_elem>\t%h0, [%1]";
939+ return "vld1.<V_sz_elem>\t%h0, %A1";
940 }
941 [(set (attr "neon_type")
942 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
943@@ -4499,16 +4499,16 @@
944 )
945
946 (define_insn "neon_vst2<mode>"
947- [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r"))
948+ [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
949 (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
950 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
951 UNSPEC_VST2))]
952 "TARGET_NEON"
953 {
954 if (<V_sz_elem> == 64)
955- return "vst1.64\t%h1, [%0]";
956+ return "vst1.64\t%h1, %A0";
957 else
958- return "vst2.<V_sz_elem>\t%h1, [%0]";
959+ return "vst2.<V_sz_elem>\t%h1, %A0";
960 }
961 [(set (attr "neon_type")
962 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
963@@ -4517,17 +4517,17 @@
964 )
965
966 (define_insn "neon_vst2<mode>"
967- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
968+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
969 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
970 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
971 UNSPEC_VST2))]
972 "TARGET_NEON"
973- "vst2.<V_sz_elem>\t%h1, [%0]"
974+ "vst2.<V_sz_elem>\t%h1, %A0"
975 [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
976 )
977
978 (define_insn "neon_vst2_lane<mode>"
979- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
980+ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
981 (unspec:<V_two_elem>
982 [(match_operand:TI 1 "s_register_operand" "w")
983 (match_operand:SI 2 "immediate_operand" "i")
984@@ -4545,14 +4545,14 @@
985 ops[1] = gen_rtx_REG (DImode, regno);
986 ops[2] = gen_rtx_REG (DImode, regno + 2);
987 ops[3] = operands[2];
988- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
989+ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
990 return "";
991 }
992 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
993 )
994
995 (define_insn "neon_vst2_lane<mode>"
996- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
997+ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
998 (unspec:<V_two_elem>
999 [(match_operand:OI 1 "s_register_operand" "w")
1000 (match_operand:SI 2 "immediate_operand" "i")
1001@@ -4575,7 +4575,7 @@
1002 ops[1] = gen_rtx_REG (DImode, regno);
1003 ops[2] = gen_rtx_REG (DImode, regno + 4);
1004 ops[3] = GEN_INT (lane);
1005- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
1006+ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
1007 return "";
1008 }
1009 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
1010@@ -4583,15 +4583,15 @@
1011
1012 (define_insn "neon_vld3<mode>"
1013 [(set (match_operand:EI 0 "s_register_operand" "=w")
1014- (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r"))
1015+ (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
1016 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1017 UNSPEC_VLD3))]
1018 "TARGET_NEON"
1019 {
1020 if (<V_sz_elem> == 64)
1021- return "vld1.64\t%h0, [%1]";
1022+ return "vld1.64\t%h0, %A1";
1023 else
1024- return "vld3.<V_sz_elem>\t%h0, [%1]";
1025+ return "vld3.<V_sz_elem>\t%h0, %A1";
1026 }
1027 [(set (attr "neon_type")
1028 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1029@@ -4600,27 +4600,25 @@
1030 )
1031
1032 (define_expand "neon_vld3<mode>"
1033- [(match_operand:CI 0 "s_register_operand" "=w")
1034- (match_operand:SI 1 "s_register_operand" "+r")
1035+ [(match_operand:CI 0 "s_register_operand")
1036+ (match_operand:CI 1 "neon_struct_operand")
1037 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1038 "TARGET_NEON"
1039 {
1040- emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0],
1041- operands[1], operands[1]));
1042- emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
1043- operands[1], operands[1]));
1044+ rtx mem;
1045+
1046+ mem = adjust_address (operands[1], EImode, 0);
1047+ emit_insn (gen_neon_vld3qa<mode> (operands[0], mem));
1048+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
1049+ emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0]));
1050 DONE;
1051 })
1052
1053 (define_insn "neon_vld3qa<mode>"
1054 [(set (match_operand:CI 0 "s_register_operand" "=w")
1055- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
1056- (match_operand:CI 1 "s_register_operand" "0")
1057+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
1058 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1059- UNSPEC_VLD3A))
1060- (set (match_operand:SI 2 "s_register_operand" "=r")
1061- (plus:SI (match_dup 3)
1062- (const_int 24)))]
1063+ UNSPEC_VLD3A))]
1064 "TARGET_NEON"
1065 {
1066 int regno = REGNO (operands[0]);
1067@@ -4628,8 +4626,8 @@
1068 ops[0] = gen_rtx_REG (DImode, regno);
1069 ops[1] = gen_rtx_REG (DImode, regno + 4);
1070 ops[2] = gen_rtx_REG (DImode, regno + 8);
1071- ops[3] = operands[2];
1072- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
1073+ ops[3] = operands[1];
1074+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
1075 return "";
1076 }
1077 [(set_attr "neon_type" "neon_vld3_vld4")]
1078@@ -4637,13 +4635,10 @@
1079
1080 (define_insn "neon_vld3qb<mode>"
1081 [(set (match_operand:CI 0 "s_register_operand" "=w")
1082- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
1083- (match_operand:CI 1 "s_register_operand" "0")
1084+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
1085+ (match_operand:CI 2 "s_register_operand" "0")
1086 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1087- UNSPEC_VLD3B))
1088- (set (match_operand:SI 2 "s_register_operand" "=r")
1089- (plus:SI (match_dup 3)
1090- (const_int 24)))]
1091+ UNSPEC_VLD3B))]
1092 "TARGET_NEON"
1093 {
1094 int regno = REGNO (operands[0]);
1095@@ -4651,8 +4646,8 @@
1096 ops[0] = gen_rtx_REG (DImode, regno + 2);
1097 ops[1] = gen_rtx_REG (DImode, regno + 6);
1098 ops[2] = gen_rtx_REG (DImode, regno + 10);
1099- ops[3] = operands[2];
1100- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
1101+ ops[3] = operands[1];
1102+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
1103 return "";
1104 }
1105 [(set_attr "neon_type" "neon_vld3_vld4")]
1106@@ -4660,7 +4655,7 @@
1107
1108 (define_insn "neon_vld3_lane<mode>"
1109 [(set (match_operand:EI 0 "s_register_operand" "=w")
1110- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
1111+ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
1112 (match_operand:EI 2 "s_register_operand" "0")
1113 (match_operand:SI 3 "immediate_operand" "i")
1114 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1115@@ -4678,7 +4673,7 @@
1116 ops[2] = gen_rtx_REG (DImode, regno + 4);
1117 ops[3] = operands[1];
1118 ops[4] = operands[3];
1119- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
1120+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
1121 ops);
1122 return "";
1123 }
1124@@ -4687,7 +4682,7 @@
1125
1126 (define_insn "neon_vld3_lane<mode>"
1127 [(set (match_operand:CI 0 "s_register_operand" "=w")
1128- (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
1129+ (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
1130 (match_operand:CI 2 "s_register_operand" "0")
1131 (match_operand:SI 3 "immediate_operand" "i")
1132 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1133@@ -4710,7 +4705,7 @@
1134 ops[2] = gen_rtx_REG (DImode, regno + 8);
1135 ops[3] = operands[1];
1136 ops[4] = GEN_INT (lane);
1137- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
1138+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
1139 ops);
1140 return "";
1141 }
1142@@ -4719,7 +4714,7 @@
1143
1144 (define_insn "neon_vld3_dup<mode>"
1145 [(set (match_operand:EI 0 "s_register_operand" "=w")
1146- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
1147+ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
1148 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1149 UNSPEC_VLD3_DUP))]
1150 "TARGET_NEON"
1151@@ -4732,11 +4727,11 @@
1152 ops[1] = gen_rtx_REG (DImode, regno + 2);
1153 ops[2] = gen_rtx_REG (DImode, regno + 4);
1154 ops[3] = operands[1];
1155- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops);
1156+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
1157 return "";
1158 }
1159 else
1160- return "vld1.<V_sz_elem>\t%h0, [%1]";
1161+ return "vld1.<V_sz_elem>\t%h0, %A1";
1162 }
1163 [(set (attr "neon_type")
1164 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
1165@@ -4744,16 +4739,16 @@
1166 (const_string "neon_vld1_1_2_regs")))])
1167
1168 (define_insn "neon_vst3<mode>"
1169- [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r"))
1170+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
1171 (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
1172 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1173 UNSPEC_VST3))]
1174 "TARGET_NEON"
1175 {
1176 if (<V_sz_elem> == 64)
1177- return "vst1.64\t%h1, [%0]";
1178+ return "vst1.64\t%h1, %A0";
1179 else
1180- return "vst3.<V_sz_elem>\t%h1, [%0]";
1181+ return "vst3.<V_sz_elem>\t%h1, %A0";
1182 }
1183 [(set (attr "neon_type")
1184 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1185@@ -4761,62 +4756,60 @@
1186 (const_string "neon_vst2_4_regs_vst3_vst4")))])
1187
1188 (define_expand "neon_vst3<mode>"
1189- [(match_operand:SI 0 "s_register_operand" "+r")
1190- (match_operand:CI 1 "s_register_operand" "w")
1191+ [(match_operand:CI 0 "neon_struct_operand")
1192+ (match_operand:CI 1 "s_register_operand")
1193 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1194 "TARGET_NEON"
1195 {
1196- emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1]));
1197- emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
1198+ rtx mem;
1199+
1200+ mem = adjust_address (operands[0], EImode, 0);
1201+ emit_insn (gen_neon_vst3qa<mode> (mem, operands[1]));
1202+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
1203+ emit_insn (gen_neon_vst3qb<mode> (mem, operands[1]));
1204 DONE;
1205 })
1206
1207 (define_insn "neon_vst3qa<mode>"
1208- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
1209- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
1210+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
1211+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
1212 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1213- UNSPEC_VST3A))
1214- (set (match_operand:SI 0 "s_register_operand" "=r")
1215- (plus:SI (match_dup 1)
1216- (const_int 24)))]
1217+ UNSPEC_VST3A))]
1218 "TARGET_NEON"
1219 {
1220- int regno = REGNO (operands[2]);
1221+ int regno = REGNO (operands[1]);
1222 rtx ops[4];
1223 ops[0] = operands[0];
1224 ops[1] = gen_rtx_REG (DImode, regno);
1225 ops[2] = gen_rtx_REG (DImode, regno + 4);
1226 ops[3] = gen_rtx_REG (DImode, regno + 8);
1227- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
1228+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
1229 return "";
1230 }
1231 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1232 )
1233
1234 (define_insn "neon_vst3qb<mode>"
1235- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
1236- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
1237+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
1238+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
1239 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1240- UNSPEC_VST3B))
1241- (set (match_operand:SI 0 "s_register_operand" "=r")
1242- (plus:SI (match_dup 1)
1243- (const_int 24)))]
1244+ UNSPEC_VST3B))]
1245 "TARGET_NEON"
1246 {
1247- int regno = REGNO (operands[2]);
1248+ int regno = REGNO (operands[1]);
1249 rtx ops[4];
1250 ops[0] = operands[0];
1251 ops[1] = gen_rtx_REG (DImode, regno + 2);
1252 ops[2] = gen_rtx_REG (DImode, regno + 6);
1253 ops[3] = gen_rtx_REG (DImode, regno + 10);
1254- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
1255+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
1256 return "";
1257 }
1258 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1259 )
1260
1261 (define_insn "neon_vst3_lane<mode>"
1262- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
1263+ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
1264 (unspec:<V_three_elem>
1265 [(match_operand:EI 1 "s_register_operand" "w")
1266 (match_operand:SI 2 "immediate_operand" "i")
1267@@ -4835,7 +4828,7 @@
1268 ops[2] = gen_rtx_REG (DImode, regno + 2);
1269 ops[3] = gen_rtx_REG (DImode, regno + 4);
1270 ops[4] = operands[2];
1271- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
1272+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
1273 ops);
1274 return "";
1275 }
1276@@ -4843,7 +4836,7 @@
1277 )
1278
1279 (define_insn "neon_vst3_lane<mode>"
1280- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
1281+ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
1282 (unspec:<V_three_elem>
1283 [(match_operand:CI 1 "s_register_operand" "w")
1284 (match_operand:SI 2 "immediate_operand" "i")
1285@@ -4867,7 +4860,7 @@
1286 ops[2] = gen_rtx_REG (DImode, regno + 4);
1287 ops[3] = gen_rtx_REG (DImode, regno + 8);
1288 ops[4] = GEN_INT (lane);
1289- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
1290+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
1291 ops);
1292 return "";
1293 }
1294@@ -4875,15 +4868,15 @@
1295
1296 (define_insn "neon_vld4<mode>"
1297 [(set (match_operand:OI 0 "s_register_operand" "=w")
1298- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
1299+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
1300 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1301 UNSPEC_VLD4))]
1302 "TARGET_NEON"
1303 {
1304 if (<V_sz_elem> == 64)
1305- return "vld1.64\t%h0, [%1]";
1306+ return "vld1.64\t%h0, %A1";
1307 else
1308- return "vld4.<V_sz_elem>\t%h0, [%1]";
1309+ return "vld4.<V_sz_elem>\t%h0, %A1";
1310 }
1311 [(set (attr "neon_type")
1312 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1313@@ -4892,27 +4885,25 @@
1314 )
1315
1316 (define_expand "neon_vld4<mode>"
1317- [(match_operand:XI 0 "s_register_operand" "=w")
1318- (match_operand:SI 1 "s_register_operand" "+r")
1319+ [(match_operand:XI 0 "s_register_operand")
1320+ (match_operand:XI 1 "neon_struct_operand")
1321 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1322 "TARGET_NEON"
1323 {
1324- emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0],
1325- operands[1], operands[1]));
1326- emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
1327- operands[1], operands[1]));
1328+ rtx mem;
1329+
1330+ mem = adjust_address (operands[1], OImode, 0);
1331+ emit_insn (gen_neon_vld4qa<mode> (operands[0], mem));
1332+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
1333+ emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0]));
1334 DONE;
1335 })
1336
1337 (define_insn "neon_vld4qa<mode>"
1338 [(set (match_operand:XI 0 "s_register_operand" "=w")
1339- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
1340- (match_operand:XI 1 "s_register_operand" "0")
1341+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
1342 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1343- UNSPEC_VLD4A))
1344- (set (match_operand:SI 2 "s_register_operand" "=r")
1345- (plus:SI (match_dup 3)
1346- (const_int 32)))]
1347+ UNSPEC_VLD4A))]
1348 "TARGET_NEON"
1349 {
1350 int regno = REGNO (operands[0]);
1351@@ -4921,8 +4912,8 @@
1352 ops[1] = gen_rtx_REG (DImode, regno + 4);
1353 ops[2] = gen_rtx_REG (DImode, regno + 8);
1354 ops[3] = gen_rtx_REG (DImode, regno + 12);
1355- ops[4] = operands[2];
1356- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
1357+ ops[4] = operands[1];
1358+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
1359 return "";
1360 }
1361 [(set_attr "neon_type" "neon_vld3_vld4")]
1362@@ -4930,13 +4921,10 @@
1363
1364 (define_insn "neon_vld4qb<mode>"
1365 [(set (match_operand:XI 0 "s_register_operand" "=w")
1366- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
1367- (match_operand:XI 1 "s_register_operand" "0")
1368+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
1369+ (match_operand:XI 2 "s_register_operand" "0")
1370 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1371- UNSPEC_VLD4B))
1372- (set (match_operand:SI 2 "s_register_operand" "=r")
1373- (plus:SI (match_dup 3)
1374- (const_int 32)))]
1375+ UNSPEC_VLD4B))]
1376 "TARGET_NEON"
1377 {
1378 int regno = REGNO (operands[0]);
1379@@ -4945,8 +4933,8 @@
1380 ops[1] = gen_rtx_REG (DImode, regno + 6);
1381 ops[2] = gen_rtx_REG (DImode, regno + 10);
1382 ops[3] = gen_rtx_REG (DImode, regno + 14);
1383- ops[4] = operands[2];
1384- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
1385+ ops[4] = operands[1];
1386+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
1387 return "";
1388 }
1389 [(set_attr "neon_type" "neon_vld3_vld4")]
1390@@ -4954,7 +4942,7 @@
1391
1392 (define_insn "neon_vld4_lane<mode>"
1393 [(set (match_operand:OI 0 "s_register_operand" "=w")
1394- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
1395+ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
1396 (match_operand:OI 2 "s_register_operand" "0")
1397 (match_operand:SI 3 "immediate_operand" "i")
1398 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1399@@ -4973,7 +4961,7 @@
1400 ops[3] = gen_rtx_REG (DImode, regno + 6);
1401 ops[4] = operands[1];
1402 ops[5] = operands[3];
1403- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
1404+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
1405 ops);
1406 return "";
1407 }
1408@@ -4982,7 +4970,7 @@
1409
1410 (define_insn "neon_vld4_lane<mode>"
1411 [(set (match_operand:XI 0 "s_register_operand" "=w")
1412- (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
1413+ (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
1414 (match_operand:XI 2 "s_register_operand" "0")
1415 (match_operand:SI 3 "immediate_operand" "i")
1416 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1417@@ -5006,7 +4994,7 @@
1418 ops[3] = gen_rtx_REG (DImode, regno + 12);
1419 ops[4] = operands[1];
1420 ops[5] = GEN_INT (lane);
1421- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
1422+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
1423 ops);
1424 return "";
1425 }
1426@@ -5015,7 +5003,7 @@
1427
1428 (define_insn "neon_vld4_dup<mode>"
1429 [(set (match_operand:OI 0 "s_register_operand" "=w")
1430- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
1431+ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
1432 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1433 UNSPEC_VLD4_DUP))]
1434 "TARGET_NEON"
1435@@ -5029,12 +5017,12 @@
1436 ops[2] = gen_rtx_REG (DImode, regno + 4);
1437 ops[3] = gen_rtx_REG (DImode, regno + 6);
1438 ops[4] = operands[1];
1439- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]",
1440+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4",
1441 ops);
1442 return "";
1443 }
1444 else
1445- return "vld1.<V_sz_elem>\t%h0, [%1]";
1446+ return "vld1.<V_sz_elem>\t%h0, %A1";
1447 }
1448 [(set (attr "neon_type")
1449 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
1450@@ -5043,16 +5031,16 @@
1451 )
1452
1453 (define_insn "neon_vst4<mode>"
1454- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
1455+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
1456 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
1457 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1458 UNSPEC_VST4))]
1459 "TARGET_NEON"
1460 {
1461 if (<V_sz_elem> == 64)
1462- return "vst1.64\t%h1, [%0]";
1463+ return "vst1.64\t%h1, %A0";
1464 else
1465- return "vst4.<V_sz_elem>\t%h1, [%0]";
1466+ return "vst4.<V_sz_elem>\t%h1, %A0";
1467 }
1468 [(set (attr "neon_type")
1469 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1470@@ -5061,64 +5049,62 @@
1471 )
1472
1473 (define_expand "neon_vst4<mode>"
1474- [(match_operand:SI 0 "s_register_operand" "+r")
1475- (match_operand:XI 1 "s_register_operand" "w")
1476+ [(match_operand:XI 0 "neon_struct_operand")
1477+ (match_operand:XI 1 "s_register_operand")
1478 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1479 "TARGET_NEON"
1480 {
1481- emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1]));
1482- emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
1483+ rtx mem;
1484+
1485+ mem = adjust_address (operands[0], OImode, 0);
1486+ emit_insn (gen_neon_vst4qa<mode> (mem, operands[1]));
1487+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
1488+ emit_insn (gen_neon_vst4qb<mode> (mem, operands[1]));
1489 DONE;
1490 })
1491
1492 (define_insn "neon_vst4qa<mode>"
1493- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
1494- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
1495+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
1496+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
1497 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1498- UNSPEC_VST4A))
1499- (set (match_operand:SI 0 "s_register_operand" "=r")
1500- (plus:SI (match_dup 1)
1501- (const_int 32)))]
1502+ UNSPEC_VST4A))]
1503 "TARGET_NEON"
1504 {
1505- int regno = REGNO (operands[2]);
1506+ int regno = REGNO (operands[1]);
1507 rtx ops[5];
1508 ops[0] = operands[0];
1509 ops[1] = gen_rtx_REG (DImode, regno);
1510 ops[2] = gen_rtx_REG (DImode, regno + 4);
1511 ops[3] = gen_rtx_REG (DImode, regno + 8);
1512 ops[4] = gen_rtx_REG (DImode, regno + 12);
1513- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
1514+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
1515 return "";
1516 }
1517 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1518 )
1519
1520 (define_insn "neon_vst4qb<mode>"
1521- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
1522- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
1523+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
1524+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
1525 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1526- UNSPEC_VST4B))
1527- (set (match_operand:SI 0 "s_register_operand" "=r")
1528- (plus:SI (match_dup 1)
1529- (const_int 32)))]
1530+ UNSPEC_VST4B))]
1531 "TARGET_NEON"
1532 {
1533- int regno = REGNO (operands[2]);
1534+ int regno = REGNO (operands[1]);
1535 rtx ops[5];
1536 ops[0] = operands[0];
1537 ops[1] = gen_rtx_REG (DImode, regno + 2);
1538 ops[2] = gen_rtx_REG (DImode, regno + 6);
1539 ops[3] = gen_rtx_REG (DImode, regno + 10);
1540 ops[4] = gen_rtx_REG (DImode, regno + 14);
1541- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
1542+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
1543 return "";
1544 }
1545 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1546 )
1547
1548 (define_insn "neon_vst4_lane<mode>"
1549- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
1550+ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
1551 (unspec:<V_four_elem>
1552 [(match_operand:OI 1 "s_register_operand" "w")
1553 (match_operand:SI 2 "immediate_operand" "i")
1554@@ -5138,7 +5124,7 @@
1555 ops[3] = gen_rtx_REG (DImode, regno + 4);
1556 ops[4] = gen_rtx_REG (DImode, regno + 6);
1557 ops[5] = operands[2];
1558- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
1559+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
1560 ops);
1561 return "";
1562 }
1563@@ -5146,7 +5132,7 @@
1564 )
1565
1566 (define_insn "neon_vst4_lane<mode>"
1567- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
1568+ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
1569 (unspec:<V_four_elem>
1570 [(match_operand:XI 1 "s_register_operand" "w")
1571 (match_operand:SI 2 "immediate_operand" "i")
1572@@ -5171,7 +5157,7 @@
1573 ops[3] = gen_rtx_REG (DImode, regno + 8);
1574 ops[4] = gen_rtx_REG (DImode, regno + 12);
1575 ops[5] = GEN_INT (lane);
1576- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
1577+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
1578 ops);
1579 return "";
1580 }
1581
1582=== modified file 'gcc/config/arm/predicates.md'
1583--- old/gcc/config/arm/predicates.md 2011-04-07 10:52:12 +0000
1584+++ new/gcc/config/arm/predicates.md 2011-05-03 15:14:56 +0000
1585@@ -683,3 +683,7 @@
1586 }
1587 return true;
1588 })
1589+
1590+(define_special_predicate "neon_struct_operand"
1591+ (and (match_code "mem")
1592+ (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
1593
1594=== modified file 'gcc/doc/tm.texi'
1595--- old/gcc/doc/tm.texi 2011-01-22 19:35:10 +0000
1596+++ new/gcc/doc/tm.texi 2011-05-03 15:17:25 +0000
1597@@ -2533,7 +2533,7 @@
1598 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1599 @var{x} is a floating-point constant. If the constant can't be loaded
1600 into any kind of register, code generation will be better if
1601-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1602+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1603 of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1604
1605 If an insn has pseudos in it after register allocation, reload will go
1606@@ -2570,8 +2570,8 @@
1607 register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1608 @var{x} is a floating-point constant. If the constant can't be loaded
1609 into any kind of register, code generation will be better if
1610-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1611-of using @code{PREFERRED_RELOAD_CLASS}.
1612+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1613+of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1614
1615 If an insn has pseudos in it after register allocation, reload will go
1616 through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
1617@@ -4319,6 +4319,34 @@
1618 must have move patterns for this mode.
1619 @end deftypefn
1620
1621+@deftypefn {Target Hook} bool TARGET_ARRAY_MODE_SUPPORTED_P (enum machine_mode @var{mode}, unsigned HOST_WIDE_INT @var{nelems})
1622+Return true if GCC should try to use a scalar mode to store an array
1623+of @var{nelems} elements, given that each element has mode @var{mode}.
1624+Returning true here overrides the usual @code{MAX_FIXED_MODE} limit
1625+and allows GCC to use any defined integer mode.
1626+
1627+One use of this hook is to support vector load and store operations
1628+that operate on several homogeneous vectors. For example, ARM NEON
1629+has operations like:
1630+
1631+@smallexample
1632+int8x8x3_t vld3_s8 (const int8_t *)
1633+@end smallexample
1634+
1635+where the return type is defined as:
1636+
1637+@smallexample
1638+typedef struct int8x8x3_t
1639+@{
1640+ int8x8_t val[3];
1641+@} int8x8x3_t;
1642+@end smallexample
1643+
1644+If this hook allows @code{val} to have a scalar mode, then
1645+@code{int8x8x3_t} can have the same mode. GCC can then store
1646+@code{int8x8x3_t}s in registers rather than forcing them onto the stack.
1647+@end deftypefn
1648+
1649 @deftypefn {Target Hook} bool TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P (enum machine_mode @var{mode})
1650 Define this to return nonzero for machine modes for which the port has
1651 small register classes. If this target hook returns nonzero for a given
1652@@ -5577,13 +5605,13 @@
1653 @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
1654 @end defmac
1655
1656-@defmac LEGITIMATE_CONSTANT_P (@var{x})
1657-A C expression that is nonzero if @var{x} is a legitimate constant for
1658-an immediate operand on the target machine. You can assume that
1659-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact,
1660-@samp{1} is a suitable definition for this macro on machines where
1661-anything @code{CONSTANT_P} is valid.
1662-@end defmac
1663+@deftypefn {Target Hook} bool TARGET_LEGITIMATE_CONSTANT_P (enum machine_mode @var{mode}, rtx @var{x})
1664+This hook returns true if @var{x} is a legitimate constant for a
1665+@var{mode}-mode immediate operand on the target machine. You can assume that
1666+@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
1667+
1668+The default definition returns true.
1669+@end deftypefn
1670
1671 @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x})
1672 This hook is used to undo the possibly obfuscating effects of the
1673
1674=== modified file 'gcc/doc/tm.texi.in'
1675--- old/gcc/doc/tm.texi.in 2011-01-22 19:35:10 +0000
1676+++ new/gcc/doc/tm.texi.in 2011-05-03 15:17:25 +0000
1677@@ -2521,7 +2521,7 @@
1678 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1679 @var{x} is a floating-point constant. If the constant can't be loaded
1680 into any kind of register, code generation will be better if
1681-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1682+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1683 of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1684
1685 If an insn has pseudos in it after register allocation, reload will go
1686@@ -2558,8 +2558,8 @@
1687 register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1688 @var{x} is a floating-point constant. If the constant can't be loaded
1689 into any kind of register, code generation will be better if
1690-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1691-of using @code{PREFERRED_RELOAD_CLASS}.
1692+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1693+of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1694
1695 If an insn has pseudos in it after register allocation, reload will go
1696 through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
1697@@ -4305,6 +4305,8 @@
1698 must have move patterns for this mode.
1699 @end deftypefn
1700
1701+@hook TARGET_ARRAY_MODE_SUPPORTED_P
1702+
1703 @hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
1704 Define this to return nonzero for machine modes for which the port has
1705 small register classes. If this target hook returns nonzero for a given
1706@@ -5555,13 +5557,13 @@
1707 @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
1708 @end defmac
1709
1710-@defmac LEGITIMATE_CONSTANT_P (@var{x})
1711-A C expression that is nonzero if @var{x} is a legitimate constant for
1712-an immediate operand on the target machine. You can assume that
1713-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact,
1714-@samp{1} is a suitable definition for this macro on machines where
1715-anything @code{CONSTANT_P} is valid.
1716-@end defmac
1717+@hook TARGET_LEGITIMATE_CONSTANT_P
1718+This hook returns true if @var{x} is a legitimate constant for a
1719+@var{mode}-mode immediate operand on the target machine. You can assume that
1720+@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
1721+
1722+The default definition returns true.
1723+@end deftypefn
1724
1725 @hook TARGET_DELEGITIMIZE_ADDRESS
1726 This hook is used to undo the possibly obfuscating effects of the
1727
1728=== modified file 'gcc/expr.c'
1729--- old/gcc/expr.c 2011-04-05 16:18:11 +0000
1730+++ new/gcc/expr.c 2011-05-03 15:17:25 +0000
1731@@ -1497,7 +1497,7 @@
1732 if (nregs == 0)
1733 return;
1734
1735- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
1736+ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
1737 x = validize_mem (force_const_mem (mode, x));
1738
1739 /* See if the machine can do this with a load multiple insn. */
1740@@ -2308,7 +2308,7 @@
1741 offset -= size;
1742
1743 cst = (*constfun) (constfundata, offset, mode);
1744- if (!LEGITIMATE_CONSTANT_P (cst))
1745+ if (!targetm.legitimate_constant_p (mode, cst))
1746 return 0;
1747
1748 if (!reverse)
1749@@ -3363,7 +3363,7 @@
1750
1751 y_cst = y;
1752
1753- if (!LEGITIMATE_CONSTANT_P (y))
1754+ if (!targetm.legitimate_constant_p (mode, y))
1755 {
1756 y = force_const_mem (mode, y);
1757
1758@@ -3419,7 +3419,7 @@
1759
1760 REAL_VALUE_FROM_CONST_DOUBLE (r, y);
1761
1762- if (LEGITIMATE_CONSTANT_P (y))
1763+ if (targetm.legitimate_constant_p (dstmode, y))
1764 oldcost = rtx_cost (y, SET, speed);
1765 else
1766 oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed);
1767@@ -3442,7 +3442,7 @@
1768
1769 trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode);
1770
1771- if (LEGITIMATE_CONSTANT_P (trunc_y))
1772+ if (targetm.legitimate_constant_p (srcmode, trunc_y))
1773 {
1774 /* Skip if the target needs extra instructions to perform
1775 the extension. */
1776@@ -3855,7 +3855,7 @@
1777 by setting SKIP to 0. */
1778 skip = (reg_parm_stack_space == 0) ? 0 : not_stack;
1779
1780- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
1781+ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
1782 x = validize_mem (force_const_mem (mode, x));
1783
1784 /* If X is a hard register in a non-integer mode, copy it into a pseudo;
1785@@ -9066,7 +9066,7 @@
1786 constant and we don't need a memory reference. */
1787 if (CONSTANT_P (op0)
1788 && mode2 != BLKmode
1789- && LEGITIMATE_CONSTANT_P (op0)
1790+ && targetm.legitimate_constant_p (mode2, op0)
1791 && !must_force_mem)
1792 op0 = force_reg (mode2, op0);
1793
1794
1795=== modified file 'gcc/hooks.c'
1796--- old/gcc/hooks.c 2010-11-25 13:16:03 +0000
1797+++ new/gcc/hooks.c 2011-05-03 15:16:01 +0000
1798@@ -101,6 +101,15 @@
1799 return true;
1800 }
1801
1802+/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT)
1803+ and returns false. */
1804+bool
1805+hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED,
1806+ unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED)
1807+{
1808+ return false;
1809+}
1810+
1811 /* Generic hook that takes (FILE *, const char *) and does nothing. */
1812 void
1813 hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED)
1814
1815=== modified file 'gcc/hooks.h'
1816--- old/gcc/hooks.h 2010-11-25 13:16:03 +0000
1817+++ new/gcc/hooks.h 2011-05-03 15:16:01 +0000
1818@@ -34,6 +34,8 @@
1819 extern bool hook_bool_mode_true (enum machine_mode);
1820 extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx);
1821 extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx);
1822+extern bool hook_bool_mode_uhwi_false (enum machine_mode,
1823+ unsigned HOST_WIDE_INT);
1824 extern bool hook_bool_tree_false (tree);
1825 extern bool hook_bool_const_tree_false (const_tree);
1826 extern bool hook_bool_tree_true (tree);
1827
1828=== modified file 'gcc/recog.c'
1829--- old/gcc/recog.c 2010-11-30 16:36:19 +0000
1830+++ new/gcc/recog.c 2011-05-03 15:17:25 +0000
1831@@ -930,7 +930,9 @@
1832 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1833 || mode == VOIDmode)
1834 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1835- && LEGITIMATE_CONSTANT_P (op));
1836+ && targetm.legitimate_constant_p (mode == VOIDmode
1837+ ? GET_MODE (op)
1838+ : mode, op));
1839
1840 /* Except for certain constants with VOIDmode, already checked for,
1841 OP's mode must match MODE if MODE specifies a mode. */
1842@@ -1107,7 +1109,9 @@
1843 && (GET_MODE (op) == mode || mode == VOIDmode
1844 || GET_MODE (op) == VOIDmode)
1845 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1846- && LEGITIMATE_CONSTANT_P (op));
1847+ && targetm.legitimate_constant_p (mode == VOIDmode
1848+ ? GET_MODE (op)
1849+ : mode, op));
1850 }
1851
1852 /* Returns 1 if OP is an operand that is a CONST_INT. */
1853
1854=== modified file 'gcc/reload.c'
1855--- old/gcc/reload.c 2011-02-02 16:52:21 +0000
1856+++ new/gcc/reload.c 2011-05-03 15:17:25 +0000
1857@@ -4721,7 +4721,8 @@
1858 simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
1859 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
1860 gcc_assert (tem);
1861- if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem))
1862+ if (CONSTANT_P (tem)
1863+ && !targetm.legitimate_constant_p (GET_MODE (x), tem))
1864 {
1865 tem = force_const_mem (GET_MODE (x), tem);
1866 i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
1867@@ -6049,7 +6050,7 @@
1868 enum reload_type type, int ind_levels)
1869 {
1870 if (CONSTANT_P (x)
1871- && (! LEGITIMATE_CONSTANT_P (x)
1872+ && (!targetm.legitimate_constant_p (mode, x)
1873 || targetm.preferred_reload_class (x, rclass) == NO_REGS))
1874 {
1875 x = force_const_mem (mode, x);
1876@@ -6059,7 +6060,7 @@
1877
1878 else if (GET_CODE (x) == PLUS
1879 && CONSTANT_P (XEXP (x, 1))
1880- && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
1881+ && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1))
1882 || targetm.preferred_reload_class (XEXP (x, 1), rclass)
1883 == NO_REGS))
1884 {
1885
1886=== modified file 'gcc/reload1.c'
1887--- old/gcc/reload1.c 2011-01-23 21:11:24 +0000
1888+++ new/gcc/reload1.c 2011-05-03 15:17:25 +0000
1889@@ -4155,6 +4155,9 @@
1890 }
1891 else if (function_invariant_p (x))
1892 {
1893+ enum machine_mode mode;
1894+
1895+ mode = GET_MODE (SET_DEST (set));
1896 if (GET_CODE (x) == PLUS)
1897 {
1898 /* This is PLUS of frame pointer and a constant,
1899@@ -4167,12 +4170,11 @@
1900 reg_equiv_invariant[i] = x;
1901 num_eliminable_invariants++;
1902 }
1903- else if (LEGITIMATE_CONSTANT_P (x))
1904+ else if (targetm.legitimate_constant_p (mode, x))
1905 reg_equiv_constant[i] = x;
1906 else
1907 {
1908- reg_equiv_memory_loc[i]
1909- = force_const_mem (GET_MODE (SET_DEST (set)), x);
1910+ reg_equiv_memory_loc[i] = force_const_mem (mode, x);
1911 if (! reg_equiv_memory_loc[i])
1912 reg_equiv_init[i] = NULL_RTX;
1913 }
1914
1915=== modified file 'gcc/stor-layout.c'
1916--- old/gcc/stor-layout.c 2011-03-10 22:37:22 +0000
1917+++ new/gcc/stor-layout.c 2011-05-03 15:16:01 +0000
1918@@ -546,6 +546,34 @@
1919 return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT));
1920 }
1921
1922+/* Return the natural mode of an array, given that it is SIZE bytes in
1923+ total and has elements of type ELEM_TYPE. */
1924+
1925+static enum machine_mode
1926+mode_for_array (tree elem_type, tree size)
1927+{
1928+ tree elem_size;
1929+ unsigned HOST_WIDE_INT int_size, int_elem_size;
1930+ bool limit_p;
1931+
1932+ /* One-element arrays get the component type's mode. */
1933+ elem_size = TYPE_SIZE (elem_type);
1934+ if (simple_cst_equal (size, elem_size))
1935+ return TYPE_MODE (elem_type);
1936+
1937+ limit_p = true;
1938+ if (host_integerp (size, 1) && host_integerp (elem_size, 1))
1939+ {
1940+ int_size = tree_low_cst (size, 1);
1941+ int_elem_size = tree_low_cst (elem_size, 1);
1942+ if (int_elem_size > 0
1943+ && int_size % int_elem_size == 0
1944+ && targetm.array_mode_supported_p (TYPE_MODE (elem_type),
1945+ int_size / int_elem_size))
1946+ limit_p = false;
1947+ }
1948+ return mode_for_size_tree (size, MODE_INT, limit_p);
1949+}
1950
1951 /* Subroutine of layout_decl: Force alignment required for the data type.
1952 But if the decl itself wants greater alignment, don't override that. */
1953@@ -2039,14 +2067,8 @@
1954 && (TYPE_MODE (TREE_TYPE (type)) != BLKmode
1955 || TYPE_NO_FORCE_BLK (TREE_TYPE (type))))
1956 {
1957- /* One-element arrays get the component type's mode. */
1958- if (simple_cst_equal (TYPE_SIZE (type),
1959- TYPE_SIZE (TREE_TYPE (type))))
1960- SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type)));
1961- else
1962- SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type),
1963- MODE_INT, 1));
1964-
1965+ SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type),
1966+ TYPE_SIZE (type)));
1967 if (TYPE_MODE (type) != BLKmode
1968 && STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT
1969 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type)))
1970
1971=== modified file 'gcc/target.def'
1972--- old/gcc/target.def 2011-01-22 19:35:10 +0000
1973+++ new/gcc/target.def 2011-05-03 15:17:25 +0000
1974@@ -1344,6 +1344,13 @@
1975 unsigned, (unsigned nunroll, struct loop *loop),
1976 NULL)
1977
1978+/* True if X is a legitimate MODE-mode immediate operand. */
1979+DEFHOOK
1980+(legitimate_constant_p,
1981+ "",
1982+ bool, (enum machine_mode mode, rtx x),
1983+ default_legitimate_constant_p)
1984+
1985 /* True if the constant X cannot be placed in the constant pool. */
1986 DEFHOOK
1987 (cannot_force_const_mem,
1988@@ -1611,6 +1618,38 @@
1989 bool, (enum machine_mode mode),
1990 hook_bool_mode_false)
1991
1992+/* True if we should try to use a scalar mode to represent an array,
1993+ overriding the usual MAX_FIXED_MODE limit. */
1994+DEFHOOK
1995+(array_mode_supported_p,
1996+ "Return true if GCC should try to use a scalar mode to store an array\n\
1997+of @var{nelems} elements, given that each element has mode @var{mode}.\n\
1998+Returning true here overrides the usual @code{MAX_FIXED_MODE} limit\n\
1999+and allows GCC to use any defined integer mode.\n\
2000+\n\
2001+One use of this hook is to support vector load and store operations\n\
2002+that operate on several homogeneous vectors. For example, ARM NEON\n\
2003+has operations like:\n\
2004+\n\
2005+@smallexample\n\
2006+int8x8x3_t vld3_s8 (const int8_t *)\n\
2007+@end smallexample\n\
2008+\n\
2009+where the return type is defined as:\n\
2010+\n\
2011+@smallexample\n\
2012+typedef struct int8x8x3_t\n\
2013+@{\n\
2014+ int8x8_t val[3];\n\
2015+@} int8x8x3_t;\n\
2016+@end smallexample\n\
2017+\n\
2018+If this hook allows @code{val} to have a scalar mode, then\n\
2019+@code{int8x8x3_t} can have the same mode. GCC can then store\n\
2020+@code{int8x8x3_t}s in registers rather than forcing them onto the stack.",
2021+ bool, (enum machine_mode mode, unsigned HOST_WIDE_INT nelems),
2022+ hook_bool_mode_uhwi_false)
2023+
2024 /* Compute cost of moving data from a register of class FROM to one of
2025 TO, using MODE. */
2026 DEFHOOK
2027
2028=== modified file 'gcc/targhooks.c'
2029--- old/gcc/targhooks.c 2011-01-14 15:02:20 +0000
2030+++ new/gcc/targhooks.c 2011-05-03 15:17:25 +0000
2031@@ -1519,4 +1519,15 @@
2032 { OPT_LEVELS_NONE, 0, NULL, 0 }
2033 };
2034
2035+bool
2036+default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2037+ rtx x ATTRIBUTE_UNUSED)
2038+{
2039+#ifdef LEGITIMATE_CONSTANT_P
2040+ return LEGITIMATE_CONSTANT_P (x);
2041+#else
2042+ return true;
2043+#endif
2044+}
2045+
2046 #include "gt-targhooks.h"
2047
2048=== modified file 'gcc/targhooks.h'
2049--- old/gcc/targhooks.h 2011-01-14 15:02:20 +0000
2050+++ new/gcc/targhooks.h 2011-05-03 15:17:25 +0000
2051@@ -183,3 +183,4 @@
2052
2053 extern void *default_get_pch_validity (size_t *);
2054 extern const char *default_pch_valid_p (const void *, size_t);
2055+extern bool default_legitimate_constant_p (enum machine_mode, rtx);
2056
2057=== added file 'gcc/testsuite/gcc.target/arm/neon-vld3-1.c'
2058--- old/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 1970-01-01 00:00:00 +0000
2059+++ new/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 2011-05-03 15:14:56 +0000
2060@@ -0,0 +1,27 @@
2061+/* { dg-do run } */
2062+/* { dg-require-effective-target arm_neon_hw } */
2063+/* { dg-options "-O2" } */
2064+/* { dg-add-options arm_neon } */
2065+
2066+#include "arm_neon.h"
2067+
2068+uint32_t buffer[12];
2069+
2070+void __attribute__((noinline))
2071+foo (uint32_t *a)
2072+{
2073+ uint32x4x3_t x;
2074+
2075+ x = vld3q_u32 (a);
2076+ x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
2077+ vst3q_u32 (a, x);
2078+}
2079+
2080+int
2081+main (void)
2082+{
2083+ buffer[0] = 1;
2084+ buffer[1] = 2;
2085+ foo (buffer);
2086+ return buffer[0] != 3;
2087+}
2088
2089=== added file 'gcc/testsuite/gcc.target/arm/neon-vst3-1.c'
2090--- old/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 1970-01-01 00:00:00 +0000
2091+++ new/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 2011-05-03 15:14:56 +0000
2092@@ -0,0 +1,25 @@
2093+/* { dg-do run } */
2094+/* { dg-require-effective-target arm_neon_hw } */
2095+/* { dg-options "-O2" } */
2096+/* { dg-add-options arm_neon } */
2097+
2098+#include "arm_neon.h"
2099+
2100+uint32_t buffer[64];
2101+
2102+void __attribute__((noinline))
2103+foo (uint32_t *a)
2104+{
2105+ uint32x4x3_t x;
2106+
2107+ x = vld3q_u32 (a);
2108+ a[35] = 1;
2109+ vst3q_lane_u32 (a + 32, x, 1);
2110+}
2111+
2112+int
2113+main (void)
2114+{
2115+ foo (buffer);
2116+ return buffer[35] != 1;
2117+}
2118
2119=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c'
2120--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-05-24 18:36:31 +0000
2121+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-05-03 15:14:56 +0000
2122@@ -15,5 +15,5 @@
2123 out_float32x4_t = vld1q_dup_f32 (0);
2124 }
2125
2126-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2127+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2128 /* { dg-final { cleanup-saved-temps } } */
2129
2130=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c'
2131--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-05-24 18:36:31 +0000
2132+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-05-03 15:14:56 +0000
2133@@ -15,5 +15,5 @@
2134 out_poly16x8_t = vld1q_dup_p16 (0);
2135 }
2136
2137-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2138+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2139 /* { dg-final { cleanup-saved-temps } } */
2140
2141=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c'
2142--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-05-24 18:36:31 +0000
2143+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-05-03 15:14:56 +0000
2144@@ -15,5 +15,5 @@
2145 out_poly8x16_t = vld1q_dup_p8 (0);
2146 }
2147
2148-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2149+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2150 /* { dg-final { cleanup-saved-temps } } */
2151
2152=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c'
2153--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-05-24 18:36:31 +0000
2154+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-05-03 15:14:56 +0000
2155@@ -15,5 +15,5 @@
2156 out_int16x8_t = vld1q_dup_s16 (0);
2157 }
2158
2159-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2160+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2161 /* { dg-final { cleanup-saved-temps } } */
2162
2163=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c'
2164--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-05-24 18:36:31 +0000
2165+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-05-03 15:14:56 +0000
2166@@ -15,5 +15,5 @@
2167 out_int32x4_t = vld1q_dup_s32 (0);
2168 }
2169
2170-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2171+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2172 /* { dg-final { cleanup-saved-temps } } */
2173
2174=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c'
2175--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-05-24 18:36:31 +0000
2176+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-05-03 15:14:56 +0000
2177@@ -15,5 +15,5 @@
2178 out_int64x2_t = vld1q_dup_s64 (0);
2179 }
2180
2181-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2182+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2183 /* { dg-final { cleanup-saved-temps } } */
2184
2185=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c'
2186--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-05-24 18:36:31 +0000
2187+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-05-03 15:14:56 +0000
2188@@ -15,5 +15,5 @@
2189 out_int8x16_t = vld1q_dup_s8 (0);
2190 }
2191
2192-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2193+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2194 /* { dg-final { cleanup-saved-temps } } */
2195
2196=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c'
2197--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-05-24 18:36:31 +0000
2198+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-05-03 15:14:56 +0000
2199@@ -15,5 +15,5 @@
2200 out_uint16x8_t = vld1q_dup_u16 (0);
2201 }
2202
2203-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2204+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2205 /* { dg-final { cleanup-saved-temps } } */
2206
2207=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c'
2208--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-05-24 18:36:31 +0000
2209+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-05-03 15:14:56 +0000
2210@@ -15,5 +15,5 @@
2211 out_uint32x4_t = vld1q_dup_u32 (0);
2212 }
2213
2214-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2215+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2216 /* { dg-final { cleanup-saved-temps } } */
2217
2218=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c'
2219--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-05-24 18:36:31 +0000
2220+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-05-03 15:14:56 +0000
2221@@ -15,5 +15,5 @@
2222 out_uint64x2_t = vld1q_dup_u64 (0);
2223 }
2224
2225-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2226+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2227 /* { dg-final { cleanup-saved-temps } } */
2228
2229=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c'
2230--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-05-24 18:36:31 +0000
2231+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-05-03 15:14:56 +0000
2232@@ -15,5 +15,5 @@
2233 out_uint8x16_t = vld1q_dup_u8 (0);
2234 }
2235
2236-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2237+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2238 /* { dg-final { cleanup-saved-temps } } */
2239
2240=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c'
2241--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-05-24 18:36:31 +0000
2242+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-05-03 15:14:56 +0000
2243@@ -16,5 +16,5 @@
2244 out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
2245 }
2246
2247-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2248+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2249 /* { dg-final { cleanup-saved-temps } } */
2250
2251=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c'
2252--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-05-24 18:36:31 +0000
2253+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-05-03 15:14:56 +0000
2254@@ -16,5 +16,5 @@
2255 out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
2256 }
2257
2258-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2259+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2260 /* { dg-final { cleanup-saved-temps } } */
2261
2262=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c'
2263--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-05-24 18:36:31 +0000
2264+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-05-03 15:14:56 +0000
2265@@ -16,5 +16,5 @@
2266 out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
2267 }
2268
2269-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2270+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2271 /* { dg-final { cleanup-saved-temps } } */
2272
2273=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c'
2274--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-05-24 18:36:31 +0000
2275+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-05-03 15:14:56 +0000
2276@@ -16,5 +16,5 @@
2277 out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
2278 }
2279
2280-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2281+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2282 /* { dg-final { cleanup-saved-temps } } */
2283
2284=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c'
2285--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-05-24 18:36:31 +0000
2286+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-05-03 15:14:56 +0000
2287@@ -16,5 +16,5 @@
2288 out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
2289 }
2290
2291-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2292+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2293 /* { dg-final { cleanup-saved-temps } } */
2294
2295=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c'
2296--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-05-24 18:36:31 +0000
2297+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-05-03 15:14:56 +0000
2298@@ -16,5 +16,5 @@
2299 out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
2300 }
2301
2302-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2303+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2304 /* { dg-final { cleanup-saved-temps } } */
2305
2306=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c'
2307--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-05-24 18:36:31 +0000
2308+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-05-03 15:14:56 +0000
2309@@ -16,5 +16,5 @@
2310 out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
2311 }
2312
2313-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2314+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2315 /* { dg-final { cleanup-saved-temps } } */
2316
2317=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c'
2318--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-05-24 18:36:31 +0000
2319+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-05-03 15:14:56 +0000
2320@@ -16,5 +16,5 @@
2321 out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
2322 }
2323
2324-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2325+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2326 /* { dg-final { cleanup-saved-temps } } */
2327
2328=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c'
2329--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-05-24 18:36:31 +0000
2330+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-05-03 15:14:56 +0000
2331@@ -16,5 +16,5 @@
2332 out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
2333 }
2334
2335-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2336+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2337 /* { dg-final { cleanup-saved-temps } } */
2338
2339=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c'
2340--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-05-24 18:36:31 +0000
2341+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-05-03 15:14:56 +0000
2342@@ -16,5 +16,5 @@
2343 out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
2344 }
2345
2346-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2347+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2348 /* { dg-final { cleanup-saved-temps } } */
2349
2350=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c'
2351--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-05-24 18:36:31 +0000
2352+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-05-03 15:14:56 +0000
2353@@ -16,5 +16,5 @@
2354 out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
2355 }
2356
2357-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2358+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2359 /* { dg-final { cleanup-saved-temps } } */
2360
2361=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c'
2362--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-05-24 18:36:31 +0000
2363+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-05-03 15:14:56 +0000
2364@@ -15,5 +15,5 @@
2365 out_float32x4_t = vld1q_f32 (0);
2366 }
2367
2368-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2369+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2370 /* { dg-final { cleanup-saved-temps } } */
2371
2372=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c'
2373--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-05-24 18:36:31 +0000
2374+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-05-03 15:14:56 +0000
2375@@ -15,5 +15,5 @@
2376 out_poly16x8_t = vld1q_p16 (0);
2377 }
2378
2379-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2380+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2381 /* { dg-final { cleanup-saved-temps } } */
2382
2383=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c'
2384--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-05-24 18:36:31 +0000
2385+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-05-03 15:14:56 +0000
2386@@ -15,5 +15,5 @@
2387 out_poly8x16_t = vld1q_p8 (0);
2388 }
2389
2390-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2391+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2392 /* { dg-final { cleanup-saved-temps } } */
2393
2394=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c'
2395--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-05-24 18:36:31 +0000
2396+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-05-03 15:14:56 +0000
2397@@ -15,5 +15,5 @@
2398 out_int16x8_t = vld1q_s16 (0);
2399 }
2400
2401-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2402+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2403 /* { dg-final { cleanup-saved-temps } } */
2404
2405=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c'
2406--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-05-24 18:36:31 +0000
2407+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-05-03 15:14:56 +0000
2408@@ -15,5 +15,5 @@
2409 out_int32x4_t = vld1q_s32 (0);
2410 }
2411
2412-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2413+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2414 /* { dg-final { cleanup-saved-temps } } */
2415
2416=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c'
2417--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-05-24 18:36:31 +0000
2418+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-05-03 15:14:56 +0000
2419@@ -15,5 +15,5 @@
2420 out_int64x2_t = vld1q_s64 (0);
2421 }
2422
2423-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2424+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2425 /* { dg-final { cleanup-saved-temps } } */
2426
2427=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c'
2428--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-05-24 18:36:31 +0000
2429+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-05-03 15:14:56 +0000
2430@@ -15,5 +15,5 @@
2431 out_int8x16_t = vld1q_s8 (0);
2432 }
2433
2434-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2435+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2436 /* { dg-final { cleanup-saved-temps } } */
2437
2438=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c'
2439--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-05-24 18:36:31 +0000
2440+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-05-03 15:14:56 +0000
2441@@ -15,5 +15,5 @@
2442 out_uint16x8_t = vld1q_u16 (0);
2443 }
2444
2445-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2446+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2447 /* { dg-final { cleanup-saved-temps } } */
2448
2449=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c'
2450--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-05-24 18:36:31 +0000
2451+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-05-03 15:14:56 +0000
2452@@ -15,5 +15,5 @@
2453 out_uint32x4_t = vld1q_u32 (0);
2454 }
2455
2456-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2457+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2458 /* { dg-final { cleanup-saved-temps } } */
2459
2460=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c'
2461--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-05-24 18:36:31 +0000
2462+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-05-03 15:14:56 +0000
2463@@ -15,5 +15,5 @@
2464 out_uint64x2_t = vld1q_u64 (0);
2465 }
2466
2467-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2468+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2469 /* { dg-final { cleanup-saved-temps } } */
2470
2471=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c'
2472--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-05-24 18:36:31 +0000
2473+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-05-03 15:14:56 +0000
2474@@ -15,5 +15,5 @@
2475 out_uint8x16_t = vld1q_u8 (0);
2476 }
2477
2478-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2479+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2480 /* { dg-final { cleanup-saved-temps } } */
2481
2482=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c'
2483--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-05-24 18:36:31 +0000
2484+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-05-03 15:14:56 +0000
2485@@ -15,5 +15,5 @@
2486 out_float32x2_t = vld1_dup_f32 (0);
2487 }
2488
2489-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2490+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2491 /* { dg-final { cleanup-saved-temps } } */
2492
2493=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c'
2494--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-05-24 18:36:31 +0000
2495+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-05-03 15:14:56 +0000
2496@@ -15,5 +15,5 @@
2497 out_poly16x4_t = vld1_dup_p16 (0);
2498 }
2499
2500-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2501+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2502 /* { dg-final { cleanup-saved-temps } } */
2503
2504=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c'
2505--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-05-24 18:36:31 +0000
2506+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-05-03 15:14:56 +0000
2507@@ -15,5 +15,5 @@
2508 out_poly8x8_t = vld1_dup_p8 (0);
2509 }
2510
2511-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2512+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2513 /* { dg-final { cleanup-saved-temps } } */
2514
2515=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c'
2516--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-05-24 18:36:31 +0000
2517+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-05-03 15:14:56 +0000
2518@@ -15,5 +15,5 @@
2519 out_int16x4_t = vld1_dup_s16 (0);
2520 }
2521
2522-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2523+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2524 /* { dg-final { cleanup-saved-temps } } */
2525
2526=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c'
2527--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-05-24 18:36:31 +0000
2528+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-05-03 15:14:56 +0000
2529@@ -15,5 +15,5 @@
2530 out_int32x2_t = vld1_dup_s32 (0);
2531 }
2532
2533-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2534+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2535 /* { dg-final { cleanup-saved-temps } } */
2536
2537=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c'
2538--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-05-24 18:36:31 +0000
2539+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-05-03 15:14:56 +0000
2540@@ -15,5 +15,5 @@
2541 out_int64x1_t = vld1_dup_s64 (0);
2542 }
2543
2544-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2545+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2546 /* { dg-final { cleanup-saved-temps } } */
2547
2548=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c'
2549--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-05-24 18:36:31 +0000
2550+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-05-03 15:14:56 +0000
2551@@ -15,5 +15,5 @@
2552 out_int8x8_t = vld1_dup_s8 (0);
2553 }
2554
2555-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2556+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2557 /* { dg-final { cleanup-saved-temps } } */
2558
2559=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c'
2560--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-05-24 18:36:31 +0000
2561+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-05-03 15:14:56 +0000
2562@@ -15,5 +15,5 @@
2563 out_uint16x4_t = vld1_dup_u16 (0);
2564 }
2565
2566-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2567+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2568 /* { dg-final { cleanup-saved-temps } } */
2569
2570=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c'
2571--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-05-24 18:36:31 +0000
2572+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-05-03 15:14:56 +0000
2573@@ -15,5 +15,5 @@
2574 out_uint32x2_t = vld1_dup_u32 (0);
2575 }
2576
2577-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2578+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2579 /* { dg-final { cleanup-saved-temps } } */
2580
2581=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c'
2582--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-05-24 18:36:31 +0000
2583+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-05-03 15:14:56 +0000
2584@@ -15,5 +15,5 @@
2585 out_uint64x1_t = vld1_dup_u64 (0);
2586 }
2587
2588-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2589+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2590 /* { dg-final { cleanup-saved-temps } } */
2591
2592=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c'
2593--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-05-24 18:36:31 +0000
2594+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-05-03 15:14:56 +0000
2595@@ -15,5 +15,5 @@
2596 out_uint8x8_t = vld1_dup_u8 (0);
2597 }
2598
2599-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2600+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2601 /* { dg-final { cleanup-saved-temps } } */
2602
2603=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c'
2604--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-05-24 18:36:31 +0000
2605+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-05-03 15:14:56 +0000
2606@@ -16,5 +16,5 @@
2607 out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
2608 }
2609
2610-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2611+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2612 /* { dg-final { cleanup-saved-temps } } */
2613
2614=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c'
2615--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-05-24 18:36:31 +0000
2616+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-05-03 15:14:56 +0000
2617@@ -16,5 +16,5 @@
2618 out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
2619 }
2620
2621-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2622+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2623 /* { dg-final { cleanup-saved-temps } } */
2624
2625=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c'
2626--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-05-24 18:36:31 +0000
2627+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-05-03 15:14:56 +0000
2628@@ -16,5 +16,5 @@
2629 out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
2630 }
2631
2632-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2633+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2634 /* { dg-final { cleanup-saved-temps } } */
2635
2636=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c'
2637--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-05-24 18:36:31 +0000
2638+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-05-03 15:14:56 +0000
2639@@ -16,5 +16,5 @@
2640 out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
2641 }
2642
2643-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2644+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2645 /* { dg-final { cleanup-saved-temps } } */
2646
2647=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c'
2648--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-05-24 18:36:31 +0000
2649+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-05-03 15:14:56 +0000
2650@@ -16,5 +16,5 @@
2651 out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
2652 }
2653
2654-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2655+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2656 /* { dg-final { cleanup-saved-temps } } */
2657
2658=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c'
2659--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-05-24 18:36:31 +0000
2660+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-05-03 15:14:56 +0000
2661@@ -16,5 +16,5 @@
2662 out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
2663 }
2664
2665-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2666+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2667 /* { dg-final { cleanup-saved-temps } } */
2668
2669=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c'
2670--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-05-24 18:36:31 +0000
2671+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-05-03 15:14:56 +0000
2672@@ -16,5 +16,5 @@
2673 out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
2674 }
2675
2676-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2677+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2678 /* { dg-final { cleanup-saved-temps } } */
2679
2680=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c'
2681--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-05-24 18:36:31 +0000
2682+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-05-03 15:14:56 +0000
2683@@ -16,5 +16,5 @@
2684 out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
2685 }
2686
2687-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2688+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2689 /* { dg-final { cleanup-saved-temps } } */
2690
2691=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c'
2692--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-05-24 18:36:31 +0000
2693+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-05-03 15:14:56 +0000
2694@@ -16,5 +16,5 @@
2695 out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
2696 }
2697
2698-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2699+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2700 /* { dg-final { cleanup-saved-temps } } */
2701
2702=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c'
2703--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-05-24 18:36:31 +0000
2704+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-05-03 15:14:56 +0000
2705@@ -16,5 +16,5 @@
2706 out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
2707 }
2708
2709-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2710+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2711 /* { dg-final { cleanup-saved-temps } } */
2712
2713=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c'
2714--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-05-24 18:36:31 +0000
2715+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-05-03 15:14:56 +0000
2716@@ -16,5 +16,5 @@
2717 out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
2718 }
2719
2720-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2721+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2722 /* { dg-final { cleanup-saved-temps } } */
2723
2724=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c'
2725--- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-05-24 18:36:31 +0000
2726+++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-05-03 15:14:56 +0000
2727@@ -15,5 +15,5 @@
2728 out_float32x2_t = vld1_f32 (0);
2729 }
2730
2731-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2732+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2733 /* { dg-final { cleanup-saved-temps } } */
2734
2735=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c'
2736--- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-05-24 18:36:31 +0000
2737+++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-05-03 15:14:56 +0000
2738@@ -15,5 +15,5 @@
2739 out_poly16x4_t = vld1_p16 (0);
2740 }
2741
2742-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2743+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2744 /* { dg-final { cleanup-saved-temps } } */
2745
2746=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c'
2747--- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-05-24 18:36:31 +0000
2748+++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-05-03 15:14:56 +0000
2749@@ -15,5 +15,5 @@
2750 out_poly8x8_t = vld1_p8 (0);
2751 }
2752
2753-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2754+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2755 /* { dg-final { cleanup-saved-temps } } */
2756
2757=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c'
2758--- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-05-24 18:36:31 +0000
2759+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-05-03 15:14:56 +0000
2760@@ -15,5 +15,5 @@
2761 out_int16x4_t = vld1_s16 (0);
2762 }
2763
2764-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2765+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2766 /* { dg-final { cleanup-saved-temps } } */
2767
2768=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c'
2769--- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-05-24 18:36:31 +0000
2770+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-05-03 15:14:56 +0000
2771@@ -15,5 +15,5 @@
2772 out_int32x2_t = vld1_s32 (0);
2773 }
2774
2775-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2776+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2777 /* { dg-final { cleanup-saved-temps } } */
2778
2779=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c'
2780--- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-05-24 18:36:31 +0000
2781+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-05-03 15:14:56 +0000
2782@@ -15,5 +15,5 @@
2783 out_int64x1_t = vld1_s64 (0);
2784 }
2785
2786-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2787+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2788 /* { dg-final { cleanup-saved-temps } } */
2789
2790=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c'
2791--- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-05-24 18:36:31 +0000
2792+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-05-03 15:14:56 +0000
2793@@ -15,5 +15,5 @@
2794 out_int8x8_t = vld1_s8 (0);
2795 }
2796
2797-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2798+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2799 /* { dg-final { cleanup-saved-temps } } */
2800
2801=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c'
2802--- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-05-24 18:36:31 +0000
2803+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-05-03 15:14:56 +0000
2804@@ -15,5 +15,5 @@
2805 out_uint16x4_t = vld1_u16 (0);
2806 }
2807
2808-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2809+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2810 /* { dg-final { cleanup-saved-temps } } */
2811
2812=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c'
2813--- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-05-24 18:36:31 +0000
2814+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-05-03 15:14:56 +0000
2815@@ -15,5 +15,5 @@
2816 out_uint32x2_t = vld1_u32 (0);
2817 }
2818
2819-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2820+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2821 /* { dg-final { cleanup-saved-temps } } */
2822
2823=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c'
2824--- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-05-24 18:36:31 +0000
2825+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-05-03 15:14:56 +0000
2826@@ -15,5 +15,5 @@
2827 out_uint64x1_t = vld1_u64 (0);
2828 }
2829
2830-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2831+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2832 /* { dg-final { cleanup-saved-temps } } */
2833
2834=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c'
2835--- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-05-24 18:36:31 +0000
2836+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-05-03 15:14:56 +0000
2837@@ -15,5 +15,5 @@
2838 out_uint8x8_t = vld1_u8 (0);
2839 }
2840
2841-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2842+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2843 /* { dg-final { cleanup-saved-temps } } */
2844
2845=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c'
2846--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-05-24 18:36:31 +0000
2847+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-05-03 15:14:56 +0000
2848@@ -16,5 +16,5 @@
2849 out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
2850 }
2851
2852-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2853+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2854 /* { dg-final { cleanup-saved-temps } } */
2855
2856=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c'
2857--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-05-24 18:36:31 +0000
2858+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-05-03 15:14:56 +0000
2859@@ -16,5 +16,5 @@
2860 out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
2861 }
2862
2863-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2864+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2865 /* { dg-final { cleanup-saved-temps } } */
2866
2867=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c'
2868--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-05-24 18:36:31 +0000
2869+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-05-03 15:14:56 +0000
2870@@ -16,5 +16,5 @@
2871 out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
2872 }
2873
2874-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2875+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2876 /* { dg-final { cleanup-saved-temps } } */
2877
2878=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c'
2879--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-05-24 18:36:31 +0000
2880+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-05-03 15:14:56 +0000
2881@@ -16,5 +16,5 @@
2882 out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
2883 }
2884
2885-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2886+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2887 /* { dg-final { cleanup-saved-temps } } */
2888
2889=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c'
2890--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-05-24 18:36:31 +0000
2891+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-05-03 15:14:56 +0000
2892@@ -16,5 +16,5 @@
2893 out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
2894 }
2895
2896-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2897+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2898 /* { dg-final { cleanup-saved-temps } } */
2899
2900=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c'
2901--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-05-24 18:36:31 +0000
2902+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-05-03 15:14:56 +0000
2903@@ -16,5 +16,5 @@
2904 out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
2905 }
2906
2907-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2908+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2909 /* { dg-final { cleanup-saved-temps } } */
2910
2911=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c'
2912--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-05-24 18:36:31 +0000
2913+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-05-03 15:14:56 +0000
2914@@ -15,6 +15,6 @@
2915 out_float32x4x2_t = vld2q_f32 (0);
2916 }
2917
2918-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2919-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2920+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2921+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2922 /* { dg-final { cleanup-saved-temps } } */
2923
2924=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c'
2925--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-05-24 18:36:31 +0000
2926+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-05-03 15:14:56 +0000
2927@@ -15,6 +15,6 @@
2928 out_poly16x8x2_t = vld2q_p16 (0);
2929 }
2930
2931-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2932-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2933+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2934+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2935 /* { dg-final { cleanup-saved-temps } } */
2936
2937=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c'
2938--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-05-24 18:36:31 +0000
2939+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-05-03 15:14:56 +0000
2940@@ -15,6 +15,6 @@
2941 out_poly8x16x2_t = vld2q_p8 (0);
2942 }
2943
2944-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2945-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2946+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2947+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2948 /* { dg-final { cleanup-saved-temps } } */
2949
2950=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c'
2951--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-05-24 18:36:31 +0000
2952+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-05-03 15:14:56 +0000
2953@@ -15,6 +15,6 @@
2954 out_int16x8x2_t = vld2q_s16 (0);
2955 }
2956
2957-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2958-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2959+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2960+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2961 /* { dg-final { cleanup-saved-temps } } */
2962
2963=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c'
2964--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-05-24 18:36:31 +0000
2965+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-05-03 15:14:56 +0000
2966@@ -15,6 +15,6 @@
2967 out_int32x4x2_t = vld2q_s32 (0);
2968 }
2969
2970-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2971-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2972+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2973+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2974 /* { dg-final { cleanup-saved-temps } } */
2975
2976=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c'
2977--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-05-24 18:36:31 +0000
2978+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-05-03 15:14:56 +0000
2979@@ -15,6 +15,6 @@
2980 out_int8x16x2_t = vld2q_s8 (0);
2981 }
2982
2983-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2984-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2985+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2986+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2987 /* { dg-final { cleanup-saved-temps } } */
2988
2989=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c'
2990--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-05-24 18:36:31 +0000
2991+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-05-03 15:14:56 +0000
2992@@ -15,6 +15,6 @@
2993 out_uint16x8x2_t = vld2q_u16 (0);
2994 }
2995
2996-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2997-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2998+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2999+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3000 /* { dg-final { cleanup-saved-temps } } */
3001
3002=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c'
3003--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-05-24 18:36:31 +0000
3004+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-05-03 15:14:56 +0000
3005@@ -15,6 +15,6 @@
3006 out_uint32x4x2_t = vld2q_u32 (0);
3007 }
3008
3009-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3010-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3011+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3012+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3013 /* { dg-final { cleanup-saved-temps } } */
3014
3015=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c'
3016--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-05-24 18:36:31 +0000
3017+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-05-03 15:14:56 +0000
3018@@ -15,6 +15,6 @@
3019 out_uint8x16x2_t = vld2q_u8 (0);
3020 }
3021
3022-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3023-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3024+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3025+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3026 /* { dg-final { cleanup-saved-temps } } */
3027
3028=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c'
3029--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-05-24 18:36:31 +0000
3030+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-05-03 15:14:56 +0000
3031@@ -15,5 +15,5 @@
3032 out_float32x2x2_t = vld2_dup_f32 (0);
3033 }
3034
3035-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3036+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3037 /* { dg-final { cleanup-saved-temps } } */
3038
3039=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c'
3040--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-05-24 18:36:31 +0000
3041+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-05-03 15:14:56 +0000
3042@@ -15,5 +15,5 @@
3043 out_poly16x4x2_t = vld2_dup_p16 (0);
3044 }
3045
3046-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3047+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3048 /* { dg-final { cleanup-saved-temps } } */
3049
3050=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c'
3051--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-05-24 18:36:31 +0000
3052+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-05-03 15:14:56 +0000
3053@@ -15,5 +15,5 @@
3054 out_poly8x8x2_t = vld2_dup_p8 (0);
3055 }
3056
3057-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3058+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3059 /* { dg-final { cleanup-saved-temps } } */
3060
3061=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c'
3062--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-05-24 18:36:31 +0000
3063+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-05-03 15:14:56 +0000
3064@@ -15,5 +15,5 @@
3065 out_int16x4x2_t = vld2_dup_s16 (0);
3066 }
3067
3068-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3069+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3070 /* { dg-final { cleanup-saved-temps } } */
3071
3072=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c'
3073--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-05-24 18:36:31 +0000
3074+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-05-03 15:14:56 +0000
3075@@ -15,5 +15,5 @@
3076 out_int32x2x2_t = vld2_dup_s32 (0);
3077 }
3078
3079-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3080+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3081 /* { dg-final { cleanup-saved-temps } } */
3082
3083=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c'
3084--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-05-24 18:36:31 +0000
3085+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-05-03 15:14:56 +0000
3086@@ -15,5 +15,5 @@
3087 out_int64x1x2_t = vld2_dup_s64 (0);
3088 }
3089
3090-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3091+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3092 /* { dg-final { cleanup-saved-temps } } */
3093
3094=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c'
3095--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-05-24 18:36:31 +0000
3096+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-05-03 15:14:56 +0000
3097@@ -15,5 +15,5 @@
3098 out_int8x8x2_t = vld2_dup_s8 (0);
3099 }
3100
3101-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3102+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3103 /* { dg-final { cleanup-saved-temps } } */
3104
3105=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c'
3106--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-05-24 18:36:31 +0000
3107+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-05-03 15:14:56 +0000
3108@@ -15,5 +15,5 @@
3109 out_uint16x4x2_t = vld2_dup_u16 (0);
3110 }
3111
3112-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3113+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3114 /* { dg-final { cleanup-saved-temps } } */
3115
3116=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c'
3117--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-05-24 18:36:31 +0000
3118+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-05-03 15:14:56 +0000
3119@@ -15,5 +15,5 @@
3120 out_uint32x2x2_t = vld2_dup_u32 (0);
3121 }
3122
3123-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3124+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3125 /* { dg-final { cleanup-saved-temps } } */
3126
3127=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c'
3128--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-05-24 18:36:31 +0000
3129+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-05-03 15:14:56 +0000
3130@@ -15,5 +15,5 @@
3131 out_uint64x1x2_t = vld2_dup_u64 (0);
3132 }
3133
3134-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3135+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3136 /* { dg-final { cleanup-saved-temps } } */
3137
3138=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c'
3139--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-05-24 18:36:31 +0000
3140+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-05-03 15:14:56 +0000
3141@@ -15,5 +15,5 @@
3142 out_uint8x8x2_t = vld2_dup_u8 (0);
3143 }
3144
3145-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3146+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3147 /* { dg-final { cleanup-saved-temps } } */
3148
3149=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c'
3150--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-05-24 18:36:31 +0000
3151+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-05-03 15:14:56 +0000
3152@@ -16,5 +16,5 @@
3153 out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
3154 }
3155
3156-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3157+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3158 /* { dg-final { cleanup-saved-temps } } */
3159
3160=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c'
3161--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-05-24 18:36:31 +0000
3162+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-05-03 15:14:56 +0000
3163@@ -16,5 +16,5 @@
3164 out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
3165 }
3166
3167-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3168+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3169 /* { dg-final { cleanup-saved-temps } } */
3170
3171=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c'
3172--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-05-24 18:36:31 +0000
3173+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-05-03 15:14:56 +0000
3174@@ -16,5 +16,5 @@
3175 out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
3176 }
3177
3178-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3179+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3180 /* { dg-final { cleanup-saved-temps } } */
3181
3182=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c'
3183--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-05-24 18:36:31 +0000
3184+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-05-03 15:14:56 +0000
3185@@ -16,5 +16,5 @@
3186 out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
3187 }
3188
3189-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3190+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3191 /* { dg-final { cleanup-saved-temps } } */
3192
3193=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c'
3194--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-05-24 18:36:31 +0000
3195+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-05-03 15:14:56 +0000
3196@@ -16,5 +16,5 @@
3197 out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
3198 }
3199
3200-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3201+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3202 /* { dg-final { cleanup-saved-temps } } */
3203
3204=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c'
3205--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-05-24 18:36:31 +0000
3206+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-05-03 15:14:56 +0000
3207@@ -16,5 +16,5 @@
3208 out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
3209 }
3210
3211-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3212+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3213 /* { dg-final { cleanup-saved-temps } } */
3214
3215=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c'
3216--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-05-24 18:36:31 +0000
3217+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-05-03 15:14:56 +0000
3218@@ -16,5 +16,5 @@
3219 out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
3220 }
3221
3222-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3223+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3224 /* { dg-final { cleanup-saved-temps } } */
3225
3226=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c'
3227--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-05-24 18:36:31 +0000
3228+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-05-03 15:14:56 +0000
3229@@ -16,5 +16,5 @@
3230 out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
3231 }
3232
3233-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3234+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3235 /* { dg-final { cleanup-saved-temps } } */
3236
3237=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c'
3238--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-05-24 18:36:31 +0000
3239+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-05-03 15:14:56 +0000
3240@@ -16,5 +16,5 @@
3241 out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
3242 }
3243
3244-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3245+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3246 /* { dg-final { cleanup-saved-temps } } */
3247
3248=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c'
3249--- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-05-24 18:36:31 +0000
3250+++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-05-03 15:14:56 +0000
3251@@ -15,5 +15,5 @@
3252 out_float32x2x2_t = vld2_f32 (0);
3253 }
3254
3255-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3256+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3257 /* { dg-final { cleanup-saved-temps } } */
3258
3259=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c'
3260--- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-05-24 18:36:31 +0000
3261+++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-05-03 15:14:56 +0000
3262@@ -15,5 +15,5 @@
3263 out_poly16x4x2_t = vld2_p16 (0);
3264 }
3265
3266-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3267+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3268 /* { dg-final { cleanup-saved-temps } } */
3269
3270=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c'
3271--- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-05-24 18:36:31 +0000
3272+++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-05-03 15:14:56 +0000
3273@@ -15,5 +15,5 @@
3274 out_poly8x8x2_t = vld2_p8 (0);
3275 }
3276
3277-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3278+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3279 /* { dg-final { cleanup-saved-temps } } */
3280
3281=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c'
3282--- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-05-24 18:36:31 +0000
3283+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-05-03 15:14:56 +0000
3284@@ -15,5 +15,5 @@
3285 out_int16x4x2_t = vld2_s16 (0);
3286 }
3287
3288-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3289+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3290 /* { dg-final { cleanup-saved-temps } } */
3291
3292=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c'
3293--- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-05-24 18:36:31 +0000
3294+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-05-03 15:14:56 +0000
3295@@ -15,5 +15,5 @@
3296 out_int32x2x2_t = vld2_s32 (0);
3297 }
3298
3299-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3300+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3301 /* { dg-final { cleanup-saved-temps } } */
3302
3303=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c'
3304--- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-05-24 18:36:31 +0000
3305+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-05-03 15:14:56 +0000
3306@@ -15,5 +15,5 @@
3307 out_int64x1x2_t = vld2_s64 (0);
3308 }
3309
3310-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3311+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3312 /* { dg-final { cleanup-saved-temps } } */
3313
3314=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c'
3315--- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-05-24 18:36:31 +0000
3316+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-05-03 15:14:56 +0000
3317@@ -15,5 +15,5 @@
3318 out_int8x8x2_t = vld2_s8 (0);
3319 }
3320
3321-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3322+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3323 /* { dg-final { cleanup-saved-temps } } */
3324
3325=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c'
3326--- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-05-24 18:36:31 +0000
3327+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-05-03 15:14:56 +0000
3328@@ -15,5 +15,5 @@
3329 out_uint16x4x2_t = vld2_u16 (0);
3330 }
3331
3332-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3333+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3334 /* { dg-final { cleanup-saved-temps } } */
3335
3336=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c'
3337--- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-05-24 18:36:31 +0000
3338+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-05-03 15:14:56 +0000
3339@@ -15,5 +15,5 @@
3340 out_uint32x2x2_t = vld2_u32 (0);
3341 }
3342
3343-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3344+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3345 /* { dg-final { cleanup-saved-temps } } */
3346
3347=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c'
3348--- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-05-24 18:36:31 +0000
3349+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-05-03 15:14:56 +0000
3350@@ -15,5 +15,5 @@
3351 out_uint64x1x2_t = vld2_u64 (0);
3352 }
3353
3354-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3355+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3356 /* { dg-final { cleanup-saved-temps } } */
3357
3358=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c'
3359--- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-05-24 18:36:31 +0000
3360+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-05-03 15:14:56 +0000
3361@@ -15,5 +15,5 @@
3362 out_uint8x8x2_t = vld2_u8 (0);
3363 }
3364
3365-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3366+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3367 /* { dg-final { cleanup-saved-temps } } */
3368
3369=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c'
3370--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-05-24 18:36:31 +0000
3371+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-05-03 15:14:56 +0000
3372@@ -16,5 +16,5 @@
3373 out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
3374 }
3375
3376-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3377+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3378 /* { dg-final { cleanup-saved-temps } } */
3379
3380=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c'
3381--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-05-24 18:36:31 +0000
3382+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-05-03 15:14:56 +0000
3383@@ -16,5 +16,5 @@
3384 out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
3385 }
3386
3387-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3388+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3389 /* { dg-final { cleanup-saved-temps } } */
3390
3391=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c'
3392--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-05-24 18:36:31 +0000
3393+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-05-03 15:14:56 +0000
3394@@ -16,5 +16,5 @@
3395 out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
3396 }
3397
3398-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3399+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3400 /* { dg-final { cleanup-saved-temps } } */
3401
3402=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c'
3403--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-05-24 18:36:31 +0000
3404+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-05-03 15:14:56 +0000
3405@@ -16,5 +16,5 @@
3406 out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
3407 }
3408
3409-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3410+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3411 /* { dg-final { cleanup-saved-temps } } */
3412
3413=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c'
3414--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-05-24 18:36:31 +0000
3415+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-05-03 15:14:56 +0000
3416@@ -16,5 +16,5 @@
3417 out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
3418 }
3419
3420-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3421+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3422 /* { dg-final { cleanup-saved-temps } } */
3423
3424=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c'
3425--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-05-24 18:36:31 +0000
3426+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-05-03 15:14:56 +0000
3427@@ -16,5 +16,5 @@
3428 out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
3429 }
3430
3431-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3432+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3433 /* { dg-final { cleanup-saved-temps } } */
3434
3435=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c'
3436--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-05-24 18:36:31 +0000
3437+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-05-03 15:14:56 +0000
3438@@ -15,6 +15,6 @@
3439 out_float32x4x3_t = vld3q_f32 (0);
3440 }
3441
3442-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3443-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3444+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3445+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3446 /* { dg-final { cleanup-saved-temps } } */
3447
3448=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c'
3449--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-05-24 18:36:31 +0000
3450+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-05-03 15:14:56 +0000
3451@@ -15,6 +15,6 @@
3452 out_poly16x8x3_t = vld3q_p16 (0);
3453 }
3454
3455-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3456-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3457+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3458+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3459 /* { dg-final { cleanup-saved-temps } } */
3460
3461=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c'
3462--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-05-24 18:36:31 +0000
3463+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-05-03 15:14:56 +0000
3464@@ -15,6 +15,6 @@
3465 out_poly8x16x3_t = vld3q_p8 (0);
3466 }
3467
3468-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3469-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3470+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3471+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3472 /* { dg-final { cleanup-saved-temps } } */
3473
3474=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c'
3475--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-05-24 18:36:31 +0000
3476+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-05-03 15:14:56 +0000
3477@@ -15,6 +15,6 @@
3478 out_int16x8x3_t = vld3q_s16 (0);
3479 }
3480
3481-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3482-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3483+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3484+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3485 /* { dg-final { cleanup-saved-temps } } */
3486
3487=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c'
3488--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-05-24 18:36:31 +0000
3489+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-05-03 15:14:56 +0000
3490@@ -15,6 +15,6 @@
3491 out_int32x4x3_t = vld3q_s32 (0);
3492 }
3493
3494-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3495-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3496+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3497+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3498 /* { dg-final { cleanup-saved-temps } } */
3499
3500=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c'
3501--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-05-24 18:36:31 +0000
3502+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-05-03 15:14:56 +0000
3503@@ -15,6 +15,6 @@
3504 out_int8x16x3_t = vld3q_s8 (0);
3505 }
3506
3507-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3508-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3509+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3510+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3511 /* { dg-final { cleanup-saved-temps } } */
3512
3513=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c'
3514--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-05-24 18:36:31 +0000
3515+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-05-03 15:14:56 +0000
3516@@ -15,6 +15,6 @@
3517 out_uint16x8x3_t = vld3q_u16 (0);
3518 }
3519
3520-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3521-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3522+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3523+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3524 /* { dg-final { cleanup-saved-temps } } */
3525
3526=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c'
3527--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-05-24 18:36:31 +0000
3528+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-05-03 15:14:56 +0000
3529@@ -15,6 +15,6 @@
3530 out_uint32x4x3_t = vld3q_u32 (0);
3531 }
3532
3533-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3534-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3535+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3536+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3537 /* { dg-final { cleanup-saved-temps } } */
3538
3539=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c'
3540--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-05-24 18:36:31 +0000
3541+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-05-03 15:14:56 +0000
3542@@ -15,6 +15,6 @@
3543 out_uint8x16x3_t = vld3q_u8 (0);
3544 }
3545
3546-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3547-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3548+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3549+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3550 /* { dg-final { cleanup-saved-temps } } */
3551
3552=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c'
3553--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-05-24 18:36:31 +0000
3554+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-05-03 15:14:56 +0000
3555@@ -15,5 +15,5 @@
3556 out_float32x2x3_t = vld3_dup_f32 (0);
3557 }
3558
3559-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3560+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3561 /* { dg-final { cleanup-saved-temps } } */
3562
3563=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c'
3564--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-05-24 18:36:31 +0000
3565+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-05-03 15:14:56 +0000
3566@@ -15,5 +15,5 @@
3567 out_poly16x4x3_t = vld3_dup_p16 (0);
3568 }
3569
3570-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3571+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3572 /* { dg-final { cleanup-saved-temps } } */
3573
3574=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c'
3575--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-05-24 18:36:31 +0000
3576+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-05-03 15:14:56 +0000
3577@@ -15,5 +15,5 @@
3578 out_poly8x8x3_t = vld3_dup_p8 (0);
3579 }
3580
3581-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3582+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3583 /* { dg-final { cleanup-saved-temps } } */
3584
3585=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c'
3586--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-05-24 18:36:31 +0000
3587+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-05-03 15:14:56 +0000
3588@@ -15,5 +15,5 @@
3589 out_int16x4x3_t = vld3_dup_s16 (0);
3590 }
3591
3592-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3593+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3594 /* { dg-final { cleanup-saved-temps } } */
3595
3596=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c'
3597--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-05-24 18:36:31 +0000
3598+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-05-03 15:14:56 +0000
3599@@ -15,5 +15,5 @@
3600 out_int32x2x3_t = vld3_dup_s32 (0);
3601 }
3602
3603-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3604+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3605 /* { dg-final { cleanup-saved-temps } } */
3606
3607=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c'
3608--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-05-24 18:36:31 +0000
3609+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-05-03 15:14:56 +0000
3610@@ -15,5 +15,5 @@
3611 out_int64x1x3_t = vld3_dup_s64 (0);
3612 }
3613
3614-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3615+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3616 /* { dg-final { cleanup-saved-temps } } */
3617
3618=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c'
3619--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-05-24 18:36:31 +0000
3620+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-05-03 15:14:56 +0000
3621@@ -15,5 +15,5 @@
3622 out_int8x8x3_t = vld3_dup_s8 (0);
3623 }
3624
3625-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3626+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3627 /* { dg-final { cleanup-saved-temps } } */
3628
3629=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c'
3630--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-05-24 18:36:31 +0000
3631+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-05-03 15:14:56 +0000
3632@@ -15,5 +15,5 @@
3633 out_uint16x4x3_t = vld3_dup_u16 (0);
3634 }
3635
3636-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3637+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3638 /* { dg-final { cleanup-saved-temps } } */
3639
3640=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c'
3641--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-05-24 18:36:31 +0000
3642+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-05-03 15:14:56 +0000
3643@@ -15,5 +15,5 @@
3644 out_uint32x2x3_t = vld3_dup_u32 (0);
3645 }
3646
3647-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3648+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3649 /* { dg-final { cleanup-saved-temps } } */
3650
3651=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c'
3652--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-05-24 18:36:31 +0000
3653+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-05-03 15:14:56 +0000
3654@@ -15,5 +15,5 @@
3655 out_uint64x1x3_t = vld3_dup_u64 (0);
3656 }
3657
3658-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3659+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3660 /* { dg-final { cleanup-saved-temps } } */
3661
3662=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c'
3663--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-05-24 18:36:31 +0000
3664+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-05-03 15:14:56 +0000
3665@@ -15,5 +15,5 @@
3666 out_uint8x8x3_t = vld3_dup_u8 (0);
3667 }
3668
3669-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3670+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3671 /* { dg-final { cleanup-saved-temps } } */
3672
3673=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c'
3674--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-05-24 18:36:31 +0000
3675+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-05-03 15:14:56 +0000
3676@@ -16,5 +16,5 @@
3677 out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
3678 }
3679
3680-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3681+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3682 /* { dg-final { cleanup-saved-temps } } */
3683
3684=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c'
3685--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-05-24 18:36:31 +0000
3686+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-05-03 15:14:56 +0000
3687@@ -16,5 +16,5 @@
3688 out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
3689 }
3690
3691-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3692+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3693 /* { dg-final { cleanup-saved-temps } } */
3694
3695=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c'
3696--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-05-24 18:36:31 +0000
3697+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-05-03 15:14:56 +0000
3698@@ -16,5 +16,5 @@
3699 out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
3700 }
3701
3702-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3703+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3704 /* { dg-final { cleanup-saved-temps } } */
3705
3706=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c'
3707--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-05-24 18:36:31 +0000
3708+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-05-03 15:14:56 +0000
3709@@ -16,5 +16,5 @@
3710 out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
3711 }
3712
3713-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3714+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3715 /* { dg-final { cleanup-saved-temps } } */
3716
3717=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c'
3718--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-05-24 18:36:31 +0000
3719+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-05-03 15:14:56 +0000
3720@@ -16,5 +16,5 @@
3721 out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
3722 }
3723
3724-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3725+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3726 /* { dg-final { cleanup-saved-temps } } */
3727
3728=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c'
3729--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-05-24 18:36:31 +0000
3730+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-05-03 15:14:56 +0000
3731@@ -16,5 +16,5 @@
3732 out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
3733 }
3734
3735-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3736+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3737 /* { dg-final { cleanup-saved-temps } } */
3738
3739=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c'
3740--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-05-24 18:36:31 +0000
3741+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-05-03 15:14:56 +0000
3742@@ -16,5 +16,5 @@
3743 out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
3744 }
3745
3746-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3747+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3748 /* { dg-final { cleanup-saved-temps } } */
3749
3750=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c'
3751--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-05-24 18:36:31 +0000
3752+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-05-03 15:14:56 +0000
3753@@ -16,5 +16,5 @@
3754 out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
3755 }
3756
3757-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3758+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3759 /* { dg-final { cleanup-saved-temps } } */
3760
3761=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c'
3762--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-05-24 18:36:31 +0000
3763+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-05-03 15:14:56 +0000
3764@@ -16,5 +16,5 @@
3765 out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
3766 }
3767
3768-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3769+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3770 /* { dg-final { cleanup-saved-temps } } */
3771
3772=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c'
3773--- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-05-24 18:36:31 +0000
3774+++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-05-03 15:14:56 +0000
3775@@ -15,5 +15,5 @@
3776 out_float32x2x3_t = vld3_f32 (0);
3777 }
3778
3779-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3780+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3781 /* { dg-final { cleanup-saved-temps } } */
3782
3783=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c'
3784--- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-05-24 18:36:31 +0000
3785+++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-05-03 15:14:56 +0000
3786@@ -15,5 +15,5 @@
3787 out_poly16x4x3_t = vld3_p16 (0);
3788 }
3789
3790-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3791+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3792 /* { dg-final { cleanup-saved-temps } } */
3793
3794=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c'
3795--- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-05-24 18:36:31 +0000
3796+++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-05-03 15:14:56 +0000
3797@@ -15,5 +15,5 @@
3798 out_poly8x8x3_t = vld3_p8 (0);
3799 }
3800
3801-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3802+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3803 /* { dg-final { cleanup-saved-temps } } */
3804
3805=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c'
3806--- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-05-24 18:36:31 +0000
3807+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-05-03 15:14:56 +0000
3808@@ -15,5 +15,5 @@
3809 out_int16x4x3_t = vld3_s16 (0);
3810 }
3811
3812-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3813+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3814 /* { dg-final { cleanup-saved-temps } } */
3815
3816=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c'
3817--- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-05-24 18:36:31 +0000
3818+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-05-03 15:14:56 +0000
3819@@ -15,5 +15,5 @@
3820 out_int32x2x3_t = vld3_s32 (0);
3821 }
3822
3823-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3824+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3825 /* { dg-final { cleanup-saved-temps } } */
3826
3827=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c'
3828--- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-05-24 18:36:31 +0000
3829+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-05-03 15:14:56 +0000
3830@@ -15,5 +15,5 @@
3831 out_int64x1x3_t = vld3_s64 (0);
3832 }
3833
3834-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3835+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3836 /* { dg-final { cleanup-saved-temps } } */
3837
3838=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c'
3839--- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-05-24 18:36:31 +0000
3840+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-05-03 15:14:56 +0000
3841@@ -15,5 +15,5 @@
3842 out_int8x8x3_t = vld3_s8 (0);
3843 }
3844
3845-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3846+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3847 /* { dg-final { cleanup-saved-temps } } */
3848
3849=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c'
3850--- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-05-24 18:36:31 +0000
3851+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-05-03 15:14:56 +0000
3852@@ -15,5 +15,5 @@
3853 out_uint16x4x3_t = vld3_u16 (0);
3854 }
3855
3856-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3857+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3858 /* { dg-final { cleanup-saved-temps } } */
3859
3860=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c'
3861--- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-05-24 18:36:31 +0000
3862+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-05-03 15:14:56 +0000
3863@@ -15,5 +15,5 @@
3864 out_uint32x2x3_t = vld3_u32 (0);
3865 }
3866
3867-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3868+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3869 /* { dg-final { cleanup-saved-temps } } */
3870
3871=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c'
3872--- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-05-24 18:36:31 +0000
3873+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-05-03 15:14:56 +0000
3874@@ -15,5 +15,5 @@
3875 out_uint64x1x3_t = vld3_u64 (0);
3876 }
3877
3878-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3879+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3880 /* { dg-final { cleanup-saved-temps } } */
3881
3882=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c'
3883--- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-05-24 18:36:31 +0000
3884+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-05-03 15:14:56 +0000
3885@@ -15,5 +15,5 @@
3886 out_uint8x8x3_t = vld3_u8 (0);
3887 }
3888
3889-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3890+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3891 /* { dg-final { cleanup-saved-temps } } */
3892
3893=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c'
3894--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-05-24 18:36:31 +0000
3895+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-05-03 15:14:56 +0000
3896@@ -16,5 +16,5 @@
3897 out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
3898 }
3899
3900-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3901+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3902 /* { dg-final { cleanup-saved-temps } } */
3903
3904=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c'
3905--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-05-24 18:36:31 +0000
3906+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-05-03 15:14:56 +0000
3907@@ -16,5 +16,5 @@
3908 out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
3909 }
3910
3911-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3912+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3913 /* { dg-final { cleanup-saved-temps } } */
3914
3915=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c'
3916--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-05-24 18:36:31 +0000
3917+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-05-03 15:14:56 +0000
3918@@ -16,5 +16,5 @@
3919 out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
3920 }
3921
3922-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3923+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3924 /* { dg-final { cleanup-saved-temps } } */
3925
3926=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c'
3927--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-05-24 18:36:31 +0000
3928+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-05-03 15:14:56 +0000
3929@@ -16,5 +16,5 @@
3930 out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
3931 }
3932
3933-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3934+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3935 /* { dg-final { cleanup-saved-temps } } */
3936
3937=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c'
3938--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-05-24 18:36:31 +0000
3939+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-05-03 15:14:56 +0000
3940@@ -16,5 +16,5 @@
3941 out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
3942 }
3943
3944-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3945+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3946 /* { dg-final { cleanup-saved-temps } } */
3947
3948=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c'
3949--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-05-24 18:36:31 +0000
3950+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-05-03 15:14:56 +0000
3951@@ -16,5 +16,5 @@
3952 out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
3953 }
3954
3955-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3956+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3957 /* { dg-final { cleanup-saved-temps } } */
3958
3959=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c'
3960--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-05-24 18:36:31 +0000
3961+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-05-03 15:14:56 +0000
3962@@ -15,6 +15,6 @@
3963 out_float32x4x4_t = vld4q_f32 (0);
3964 }
3965
3966-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3967-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3968+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3969+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3970 /* { dg-final { cleanup-saved-temps } } */
3971
3972=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c'
3973--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-05-24 18:36:31 +0000
3974+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-05-03 15:14:56 +0000
3975@@ -15,6 +15,6 @@
3976 out_poly16x8x4_t = vld4q_p16 (0);
3977 }
3978
3979-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3980-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3981+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3982+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3983 /* { dg-final { cleanup-saved-temps } } */
3984
3985=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c'
3986--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-05-24 18:36:31 +0000
3987+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-05-03 15:14:56 +0000
3988@@ -15,6 +15,6 @@
3989 out_poly8x16x4_t = vld4q_p8 (0);
3990 }
3991
3992-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3993-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3994+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3995+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3996 /* { dg-final { cleanup-saved-temps } } */
3997
3998=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c'
3999--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-05-24 18:36:31 +0000
4000+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-05-03 15:14:56 +0000
4001@@ -15,6 +15,6 @@
4002 out_int16x8x4_t = vld4q_s16 (0);
4003 }
4004
4005-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4006-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4007+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4008+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4009 /* { dg-final { cleanup-saved-temps } } */
4010
4011=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c'
4012--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-05-24 18:36:31 +0000
4013+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-05-03 15:14:56 +0000
4014@@ -15,6 +15,6 @@
4015 out_int32x4x4_t = vld4q_s32 (0);
4016 }
4017
4018-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4019-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4020+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4021+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4022 /* { dg-final { cleanup-saved-temps } } */
4023
4024=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c'
4025--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-05-24 18:36:31 +0000
4026+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-05-03 15:14:56 +0000
4027@@ -15,6 +15,6 @@
4028 out_int8x16x4_t = vld4q_s8 (0);
4029 }
4030
4031-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4032-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4033+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4034+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4035 /* { dg-final { cleanup-saved-temps } } */
4036
4037=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c'
4038--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-05-24 18:36:31 +0000
4039+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-05-03 15:14:56 +0000
4040@@ -15,6 +15,6 @@
4041 out_uint16x8x4_t = vld4q_u16 (0);
4042 }
4043
4044-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4045-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4046+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4047+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4048 /* { dg-final { cleanup-saved-temps } } */
4049
4050=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c'
4051--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-05-24 18:36:31 +0000
4052+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-05-03 15:14:56 +0000
4053@@ -15,6 +15,6 @@
4054 out_uint32x4x4_t = vld4q_u32 (0);
4055 }
4056
4057-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4058-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4059+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4060+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4061 /* { dg-final { cleanup-saved-temps } } */
4062
4063=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c'
4064--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-05-24 18:36:31 +0000
4065+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-05-03 15:14:56 +0000
4066@@ -15,6 +15,6 @@
4067 out_uint8x16x4_t = vld4q_u8 (0);
4068 }
4069
4070-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4071-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4072+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4073+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4074 /* { dg-final { cleanup-saved-temps } } */
4075
4076=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c'
4077--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-05-24 18:36:31 +0000
4078+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-05-03 15:14:56 +0000
4079@@ -15,5 +15,5 @@
4080 out_float32x2x4_t = vld4_dup_f32 (0);
4081 }
4082
4083-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4084+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4085 /* { dg-final { cleanup-saved-temps } } */
4086
4087=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c'
4088--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-05-24 18:36:31 +0000
4089+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-05-03 15:14:56 +0000
4090@@ -15,5 +15,5 @@
4091 out_poly16x4x4_t = vld4_dup_p16 (0);
4092 }
4093
4094-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4095+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4096 /* { dg-final { cleanup-saved-temps } } */
4097
4098=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c'
4099--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-05-24 18:36:31 +0000
4100+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-05-03 15:14:56 +0000
4101@@ -15,5 +15,5 @@
4102 out_poly8x8x4_t = vld4_dup_p8 (0);
4103 }
4104
4105-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4106+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4107 /* { dg-final { cleanup-saved-temps } } */
4108
4109=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c'
4110--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-05-24 18:36:31 +0000
4111+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-05-03 15:14:56 +0000
4112@@ -15,5 +15,5 @@
4113 out_int16x4x4_t = vld4_dup_s16 (0);
4114 }
4115
4116-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4117+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4118 /* { dg-final { cleanup-saved-temps } } */
4119
4120=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c'
4121--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-05-24 18:36:31 +0000
4122+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-05-03 15:14:56 +0000
4123@@ -15,5 +15,5 @@
4124 out_int32x2x4_t = vld4_dup_s32 (0);
4125 }
4126
4127-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4128+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4129 /* { dg-final { cleanup-saved-temps } } */
4130
4131=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c'
4132--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-05-24 18:36:31 +0000
4133+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-05-03 15:14:56 +0000
4134@@ -15,5 +15,5 @@
4135 out_int64x1x4_t = vld4_dup_s64 (0);
4136 }
4137
4138-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4139+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4140 /* { dg-final { cleanup-saved-temps } } */
4141
4142=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c'
4143--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-05-24 18:36:31 +0000
4144+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-05-03 15:14:56 +0000
4145@@ -15,5 +15,5 @@
4146 out_int8x8x4_t = vld4_dup_s8 (0);
4147 }
4148
4149-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4150+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4151 /* { dg-final { cleanup-saved-temps } } */
4152
4153=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c'
4154--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-05-24 18:36:31 +0000
4155+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-05-03 15:14:56 +0000
4156@@ -15,5 +15,5 @@
4157 out_uint16x4x4_t = vld4_dup_u16 (0);
4158 }
4159
4160-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4161+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4162 /* { dg-final { cleanup-saved-temps } } */
4163
4164=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c'
4165--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-05-24 18:36:31 +0000
4166+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-05-03 15:14:56 +0000
4167@@ -15,5 +15,5 @@
4168 out_uint32x2x4_t = vld4_dup_u32 (0);
4169 }
4170
4171-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4172+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4173 /* { dg-final { cleanup-saved-temps } } */
4174
4175=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c'
4176--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-05-24 18:36:31 +0000
4177+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-05-03 15:14:56 +0000
4178@@ -15,5 +15,5 @@
4179 out_uint64x1x4_t = vld4_dup_u64 (0);
4180 }
4181
4182-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4183+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4184 /* { dg-final { cleanup-saved-temps } } */
4185
4186=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c'
4187--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-05-24 18:36:31 +0000
4188+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-05-03 15:14:56 +0000
4189@@ -15,5 +15,5 @@
4190 out_uint8x8x4_t = vld4_dup_u8 (0);
4191 }
4192
4193-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4194+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4195 /* { dg-final { cleanup-saved-temps } } */
4196
4197=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c'
4198--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-05-24 18:36:31 +0000
4199+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-05-03 15:14:56 +0000
4200@@ -16,5 +16,5 @@
4201 out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
4202 }
4203
4204-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4205+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4206 /* { dg-final { cleanup-saved-temps } } */
4207
4208=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c'
4209--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-05-24 18:36:31 +0000
4210+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-05-03 15:14:56 +0000
4211@@ -16,5 +16,5 @@
4212 out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
4213 }
4214
4215-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4216+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4217 /* { dg-final { cleanup-saved-temps } } */
4218
4219=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c'
4220--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-05-24 18:36:31 +0000
4221+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-05-03 15:14:56 +0000
4222@@ -16,5 +16,5 @@
4223 out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
4224 }
4225
4226-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4227+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4228 /* { dg-final { cleanup-saved-temps } } */
4229
4230=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c'
4231--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-05-24 18:36:31 +0000
4232+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-05-03 15:14:56 +0000
4233@@ -16,5 +16,5 @@
4234 out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
4235 }
4236
4237-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4238+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4239 /* { dg-final { cleanup-saved-temps } } */
4240
4241=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c'
4242--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-05-24 18:36:31 +0000
4243+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-05-03 15:14:56 +0000
4244@@ -16,5 +16,5 @@
4245 out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
4246 }
4247
4248-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4249+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4250 /* { dg-final { cleanup-saved-temps } } */
4251
4252=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c'
4253--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-05-24 18:36:31 +0000
4254+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-05-03 15:14:56 +0000
4255@@ -16,5 +16,5 @@
4256 out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
4257 }
4258
4259-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4260+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4261 /* { dg-final { cleanup-saved-temps } } */
4262
4263=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c'
4264--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-05-24 18:36:31 +0000
4265+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-05-03 15:14:56 +0000
4266@@ -16,5 +16,5 @@
4267 out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
4268 }
4269
4270-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4271+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4272 /* { dg-final { cleanup-saved-temps } } */
4273
4274=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c'
4275--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-05-24 18:36:31 +0000
4276+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-05-03 15:14:56 +0000
4277@@ -16,5 +16,5 @@
4278 out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
4279 }
4280
4281-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4282+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4283 /* { dg-final { cleanup-saved-temps } } */
4284
4285=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c'
4286--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-05-24 18:36:31 +0000
4287+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-05-03 15:14:56 +0000
4288@@ -16,5 +16,5 @@
4289 out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
4290 }
4291
4292-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4293+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4294 /* { dg-final { cleanup-saved-temps } } */
4295
4296=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c'
4297--- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-05-24 18:36:31 +0000
4298+++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-05-03 15:14:56 +0000
4299@@ -15,5 +15,5 @@
4300 out_float32x2x4_t = vld4_f32 (0);
4301 }
4302
4303-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4304+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4305 /* { dg-final { cleanup-saved-temps } } */
4306
4307=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c'
4308--- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-05-24 18:36:31 +0000
4309+++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-05-03 15:14:56 +0000
4310@@ -15,5 +15,5 @@
4311 out_poly16x4x4_t = vld4_p16 (0);
4312 }
4313
4314-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4315+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4316 /* { dg-final { cleanup-saved-temps } } */
4317
4318=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c'
4319--- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-05-24 18:36:31 +0000
4320+++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-05-03 15:14:56 +0000
4321@@ -15,5 +15,5 @@
4322 out_poly8x8x4_t = vld4_p8 (0);
4323 }
4324
4325-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4326+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4327 /* { dg-final { cleanup-saved-temps } } */
4328
4329=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c'
4330--- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-05-24 18:36:31 +0000
4331+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-05-03 15:14:56 +0000
4332@@ -15,5 +15,5 @@
4333 out_int16x4x4_t = vld4_s16 (0);
4334 }
4335
4336-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4337+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4338 /* { dg-final { cleanup-saved-temps } } */
4339
4340=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c'
4341--- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-05-24 18:36:31 +0000
4342+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-05-03 15:14:56 +0000
4343@@ -15,5 +15,5 @@
4344 out_int32x2x4_t = vld4_s32 (0);
4345 }
4346
4347-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4348+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4349 /* { dg-final { cleanup-saved-temps } } */
4350
4351=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c'
4352--- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-05-24 18:36:31 +0000
4353+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-05-03 15:14:56 +0000
4354@@ -15,5 +15,5 @@
4355 out_int64x1x4_t = vld4_s64 (0);
4356 }
4357
4358-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4359+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4360 /* { dg-final { cleanup-saved-temps } } */
4361
4362=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c'
4363--- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-05-24 18:36:31 +0000
4364+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-05-03 15:14:56 +0000
4365@@ -15,5 +15,5 @@
4366 out_int8x8x4_t = vld4_s8 (0);
4367 }
4368
4369-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4370+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4371 /* { dg-final { cleanup-saved-temps } } */
4372
4373=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c'
4374--- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-05-24 18:36:31 +0000
4375+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-05-03 15:14:56 +0000
4376@@ -15,5 +15,5 @@
4377 out_uint16x4x4_t = vld4_u16 (0);
4378 }
4379
4380-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4381+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4382 /* { dg-final { cleanup-saved-temps } } */
4383
4384=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c'
4385--- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-05-24 18:36:31 +0000
4386+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-05-03 15:14:56 +0000
4387@@ -15,5 +15,5 @@
4388 out_uint32x2x4_t = vld4_u32 (0);
4389 }
4390
4391-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4392+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4393 /* { dg-final { cleanup-saved-temps } } */
4394
4395=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c'
4396--- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-05-24 18:36:31 +0000
4397+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-05-03 15:14:56 +0000
4398@@ -15,5 +15,5 @@
4399 out_uint64x1x4_t = vld4_u64 (0);
4400 }
4401
4402-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4403+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4404 /* { dg-final { cleanup-saved-temps } } */
4405
4406=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c'
4407--- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-05-24 18:36:31 +0000
4408+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-05-03 15:14:56 +0000
4409@@ -15,5 +15,5 @@
4410 out_uint8x8x4_t = vld4_u8 (0);
4411 }
4412
4413-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4414+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4415 /* { dg-final { cleanup-saved-temps } } */
4416
4417=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c'
4418--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-05-24 18:36:31 +0000
4419+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-05-03 15:14:56 +0000
4420@@ -16,5 +16,5 @@
4421 vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
4422 }
4423
4424-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4425+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4426 /* { dg-final { cleanup-saved-temps } } */
4427
4428=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c'
4429--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-05-24 18:36:31 +0000
4430+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-05-03 15:14:56 +0000
4431@@ -16,5 +16,5 @@
4432 vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
4433 }
4434
4435-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4436+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4437 /* { dg-final { cleanup-saved-temps } } */
4438
4439=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c'
4440--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-05-24 18:36:31 +0000
4441+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-05-03 15:14:56 +0000
4442@@ -16,5 +16,5 @@
4443 vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
4444 }
4445
4446-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4447+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4448 /* { dg-final { cleanup-saved-temps } } */
4449
4450=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c'
4451--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-05-24 18:36:31 +0000
4452+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-05-03 15:14:56 +0000
4453@@ -16,5 +16,5 @@
4454 vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
4455 }
4456
4457-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4458+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4459 /* { dg-final { cleanup-saved-temps } } */
4460
4461=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c'
4462--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-05-24 18:36:31 +0000
4463+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-05-03 15:14:56 +0000
4464@@ -16,5 +16,5 @@
4465 vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
4466 }
4467
4468-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4469+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4470 /* { dg-final { cleanup-saved-temps } } */
4471
4472=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c'
4473--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-05-24 18:36:31 +0000
4474+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-05-03 15:14:56 +0000
4475@@ -16,5 +16,5 @@
4476 vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
4477 }
4478
4479-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4480+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4481 /* { dg-final { cleanup-saved-temps } } */
4482
4483=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c'
4484--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-05-24 18:36:31 +0000
4485+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-05-03 15:14:56 +0000
4486@@ -16,5 +16,5 @@
4487 vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
4488 }
4489
4490-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4491+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4492 /* { dg-final { cleanup-saved-temps } } */
4493
4494=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c'
4495--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-05-24 18:36:31 +0000
4496+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-05-03 15:14:56 +0000
4497@@ -16,5 +16,5 @@
4498 vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
4499 }
4500
4501-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4502+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4503 /* { dg-final { cleanup-saved-temps } } */
4504
4505=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c'
4506--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-05-24 18:36:31 +0000
4507+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-05-03 15:14:56 +0000
4508@@ -16,5 +16,5 @@
4509 vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
4510 }
4511
4512-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4513+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4514 /* { dg-final { cleanup-saved-temps } } */
4515
4516=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c'
4517--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-05-24 18:36:31 +0000
4518+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-05-03 15:14:56 +0000
4519@@ -16,5 +16,5 @@
4520 vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
4521 }
4522
4523-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4524+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4525 /* { dg-final { cleanup-saved-temps } } */
4526
4527=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c'
4528--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-05-24 18:36:31 +0000
4529+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-05-03 15:14:56 +0000
4530@@ -16,5 +16,5 @@
4531 vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
4532 }
4533
4534-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4535+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4536 /* { dg-final { cleanup-saved-temps } } */
4537
4538=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c'
4539--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-05-24 18:36:31 +0000
4540+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-05-03 15:14:56 +0000
4541@@ -16,5 +16,5 @@
4542 vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
4543 }
4544
4545-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4546+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4547 /* { dg-final { cleanup-saved-temps } } */
4548
4549=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c'
4550--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-05-24 18:36:31 +0000
4551+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-05-03 15:14:56 +0000
4552@@ -16,5 +16,5 @@
4553 vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
4554 }
4555
4556-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4557+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4558 /* { dg-final { cleanup-saved-temps } } */
4559
4560=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c'
4561--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-05-24 18:36:31 +0000
4562+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-05-03 15:14:56 +0000
4563@@ -16,5 +16,5 @@
4564 vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
4565 }
4566
4567-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4568+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4569 /* { dg-final { cleanup-saved-temps } } */
4570
4571=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c'
4572--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-05-24 18:36:31 +0000
4573+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-05-03 15:14:56 +0000
4574@@ -16,5 +16,5 @@
4575 vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
4576 }
4577
4578-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4579+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4580 /* { dg-final { cleanup-saved-temps } } */
4581
4582=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c'
4583--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-05-24 18:36:31 +0000
4584+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-05-03 15:14:56 +0000
4585@@ -16,5 +16,5 @@
4586 vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
4587 }
4588
4589-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4590+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4591 /* { dg-final { cleanup-saved-temps } } */
4592
4593=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c'
4594--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-05-24 18:36:31 +0000
4595+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-05-03 15:14:56 +0000
4596@@ -16,5 +16,5 @@
4597 vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
4598 }
4599
4600-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4601+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4602 /* { dg-final { cleanup-saved-temps } } */
4603
4604=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c'
4605--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-05-24 18:36:31 +0000
4606+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-05-03 15:14:56 +0000
4607@@ -16,5 +16,5 @@
4608 vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
4609 }
4610
4611-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4612+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4613 /* { dg-final { cleanup-saved-temps } } */
4614
4615=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c'
4616--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-05-24 18:36:31 +0000
4617+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-05-03 15:14:56 +0000
4618@@ -16,5 +16,5 @@
4619 vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
4620 }
4621
4622-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4623+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4624 /* { dg-final { cleanup-saved-temps } } */
4625
4626=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c'
4627--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-05-24 18:36:31 +0000
4628+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-05-03 15:14:56 +0000
4629@@ -16,5 +16,5 @@
4630 vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
4631 }
4632
4633-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4634+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4635 /* { dg-final { cleanup-saved-temps } } */
4636
4637=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c'
4638--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-05-24 18:36:31 +0000
4639+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-05-03 15:14:56 +0000
4640@@ -16,5 +16,5 @@
4641 vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
4642 }
4643
4644-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4645+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4646 /* { dg-final { cleanup-saved-temps } } */
4647
4648=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c'
4649--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-05-24 18:36:31 +0000
4650+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-05-03 15:14:56 +0000
4651@@ -16,5 +16,5 @@
4652 vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
4653 }
4654
4655-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4656+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4657 /* { dg-final { cleanup-saved-temps } } */
4658
4659=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c'
4660--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-05-24 18:36:31 +0000
4661+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-05-03 15:14:56 +0000
4662@@ -16,5 +16,5 @@
4663 vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
4664 }
4665
4666-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4667+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4668 /* { dg-final { cleanup-saved-temps } } */
4669
4670=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c'
4671--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-05-24 18:36:31 +0000
4672+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-05-03 15:14:56 +0000
4673@@ -16,5 +16,5 @@
4674 vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
4675 }
4676
4677-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4678+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4679 /* { dg-final { cleanup-saved-temps } } */
4680
4681=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c'
4682--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-05-24 18:36:31 +0000
4683+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-05-03 15:14:56 +0000
4684@@ -16,5 +16,5 @@
4685 vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
4686 }
4687
4688-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4689+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4690 /* { dg-final { cleanup-saved-temps } } */
4691
4692=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c'
4693--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-05-24 18:36:31 +0000
4694+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-05-03 15:14:56 +0000
4695@@ -16,5 +16,5 @@
4696 vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
4697 }
4698
4699-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4700+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4701 /* { dg-final { cleanup-saved-temps } } */
4702
4703=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c'
4704--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-05-24 18:36:31 +0000
4705+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-05-03 15:14:56 +0000
4706@@ -16,5 +16,5 @@
4707 vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
4708 }
4709
4710-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4711+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4712 /* { dg-final { cleanup-saved-temps } } */
4713
4714=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c'
4715--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-05-24 18:36:31 +0000
4716+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-05-03 15:14:56 +0000
4717@@ -16,5 +16,5 @@
4718 vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
4719 }
4720
4721-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4722+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4723 /* { dg-final { cleanup-saved-temps } } */
4724
4725=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c'
4726--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-05-24 18:36:31 +0000
4727+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-05-03 15:14:56 +0000
4728@@ -16,5 +16,5 @@
4729 vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
4730 }
4731
4732-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4733+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4734 /* { dg-final { cleanup-saved-temps } } */
4735
4736=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c'
4737--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-05-24 18:36:31 +0000
4738+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-05-03 15:14:56 +0000
4739@@ -16,5 +16,5 @@
4740 vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
4741 }
4742
4743-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4744+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4745 /* { dg-final { cleanup-saved-temps } } */
4746
4747=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c'
4748--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-05-24 18:36:31 +0000
4749+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-05-03 15:14:56 +0000
4750@@ -16,5 +16,5 @@
4751 vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
4752 }
4753
4754-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4755+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4756 /* { dg-final { cleanup-saved-temps } } */
4757
4758=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c'
4759--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-05-24 18:36:31 +0000
4760+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-05-03 15:14:56 +0000
4761@@ -16,5 +16,5 @@
4762 vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
4763 }
4764
4765-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4766+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4767 /* { dg-final { cleanup-saved-temps } } */
4768
4769=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c'
4770--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-05-24 18:36:31 +0000
4771+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-05-03 15:14:56 +0000
4772@@ -16,5 +16,5 @@
4773 vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
4774 }
4775
4776-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4777+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4778 /* { dg-final { cleanup-saved-temps } } */
4779
4780=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c'
4781--- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-05-24 18:36:31 +0000
4782+++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-05-03 15:14:56 +0000
4783@@ -16,5 +16,5 @@
4784 vst1_f32 (arg0_float32_t, arg1_float32x2_t);
4785 }
4786
4787-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4788+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4789 /* { dg-final { cleanup-saved-temps } } */
4790
4791=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c'
4792--- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-05-24 18:36:31 +0000
4793+++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-05-03 15:14:56 +0000
4794@@ -16,5 +16,5 @@
4795 vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
4796 }
4797
4798-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4799+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4800 /* { dg-final { cleanup-saved-temps } } */
4801
4802=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c'
4803--- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-05-24 18:36:31 +0000
4804+++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-05-03 15:14:56 +0000
4805@@ -16,5 +16,5 @@
4806 vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
4807 }
4808
4809-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4810+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4811 /* { dg-final { cleanup-saved-temps } } */
4812
4813=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c'
4814--- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-05-24 18:36:31 +0000
4815+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-05-03 15:14:56 +0000
4816@@ -16,5 +16,5 @@
4817 vst1_s16 (arg0_int16_t, arg1_int16x4_t);
4818 }
4819
4820-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4821+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4822 /* { dg-final { cleanup-saved-temps } } */
4823
4824=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c'
4825--- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-05-24 18:36:31 +0000
4826+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-05-03 15:14:56 +0000
4827@@ -16,5 +16,5 @@
4828 vst1_s32 (arg0_int32_t, arg1_int32x2_t);
4829 }
4830
4831-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4832+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4833 /* { dg-final { cleanup-saved-temps } } */
4834
4835=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c'
4836--- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-05-24 18:36:31 +0000
4837+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-05-03 15:14:56 +0000
4838@@ -16,5 +16,5 @@
4839 vst1_s64 (arg0_int64_t, arg1_int64x1_t);
4840 }
4841
4842-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4843+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4844 /* { dg-final { cleanup-saved-temps } } */
4845
4846=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c'
4847--- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-05-24 18:36:31 +0000
4848+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-05-03 15:14:56 +0000
4849@@ -16,5 +16,5 @@
4850 vst1_s8 (arg0_int8_t, arg1_int8x8_t);
4851 }
4852
4853-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4854+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4855 /* { dg-final { cleanup-saved-temps } } */
4856
4857=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c'
4858--- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-05-24 18:36:31 +0000
4859+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-05-03 15:14:56 +0000
4860@@ -16,5 +16,5 @@
4861 vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
4862 }
4863
4864-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4865+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4866 /* { dg-final { cleanup-saved-temps } } */
4867
4868=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c'
4869--- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-05-24 18:36:31 +0000
4870+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-05-03 15:14:56 +0000
4871@@ -16,5 +16,5 @@
4872 vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
4873 }
4874
4875-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4876+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4877 /* { dg-final { cleanup-saved-temps } } */
4878
4879=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c'
4880--- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-05-24 18:36:31 +0000
4881+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-05-03 15:14:56 +0000
4882@@ -16,5 +16,5 @@
4883 vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
4884 }
4885
4886-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4887+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4888 /* { dg-final { cleanup-saved-temps } } */
4889
4890=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c'
4891--- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-05-24 18:36:31 +0000
4892+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-05-03 15:14:56 +0000
4893@@ -16,5 +16,5 @@
4894 vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
4895 }
4896
4897-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4898+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4899 /* { dg-final { cleanup-saved-temps } } */
4900
4901=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c'
4902--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-05-24 18:36:31 +0000
4903+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-05-03 15:14:56 +0000
4904@@ -16,5 +16,5 @@
4905 vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
4906 }
4907
4908-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4909+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4910 /* { dg-final { cleanup-saved-temps } } */
4911
4912=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c'
4913--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-05-24 18:36:31 +0000
4914+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-05-03 15:14:56 +0000
4915@@ -16,5 +16,5 @@
4916 vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
4917 }
4918
4919-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4920+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4921 /* { dg-final { cleanup-saved-temps } } */
4922
4923=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c'
4924--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-05-24 18:36:31 +0000
4925+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-05-03 15:14:56 +0000
4926@@ -16,5 +16,5 @@
4927 vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
4928 }
4929
4930-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4931+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4932 /* { dg-final { cleanup-saved-temps } } */
4933
4934=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c'
4935--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-05-24 18:36:31 +0000
4936+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-05-03 15:14:56 +0000
4937@@ -16,5 +16,5 @@
4938 vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
4939 }
4940
4941-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4942+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4943 /* { dg-final { cleanup-saved-temps } } */
4944
4945=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c'
4946--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-05-24 18:36:31 +0000
4947+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-05-03 15:14:56 +0000
4948@@ -16,5 +16,5 @@
4949 vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
4950 }
4951
4952-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4953+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4954 /* { dg-final { cleanup-saved-temps } } */
4955
4956=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c'
4957--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-05-24 18:36:31 +0000
4958+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-05-03 15:14:56 +0000
4959@@ -16,5 +16,5 @@
4960 vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
4961 }
4962
4963-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4964+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4965 /* { dg-final { cleanup-saved-temps } } */
4966
4967=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c'
4968--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-05-24 18:36:31 +0000
4969+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-05-03 15:14:56 +0000
4970@@ -16,6 +16,6 @@
4971 vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
4972 }
4973
4974-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4975-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4976+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4977+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4978 /* { dg-final { cleanup-saved-temps } } */
4979
4980=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c'
4981--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-05-24 18:36:31 +0000
4982+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-05-03 15:14:56 +0000
4983@@ -16,6 +16,6 @@
4984 vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
4985 }
4986
4987-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4988-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4989+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4990+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4991 /* { dg-final { cleanup-saved-temps } } */
4992
4993=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c'
4994--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-05-24 18:36:31 +0000
4995+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-05-03 15:14:56 +0000
4996@@ -16,6 +16,6 @@
4997 vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
4998 }
4999
5000-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5001-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5002+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5003+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5004 /* { dg-final { cleanup-saved-temps } } */
5005
5006=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c'
5007--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-05-24 18:36:31 +0000
5008+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-05-03 15:14:56 +0000
5009@@ -16,6 +16,6 @@
5010 vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
5011 }
5012
5013-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5014-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5015+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5016+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5017 /* { dg-final { cleanup-saved-temps } } */
5018
5019=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c'
5020--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-05-24 18:36:31 +0000
5021+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-05-03 15:14:56 +0000
5022@@ -16,6 +16,6 @@
5023 vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
5024 }
5025
5026-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5027-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5028+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5029+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5030 /* { dg-final { cleanup-saved-temps } } */
5031
5032=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c'
5033--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-05-24 18:36:31 +0000
5034+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-05-03 15:14:56 +0000
5035@@ -16,6 +16,6 @@
5036 vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
5037 }
5038
5039-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5040-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5041+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5042+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5043 /* { dg-final { cleanup-saved-temps } } */
5044
5045=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c'
5046--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-05-24 18:36:31 +0000
5047+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-05-03 15:14:56 +0000
5048@@ -16,6 +16,6 @@
5049 vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
5050 }
5051
5052-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5053-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5054+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5055+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5056 /* { dg-final { cleanup-saved-temps } } */
5057
5058=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c'
5059--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-05-24 18:36:31 +0000
5060+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-05-03 15:14:56 +0000
5061@@ -16,6 +16,6 @@
5062 vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
5063 }
5064
5065-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5066-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5067+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5068+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5069 /* { dg-final { cleanup-saved-temps } } */
5070
5071=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c'
5072--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-05-24 18:36:31 +0000
5073+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-05-03 15:14:56 +0000
5074@@ -16,6 +16,6 @@
5075 vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
5076 }
5077
5078-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5079-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5080+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5081+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5082 /* { dg-final { cleanup-saved-temps } } */
5083
5084=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c'
5085--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-05-24 18:36:31 +0000
5086+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-05-03 15:14:56 +0000
5087@@ -16,5 +16,5 @@
5088 vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
5089 }
5090
5091-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5092+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5093 /* { dg-final { cleanup-saved-temps } } */
5094
5095=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c'
5096--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-05-24 18:36:31 +0000
5097+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-05-03 15:14:56 +0000
5098@@ -16,5 +16,5 @@
5099 vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
5100 }
5101
5102-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5103+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5104 /* { dg-final { cleanup-saved-temps } } */
5105
5106=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c'
5107--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-05-24 18:36:31 +0000
5108+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-05-03 15:14:56 +0000
5109@@ -16,5 +16,5 @@
5110 vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
5111 }
5112
5113-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5114+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5115 /* { dg-final { cleanup-saved-temps } } */
5116
5117=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c'
5118--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-05-24 18:36:31 +0000
5119+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-05-03 15:14:56 +0000
5120@@ -16,5 +16,5 @@
5121 vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
5122 }
5123
5124-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5125+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5126 /* { dg-final { cleanup-saved-temps } } */
5127
5128=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c'
5129--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-05-24 18:36:31 +0000
5130+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-05-03 15:14:56 +0000
5131@@ -16,5 +16,5 @@
5132 vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
5133 }
5134
5135-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5136+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5137 /* { dg-final { cleanup-saved-temps } } */
5138
5139=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c'
5140--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-05-24 18:36:31 +0000
5141+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-05-03 15:14:56 +0000
5142@@ -16,5 +16,5 @@
5143 vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
5144 }
5145
5146-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5147+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5148 /* { dg-final { cleanup-saved-temps } } */
5149
5150=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c'
5151--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-05-24 18:36:31 +0000
5152+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-05-03 15:14:56 +0000
5153@@ -16,5 +16,5 @@
5154 vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
5155 }
5156
5157-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5158+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5159 /* { dg-final { cleanup-saved-temps } } */
5160
5161=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c'
5162--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-05-24 18:36:31 +0000
5163+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-05-03 15:14:56 +0000
5164@@ -16,5 +16,5 @@
5165 vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
5166 }
5167
5168-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5169+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5170 /* { dg-final { cleanup-saved-temps } } */
5171
5172=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c'
5173--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-05-24 18:36:31 +0000
5174+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-05-03 15:14:56 +0000
5175@@ -16,5 +16,5 @@
5176 vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
5177 }
5178
5179-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5180+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5181 /* { dg-final { cleanup-saved-temps } } */
5182
5183=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c'
5184--- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-05-24 18:36:31 +0000
5185+++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-05-03 15:14:56 +0000
5186@@ -16,5 +16,5 @@
5187 vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
5188 }
5189
5190-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5191+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5192 /* { dg-final { cleanup-saved-temps } } */
5193
5194=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c'
5195--- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-05-24 18:36:31 +0000
5196+++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-05-03 15:14:56 +0000
5197@@ -16,5 +16,5 @@
5198 vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
5199 }
5200
5201-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5202+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5203 /* { dg-final { cleanup-saved-temps } } */
5204
5205=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c'
5206--- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-05-24 18:36:31 +0000
5207+++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-05-03 15:14:56 +0000
5208@@ -16,5 +16,5 @@
5209 vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
5210 }
5211
5212-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5213+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5214 /* { dg-final { cleanup-saved-temps } } */
5215
5216=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c'
5217--- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-05-24 18:36:31 +0000
5218+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-05-03 15:14:56 +0000
5219@@ -16,5 +16,5 @@
5220 vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
5221 }
5222
5223-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5224+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5225 /* { dg-final { cleanup-saved-temps } } */
5226
5227=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c'
5228--- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-05-24 18:36:31 +0000
5229+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-05-03 15:14:56 +0000
5230@@ -16,5 +16,5 @@
5231 vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
5232 }
5233
5234-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5235+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5236 /* { dg-final { cleanup-saved-temps } } */
5237
5238=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c'
5239--- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-05-24 18:36:31 +0000
5240+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-05-03 15:14:56 +0000
5241@@ -16,5 +16,5 @@
5242 vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
5243 }
5244
5245-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5246+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5247 /* { dg-final { cleanup-saved-temps } } */
5248
5249=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c'
5250--- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-05-24 18:36:31 +0000
5251+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-05-03 15:14:56 +0000
5252@@ -16,5 +16,5 @@
5253 vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
5254 }
5255
5256-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5257+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5258 /* { dg-final { cleanup-saved-temps } } */
5259
5260=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c'
5261--- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-05-24 18:36:31 +0000
5262+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-05-03 15:14:56 +0000
5263@@ -16,5 +16,5 @@
5264 vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
5265 }
5266
5267-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5268+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5269 /* { dg-final { cleanup-saved-temps } } */
5270
5271=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c'
5272--- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-05-24 18:36:31 +0000
5273+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-05-03 15:14:56 +0000
5274@@ -16,5 +16,5 @@
5275 vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
5276 }
5277
5278-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5279+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5280 /* { dg-final { cleanup-saved-temps } } */
5281
5282=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c'
5283--- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-05-24 18:36:31 +0000
5284+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-05-03 15:14:56 +0000
5285@@ -16,5 +16,5 @@
5286 vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
5287 }
5288
5289-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5290+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5291 /* { dg-final { cleanup-saved-temps } } */
5292
5293=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c'
5294--- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-05-24 18:36:31 +0000
5295+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-05-03 15:14:56 +0000
5296@@ -16,5 +16,5 @@
5297 vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
5298 }
5299
5300-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5301+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5302 /* { dg-final { cleanup-saved-temps } } */
5303
5304=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c'
5305--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-05-24 18:36:31 +0000
5306+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-05-03 15:14:56 +0000
5307@@ -16,5 +16,5 @@
5308 vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
5309 }
5310
5311-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5312+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5313 /* { dg-final { cleanup-saved-temps } } */
5314
5315=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c'
5316--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-05-24 18:36:31 +0000
5317+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-05-03 15:14:56 +0000
5318@@ -16,5 +16,5 @@
5319 vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
5320 }
5321
5322-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5323+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5324 /* { dg-final { cleanup-saved-temps } } */
5325
5326=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c'
5327--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-05-24 18:36:31 +0000
5328+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-05-03 15:14:56 +0000
5329@@ -16,5 +16,5 @@
5330 vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
5331 }
5332
5333-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5334+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5335 /* { dg-final { cleanup-saved-temps } } */
5336
5337=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c'
5338--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-05-24 18:36:31 +0000
5339+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-05-03 15:14:56 +0000
5340@@ -16,5 +16,5 @@
5341 vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
5342 }
5343
5344-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5345+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5346 /* { dg-final { cleanup-saved-temps } } */
5347
5348=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c'
5349--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-05-24 18:36:31 +0000
5350+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-05-03 15:14:56 +0000
5351@@ -16,5 +16,5 @@
5352 vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
5353 }
5354
5355-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5356+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5357 /* { dg-final { cleanup-saved-temps } } */
5358
5359=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c'
5360--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-05-24 18:36:31 +0000
5361+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-05-03 15:14:56 +0000
5362@@ -16,5 +16,5 @@
5363 vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
5364 }
5365
5366-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5367+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5368 /* { dg-final { cleanup-saved-temps } } */
5369
5370=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c'
5371--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-05-24 18:36:31 +0000
5372+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-05-03 15:14:56 +0000
5373@@ -16,6 +16,6 @@
5374 vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
5375 }
5376
5377-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5378-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5379+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5380+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5381 /* { dg-final { cleanup-saved-temps } } */
5382
5383=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c'
5384--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-05-24 18:36:31 +0000
5385+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-05-03 15:14:56 +0000
5386@@ -16,6 +16,6 @@
5387 vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
5388 }
5389
5390-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5391-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5392+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5393+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5394 /* { dg-final { cleanup-saved-temps } } */
5395
5396=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c'
5397--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-05-24 18:36:31 +0000
5398+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-05-03 15:14:56 +0000
5399@@ -16,6 +16,6 @@
5400 vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
5401 }
5402
5403-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5404-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5405+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5406+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5407 /* { dg-final { cleanup-saved-temps } } */
5408
5409=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c'
5410--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-05-24 18:36:31 +0000
5411+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-05-03 15:14:56 +0000
5412@@ -16,6 +16,6 @@
5413 vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
5414 }
5415
5416-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5417-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5418+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5419+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5420 /* { dg-final { cleanup-saved-temps } } */
5421
5422=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c'
5423--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-05-24 18:36:31 +0000
5424+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-05-03 15:14:56 +0000
5425@@ -16,6 +16,6 @@
5426 vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
5427 }
5428
5429-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5430-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5431+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5432+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5433 /* { dg-final { cleanup-saved-temps } } */
5434
5435=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c'
5436--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-05-24 18:36:31 +0000
5437+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-05-03 15:14:56 +0000
5438@@ -16,6 +16,6 @@
5439 vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
5440 }
5441
5442-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5443-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5444+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5445+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5446 /* { dg-final { cleanup-saved-temps } } */
5447
5448=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c'
5449--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-05-24 18:36:31 +0000
5450+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-05-03 15:14:56 +0000
5451@@ -16,6 +16,6 @@
5452 vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
5453 }
5454
5455-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5456-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5457+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5458+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5459 /* { dg-final { cleanup-saved-temps } } */
5460
5461=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c'
5462--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-05-24 18:36:31 +0000
5463+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-05-03 15:14:56 +0000
5464@@ -16,6 +16,6 @@
5465 vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
5466 }
5467
5468-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5469-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5470+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5471+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5472 /* { dg-final { cleanup-saved-temps } } */
5473
5474=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c'
5475--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-05-24 18:36:31 +0000
5476+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-05-03 15:14:56 +0000
5477@@ -16,6 +16,6 @@
5478 vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
5479 }
5480
5481-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5482-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5483+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5484+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5485 /* { dg-final { cleanup-saved-temps } } */
5486
5487=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c'
5488--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-05-24 18:36:31 +0000
5489+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-05-03 15:14:56 +0000
5490@@ -16,5 +16,5 @@
5491 vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
5492 }
5493
5494-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5495+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5496 /* { dg-final { cleanup-saved-temps } } */
5497
5498=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c'
5499--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-05-24 18:36:31 +0000
5500+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-05-03 15:14:56 +0000
5501@@ -16,5 +16,5 @@
5502 vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
5503 }
5504
5505-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5506+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5507 /* { dg-final { cleanup-saved-temps } } */
5508
5509=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c'
5510--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-05-24 18:36:31 +0000
5511+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-05-03 15:14:56 +0000
5512@@ -16,5 +16,5 @@
5513 vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
5514 }
5515
5516-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5517+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5518 /* { dg-final { cleanup-saved-temps } } */
5519
5520=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c'
5521--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-05-24 18:36:31 +0000
5522+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-05-03 15:14:56 +0000
5523@@ -16,5 +16,5 @@
5524 vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
5525 }
5526
5527-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5528+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5529 /* { dg-final { cleanup-saved-temps } } */
5530
5531=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c'
5532--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-05-24 18:36:31 +0000
5533+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-05-03 15:14:56 +0000
5534@@ -16,5 +16,5 @@
5535 vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
5536 }
5537
5538-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5539+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5540 /* { dg-final { cleanup-saved-temps } } */
5541
5542=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c'
5543--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-05-24 18:36:31 +0000
5544+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-05-03 15:14:56 +0000
5545@@ -16,5 +16,5 @@
5546 vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
5547 }
5548
5549-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5550+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5551 /* { dg-final { cleanup-saved-temps } } */
5552
5553=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c'
5554--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-05-24 18:36:31 +0000
5555+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-05-03 15:14:56 +0000
5556@@ -16,5 +16,5 @@
5557 vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
5558 }
5559
5560-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5561+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5562 /* { dg-final { cleanup-saved-temps } } */
5563
5564=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c'
5565--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-05-24 18:36:31 +0000
5566+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-05-03 15:14:56 +0000
5567@@ -16,5 +16,5 @@
5568 vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
5569 }
5570
5571-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5572+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5573 /* { dg-final { cleanup-saved-temps } } */
5574
5575=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c'
5576--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-05-24 18:36:31 +0000
5577+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-05-03 15:14:56 +0000
5578@@ -16,5 +16,5 @@
5579 vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
5580 }
5581
5582-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5583+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5584 /* { dg-final { cleanup-saved-temps } } */
5585
5586=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c'
5587--- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-05-24 18:36:31 +0000
5588+++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-05-03 15:14:56 +0000
5589@@ -16,5 +16,5 @@
5590 vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
5591 }
5592
5593-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5594+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5595 /* { dg-final { cleanup-saved-temps } } */
5596
5597=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c'
5598--- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-05-24 18:36:31 +0000
5599+++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-05-03 15:14:56 +0000
5600@@ -16,5 +16,5 @@
5601 vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
5602 }
5603
5604-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5605+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5606 /* { dg-final { cleanup-saved-temps } } */
5607
5608=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c'
5609--- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-05-24 18:36:31 +0000
5610+++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-05-03 15:14:56 +0000
5611@@ -16,5 +16,5 @@
5612 vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
5613 }
5614
5615-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5616+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5617 /* { dg-final { cleanup-saved-temps } } */
5618
5619=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c'
5620--- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-05-24 18:36:31 +0000
5621+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-05-03 15:14:56 +0000
5622@@ -16,5 +16,5 @@
5623 vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
5624 }
5625
5626-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5627+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5628 /* { dg-final { cleanup-saved-temps } } */
5629
5630=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c'
5631--- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-05-24 18:36:31 +0000
5632+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-05-03 15:14:56 +0000
5633@@ -16,5 +16,5 @@
5634 vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
5635 }
5636
5637-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5638+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5639 /* { dg-final { cleanup-saved-temps } } */
5640
5641=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c'
5642--- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-05-24 18:36:31 +0000
5643+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-05-03 15:14:56 +0000
5644@@ -16,5 +16,5 @@
5645 vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
5646 }
5647
5648-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5649+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5650 /* { dg-final { cleanup-saved-temps } } */
5651
5652=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c'
5653--- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-05-24 18:36:31 +0000
5654+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-05-03 15:14:56 +0000
5655@@ -16,5 +16,5 @@
5656 vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
5657 }
5658
5659-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5660+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5661 /* { dg-final { cleanup-saved-temps } } */
5662
5663=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c'
5664--- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-05-24 18:36:31 +0000
5665+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-05-03 15:14:56 +0000
5666@@ -16,5 +16,5 @@
5667 vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
5668 }
5669
5670-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5671+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5672 /* { dg-final { cleanup-saved-temps } } */
5673
5674=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c'
5675--- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-05-24 18:36:31 +0000
5676+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-05-03 15:14:56 +0000
5677@@ -16,5 +16,5 @@
5678 vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
5679 }
5680
5681-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5682+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5683 /* { dg-final { cleanup-saved-temps } } */
5684
5685=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c'
5686--- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-05-24 18:36:31 +0000
5687+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-05-03 15:14:56 +0000
5688@@ -16,5 +16,5 @@
5689 vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
5690 }
5691
5692-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5693+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5694 /* { dg-final { cleanup-saved-temps } } */
5695
5696=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c'
5697--- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-05-24 18:36:31 +0000
5698+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-05-03 15:14:56 +0000
5699@@ -16,5 +16,5 @@
5700 vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
5701 }
5702
5703-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5704+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5705 /* { dg-final { cleanup-saved-temps } } */
5706
5707=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c'
5708--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-05-24 18:36:31 +0000
5709+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-05-03 15:14:56 +0000
5710@@ -16,5 +16,5 @@
5711 vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
5712 }
5713
5714-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5715+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5716 /* { dg-final { cleanup-saved-temps } } */
5717
5718=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c'
5719--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-05-24 18:36:31 +0000
5720+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-05-03 15:14:56 +0000
5721@@ -16,5 +16,5 @@
5722 vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
5723 }
5724
5725-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5726+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5727 /* { dg-final { cleanup-saved-temps } } */
5728
5729=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c'
5730--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-05-24 18:36:31 +0000
5731+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-05-03 15:14:56 +0000
5732@@ -16,5 +16,5 @@
5733 vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
5734 }
5735
5736-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5737+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5738 /* { dg-final { cleanup-saved-temps } } */
5739
5740=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c'
5741--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-05-24 18:36:31 +0000
5742+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-05-03 15:14:56 +0000
5743@@ -16,5 +16,5 @@
5744 vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
5745 }
5746
5747-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5748+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5749 /* { dg-final { cleanup-saved-temps } } */
5750
5751=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c'
5752--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-05-24 18:36:31 +0000
5753+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-05-03 15:14:56 +0000
5754@@ -16,5 +16,5 @@
5755 vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
5756 }
5757
5758-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5759+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5760 /* { dg-final { cleanup-saved-temps } } */
5761
5762=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c'
5763--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-05-24 18:36:31 +0000
5764+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-05-03 15:14:56 +0000
5765@@ -16,5 +16,5 @@
5766 vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
5767 }
5768
5769-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5770+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5771 /* { dg-final { cleanup-saved-temps } } */
5772
5773=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c'
5774--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-05-24 18:36:31 +0000
5775+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-05-03 15:14:56 +0000
5776@@ -16,6 +16,6 @@
5777 vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
5778 }
5779
5780-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5781-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5782+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5783+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5784 /* { dg-final { cleanup-saved-temps } } */
5785
5786=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c'
5787--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-05-24 18:36:31 +0000
5788+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-05-03 15:14:56 +0000
5789@@ -16,6 +16,6 @@
5790 vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
5791 }
5792
5793-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5794-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5795+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5796+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5797 /* { dg-final { cleanup-saved-temps } } */
5798
5799=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c'
5800--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-05-24 18:36:31 +0000
5801+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-05-03 15:14:56 +0000
5802@@ -16,6 +16,6 @@
5803 vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
5804 }
5805
5806-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5807-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5808+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5809+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5810 /* { dg-final { cleanup-saved-temps } } */
5811
5812=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c'
5813--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-05-24 18:36:31 +0000
5814+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-05-03 15:14:56 +0000
5815@@ -16,6 +16,6 @@
5816 vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
5817 }
5818
5819-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5820-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5821+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5822+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5823 /* { dg-final { cleanup-saved-temps } } */
5824
5825=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c'
5826--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-05-24 18:36:31 +0000
5827+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-05-03 15:14:56 +0000
5828@@ -16,6 +16,6 @@
5829 vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
5830 }
5831
5832-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5833-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5834+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5835+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5836 /* { dg-final { cleanup-saved-temps } } */
5837
5838=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c'
5839--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-05-24 18:36:31 +0000
5840+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-05-03 15:14:56 +0000
5841@@ -16,6 +16,6 @@
5842 vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
5843 }
5844
5845-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5846-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5847+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5848+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5849 /* { dg-final { cleanup-saved-temps } } */
5850
5851=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c'
5852--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-05-24 18:36:31 +0000
5853+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-05-03 15:14:56 +0000
5854@@ -16,6 +16,6 @@
5855 vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
5856 }
5857
5858-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5859-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5860+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5861+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5862 /* { dg-final { cleanup-saved-temps } } */
5863
5864=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c'
5865--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-05-24 18:36:31 +0000
5866+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-05-03 15:14:56 +0000
5867@@ -16,6 +16,6 @@
5868 vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
5869 }
5870
5871-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5872-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5873+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5874+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5875 /* { dg-final { cleanup-saved-temps } } */
5876
5877=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c'
5878--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-05-24 18:36:31 +0000
5879+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-05-03 15:14:56 +0000
5880@@ -16,6 +16,6 @@
5881 vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
5882 }
5883
5884-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5885-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5886+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5887+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5888 /* { dg-final { cleanup-saved-temps } } */
5889
5890=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c'
5891--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-05-24 18:36:31 +0000
5892+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-05-03 15:14:56 +0000
5893@@ -16,5 +16,5 @@
5894 vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
5895 }
5896
5897-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5898+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5899 /* { dg-final { cleanup-saved-temps } } */
5900
5901=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c'
5902--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-05-24 18:36:31 +0000
5903+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-05-03 15:14:56 +0000
5904@@ -16,5 +16,5 @@
5905 vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
5906 }
5907
5908-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5909+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5910 /* { dg-final { cleanup-saved-temps } } */
5911
5912=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c'
5913--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-05-24 18:36:31 +0000
5914+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-05-03 15:14:56 +0000
5915@@ -16,5 +16,5 @@
5916 vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
5917 }
5918
5919-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5920+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5921 /* { dg-final { cleanup-saved-temps } } */
5922
5923=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c'
5924--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-05-24 18:36:31 +0000
5925+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-05-03 15:14:56 +0000
5926@@ -16,5 +16,5 @@
5927 vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
5928 }
5929
5930-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5931+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5932 /* { dg-final { cleanup-saved-temps } } */
5933
5934=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c'
5935--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-05-24 18:36:31 +0000
5936+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-05-03 15:14:56 +0000
5937@@ -16,5 +16,5 @@
5938 vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
5939 }
5940
5941-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5942+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5943 /* { dg-final { cleanup-saved-temps } } */
5944
5945=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c'
5946--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-05-24 18:36:31 +0000
5947+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-05-03 15:14:56 +0000
5948@@ -16,5 +16,5 @@
5949 vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
5950 }
5951
5952-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5953+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5954 /* { dg-final { cleanup-saved-temps } } */
5955
5956=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c'
5957--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-05-24 18:36:31 +0000
5958+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-05-03 15:14:56 +0000
5959@@ -16,5 +16,5 @@
5960 vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
5961 }
5962
5963-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5964+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5965 /* { dg-final { cleanup-saved-temps } } */
5966
5967=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c'
5968--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-05-24 18:36:31 +0000
5969+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-05-03 15:14:56 +0000
5970@@ -16,5 +16,5 @@
5971 vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
5972 }
5973
5974-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5975+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5976 /* { dg-final { cleanup-saved-temps } } */
5977
5978=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c'
5979--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-05-24 18:36:31 +0000
5980+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-05-03 15:14:56 +0000
5981@@ -16,5 +16,5 @@
5982 vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
5983 }
5984
5985-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5986+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5987 /* { dg-final { cleanup-saved-temps } } */
5988
5989=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c'
5990--- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-05-24 18:36:31 +0000
5991+++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-05-03 15:14:56 +0000
5992@@ -16,5 +16,5 @@
5993 vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
5994 }
5995
5996-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5997+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5998 /* { dg-final { cleanup-saved-temps } } */
5999
6000=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c'
6001--- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-05-24 18:36:31 +0000
6002+++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-05-03 15:14:56 +0000
6003@@ -16,5 +16,5 @@
6004 vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
6005 }
6006
6007-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6008+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6009 /* { dg-final { cleanup-saved-temps } } */
6010
6011=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c'
6012--- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-05-24 18:36:31 +0000
6013+++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-05-03 15:14:56 +0000
6014@@ -16,5 +16,5 @@
6015 vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
6016 }
6017
6018-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6019+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6020 /* { dg-final { cleanup-saved-temps } } */
6021
6022=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c'
6023--- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-05-24 18:36:31 +0000
6024+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-05-03 15:14:56 +0000
6025@@ -16,5 +16,5 @@
6026 vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
6027 }
6028
6029-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6030+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6031 /* { dg-final { cleanup-saved-temps } } */
6032
6033=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c'
6034--- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-05-24 18:36:31 +0000
6035+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-05-03 15:14:56 +0000
6036@@ -16,5 +16,5 @@
6037 vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
6038 }
6039
6040-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6041+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6042 /* { dg-final { cleanup-saved-temps } } */
6043
6044=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c'
6045--- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-05-24 18:36:31 +0000
6046+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-05-03 15:14:56 +0000
6047@@ -16,5 +16,5 @@
6048 vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
6049 }
6050
6051-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6052+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6053 /* { dg-final { cleanup-saved-temps } } */
6054
6055=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c'
6056--- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-05-24 18:36:31 +0000
6057+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-05-03 15:14:56 +0000
6058@@ -16,5 +16,5 @@
6059 vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
6060 }
6061
6062-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6063+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6064 /* { dg-final { cleanup-saved-temps } } */
6065
6066=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c'
6067--- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-05-24 18:36:31 +0000
6068+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-05-03 15:14:56 +0000
6069@@ -16,5 +16,5 @@
6070 vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
6071 }
6072
6073-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6074+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6075 /* { dg-final { cleanup-saved-temps } } */
6076
6077=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c'
6078--- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-05-24 18:36:31 +0000
6079+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-05-03 15:14:56 +0000
6080@@ -16,5 +16,5 @@
6081 vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
6082 }
6083
6084-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6085+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6086 /* { dg-final { cleanup-saved-temps } } */
6087
6088=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c'
6089--- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-05-24 18:36:31 +0000
6090+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-05-03 15:14:56 +0000
6091@@ -16,5 +16,5 @@
6092 vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
6093 }
6094
6095-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6096+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6097 /* { dg-final { cleanup-saved-temps } } */
6098
6099=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c'
6100--- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-05-24 18:36:31 +0000
6101+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-05-03 15:14:56 +0000
6102@@ -16,5 +16,5 @@
6103 vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
6104 }
6105
6106-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6107+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6108 /* { dg-final { cleanup-saved-temps } } */
6109
6110=== added file 'gcc/testsuite/gcc.target/arm/pr46329.c'
6111--- old/gcc/testsuite/gcc.target/arm/pr46329.c 1970-01-01 00:00:00 +0000
6112+++ new/gcc/testsuite/gcc.target/arm/pr46329.c 2011-05-03 15:18:07 +0000
6113@@ -0,0 +1,9 @@
6114+/* { dg-options "-O2" } */
6115+/* { dg-add-options arm_neon } */
6116+
6117+int __attribute__ ((vector_size (32))) x;
6118+void
6119+foo (void)
6120+{
6121+ x <<= x;
6122+}
6123
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch
new file mode 100644
index 000000000..aba2a497e
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch
@@ -0,0 +1,25 @@
12011-04-26 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-04-05 Tom de Vries <tom@codesourcery.com>
6
7 PR target/43920
8 gcc/
9 * config/arm/arm.h (BRANCH_COST): Set to 1 for Thumb-2 when optimizing
10 for size.
11
12=== modified file 'gcc/config/arm/arm.h'
13--- old/gcc/config/arm/arm.h 2011-05-03 15:17:25 +0000
14+++ new/gcc/config/arm/arm.h 2011-04-26 14:42:21 +0000
15@@ -2018,7 +2018,8 @@
16 /* Try to generate sequences that don't involve branches, we can then use
17 conditional instructions */
18 #define BRANCH_COST(speed_p, predictable_p) \
19- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
20+ (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
21+ : (optimize > 0 ? 2 : 0))
22
23 /* Position Independent Code. */
24 /* We decide which register to use based on the compilation options and
25
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch
new file mode 100644
index 000000000..004f0131c
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch
@@ -0,0 +1,21 @@
12011-05-06 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 From Sergey Grechanik <mouseentity@ispras.ru>, approved for mainline
5
6 * config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS
7 for constant vectors.
8
9=== modified file 'gcc/config/arm/arm.c'
10--- old/gcc/config/arm/arm.c 2011-05-03 15:18:07 +0000
11+++ new/gcc/config/arm/arm.c 2011-05-06 11:33:02 +0000
12@@ -9193,7 +9193,7 @@
13 /* The neon move patterns handle all legitimate vector and struct
14 addresses. */
15 if (TARGET_NEON
16- && MEM_P (x)
17+ && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
18 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
19 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
20 || VALID_NEON_STRUCT_MODE (mode)))
21
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch
new file mode 100644
index 000000000..ce0272431
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch
@@ -0,0 +1,24 @@
12011-05-12 Michael Hope <michael.hope@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-05-05 Michael Hope <michael.hope@linaro.org>
7
8 PR pch/45979
9 * config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for
10 __ARM_EABI__ hosts.
11
12=== modified file 'gcc/config/host-linux.c'
13--- old/gcc/config/host-linux.c 2010-11-29 14:09:41 +0000
14+++ new/gcc/config/host-linux.c 2011-05-06 20:19:30 +0000
15@@ -84,6 +84,8 @@
16 # define TRY_EMPTY_VM_SPACE 0x60000000
17 #elif defined(__mc68000__)
18 # define TRY_EMPTY_VM_SPACE 0x40000000
19+#elif defined(__ARM_EABI__)
20+# define TRY_EMPTY_VM_SPACE 0x60000000
21 #else
22 # define TRY_EMPTY_VM_SPACE 0
23 #endif
24
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch
new file mode 100644
index 000000000..7885b7af4
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch
@@ -0,0 +1,640 @@
12011-05-13 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 * loop-doloop.c (doloop_condition_get): Support new form of
5 doloop pattern and use prev_nondebug_insn instead of PREV_INSN.
6 * config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*".
7 (doloop_end): New.
8 * config/arm/arm.md (*addsi3_compare0): Remove "*".
9 * params.def (sms-min-sc): New param flag.
10 * doc/invoke.texi (sms-min-sc): Document it.
11 * ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge
12 enters the branch create an anti edge in the opposite direction
13 to prevent the creation of reg-moves.
14 * modulo-sched.c: Adjust comment to reflect the fact we are
15 scheduling closing branch.
16 (PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine.
17 (stage_count): New field in struct partial_schedule.
18 (calculate_stage_count): New function.
19 (normalize_sched_times): Rename to reset_sched_times and handle
20 incrementing the sched time of the nodes by a constant value
21 passed as parameter.
22 (duplicate_insns_of_cycles): Skip closing branch.
23 (sms_schedule_by_order): Schedule closing branch.
24 (ps_insn_find_column): Handle closing branch.
25 (sms_schedule): Call reset_sched_times and adjust the code to
26 support scheduling of the closing branch. Use sms-min-sc.
27 Support new form of doloop pattern.
28 (ps_insert_empty_row): Update calls to normalize_sched_times
29 and rotate_partial_schedule functions.
30
31=== modified file 'gcc/config/arm/arm.md'
32--- old/gcc/config/arm/arm.md 2011-05-06 11:28:27 +0000
33+++ new/gcc/config/arm/arm.md 2011-05-13 13:42:39 +0000
34@@ -791,7 +791,7 @@
35 ""
36 )
37
38-(define_insn "*addsi3_compare0"
39+(define_insn "addsi3_compare0"
40 [(set (reg:CC_NOOV CC_REGNUM)
41 (compare:CC_NOOV
42 (plus:SI (match_operand:SI 1 "s_register_operand" "r, r")
43
44=== modified file 'gcc/config/arm/thumb2.md'
45--- old/gcc/config/arm/thumb2.md 2011-01-03 20:52:22 +0000
46+++ new/gcc/config/arm/thumb2.md 2011-05-11 07:15:47 +0000
47@@ -836,7 +836,7 @@
48 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
49 )
50
51-(define_insn "*thumb2_addsi3_compare0"
52+(define_insn "thumb2_addsi3_compare0"
53 [(set (reg:CC_NOOV CC_REGNUM)
54 (compare:CC_NOOV
55 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
56@@ -1118,3 +1118,54 @@
57 "
58 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
59 ")
60+
61+;; Define the subtract-one-and-jump insns so loop.c
62+;; knows what to generate.
63+(define_expand "doloop_end"
64+ [(use (match_operand 0 "" "")) ; loop pseudo
65+ (use (match_operand 1 "" "")) ; iterations; zero if unknown
66+ (use (match_operand 2 "" "")) ; max iterations
67+ (use (match_operand 3 "" "")) ; loop level
68+ (use (match_operand 4 "" ""))] ; label
69+ "TARGET_32BIT"
70+ "
71+ {
72+ /* Currently SMS relies on the do-loop pattern to recognize loops
73+ where (1) the control part consists of all insns defining and/or
74+ using a certain 'count' register and (2) the loop count can be
75+ adjusted by modifying this register prior to the loop.
76+ ??? The possible introduction of a new block to initialize the
77+ new IV can potentially affect branch optimizations. */
78+ if (optimize > 0 && flag_modulo_sched)
79+ {
80+ rtx s0;
81+ rtx bcomp;
82+ rtx loc_ref;
83+ rtx cc_reg;
84+ rtx insn;
85+ rtx cmp;
86+
87+ /* Only use this on innermost loops. */
88+ if (INTVAL (operands[3]) > 1)
89+ FAIL;
90+ if (GET_MODE (operands[0]) != SImode)
91+ FAIL;
92+
93+ s0 = operands [0];
94+ if (TARGET_THUMB2)
95+ insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
96+ else
97+ insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
98+
99+ cmp = XVECEXP (PATTERN (insn), 0, 0);
100+ cc_reg = SET_DEST (cmp);
101+ bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
102+ loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
103+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
104+ gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
105+ loc_ref, pc_rtx)));
106+ DONE;
107+ }else
108+ FAIL;
109+}")
110+
111
112=== modified file 'gcc/ddg.c'
113--- old/gcc/ddg.c 2010-11-30 11:41:24 +0000
114+++ new/gcc/ddg.c 2011-05-11 07:15:47 +0000
115@@ -197,6 +197,11 @@
116 }
117 }
118
119+ /* If a true dep edge enters the branch create an anti edge in the
120+ opposite direction to prevent the creation of reg-moves. */
121+ if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
122+ create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
123+
124 latency = dep_cost (link);
125 e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
126 add_edge_to_ddg (g, e);
127
128=== modified file 'gcc/doc/invoke.texi'
129--- old/gcc/doc/invoke.texi 2011-04-18 11:31:29 +0000
130+++ new/gcc/doc/invoke.texi 2011-05-11 07:15:47 +0000
131@@ -8730,6 +8730,10 @@
132 The maximum number of best instructions in the ready list that are considered
133 for renaming in the selective scheduler. The default value is 2.
134
135+@item sms-min-sc
136+The minimum value of stage count that swing modulo scheduler will
137+generate. The default value is 2.
138+
139 @item max-last-value-rtl
140 The maximum size measured as number of RTLs that can be recorded in an expression
141 in combiner for a pseudo register as last known value of that register. The default
142
143=== modified file 'gcc/loop-doloop.c'
144--- old/gcc/loop-doloop.c 2010-11-30 11:41:24 +0000
145+++ new/gcc/loop-doloop.c 2011-05-11 07:15:47 +0000
146@@ -78,6 +78,8 @@
147 rtx inc_src;
148 rtx condition;
149 rtx pattern;
150+ rtx cc_reg = NULL_RTX;
151+ rtx reg_orig = NULL_RTX;
152
153 /* The canonical doloop pattern we expect has one of the following
154 forms:
155@@ -96,7 +98,16 @@
156 2) (set (reg) (plus (reg) (const_int -1))
157 (set (pc) (if_then_else (reg != 0)
158 (label_ref (label))
159- (pc))). */
160+ (pc))).
161+
162+ Some targets (ARM) do the comparison before the branch, as in the
163+ following form:
164+
165+ 3) (parallel [(set (cc) (compare ((plus (reg) (const_int -1), 0)))
166+ (set (reg) (plus (reg) (const_int -1)))])
167+ (set (pc) (if_then_else (cc == NE)
168+ (label_ref (label))
169+ (pc))) */
170
171 pattern = PATTERN (doloop_pat);
172
173@@ -104,19 +115,47 @@
174 {
175 rtx cond;
176 rtx prev_insn = prev_nondebug_insn (doloop_pat);
177+ rtx cmp_arg1, cmp_arg2;
178+ rtx cmp_orig;
179
180- /* We expect the decrement to immediately precede the branch. */
181+ /* In case the pattern is not PARALLEL we expect two forms
182+ of doloop which are cases 2) and 3) above: in case 2) the
183+ decrement immediately precedes the branch, while in case 3)
184+ the compare and decrement instructions immediately precede
185+ the branch. */
186
187 if (prev_insn == NULL_RTX || !INSN_P (prev_insn))
188 return 0;
189
190 cmp = pattern;
191- inc = PATTERN (PREV_INSN (doloop_pat));
192+ if (GET_CODE (PATTERN (prev_insn)) == PARALLEL)
193+ {
194+ /* The third case: the compare and decrement instructions
195+ immediately precede the branch. */
196+ cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0);
197+ if (GET_CODE (cmp_orig) != SET)
198+ return 0;
199+ if (GET_CODE (SET_SRC (cmp_orig)) != COMPARE)
200+ return 0;
201+ cmp_arg1 = XEXP (SET_SRC (cmp_orig), 0);
202+ cmp_arg2 = XEXP (SET_SRC (cmp_orig), 1);
203+ if (cmp_arg2 != const0_rtx
204+ || GET_CODE (cmp_arg1) != PLUS)
205+ return 0;
206+ reg_orig = XEXP (cmp_arg1, 0);
207+ if (XEXP (cmp_arg1, 1) != GEN_INT (-1)
208+ || !REG_P (reg_orig))
209+ return 0;
210+ cc_reg = SET_DEST (cmp_orig);
211+
212+ inc = XVECEXP (PATTERN (prev_insn), 0, 1);
213+ }
214+ else
215+ inc = PATTERN (prev_insn);
216 /* We expect the condition to be of the form (reg != 0) */
217 cond = XEXP (SET_SRC (cmp), 0);
218 if (GET_CODE (cond) != NE || XEXP (cond, 1) != const0_rtx)
219 return 0;
220-
221 }
222 else
223 {
224@@ -162,11 +201,15 @@
225 return 0;
226
227 if ((XEXP (condition, 0) == reg)
228+ /* For the third case: */
229+ || ((cc_reg != NULL_RTX)
230+ && (XEXP (condition, 0) == cc_reg)
231+ && (reg_orig == reg))
232 || (GET_CODE (XEXP (condition, 0)) == PLUS
233- && XEXP (XEXP (condition, 0), 0) == reg))
234+ && XEXP (XEXP (condition, 0), 0) == reg))
235 {
236 if (GET_CODE (pattern) != PARALLEL)
237- /* The second form we expect:
238+ /* For the second form we expect:
239
240 (set (reg) (plus (reg) (const_int -1))
241 (set (pc) (if_then_else (reg != 0)
242@@ -181,7 +224,24 @@
243 (set (reg) (plus (reg) (const_int -1)))
244 (additional clobbers and uses)])
245
246- So we return that form instead.
247+ For the third form we expect:
248+
249+ (parallel [(set (cc) (compare ((plus (reg) (const_int -1)), 0))
250+ (set (reg) (plus (reg) (const_int -1)))])
251+ (set (pc) (if_then_else (cc == NE)
252+ (label_ref (label))
253+ (pc)))
254+
255+ which is equivalent to the following:
256+
257+ (parallel [(set (cc) (compare (reg, 1))
258+ (set (reg) (plus (reg) (const_int -1)))
259+ (set (pc) (if_then_else (NE == cc)
260+ (label_ref (label))
261+ (pc))))])
262+
263+ So we return the second form instead for the two cases.
264+
265 */
266 condition = gen_rtx_fmt_ee (NE, VOIDmode, inc_src, const1_rtx);
267
268
269=== modified file 'gcc/modulo-sched.c'
270--- old/gcc/modulo-sched.c 2011-02-14 17:59:10 +0000
271+++ new/gcc/modulo-sched.c 2011-05-11 07:15:47 +0000
272@@ -84,14 +84,13 @@
273 II cycles (i.e. use register copies to prevent a def from overwriting
274 itself before reaching the use).
275
276- SMS works with countable loops (1) whose control part can be easily
277- decoupled from the rest of the loop and (2) whose loop count can
278- be easily adjusted. This is because we peel a constant number of
279- iterations into a prologue and epilogue for which we want to avoid
280- emitting the control part, and a kernel which is to iterate that
281- constant number of iterations less than the original loop. So the
282- control part should be a set of insns clearly identified and having
283- its own iv, not otherwise used in the loop (at-least for now), which
284+ SMS works with countable loops whose loop count can be easily
285+ adjusted. This is because we peel a constant number of iterations
286+ into a prologue and epilogue for which we want to avoid emitting
287+ the control part, and a kernel which is to iterate that constant
288+ number of iterations less than the original loop. So the control
289+ part should be a set of insns clearly identified and having its
290+ own iv, not otherwise used in the loop (at-least for now), which
291 initializes a register before the loop to the number of iterations.
292 Currently SMS relies on the do-loop pattern to recognize such loops,
293 where (1) the control part comprises of all insns defining and/or
294@@ -116,8 +115,10 @@
295
296 /* The number of different iterations the nodes in ps span, assuming
297 the stage boundaries are placed efficiently. */
298-#define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
299- + 1 + (ps)->ii - 1) / (ps)->ii)
300+#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \
301+ + 1 + ii - 1) / ii)
302+/* The stage count of ps. */
303+#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count)
304
305 /* A single instruction in the partial schedule. */
306 struct ps_insn
307@@ -155,6 +156,8 @@
308 int max_cycle;
309
310 ddg_ptr g; /* The DDG of the insns in the partial schedule. */
311+
312+ int stage_count; /* The stage count of the partial schedule. */
313 };
314
315 /* We use this to record all the register replacements we do in
316@@ -195,7 +198,7 @@
317 rtx, rtx);
318 static void duplicate_insns_of_cycles (partial_schedule_ptr,
319 int, int, int, rtx);
320-
321+static int calculate_stage_count (partial_schedule_ptr ps);
322 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
323 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
324 #define SCHED_FIRST_REG_MOVE(x) \
325@@ -310,10 +313,10 @@
326 either a single (parallel) branch-on-count or a (non-parallel)
327 branch immediately preceded by a single (decrement) insn. */
328 first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
329- : PREV_INSN (tail));
330+ : prev_nondebug_insn (tail));
331
332 for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn))
333- if (reg_mentioned_p (reg, insn))
334+ if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn))
335 {
336 if (dump_file)
337 {
338@@ -569,13 +572,12 @@
339 }
340 }
341
342-/* Bump the SCHED_TIMEs of all nodes to start from zero. Set the values
343- of SCHED_ROW and SCHED_STAGE. */
344+/* Bump the SCHED_TIMEs of all nodes by AMOUNT. Set the values of
345+ SCHED_ROW and SCHED_STAGE. */
346 static void
347-normalize_sched_times (partial_schedule_ptr ps)
348+reset_sched_times (partial_schedule_ptr ps, int amount)
349 {
350 int row;
351- int amount = PS_MIN_CYCLE (ps);
352 int ii = ps->ii;
353 ps_insn_ptr crr_insn;
354
355@@ -584,19 +586,43 @@
356 {
357 ddg_node_ptr u = crr_insn->node;
358 int normalized_time = SCHED_TIME (u) - amount;
359+ int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
360+ int sc_until_cycle_zero, stage;
361
362- if (dump_file)
363- fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
364- min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME
365- (u), ps->min_cycle);
366+ if (dump_file)
367+ {
368+ /* Print the scheduling times after the rotation. */
369+ fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
370+ "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
371+ INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
372+ normalized_time);
373+ if (JUMP_P (crr_insn->node->insn))
374+ fprintf (dump_file, " (branch)");
375+ fprintf (dump_file, "\n");
376+ }
377+
378 gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
379 gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
380 SCHED_TIME (u) = normalized_time;
381- SCHED_ROW (u) = normalized_time % ii;
382- SCHED_STAGE (u) = normalized_time / ii;
383+ SCHED_ROW (u) = SMODULO (normalized_time, ii);
384+
385+ /* The calculation of stage count is done adding the number
386+ of stages before cycle zero and after cycle zero. */
387+ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
388+
389+ if (SCHED_TIME (u) < 0)
390+ {
391+ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
392+ SCHED_STAGE (u) = sc_until_cycle_zero - stage;
393+ }
394+ else
395+ {
396+ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
397+ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
398+ }
399 }
400 }
401-
402+
403 /* Set SCHED_COLUMN of each node according to its position in PS. */
404 static void
405 set_columns_for_ps (partial_schedule_ptr ps)
406@@ -646,9 +672,12 @@
407
408 /* Do not duplicate any insn which refers to count_reg as it
409 belongs to the control part.
410+ The closing branch is scheduled as well and thus should
411+ be ignored.
412 TODO: This should be done by analyzing the control part of
413 the loop. */
414- if (reg_mentioned_p (count_reg, u_node->insn))
415+ if (reg_mentioned_p (count_reg, u_node->insn)
416+ || JUMP_P (ps_ij->node->insn))
417 continue;
418
419 if (for_prolog)
420@@ -1009,9 +1038,11 @@
421 continue;
422 }
423
424- /* Don't handle BBs with calls or barriers, or !single_set insns,
425- or auto-increment insns (to avoid creating invalid reg-moves
426- for the auto-increment insns).
427+ /* Don't handle BBs with calls or barriers or auto-increment insns
428+ (to avoid creating invalid reg-moves for the auto-increment insns),
429+ or !single_set with the exception of instructions that include
430+ count_reg---these instructions are part of the control part
431+ that do-loop recognizes.
432 ??? Should handle auto-increment insns.
433 ??? Should handle insns defining subregs. */
434 for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
435@@ -1021,7 +1052,8 @@
436 if (CALL_P (insn)
437 || BARRIER_P (insn)
438 || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
439- && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE)
440+ && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
441+ && !reg_mentioned_p (count_reg, insn))
442 || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
443 || (INSN_P (insn) && (set = single_set (insn))
444 && GET_CODE (SET_DEST (set)) == SUBREG))
445@@ -1049,7 +1081,11 @@
446 continue;
447 }
448
449- if (! (g = create_ddg (bb, 0)))
450+ /* Always schedule the closing branch with the rest of the
451+ instructions. The branch is rotated to be in row ii-1 at the
452+ end of the scheduling procedure to make sure it's the last
453+ instruction in the iteration. */
454+ if (! (g = create_ddg (bb, 1)))
455 {
456 if (dump_file)
457 fprintf (dump_file, "SMS create_ddg failed\n");
458@@ -1157,14 +1193,17 @@
459
460 ps = sms_schedule_by_order (g, mii, maxii, node_order);
461
462- if (ps){
463- stage_count = PS_STAGE_COUNT (ps);
464- gcc_assert(stage_count >= 1);
465- }
466+ if (ps)
467+ {
468+ stage_count = calculate_stage_count (ps);
469+ gcc_assert(stage_count >= 1);
470+ PS_STAGE_COUNT(ps) = stage_count;
471+ }
472
473- /* Stage count of 1 means that there is no interleaving between
474- iterations, let the scheduling passes do the job. */
475- if (stage_count <= 1
476+ /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
477+ 1 means that there is no interleaving between iterations thus
478+ we let the scheduling passes do the job in this case. */
479+ if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
480 || (count_init && (loop_count <= stage_count))
481 || (flag_branch_probabilities && (trip_count <= stage_count)))
482 {
483@@ -1182,32 +1221,24 @@
484 else
485 {
486 struct undo_replace_buff_elem *reg_move_replaces;
487-
488- if (dump_file)
489- {
490+ int amount = SCHED_TIME (g->closing_branch) + 1;
491+
492+ /* Set the stage boundaries. The closing_branch was scheduled
493+ and should appear in the last (ii-1) row. */
494+ reset_sched_times (ps, amount);
495+ rotate_partial_schedule (ps, amount);
496+ set_columns_for_ps (ps);
497+
498+ canon_loop (loop);
499+
500+ if (dump_file)
501+ {
502 fprintf (dump_file,
503 "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
504 stage_count);
505 print_partial_schedule (ps, dump_file);
506- fprintf (dump_file,
507- "SMS Branch (%d) will later be scheduled at cycle %d.\n",
508- g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
509 }
510-
511- /* Set the stage boundaries. If the DDG is built with closing_branch_deps,
512- the closing_branch was scheduled and should appear in the last (ii-1)
513- row. Otherwise, we are free to schedule the branch, and we let nodes
514- that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
515- row; this should reduce stage_count to minimum.
516- TODO: Revisit the issue of scheduling the insns of the
517- control part relative to the branch when the control part
518- has more than one insn. */
519- normalize_sched_times (ps);
520- rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
521- set_columns_for_ps (ps);
522-
523- canon_loop (loop);
524-
525+
526 /* case the BCT count is not known , Do loop-versioning */
527 if (count_reg && ! count_init)
528 {
529@@ -1760,12 +1791,6 @@
530 continue;
531 }
532
533- if (JUMP_P (insn)) /* Closing branch handled later. */
534- {
535- RESET_BIT (tobe_scheduled, u);
536- continue;
537- }
538-
539 if (TEST_BIT (sched_nodes, u))
540 continue;
541
542@@ -1893,8 +1918,8 @@
543 if (dump_file)
544 fprintf (dump_file, "split_row=%d\n", split_row);
545
546- normalize_sched_times (ps);
547- rotate_partial_schedule (ps, ps->min_cycle);
548+ reset_sched_times (ps, PS_MIN_CYCLE (ps));
549+ rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
550
551 rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
552 for (row = 0; row < split_row; row++)
553@@ -2571,6 +2596,7 @@
554 ps_insn_ptr next_ps_i;
555 ps_insn_ptr first_must_follow = NULL;
556 ps_insn_ptr last_must_precede = NULL;
557+ ps_insn_ptr last_in_row = NULL;
558 int row;
559
560 if (! ps_i)
561@@ -2597,8 +2623,37 @@
562 else
563 last_must_precede = next_ps_i;
564 }
565+ /* The closing branch must be the last in the row. */
566+ if (must_precede
567+ && TEST_BIT (must_precede, next_ps_i->node->cuid)
568+ && JUMP_P (next_ps_i->node->insn))
569+ return false;
570+
571+ last_in_row = next_ps_i;
572 }
573
574+ /* The closing branch is scheduled as well. Make sure there is no
575+ dependent instruction after it as the branch should be the last
576+ instruction in the row. */
577+ if (JUMP_P (ps_i->node->insn))
578+ {
579+ if (first_must_follow)
580+ return false;
581+ if (last_in_row)
582+ {
583+ /* Make the branch the last in the row. New instructions
584+ will be inserted at the beginning of the row or after the
585+ last must_precede instruction thus the branch is guaranteed
586+ to remain the last instruction in the row. */
587+ last_in_row->next_in_row = ps_i;
588+ ps_i->prev_in_row = last_in_row;
589+ ps_i->next_in_row = NULL;
590+ }
591+ else
592+ ps->rows[row] = ps_i;
593+ return true;
594+ }
595+
596 /* Now insert the node after INSERT_AFTER_PSI. */
597
598 if (! last_must_precede)
599@@ -2820,6 +2875,24 @@
600 return ps_i;
601 }
602
603+/* Calculate the stage count of the partial schedule PS. The calculation
604+ takes into account the rotation to bring the closing branch to row
605+ ii-1. */
606+int
607+calculate_stage_count (partial_schedule_ptr ps)
608+{
609+ int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
610+ int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
611+ int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
612+ int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
613+
614+ /* The calculation of stage count is done adding the number of stages
615+ before cycle zero and after cycle zero. */
616+ stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii);
617+
618+ return stage_count;
619+}
620+
621 /* Rotate the rows of PS such that insns scheduled at time
622 START_CYCLE will appear in row 0. Updates max/min_cycles. */
623 void
624
625=== modified file 'gcc/params.def'
626--- old/gcc/params.def 2011-04-18 11:31:29 +0000
627+++ new/gcc/params.def 2011-05-11 07:15:47 +0000
628@@ -344,6 +344,11 @@
629 "sms-max-ii-factor",
630 "A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop",
631 100, 0, 0)
632+/* The minimum value of stage count that swing modulo scheduler will generate. */
633+DEFPARAM(PARAM_SMS_MIN_SC,
634+ "sms-min-sc",
635+ "The minimum value of stage count that swing modulo scheduler will generate.",
636+ 2, 1, 1)
637 DEFPARAM(PARAM_SMS_DFA_HISTORY,
638 "sms-dfa-history",
639 "The number of cycles the swing modulo scheduler considers when checking conflicts using DFA",
640
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch
new file mode 100644
index 000000000..9c62102db
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch
@@ -0,0 +1,30 @@
1 2011-05-13 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 * ddg.c (free_ddg_all_sccs): Free sccs field in struct ddg_all_sccs.
5 * modulo-sched.c (sms_schedule): Avoid unfreed memory when SMS fails.
6
7=== modified file 'gcc/ddg.c'
8--- old/gcc/ddg.c 2011-05-11 07:15:47 +0000
9+++ new/gcc/ddg.c 2011-05-13 16:03:40 +0000
10@@ -1016,6 +1016,7 @@
11 for (i = 0; i < all_sccs->num_sccs; i++)
12 free_scc (all_sccs->sccs[i]);
13
14+ free (all_sccs->sccs);
15 free (all_sccs);
16 }
17
18
19=== modified file 'gcc/modulo-sched.c'
20--- old/gcc/modulo-sched.c 2011-05-11 07:15:47 +0000
21+++ new/gcc/modulo-sched.c 2011-05-13 16:03:40 +0000
22@@ -1216,7 +1216,6 @@
23 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
24 fprintf (dump_file, ")\n");
25 }
26- continue;
27 }
28 else
29 {
30
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch
new file mode 100644
index 000000000..c26ee5bde
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch
@@ -0,0 +1,134 @@
12011-06-02 Chung-Lin Tang <cltang@codesourcery.com>
2
3 Backport from mainline:
4
5 2011-03-21 Chung-Lin Tang <cltang@codesourcery.com>
6
7 gcc/
8 * simplify-rtx.c (simplify_binary_operation_1): Handle
9 (xor (and A B) C) case when B and C are both constants.
10
11 gcc/testsuite/
12 * gcc.target/arm/xor-and.c: New.
13
14 2011-03-18 Chung-Lin Tang <cltang@codesourcery.com>
15
16 gcc/
17 * combine.c (try_combine): Do simplification only call of
18 subst() on i2 even when i1 is present. Update comments.
19
20 gcc/testsuite/
21 * gcc.target/arm/unsigned-extend-1.c: New.
22
23=== modified file 'gcc/combine.c'
24--- old/gcc/combine.c 2011-05-06 11:28:27 +0000
25+++ new/gcc/combine.c 2011-05-27 14:31:18 +0000
26@@ -3089,7 +3089,7 @@
27 /* It is possible that the source of I2 or I1 may be performing
28 an unneeded operation, such as a ZERO_EXTEND of something
29 that is known to have the high part zero. Handle that case
30- by letting subst look at the innermost one of them.
31+ by letting subst look at the inner insns.
32
33 Another way to do this would be to have a function that tries
34 to simplify a single insn instead of merging two or more
35@@ -3114,11 +3114,9 @@
36 subst_low_luid = DF_INSN_LUID (i1);
37 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
38 }
39- else
40- {
41- subst_low_luid = DF_INSN_LUID (i2);
42- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
43- }
44+
45+ subst_low_luid = DF_INSN_LUID (i2);
46+ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
47 }
48
49 n_occurrences = 0; /* `subst' counts here */
50
51=== modified file 'gcc/simplify-rtx.c'
52--- old/gcc/simplify-rtx.c 2011-03-26 09:24:06 +0000
53+++ new/gcc/simplify-rtx.c 2011-05-27 14:31:18 +0000
54@@ -2484,6 +2484,46 @@
55 XEXP (op0, 1), mode),
56 op1);
57
58+ /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
59+ we can transform like this:
60+ (A&B)^C == ~(A&B)&C | ~C&(A&B)
61+ == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
62+ == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
63+ Attempt a few simplifications when B and C are both constants. */
64+ if (GET_CODE (op0) == AND
65+ && CONST_INT_P (op1)
66+ && CONST_INT_P (XEXP (op0, 1)))
67+ {
68+ rtx a = XEXP (op0, 0);
69+ rtx b = XEXP (op0, 1);
70+ rtx c = op1;
71+ HOST_WIDE_INT bval = INTVAL (b);
72+ HOST_WIDE_INT cval = INTVAL (c);
73+
74+ rtx na_c
75+ = simplify_binary_operation (AND, mode,
76+ simplify_gen_unary (NOT, mode, a, mode),
77+ c);
78+ if ((~cval & bval) == 0)
79+ {
80+ /* Try to simplify ~A&C | ~B&C. */
81+ if (na_c != NULL_RTX)
82+ return simplify_gen_binary (IOR, mode, na_c,
83+ GEN_INT (~bval & cval));
84+ }
85+ else
86+ {
87+ /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
88+ if (na_c == const0_rtx)
89+ {
90+ rtx a_nc_b = simplify_gen_binary (AND, mode, a,
91+ GEN_INT (~cval & bval));
92+ return simplify_gen_binary (IOR, mode, a_nc_b,
93+ GEN_INT (~bval & cval));
94+ }
95+ }
96+ }
97+
98 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
99 comparison if STORE_FLAG_VALUE is 1. */
100 if (STORE_FLAG_VALUE == 1
101
102=== added file 'gcc/testsuite/gcc.target/arm/unsigned-extend-1.c'
103--- old/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 1970-01-01 00:00:00 +0000
104+++ new/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 2011-05-27 14:31:18 +0000
105@@ -0,0 +1,9 @@
106+/* { dg-do compile } */
107+/* { dg-options "-O2 -march=armv6" } */
108+
109+unsigned char foo (unsigned char c)
110+{
111+ return (c >= '0') && (c <= '9');
112+}
113+
114+/* { dg-final { scan-assembler-not "uxtb" } } */
115
116=== added file 'gcc/testsuite/gcc.target/arm/xor-and.c'
117--- old/gcc/testsuite/gcc.target/arm/xor-and.c 1970-01-01 00:00:00 +0000
118+++ new/gcc/testsuite/gcc.target/arm/xor-and.c 2011-05-27 14:31:18 +0000
119@@ -0,0 +1,14 @@
120+/* { dg-do compile } */
121+/* { dg-options "-O -march=armv6" } */
122+
123+unsigned short foo (unsigned short x)
124+{
125+ x ^= 0x4002;
126+ x >>= 1;
127+ x |= 0x8000;
128+ return x;
129+}
130+
131+/* { dg-final { scan-assembler "orr" } } */
132+/* { dg-final { scan-assembler-not "mvn" } } */
133+/* { dg-final { scan-assembler-not "uxth" } } */
134
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch
new file mode 100644
index 000000000..bda39e8fa
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch
@@ -0,0 +1,5027 @@
12001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 * gimple.c (gimple_build_call_internal_1): Add missing call to
5 gimple_call_reset_alias_info.
6
72001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
8
9 gcc/testsuite/
10 Backport from mainline:
11
12 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
13
14 * gcc.dg/vect/vect-strided-u16-i3.c: New test.
15
162001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
17
18 gcc/testsuite/
19 Backport from mainline:
20
21 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
22
23 * lib/target-supports.exp (check_effective_target_vect_strided):
24 Replace with...
25 (check_effective_target_vect_strided2)
26 (check_effective_target_vect_strided3)
27 (check_effective_target_vect_strided4)
28 (check_effective_target_vect_strided8): ...these new functions.
29
30 * gcc.dg/vect/O3-pr39675-2.c: Update accordingly.
31 * gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c: Likewise.
32 * gcc.dg/vect/fast-math-slp-27.c: Likewise.
33 * gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: Likewise.
34 * gcc.dg/vect/pr37539.c: Likewise.
35 * gcc.dg/vect/slp-11a.c: Likewise.
36 * gcc.dg/vect/slp-11b.c: Likewise.
37 * gcc.dg/vect/slp-11c.c: Likewise.
38 * gcc.dg/vect/slp-12a.c: Likewise.
39 * gcc.dg/vect/slp-12b.c: Likewise.
40 * gcc.dg/vect/slp-18.c: Likewise.
41 * gcc.dg/vect/slp-19a.c: Likewise.
42 * gcc.dg/vect/slp-19b.c: Likewise.
43 * gcc.dg/vect/slp-21.c: Likewise.
44 * gcc.dg/vect/slp-23.c: Likewise.
45 * gcc.dg/vect/vect-cselim-1.c: Likewise.
46
47 * gcc.dg/vect/fast-math-vect-complex-3.c: Use vect_stridedN
48 instead of vect_interleave && vect_extract_even_odd.
49 * gcc.dg/vect/no-scevccp-outer-10a.c: Likewise.
50 * gcc.dg/vect/no-scevccp-outer-10b.c: Likewise.
51 * gcc.dg/vect/no-scevccp-outer-20.c: Likewise.
52 * gcc.dg/vect/vect-1.c: Likewise.
53 * gcc.dg/vect/vect-10.c: Likewise.
54 * gcc.dg/vect/vect-98.c: Likewise.
55 * gcc.dg/vect/vect-107.c: Likewise.
56 * gcc.dg/vect/vect-strided-a-mult.c: Likewise.
57 * gcc.dg/vect/vect-strided-a-u16-i2.c: Likewise.
58 * gcc.dg/vect/vect-strided-a-u16-i4.c: Likewise.
59 * gcc.dg/vect/vect-strided-a-u16-mult.c: Likewise.
60 * gcc.dg/vect/vect-strided-a-u32-mult.c: Likewise.
61 * gcc.dg/vect/vect-strided-a-u8-i2-gap.c: Likewise.
62 * gcc.dg/vect/vect-strided-a-u8-i8-gap2.c: Likewise.
63 * gcc.dg/vect/vect-strided-a-u8-i8-gap7.c: Likewise.
64 * gcc.dg/vect/vect-strided-float.c: Likewise.
65 * gcc.dg/vect/vect-strided-mult-char-ls.c: Likewise.
66 * gcc.dg/vect/vect-strided-mult.c: Likewise.
67 * gcc.dg/vect/vect-strided-same-dr.c: Likewise.
68 * gcc.dg/vect/vect-strided-u16-i2.c: Likewise.
69 * gcc.dg/vect/vect-strided-u16-i4.c: Likewise.
70 * gcc.dg/vect/vect-strided-u32-i4.c: Likewise.
71 * gcc.dg/vect/vect-strided-u32-i8.c: Likewise.
72 * gcc.dg/vect/vect-strided-u32-mult.c: Likewise.
73 * gcc.dg/vect/vect-strided-u8-i2-gap.c: Likewise.
74 * gcc.dg/vect/vect-strided-u8-i2.c: Likewise.
75 * gcc.dg/vect/vect-strided-u8-i8-gap2.c: Likewise.
76 * gcc.dg/vect/vect-strided-u8-i8-gap4.c: Likewise.
77 * gcc.dg/vect/vect-strided-u8-i8-gap7.c: Likewise.
78 * gcc.dg/vect/vect-strided-u8-i8.c: Likewise.
79 * gcc.dg/vect/vect-vfa-03.c: Likewise.
80
81 * gcc.dg/vect/no-scevccp-outer-18.c: Add vect_stridedN to the
82 target condition.
83 * gcc.dg/vect/pr30843.c: Likewise.
84 * gcc.dg/vect/pr33866.c: Likewise.
85 * gcc.dg/vect/slp-reduc-6.c: Likewise.
86 * gcc.dg/vect/vect-strided-store-a-u8-i2.c: Likewise.
87 * gcc.dg/vect/vect-strided-store-u16-i4.c: Likewise.
88 * gcc.dg/vect/vect-strided-store-u32-i2.c: Likewise.
89
902001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
91
92 gcc/testsuite/
93 Backport from mainline:
94
95 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
96
97 * gcc.dg/vect/slp-11.c: Split into...
98 * gcc.dg/vect/slp-11a.c, gcc.dg/vect/slp-11b.c,
99 gcc.dg/vect/slp-11c.c: ...these tests.
100 * gcc.dg/vect/slp-12a.c: Split 4-stride loop into...
101 * gcc.dg/vect/slp-12c.c: ...this new test.
102 * gcc.dg/vect/slp-19.c: Split into...
103 * gcc.dg/vect/slp-19a.c, gcc.dg/vect/slp-19b.c,
104 gcc.dg/vect/slp-19c.c: ...these new tests.
105
1062001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
107
108 gcc/testsuite/
109 Backport from mainline:
110
111 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
112
113 * lib/target-supports.exp
114 (check_effective_target_vect_extract_even_odd_wide): Delete.
115 (check_effective_target_vect_strided_wide): Likewise.
116 * gcc.dg/vect/O3-pr39675-2.c: Use the non-wide versions instead.
117 * gcc.dg/vect/fast-math-pr35982.c: Likewise.
118 * gcc.dg/vect/fast-math-vect-complex-3.c: Likewise.
119 * gcc.dg/vect/pr37539.c: Likewise.
120 * gcc.dg/vect/slp-11.c: Likewise.
121 * gcc.dg/vect/slp-12a.c: Likewise.
122 * gcc.dg/vect/slp-12b.c: Likewise.
123 * gcc.dg/vect/slp-19.c: Likewise.
124 * gcc.dg/vect/slp-23.c: Likewise.
125 * gcc.dg/vect/vect-1.c: Likewise.
126 * gcc.dg/vect/vect-98.c: Likewise.
127 * gcc.dg/vect/vect-107.c: Likewise.
128 * gcc.dg/vect/vect-strided-float.c: Likewise.
129
1302001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
131
132 gcc/testsuite/
133 Backport from mainline:
134
135 2011-04-21 Richard Sandiford <richard.sandiford@linaro.org>
136
137 * gcc.dg/vect/vect.exp: Run the main tests twice, one with -flto
138 and once without.
139
1402001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
141
142 gcc/
143 Backport from mainlie:
144
145 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
146
147 * config/arm/neon.md (vec_load_lanes<mode><mode>): New expanders,
148 (vec_store_lanes<mode><mode>): Likewise.
149
1502001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
151
152 gcc/
153 Backport from mainline:
154
155 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
156
157 * doc/md.texi (vec_load_lanes, vec_store_lanes): Document.
158 * optabs.h (COI_vec_load_lanes, COI_vec_store_lanes): New
159 convert_optab_index values.
160 (vec_load_lanes_optab, vec_store_lanes_optab): New convert optabs.
161 * genopinit.c (optabs): Initialize the new optabs.
162 * internal-fn.def (LOAD_LANES, STORE_LANES): New internal functions.
163 * internal-fn.c (get_multi_vector_move, expand_LOAD_LANES)
164 (expand_STORE_LANES): New functions.
165 * tree.h (build_array_type_nelts): Declare.
166 * tree.c (build_array_type_nelts): New function.
167 * tree-vectorizer.h (vect_model_store_cost): Add a bool argument.
168 (vect_model_load_cost): Likewise.
169 (vect_store_lanes_supported, vect_load_lanes_supported)
170 (vect_record_strided_load_vectors): Declare.
171 * tree-vect-data-refs.c (vect_lanes_optab_supported_p)
172 (vect_store_lanes_supported, vect_load_lanes_supported): New functions.
173 (vect_transform_strided_load): Split out statement recording into...
174 (vect_record_strided_load_vectors): ...this new function.
175 * tree-vect-stmts.c (create_vector_array, read_vector_array)
176 (write_vector_array, create_array_ref): New functions.
177 (vect_model_store_cost): Add store_lanes_p argument.
178 (vect_model_load_cost): Add load_lanes_p argument.
179 (vectorizable_store): Try to use store-lanes functions for
180 interleaved stores.
181 (vectorizable_load): Likewise load-lanes and loads.
182 * tree-vect-slp.c (vect_get_and_check_slp_defs): Update call
183 to vect_model_store_cost.
184 (vect_build_slp_tree): Likewise vect_model_load_cost.
185
1862001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
187
188 gcc/
189 Backport from mainline:
190
191 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
192
193 * tree-vect-stmts.c (vectorizable_store): Only chain one related
194 statement per copy.
195
1962001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
197
198 gcc/
199 * tree-inline.c (estimate_num_insns): Likewise.
200
201 Backport from mainline:
202
203 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
204
205 * Makefile.in (INTERNAL_FN_DEF, INTERNAL_FN_H): Define.
206 (GIMPLE_H): Include $(INTERNAL_FN_H).
207 (OBJS-common): Add internal-fn.o.
208 (internal-fn.o): New rule.
209 * internal-fn.def: New file.
210 * internal-fn.h: Likewise.
211 * internal-fn.c: Likewise.
212 * gimple.h: Include internal-fn.h.
213 (GF_CALL_INTERNAL): New gf_mask.
214 (gimple_statement_call): Put fntype into a union with a new
215 internal_fn field.
216 (gimple_build_call_internal): Declare.
217 (gimple_build_call_internal_vec): Likewise.
218 (gimple_call_same_target_p): Likewise.
219 (gimple_call_internal_p): New function.
220 (gimple_call_internal_fn): Likewise.
221 (gimple_call_set_fn): Assert that the function is not internal.
222 (gimple_call_set_fndecl): Likewise.
223 (gimple_call_set_internal_fn): New function.
224 (gimple_call_addr_fndecl): Handle null functions.
225 (gimple_call_return_type): Likewise.
226 [---- Plus backport adjustments:
227 (GF_CALL_INTERNAL_FN_SHIFT): New macro.
228 (GF_CALL_INTERNAL_FN): New gf_mask.
229 ----]
230 * gimple.c (gimple_build_call_internal_1): New function.
231 (gimple_build_call_internal): Likewise.
232 (gimple_build_call_internal_vec): Likewise.
233 (gimple_call_same_target_p): Likewise.
234 (gimple_call_flags): Handle calls to internal functions.
235 (gimple_call_fnspec): New function.
236 (gimple_call_arg_flags, gimple_call_return_flags): Use it.
237 (gimple_has_side_effects): Handle null functions.
238 (gimple_rhs_has_side_effects): Likewise.
239 (gimple_call_copy_skip_args): Handle calls to internal functions.
240 * cfgexpand.c (expand_call_stmt): Likewise.
241 * expr.c (expand_expr_real_1): Assert that the call isn't internal.
242 * gimple-low.c (gimple_check_call_args): Handle calls to internal
243 functions.
244 * gimple-pretty-print.c (dump_gimple_call): Likewise.
245 * ipa-prop.c (ipa_analyze_call_uses): Handle null functions.
246 * tree-cfg.c (verify_gimple_call): Handle calls to internal functions.
247 (do_warn_unused_result): Likewise.
248 [---- Plus backport adjustments:
249 (verify_stmt): Likewise.
250 ----]
251 * tree-eh.c (same_handler_p): Use gimple_call_same_target_p.
252 * tree-ssa-ccp.c (ccp_fold_stmt): Handle calls to internal functions.
253 [---- Plus backport adjustments:
254 (fold_gimple_call): Likewise.
255 ----]
256 * tree-ssa-dom.c (hashable_expr): Use the gimple statement to record
257 the target of a call.
258 (initialize_hash_element): Update accordingly.
259 (hashable_expr_equal_p): Use gimple_call_same_target_p.
260 (iterative_hash_hashable_expr): Handle calls to internal functions.
261 (print_expr_hash_elt): Likewise.
262 * tree-ssa-pre.c (can_value_number_call): Likewise.
263 (eliminate): Handle null functions.
264 * tree-ssa-sccvn.c (visit_use): Handle calls to internal functions.
265 * tree-ssa-structalias.c (find_func_aliases): Likewise.
266 * value-prof.c (gimple_ic_transform): Likewise.
267 (gimple_indirect_call_to_profile): Likewise.
268
2692001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
270
271 gcc/
272 Backport from mainline:
273
274 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
275
276 * tree-vectorizer.h (vect_strided_store_supported): Add a
277 HOST_WIDE_INT argument.
278 (vect_strided_load_supported): Likewise.
279 (vect_permute_store_chain): Return void.
280 (vect_transform_strided_load): Likewise.
281 (vect_permute_load_chain): Delete.
282 * tree-vect-data-refs.c (vect_strided_store_supported): Take a
283 count argument. Check that the count is a power of two.
284 (vect_strided_load_supported): Likewise.
285 (vect_permute_store_chain): Return void. Update after above changes.
286 Assert that the access is supported.
287 (vect_permute_load_chain): Likewise.
288 (vect_transform_strided_load): Return void.
289 * tree-vect-stmts.c (vectorizable_store): Update calls after
290 above interface changes.
291 (vectorizable_load): Likewise.
292 (vect_analyze_stmt): Don't check for strided powers of two here.
293
2942001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
295
296 gcc/
297 Backport from mainline:
298
299 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
300
301 * tree-vectorizer.h (vect_create_data_ref_ptr): Add an extra
302 type parameter.
303 * tree-vect-data-refs.c (vect_create_data_ref_ptr): Add an aggr_type
304 parameter. Generalise code to handle arrays as well as vectors.
305 (vect_setup_realignment): Update accordingly.
306 * tree-vect-stmts.c (vectorizable_store): Likewise.
307 (vectorizable_load): Likewise.
308
3092001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
310
311 gcc/
312 Backport from mainline:
313
314 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
315
316 * tree-vect-stmts.c (vectorizable_load): Allocate and free dr_chain
317 within the per-copy loop.
318
3192001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
320
321 gcc/
322 Backport from mainline:
323
324 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
325
326 * tree-vect-stmts.c (vectorizable_load): Print the number of copies
327 in the dump file.
328
3292001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
330
331 gcc/
332 Backport from mainline:
333
334 2011-03-25 Richard Sandiford <richard.sandiford@linaro.org>
335
336 * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS
337 case to VFPv1.
338
339=== modified file 'gcc/Makefile.in'
340--- old/gcc/Makefile.in 2011-05-26 14:27:33 +0000
341+++ new/gcc/Makefile.in 2011-06-02 12:12:00 +0000
342@@ -888,6 +888,8 @@
343 READ_MD_H = $(OBSTACK_H) $(HASHTAB_H) read-md.h
344 PARAMS_H = params.h params.def
345 BUILTINS_DEF = builtins.def sync-builtins.def omp-builtins.def
346+INTERNAL_FN_DEF = internal-fn.def
347+INTERNAL_FN_H = internal-fn.h $(INTERNAL_FN_DEF)
348 TREE_H = tree.h all-tree.def tree.def c-family/c-common.def \
349 $(lang_tree_files) $(MACHMODE_H) tree-check.h $(BUILTINS_DEF) \
350 $(INPUT_H) statistics.h $(VEC_H) treestruct.def $(HASHTAB_H) \
351@@ -897,7 +899,7 @@
352 BASIC_BLOCK_H = basic-block.h $(PREDICT_H) $(VEC_H) $(FUNCTION_H) cfghooks.h
353 GIMPLE_H = gimple.h gimple.def gsstruct.def pointer-set.h $(VEC_H) \
354 $(GGC_H) $(BASIC_BLOCK_H) $(TARGET_H) tree-ssa-operands.h \
355- tree-ssa-alias.h vecir.h
356+ tree-ssa-alias.h vecir.h $(INTERNAL_FN_H)
357 GCOV_IO_H = gcov-io.h gcov-iov.h auto-host.h
358 COVERAGE_H = coverage.h $(GCOV_IO_H)
359 DEMANGLE_H = $(srcdir)/../include/demangle.h
360@@ -1269,6 +1271,7 @@
361 init-regs.o \
362 input.o \
363 integrate.o \
364+ internal-fn.o \
365 intl.o \
366 ira.o \
367 ira-build.o \
368@@ -2751,6 +2754,8 @@
369 $(TM_H) $(TREE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) $(TREE_FLOW_H) \
370 $(TREE_PASS_H) tree-ssa-propagate.h tree-pretty-print.h \
371 gimple-pretty-print.h
372+internal-fn.o : internal-fn.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
373+ $(GIMPLE_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H)
374 gimple.o : gimple.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \
375 $(GGC_H) $(GIMPLE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) gt-gimple.h \
376 $(TREE_FLOW_H) value-prof.h $(FLAGS_H) $(DEMANGLE_H) \
377
378=== modified file 'gcc/cfgexpand.c'
379--- old/gcc/cfgexpand.c 2011-04-20 11:18:50 +0000
380+++ new/gcc/cfgexpand.c 2011-06-02 12:12:00 +0000
381@@ -1839,12 +1839,17 @@
382 static void
383 expand_call_stmt (gimple stmt)
384 {
385- tree exp;
386- tree lhs = gimple_call_lhs (stmt);
387+ tree exp, lhs;
388 size_t i;
389 bool builtin_p;
390 tree decl;
391
392+ if (gimple_call_internal_p (stmt))
393+ {
394+ expand_internal_call (stmt);
395+ return;
396+ }
397+
398 exp = build_vl_exp (CALL_EXPR, gimple_call_num_args (stmt) + 3);
399
400 CALL_EXPR_FN (exp) = gimple_call_fn (stmt);
401@@ -1882,6 +1887,7 @@
402 SET_EXPR_LOCATION (exp, gimple_location (stmt));
403 TREE_BLOCK (exp) = gimple_block (stmt);
404
405+ lhs = gimple_call_lhs (stmt);
406 if (lhs)
407 expand_assignment (lhs, exp, false);
408 else
409
410=== modified file 'gcc/config/arm/arm.h'
411--- old/gcc/config/arm/arm.h 2011-04-26 14:42:21 +0000
412+++ new/gcc/config/arm/arm.h 2011-06-02 12:12:00 +0000
413@@ -1169,12 +1169,12 @@
414 }
415
416 /* FPA registers can't do subreg as all values are reformatted to internal
417- precision. VFP registers may only be accessed in the mode they
418- were set. */
419-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
420- (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
421- ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
422- || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
423+ precision. In VFPv1, VFP registers could only be accessed in the mode
424+ they were set, so subregs would be invalid there too. However, we don't
425+ support VFPv1 at the moment, and the restriction was lifted in VFPv2. */
426+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
427+ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
428+ ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
429 : 0)
430
431 /* The class value for index registers, and the one for base regs. */
432
433=== modified file 'gcc/config/arm/neon.md'
434--- old/gcc/config/arm/neon.md 2011-05-06 11:28:27 +0000
435+++ new/gcc/config/arm/neon.md 2011-06-02 12:12:00 +0000
436@@ -4248,6 +4248,12 @@
437 DONE;
438 })
439
440+(define_expand "vec_load_lanes<mode><mode>"
441+ [(set (match_operand:VDQX 0 "s_register_operand")
442+ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand")]
443+ UNSPEC_VLD1))]
444+ "TARGET_NEON")
445+
446 (define_insn "neon_vld1<mode>"
447 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
448 (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
449@@ -4345,6 +4351,12 @@
450 (const_string "neon_vld1_1_2_regs")))]
451 )
452
453+(define_expand "vec_store_lanes<mode><mode>"
454+ [(set (match_operand:VDQX 0 "neon_struct_operand")
455+ (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand")]
456+ UNSPEC_VST1))]
457+ "TARGET_NEON")
458+
459 (define_insn "neon_vst1<mode>"
460 [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
461 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
462@@ -4401,6 +4413,13 @@
463 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
464 )
465
466+(define_expand "vec_load_lanesti<mode>"
467+ [(set (match_operand:TI 0 "s_register_operand")
468+ (unspec:TI [(match_operand:TI 1 "neon_struct_operand")
469+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
470+ UNSPEC_VLD2))]
471+ "TARGET_NEON")
472+
473 (define_insn "neon_vld2<mode>"
474 [(set (match_operand:TI 0 "s_register_operand" "=w")
475 (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
476@@ -4419,6 +4438,13 @@
477 (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")))]
478 )
479
480+(define_expand "vec_load_lanesoi<mode>"
481+ [(set (match_operand:OI 0 "s_register_operand")
482+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand")
483+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
484+ UNSPEC_VLD2))]
485+ "TARGET_NEON")
486+
487 (define_insn "neon_vld2<mode>"
488 [(set (match_operand:OI 0 "s_register_operand" "=w")
489 (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
490@@ -4501,6 +4527,13 @@
491 (const_string "neon_vld1_1_2_regs")))]
492 )
493
494+(define_expand "vec_store_lanesti<mode>"
495+ [(set (match_operand:TI 0 "neon_struct_operand")
496+ (unspec:TI [(match_operand:TI 1 "s_register_operand")
497+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
498+ UNSPEC_VST2))]
499+ "TARGET_NEON")
500+
501 (define_insn "neon_vst2<mode>"
502 [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
503 (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
504@@ -4519,6 +4552,13 @@
505 (const_string "neon_vst1_1_2_regs_vst2_2_regs")))]
506 )
507
508+(define_expand "vec_store_lanesoi<mode>"
509+ [(set (match_operand:OI 0 "neon_struct_operand")
510+ (unspec:OI [(match_operand:OI 1 "s_register_operand")
511+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
512+ UNSPEC_VST2))]
513+ "TARGET_NEON")
514+
515 (define_insn "neon_vst2<mode>"
516 [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
517 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
518@@ -4584,6 +4624,13 @@
519 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
520 )
521
522+(define_expand "vec_load_lanesei<mode>"
523+ [(set (match_operand:EI 0 "s_register_operand")
524+ (unspec:EI [(match_operand:EI 1 "neon_struct_operand")
525+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
526+ UNSPEC_VLD3))]
527+ "TARGET_NEON")
528+
529 (define_insn "neon_vld3<mode>"
530 [(set (match_operand:EI 0 "s_register_operand" "=w")
531 (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
532@@ -4602,6 +4649,16 @@
533 (const_string "neon_vld3_vld4")))]
534 )
535
536+(define_expand "vec_load_lanesci<mode>"
537+ [(match_operand:CI 0 "s_register_operand")
538+ (match_operand:CI 1 "neon_struct_operand")
539+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
540+ "TARGET_NEON"
541+{
542+ emit_insn (gen_neon_vld3<mode> (operands[0], operands[1]));
543+ DONE;
544+})
545+
546 (define_expand "neon_vld3<mode>"
547 [(match_operand:CI 0 "s_register_operand")
548 (match_operand:CI 1 "neon_struct_operand")
549@@ -4741,6 +4798,13 @@
550 (const_string "neon_vld3_vld4_all_lanes")
551 (const_string "neon_vld1_1_2_regs")))])
552
553+(define_expand "vec_store_lanesei<mode>"
554+ [(set (match_operand:EI 0 "neon_struct_operand")
555+ (unspec:EI [(match_operand:EI 1 "s_register_operand")
556+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
557+ UNSPEC_VST3))]
558+ "TARGET_NEON")
559+
560 (define_insn "neon_vst3<mode>"
561 [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
562 (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
563@@ -4758,6 +4822,16 @@
564 (const_string "neon_vst1_1_2_regs_vst2_2_regs")
565 (const_string "neon_vst2_4_regs_vst3_vst4")))])
566
567+(define_expand "vec_store_lanesci<mode>"
568+ [(match_operand:CI 0 "neon_struct_operand")
569+ (match_operand:CI 1 "s_register_operand")
570+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
571+ "TARGET_NEON"
572+{
573+ emit_insn (gen_neon_vst3<mode> (operands[0], operands[1]));
574+ DONE;
575+})
576+
577 (define_expand "neon_vst3<mode>"
578 [(match_operand:CI 0 "neon_struct_operand")
579 (match_operand:CI 1 "s_register_operand")
580@@ -4869,6 +4943,13 @@
581 }
582 [(set_attr "neon_type" "neon_vst3_vst4_lane")])
583
584+(define_expand "vec_load_lanesoi<mode>"
585+ [(set (match_operand:OI 0 "s_register_operand")
586+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand")
587+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
588+ UNSPEC_VLD4))]
589+ "TARGET_NEON")
590+
591 (define_insn "neon_vld4<mode>"
592 [(set (match_operand:OI 0 "s_register_operand" "=w")
593 (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
594@@ -4887,6 +4968,16 @@
595 (const_string "neon_vld3_vld4")))]
596 )
597
598+(define_expand "vec_load_lanesxi<mode>"
599+ [(match_operand:XI 0 "s_register_operand")
600+ (match_operand:XI 1 "neon_struct_operand")
601+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
602+ "TARGET_NEON"
603+{
604+ emit_insn (gen_neon_vld4<mode> (operands[0], operands[1]));
605+ DONE;
606+})
607+
608 (define_expand "neon_vld4<mode>"
609 [(match_operand:XI 0 "s_register_operand")
610 (match_operand:XI 1 "neon_struct_operand")
611@@ -5033,6 +5124,13 @@
612 (const_string "neon_vld1_1_2_regs")))]
613 )
614
615+(define_expand "vec_store_lanesoi<mode>"
616+ [(set (match_operand:OI 0 "neon_struct_operand")
617+ (unspec:OI [(match_operand:OI 1 "s_register_operand")
618+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
619+ UNSPEC_VST4))]
620+ "TARGET_NEON")
621+
622 (define_insn "neon_vst4<mode>"
623 [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
624 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
625@@ -5051,6 +5149,16 @@
626 (const_string "neon_vst2_4_regs_vst3_vst4")))]
627 )
628
629+(define_expand "vec_store_lanesxi<mode>"
630+ [(match_operand:XI 0 "neon_struct_operand")
631+ (match_operand:XI 1 "s_register_operand")
632+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
633+ "TARGET_NEON"
634+{
635+ emit_insn (gen_neon_vst4<mode> (operands[0], operands[1]));
636+ DONE;
637+})
638+
639 (define_expand "neon_vst4<mode>"
640 [(match_operand:XI 0 "neon_struct_operand")
641 (match_operand:XI 1 "s_register_operand")
642
643=== modified file 'gcc/doc/md.texi'
644--- old/gcc/doc/md.texi 2011-01-03 20:52:22 +0000
645+++ new/gcc/doc/md.texi 2011-05-05 15:43:06 +0000
646@@ -3935,6 +3935,48 @@
647 consecutive memory locations, operand 1 is the first register, and
648 operand 2 is a constant: the number of consecutive registers.
649
650+@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
651+@item @samp{vec_load_lanes@var{m}@var{n}}
652+Perform an interleaved load of several vectors from memory operand 1
653+into register operand 0. Both operands have mode @var{m}. The register
654+operand is viewed as holding consecutive vectors of mode @var{n},
655+while the memory operand is a flat array that contains the same number
656+of elements. The operation is equivalent to:
657+
658+@smallexample
659+int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
660+for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
661+ for (i = 0; i < c; i++)
662+ operand0[i][j] = operand1[j * c + i];
663+@end smallexample
664+
665+For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
666+from memory into a register of mode @samp{TI}@. The register
667+contains two consecutive vectors of mode @samp{V4HI}@.
668+
669+This pattern can only be used if:
670+@smallexample
671+TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
672+@end smallexample
673+is true. GCC assumes that, if a target supports this kind of
674+instruction for some mode @var{n}, it also supports unaligned
675+loads for vectors of mode @var{n}.
676+
677+@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
678+@item @samp{vec_store_lanes@var{m}@var{n}}
679+Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
680+and register operands reversed. That is, the instruction is
681+equivalent to:
682+
683+@smallexample
684+int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
685+for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
686+ for (i = 0; i < c; i++)
687+ operand0[j * c + i] = operand1[i][j];
688+@end smallexample
689+
690+for a memory operand 0 and register operand 1.
691+
692 @cindex @code{vec_set@var{m}} instruction pattern
693 @item @samp{vec_set@var{m}}
694 Set given field in the vector value. Operand 0 is the vector to modify,
695
696=== modified file 'gcc/expr.c'
697--- old/gcc/expr.c 2011-05-26 14:27:33 +0000
698+++ new/gcc/expr.c 2011-06-02 12:12:00 +0000
699@@ -8537,10 +8537,13 @@
700 if (code == SSA_NAME
701 && (g = SSA_NAME_DEF_STMT (ssa_name))
702 && gimple_code (g) == GIMPLE_CALL)
703- pmode = promote_function_mode (type, mode, &unsignedp,
704- TREE_TYPE
705- (TREE_TYPE (gimple_call_fn (g))),
706- 2);
707+ {
708+ gcc_assert (!gimple_call_internal_p (g));
709+ pmode = promote_function_mode (type, mode, &unsignedp,
710+ TREE_TYPE
711+ (TREE_TYPE (gimple_call_fn (g))),
712+ 2);
713+ }
714 else
715 pmode = promote_decl_mode (exp, &unsignedp);
716 gcc_assert (GET_MODE (decl_rtl) == pmode);
717
718=== modified file 'gcc/genopinit.c'
719--- old/gcc/genopinit.c 2011-01-03 20:52:22 +0000
720+++ new/gcc/genopinit.c 2011-05-05 15:43:06 +0000
721@@ -74,6 +74,8 @@
722 "set_convert_optab_handler (fractuns_optab, $B, $A, CODE_FOR_$(fractuns$Q$a$I$b2$))",
723 "set_convert_optab_handler (satfract_optab, $B, $A, CODE_FOR_$(satfract$a$Q$b2$))",
724 "set_convert_optab_handler (satfractuns_optab, $B, $A, CODE_FOR_$(satfractuns$I$a$Q$b2$))",
725+ "set_convert_optab_handler (vec_load_lanes_optab, $A, $B, CODE_FOR_$(vec_load_lanes$a$b$))",
726+ "set_convert_optab_handler (vec_store_lanes_optab, $A, $B, CODE_FOR_$(vec_store_lanes$a$b$))",
727 "set_optab_handler (add_optab, $A, CODE_FOR_$(add$P$a3$))",
728 "set_optab_handler (addv_optab, $A, CODE_FOR_$(add$F$a3$)),\n\
729 set_optab_handler (add_optab, $A, CODE_FOR_$(add$F$a3$))",
730
731=== modified file 'gcc/gimple-low.c'
732--- old/gcc/gimple-low.c 2011-02-08 11:15:53 +0000
733+++ new/gcc/gimple-low.c 2011-05-05 15:42:22 +0000
734@@ -218,6 +218,10 @@
735 tree fndecl, parms, p;
736 unsigned int i, nargs;
737
738+ /* Calls to internal functions always match their signature. */
739+ if (gimple_call_internal_p (stmt))
740+ return true;
741+
742 nargs = gimple_call_num_args (stmt);
743
744 /* Get argument types for verification. */
745
746=== modified file 'gcc/gimple-pretty-print.c'
747--- old/gcc/gimple-pretty-print.c 2011-02-15 18:36:16 +0000
748+++ new/gcc/gimple-pretty-print.c 2011-05-05 15:42:22 +0000
749@@ -596,8 +596,12 @@
750
751 if (flags & TDF_RAW)
752 {
753- dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T",
754- gs, gimple_call_fn (gs), lhs);
755+ if (gimple_call_internal_p (gs))
756+ dump_gimple_fmt (buffer, spc, flags, "%G <%s, %T", gs,
757+ internal_fn_name (gimple_call_internal_fn (gs)), lhs);
758+ else
759+ dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T",
760+ gs, gimple_call_fn (gs), lhs);
761 if (gimple_call_num_args (gs) > 0)
762 {
763 pp_string (buffer, ", ");
764@@ -617,7 +621,10 @@
765
766 pp_space (buffer);
767 }
768- print_call_name (buffer, gimple_call_fn (gs), flags);
769+ if (gimple_call_internal_p (gs))
770+ pp_string (buffer, internal_fn_name (gimple_call_internal_fn (gs)));
771+ else
772+ print_call_name (buffer, gimple_call_fn (gs), flags);
773 pp_string (buffer, " (");
774 dump_gimple_call_args (buffer, gs, flags);
775 pp_character (buffer, ')');
776
777=== modified file 'gcc/gimple.c'
778--- old/gcc/gimple.c 2011-05-18 13:33:53 +0000
779+++ new/gcc/gimple.c 2011-06-02 12:12:00 +0000
780@@ -276,6 +276,59 @@
781 }
782
783
784+/* Helper for gimple_build_call_internal and gimple_build_call_internal_vec.
785+ Build the basic components of a GIMPLE_CALL statement to internal
786+ function FN with NARGS arguments. */
787+
788+static inline gimple
789+gimple_build_call_internal_1 (enum internal_fn fn, unsigned nargs)
790+{
791+ gimple s = gimple_build_with_ops (GIMPLE_CALL, ERROR_MARK, nargs + 3);
792+ s->gsbase.subcode |= GF_CALL_INTERNAL;
793+ gimple_call_set_internal_fn (s, fn);
794+ gimple_call_reset_alias_info (s);
795+ return s;
796+}
797+
798+
799+/* Build a GIMPLE_CALL statement to internal function FN. NARGS is
800+ the number of arguments. The ... are the arguments. */
801+
802+gimple
803+gimple_build_call_internal (enum internal_fn fn, unsigned nargs, ...)
804+{
805+ va_list ap;
806+ gimple call;
807+ unsigned i;
808+
809+ call = gimple_build_call_internal_1 (fn, nargs);
810+ va_start (ap, nargs);
811+ for (i = 0; i < nargs; i++)
812+ gimple_call_set_arg (call, i, va_arg (ap, tree));
813+ va_end (ap);
814+
815+ return call;
816+}
817+
818+
819+/* Build a GIMPLE_CALL statement to internal function FN with the arguments
820+ specified in vector ARGS. */
821+
822+gimple
823+gimple_build_call_internal_vec (enum internal_fn fn, VEC(tree, heap) *args)
824+{
825+ unsigned i, nargs;
826+ gimple call;
827+
828+ nargs = VEC_length (tree, args);
829+ call = gimple_build_call_internal_1 (fn, nargs);
830+ for (i = 0; i < nargs; i++)
831+ gimple_call_set_arg (call, i, VEC_index (tree, args, i));
832+
833+ return call;
834+}
835+
836+
837 /* Build a GIMPLE_CALL statement from CALL_EXPR T. Note that T is
838 assumed to be in GIMPLE form already. Minimal checking is done of
839 this fact. */
840@@ -1774,6 +1827,20 @@
841 return (gimple_body (fndecl) || (fn && fn->cfg));
842 }
843
844+/* Return true if calls C1 and C2 are known to go to the same function. */
845+
846+bool
847+gimple_call_same_target_p (const_gimple c1, const_gimple c2)
848+{
849+ if (gimple_call_internal_p (c1))
850+ return (gimple_call_internal_p (c2)
851+ && gimple_call_internal_fn (c1) == gimple_call_internal_fn (c2));
852+ else
853+ return (gimple_call_fn (c1) == gimple_call_fn (c2)
854+ || (gimple_call_fndecl (c1)
855+ && gimple_call_fndecl (c1) == gimple_call_fndecl (c2)));
856+}
857+
858 /* Detect flags from a GIMPLE_CALL. This is just like
859 call_expr_flags, but for gimple tuples. */
860
861@@ -1786,6 +1853,8 @@
862
863 if (decl)
864 flags = flags_from_decl_or_type (decl);
865+ else if (gimple_call_internal_p (stmt))
866+ flags = internal_fn_flags (gimple_call_internal_fn (stmt));
867 else
868 {
869 t = TREE_TYPE (gimple_call_fn (stmt));
870@@ -1801,18 +1870,35 @@
871 return flags;
872 }
873
874+/* Return the "fn spec" string for call STMT. */
875+
876+static tree
877+gimple_call_fnspec (const_gimple stmt)
878+{
879+ tree fn, type, attr;
880+
881+ fn = gimple_call_fn (stmt);
882+ if (!fn)
883+ return NULL_TREE;
884+
885+ type = TREE_TYPE (TREE_TYPE (fn));
886+ if (!type)
887+ return NULL_TREE;
888+
889+ attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
890+ if (!attr)
891+ return NULL_TREE;
892+
893+ return TREE_VALUE (TREE_VALUE (attr));
894+}
895+
896 /* Detects argument flags for argument number ARG on call STMT. */
897
898 int
899 gimple_call_arg_flags (const_gimple stmt, unsigned arg)
900 {
901- tree type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt)));
902- tree attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
903- if (!attr)
904- return 0;
905-
906- attr = TREE_VALUE (TREE_VALUE (attr));
907- if (1 + arg >= (unsigned) TREE_STRING_LENGTH (attr))
908+ tree attr = gimple_call_fnspec (stmt);
909+ if (!attr || 1 + arg >= (unsigned) TREE_STRING_LENGTH (attr))
910 return 0;
911
912 switch (TREE_STRING_POINTER (attr)[1 + arg])
913@@ -1850,13 +1936,8 @@
914 if (gimple_call_flags (stmt) & ECF_MALLOC)
915 return ERF_NOALIAS;
916
917- type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt)));
918- attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
919- if (!attr)
920- return 0;
921-
922- attr = TREE_VALUE (TREE_VALUE (attr));
923- if (TREE_STRING_LENGTH (attr) < 1)
924+ attr = gimple_call_fnspec (stmt);
925+ if (!attr || TREE_STRING_LENGTH (attr) < 1)
926 return 0;
927
928 switch (TREE_STRING_POINTER (attr)[0])
929@@ -2293,6 +2374,7 @@
930 if (is_gimple_call (s))
931 {
932 unsigned nargs = gimple_call_num_args (s);
933+ tree fn;
934
935 if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE)))
936 return true;
937@@ -2307,7 +2389,8 @@
938 return true;
939 }
940
941- if (TREE_SIDE_EFFECTS (gimple_call_fn (s)))
942+ fn = gimple_call_fn (s);
943+ if (fn && TREE_SIDE_EFFECTS (fn))
944 return true;
945
946 for (i = 0; i < nargs; i++)
947@@ -2349,14 +2432,15 @@
948 if (is_gimple_call (s))
949 {
950 unsigned nargs = gimple_call_num_args (s);
951+ tree fn;
952
953 if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE)))
954 return true;
955
956 /* We cannot use gimple_has_volatile_ops here,
957 because we must ignore a volatile LHS. */
958- if (TREE_SIDE_EFFECTS (gimple_call_fn (s))
959- || TREE_THIS_VOLATILE (gimple_call_fn (s)))
960+ fn = gimple_call_fn (s);
961+ if (fn && (TREE_SIDE_EFFECTS (fn) || TREE_THIS_VOLATILE (fn)))
962 {
963 gcc_assert (gimple_has_volatile_ops (s));
964 return true;
965@@ -3113,7 +3197,6 @@
966 gimple_call_copy_skip_args (gimple stmt, bitmap args_to_skip)
967 {
968 int i;
969- tree fn = gimple_call_fn (stmt);
970 int nargs = gimple_call_num_args (stmt);
971 VEC(tree, heap) *vargs = VEC_alloc (tree, heap, nargs);
972 gimple new_stmt;
973@@ -3122,7 +3205,11 @@
974 if (!bitmap_bit_p (args_to_skip, i))
975 VEC_quick_push (tree, vargs, gimple_call_arg (stmt, i));
976
977- new_stmt = gimple_build_call_vec (fn, vargs);
978+ if (gimple_call_internal_p (stmt))
979+ new_stmt = gimple_build_call_internal_vec (gimple_call_internal_fn (stmt),
980+ vargs);
981+ else
982+ new_stmt = gimple_build_call_vec (gimple_call_fn (stmt), vargs);
983 VEC_free (tree, heap, vargs);
984 if (gimple_call_lhs (stmt))
985 gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
986
987=== modified file 'gcc/gimple.h'
988--- old/gcc/gimple.h 2011-04-18 21:58:03 +0000
989+++ new/gcc/gimple.h 2011-06-02 12:12:00 +0000
990@@ -30,6 +30,7 @@
991 #include "basic-block.h"
992 #include "tree-ssa-operands.h"
993 #include "tree-ssa-alias.h"
994+#include "internal-fn.h"
995
996 struct gimple_seq_node_d;
997 typedef struct gimple_seq_node_d *gimple_seq_node;
998@@ -82,6 +83,8 @@
999 name, a _DECL, a _REF, etc. */
1000 };
1001
1002+#define GF_CALL_INTERNAL_FN_SHIFT 8
1003+
1004 /* Specific flags for individual GIMPLE statements. These flags are
1005 always stored in gimple_statement_base.subcode and they may only be
1006 defined for statement codes that do not use sub-codes.
1007@@ -102,6 +105,8 @@
1008 GF_CALL_TAILCALL = 1 << 3,
1009 GF_CALL_VA_ARG_PACK = 1 << 4,
1010 GF_CALL_NOTHROW = 1 << 5,
1011+ GF_CALL_INTERNAL = 1 << 6,
1012+ GF_CALL_INTERNAL_FN = 0xff << GF_CALL_INTERNAL_FN_SHIFT,
1013 GF_OMP_PARALLEL_COMBINED = 1 << 0,
1014
1015 /* True on an GIMPLE_OMP_RETURN statement if the return does not require
1016@@ -817,6 +822,8 @@
1017
1018 gimple gimple_build_call_vec (tree, VEC(tree, heap) *);
1019 gimple gimple_build_call (tree, unsigned, ...);
1020+gimple gimple_build_call_internal (enum internal_fn, unsigned, ...);
1021+gimple gimple_build_call_internal_vec (enum internal_fn, VEC(tree, heap) *);
1022 gimple gimple_build_call_from_tree (tree);
1023 gimple gimplify_assign (tree, tree, gimple_seq *);
1024 gimple gimple_build_cond (enum tree_code, tree, tree, tree, tree);
1025@@ -861,6 +868,7 @@
1026 void gimple_seq_free (gimple_seq);
1027 void gimple_seq_add_seq (gimple_seq *, gimple_seq);
1028 gimple_seq gimple_seq_copy (gimple_seq);
1029+bool gimple_call_same_target_p (const_gimple, const_gimple);
1030 int gimple_call_flags (const_gimple);
1031 int gimple_call_return_flags (const_gimple);
1032 int gimple_call_arg_flags (const_gimple, unsigned);
1033@@ -2012,6 +2020,27 @@
1034 }
1035
1036
1037+/* Return true if call GS calls an internal-only function, as enumerated
1038+ by internal_fn. */
1039+
1040+static inline bool
1041+gimple_call_internal_p (const_gimple gs)
1042+{
1043+ GIMPLE_CHECK (gs, GIMPLE_CALL);
1044+ return (gs->gsbase.subcode & GF_CALL_INTERNAL) != 0;
1045+}
1046+
1047+
1048+/* Return the target of internal call GS. */
1049+
1050+static inline enum internal_fn
1051+gimple_call_internal_fn (const_gimple gs)
1052+{
1053+ gcc_assert (gimple_call_internal_p (gs));
1054+ return (enum internal_fn) (gs->gsbase.subcode >> GF_CALL_INTERNAL_FN_SHIFT);
1055+}
1056+
1057+
1058 /* Return a pointer to the tree node representing the function called by call
1059 statement GS. */
1060
1061@@ -2029,6 +2058,7 @@
1062 gimple_call_set_fn (gimple gs, tree fn)
1063 {
1064 GIMPLE_CHECK (gs, GIMPLE_CALL);
1065+ gcc_assert (!gimple_call_internal_p (gs));
1066 gimple_set_op (gs, 1, fn);
1067 }
1068
1069@@ -2039,10 +2069,23 @@
1070 gimple_call_set_fndecl (gimple gs, tree decl)
1071 {
1072 GIMPLE_CHECK (gs, GIMPLE_CALL);
1073+ gcc_assert (!gimple_call_internal_p (gs));
1074 gimple_set_op (gs, 1, build_fold_addr_expr_loc (gimple_location (gs), decl));
1075 }
1076
1077
1078+/* Set internal function FN to be the function called by call statement GS. */
1079+
1080+static inline void
1081+gimple_call_set_internal_fn (gimple gs, enum internal_fn fn)
1082+{
1083+ GIMPLE_CHECK (gs, GIMPLE_CALL);
1084+ gcc_assert (gimple_call_internal_p (gs));
1085+ gs->gsbase.subcode &= ~GF_CALL_INTERNAL_FN;
1086+ gs->gsbase.subcode |= (int) fn << GF_CALL_INTERNAL_FN_SHIFT;
1087+}
1088+
1089+
1090 /* If a given GIMPLE_CALL's callee is a FUNCTION_DECL, return it.
1091 Otherwise return NULL. This function is analogous to
1092 get_callee_fndecl in tree land. */
1093@@ -2051,7 +2094,7 @@
1094 gimple_call_fndecl (const_gimple gs)
1095 {
1096 tree addr = gimple_call_fn (gs);
1097- if (TREE_CODE (addr) == ADDR_EXPR)
1098+ if (addr && TREE_CODE (addr) == ADDR_EXPR)
1099 {
1100 tree fndecl = TREE_OPERAND (addr, 0);
1101 if (TREE_CODE (fndecl) == MEM_REF)
1102@@ -2073,8 +2116,13 @@
1103 static inline tree
1104 gimple_call_return_type (const_gimple gs)
1105 {
1106- tree fn = gimple_call_fn (gs);
1107- tree type = TREE_TYPE (fn);
1108+ tree fn, type;
1109+
1110+ fn = gimple_call_fn (gs);
1111+ if (fn == NULL_TREE)
1112+ return TREE_TYPE (gimple_call_lhs (gs));
1113+
1114+ type = TREE_TYPE (fn);
1115
1116 /* See through the pointer. */
1117 type = TREE_TYPE (type);
1118
1119=== added file 'gcc/internal-fn.c'
1120--- old/gcc/internal-fn.c 1970-01-01 00:00:00 +0000
1121+++ new/gcc/internal-fn.c 2011-05-05 15:43:06 +0000
1122@@ -0,0 +1,147 @@
1123+/* Internal functions.
1124+ Copyright (C) 2011 Free Software Foundation, Inc.
1125+
1126+This file is part of GCC.
1127+
1128+GCC is free software; you can redistribute it and/or modify it under
1129+the terms of the GNU General Public License as published by the Free
1130+Software Foundation; either version 3, or (at your option) any later
1131+version.
1132+
1133+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
1134+WARRANTY; without even the implied warranty of MERCHANTABILITY or
1135+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1136+for more details.
1137+
1138+You should have received a copy of the GNU General Public License
1139+along with GCC; see the file COPYING3. If not see
1140+<http://www.gnu.org/licenses/>. */
1141+
1142+#include "config.h"
1143+#include "system.h"
1144+#include "coretypes.h"
1145+#include "gimple.h"
1146+#include "tree.h"
1147+#include "expr.h"
1148+#include "optabs.h"
1149+#include "recog.h"
1150+
1151+/* The names of each internal function, indexed by function number. */
1152+const char *const internal_fn_name_array[] = {
1153+#define DEF_INTERNAL_FN(CODE, FLAGS) #CODE,
1154+#include "internal-fn.def"
1155+#undef DEF_INTERNAL_FN
1156+ "<invalid-fn>"
1157+};
1158+
1159+/* The ECF_* flags of each internal function, indexed by function number. */
1160+const int internal_fn_flags_array[] = {
1161+#define DEF_INTERNAL_FN(CODE, FLAGS) FLAGS,
1162+#include "internal-fn.def"
1163+#undef DEF_INTERNAL_FN
1164+ 0
1165+};
1166+
1167+/* ARRAY_TYPE is an array of vector modes. Return the associated insn
1168+ for load-lanes-style optab OPTAB. The insn must exist. */
1169+
1170+static enum insn_code
1171+get_multi_vector_move (tree array_type, convert_optab optab)
1172+{
1173+ enum insn_code icode;
1174+ enum machine_mode imode;
1175+ enum machine_mode vmode;
1176+
1177+ gcc_assert (TREE_CODE (array_type) == ARRAY_TYPE);
1178+ imode = TYPE_MODE (array_type);
1179+ vmode = TYPE_MODE (TREE_TYPE (array_type));
1180+
1181+ icode = convert_optab_handler (optab, imode, vmode);
1182+ gcc_assert (icode != CODE_FOR_nothing);
1183+ return icode;
1184+}
1185+
1186+/* Expand LOAD_LANES call STMT. */
1187+
1188+static void
1189+expand_LOAD_LANES (gimple stmt)
1190+{
1191+ tree type, lhs, rhs;
1192+ rtx target, mem;
1193+ enum insn_code icode;
1194+ const struct insn_operand_data *operand;
1195+
1196+ lhs = gimple_call_lhs (stmt);
1197+ rhs = gimple_call_arg (stmt, 0);
1198+ type = TREE_TYPE (lhs);
1199+
1200+ target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
1201+ mem = expand_normal (rhs);
1202+
1203+ gcc_assert (REG_P (target));
1204+ gcc_assert (MEM_P (mem));
1205+ PUT_MODE (mem, TYPE_MODE (type));
1206+
1207+ icode = get_multi_vector_move (type, vec_load_lanes_optab);
1208+
1209+ operand = &insn_data[(int) icode].operand[1];
1210+ if (operand->predicate && !operand->predicate (mem, operand->mode))
1211+ mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0)));
1212+
1213+ emit_insn (GEN_FCN (icode) (target, mem));
1214+}
1215+
1216+/* Expand STORE_LANES call STMT. */
1217+
1218+static void
1219+expand_STORE_LANES (gimple stmt)
1220+{
1221+ tree type, lhs, rhs;
1222+ rtx target, reg;
1223+ enum insn_code icode;
1224+ const struct insn_operand_data *operand;
1225+
1226+ lhs = gimple_call_lhs (stmt);
1227+ rhs = gimple_call_arg (stmt, 0);
1228+ type = TREE_TYPE (rhs);
1229+
1230+ target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
1231+ reg = expand_normal (rhs);
1232+
1233+ gcc_assert (MEM_P (target));
1234+ PUT_MODE (target, TYPE_MODE (type));
1235+
1236+ icode = get_multi_vector_move (type, vec_store_lanes_optab);
1237+
1238+ operand = &insn_data[(int) icode].operand[0];
1239+ if (operand->predicate && !operand->predicate (target, operand->mode))
1240+ target = replace_equiv_address (target,
1241+ force_reg (Pmode, XEXP (target, 0)));
1242+
1243+ operand = &insn_data[(int) icode].operand[1];
1244+ if (operand->predicate && !operand->predicate (reg, operand->mode))
1245+ reg = force_reg (TYPE_MODE (type), reg);
1246+
1247+ emit_insn (GEN_FCN (icode) (target, reg));
1248+}
1249+
1250+/* Routines to expand each internal function, indexed by function number.
1251+ Each routine has the prototype:
1252+
1253+ expand_<NAME> (gimple stmt)
1254+
1255+ where STMT is the statement that performs the call. */
1256+static void (*const internal_fn_expanders[]) (gimple) = {
1257+#define DEF_INTERNAL_FN(CODE, FLAGS) expand_##CODE,
1258+#include "internal-fn.def"
1259+#undef DEF_INTERNAL_FN
1260+ 0
1261+};
1262+
1263+/* Expand STMT, which is a call to internal function FN. */
1264+
1265+void
1266+expand_internal_call (gimple stmt)
1267+{
1268+ internal_fn_expanders[(int) gimple_call_internal_fn (stmt)] (stmt);
1269+}
1270
1271=== added file 'gcc/internal-fn.def'
1272--- old/gcc/internal-fn.def 1970-01-01 00:00:00 +0000
1273+++ new/gcc/internal-fn.def 2011-05-05 15:43:06 +0000
1274@@ -0,0 +1,42 @@
1275+/* Internal functions.
1276+ Copyright (C) 2011 Free Software Foundation, Inc.
1277+
1278+This file is part of GCC.
1279+
1280+GCC is free software; you can redistribute it and/or modify it under
1281+the terms of the GNU General Public License as published by the Free
1282+Software Foundation; either version 3, or (at your option) any later
1283+version.
1284+
1285+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
1286+WARRANTY; without even the implied warranty of MERCHANTABILITY or
1287+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1288+for more details.
1289+
1290+You should have received a copy of the GNU General Public License
1291+along with GCC; see the file COPYING3. If not see
1292+<http://www.gnu.org/licenses/>. */
1293+
1294+/* This file specifies a list of internal "functions". These functions
1295+ differ from built-in functions in that they have no linkage and cannot
1296+ be called directly by the user. They represent operations that are only
1297+ synthesised by GCC itself.
1298+
1299+ Internal functions are used instead of tree codes if the operation
1300+ and its operands are more naturally represented as a GIMPLE_CALL
1301+ than a GIMPLE_ASSIGN.
1302+
1303+ Each entry in this file has the form:
1304+
1305+ DEF_INTERNAL_FN (NAME, FLAGS)
1306+
1307+ where NAME is the name of the function and FLAGS is a set of
1308+ ECF_* flags. Each entry must have a corresponding expander
1309+ of the form:
1310+
1311+ void expand_NAME (gimple stmt)
1312+
1313+ where STMT is the statement that performs the call. */
1314+
1315+DEF_INTERNAL_FN (LOAD_LANES, ECF_CONST | ECF_LEAF)
1316+DEF_INTERNAL_FN (STORE_LANES, ECF_CONST | ECF_LEAF)
1317
1318=== added file 'gcc/internal-fn.h'
1319--- old/gcc/internal-fn.h 1970-01-01 00:00:00 +0000
1320+++ new/gcc/internal-fn.h 2011-05-05 15:42:22 +0000
1321@@ -0,0 +1,52 @@
1322+/* Internal functions.
1323+ Copyright (C) 2011 Free Software Foundation, Inc.
1324+
1325+This file is part of GCC.
1326+
1327+GCC is free software; you can redistribute it and/or modify it under
1328+the terms of the GNU General Public License as published by the Free
1329+Software Foundation; either version 3, or (at your option) any later
1330+version.
1331+
1332+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
1333+WARRANTY; without even the implied warranty of MERCHANTABILITY or
1334+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1335+for more details.
1336+
1337+You should have received a copy of the GNU General Public License
1338+along with GCC; see the file COPYING3. If not see
1339+<http://www.gnu.org/licenses/>. */
1340+
1341+#ifndef GCC_INTERNAL_FN_H
1342+#define GCC_INTERNAL_FN_H
1343+
1344+enum internal_fn {
1345+#define DEF_INTERNAL_FN(CODE, FLAGS) IFN_##CODE,
1346+#include "internal-fn.def"
1347+#undef DEF_INTERNAL_FN
1348+ IFN_LAST
1349+};
1350+
1351+extern const char *const internal_fn_name_array[];
1352+extern const int internal_fn_flags_array[];
1353+
1354+/* Return the name of internal function FN. The name is only meaningful
1355+ for dumps; it has no linkage. */
1356+
1357+static inline const char *
1358+internal_fn_name (enum internal_fn fn)
1359+{
1360+ return internal_fn_name_array[(int) fn];
1361+}
1362+
1363+/* Return the ECF_* flags for function FN. */
1364+
1365+static inline int
1366+internal_fn_flags (enum internal_fn fn)
1367+{
1368+ return internal_fn_flags_array[(int) fn];
1369+}
1370+
1371+extern void expand_internal_call (gimple);
1372+
1373+#endif
1374
1375=== modified file 'gcc/ipa-prop.c'
1376--- old/gcc/ipa-prop.c 2011-04-18 21:58:03 +0000
1377+++ new/gcc/ipa-prop.c 2011-06-02 12:12:00 +0000
1378@@ -1418,6 +1418,8 @@
1379 {
1380 tree target = gimple_call_fn (call);
1381
1382+ if (!target)
1383+ return;
1384 if (TREE_CODE (target) == SSA_NAME)
1385 ipa_analyze_indirect_call_uses (node, info, parms_info, call, target);
1386 else if (TREE_CODE (target) == OBJ_TYPE_REF)
1387
1388=== modified file 'gcc/optabs.h'
1389--- old/gcc/optabs.h 2011-01-03 20:52:22 +0000
1390+++ new/gcc/optabs.h 2011-05-05 15:43:06 +0000
1391@@ -578,6 +578,9 @@
1392 COI_satfract,
1393 COI_satfractuns,
1394
1395+ COI_vec_load_lanes,
1396+ COI_vec_store_lanes,
1397+
1398 COI_MAX
1399 };
1400
1401@@ -598,6 +601,8 @@
1402 #define fractuns_optab (&convert_optab_table[COI_fractuns])
1403 #define satfract_optab (&convert_optab_table[COI_satfract])
1404 #define satfractuns_optab (&convert_optab_table[COI_satfractuns])
1405+#define vec_load_lanes_optab (&convert_optab_table[COI_vec_load_lanes])
1406+#define vec_store_lanes_optab (&convert_optab_table[COI_vec_store_lanes])
1407
1408 /* Contains the optab used for each rtx code. */
1409 extern optab code_to_optab[NUM_RTX_CODE + 1];
1410
1411=== modified file 'gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c'
1412--- old/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c 2009-04-20 10:26:18 +0000
1413+++ new/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c 2011-05-05 15:46:10 +0000
1414@@ -26,7 +26,7 @@
1415 }
1416 }
1417
1418-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided_wide } } } */
1419-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided_wide } } } */
1420+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
1421+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */
1422 /* { dg-final { cleanup-tree-dump "vect" } } */
1423
1424
1425=== modified file 'gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c'
1426--- old/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c 2010-11-22 12:16:52 +0000
1427+++ new/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c 2011-05-05 15:46:10 +0000
1428@@ -113,7 +113,7 @@
1429 return 0;
1430 }
1431
1432-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" {target { vect_strided && vect_int_mult } } } } */
1433-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided && vect_int_mult } } } } */
1434+/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" {target { vect_strided8 && vect_int_mult } } } } */
1435+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided8 && vect_int_mult } } } } */
1436 /* { dg-final { cleanup-tree-dump "vect" } } */
1437
1438
1439=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c'
1440--- old/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c 2008-08-26 08:14:37 +0000
1441+++ new/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c 2011-05-05 15:44:00 +0000
1442@@ -20,7 +20,7 @@
1443 return avg;
1444 }
1445
1446-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
1447-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
1448+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd } } } */
1449+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd } } } */
1450 /* { dg-final { cleanup-tree-dump "vect" } } */
1451
1452
1453=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c'
1454--- old/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c 2010-08-26 11:13:58 +0000
1455+++ new/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c 2011-05-05 15:46:10 +0000
1456@@ -13,5 +13,5 @@
1457 }
1458 }
1459
1460-/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided } } } */
1461+/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided2 } } } */
1462 /* { dg-final { cleanup-tree-dump "vect" } } */
1463
1464=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c'
1465--- old/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c 2010-11-22 12:16:52 +0000
1466+++ new/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c 2011-05-05 15:46:10 +0000
1467@@ -56,5 +56,5 @@
1468 return 0;
1469 }
1470
1471-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
1472+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
1473 /* { dg-final { cleanup-tree-dump "vect" } } */
1474
1475=== modified file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c'
1476--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-04-24 07:45:49 +0000
1477+++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-05-05 15:46:10 +0000
1478@@ -65,5 +65,5 @@
1479 return 0;
1480 }
1481
1482-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
1483+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || { ! vect_strided2 } } } } } */
1484 /* { dg-final { cleanup-tree-dump "vect" } } */
1485
1486=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c'
1487--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c 2007-09-04 12:05:19 +0000
1488+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c 2011-05-05 15:46:10 +0000
1489@@ -54,5 +54,5 @@
1490 return 0;
1491 }
1492
1493-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
1494+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
1495 /* { dg-final { cleanup-tree-dump "vect" } } */
1496
1497=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c'
1498--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c 2007-09-04 12:05:19 +0000
1499+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c 2011-05-05 15:46:10 +0000
1500@@ -53,5 +53,5 @@
1501 return 0;
1502 }
1503
1504-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
1505+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
1506 /* { dg-final { cleanup-tree-dump "vect" } } */
1507
1508=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c'
1509--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c 2007-10-21 09:01:16 +0000
1510+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c 2011-05-05 15:46:10 +0000
1511@@ -47,5 +47,5 @@
1512 return 0;
1513 }
1514
1515-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_interleave } } } */
1516+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
1517 /* { dg-final { cleanup-tree-dump "vect" } } */
1518
1519=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c'
1520--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c 2007-09-04 12:05:19 +0000
1521+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c 2011-05-05 15:46:10 +0000
1522@@ -50,5 +50,5 @@
1523 return 0;
1524 }
1525
1526-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
1527+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
1528 /* { dg-final { cleanup-tree-dump "vect" } } */
1529
1530=== modified file 'gcc/testsuite/gcc.dg/vect/pr30843.c'
1531--- old/gcc/testsuite/gcc.dg/vect/pr30843.c 2007-02-22 12:30:12 +0000
1532+++ new/gcc/testsuite/gcc.dg/vect/pr30843.c 2011-05-05 15:46:10 +0000
1533@@ -20,6 +20,6 @@
1534 }
1535 }
1536
1537-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
1538+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided4 } } } } */
1539 /* { dg-final { cleanup-tree-dump "vect" } } */
1540
1541
1542=== modified file 'gcc/testsuite/gcc.dg/vect/pr33866.c'
1543--- old/gcc/testsuite/gcc.dg/vect/pr33866.c 2007-10-30 08:26:14 +0000
1544+++ new/gcc/testsuite/gcc.dg/vect/pr33866.c 2011-05-05 15:46:10 +0000
1545@@ -27,6 +27,6 @@
1546 }
1547
1548 /* Needs interleaving support. */
1549-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
1550+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
1551 /* { dg-final { cleanup-tree-dump "vect" } } */
1552
1553
1554=== modified file 'gcc/testsuite/gcc.dg/vect/pr37539.c'
1555--- old/gcc/testsuite/gcc.dg/vect/pr37539.c 2009-11-26 02:03:50 +0000
1556+++ new/gcc/testsuite/gcc.dg/vect/pr37539.c 2011-05-05 15:46:10 +0000
1557@@ -40,7 +40,7 @@
1558 return 0;
1559 }
1560
1561-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_strided_wide } } } */
1562+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_strided4 && vect_strided2 } } } } */
1563 /* { dg-final { cleanup-tree-dump "vect" } } */
1564
1565
1566
1567=== removed file 'gcc/testsuite/gcc.dg/vect/slp-11.c'
1568--- old/gcc/testsuite/gcc.dg/vect/slp-11.c 2010-11-22 12:16:52 +0000
1569+++ new/gcc/testsuite/gcc.dg/vect/slp-11.c 1970-01-01 00:00:00 +0000
1570@@ -1,113 +0,0 @@
1571-/* { dg-require-effective-target vect_int } */
1572-
1573-#include <stdarg.h>
1574-#include "tree-vect.h"
1575-
1576-#define N 8
1577-
1578-int
1579-main1 ()
1580-{
1581- int i;
1582- unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1583- unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1584- float out2[N*8];
1585-
1586- /* Different operations - not SLPable. */
1587- for (i = 0; i < N; i++)
1588- {
1589- a0 = in[i*8] + 5;
1590- a1 = in[i*8 + 1] * 6;
1591- a2 = in[i*8 + 2] + 7;
1592- a3 = in[i*8 + 3] + 8;
1593- a4 = in[i*8 + 4] + 9;
1594- a5 = in[i*8 + 5] + 10;
1595- a6 = in[i*8 + 6] + 11;
1596- a7 = in[i*8 + 7] + 12;
1597-
1598- b0 = a0 * 3;
1599- b1 = a1 * 2;
1600- b2 = a2 * 12;
1601- b3 = a3 * 5;
1602- b4 = a4 * 8;
1603- b5 = a5 * 4;
1604- b6 = a6 * 3;
1605- b7 = a7 * 2;
1606-
1607- out[i*8] = b0 - 2;
1608- out[i*8 + 1] = b1 - 3;
1609- out[i*8 + 2] = b2 - 2;
1610- out[i*8 + 3] = b3 - 1;
1611- out[i*8 + 4] = b4 - 8;
1612- out[i*8 + 5] = b5 - 7;
1613- out[i*8 + 6] = b6 - 3;
1614- out[i*8 + 7] = b7 - 7;
1615- }
1616-
1617- /* check results: */
1618- for (i = 0; i < N; i++)
1619- {
1620- if (out[i*8] != (in[i*8] + 5) * 3 - 2
1621- || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3
1622- || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2
1623- || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1
1624- || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8
1625- || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7
1626- || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3
1627- || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7)
1628- abort ();
1629- }
1630-
1631- /* Requires permutation - not SLPable. */
1632- for (i = 0; i < N*2; i++)
1633- {
1634- out[i*4] = (in[i*4] + 2) * 3;
1635- out[i*4 + 1] = (in[i*4 + 2] + 2) * 7;
1636- out[i*4 + 2] = (in[i*4 + 1] + 7) * 3;
1637- out[i*4 + 3] = (in[i*4 + 3] + 3) * 4;
1638- }
1639-
1640- /* check results: */
1641- for (i = 0; i < N*2; i++)
1642- {
1643- if (out[i*4] != (in[i*4] + 2) * 3
1644- || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7
1645- || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3
1646- || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4)
1647- abort ();
1648- }
1649-
1650- /* Different operations - not SLPable. */
1651- for (i = 0; i < N*4; i++)
1652- {
1653- out2[i*2] = ((float) in[i*2] * 2 + 6) ;
1654- out2[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7);
1655- }
1656-
1657- /* check results: */
1658- for (i = 0; i < N*4; i++)
1659- {
1660- if (out2[i*2] != ((float) in[i*2] * 2 + 6)
1661- || out2[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7))
1662- abort ();
1663- }
1664-
1665-
1666- return 0;
1667-}
1668-
1669-int main (void)
1670-{
1671- check_vect ();
1672-
1673- main1 ();
1674-
1675- return 0;
1676-}
1677-
1678-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { { vect_uintfloat_cvt && vect_strided_wide } && vect_int_mult } } } } */
1679-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { { { ! vect_uintfloat_cvt } && vect_strided_wide } && vect_int_mult } } } } */
1680-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! { vect_int_mult && vect_strided_wide } } } } } */
1681-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1682-/* { dg-final { cleanup-tree-dump "vect" } } */
1683-
1684
1685=== added file 'gcc/testsuite/gcc.dg/vect/slp-11a.c'
1686--- old/gcc/testsuite/gcc.dg/vect/slp-11a.c 1970-01-01 00:00:00 +0000
1687+++ new/gcc/testsuite/gcc.dg/vect/slp-11a.c 2011-05-05 15:46:10 +0000
1688@@ -0,0 +1,75 @@
1689+/* { dg-require-effective-target vect_int } */
1690+
1691+#include <stdarg.h>
1692+#include "tree-vect.h"
1693+
1694+#define N 8
1695+
1696+int
1697+main1 ()
1698+{
1699+ int i;
1700+ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1701+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1702+
1703+ /* Different operations - not SLPable. */
1704+ for (i = 0; i < N; i++)
1705+ {
1706+ a0 = in[i*8] + 5;
1707+ a1 = in[i*8 + 1] * 6;
1708+ a2 = in[i*8 + 2] + 7;
1709+ a3 = in[i*8 + 3] + 8;
1710+ a4 = in[i*8 + 4] + 9;
1711+ a5 = in[i*8 + 5] + 10;
1712+ a6 = in[i*8 + 6] + 11;
1713+ a7 = in[i*8 + 7] + 12;
1714+
1715+ b0 = a0 * 3;
1716+ b1 = a1 * 2;
1717+ b2 = a2 * 12;
1718+ b3 = a3 * 5;
1719+ b4 = a4 * 8;
1720+ b5 = a5 * 4;
1721+ b6 = a6 * 3;
1722+ b7 = a7 * 2;
1723+
1724+ out[i*8] = b0 - 2;
1725+ out[i*8 + 1] = b1 - 3;
1726+ out[i*8 + 2] = b2 - 2;
1727+ out[i*8 + 3] = b3 - 1;
1728+ out[i*8 + 4] = b4 - 8;
1729+ out[i*8 + 5] = b5 - 7;
1730+ out[i*8 + 6] = b6 - 3;
1731+ out[i*8 + 7] = b7 - 7;
1732+ }
1733+
1734+ /* check results: */
1735+ for (i = 0; i < N; i++)
1736+ {
1737+ if (out[i*8] != (in[i*8] + 5) * 3 - 2
1738+ || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3
1739+ || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2
1740+ || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1
1741+ || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8
1742+ || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7
1743+ || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3
1744+ || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7)
1745+ abort ();
1746+ }
1747+
1748+ return 0;
1749+}
1750+
1751+int main (void)
1752+{
1753+ check_vect ();
1754+
1755+ main1 ();
1756+
1757+ return 0;
1758+}
1759+
1760+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
1761+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
1762+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1763+/* { dg-final { cleanup-tree-dump "vect" } } */
1764
1765=== added file 'gcc/testsuite/gcc.dg/vect/slp-11b.c'
1766--- old/gcc/testsuite/gcc.dg/vect/slp-11b.c 1970-01-01 00:00:00 +0000
1767+++ new/gcc/testsuite/gcc.dg/vect/slp-11b.c 2011-05-05 15:46:10 +0000
1768@@ -0,0 +1,49 @@
1769+/* { dg-require-effective-target vect_int } */
1770+
1771+#include <stdarg.h>
1772+#include "tree-vect.h"
1773+
1774+#define N 8
1775+
1776+int
1777+main1 ()
1778+{
1779+ int i;
1780+ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1781+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1782+
1783+ /* Requires permutation - not SLPable. */
1784+ for (i = 0; i < N*2; i++)
1785+ {
1786+ out[i*4] = (in[i*4] + 2) * 3;
1787+ out[i*4 + 1] = (in[i*4 + 2] + 2) * 7;
1788+ out[i*4 + 2] = (in[i*4 + 1] + 7) * 3;
1789+ out[i*4 + 3] = (in[i*4 + 3] + 3) * 4;
1790+ }
1791+
1792+ /* check results: */
1793+ for (i = 0; i < N*2; i++)
1794+ {
1795+ if (out[i*4] != (in[i*4] + 2) * 3
1796+ || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7
1797+ || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3
1798+ || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4)
1799+ abort ();
1800+ }
1801+
1802+ return 0;
1803+}
1804+
1805+int main (void)
1806+{
1807+ check_vect ();
1808+
1809+ main1 ();
1810+
1811+ return 0;
1812+}
1813+
1814+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided4 && vect_int_mult } } } } */
1815+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided4 && vect_int_mult } } } } } */
1816+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1817+/* { dg-final { cleanup-tree-dump "vect" } } */
1818
1819=== added file 'gcc/testsuite/gcc.dg/vect/slp-11c.c'
1820--- old/gcc/testsuite/gcc.dg/vect/slp-11c.c 1970-01-01 00:00:00 +0000
1821+++ new/gcc/testsuite/gcc.dg/vect/slp-11c.c 2011-05-05 15:46:10 +0000
1822@@ -0,0 +1,46 @@
1823+/* { dg-require-effective-target vect_int } */
1824+
1825+#include <stdarg.h>
1826+#include "tree-vect.h"
1827+
1828+#define N 8
1829+
1830+int
1831+main1 ()
1832+{
1833+ int i;
1834+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1835+ float out[N*8];
1836+
1837+ /* Different operations - not SLPable. */
1838+ for (i = 0; i < N*4; i++)
1839+ {
1840+ out[i*2] = ((float) in[i*2] * 2 + 6) ;
1841+ out[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7);
1842+ }
1843+
1844+ /* check results: */
1845+ for (i = 0; i < N*4; i++)
1846+ {
1847+ if (out[i*2] != ((float) in[i*2] * 2 + 6)
1848+ || out[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7))
1849+ abort ();
1850+ }
1851+
1852+
1853+ return 0;
1854+}
1855+
1856+int main (void)
1857+{
1858+ check_vect ();
1859+
1860+ main1 ();
1861+
1862+ return 0;
1863+}
1864+
1865+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } */
1866+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } } */
1867+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1868+/* { dg-final { cleanup-tree-dump "vect" } } */
1869
1870=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12a.c'
1871--- old/gcc/testsuite/gcc.dg/vect/slp-12a.c 2010-11-22 12:16:52 +0000
1872+++ new/gcc/testsuite/gcc.dg/vect/slp-12a.c 2011-05-05 15:46:10 +0000
1873@@ -11,7 +11,7 @@
1874 int i;
1875 unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1876 unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1877- unsigned int ia[N], ib[N*2];
1878+ unsigned int ia[N];
1879
1880 for (i = 0; i < N; i++)
1881 {
1882@@ -61,27 +61,6 @@
1883 abort ();
1884 }
1885
1886- for (i = 0; i < N*2; i++)
1887- {
1888- out[i*4] = (in[i*4] + 2) * 3;
1889- out[i*4 + 1] = (in[i*4 + 1] + 2) * 7;
1890- out[i*4 + 2] = (in[i*4 + 2] + 7) * 3;
1891- out[i*4 + 3] = (in[i*4 + 3] + 7) * 7;
1892-
1893- ib[i] = 7;
1894- }
1895-
1896- /* check results: */
1897- for (i = 0; i < N*2; i++)
1898- {
1899- if (out[i*4] != (in[i*4] + 2) * 3
1900- || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7
1901- || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3
1902- || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7
1903- || ib[i] != 7)
1904- abort ();
1905- }
1906-
1907 return 0;
1908 }
1909
1910@@ -94,11 +73,8 @@
1911 return 0;
1912 }
1913
1914-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult} } } } */
1915-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
1916-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! vect_int_mult } } } } */
1917-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
1918-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
1919-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { ! vect_int_mult } } } } */
1920+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
1921+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
1922+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
1923+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
1924 /* { dg-final { cleanup-tree-dump "vect" } } */
1925-
1926
1927=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12b.c'
1928--- old/gcc/testsuite/gcc.dg/vect/slp-12b.c 2010-11-22 12:16:52 +0000
1929+++ new/gcc/testsuite/gcc.dg/vect/slp-12b.c 2011-05-05 15:46:10 +0000
1930@@ -43,9 +43,9 @@
1931 return 0;
1932 }
1933
1934-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
1935-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
1936-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
1937-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
1938+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided2 && vect_int_mult } } } } */
1939+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided2 && vect_int_mult } } } } } */
1940+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_strided2 && vect_int_mult } } } } */
1941+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided2 && vect_int_mult } } } } } */
1942 /* { dg-final { cleanup-tree-dump "vect" } } */
1943
1944
1945=== added file 'gcc/testsuite/gcc.dg/vect/slp-12c.c'
1946--- old/gcc/testsuite/gcc.dg/vect/slp-12c.c 1970-01-01 00:00:00 +0000
1947+++ new/gcc/testsuite/gcc.dg/vect/slp-12c.c 2011-05-05 15:44:41 +0000
1948@@ -0,0 +1,53 @@
1949+/* { dg-require-effective-target vect_int } */
1950+
1951+#include <stdarg.h>
1952+#include "tree-vect.h"
1953+
1954+#define N 8
1955+
1956+int
1957+main1 ()
1958+{
1959+ int i;
1960+ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1961+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1962+ unsigned int ia[N*2];
1963+
1964+ for (i = 0; i < N*2; i++)
1965+ {
1966+ out[i*4] = (in[i*4] + 2) * 3;
1967+ out[i*4 + 1] = (in[i*4 + 1] + 2) * 7;
1968+ out[i*4 + 2] = (in[i*4 + 2] + 7) * 3;
1969+ out[i*4 + 3] = (in[i*4 + 3] + 7) * 7;
1970+
1971+ ia[i] = 7;
1972+ }
1973+
1974+ /* check results: */
1975+ for (i = 0; i < N*2; i++)
1976+ {
1977+ if (out[i*4] != (in[i*4] + 2) * 3
1978+ || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7
1979+ || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3
1980+ || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7
1981+ || ia[i] != 7)
1982+ abort ();
1983+ }
1984+
1985+ return 0;
1986+}
1987+
1988+int main (void)
1989+{
1990+ check_vect ();
1991+
1992+ main1 ();
1993+
1994+ return 0;
1995+}
1996+
1997+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_int_mult } } } } */
1998+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_int_mult } } } } */
1999+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_int_mult } } } */
2000+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_int_mult } } } } */
2001+/* { dg-final { cleanup-tree-dump "vect" } } */
2002
2003=== modified file 'gcc/testsuite/gcc.dg/vect/slp-18.c'
2004--- old/gcc/testsuite/gcc.dg/vect/slp-18.c 2010-11-22 12:16:52 +0000
2005+++ new/gcc/testsuite/gcc.dg/vect/slp-18.c 2011-05-05 15:46:10 +0000
2006@@ -91,7 +91,7 @@
2007 return 0;
2008 }
2009
2010-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided } } } } */
2011-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_strided } } } } */
2012+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2013+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided8 } } } */
2014 /* { dg-final { cleanup-tree-dump "vect" } } */
2015
2016
2017=== removed file 'gcc/testsuite/gcc.dg/vect/slp-19.c'
2018--- old/gcc/testsuite/gcc.dg/vect/slp-19.c 2010-11-22 12:16:52 +0000
2019+++ new/gcc/testsuite/gcc.dg/vect/slp-19.c 1970-01-01 00:00:00 +0000
2020@@ -1,154 +0,0 @@
2021-/* { dg-require-effective-target vect_int } */
2022-
2023-#include <stdarg.h>
2024-#include "tree-vect.h"
2025-
2026-#define N 16
2027-
2028-int
2029-main1 ()
2030-{
2031- unsigned int i;
2032- unsigned int out[N*8];
2033- unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2034- unsigned int ia[N*2], a0, a1, a2, a3;
2035-
2036- for (i = 0; i < N; i++)
2037- {
2038- out[i*8] = in[i*8];
2039- out[i*8 + 1] = in[i*8 + 1];
2040- out[i*8 + 2] = in[i*8 + 2];
2041- out[i*8 + 3] = in[i*8 + 3];
2042- out[i*8 + 4] = in[i*8 + 4];
2043- out[i*8 + 5] = in[i*8 + 5];
2044- out[i*8 + 6] = in[i*8 + 6];
2045- out[i*8 + 7] = in[i*8 + 7];
2046-
2047- ia[i] = in[i*8 + 2];
2048- }
2049-
2050- /* check results: */
2051- for (i = 0; i < N; i++)
2052- {
2053- if (out[i*8] != in[i*8]
2054- || out[i*8 + 1] != in[i*8 + 1]
2055- || out[i*8 + 2] != in[i*8 + 2]
2056- || out[i*8 + 3] != in[i*8 + 3]
2057- || out[i*8 + 4] != in[i*8 + 4]
2058- || out[i*8 + 5] != in[i*8 + 5]
2059- || out[i*8 + 6] != in[i*8 + 6]
2060- || out[i*8 + 7] != in[i*8 + 7]
2061- || ia[i] != in[i*8 + 2])
2062- abort ();
2063- }
2064-
2065- for (i = 0; i < N*2; i++)
2066- {
2067- a0 = in[i*4] + 1;
2068- a1 = in[i*4 + 1] + 2;
2069- a2 = in[i*4 + 2] + 3;
2070- a3 = in[i*4 + 3] + 4;
2071-
2072- out[i*4] = a0;
2073- out[i*4 + 1] = a1;
2074- out[i*4 + 2] = a2;
2075- out[i*4 + 3] = a3;
2076-
2077- ia[i] = a2;
2078- }
2079-
2080- /* check results: */
2081- for (i = 0; i < N*2; i++)
2082- {
2083- if (out[i*4] != in[i*4] + 1
2084- || out[i*4 + 1] != in[i*4 + 1] + 2
2085- || out[i*4 + 2] != in[i*4 + 2] + 3
2086- || out[i*4 + 3] != in[i*4 + 3] + 4
2087- || ia[i] != in[i*4 + 2] + 3)
2088- abort ();
2089- }
2090-
2091- /* The last stmt requires interleaving of not power of 2 size - not
2092- vectorizable. */
2093- for (i = 0; i < N/2; i++)
2094- {
2095- out[i*12] = in[i*12];
2096- out[i*12 + 1] = in[i*12 + 1];
2097- out[i*12 + 2] = in[i*12 + 2];
2098- out[i*12 + 3] = in[i*12 + 3];
2099- out[i*12 + 4] = in[i*12 + 4];
2100- out[i*12 + 5] = in[i*12 + 5];
2101- out[i*12 + 6] = in[i*12 + 6];
2102- out[i*12 + 7] = in[i*12 + 7];
2103- out[i*12 + 8] = in[i*12 + 8];
2104- out[i*12 + 9] = in[i*12 + 9];
2105- out[i*12 + 10] = in[i*12 + 10];
2106- out[i*12 + 11] = in[i*12 + 11];
2107-
2108- ia[i] = in[i*12 + 7];
2109- }
2110-
2111- /* check results: */
2112- for (i = 0; i < N/2; i++)
2113- {
2114- if (out[i*12] != in[i*12]
2115- || out[i*12 + 1] != in[i*12 + 1]
2116- || out[i*12 + 2] != in[i*12 + 2]
2117- || out[i*12 + 3] != in[i*12 + 3]
2118- || out[i*12 + 4] != in[i*12 + 4]
2119- || out[i*12 + 5] != in[i*12 + 5]
2120- || out[i*12 + 6] != in[i*12 + 6]
2121- || out[i*12 + 7] != in[i*12 + 7]
2122- || out[i*12 + 8] != in[i*12 + 8]
2123- || out[i*12 + 9] != in[i*12 + 9]
2124- || out[i*12 + 10] != in[i*12 + 10]
2125- || out[i*12 + 11] != in[i*12 + 11]
2126- || ia[i] != in[i*12 + 7])
2127- abort ();
2128- }
2129-
2130- /* Hybrid SLP with unrolling by 2. */
2131- for (i = 0; i < N; i++)
2132- {
2133- out[i*6] = in[i*6];
2134- out[i*6 + 1] = in[i*6 + 1];
2135- out[i*6 + 2] = in[i*6 + 2];
2136- out[i*6 + 3] = in[i*6 + 3];
2137- out[i*6 + 4] = in[i*6 + 4];
2138- out[i*6 + 5] = in[i*6 + 5];
2139-
2140- ia[i] = i;
2141- }
2142-
2143- /* check results: */
2144- for (i = 0; i < N/2; i++)
2145- {
2146- if (out[i*6] != in[i*6]
2147- || out[i*6 + 1] != in[i*6 + 1]
2148- || out[i*6 + 2] != in[i*6 + 2]
2149- || out[i*6 + 3] != in[i*6 + 3]
2150- || out[i*6 + 4] != in[i*6 + 4]
2151- || out[i*6 + 5] != in[i*6 + 5]
2152- || ia[i] != i)
2153- abort ();
2154- }
2155-
2156-
2157- return 0;
2158-}
2159-
2160-int main (void)
2161-{
2162- check_vect ();
2163-
2164- main1 ();
2165-
2166- return 0;
2167-}
2168-
2169-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target vect_strided_wide } } } */
2170-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide } } } } } */
2171-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" { target vect_strided_wide } } } */
2172-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! { vect_strided_wide } } } } } */
2173-/* { dg-final { cleanup-tree-dump "vect" } } */
2174-
2175
2176=== added file 'gcc/testsuite/gcc.dg/vect/slp-19a.c'
2177--- old/gcc/testsuite/gcc.dg/vect/slp-19a.c 1970-01-01 00:00:00 +0000
2178+++ new/gcc/testsuite/gcc.dg/vect/slp-19a.c 2011-05-05 15:46:10 +0000
2179@@ -0,0 +1,61 @@
2180+/* { dg-require-effective-target vect_int } */
2181+
2182+#include <stdarg.h>
2183+#include "tree-vect.h"
2184+
2185+#define N 16
2186+
2187+int
2188+main1 ()
2189+{
2190+ unsigned int i;
2191+ unsigned int out[N*8];
2192+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2193+ unsigned int ia[N*2];
2194+
2195+ for (i = 0; i < N; i++)
2196+ {
2197+ out[i*8] = in[i*8];
2198+ out[i*8 + 1] = in[i*8 + 1];
2199+ out[i*8 + 2] = in[i*8 + 2];
2200+ out[i*8 + 3] = in[i*8 + 3];
2201+ out[i*8 + 4] = in[i*8 + 4];
2202+ out[i*8 + 5] = in[i*8 + 5];
2203+ out[i*8 + 6] = in[i*8 + 6];
2204+ out[i*8 + 7] = in[i*8 + 7];
2205+
2206+ ia[i] = in[i*8 + 2];
2207+ }
2208+
2209+ /* check results: */
2210+ for (i = 0; i < N; i++)
2211+ {
2212+ if (out[i*8] != in[i*8]
2213+ || out[i*8 + 1] != in[i*8 + 1]
2214+ || out[i*8 + 2] != in[i*8 + 2]
2215+ || out[i*8 + 3] != in[i*8 + 3]
2216+ || out[i*8 + 4] != in[i*8 + 4]
2217+ || out[i*8 + 5] != in[i*8 + 5]
2218+ || out[i*8 + 6] != in[i*8 + 6]
2219+ || out[i*8 + 7] != in[i*8 + 7]
2220+ || ia[i] != in[i*8 + 2])
2221+ abort ();
2222+ }
2223+
2224+ return 0;
2225+}
2226+
2227+int main (void)
2228+{
2229+ check_vect ();
2230+
2231+ main1 ();
2232+
2233+ return 0;
2234+}
2235+
2236+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2237+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided8 } } } } */
2238+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided8 } } } */
2239+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided8} } } } */
2240+/* { dg-final { cleanup-tree-dump "vect" } } */
2241
2242=== added file 'gcc/testsuite/gcc.dg/vect/slp-19b.c'
2243--- old/gcc/testsuite/gcc.dg/vect/slp-19b.c 1970-01-01 00:00:00 +0000
2244+++ new/gcc/testsuite/gcc.dg/vect/slp-19b.c 2011-05-05 15:46:10 +0000
2245@@ -0,0 +1,58 @@
2246+/* { dg-require-effective-target vect_int } */
2247+
2248+#include <stdarg.h>
2249+#include "tree-vect.h"
2250+
2251+#define N 16
2252+
2253+int
2254+main1 ()
2255+{
2256+ unsigned int i;
2257+ unsigned int out[N*8];
2258+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2259+ unsigned int ia[N*2], a0, a1, a2, a3;
2260+
2261+ for (i = 0; i < N*2; i++)
2262+ {
2263+ a0 = in[i*4] + 1;
2264+ a1 = in[i*4 + 1] + 2;
2265+ a2 = in[i*4 + 2] + 3;
2266+ a3 = in[i*4 + 3] + 4;
2267+
2268+ out[i*4] = a0;
2269+ out[i*4 + 1] = a1;
2270+ out[i*4 + 2] = a2;
2271+ out[i*4 + 3] = a3;
2272+
2273+ ia[i] = a2;
2274+ }
2275+
2276+ /* check results: */
2277+ for (i = 0; i < N*2; i++)
2278+ {
2279+ if (out[i*4] != in[i*4] + 1
2280+ || out[i*4 + 1] != in[i*4 + 1] + 2
2281+ || out[i*4 + 2] != in[i*4 + 2] + 3
2282+ || out[i*4 + 3] != in[i*4 + 3] + 4
2283+ || ia[i] != in[i*4 + 2] + 3)
2284+ abort ();
2285+ }
2286+
2287+ return 0;
2288+}
2289+
2290+int main (void)
2291+{
2292+ check_vect ();
2293+
2294+ main1 ();
2295+
2296+ return 0;
2297+}
2298+
2299+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2300+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided4 } } } } */
2301+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */
2302+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided4 } } } } */
2303+/* { dg-final { cleanup-tree-dump "vect" } } */
2304
2305=== added file 'gcc/testsuite/gcc.dg/vect/slp-19c.c'
2306--- old/gcc/testsuite/gcc.dg/vect/slp-19c.c 1970-01-01 00:00:00 +0000
2307+++ new/gcc/testsuite/gcc.dg/vect/slp-19c.c 2011-05-05 15:44:41 +0000
2308@@ -0,0 +1,95 @@
2309+/* { dg-require-effective-target vect_int } */
2310+
2311+#include <stdarg.h>
2312+#include "tree-vect.h"
2313+
2314+#define N 16
2315+
2316+int
2317+main1 ()
2318+{
2319+ unsigned int i;
2320+ unsigned int out[N*8];
2321+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2322+ unsigned int ia[N*2], a0, a1, a2, a3;
2323+
2324+ /* The last stmt requires interleaving of not power of 2 size - not
2325+ vectorizable. */
2326+ for (i = 0; i < N/2; i++)
2327+ {
2328+ out[i*12] = in[i*12];
2329+ out[i*12 + 1] = in[i*12 + 1];
2330+ out[i*12 + 2] = in[i*12 + 2];
2331+ out[i*12 + 3] = in[i*12 + 3];
2332+ out[i*12 + 4] = in[i*12 + 4];
2333+ out[i*12 + 5] = in[i*12 + 5];
2334+ out[i*12 + 6] = in[i*12 + 6];
2335+ out[i*12 + 7] = in[i*12 + 7];
2336+ out[i*12 + 8] = in[i*12 + 8];
2337+ out[i*12 + 9] = in[i*12 + 9];
2338+ out[i*12 + 10] = in[i*12 + 10];
2339+ out[i*12 + 11] = in[i*12 + 11];
2340+
2341+ ia[i] = in[i*12 + 7];
2342+ }
2343+
2344+ /* check results: */
2345+ for (i = 0; i < N/2; i++)
2346+ {
2347+ if (out[i*12] != in[i*12]
2348+ || out[i*12 + 1] != in[i*12 + 1]
2349+ || out[i*12 + 2] != in[i*12 + 2]
2350+ || out[i*12 + 3] != in[i*12 + 3]
2351+ || out[i*12 + 4] != in[i*12 + 4]
2352+ || out[i*12 + 5] != in[i*12 + 5]
2353+ || out[i*12 + 6] != in[i*12 + 6]
2354+ || out[i*12 + 7] != in[i*12 + 7]
2355+ || out[i*12 + 8] != in[i*12 + 8]
2356+ || out[i*12 + 9] != in[i*12 + 9]
2357+ || out[i*12 + 10] != in[i*12 + 10]
2358+ || out[i*12 + 11] != in[i*12 + 11]
2359+ || ia[i] != in[i*12 + 7])
2360+ abort ();
2361+ }
2362+
2363+ /* Hybrid SLP with unrolling by 2. */
2364+ for (i = 0; i < N; i++)
2365+ {
2366+ out[i*6] = in[i*6];
2367+ out[i*6 + 1] = in[i*6 + 1];
2368+ out[i*6 + 2] = in[i*6 + 2];
2369+ out[i*6 + 3] = in[i*6 + 3];
2370+ out[i*6 + 4] = in[i*6 + 4];
2371+ out[i*6 + 5] = in[i*6 + 5];
2372+
2373+ ia[i] = i;
2374+ }
2375+
2376+ /* check results: */
2377+ for (i = 0; i < N/2; i++)
2378+ {
2379+ if (out[i*6] != in[i*6]
2380+ || out[i*6 + 1] != in[i*6 + 1]
2381+ || out[i*6 + 2] != in[i*6 + 2]
2382+ || out[i*6 + 3] != in[i*6 + 3]
2383+ || out[i*6 + 4] != in[i*6 + 4]
2384+ || out[i*6 + 5] != in[i*6 + 5]
2385+ || ia[i] != i)
2386+ abort ();
2387+ }
2388+
2389+ return 0;
2390+}
2391+
2392+int main (void)
2393+{
2394+ check_vect ();
2395+
2396+ main1 ();
2397+
2398+ return 0;
2399+}
2400+
2401+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
2402+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */
2403+/* { dg-final { cleanup-tree-dump "vect" } } */
2404
2405=== modified file 'gcc/testsuite/gcc.dg/vect/slp-21.c'
2406--- old/gcc/testsuite/gcc.dg/vect/slp-21.c 2010-11-22 12:16:52 +0000
2407+++ new/gcc/testsuite/gcc.dg/vect/slp-21.c 2011-05-05 15:46:10 +0000
2408@@ -199,9 +199,9 @@
2409 return 0;
2410 }
2411
2412-/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target { vect_strided || vect_extract_even_odd } } } } */
2413-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided || vect_extract_even_odd } } } } } */
2414-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided } } } */
2415-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided } } } } } */
2416+/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target { vect_strided4 || vect_extract_even_odd } } } } */
2417+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided4 || vect_extract_even_odd } } } } } */
2418+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided4 } } } */
2419+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided4 } } } } } */
2420 /* { dg-final { cleanup-tree-dump "vect" } } */
2421
2422
2423=== modified file 'gcc/testsuite/gcc.dg/vect/slp-23.c'
2424--- old/gcc/testsuite/gcc.dg/vect/slp-23.c 2011-01-10 12:51:00 +0000
2425+++ new/gcc/testsuite/gcc.dg/vect/slp-23.c 2011-05-05 15:46:10 +0000
2426@@ -106,8 +106,8 @@
2427 return 0;
2428 }
2429
2430-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided_wide } && {! { vect_no_align} } } } } */
2431-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide || vect_no_align} } } } } */
2432+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided8 && { ! { vect_no_align} } } } } } */
2433+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided8 || vect_no_align } } } } } */
2434 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */
2435 /* { dg-final { cleanup-tree-dump "vect" } } */
2436
2437
2438=== modified file 'gcc/testsuite/gcc.dg/vect/slp-reduc-6.c'
2439--- old/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c 2010-11-22 12:16:52 +0000
2440+++ new/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c 2011-05-05 15:46:10 +0000
2441@@ -42,7 +42,7 @@
2442 return 0;
2443 }
2444
2445-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! vect_unpack } } } } } */
2446+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! { vect_unpack || vect_strided2 } } } } } } */
2447 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
2448 /* { dg-final { scan-tree-dump-times "different interleaving chains in one node" 1 "vect" { target { ! vect_no_int_add } } } } */
2449 /* { dg-final { cleanup-tree-dump "vect" } } */
2450
2451=== modified file 'gcc/testsuite/gcc.dg/vect/vect-1.c'
2452--- old/gcc/testsuite/gcc.dg/vect/vect-1.c 2010-08-19 10:23:50 +0000
2453+++ new/gcc/testsuite/gcc.dg/vect/vect-1.c 2011-05-05 15:46:10 +0000
2454@@ -85,6 +85,6 @@
2455 fbar (a);
2456 }
2457
2458-/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
2459-/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
2460+/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_strided2 } } } */
2461+/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_strided2 } } } */
2462 /* { dg-final { cleanup-tree-dump "vect" } } */
2463
2464=== modified file 'gcc/testsuite/gcc.dg/vect/vect-10.c'
2465--- old/gcc/testsuite/gcc.dg/vect/vect-10.c 2010-05-27 12:23:45 +0000
2466+++ new/gcc/testsuite/gcc.dg/vect/vect-10.c 2011-05-05 15:46:10 +0000
2467@@ -22,5 +22,5 @@
2468 return 0;
2469 }
2470
2471-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_extract_even_odd } } } } */
2472+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_strided2 } } } } */
2473 /* { dg-final { cleanup-tree-dump "vect" } } */
2474
2475=== modified file 'gcc/testsuite/gcc.dg/vect/vect-107.c'
2476--- old/gcc/testsuite/gcc.dg/vect/vect-107.c 2008-08-19 08:06:54 +0000
2477+++ new/gcc/testsuite/gcc.dg/vect/vect-107.c 2011-05-05 15:46:10 +0000
2478@@ -40,6 +40,6 @@
2479 return main1 ();
2480 }
2481
2482-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
2483-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
2484+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2485+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */
2486 /* { dg-final { cleanup-tree-dump "vect" } } */
2487
2488=== modified file 'gcc/testsuite/gcc.dg/vect/vect-98.c'
2489--- old/gcc/testsuite/gcc.dg/vect/vect-98.c 2008-08-02 11:05:47 +0000
2490+++ new/gcc/testsuite/gcc.dg/vect/vect-98.c 2011-05-05 15:46:10 +0000
2491@@ -38,6 +38,6 @@
2492 }
2493
2494 /* Needs interleaving support. */
2495-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
2496-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */
2497+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2498+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail vect_strided4 } } } */
2499 /* { dg-final { cleanup-tree-dump "vect" } } */
2500
2501=== modified file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c'
2502--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-03-27 09:38:18 +0000
2503+++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-05-05 15:46:10 +0000
2504@@ -82,5 +82,5 @@
2505 return 0;
2506 }
2507
2508-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
2509+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || { ! vect_strided2 } } } } } */
2510 /* { dg-final { cleanup-tree-dump "vect" } } */
2511
2512=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c'
2513--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c 2007-09-04 12:05:19 +0000
2514+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c 2011-05-05 15:46:10 +0000
2515@@ -71,6 +71,6 @@
2516 return 0;
2517 }
2518
2519-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2520+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2521 /* { dg-final { cleanup-tree-dump "vect" } } */
2522
2523
2524=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c'
2525--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c 2007-09-04 12:05:19 +0000
2526+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c 2011-05-05 15:46:10 +0000
2527@@ -55,6 +55,6 @@
2528 return 0;
2529 }
2530
2531-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2532+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2533 /* { dg-final { cleanup-tree-dump "vect" } } */
2534
2535
2536=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c'
2537--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c 2007-09-04 12:05:19 +0000
2538+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c 2011-05-05 15:46:10 +0000
2539@@ -68,6 +68,6 @@
2540 return 0;
2541 }
2542
2543-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2544+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2545 /* { dg-final { cleanup-tree-dump "vect" } } */
2546
2547
2548=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c'
2549--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c 2007-09-04 12:05:19 +0000
2550+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c 2011-05-05 15:46:10 +0000
2551@@ -62,6 +62,6 @@
2552 return 0;
2553 }
2554
2555-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2556+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2557 /* { dg-final { cleanup-tree-dump "vect" } } */
2558
2559
2560=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c'
2561--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c 2010-05-27 12:23:45 +0000
2562+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c 2011-05-05 15:46:10 +0000
2563@@ -61,6 +61,6 @@
2564 return 0;
2565 }
2566
2567-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2568+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2569 /* { dg-final { cleanup-tree-dump "vect" } } */
2570
2571
2572=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c'
2573--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c 2007-09-04 12:05:19 +0000
2574+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c 2011-05-05 15:46:10 +0000
2575@@ -69,6 +69,6 @@
2576 return 0;
2577 }
2578
2579-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2580+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2581 /* { dg-final { cleanup-tree-dump "vect" } } */
2582
2583
2584=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c'
2585--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c 2010-11-22 12:16:52 +0000
2586+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c 2011-05-05 15:46:10 +0000
2587@@ -76,6 +76,6 @@
2588 return 0;
2589 }
2590
2591-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2592+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2593 /* { dg-final { cleanup-tree-dump "vect" } } */
2594
2595
2596=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c'
2597--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c 2007-09-04 12:05:19 +0000
2598+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c 2011-05-05 15:46:10 +0000
2599@@ -81,6 +81,6 @@
2600 return 0;
2601 }
2602
2603-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2604+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2605 /* { dg-final { cleanup-tree-dump "vect" } } */
2606
2607
2608=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-float.c'
2609--- old/gcc/testsuite/gcc.dg/vect/vect-strided-float.c 2008-08-19 08:06:54 +0000
2610+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-float.c 2011-05-05 15:46:10 +0000
2611@@ -39,7 +39,7 @@
2612 }
2613
2614 /* Needs interleaving support. */
2615-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
2616-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */
2617+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2618+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */
2619 /* { dg-final { cleanup-tree-dump "vect" } } */
2620
2621
2622=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c'
2623--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c 2007-09-04 12:05:19 +0000
2624+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c 2011-05-05 15:46:10 +0000
2625@@ -71,6 +71,6 @@
2626 return 0;
2627 }
2628
2629-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2630+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2631 /* { dg-final { cleanup-tree-dump "vect" } } */
2632
2633
2634=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult.c'
2635--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c 2007-09-04 12:05:19 +0000
2636+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c 2011-05-05 15:46:10 +0000
2637@@ -71,6 +71,6 @@
2638 return 0;
2639 }
2640
2641-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2642+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2643 /* { dg-final { cleanup-tree-dump "vect" } } */
2644
2645
2646=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c'
2647--- old/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c 2007-09-04 12:05:19 +0000
2648+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c 2011-05-05 15:46:10 +0000
2649@@ -72,5 +72,5 @@
2650 return 0;
2651 }
2652
2653-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2654+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2655 /* { dg-final { cleanup-tree-dump "vect" } } */
2656
2657=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c'
2658--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c 2008-08-12 05:31:57 +0000
2659+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c 2011-05-05 15:46:10 +0000
2660@@ -55,6 +55,6 @@
2661 return 0;
2662 }
2663
2664-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
2665+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
2666 /* { dg-final { cleanup-tree-dump "vect" } } */
2667
2668
2669=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c'
2670--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c 2007-10-21 09:01:16 +0000
2671+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c 2011-05-05 15:46:10 +0000
2672@@ -65,8 +65,8 @@
2673 return 0;
2674 }
2675
2676-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_interleave && vect_pack_trunc } } } } */
2677-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { ! { vect_interleave } } && { vect_pack_trunc } } } } } */
2678+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_interleave || vect_strided4 } && vect_pack_trunc } } } } */
2679+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { ! { vect_interleave || vect_strided4 } } && { vect_pack_trunc } } } } } */
2680 /* { dg-final { cleanup-tree-dump "vect" } } */
2681
2682
2683
2684=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c'
2685--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c 2010-11-22 12:16:52 +0000
2686+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c 2011-05-05 15:46:10 +0000
2687@@ -39,7 +39,7 @@
2688 }
2689
2690 /* Needs interleaving support. */
2691-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
2692-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave } } } } */
2693+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
2694+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave || vect_strided2 } } } } */
2695 /* { dg-final { cleanup-tree-dump "vect" } } */
2696
2697
2698=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c'
2699--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c 2007-09-04 12:05:19 +0000
2700+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c 2011-05-05 15:46:10 +0000
2701@@ -55,6 +55,6 @@
2702 return 0;
2703 }
2704
2705-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2706+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2707 /* { dg-final { cleanup-tree-dump "vect" } } */
2708
2709
2710=== added file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c'
2711--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c 1970-01-01 00:00:00 +0000
2712+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c 2011-05-05 15:46:25 +0000
2713@@ -0,0 +1,112 @@
2714+#include <stdarg.h>
2715+#include "tree-vect.h"
2716+
2717+#define N 128
2718+
2719+typedef struct {
2720+ unsigned short a;
2721+ unsigned short b;
2722+ unsigned short c;
2723+} s;
2724+
2725+#define A(I) (I)
2726+#define B(I) ((I) * 2)
2727+#define C(I) ((unsigned short) ~((I) ^ 0x18))
2728+
2729+void __attribute__ ((noinline))
2730+check1 (s *res)
2731+{
2732+ int i;
2733+
2734+ for (i = 0; i < N; i++)
2735+ if (res[i].a != C (i)
2736+ || res[i].b != A (i)
2737+ || res[i].c != B (i))
2738+ abort ();
2739+}
2740+
2741+void __attribute__ ((noinline))
2742+check2 (unsigned short *res)
2743+{
2744+ int i;
2745+
2746+ for (i = 0; i < N; i++)
2747+ if (res[i] != (unsigned short) (A (i) + B (i) + C (i)))
2748+ abort ();
2749+}
2750+
2751+void __attribute__ ((noinline))
2752+check3 (s *res)
2753+{
2754+ int i;
2755+
2756+ for (i = 0; i < N; i++)
2757+ if (res[i].a != i
2758+ || res[i].b != i
2759+ || res[i].c != i)
2760+ abort ();
2761+}
2762+
2763+void __attribute__ ((noinline))
2764+check4 (unsigned short *res)
2765+{
2766+ int i;
2767+
2768+ for (i = 0; i < N; i++)
2769+ if (res[i] != (unsigned short) (A (i) + B (i)))
2770+ abort ();
2771+}
2772+
2773+void __attribute__ ((noinline))
2774+main1 (s *arr)
2775+{
2776+ int i;
2777+ s *ptr = arr;
2778+ s res1[N];
2779+ unsigned short res2[N];
2780+
2781+ for (i = 0; i < N; i++)
2782+ {
2783+ res1[i].a = arr[i].c;
2784+ res1[i].b = arr[i].a;
2785+ res1[i].c = arr[i].b;
2786+ }
2787+ check1 (res1);
2788+
2789+ for (i = 0; i < N; i++)
2790+ res2[i] = arr[i].a + arr[i].b + arr[i].c;
2791+ check2 (res2);
2792+
2793+ for (i = 0; i < N; i++)
2794+ {
2795+ res1[i].a = i;
2796+ res1[i].b = i;
2797+ res1[i].c = i;
2798+ }
2799+ check3 (res1);
2800+
2801+ for (i = 0; i < N; i++)
2802+ res2[i] = arr[i].a + arr[i].b;
2803+ check4 (res2);
2804+}
2805+
2806+int main (void)
2807+{
2808+ int i;
2809+ s arr[N];
2810+
2811+ check_vect ();
2812+
2813+ for (i = 0; i < N; i++)
2814+ {
2815+ arr[i].a = A (i);
2816+ arr[i].b = B (i);
2817+ arr[i].c = C (i);
2818+ }
2819+ main1 (arr);
2820+
2821+ return 0;
2822+}
2823+
2824+/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target vect_strided3 } } } */
2825+/* { dg-final { cleanup-tree-dump "vect" } } */
2826
2827=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c'
2828--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c 2007-09-04 12:05:19 +0000
2829+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c 2011-05-05 15:46:10 +0000
2830@@ -68,6 +68,6 @@
2831 return 0;
2832 }
2833
2834-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2835+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2836 /* { dg-final { cleanup-tree-dump "vect" } } */
2837
2838
2839=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c'
2840--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c 2007-09-04 12:05:19 +0000
2841+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c 2011-05-05 15:46:10 +0000
2842@@ -63,6 +63,6 @@
2843 return 0;
2844 }
2845
2846-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2847+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2848 /* { dg-final { cleanup-tree-dump "vect" } } */
2849
2850
2851=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c'
2852--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c 2007-09-04 12:05:19 +0000
2853+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c 2011-05-05 15:46:10 +0000
2854@@ -77,6 +77,6 @@
2855 return 0;
2856 }
2857
2858-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2859+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2860 /* { dg-final { cleanup-tree-dump "vect" } } */
2861
2862
2863=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c'
2864--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c 2010-05-27 12:23:45 +0000
2865+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c 2011-05-05 15:46:10 +0000
2866@@ -60,6 +60,6 @@
2867 return 0;
2868 }
2869
2870-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2871+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2872 /* { dg-final { cleanup-tree-dump "vect" } } */
2873
2874
2875=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c'
2876--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c 2007-09-04 12:05:19 +0000
2877+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c 2011-05-05 15:46:10 +0000
2878@@ -71,6 +71,6 @@
2879 return 0;
2880 }
2881
2882-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2883+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2884 /* { dg-final { cleanup-tree-dump "vect" } } */
2885
2886
2887=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c'
2888--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c 2007-09-04 12:05:19 +0000
2889+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c 2011-05-05 15:46:10 +0000
2890@@ -54,6 +54,6 @@
2891 return 0;
2892 }
2893
2894-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2895+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2896 /* { dg-final { cleanup-tree-dump "vect" } } */
2897
2898
2899=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c'
2900--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c 2010-11-22 12:16:52 +0000
2901+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c 2011-05-05 15:46:10 +0000
2902@@ -78,6 +78,6 @@
2903 return 0;
2904 }
2905
2906-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2907+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2908 /* { dg-final { cleanup-tree-dump "vect" } } */
2909
2910
2911=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c'
2912--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c 2007-09-04 12:05:19 +0000
2913+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c 2011-05-05 15:46:10 +0000
2914@@ -98,6 +98,6 @@
2915 return 0;
2916 }
2917
2918-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2919+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2920 /* { dg-final { cleanup-tree-dump "vect" } } */
2921
2922
2923=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c'
2924--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c 2007-09-04 12:05:19 +0000
2925+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c 2011-05-05 15:46:10 +0000
2926@@ -83,6 +83,6 @@
2927 return 0;
2928 }
2929
2930-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2931+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2932 /* { dg-final { cleanup-tree-dump "vect" } } */
2933
2934
2935=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c'
2936--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c 2010-11-22 12:16:52 +0000
2937+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c 2011-05-05 15:46:10 +0000
2938@@ -85,6 +85,6 @@
2939 return 0;
2940 }
2941
2942-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2943+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2944 /* { dg-final { cleanup-tree-dump "vect" } } */
2945
2946
2947=== modified file 'gcc/testsuite/gcc.dg/vect/vect-vfa-03.c'
2948--- old/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c 2007-09-09 07:46:12 +0000
2949+++ new/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c 2011-05-05 15:46:10 +0000
2950@@ -53,6 +53,6 @@
2951 }
2952
2953 /* Needs interleaving support. */
2954-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2955-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd } } } } */
2956+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2957+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail vect_strided2 } } } */
2958 /* { dg-final { cleanup-tree-dump "vect" } } */
2959
2960=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
2961--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2011-04-24 07:45:49 +0000
2962+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-05-05 15:43:31 +0000
2963@@ -75,15 +75,20 @@
2964 lappend VECT_SLP_CFLAGS "-fdump-tree-slp-details"
2965
2966 # Main loop.
2967-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]] \
2968- "" $DEFAULT_VECTCFLAGS
2969-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]] \
2970- "" $DEFAULT_VECTCFLAGS
2971-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]] \
2972- "" $DEFAULT_VECTCFLAGS
2973-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]] \
2974- "" $VECT_SLP_CFLAGS
2975-
2976+set VECT_ADDITIONAL_FLAGS [list ""]
2977+if { [check_effective_target_lto] } {
2978+ lappend VECT_ADDITIONAL_FLAGS "-flto"
2979+}
2980+foreach flags $VECT_ADDITIONAL_FLAGS {
2981+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]] \
2982+ $flags $DEFAULT_VECTCFLAGS
2983+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]] \
2984+ $flags $DEFAULT_VECTCFLAGS
2985+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]] \
2986+ $flags $DEFAULT_VECTCFLAGS
2987+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]] \
2988+ $flags $VECT_SLP_CFLAGS
2989+}
2990
2991 #### Tests with special options
2992 global SAVED_DEFAULT_VECTCFLAGS
2993
2994=== modified file 'gcc/testsuite/lib/target-supports.exp'
2995--- old/gcc/testsuite/lib/target-supports.exp 2011-05-06 11:28:27 +0000
2996+++ new/gcc/testsuite/lib/target-supports.exp 2011-06-02 12:12:00 +0000
2997@@ -3139,29 +3139,6 @@
2998 return $et_vect_extract_even_odd_saved
2999 }
3000
3001-# Return 1 if the target supports vector even/odd elements extraction of
3002-# vectors with SImode elements or larger, 0 otherwise.
3003-
3004-proc check_effective_target_vect_extract_even_odd_wide { } {
3005- global et_vect_extract_even_odd_wide_saved
3006-
3007- if [info exists et_vect_extract_even_odd_wide_saved] {
3008- verbose "check_effective_target_vect_extract_even_odd_wide: using cached result" 2
3009- } else {
3010- set et_vect_extract_even_odd_wide_saved 0
3011- if { [istarget powerpc*-*-*]
3012- || [istarget i?86-*-*]
3013- || [istarget x86_64-*-*]
3014- || [istarget ia64-*-*]
3015- || [istarget spu-*-*] } {
3016- set et_vect_extract_even_odd_wide_saved 1
3017- }
3018- }
3019-
3020- verbose "check_effective_target_vect_extract_even_wide_odd: returning $et_vect_extract_even_odd_wide_saved" 2
3021- return $et_vect_extract_even_odd_wide_saved
3022-}
3023-
3024 # Return 1 if the target supports vector interleaving, 0 otherwise.
3025
3026 proc check_effective_target_vect_interleave { } {
3027@@ -3184,41 +3161,30 @@
3028 return $et_vect_interleave_saved
3029 }
3030
3031-# Return 1 if the target supports vector interleaving and extract even/odd, 0 otherwise.
3032-proc check_effective_target_vect_strided { } {
3033- global et_vect_strided_saved
3034-
3035- if [info exists et_vect_strided_saved] {
3036- verbose "check_effective_target_vect_strided: using cached result" 2
3037- } else {
3038- set et_vect_strided_saved 0
3039- if { [check_effective_target_vect_interleave]
3040- && [check_effective_target_vect_extract_even_odd] } {
3041- set et_vect_strided_saved 1
3042- }
3043- }
3044-
3045- verbose "check_effective_target_vect_strided: returning $et_vect_strided_saved" 2
3046- return $et_vect_strided_saved
3047-}
3048-
3049-# Return 1 if the target supports vector interleaving and extract even/odd
3050-# for wide element types, 0 otherwise.
3051-proc check_effective_target_vect_strided_wide { } {
3052- global et_vect_strided_wide_saved
3053-
3054- if [info exists et_vect_strided_wide_saved] {
3055- verbose "check_effective_target_vect_strided_wide: using cached result" 2
3056- } else {
3057- set et_vect_strided_wide_saved 0
3058- if { [check_effective_target_vect_interleave]
3059- && [check_effective_target_vect_extract_even_odd_wide] } {
3060- set et_vect_strided_wide_saved 1
3061- }
3062- }
3063-
3064- verbose "check_effective_target_vect_strided_wide: returning $et_vect_strided_wide_saved" 2
3065- return $et_vect_strided_wide_saved
3066+foreach N {2 3 4 8} {
3067+ eval [string map [list N $N] {
3068+ # Return 1 if the target supports 2-vector interleaving
3069+ proc check_effective_target_vect_stridedN { } {
3070+ global et_vect_stridedN_saved
3071+
3072+ if [info exists et_vect_stridedN_saved] {
3073+ verbose "check_effective_target_vect_stridedN: using cached result" 2
3074+ } else {
3075+ set et_vect_stridedN_saved 0
3076+ if { (N & -N) == N
3077+ && [check_effective_target_vect_interleave]
3078+ && [check_effective_target_vect_extract_even_odd] } {
3079+ set et_vect_stridedN_saved 1
3080+ }
3081+ if { [istarget arm*-*-*] && N >= 2 && N <= 4 } {
3082+ set et_vect_stridedN_saved 1
3083+ }
3084+ }
3085+
3086+ verbose "check_effective_target_vect_stridedN: returning $et_vect_stridedN_saved" 2
3087+ return $et_vect_stridedN_saved
3088+ }
3089+ }]
3090 }
3091
3092 # Return 1 if the target supports section-anchors
3093
3094=== modified file 'gcc/tree-cfg.c'
3095--- old/gcc/tree-cfg.c 2011-02-12 21:11:33 +0000
3096+++ new/gcc/tree-cfg.c 2011-05-05 15:42:22 +0000
3097@@ -3046,7 +3046,26 @@
3098 tree fntype;
3099 unsigned i;
3100
3101- if (TREE_CODE (fn) != OBJ_TYPE_REF
3102+ if (gimple_call_internal_p (stmt))
3103+ {
3104+ if (fn)
3105+ {
3106+ error ("gimple call has two targets");
3107+ debug_generic_stmt (fn);
3108+ return true;
3109+ }
3110+ }
3111+ else
3112+ {
3113+ if (!fn)
3114+ {
3115+ error ("gimple call has no target");
3116+ return true;
3117+ }
3118+ }
3119+
3120+ if (fn
3121+ && TREE_CODE (fn) != OBJ_TYPE_REF
3122 && !is_gimple_val (fn))
3123 {
3124 error ("invalid function in gimple call");
3125@@ -3054,9 +3073,10 @@
3126 return true;
3127 }
3128
3129- if (!POINTER_TYPE_P (TREE_TYPE (fn))
3130- || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE
3131- && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE))
3132+ if (fn
3133+ && (!POINTER_TYPE_P (TREE_TYPE (fn))
3134+ || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE
3135+ && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE)))
3136 {
3137 error ("non-function in gimple call");
3138 return true;
3139@@ -3076,8 +3096,12 @@
3140 return true;
3141 }
3142
3143- fntype = TREE_TYPE (TREE_TYPE (fn));
3144- if (gimple_call_lhs (stmt)
3145+ if (fn)
3146+ fntype = TREE_TYPE (TREE_TYPE (fn));
3147+ else
3148+ fntype = NULL_TREE;
3149+ if (fntype
3150+ && gimple_call_lhs (stmt)
3151 && !useless_type_conversion_p (TREE_TYPE (gimple_call_lhs (stmt)),
3152 TREE_TYPE (fntype))
3153 /* ??? At least C++ misses conversions at assignments from
3154@@ -4130,9 +4154,10 @@
3155 didn't see a function declaration before the call. */
3156 if (is_gimple_call (stmt))
3157 {
3158- tree decl;
3159+ tree fn, decl;
3160
3161- if (!is_gimple_call_addr (gimple_call_fn (stmt)))
3162+ fn = gimple_call_fn (stmt);
3163+ if (fn && !is_gimple_call_addr (fn))
3164 {
3165 error ("invalid function in call statement");
3166 return true;
3167@@ -7484,6 +7509,8 @@
3168 case GIMPLE_CALL:
3169 if (gimple_call_lhs (g))
3170 break;
3171+ if (gimple_call_internal_p (g))
3172+ break;
3173
3174 /* This is a naked call, as opposed to a GIMPLE_CALL with an
3175 LHS. All calls whose value is ignored should be
3176
3177=== modified file 'gcc/tree-eh.c'
3178--- old/gcc/tree-eh.c 2011-05-10 06:31:59 +0000
3179+++ new/gcc/tree-eh.c 2011-06-02 12:12:00 +0000
3180@@ -2745,7 +2745,7 @@
3181 || gimple_call_lhs (twos)
3182 || gimple_call_chain (ones)
3183 || gimple_call_chain (twos)
3184- || !operand_equal_p (gimple_call_fn (ones), gimple_call_fn (twos), 0)
3185+ || !gimple_call_same_target_p (ones, twos)
3186 || gimple_call_num_args (ones) != gimple_call_num_args (twos))
3187 return false;
3188
3189
3190=== modified file 'gcc/tree-inline.c'
3191--- old/gcc/tree-inline.c 2011-05-05 21:02:06 +0000
3192+++ new/gcc/tree-inline.c 2011-06-02 12:12:00 +0000
3193@@ -3471,10 +3471,13 @@
3194 {
3195 tree decl = gimple_call_fndecl (stmt);
3196 tree addr = gimple_call_fn (stmt);
3197- tree funtype = TREE_TYPE (addr);
3198+ tree funtype = NULL_TREE;
3199 bool stdarg = false;
3200
3201- if (POINTER_TYPE_P (funtype))
3202+ if (addr)
3203+ funtype = TREE_TYPE (addr);
3204+
3205+ if (funtype && POINTER_TYPE_P (funtype))
3206 funtype = TREE_TYPE (funtype);
3207
3208 /* Do not special case builtins where we see the body.
3209@@ -3514,7 +3517,7 @@
3210 if (decl)
3211 funtype = TREE_TYPE (decl);
3212
3213- if (!VOID_TYPE_P (TREE_TYPE (funtype)))
3214+ if (funtype && !VOID_TYPE_P (TREE_TYPE (funtype)))
3215 cost += estimate_move_cost (TREE_TYPE (funtype));
3216
3217 if (funtype)
3218
3219=== modified file 'gcc/tree-ssa-ccp.c'
3220--- old/gcc/tree-ssa-ccp.c 2011-01-31 16:52:22 +0000
3221+++ new/gcc/tree-ssa-ccp.c 2011-05-05 15:42:22 +0000
3222@@ -1279,7 +1279,10 @@
3223
3224 case GIMPLE_CALL:
3225 {
3226- tree fn = valueize_op (gimple_call_fn (stmt));
3227+ tree fn = gimple_call_fn (stmt);
3228+ if (!fn)
3229+ return NULL_TREE;
3230+ fn = valueize_op (fn);
3231 if (TREE_CODE (fn) == ADDR_EXPR
3232 && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL
3233 && DECL_BUILT_IN (TREE_OPERAND (fn, 0)))
3234@@ -2310,6 +2313,11 @@
3235 return true;
3236 }
3237
3238+ /* Internal calls provide no argument types, so the extra laxity
3239+ for normal calls does not apply. */
3240+ if (gimple_call_internal_p (stmt))
3241+ return false;
3242+
3243 /* Propagate into the call arguments. Compared to replace_uses_in
3244 this can use the argument slot types for type verification
3245 instead of the current argument type. We also can safely
3246
3247=== modified file 'gcc/tree-ssa-dom.c'
3248--- old/gcc/tree-ssa-dom.c 2011-02-14 17:59:10 +0000
3249+++ new/gcc/tree-ssa-dom.c 2011-05-05 15:42:22 +0000
3250@@ -64,7 +64,7 @@
3251 struct { enum tree_code op; tree opnd; } unary;
3252 struct { enum tree_code op; tree opnd0, opnd1; } binary;
3253 struct { enum tree_code op; tree opnd0, opnd1, opnd2; } ternary;
3254- struct { tree fn; bool pure; size_t nargs; tree *args; } call;
3255+ struct { gimple fn_from; bool pure; size_t nargs; tree *args; } call;
3256 } ops;
3257 };
3258
3259@@ -258,7 +258,7 @@
3260
3261 expr->type = TREE_TYPE (gimple_call_lhs (stmt));
3262 expr->kind = EXPR_CALL;
3263- expr->ops.call.fn = gimple_call_fn (stmt);
3264+ expr->ops.call.fn_from = stmt;
3265
3266 if (gimple_call_flags (stmt) & (ECF_CONST | ECF_PURE))
3267 expr->ops.call.pure = true;
3268@@ -422,8 +422,8 @@
3269
3270 /* If the calls are to different functions, then they
3271 clearly cannot be equal. */
3272- if (! operand_equal_p (expr0->ops.call.fn,
3273- expr1->ops.call.fn, 0))
3274+ if (!gimple_call_same_target_p (expr0->ops.call.fn_from,
3275+ expr1->ops.call.fn_from))
3276 return false;
3277
3278 if (! expr0->ops.call.pure)
3279@@ -503,9 +503,15 @@
3280 {
3281 size_t i;
3282 enum tree_code code = CALL_EXPR;
3283+ gimple fn_from;
3284
3285 val = iterative_hash_object (code, val);
3286- val = iterative_hash_expr (expr->ops.call.fn, val);
3287+ fn_from = expr->ops.call.fn_from;
3288+ if (gimple_call_internal_p (fn_from))
3289+ val = iterative_hash_hashval_t
3290+ ((hashval_t) gimple_call_internal_fn (fn_from), val);
3291+ else
3292+ val = iterative_hash_expr (gimple_call_fn (fn_from), val);
3293 for (i = 0; i < expr->ops.call.nargs; i++)
3294 val = iterative_hash_expr (expr->ops.call.args[i], val);
3295 }
3296@@ -565,8 +571,14 @@
3297 {
3298 size_t i;
3299 size_t nargs = element->expr.ops.call.nargs;
3300+ gimple fn_from;
3301
3302- print_generic_expr (stream, element->expr.ops.call.fn, 0);
3303+ fn_from = element->expr.ops.call.fn_from;
3304+ if (gimple_call_internal_p (fn_from))
3305+ fputs (internal_fn_name (gimple_call_internal_fn (fn_from)),
3306+ stream);
3307+ else
3308+ print_generic_expr (stream, gimple_call_fn (fn_from), 0);
3309 fprintf (stream, " (");
3310 for (i = 0; i < nargs; i++)
3311 {
3312
3313=== modified file 'gcc/tree-ssa-pre.c'
3314--- old/gcc/tree-ssa-pre.c 2011-02-15 13:04:47 +0000
3315+++ new/gcc/tree-ssa-pre.c 2011-05-05 15:42:22 +0000
3316@@ -2657,11 +2657,13 @@
3317 }
3318
3319 /* Return true if we can value number the call in STMT. This is true
3320- if we have a pure or constant call. */
3321+ if we have a pure or constant call to a real function. */
3322
3323 static bool
3324 can_value_number_call (gimple stmt)
3325 {
3326+ if (gimple_call_internal_p (stmt))
3327+ return false;
3328 if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
3329 return true;
3330 return false;
3331@@ -4187,6 +4189,7 @@
3332 gimple_stmt_iterator gsi;
3333 gimple stmt;
3334 unsigned i;
3335+ tree fn;
3336
3337 FOR_EACH_BB (b)
3338 {
3339@@ -4378,9 +4381,10 @@
3340 /* Visit indirect calls and turn them into direct calls if
3341 possible. */
3342 if (is_gimple_call (stmt)
3343- && TREE_CODE (gimple_call_fn (stmt)) == SSA_NAME)
3344+ && (fn = gimple_call_fn (stmt))
3345+ && TREE_CODE (fn) == SSA_NAME)
3346 {
3347- tree fn = VN_INFO (gimple_call_fn (stmt))->valnum;
3348+ fn = VN_INFO (fn)->valnum;
3349 if (TREE_CODE (fn) == ADDR_EXPR
3350 && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL)
3351 {
3352
3353=== modified file 'gcc/tree-ssa-sccvn.c'
3354--- old/gcc/tree-ssa-sccvn.c 2011-05-12 14:08:00 +0000
3355+++ new/gcc/tree-ssa-sccvn.c 2011-06-02 12:12:00 +0000
3356@@ -2982,7 +2982,8 @@
3357 /* ??? We should handle stores from calls. */
3358 else if (TREE_CODE (lhs) == SSA_NAME)
3359 {
3360- if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
3361+ if (!gimple_call_internal_p (stmt)
3362+ && gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
3363 changed = visit_reference_op_call (lhs, stmt);
3364 else
3365 changed = defs_to_varying (stmt);
3366
3367=== modified file 'gcc/tree-ssa-structalias.c'
3368--- old/gcc/tree-ssa-structalias.c 2011-02-10 15:29:52 +0000
3369+++ new/gcc/tree-ssa-structalias.c 2011-05-05 15:42:22 +0000
3370@@ -4319,6 +4319,7 @@
3371 /* Fallthru to general call handling. */;
3372 }
3373 if (!in_ipa_mode
3374+ || gimple_call_internal_p (t)
3375 || (fndecl
3376 && (!(fi = lookup_vi_for_tree (fndecl))
3377 || !fi->is_fn_info)))
3378
3379=== modified file 'gcc/tree-vect-data-refs.c'
3380--- old/gcc/tree-vect-data-refs.c 2011-05-06 11:28:27 +0000
3381+++ new/gcc/tree-vect-data-refs.c 2011-06-02 12:12:00 +0000
3382@@ -43,6 +43,45 @@
3383 #include "expr.h"
3384 #include "optabs.h"
3385
3386+/* Return true if load- or store-lanes optab OPTAB is implemented for
3387+ COUNT vectors of type VECTYPE. NAME is the name of OPTAB. */
3388+
3389+static bool
3390+vect_lanes_optab_supported_p (const char *name, convert_optab optab,
3391+ tree vectype, unsigned HOST_WIDE_INT count)
3392+{
3393+ enum machine_mode mode, array_mode;
3394+ bool limit_p;
3395+
3396+ mode = TYPE_MODE (vectype);
3397+ limit_p = !targetm.array_mode_supported_p (mode, count);
3398+ array_mode = mode_for_size (count * GET_MODE_BITSIZE (mode),
3399+ MODE_INT, limit_p);
3400+
3401+ if (array_mode == BLKmode)
3402+ {
3403+ if (vect_print_dump_info (REPORT_DETAILS))
3404+ fprintf (vect_dump, "no array mode for %s[" HOST_WIDE_INT_PRINT_DEC "]",
3405+ GET_MODE_NAME (mode), count);
3406+ return false;
3407+ }
3408+
3409+ if (convert_optab_handler (optab, array_mode, mode) == CODE_FOR_nothing)
3410+ {
3411+ if (vect_print_dump_info (REPORT_DETAILS))
3412+ fprintf (vect_dump, "cannot use %s<%s><%s>",
3413+ name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode));
3414+ return false;
3415+ }
3416+
3417+ if (vect_print_dump_info (REPORT_DETAILS))
3418+ fprintf (vect_dump, "can use %s<%s><%s>",
3419+ name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode));
3420+
3421+ return true;
3422+}
3423+
3424+
3425 /* Return the smallest scalar part of STMT.
3426 This is used to determine the vectype of the stmt. We generally set the
3427 vectype according to the type of the result (lhs). For stmts whose
3428@@ -2196,19 +2235,6 @@
3429 return false;
3430 }
3431
3432- /* FORNOW: we handle only interleaving that is a power of 2.
3433- We don't fail here if it may be still possible to vectorize the
3434- group using SLP. If not, the size of the group will be checked in
3435- vect_analyze_operations, and the vectorization will fail. */
3436- if (exact_log2 (stride) == -1)
3437- {
3438- if (vect_print_dump_info (REPORT_DETAILS))
3439- fprintf (vect_dump, "interleaving is not a power of 2");
3440-
3441- if (slp_impossible)
3442- return false;
3443- }
3444-
3445 if (stride == 0)
3446 stride = count;
3447
3448@@ -2911,31 +2937,33 @@
3449
3450 /* Function vect_create_data_ref_ptr.
3451
3452- Create a new pointer to vector type (vp), that points to the first location
3453- accessed in the loop by STMT, along with the def-use update chain to
3454- appropriately advance the pointer through the loop iterations. Also set
3455- aliasing information for the pointer. This vector pointer is used by the
3456- callers to this function to create a memory reference expression for vector
3457- load/store access.
3458+ Create a new pointer-to-AGGR_TYPE variable (ap), that points to the first
3459+ location accessed in the loop by STMT, along with the def-use update
3460+ chain to appropriately advance the pointer through the loop iterations.
3461+ Also set aliasing information for the pointer. This pointer is used by
3462+ the callers to this function to create a memory reference expression for
3463+ vector load/store access.
3464
3465 Input:
3466 1. STMT: a stmt that references memory. Expected to be of the form
3467 GIMPLE_ASSIGN <name, data-ref> or
3468 GIMPLE_ASSIGN <data-ref, name>.
3469- 2. AT_LOOP: the loop where the vector memref is to be created.
3470- 3. OFFSET (optional): an offset to be added to the initial address accessed
3471+ 2. AGGR_TYPE: the type of the reference, which should be either a vector
3472+ or an array.
3473+ 3. AT_LOOP: the loop where the vector memref is to be created.
3474+ 4. OFFSET (optional): an offset to be added to the initial address accessed
3475 by the data-ref in STMT.
3476- 4. ONLY_INIT: indicate if vp is to be updated in the loop, or remain
3477+ 5. ONLY_INIT: indicate if vp is to be updated in the loop, or remain
3478 pointing to the initial address.
3479- 5. TYPE: if not NULL indicates the required type of the data-ref.
3480+ 6. TYPE: if not NULL indicates the required type of the data-ref.
3481
3482 Output:
3483 1. Declare a new ptr to vector_type, and have it point to the base of the
3484 data reference (initial addressed accessed by the data reference).
3485 For example, for vector of type V8HI, the following code is generated:
3486
3487- v8hi *vp;
3488- vp = (v8hi *)initial_address;
3489+ v8hi *ap;
3490+ ap = (v8hi *)initial_address;
3491
3492 if OFFSET is not supplied:
3493 initial_address = &a[init];
3494@@ -2955,7 +2983,7 @@
3495 4. Return the pointer. */
3496
3497 tree
3498-vect_create_data_ref_ptr (gimple stmt, struct loop *at_loop,
3499+vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop,
3500 tree offset, tree *initial_address, gimple *ptr_incr,
3501 bool only_init, bool *inv_p)
3502 {
3503@@ -2965,17 +2993,16 @@
3504 struct loop *loop = NULL;
3505 bool nested_in_vect_loop = false;
3506 struct loop *containing_loop = NULL;
3507- tree vectype = STMT_VINFO_VECTYPE (stmt_info);
3508- tree vect_ptr_type;
3509- tree vect_ptr;
3510+ tree aggr_ptr_type;
3511+ tree aggr_ptr;
3512 tree new_temp;
3513 gimple vec_stmt;
3514 gimple_seq new_stmt_list = NULL;
3515 edge pe = NULL;
3516 basic_block new_bb;
3517- tree vect_ptr_init;
3518+ tree aggr_ptr_init;
3519 struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info);
3520- tree vptr;
3521+ tree aptr;
3522 gimple_stmt_iterator incr_gsi;
3523 bool insert_after;
3524 bool negative;
3525@@ -2986,6 +3013,9 @@
3526 gimple_stmt_iterator gsi = gsi_for_stmt (stmt);
3527 tree base;
3528
3529+ gcc_assert (TREE_CODE (aggr_type) == ARRAY_TYPE
3530+ || TREE_CODE (aggr_type) == VECTOR_TYPE);
3531+
3532 if (loop_vinfo)
3533 {
3534 loop = LOOP_VINFO_LOOP (loop_vinfo);
3535@@ -3020,8 +3050,9 @@
3536 if (vect_print_dump_info (REPORT_DETAILS))
3537 {
3538 tree data_ref_base = base_name;
3539- fprintf (vect_dump, "create vector-pointer variable to type: ");
3540- print_generic_expr (vect_dump, vectype, TDF_SLIM);
3541+ fprintf (vect_dump, "create %s-pointer variable to type: ",
3542+ tree_code_name[(int) TREE_CODE (aggr_type)]);
3543+ print_generic_expr (vect_dump, aggr_type, TDF_SLIM);
3544 if (TREE_CODE (data_ref_base) == VAR_DECL
3545 || TREE_CODE (data_ref_base) == ARRAY_REF)
3546 fprintf (vect_dump, " vectorizing an array ref: ");
3547@@ -3032,27 +3063,28 @@
3548 print_generic_expr (vect_dump, base_name, TDF_SLIM);
3549 }
3550
3551- /* (1) Create the new vector-pointer variable. */
3552- vect_ptr_type = build_pointer_type (vectype);
3553+ /* (1) Create the new aggregate-pointer variable. */
3554+ aggr_ptr_type = build_pointer_type (aggr_type);
3555 base = get_base_address (DR_REF (dr));
3556 if (base
3557 && TREE_CODE (base) == MEM_REF)
3558- vect_ptr_type
3559- = build_qualified_type (vect_ptr_type,
3560+ aggr_ptr_type
3561+ = build_qualified_type (aggr_ptr_type,
3562 TYPE_QUALS (TREE_TYPE (TREE_OPERAND (base, 0))));
3563- vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
3564+ aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
3565 get_name (base_name));
3566
3567- /* Vector types inherit the alias set of their component type by default so
3568- we need to use a ref-all pointer if the data reference does not conflict
3569- with the created vector data reference because it is not addressable. */
3570- if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr),
3571+ /* Vector and array types inherit the alias set of their component
3572+ type by default so we need to use a ref-all pointer if the data
3573+ reference does not conflict with the created aggregated data
3574+ reference because it is not addressable. */
3575+ if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr),
3576 get_alias_set (DR_REF (dr))))
3577 {
3578- vect_ptr_type
3579- = build_pointer_type_for_mode (vectype,
3580- TYPE_MODE (vect_ptr_type), true);
3581- vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
3582+ aggr_ptr_type
3583+ = build_pointer_type_for_mode (aggr_type,
3584+ TYPE_MODE (aggr_ptr_type), true);
3585+ aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
3586 get_name (base_name));
3587 }
3588
3589@@ -3063,14 +3095,14 @@
3590 do
3591 {
3592 tree lhs = gimple_assign_lhs (orig_stmt);
3593- if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr),
3594+ if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr),
3595 get_alias_set (lhs)))
3596 {
3597- vect_ptr_type
3598- = build_pointer_type_for_mode (vectype,
3599- TYPE_MODE (vect_ptr_type), true);
3600- vect_ptr
3601- = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
3602+ aggr_ptr_type
3603+ = build_pointer_type_for_mode (aggr_type,
3604+ TYPE_MODE (aggr_ptr_type), true);
3605+ aggr_ptr
3606+ = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
3607 get_name (base_name));
3608 break;
3609 }
3610@@ -3080,7 +3112,7 @@
3611 while (orig_stmt);
3612 }
3613
3614- add_referenced_var (vect_ptr);
3615+ add_referenced_var (aggr_ptr);
3616
3617 /* Note: If the dataref is in an inner-loop nested in LOOP, and we are
3618 vectorizing LOOP (i.e., outer-loop vectorization), we need to create two
3619@@ -3113,8 +3145,8 @@
3620 vp2 = vp1 + step
3621 if () goto LOOP */
3622
3623- /* (2) Calculate the initial address the vector-pointer, and set
3624- the vector-pointer to point to it before the loop. */
3625+ /* (2) Calculate the initial address of the aggregate-pointer, and set
3626+ the aggregate-pointer to point to it before the loop. */
3627
3628 /* Create: (&(base[init_val+offset]) in the loop preheader. */
3629
3630@@ -3133,17 +3165,17 @@
3631
3632 *initial_address = new_temp;
3633
3634- /* Create: p = (vectype *) initial_base */
3635+ /* Create: p = (aggr_type *) initial_base */
3636 if (TREE_CODE (new_temp) != SSA_NAME
3637- || !useless_type_conversion_p (vect_ptr_type, TREE_TYPE (new_temp)))
3638+ || !useless_type_conversion_p (aggr_ptr_type, TREE_TYPE (new_temp)))
3639 {
3640- vec_stmt = gimple_build_assign (vect_ptr,
3641- fold_convert (vect_ptr_type, new_temp));
3642- vect_ptr_init = make_ssa_name (vect_ptr, vec_stmt);
3643+ vec_stmt = gimple_build_assign (aggr_ptr,
3644+ fold_convert (aggr_ptr_type, new_temp));
3645+ aggr_ptr_init = make_ssa_name (aggr_ptr, vec_stmt);
3646 /* Copy the points-to information if it exists. */
3647 if (DR_PTR_INFO (dr))
3648- duplicate_ssa_name_ptr_info (vect_ptr_init, DR_PTR_INFO (dr));
3649- gimple_assign_set_lhs (vec_stmt, vect_ptr_init);
3650+ duplicate_ssa_name_ptr_info (aggr_ptr_init, DR_PTR_INFO (dr));
3651+ gimple_assign_set_lhs (vec_stmt, aggr_ptr_init);
3652 if (pe)
3653 {
3654 new_bb = gsi_insert_on_edge_immediate (pe, vec_stmt);
3655@@ -3153,19 +3185,19 @@
3656 gsi_insert_before (&gsi, vec_stmt, GSI_SAME_STMT);
3657 }
3658 else
3659- vect_ptr_init = new_temp;
3660+ aggr_ptr_init = new_temp;
3661
3662- /* (3) Handle the updating of the vector-pointer inside the loop.
3663+ /* (3) Handle the updating of the aggregate-pointer inside the loop.
3664 This is needed when ONLY_INIT is false, and also when AT_LOOP is the
3665 inner-loop nested in LOOP (during outer-loop vectorization). */
3666
3667 /* No update in loop is required. */
3668 if (only_init && (!loop_vinfo || at_loop == loop))
3669- vptr = vect_ptr_init;
3670+ aptr = aggr_ptr_init;
3671 else
3672 {
3673- /* The step of the vector pointer is the Vector Size. */
3674- tree step = TYPE_SIZE_UNIT (vectype);
3675+ /* The step of the aggregate pointer is the type size. */
3676+ tree step = TYPE_SIZE_UNIT (aggr_type);
3677 /* One exception to the above is when the scalar step of the load in
3678 LOOP is zero. In this case the step here is also zero. */
3679 if (*inv_p)
3680@@ -3175,9 +3207,9 @@
3681
3682 standard_iv_increment_position (loop, &incr_gsi, &insert_after);
3683
3684- create_iv (vect_ptr_init,
3685- fold_convert (vect_ptr_type, step),
3686- vect_ptr, loop, &incr_gsi, insert_after,
3687+ create_iv (aggr_ptr_init,
3688+ fold_convert (aggr_ptr_type, step),
3689+ aggr_ptr, loop, &incr_gsi, insert_after,
3690 &indx_before_incr, &indx_after_incr);
3691 incr = gsi_stmt (incr_gsi);
3692 set_vinfo_for_stmt (incr, new_stmt_vec_info (incr, loop_vinfo, NULL));
3693@@ -3191,14 +3223,14 @@
3694 if (ptr_incr)
3695 *ptr_incr = incr;
3696
3697- vptr = indx_before_incr;
3698+ aptr = indx_before_incr;
3699 }
3700
3701 if (!nested_in_vect_loop || only_init)
3702- return vptr;
3703-
3704-
3705- /* (4) Handle the updating of the vector-pointer inside the inner-loop
3706+ return aptr;
3707+
3708+
3709+ /* (4) Handle the updating of the aggregate-pointer inside the inner-loop
3710 nested in LOOP, if exists. */
3711
3712 gcc_assert (nested_in_vect_loop);
3713@@ -3206,7 +3238,7 @@
3714 {
3715 standard_iv_increment_position (containing_loop, &incr_gsi,
3716 &insert_after);
3717- create_iv (vptr, fold_convert (vect_ptr_type, DR_STEP (dr)), vect_ptr,
3718+ create_iv (aptr, fold_convert (aggr_ptr_type, DR_STEP (dr)), aggr_ptr,
3719 containing_loop, &incr_gsi, insert_after, &indx_before_incr,
3720 &indx_after_incr);
3721 incr = gsi_stmt (incr_gsi);
3722@@ -3343,13 +3375,22 @@
3723 and FALSE otherwise. */
3724
3725 bool
3726-vect_strided_store_supported (tree vectype)
3727+vect_strided_store_supported (tree vectype, unsigned HOST_WIDE_INT count)
3728 {
3729 optab interleave_high_optab, interleave_low_optab;
3730 enum machine_mode mode;
3731
3732 mode = TYPE_MODE (vectype);
3733
3734+ /* vect_permute_store_chain requires the group size to be a power of two. */
3735+ if (exact_log2 (count) == -1)
3736+ {
3737+ if (vect_print_dump_info (REPORT_DETAILS))
3738+ fprintf (vect_dump, "the size of the group of strided accesses"
3739+ " is not a power of 2");
3740+ return false;
3741+ }
3742+
3743 /* Check that the operation is supported. */
3744 interleave_high_optab = optab_for_tree_code (VEC_INTERLEAVE_HIGH_EXPR,
3745 vectype, optab_default);
3746@@ -3374,6 +3415,18 @@
3747 }
3748
3749
3750+/* Return TRUE if vec_store_lanes is available for COUNT vectors of
3751+ type VECTYPE. */
3752+
3753+bool
3754+vect_store_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count)
3755+{
3756+ return vect_lanes_optab_supported_p ("vec_store_lanes",
3757+ vec_store_lanes_optab,
3758+ vectype, count);
3759+}
3760+
3761+
3762 /* Function vect_permute_store_chain.
3763
3764 Given a chain of interleaved stores in DR_CHAIN of LENGTH that must be
3765@@ -3435,7 +3488,7 @@
3766 I3: 4 12 20 28 5 13 21 30
3767 I4: 6 14 22 30 7 15 23 31. */
3768
3769-bool
3770+void
3771 vect_permute_store_chain (VEC(tree,heap) *dr_chain,
3772 unsigned int length,
3773 gimple stmt,
3774@@ -3449,9 +3502,7 @@
3775 unsigned int j;
3776 enum tree_code high_code, low_code;
3777
3778- /* Check that the operation is supported. */
3779- if (!vect_strided_store_supported (vectype))
3780- return false;
3781+ gcc_assert (vect_strided_store_supported (vectype, length));
3782
3783 *result_chain = VEC_copy (tree, heap, dr_chain);
3784
3785@@ -3504,7 +3555,6 @@
3786 }
3787 dr_chain = VEC_copy (tree, heap, *result_chain);
3788 }
3789- return true;
3790 }
3791
3792 /* Function vect_setup_realignment
3793@@ -3674,8 +3724,9 @@
3794
3795 gcc_assert (!compute_in_loop);
3796 vec_dest = vect_create_destination_var (scalar_dest, vectype);
3797- ptr = vect_create_data_ref_ptr (stmt, loop_for_initial_load, NULL_TREE,
3798- &init_addr, &inc, true, &inv_p);
3799+ ptr = vect_create_data_ref_ptr (stmt, vectype, loop_for_initial_load,
3800+ NULL_TREE, &init_addr, &inc,
3801+ true, &inv_p);
3802 new_stmt = gimple_build_assign_with_ops
3803 (BIT_AND_EXPR, NULL_TREE, ptr,
3804 build_int_cst (TREE_TYPE (ptr),
3805@@ -3780,13 +3831,22 @@
3806 and FALSE otherwise. */
3807
3808 bool
3809-vect_strided_load_supported (tree vectype)
3810+vect_strided_load_supported (tree vectype, unsigned HOST_WIDE_INT count)
3811 {
3812 optab perm_even_optab, perm_odd_optab;
3813 enum machine_mode mode;
3814
3815 mode = TYPE_MODE (vectype);
3816
3817+ /* vect_permute_load_chain requires the group size to be a power of two. */
3818+ if (exact_log2 (count) == -1)
3819+ {
3820+ if (vect_print_dump_info (REPORT_DETAILS))
3821+ fprintf (vect_dump, "the size of the group of strided accesses"
3822+ " is not a power of 2");
3823+ return false;
3824+ }
3825+
3826 perm_even_optab = optab_for_tree_code (VEC_EXTRACT_EVEN_EXPR, vectype,
3827 optab_default);
3828 if (!perm_even_optab)
3829@@ -3821,6 +3881,16 @@
3830 return true;
3831 }
3832
3833+/* Return TRUE if vec_load_lanes is available for COUNT vectors of
3834+ type VECTYPE. */
3835+
3836+bool
3837+vect_load_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count)
3838+{
3839+ return vect_lanes_optab_supported_p ("vec_load_lanes",
3840+ vec_load_lanes_optab,
3841+ vectype, count);
3842+}
3843
3844 /* Function vect_permute_load_chain.
3845
3846@@ -3898,7 +3968,7 @@
3847 3rd vec (E2): 2 6 10 14 18 22 26 30
3848 4th vec (E4): 3 7 11 15 19 23 27 31. */
3849
3850-bool
3851+static void
3852 vect_permute_load_chain (VEC(tree,heap) *dr_chain,
3853 unsigned int length,
3854 gimple stmt,
3855@@ -3911,9 +3981,7 @@
3856 int i;
3857 unsigned int j;
3858
3859- /* Check that the operation is supported. */
3860- if (!vect_strided_load_supported (vectype))
3861- return false;
3862+ gcc_assert (vect_strided_load_supported (vectype, length));
3863
3864 *result_chain = VEC_copy (tree, heap, dr_chain);
3865 for (i = 0; i < exact_log2 (length); i++)
3866@@ -3956,7 +4024,6 @@
3867 }
3868 dr_chain = VEC_copy (tree, heap, *result_chain);
3869 }
3870- return true;
3871 }
3872
3873
3874@@ -3967,24 +4034,32 @@
3875 the scalar statements.
3876 */
3877
3878-bool
3879+void
3880 vect_transform_strided_load (gimple stmt, VEC(tree,heap) *dr_chain, int size,
3881 gimple_stmt_iterator *gsi)
3882 {
3883- stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
3884- gimple first_stmt = DR_GROUP_FIRST_DR (stmt_info);
3885- gimple next_stmt, new_stmt;
3886 VEC(tree,heap) *result_chain = NULL;
3887- unsigned int i, gap_count;
3888- tree tmp_data_ref;
3889
3890 /* DR_CHAIN contains input data-refs that are a part of the interleaving.
3891 RESULT_CHAIN is the output of vect_permute_load_chain, it contains permuted
3892 vectors, that are ready for vector computation. */
3893 result_chain = VEC_alloc (tree, heap, size);
3894- /* Permute. */
3895- if (!vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain))
3896- return false;
3897+ vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain);
3898+ vect_record_strided_load_vectors (stmt, result_chain);
3899+ VEC_free (tree, heap, result_chain);
3900+}
3901+
3902+/* RESULT_CHAIN contains the output of a group of strided loads that were
3903+ generated as part of the vectorization of STMT. Assign the statement
3904+ for each vector to the associated scalar statement. */
3905+
3906+void
3907+vect_record_strided_load_vectors (gimple stmt, VEC(tree,heap) *result_chain)
3908+{
3909+ gimple first_stmt = DR_GROUP_FIRST_DR (vinfo_for_stmt (stmt));
3910+ gimple next_stmt, new_stmt;
3911+ unsigned int i, gap_count;
3912+ tree tmp_data_ref;
3913
3914 /* Put a permuted data-ref in the VECTORIZED_STMT field.
3915 Since we scan the chain starting from it's first node, their order
3916@@ -4046,9 +4121,6 @@
3917 break;
3918 }
3919 }
3920-
3921- VEC_free (tree, heap, result_chain);
3922- return true;
3923 }
3924
3925 /* Function vect_force_dr_alignment_p.
3926
3927=== modified file 'gcc/tree-vect-slp.c'
3928--- old/gcc/tree-vect-slp.c 2010-12-23 16:25:52 +0000
3929+++ new/gcc/tree-vect-slp.c 2011-05-05 15:43:06 +0000
3930@@ -215,7 +215,8 @@
3931 vect_model_simple_cost (stmt_info, ncopies_for_cost, dt, slp_node);
3932 else
3933 /* Store. */
3934- vect_model_store_cost (stmt_info, ncopies_for_cost, dt[0], slp_node);
3935+ vect_model_store_cost (stmt_info, ncopies_for_cost, false,
3936+ dt[0], slp_node);
3937 }
3938
3939 else
3940@@ -579,7 +580,7 @@
3941
3942 /* Analyze costs (for the first stmt in the group). */
3943 vect_model_load_cost (vinfo_for_stmt (stmt),
3944- ncopies_for_cost, *node);
3945+ ncopies_for_cost, false, *node);
3946 }
3947
3948 /* Store the place of this load in the interleaving chain. In
3949
3950=== modified file 'gcc/tree-vect-stmts.c'
3951--- old/gcc/tree-vect-stmts.c 2011-04-18 07:38:11 +0000
3952+++ new/gcc/tree-vect-stmts.c 2011-06-02 12:12:00 +0000
3953@@ -42,6 +42,82 @@
3954 #include "langhooks.h"
3955
3956
3957+/* Return a variable of type ELEM_TYPE[NELEMS]. */
3958+
3959+static tree
3960+create_vector_array (tree elem_type, unsigned HOST_WIDE_INT nelems)
3961+{
3962+ return create_tmp_var (build_array_type_nelts (elem_type, nelems),
3963+ "vect_array");
3964+}
3965+
3966+/* ARRAY is an array of vectors created by create_vector_array.
3967+ Return an SSA_NAME for the vector in index N. The reference
3968+ is part of the vectorization of STMT and the vector is associated
3969+ with scalar destination SCALAR_DEST. */
3970+
3971+static tree
3972+read_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree scalar_dest,
3973+ tree array, unsigned HOST_WIDE_INT n)
3974+{
3975+ tree vect_type, vect, vect_name, array_ref;
3976+ gimple new_stmt;
3977+
3978+ gcc_assert (TREE_CODE (TREE_TYPE (array)) == ARRAY_TYPE);
3979+ vect_type = TREE_TYPE (TREE_TYPE (array));
3980+ vect = vect_create_destination_var (scalar_dest, vect_type);
3981+ array_ref = build4 (ARRAY_REF, vect_type, array,
3982+ build_int_cst (size_type_node, n),
3983+ NULL_TREE, NULL_TREE);
3984+
3985+ new_stmt = gimple_build_assign (vect, array_ref);
3986+ vect_name = make_ssa_name (vect, new_stmt);
3987+ gimple_assign_set_lhs (new_stmt, vect_name);
3988+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
3989+ mark_symbols_for_renaming (new_stmt);
3990+
3991+ return vect_name;
3992+}
3993+
3994+/* ARRAY is an array of vectors created by create_vector_array.
3995+ Emit code to store SSA_NAME VECT in index N of the array.
3996+ The store is part of the vectorization of STMT. */
3997+
3998+static void
3999+write_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree vect,
4000+ tree array, unsigned HOST_WIDE_INT n)
4001+{
4002+ tree array_ref;
4003+ gimple new_stmt;
4004+
4005+ array_ref = build4 (ARRAY_REF, TREE_TYPE (vect), array,
4006+ build_int_cst (size_type_node, n),
4007+ NULL_TREE, NULL_TREE);
4008+
4009+ new_stmt = gimple_build_assign (array_ref, vect);
4010+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4011+ mark_symbols_for_renaming (new_stmt);
4012+}
4013+
4014+/* PTR is a pointer to an array of type TYPE. Return a representation
4015+ of *PTR. The memory reference replaces those in FIRST_DR
4016+ (and its group). */
4017+
4018+static tree
4019+create_array_ref (tree type, tree ptr, struct data_reference *first_dr)
4020+{
4021+ struct ptr_info_def *pi;
4022+ tree mem_ref, alias_ptr_type;
4023+
4024+ alias_ptr_type = reference_alias_ptr_type (DR_REF (first_dr));
4025+ mem_ref = build2 (MEM_REF, type, ptr, build_int_cst (alias_ptr_type, 0));
4026+ /* Arrays have the same alignment as their type. */
4027+ pi = get_ptr_info (ptr);
4028+ pi->align = TYPE_ALIGN_UNIT (type);
4029+ pi->misalign = 0;
4030+ return mem_ref;
4031+}
4032+
4033 /* Utility functions used by vect_mark_stmts_to_be_vectorized. */
4034
4035 /* Function vect_mark_relevant.
4036@@ -648,7 +724,8 @@
4037
4038 void
4039 vect_model_store_cost (stmt_vec_info stmt_info, int ncopies,
4040- enum vect_def_type dt, slp_tree slp_node)
4041+ bool store_lanes_p, enum vect_def_type dt,
4042+ slp_tree slp_node)
4043 {
4044 int group_size;
4045 unsigned int inside_cost = 0, outside_cost = 0;
4046@@ -685,9 +762,11 @@
4047 first_dr = STMT_VINFO_DATA_REF (stmt_info);
4048 }
4049
4050- /* Is this an access in a group of stores, which provide strided access?
4051- If so, add in the cost of the permutes. */
4052- if (group_size > 1)
4053+ /* We assume that the cost of a single store-lanes instruction is
4054+ equivalent to the cost of GROUP_SIZE separate stores. If a strided
4055+ access is instead being provided by a permute-and-store operation,
4056+ include the cost of the permutes. */
4057+ if (!store_lanes_p && group_size > 1)
4058 {
4059 /* Uses a high and low interleave operation for each needed permute. */
4060 inside_cost = ncopies * exact_log2(group_size) * group_size
4061@@ -763,8 +842,8 @@
4062 access scheme chosen. */
4063
4064 void
4065-vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, slp_tree slp_node)
4066-
4067+vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, bool load_lanes_p,
4068+ slp_tree slp_node)
4069 {
4070 int group_size;
4071 gimple first_stmt;
4072@@ -789,9 +868,11 @@
4073 first_dr = dr;
4074 }
4075
4076- /* Is this an access in a group of loads providing strided access?
4077- If so, add in the cost of the permutes. */
4078- if (group_size > 1)
4079+ /* We assume that the cost of a single load-lanes instruction is
4080+ equivalent to the cost of GROUP_SIZE separate loads. If a strided
4081+ access is instead being provided by a load-and-permute operation,
4082+ include the cost of the permutes. */
4083+ if (!load_lanes_p && group_size > 1)
4084 {
4085 /* Uses an even and odd extract operations for each needed permute. */
4086 inside_cost = ncopies * exact_log2(group_size) * group_size
4087@@ -3329,6 +3410,7 @@
4088 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
4089 struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr = NULL;
4090 tree vectype = STMT_VINFO_VECTYPE (stmt_info);
4091+ tree elem_type;
4092 loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
4093 struct loop *loop = NULL;
4094 enum machine_mode vec_mode;
4095@@ -3344,6 +3426,7 @@
4096 int j;
4097 gimple next_stmt, first_stmt = NULL;
4098 bool strided_store = false;
4099+ bool store_lanes_p = false;
4100 unsigned int group_size, i;
4101 VEC(tree,heap) *dr_chain = NULL, *oprnds = NULL, *result_chain = NULL;
4102 bool inv_p;
4103@@ -3351,6 +3434,7 @@
4104 bool slp = (slp_node != NULL);
4105 unsigned int vec_num;
4106 bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
4107+ tree aggr_type;
4108
4109 if (loop_vinfo)
4110 loop = LOOP_VINFO_LOOP (loop_vinfo);
4111@@ -3404,7 +3488,8 @@
4112
4113 /* The scalar rhs type needs to be trivially convertible to the vector
4114 component type. This should always be the case. */
4115- if (!useless_type_conversion_p (TREE_TYPE (vectype), TREE_TYPE (op)))
4116+ elem_type = TREE_TYPE (vectype);
4117+ if (!useless_type_conversion_p (elem_type, TREE_TYPE (op)))
4118 {
4119 if (vect_print_dump_info (REPORT_DETAILS))
4120 fprintf (vect_dump, "??? operands of different types");
4121@@ -3431,9 +3516,14 @@
4122 {
4123 strided_store = true;
4124 first_stmt = DR_GROUP_FIRST_DR (stmt_info);
4125- if (!vect_strided_store_supported (vectype)
4126- && !PURE_SLP_STMT (stmt_info) && !slp)
4127- return false;
4128+ if (!slp && !PURE_SLP_STMT (stmt_info))
4129+ {
4130+ group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt));
4131+ if (vect_store_lanes_supported (vectype, group_size))
4132+ store_lanes_p = true;
4133+ else if (!vect_strided_store_supported (vectype, group_size))
4134+ return false;
4135+ }
4136
4137 if (first_stmt == stmt)
4138 {
4139@@ -3459,7 +3549,7 @@
4140 if (!vec_stmt) /* transformation not required. */
4141 {
4142 STMT_VINFO_TYPE (stmt_info) = store_vec_info_type;
4143- vect_model_store_cost (stmt_info, ncopies, dt, NULL);
4144+ vect_model_store_cost (stmt_info, ncopies, store_lanes_p, dt, NULL);
4145 return true;
4146 }
4147
4148@@ -3514,6 +3604,16 @@
4149
4150 alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false);
4151 gcc_assert (alignment_support_scheme);
4152+ /* Targets with store-lane instructions must not require explicit
4153+ realignment. */
4154+ gcc_assert (!store_lanes_p
4155+ || alignment_support_scheme == dr_aligned
4156+ || alignment_support_scheme == dr_unaligned_supported);
4157+
4158+ if (store_lanes_p)
4159+ aggr_type = build_array_type_nelts (elem_type, vec_num * nunits);
4160+ else
4161+ aggr_type = vectype;
4162
4163 /* In case the vectorization factor (VF) is bigger than the number
4164 of elements that we can fit in a vectype (nunits), we have to generate
4165@@ -3602,9 +3702,9 @@
4166 /* We should have catched mismatched types earlier. */
4167 gcc_assert (useless_type_conversion_p (vectype,
4168 TREE_TYPE (vec_oprnd)));
4169- dataref_ptr = vect_create_data_ref_ptr (first_stmt, NULL, NULL_TREE,
4170- &dummy, &ptr_incr, false,
4171- &inv_p);
4172+ dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, NULL,
4173+ NULL_TREE, &dummy,
4174+ &ptr_incr, false, &inv_p);
4175 gcc_assert (bb_vinfo || !inv_p);
4176 }
4177 else
4178@@ -3625,76 +3725,101 @@
4179 VEC_replace(tree, dr_chain, i, vec_oprnd);
4180 VEC_replace(tree, oprnds, i, vec_oprnd);
4181 }
4182- dataref_ptr =
4183- bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE);
4184- }
4185-
4186- if (strided_store)
4187- {
4188- result_chain = VEC_alloc (tree, heap, group_size);
4189- /* Permute. */
4190- if (!vect_permute_store_chain (dr_chain, group_size, stmt, gsi,
4191- &result_chain))
4192- return false;
4193- }
4194-
4195- next_stmt = first_stmt;
4196- for (i = 0; i < vec_num; i++)
4197- {
4198- struct ptr_info_def *pi;
4199-
4200- if (i > 0)
4201- /* Bump the vector pointer. */
4202- dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4203- NULL_TREE);
4204-
4205- if (slp)
4206- vec_oprnd = VEC_index (tree, vec_oprnds, i);
4207- else if (strided_store)
4208- /* For strided stores vectorized defs are interleaved in
4209- vect_permute_store_chain(). */
4210- vec_oprnd = VEC_index (tree, result_chain, i);
4211-
4212- data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr,
4213- build_int_cst (reference_alias_ptr_type
4214- (DR_REF (first_dr)), 0));
4215- pi = get_ptr_info (dataref_ptr);
4216- pi->align = TYPE_ALIGN_UNIT (vectype);
4217- if (aligned_access_p (first_dr))
4218- pi->misalign = 0;
4219- else if (DR_MISALIGNMENT (first_dr) == -1)
4220- {
4221- TREE_TYPE (data_ref)
4222- = build_aligned_type (TREE_TYPE (data_ref),
4223- TYPE_ALIGN (TREE_TYPE (vectype)));
4224- pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype));
4225- pi->misalign = 0;
4226- }
4227- else
4228- {
4229- TREE_TYPE (data_ref)
4230- = build_aligned_type (TREE_TYPE (data_ref),
4231- TYPE_ALIGN (TREE_TYPE (vectype)));
4232- pi->misalign = DR_MISALIGNMENT (first_dr);
4233- }
4234-
4235- /* Arguments are ready. Create the new vector stmt. */
4236- new_stmt = gimple_build_assign (data_ref, vec_oprnd);
4237+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4238+ TYPE_SIZE_UNIT (aggr_type));
4239+ }
4240+
4241+ if (store_lanes_p)
4242+ {
4243+ tree vec_array;
4244+
4245+ /* Combine all the vectors into an array. */
4246+ vec_array = create_vector_array (vectype, vec_num);
4247+ for (i = 0; i < vec_num; i++)
4248+ {
4249+ vec_oprnd = VEC_index (tree, dr_chain, i);
4250+ write_vector_array (stmt, gsi, vec_oprnd, vec_array, i);
4251+ }
4252+
4253+ /* Emit:
4254+ MEM_REF[...all elements...] = STORE_LANES (VEC_ARRAY). */
4255+ data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr);
4256+ new_stmt = gimple_build_call_internal (IFN_STORE_LANES, 1, vec_array);
4257+ gimple_call_set_lhs (new_stmt, data_ref);
4258 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4259 mark_symbols_for_renaming (new_stmt);
4260-
4261- if (slp)
4262- continue;
4263-
4264- if (j == 0)
4265- STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
4266+ }
4267+ else
4268+ {
4269+ new_stmt = NULL;
4270+ if (strided_store)
4271+ {
4272+ result_chain = VEC_alloc (tree, heap, group_size);
4273+ /* Permute. */
4274+ vect_permute_store_chain (dr_chain, group_size, stmt, gsi,
4275+ &result_chain);
4276+ }
4277+
4278+ next_stmt = first_stmt;
4279+ for (i = 0; i < vec_num; i++)
4280+ {
4281+ struct ptr_info_def *pi;
4282+
4283+ if (i > 0)
4284+ /* Bump the vector pointer. */
4285+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi,
4286+ stmt, NULL_TREE);
4287+
4288+ if (slp)
4289+ vec_oprnd = VEC_index (tree, vec_oprnds, i);
4290+ else if (strided_store)
4291+ /* For strided stores vectorized defs are interleaved in
4292+ vect_permute_store_chain(). */
4293+ vec_oprnd = VEC_index (tree, result_chain, i);
4294+
4295+ data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr,
4296+ build_int_cst (reference_alias_ptr_type
4297+ (DR_REF (first_dr)), 0));
4298+ pi = get_ptr_info (dataref_ptr);
4299+ pi->align = TYPE_ALIGN_UNIT (vectype);
4300+ if (aligned_access_p (first_dr))
4301+ pi->misalign = 0;
4302+ else if (DR_MISALIGNMENT (first_dr) == -1)
4303+ {
4304+ TREE_TYPE (data_ref)
4305+ = build_aligned_type (TREE_TYPE (data_ref),
4306+ TYPE_ALIGN (elem_type));
4307+ pi->align = TYPE_ALIGN_UNIT (elem_type);
4308+ pi->misalign = 0;
4309+ }
4310+ else
4311+ {
4312+ TREE_TYPE (data_ref)
4313+ = build_aligned_type (TREE_TYPE (data_ref),
4314+ TYPE_ALIGN (elem_type));
4315+ pi->misalign = DR_MISALIGNMENT (first_dr);
4316+ }
4317+
4318+ /* Arguments are ready. Create the new vector stmt. */
4319+ new_stmt = gimple_build_assign (data_ref, vec_oprnd);
4320+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4321+ mark_symbols_for_renaming (new_stmt);
4322+
4323+ if (slp)
4324+ continue;
4325+
4326+ next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt));
4327+ if (!next_stmt)
4328+ break;
4329+ }
4330+ }
4331+ if (!slp)
4332+ {
4333+ if (j == 0)
4334+ STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
4335 else
4336 STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt;
4337-
4338 prev_stmt_info = vinfo_for_stmt (new_stmt);
4339- next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt));
4340- if (!next_stmt)
4341- break;
4342 }
4343 }
4344
4345@@ -3805,6 +3930,7 @@
4346 bool nested_in_vect_loop = false;
4347 struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr;
4348 tree vectype = STMT_VINFO_VECTYPE (stmt_info);
4349+ tree elem_type;
4350 tree new_temp;
4351 enum machine_mode mode;
4352 gimple new_stmt = NULL;
4353@@ -3821,6 +3947,7 @@
4354 gimple phi = NULL;
4355 VEC(tree,heap) *dr_chain = NULL;
4356 bool strided_load = false;
4357+ bool load_lanes_p = false;
4358 gimple first_stmt;
4359 tree scalar_type;
4360 bool inv_p;
4361@@ -3833,6 +3960,7 @@
4362 enum tree_code code;
4363 bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
4364 int vf;
4365+ tree aggr_type;
4366
4367 if (loop_vinfo)
4368 {
4369@@ -3909,7 +4037,8 @@
4370
4371 /* The vector component type needs to be trivially convertible to the
4372 scalar lhs. This should always be the case. */
4373- if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), TREE_TYPE (vectype)))
4374+ elem_type = TREE_TYPE (vectype);
4375+ if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), elem_type))
4376 {
4377 if (vect_print_dump_info (REPORT_DETAILS))
4378 fprintf (vect_dump, "??? operands of different types");
4379@@ -3923,10 +4052,15 @@
4380 /* FORNOW */
4381 gcc_assert (! nested_in_vect_loop);
4382
4383- /* Check if interleaving is supported. */
4384- if (!vect_strided_load_supported (vectype)
4385- && !PURE_SLP_STMT (stmt_info) && !slp)
4386- return false;
4387+ first_stmt = DR_GROUP_FIRST_DR (stmt_info);
4388+ if (!slp && !PURE_SLP_STMT (stmt_info))
4389+ {
4390+ group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt));
4391+ if (vect_load_lanes_supported (vectype, group_size))
4392+ load_lanes_p = true;
4393+ else if (!vect_strided_load_supported (vectype, group_size))
4394+ return false;
4395+ }
4396 }
4397
4398 if (negative)
4399@@ -3951,12 +4085,12 @@
4400 if (!vec_stmt) /* transformation not required. */
4401 {
4402 STMT_VINFO_TYPE (stmt_info) = load_vec_info_type;
4403- vect_model_load_cost (stmt_info, ncopies, NULL);
4404+ vect_model_load_cost (stmt_info, ncopies, load_lanes_p, NULL);
4405 return true;
4406 }
4407
4408 if (vect_print_dump_info (REPORT_DETAILS))
4409- fprintf (vect_dump, "transform load.");
4410+ fprintf (vect_dump, "transform load. ncopies = %d", ncopies);
4411
4412 /** Transform. **/
4413
4414@@ -3982,8 +4116,6 @@
4415 }
4416 else
4417 vec_num = group_size;
4418-
4419- dr_chain = VEC_alloc (tree, heap, vec_num);
4420 }
4421 else
4422 {
4423@@ -3994,6 +4126,11 @@
4424
4425 alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false);
4426 gcc_assert (alignment_support_scheme);
4427+ /* Targets with load-lane instructions must not require explicit
4428+ realignment. */
4429+ gcc_assert (!load_lanes_p
4430+ || alignment_support_scheme == dr_aligned
4431+ || alignment_support_scheme == dr_unaligned_supported);
4432
4433 /* In case the vectorization factor (VF) is bigger than the number
4434 of elements that we can fit in a vectype (nunits), we have to generate
4435@@ -4125,208 +4262,252 @@
4436 if (negative)
4437 offset = size_int (-TYPE_VECTOR_SUBPARTS (vectype) + 1);
4438
4439+ if (load_lanes_p)
4440+ aggr_type = build_array_type_nelts (elem_type, vec_num * nunits);
4441+ else
4442+ aggr_type = vectype;
4443+
4444 prev_stmt_info = NULL;
4445 for (j = 0; j < ncopies; j++)
4446 {
4447 /* 1. Create the vector pointer update chain. */
4448 if (j == 0)
4449- dataref_ptr = vect_create_data_ref_ptr (first_stmt,
4450+ dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type,
4451 at_loop, offset,
4452 &dummy, &ptr_incr, false,
4453 &inv_p);
4454 else
4455- dataref_ptr =
4456- bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE);
4457-
4458- for (i = 0; i < vec_num; i++)
4459+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4460+ TYPE_SIZE_UNIT (aggr_type));
4461+
4462+ if (strided_load || slp_perm)
4463+ dr_chain = VEC_alloc (tree, heap, vec_num);
4464+
4465+ if (load_lanes_p)
4466 {
4467- if (i > 0)
4468- dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4469- NULL_TREE);
4470-
4471- /* 2. Create the vector-load in the loop. */
4472- switch (alignment_support_scheme)
4473- {
4474- case dr_aligned:
4475- case dr_unaligned_supported:
4476- {
4477- struct ptr_info_def *pi;
4478- data_ref
4479- = build2 (MEM_REF, vectype, dataref_ptr,
4480- build_int_cst (reference_alias_ptr_type
4481- (DR_REF (first_dr)), 0));
4482- pi = get_ptr_info (dataref_ptr);
4483- pi->align = TYPE_ALIGN_UNIT (vectype);
4484- if (alignment_support_scheme == dr_aligned)
4485- {
4486- gcc_assert (aligned_access_p (first_dr));
4487- pi->misalign = 0;
4488- }
4489- else if (DR_MISALIGNMENT (first_dr) == -1)
4490- {
4491- TREE_TYPE (data_ref)
4492- = build_aligned_type (TREE_TYPE (data_ref),
4493- TYPE_ALIGN (TREE_TYPE (vectype)));
4494- pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype));
4495- pi->misalign = 0;
4496- }
4497- else
4498- {
4499- TREE_TYPE (data_ref)
4500- = build_aligned_type (TREE_TYPE (data_ref),
4501- TYPE_ALIGN (TREE_TYPE (vectype)));
4502- pi->misalign = DR_MISALIGNMENT (first_dr);
4503- }
4504- break;
4505- }
4506- case dr_explicit_realign:
4507- {
4508- tree ptr, bump;
4509- tree vs_minus_1 = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1);
4510-
4511- if (compute_in_loop)
4512- msq = vect_setup_realignment (first_stmt, gsi,
4513- &realignment_token,
4514- dr_explicit_realign,
4515- dataref_ptr, NULL);
4516-
4517- new_stmt = gimple_build_assign_with_ops
4518- (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4519- build_int_cst
4520- (TREE_TYPE (dataref_ptr),
4521- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4522- ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4523- gimple_assign_set_lhs (new_stmt, ptr);
4524- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4525- data_ref
4526- = build2 (MEM_REF, vectype, ptr,
4527- build_int_cst (reference_alias_ptr_type
4528- (DR_REF (first_dr)), 0));
4529- vec_dest = vect_create_destination_var (scalar_dest, vectype);
4530- new_stmt = gimple_build_assign (vec_dest, data_ref);
4531- new_temp = make_ssa_name (vec_dest, new_stmt);
4532- gimple_assign_set_lhs (new_stmt, new_temp);
4533- gimple_set_vdef (new_stmt, gimple_vdef (stmt));
4534- gimple_set_vuse (new_stmt, gimple_vuse (stmt));
4535- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4536- msq = new_temp;
4537-
4538- bump = size_binop (MULT_EXPR, vs_minus_1,
4539- TYPE_SIZE_UNIT (scalar_type));
4540- ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump);
4541- new_stmt = gimple_build_assign_with_ops
4542- (BIT_AND_EXPR, NULL_TREE, ptr,
4543- build_int_cst
4544- (TREE_TYPE (ptr),
4545- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4546- ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4547- gimple_assign_set_lhs (new_stmt, ptr);
4548- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4549- data_ref
4550- = build2 (MEM_REF, vectype, ptr,
4551- build_int_cst (reference_alias_ptr_type
4552- (DR_REF (first_dr)), 0));
4553- break;
4554- }
4555- case dr_explicit_realign_optimized:
4556- new_stmt = gimple_build_assign_with_ops
4557- (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4558- build_int_cst
4559- (TREE_TYPE (dataref_ptr),
4560- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4561- new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4562- gimple_assign_set_lhs (new_stmt, new_temp);
4563- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4564- data_ref
4565- = build2 (MEM_REF, vectype, new_temp,
4566- build_int_cst (reference_alias_ptr_type
4567- (DR_REF (first_dr)), 0));
4568- break;
4569- default:
4570- gcc_unreachable ();
4571- }
4572- vec_dest = vect_create_destination_var (scalar_dest, vectype);
4573- new_stmt = gimple_build_assign (vec_dest, data_ref);
4574- new_temp = make_ssa_name (vec_dest, new_stmt);
4575- gimple_assign_set_lhs (new_stmt, new_temp);
4576+ tree vec_array;
4577+
4578+ vec_array = create_vector_array (vectype, vec_num);
4579+
4580+ /* Emit:
4581+ VEC_ARRAY = LOAD_LANES (MEM_REF[...all elements...]). */
4582+ data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr);
4583+ new_stmt = gimple_build_call_internal (IFN_LOAD_LANES, 1, data_ref);
4584+ gimple_call_set_lhs (new_stmt, vec_array);
4585 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4586 mark_symbols_for_renaming (new_stmt);
4587
4588- /* 3. Handle explicit realignment if necessary/supported. Create in
4589- loop: vec_dest = realign_load (msq, lsq, realignment_token) */
4590- if (alignment_support_scheme == dr_explicit_realign_optimized
4591- || alignment_support_scheme == dr_explicit_realign)
4592- {
4593- tree tmp;
4594-
4595- lsq = gimple_assign_lhs (new_stmt);
4596- if (!realignment_token)
4597- realignment_token = dataref_ptr;
4598+ /* Extract each vector into an SSA_NAME. */
4599+ for (i = 0; i < vec_num; i++)
4600+ {
4601+ new_temp = read_vector_array (stmt, gsi, scalar_dest,
4602+ vec_array, i);
4603+ VEC_quick_push (tree, dr_chain, new_temp);
4604+ }
4605+
4606+ /* Record the mapping between SSA_NAMEs and statements. */
4607+ vect_record_strided_load_vectors (stmt, dr_chain);
4608+ }
4609+ else
4610+ {
4611+ for (i = 0; i < vec_num; i++)
4612+ {
4613+ if (i > 0)
4614+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi,
4615+ stmt, NULL_TREE);
4616+
4617+ /* 2. Create the vector-load in the loop. */
4618+ switch (alignment_support_scheme)
4619+ {
4620+ case dr_aligned:
4621+ case dr_unaligned_supported:
4622+ {
4623+ struct ptr_info_def *pi;
4624+ data_ref
4625+ = build2 (MEM_REF, vectype, dataref_ptr,
4626+ build_int_cst (reference_alias_ptr_type
4627+ (DR_REF (first_dr)), 0));
4628+ pi = get_ptr_info (dataref_ptr);
4629+ pi->align = TYPE_ALIGN_UNIT (vectype);
4630+ if (alignment_support_scheme == dr_aligned)
4631+ {
4632+ gcc_assert (aligned_access_p (first_dr));
4633+ pi->misalign = 0;
4634+ }
4635+ else if (DR_MISALIGNMENT (first_dr) == -1)
4636+ {
4637+ TREE_TYPE (data_ref)
4638+ = build_aligned_type (TREE_TYPE (data_ref),
4639+ TYPE_ALIGN (elem_type));
4640+ pi->align = TYPE_ALIGN_UNIT (elem_type);
4641+ pi->misalign = 0;
4642+ }
4643+ else
4644+ {
4645+ TREE_TYPE (data_ref)
4646+ = build_aligned_type (TREE_TYPE (data_ref),
4647+ TYPE_ALIGN (elem_type));
4648+ pi->misalign = DR_MISALIGNMENT (first_dr);
4649+ }
4650+ break;
4651+ }
4652+ case dr_explicit_realign:
4653+ {
4654+ tree ptr, bump;
4655+ tree vs_minus_1
4656+ = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1);
4657+
4658+ if (compute_in_loop)
4659+ msq = vect_setup_realignment (first_stmt, gsi,
4660+ &realignment_token,
4661+ dr_explicit_realign,
4662+ dataref_ptr, NULL);
4663+
4664+ new_stmt = gimple_build_assign_with_ops
4665+ (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4666+ build_int_cst
4667+ (TREE_TYPE (dataref_ptr),
4668+ -(HOST_WIDE_INT)
4669+ TYPE_ALIGN_UNIT (vectype)));
4670+ ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4671+ gimple_assign_set_lhs (new_stmt, ptr);
4672+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4673+ data_ref
4674+ = build2 (MEM_REF, vectype, ptr,
4675+ build_int_cst (reference_alias_ptr_type
4676+ (DR_REF (first_dr)), 0));
4677+ vec_dest = vect_create_destination_var (scalar_dest,
4678+ vectype);
4679+ new_stmt = gimple_build_assign (vec_dest, data_ref);
4680+ new_temp = make_ssa_name (vec_dest, new_stmt);
4681+ gimple_assign_set_lhs (new_stmt, new_temp);
4682+ gimple_set_vdef (new_stmt, gimple_vdef (stmt));
4683+ gimple_set_vuse (new_stmt, gimple_vuse (stmt));
4684+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4685+ msq = new_temp;
4686+
4687+ bump = size_binop (MULT_EXPR, vs_minus_1,
4688+ TYPE_SIZE_UNIT (scalar_type));
4689+ ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump);
4690+ new_stmt = gimple_build_assign_with_ops
4691+ (BIT_AND_EXPR, NULL_TREE, ptr,
4692+ build_int_cst
4693+ (TREE_TYPE (ptr),
4694+ -(HOST_WIDE_INT)
4695+ TYPE_ALIGN_UNIT (vectype)));
4696+ ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4697+ gimple_assign_set_lhs (new_stmt, ptr);
4698+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4699+ data_ref
4700+ = build2 (MEM_REF, vectype, ptr,
4701+ build_int_cst (reference_alias_ptr_type
4702+ (DR_REF (first_dr)), 0));
4703+ break;
4704+ }
4705+ case dr_explicit_realign_optimized:
4706+ new_stmt = gimple_build_assign_with_ops
4707+ (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4708+ build_int_cst
4709+ (TREE_TYPE (dataref_ptr),
4710+ -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4711+ new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr),
4712+ new_stmt);
4713+ gimple_assign_set_lhs (new_stmt, new_temp);
4714+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4715+ data_ref
4716+ = build2 (MEM_REF, vectype, new_temp,
4717+ build_int_cst (reference_alias_ptr_type
4718+ (DR_REF (first_dr)), 0));
4719+ break;
4720+ default:
4721+ gcc_unreachable ();
4722+ }
4723 vec_dest = vect_create_destination_var (scalar_dest, vectype);
4724- tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq,
4725- realignment_token);
4726- new_stmt = gimple_build_assign (vec_dest, tmp);
4727+ new_stmt = gimple_build_assign (vec_dest, data_ref);
4728 new_temp = make_ssa_name (vec_dest, new_stmt);
4729 gimple_assign_set_lhs (new_stmt, new_temp);
4730 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4731-
4732- if (alignment_support_scheme == dr_explicit_realign_optimized)
4733- {
4734- gcc_assert (phi);
4735- if (i == vec_num - 1 && j == ncopies - 1)
4736- add_phi_arg (phi, lsq, loop_latch_edge (containing_loop),
4737- UNKNOWN_LOCATION);
4738- msq = lsq;
4739- }
4740- }
4741-
4742- /* 4. Handle invariant-load. */
4743- if (inv_p && !bb_vinfo)
4744- {
4745- gcc_assert (!strided_load);
4746- gcc_assert (nested_in_vect_loop_p (loop, stmt));
4747- if (j == 0)
4748- {
4749- int k;
4750- tree t = NULL_TREE;
4751- tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type);
4752-
4753- /* CHECKME: bitpos depends on endianess? */
4754- bitpos = bitsize_zero_node;
4755- vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp,
4756- bitsize, bitpos);
4757- vec_dest =
4758- vect_create_destination_var (scalar_dest, NULL_TREE);
4759- new_stmt = gimple_build_assign (vec_dest, vec_inv);
4760- new_temp = make_ssa_name (vec_dest, new_stmt);
4761+ mark_symbols_for_renaming (new_stmt);
4762+
4763+ /* 3. Handle explicit realignment if necessary/supported.
4764+ Create in loop:
4765+ vec_dest = realign_load (msq, lsq, realignment_token) */
4766+ if (alignment_support_scheme == dr_explicit_realign_optimized
4767+ || alignment_support_scheme == dr_explicit_realign)
4768+ {
4769+ tree tmp;
4770+
4771+ lsq = gimple_assign_lhs (new_stmt);
4772+ if (!realignment_token)
4773+ realignment_token = dataref_ptr;
4774+ vec_dest = vect_create_destination_var (scalar_dest, vectype);
4775+ tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq,
4776+ realignment_token);
4777+ new_stmt = gimple_build_assign (vec_dest, tmp);
4778+ new_temp = make_ssa_name (vec_dest, new_stmt);
4779 gimple_assign_set_lhs (new_stmt, new_temp);
4780 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4781
4782- for (k = nunits - 1; k >= 0; --k)
4783- t = tree_cons (NULL_TREE, new_temp, t);
4784- /* FIXME: use build_constructor directly. */
4785- vec_inv = build_constructor_from_list (vectype, t);
4786- new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi);
4787+ if (alignment_support_scheme == dr_explicit_realign_optimized)
4788+ {
4789+ gcc_assert (phi);
4790+ if (i == vec_num - 1 && j == ncopies - 1)
4791+ add_phi_arg (phi, lsq,
4792+ loop_latch_edge (containing_loop),
4793+ UNKNOWN_LOCATION);
4794+ msq = lsq;
4795+ }
4796+ }
4797+
4798+ /* 4. Handle invariant-load. */
4799+ if (inv_p && !bb_vinfo)
4800+ {
4801+ gcc_assert (!strided_load);
4802+ gcc_assert (nested_in_vect_loop_p (loop, stmt));
4803+ if (j == 0)
4804+ {
4805+ int k;
4806+ tree t = NULL_TREE;
4807+ tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type);
4808+
4809+ /* CHECKME: bitpos depends on endianess? */
4810+ bitpos = bitsize_zero_node;
4811+ vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp,
4812+ bitsize, bitpos);
4813+ vec_dest = vect_create_destination_var (scalar_dest,
4814+ NULL_TREE);
4815+ new_stmt = gimple_build_assign (vec_dest, vec_inv);
4816+ new_temp = make_ssa_name (vec_dest, new_stmt);
4817+ gimple_assign_set_lhs (new_stmt, new_temp);
4818+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4819+
4820+ for (k = nunits - 1; k >= 0; --k)
4821+ t = tree_cons (NULL_TREE, new_temp, t);
4822+ /* FIXME: use build_constructor directly. */
4823+ vec_inv = build_constructor_from_list (vectype, t);
4824+ new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi);
4825+ new_stmt = SSA_NAME_DEF_STMT (new_temp);
4826+ }
4827+ else
4828+ gcc_unreachable (); /* FORNOW. */
4829+ }
4830+
4831+ if (negative)
4832+ {
4833+ new_temp = reverse_vec_elements (new_temp, stmt, gsi);
4834 new_stmt = SSA_NAME_DEF_STMT (new_temp);
4835 }
4836- else
4837- gcc_unreachable (); /* FORNOW. */
4838- }
4839-
4840- if (negative)
4841- {
4842- new_temp = reverse_vec_elements (new_temp, stmt, gsi);
4843- new_stmt = SSA_NAME_DEF_STMT (new_temp);
4844- }
4845-
4846- /* Collect vector loads and later create their permutation in
4847- vect_transform_strided_load (). */
4848- if (strided_load || slp_perm)
4849- VEC_quick_push (tree, dr_chain, new_temp);
4850-
4851- /* Store vector loads in the corresponding SLP_NODE. */
4852- if (slp && !slp_perm)
4853- VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node), new_stmt);
4854+
4855+ /* Collect vector loads and later create their permutation in
4856+ vect_transform_strided_load (). */
4857+ if (strided_load || slp_perm)
4858+ VEC_quick_push (tree, dr_chain, new_temp);
4859+
4860+ /* Store vector loads in the corresponding SLP_NODE. */
4861+ if (slp && !slp_perm)
4862+ VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node),
4863+ new_stmt);
4864+ }
4865 }
4866
4867 if (slp && !slp_perm)
4868@@ -4345,12 +4526,9 @@
4869 {
4870 if (strided_load)
4871 {
4872- if (!vect_transform_strided_load (stmt, dr_chain, group_size, gsi))
4873- return false;
4874-
4875+ if (!load_lanes_p)
4876+ vect_transform_strided_load (stmt, dr_chain, group_size, gsi);
4877 *vec_stmt = STMT_VINFO_VEC_STMT (stmt_info);
4878- VEC_free (tree, heap, dr_chain);
4879- dr_chain = VEC_alloc (tree, heap, group_size);
4880 }
4881 else
4882 {
4883@@ -4361,11 +4539,10 @@
4884 prev_stmt_info = vinfo_for_stmt (new_stmt);
4885 }
4886 }
4887+ if (dr_chain)
4888+ VEC_free (tree, heap, dr_chain);
4889 }
4890
4891- if (dr_chain)
4892- VEC_free (tree, heap, dr_chain);
4893-
4894 return true;
4895 }
4896
4897@@ -4769,27 +4946,6 @@
4898 return false;
4899 }
4900
4901- if (!PURE_SLP_STMT (stmt_info))
4902- {
4903- /* Groups of strided accesses whose size is not a power of 2 are not
4904- vectorizable yet using loop-vectorization. Therefore, if this stmt
4905- feeds non-SLP-able stmts (i.e., this stmt has to be both SLPed and
4906- loop-based vectorized), the loop cannot be vectorized. */
4907- if (STMT_VINFO_STRIDED_ACCESS (stmt_info)
4908- && exact_log2 (DR_GROUP_SIZE (vinfo_for_stmt (
4909- DR_GROUP_FIRST_DR (stmt_info)))) == -1)
4910- {
4911- if (vect_print_dump_info (REPORT_DETAILS))
4912- {
4913- fprintf (vect_dump, "not vectorized: the size of group "
4914- "of strided accesses is not a power of 2");
4915- print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
4916- }
4917-
4918- return false;
4919- }
4920- }
4921-
4922 return true;
4923 }
4924
4925
4926=== modified file 'gcc/tree-vectorizer.h'
4927--- old/gcc/tree-vectorizer.h 2010-12-23 16:25:52 +0000
4928+++ new/gcc/tree-vectorizer.h 2011-05-05 15:43:06 +0000
4929@@ -788,9 +788,9 @@
4930 extern tree vectorizable_function (gimple, tree, tree);
4931 extern void vect_model_simple_cost (stmt_vec_info, int, enum vect_def_type *,
4932 slp_tree);
4933-extern void vect_model_store_cost (stmt_vec_info, int, enum vect_def_type,
4934- slp_tree);
4935-extern void vect_model_load_cost (stmt_vec_info, int, slp_tree);
4936+extern void vect_model_store_cost (stmt_vec_info, int, bool,
4937+ enum vect_def_type, slp_tree);
4938+extern void vect_model_load_cost (stmt_vec_info, int, bool, slp_tree);
4939 extern void vect_finish_stmt_generation (gimple, gimple,
4940 gimple_stmt_iterator *);
4941 extern bool vect_mark_stmts_to_be_vectorized (loop_vec_info);
4942@@ -823,21 +823,22 @@
4943 extern bool vect_analyze_data_ref_accesses (loop_vec_info, bb_vec_info);
4944 extern bool vect_prune_runtime_alias_test_list (loop_vec_info);
4945 extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *);
4946-extern tree vect_create_data_ref_ptr (gimple, struct loop *, tree, tree *,
4947- gimple *, bool, bool *);
4948+extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree,
4949+ tree *, gimple *, bool, bool *);
4950 extern tree bump_vector_ptr (tree, gimple, gimple_stmt_iterator *, gimple, tree);
4951 extern tree vect_create_destination_var (tree, tree);
4952-extern bool vect_strided_store_supported (tree);
4953-extern bool vect_strided_load_supported (tree);
4954-extern bool vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple,
4955+extern bool vect_strided_store_supported (tree, unsigned HOST_WIDE_INT);
4956+extern bool vect_store_lanes_supported (tree, unsigned HOST_WIDE_INT);
4957+extern bool vect_strided_load_supported (tree, unsigned HOST_WIDE_INT);
4958+extern bool vect_load_lanes_supported (tree, unsigned HOST_WIDE_INT);
4959+extern void vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple,
4960 gimple_stmt_iterator *, VEC(tree,heap) **);
4961 extern tree vect_setup_realignment (gimple, gimple_stmt_iterator *, tree *,
4962 enum dr_alignment_support, tree,
4963 struct loop **);
4964-extern bool vect_permute_load_chain (VEC(tree,heap) *,unsigned int, gimple,
4965- gimple_stmt_iterator *, VEC(tree,heap) **);
4966-extern bool vect_transform_strided_load (gimple, VEC(tree,heap) *, int,
4967+extern void vect_transform_strided_load (gimple, VEC(tree,heap) *, int,
4968 gimple_stmt_iterator *);
4969+extern void vect_record_strided_load_vectors (gimple, VEC(tree,heap) *);
4970 extern int vect_get_place_in_interleaving_chain (gimple, gimple);
4971 extern tree vect_get_new_vect_var (tree, enum vect_var_kind, const char *);
4972 extern tree vect_create_addr_base_for_vector_ref (gimple, gimple_seq *,
4973
4974=== modified file 'gcc/tree.c'
4975--- old/gcc/tree.c 2011-05-18 13:29:24 +0000
4976+++ new/gcc/tree.c 2011-06-02 12:12:00 +0000
4977@@ -7321,6 +7321,15 @@
4978 return build_array_type_1 (elt_type, index_type, false);
4979 }
4980
4981+/* Return a representation of ELT_TYPE[NELTS], using indices of type
4982+ sizetype. */
4983+
4984+tree
4985+build_array_type_nelts (tree elt_type, unsigned HOST_WIDE_INT nelts)
4986+{
4987+ return build_array_type (elt_type, build_index_type (size_int (nelts - 1)));
4988+}
4989+
4990 /* Recursively examines the array elements of TYPE, until a non-array
4991 element type is found. */
4992
4993
4994=== modified file 'gcc/tree.h'
4995--- old/gcc/tree.h 2011-03-11 22:38:58 +0000
4996+++ new/gcc/tree.h 2011-05-05 15:43:06 +0000
4997@@ -4192,6 +4192,7 @@
4998 extern tree build_index_type (tree);
4999 extern tree build_array_type (tree, tree);
5000 extern tree build_nonshared_array_type (tree, tree);
5001+extern tree build_array_type_nelts (tree, unsigned HOST_WIDE_INT);
5002 extern tree build_function_type (tree, tree);
5003 extern tree build_function_type_list (tree, ...);
5004 extern tree build_function_type_skip_args (tree, bitmap);
5005
5006=== modified file 'gcc/value-prof.c'
5007--- old/gcc/value-prof.c 2011-01-29 03:54:56 +0000
5008+++ new/gcc/value-prof.c 2011-05-05 15:42:22 +0000
5009@@ -1242,6 +1242,9 @@
5010 if (TREE_CODE (callee) == FUNCTION_DECL)
5011 return false;
5012
5013+ if (gimple_call_internal_p (stmt))
5014+ return false;
5015+
5016 histogram = gimple_histogram_value_of_type (cfun, stmt, HIST_TYPE_INDIR_CALL);
5017 if (!histogram)
5018 return false;
5019@@ -1630,6 +1633,7 @@
5020 tree callee;
5021
5022 if (gimple_code (stmt) != GIMPLE_CALL
5023+ || gimple_call_internal_p (stmt)
5024 || gimple_call_fndecl (stmt) != NULL_TREE)
5025 return;
5026
5027
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch
new file mode 100644
index 000000000..b64991836
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch
@@ -0,0 +1,329 @@
12011-06-07 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-06-07 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/arm.md (*maddhidi4tb, *maddhidi4tt): New define_insns.
9 (*maddhisi4tb, *maddhisi4tt): New define_insns.
10
11 gcc/testsuite/
12 * gcc.target/arm/smlatb-1.c: New file.
13 * gcc.target/arm/smlatt-1.c: New file.
14 * gcc.target/arm/smlaltb-1.c: New file.
15 * gcc.target/arm/smlaltt-1.c: New file.
16
172011-06-07 Andrew Stubbs <ams@codesourcery.com>
18
19 Backport from FSF:
20
21 2011-06-07 Bernd Schmidt <bernds@codesourcery.com>
22 Andrew Stubbs <ams@codesourcery.com>
23
24 gcc/
25 * simplify-rtx.c (simplify_unary_operation_1): Canonicalize widening
26 multiplies.
27 * doc/md.texi (Canonicalization of Instructions): Document widening
28 multiply canonicalization.
29
30 gcc/testsuite/
31 * gcc.target/arm/mla-2.c: New test.
32
33=== modified file 'gcc/config/arm/arm.md'
34--- old/gcc/config/arm/arm.md 2011-05-13 13:42:39 +0000
35+++ new/gcc/config/arm/arm.md 2011-06-02 15:58:33 +0000
36@@ -1809,6 +1809,36 @@
37 (set_attr "predicable" "yes")]
38 )
39
40+;; Note: there is no maddhisi4ibt because this one is canonical form
41+(define_insn "*maddhisi4tb"
42+ [(set (match_operand:SI 0 "s_register_operand" "=r")
43+ (plus:SI (mult:SI (ashiftrt:SI
44+ (match_operand:SI 1 "s_register_operand" "r")
45+ (const_int 16))
46+ (sign_extend:SI
47+ (match_operand:HI 2 "s_register_operand" "r")))
48+ (match_operand:SI 3 "s_register_operand" "r")))]
49+ "TARGET_DSP_MULTIPLY"
50+ "smlatb%?\\t%0, %1, %2, %3"
51+ [(set_attr "insn" "smlaxy")
52+ (set_attr "predicable" "yes")]
53+)
54+
55+(define_insn "*maddhisi4tt"
56+ [(set (match_operand:SI 0 "s_register_operand" "=r")
57+ (plus:SI (mult:SI (ashiftrt:SI
58+ (match_operand:SI 1 "s_register_operand" "r")
59+ (const_int 16))
60+ (ashiftrt:SI
61+ (match_operand:SI 2 "s_register_operand" "r")
62+ (const_int 16)))
63+ (match_operand:SI 3 "s_register_operand" "r")))]
64+ "TARGET_DSP_MULTIPLY"
65+ "smlatt%?\\t%0, %1, %2, %3"
66+ [(set_attr "insn" "smlaxy")
67+ (set_attr "predicable" "yes")]
68+)
69+
70 (define_insn "*maddhidi4"
71 [(set (match_operand:DI 0 "s_register_operand" "=r")
72 (plus:DI
73@@ -1822,6 +1852,39 @@
74 [(set_attr "insn" "smlalxy")
75 (set_attr "predicable" "yes")])
76
77+;; Note: there is no maddhidi4ibt because this one is canonical form
78+(define_insn "*maddhidi4tb"
79+ [(set (match_operand:DI 0 "s_register_operand" "=r")
80+ (plus:DI
81+ (mult:DI (sign_extend:DI
82+ (ashiftrt:SI
83+ (match_operand:SI 1 "s_register_operand" "r")
84+ (const_int 16)))
85+ (sign_extend:DI
86+ (match_operand:HI 2 "s_register_operand" "r")))
87+ (match_operand:DI 3 "s_register_operand" "0")))]
88+ "TARGET_DSP_MULTIPLY"
89+ "smlaltb%?\\t%Q0, %R0, %1, %2"
90+ [(set_attr "insn" "smlalxy")
91+ (set_attr "predicable" "yes")])
92+
93+(define_insn "*maddhidi4tt"
94+ [(set (match_operand:DI 0 "s_register_operand" "=r")
95+ (plus:DI
96+ (mult:DI (sign_extend:DI
97+ (ashiftrt:SI
98+ (match_operand:SI 1 "s_register_operand" "r")
99+ (const_int 16)))
100+ (sign_extend:DI
101+ (ashiftrt:SI
102+ (match_operand:SI 2 "s_register_operand" "r")
103+ (const_int 16))))
104+ (match_operand:DI 3 "s_register_operand" "0")))]
105+ "TARGET_DSP_MULTIPLY"
106+ "smlaltt%?\\t%Q0, %R0, %1, %2"
107+ [(set_attr "insn" "smlalxy")
108+ (set_attr "predicable" "yes")])
109+
110 (define_expand "mulsf3"
111 [(set (match_operand:SF 0 "s_register_operand" "")
112 (mult:SF (match_operand:SF 1 "s_register_operand" "")
113
114=== modified file 'gcc/doc/md.texi'
115--- old/gcc/doc/md.texi 2011-05-05 15:43:06 +0000
116+++ new/gcc/doc/md.texi 2011-06-07 11:18:20 +0000
117@@ -5929,6 +5929,23 @@
118 will be written using @code{zero_extract} rather than the equivalent
119 @code{and} or @code{sign_extract} operations.
120
121+@cindex @code{mult}, canonicalization of
122+@item
123+@code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
124+(sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
125+(sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
126+for @code{zero_extend}.
127+
128+@item
129+@code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
130+@var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
131+to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
132+@var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
133+patterns using @code{zero_extend} and @code{lshiftrt}. If the second
134+operand of @code{mult} is also a shift, then that is extended also.
135+This transformation is only applied when it can be proven that the
136+original operation had sufficient precision to prevent overflow.
137+
138 @end itemize
139
140 Further canonicalization rules are defined in the function
141
142=== modified file 'gcc/simplify-rtx.c'
143--- old/gcc/simplify-rtx.c 2011-05-27 14:31:18 +0000
144+++ new/gcc/simplify-rtx.c 2011-06-02 12:32:16 +0000
145@@ -1000,6 +1000,48 @@
146 && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
147 return XEXP (op, 0);
148
149+ /* Extending a widening multiplication should be canonicalized to
150+ a wider widening multiplication. */
151+ if (GET_CODE (op) == MULT)
152+ {
153+ rtx lhs = XEXP (op, 0);
154+ rtx rhs = XEXP (op, 1);
155+ enum rtx_code lcode = GET_CODE (lhs);
156+ enum rtx_code rcode = GET_CODE (rhs);
157+
158+ /* Widening multiplies usually extend both operands, but sometimes
159+ they use a shift to extract a portion of a register. */
160+ if ((lcode == SIGN_EXTEND
161+ || (lcode == ASHIFTRT && CONST_INT_P (XEXP (lhs, 1))))
162+ && (rcode == SIGN_EXTEND
163+ || (rcode == ASHIFTRT && CONST_INT_P (XEXP (rhs, 1)))))
164+ {
165+ enum machine_mode lmode = GET_MODE (lhs);
166+ enum machine_mode rmode = GET_MODE (rhs);
167+ int bits;
168+
169+ if (lcode == ASHIFTRT)
170+ /* Number of bits not shifted off the end. */
171+ bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1));
172+ else /* lcode == SIGN_EXTEND */
173+ /* Size of inner mode. */
174+ bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0)));
175+
176+ if (rcode == ASHIFTRT)
177+ bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1));
178+ else /* rcode == SIGN_EXTEND */
179+ bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0)));
180+
181+ /* We can only widen multiplies if the result is mathematiclly
182+ equivalent. I.e. if overflow was impossible. */
183+ if (bits <= GET_MODE_PRECISION (GET_MODE (op)))
184+ return simplify_gen_binary
185+ (MULT, mode,
186+ simplify_gen_unary (SIGN_EXTEND, mode, lhs, lmode),
187+ simplify_gen_unary (SIGN_EXTEND, mode, rhs, rmode));
188+ }
189+ }
190+
191 /* Check for a sign extension of a subreg of a promoted
192 variable, where the promotion is sign-extended, and the
193 target mode is the same as the variable's promotion. */
194@@ -1071,6 +1113,48 @@
195 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
196 return rtl_hooks.gen_lowpart_no_emit (mode, op);
197
198+ /* Extending a widening multiplication should be canonicalized to
199+ a wider widening multiplication. */
200+ if (GET_CODE (op) == MULT)
201+ {
202+ rtx lhs = XEXP (op, 0);
203+ rtx rhs = XEXP (op, 1);
204+ enum rtx_code lcode = GET_CODE (lhs);
205+ enum rtx_code rcode = GET_CODE (rhs);
206+
207+ /* Widening multiplies usually extend both operands, but sometimes
208+ they use a shift to extract a portion of a register. */
209+ if ((lcode == ZERO_EXTEND
210+ || (lcode == LSHIFTRT && CONST_INT_P (XEXP (lhs, 1))))
211+ && (rcode == ZERO_EXTEND
212+ || (rcode == LSHIFTRT && CONST_INT_P (XEXP (rhs, 1)))))
213+ {
214+ enum machine_mode lmode = GET_MODE (lhs);
215+ enum machine_mode rmode = GET_MODE (rhs);
216+ int bits;
217+
218+ if (lcode == LSHIFTRT)
219+ /* Number of bits not shifted off the end. */
220+ bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1));
221+ else /* lcode == ZERO_EXTEND */
222+ /* Size of inner mode. */
223+ bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0)));
224+
225+ if (rcode == LSHIFTRT)
226+ bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1));
227+ else /* rcode == ZERO_EXTEND */
228+ bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0)));
229+
230+ /* We can only widen multiplies if the result is mathematiclly
231+ equivalent. I.e. if overflow was impossible. */
232+ if (bits <= GET_MODE_PRECISION (GET_MODE (op)))
233+ return simplify_gen_binary
234+ (MULT, mode,
235+ simplify_gen_unary (ZERO_EXTEND, mode, lhs, lmode),
236+ simplify_gen_unary (ZERO_EXTEND, mode, rhs, rmode));
237+ }
238+ }
239+
240 /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
241 if (GET_CODE (op) == ZERO_EXTEND)
242 return simplify_gen_unary (ZERO_EXTEND, mode, XEXP (op, 0),
243
244=== added file 'gcc/testsuite/gcc.target/arm/mla-2.c'
245--- old/gcc/testsuite/gcc.target/arm/mla-2.c 1970-01-01 00:00:00 +0000
246+++ new/gcc/testsuite/gcc.target/arm/mla-2.c 2011-06-02 12:32:16 +0000
247@@ -0,0 +1,9 @@
248+/* { dg-do compile } */
249+/* { dg-options "-O2 -march=armv7-a" } */
250+
251+long long foolong (long long x, short *a, short *b)
252+{
253+ return x + *a * *b;
254+}
255+
256+/* { dg-final { scan-assembler "smlalbb" } } */
257
258=== added file 'gcc/testsuite/gcc.target/arm/smlaltb-1.c'
259--- old/gcc/testsuite/gcc.target/arm/smlaltb-1.c 1970-01-01 00:00:00 +0000
260+++ new/gcc/testsuite/gcc.target/arm/smlaltb-1.c 2011-06-02 15:58:33 +0000
261@@ -0,0 +1,13 @@
262+/* { dg-do compile } */
263+/* { dg-options "-O2 -march=armv7-a" } */
264+
265+long long int
266+foo (long long x, int in)
267+{
268+ short a = in & 0xffff;
269+ short b = (in & 0xffff0000) >> 16;
270+
271+ return x + b * a;
272+}
273+
274+/* { dg-final { scan-assembler "smlaltb" } } */
275
276=== added file 'gcc/testsuite/gcc.target/arm/smlaltt-1.c'
277--- old/gcc/testsuite/gcc.target/arm/smlaltt-1.c 1970-01-01 00:00:00 +0000
278+++ new/gcc/testsuite/gcc.target/arm/smlaltt-1.c 2011-06-02 15:58:33 +0000
279@@ -0,0 +1,13 @@
280+/* { dg-do compile } */
281+/* { dg-options "-O2 -march=armv7-a" } */
282+
283+long long int
284+foo (long long x, int in1, int in2)
285+{
286+ short a = (in1 & 0xffff0000) >> 16;
287+ short b = (in2 & 0xffff0000) >> 16;
288+
289+ return x + b * a;
290+}
291+
292+/* { dg-final { scan-assembler "smlaltt" } } */
293
294=== added file 'gcc/testsuite/gcc.target/arm/smlatb-1.c'
295--- old/gcc/testsuite/gcc.target/arm/smlatb-1.c 1970-01-01 00:00:00 +0000
296+++ new/gcc/testsuite/gcc.target/arm/smlatb-1.c 2011-06-02 15:58:33 +0000
297@@ -0,0 +1,13 @@
298+/* { dg-do compile } */
299+/* { dg-options "-O2 -march=armv7-a" } */
300+
301+int
302+foo (int x, int in)
303+{
304+ short a = in & 0xffff;
305+ short b = (in & 0xffff0000) >> 16;
306+
307+ return x + b * a;
308+}
309+
310+/* { dg-final { scan-assembler "smlatb" } } */
311
312=== added file 'gcc/testsuite/gcc.target/arm/smlatt-1.c'
313--- old/gcc/testsuite/gcc.target/arm/smlatt-1.c 1970-01-01 00:00:00 +0000
314+++ new/gcc/testsuite/gcc.target/arm/smlatt-1.c 2011-06-02 15:58:33 +0000
315@@ -0,0 +1,13 @@
316+/* { dg-do compile } */
317+/* { dg-options "-O2 -march=armv7-a" } */
318+
319+int
320+foo (int x, int in1, int in2)
321+{
322+ short a = (in1 & 0xffff0000) >> 16;
323+ short b = (in2 & 0xffff0000) >> 16;
324+
325+ return x + b * a;
326+}
327+
328+/* { dg-final { scan-assembler "smlatt" } } */
329
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch
new file mode 100644
index 000000000..b8f587c9f
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch
@@ -0,0 +1,120 @@
12011-06-10 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline:
4 gcc/
5 2011-06-02 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
6 * config/arm/neon.md (orndi3_neon): Actually split it.
7
8
92011-06-10 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
10
11 Backport from mainline.
12 gcc/
13 2011-05-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
14
15 * config/arm/neon.md ("orn<mode>3_neon"): Canonicalize not.
16 ("orndi3_neon"): Likewise.
17 ("bic<mode>3_neon"): Likewise.
18
19 gcc/testsuite
20 2011-05-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
21
22 * gcc.target/arm/neon-vorn-vbic.c: New test.
23
24=== modified file 'gcc/config/arm/neon.md'
25--- old/gcc/config/arm/neon.md 2011-06-02 12:12:00 +0000
26+++ new/gcc/config/arm/neon.md 2011-06-04 00:04:47 +0000
27@@ -783,30 +783,57 @@
28
29 (define_insn "orn<mode>3_neon"
30 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
31- (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
32- (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
33+ (ior:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
34+ (match_operand:VDQ 1 "s_register_operand" "w")))]
35 "TARGET_NEON"
36 "vorn\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
37 [(set_attr "neon_type" "neon_int_1")]
38 )
39
40-(define_insn "orndi3_neon"
41- [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
42- (ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0")
43- (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))]
44+;; TODO: investigate whether we should disable
45+;; this and bicdi3_neon for the A8 in line with the other
46+;; changes above.
47+(define_insn_and_split "orndi3_neon"
48+ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
49+ (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r"))
50+ (match_operand:DI 1 "s_register_operand" "w,r,r,0")))]
51 "TARGET_NEON"
52 "@
53 vorn\t%P0, %P1, %P2
54 #
55+ #
56 #"
57- [(set_attr "neon_type" "neon_int_1,*,*")
58- (set_attr "length" "*,8,8")]
59+ "reload_completed &&
60+ (TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))"
61+ [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
62+ (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
63+ "
64+ {
65+ if (TARGET_THUMB2)
66+ {
67+ operands[3] = gen_highpart (SImode, operands[0]);
68+ operands[0] = gen_lowpart (SImode, operands[0]);
69+ operands[4] = gen_highpart (SImode, operands[2]);
70+ operands[2] = gen_lowpart (SImode, operands[2]);
71+ operands[5] = gen_highpart (SImode, operands[1]);
72+ operands[1] = gen_lowpart (SImode, operands[1]);
73+ }
74+ else
75+ {
76+ emit_insn (gen_one_cmpldi2 (operands[0], operands[2]));
77+ emit_insn (gen_iordi3 (operands[0], operands[1], operands[0]));
78+ DONE;
79+ }
80+ }"
81+ [(set_attr "neon_type" "neon_int_1,*,*,*")
82+ (set_attr "length" "*,16,8,8")
83+ (set_attr "arch" "any,a,t2,t2")]
84 )
85
86 (define_insn "bic<mode>3_neon"
87 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
88- (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
89- (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
90+ (and:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
91+ (match_operand:VDQ 1 "s_register_operand" "w")))]
92 "TARGET_NEON"
93 "vbic\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
94 [(set_attr "neon_type" "neon_int_1")]
95
96=== added file 'gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c'
97--- old/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c 1970-01-01 00:00:00 +0000
98+++ new/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c 2011-06-03 23:50:02 +0000
99@@ -0,0 +1,20 @@
100+/* { dg-do compile } */
101+/* { dg-require-effective-target arm_neon_ok } */
102+/* { dg-options "-O2 -ftree-vectorize" } */
103+/* { dg-add-options arm_neon } */
104+
105+void bor (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
106+{
107+ int i;
108+ for (i = 0; i < 9; i++)
109+ c[i] = b[i] | (~a[i]);
110+}
111+void bic (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
112+{
113+ int i;
114+ for (i = 0; i < 9; i++)
115+ c[i] = b[i] & (~a[i]);
116+}
117+
118+/* { dg-final { scan-assembler "vorn\\t" } } */
119+/* { dg-final { scan-assembler "vbic\\t" } } */
120
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc b/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
index 5f506f00d..e3f6114e5 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+++ b/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
@@ -2,7 +2,6 @@ GCC-4_6-BRANCH-LINARO-BACKPORTS = " \
2file://linaro/gcc-4.6-linaro-r106720.patch \ 2file://linaro/gcc-4.6-linaro-r106720.patch \
3file://linaro/gcc-4.6-linaro-r106723.patch \ 3file://linaro/gcc-4.6-linaro-r106723.patch \
4file://linaro/gcc-4.6-linaro-r106729.patch \ 4file://linaro/gcc-4.6-linaro-r106729.patch \
5file://linaro/gcc-4.6-linaro-r106731.patch \
6file://linaro/gcc-4.6-linaro-r106733.patch \ 5file://linaro/gcc-4.6-linaro-r106733.patch \
7file://linaro/gcc-4.6-linaro-r106737.patch \ 6file://linaro/gcc-4.6-linaro-r106737.patch \
8file://linaro/gcc-4.6-linaro-r106738.patch \ 7file://linaro/gcc-4.6-linaro-r106738.patch \
@@ -15,4 +14,8 @@ file://linaro/gcc-4.6-linaro-r106744.patch \
15file://linaro/gcc-4.6-linaro-r106746.patch \ 14file://linaro/gcc-4.6-linaro-r106746.patch \
16file://linaro/gcc-4.6-linaro-r106747.patch \ 15file://linaro/gcc-4.6-linaro-r106747.patch \
17file://linaro/gcc-4.6-linaro-r106750.patch \ 16file://linaro/gcc-4.6-linaro-r106750.patch \
17file://linaro/gcc-4.6-linaro-r106751.patch \
18file://linaro/gcc-4.6-linaro-r106753.patch \
19file://linaro/gcc-4.6-linaro-r106754.patch \
20file://linaro/gcc-4.6-linaro-r106755.patch \
18" 21"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc b/meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc
new file mode 100644
index 000000000..38167bf30
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc
@@ -0,0 +1,3 @@
1# this will prepend this layer to FILESPATH
2FILESEXTRAPATHS := "${THISDIR}/gcc-4.6.0"
3PRINC = "0"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend
new file mode 100644
index 000000000..fc419b62b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-15 04:35:40 +0000