From 8052751332dbd5bc35f854735e99d9bb20086c61 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Sun, 12 Jun 2011 21:06:58 -0700 Subject: Add bbappend files for gcc 4.6.0 from oe-core The bbappends add patches for linaro so with this we can enhance gcc 4.6.0 from oe-core and have patches that are in meta-oe on top of it. Add patches from for linaro 4.6 This obsoletes the need of having gcc 4.6 recipes in meta-oe Signed-off-by: Khem Raj Signed-off-by: Koen Kooi --- .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch | 51 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch | 63 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch | 32 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch | 653 +++ .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch | 126 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch | 177 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch | 140 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106740.patch | 294 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch | 254 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch | 6123 ++++++++++++++++++++ .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch | 25 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch | 21 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch | 24 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch | 640 ++ .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch | 30 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch | 134 + .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch | 5027 ++++++++++++++++ .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch | 329 ++ .../gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch | 120 + .../gcc/gcc-4_6-branch-linaro-backports.inc | 5 +- meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc | 3 + .../gcc/gcc-cross-canadian_4.6.0.bbappend | 3 + .../gcc/gcc-cross-initial_4.6.0.bbappend | 3 + .../gcc/gcc-cross-intermediate_4.6.0.bbappend | 3 + .../recipes-devtools/gcc/gcc-cross_4.6.0.bbappend | 3 + .../gcc/gcc-crosssdk-initial_4.6.0.bbappend | 3 + .../gcc/gcc-crosssdk-intermediate_4.6.0.bbappend | 3 + .../gcc/gcc-crosssdk_4.6.0.bbappend | 3 + .../gcc/gcc-runtime_4.6.0.bbappend | 3 + meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend | 3 + meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend | 3 + 31 files changed, 14300 insertions(+), 1 deletion(-) create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106740.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch create mode 100644 meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc create mode 100644 meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend create mode 100644 meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch new file mode 100644 index 0000000000..4c573f401e --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106720.patch @@ -0,0 +1,51 @@ +2011-02-21 Andrew Stubbs + Julian Brown + Mark Shinwell + + Forward-ported from Linaro GCC 4.5 (bzr99324). + + gcc/ + * config/arm/arm.h (arm_class_likely_spilled_p): Check against + LO_REGS only for Thumb-1. + (MODE_BASE_REG_CLASS): Restrict base registers to those which can + be used in short instructions when optimising for size on Thumb-2. + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2011-01-29 03:20:57 +0000 ++++ new/gcc/config/arm/arm.c 2011-02-21 14:04:51 +0000 +@@ -22304,14 +22304,16 @@ + + /* Implement TARGET_CLASS_LIKELY_SPILLED_P. + +- We need to define this for LO_REGS on thumb. Otherwise we can end up +- using r0-r4 for function arguments, r7 for the stack frame and don't +- have enough left over to do doubleword arithmetic. */ +- ++ We need to define this for LO_REGS on Thumb-1. Otherwise we can end up ++ using r0-r4 for function arguments, r7 for the stack frame and don't have ++ enough left over to do doubleword arithmetic. For Thumb-2 all the ++ potentially problematic instructions accept high registers so this is not ++ necessary. Care needs to be taken to avoid adding new Thumb-2 patterns ++ that require many low registers. */ + static bool + arm_class_likely_spilled_p (reg_class_t rclass) + { +- if ((TARGET_THUMB && rclass == LO_REGS) ++ if ((TARGET_THUMB1 && rclass == LO_REGS) + || rclass == CC_REG) + return true; + + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2011-01-29 03:20:57 +0000 ++++ new/gcc/config/arm/arm.h 2011-02-21 14:04:51 +0000 +@@ -1185,7 +1185,7 @@ + when addressing quantities in QI or HI mode; if we don't know the + mode, then we must be conservative. */ + #define MODE_BASE_REG_CLASS(MODE) \ +- (TARGET_32BIT ? CORE_REGS : \ ++ (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ + (((MODE) == SImode) ? BASE_REGS : LO_REGS)) + + /* For Thumb we can not support SP+reg addressing, so we return LO_REGS + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch new file mode 100644 index 0000000000..5271ffa6f2 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106723.patch @@ -0,0 +1,63 @@ +2011-02-02 Richard Sandiford + + gcc/ + PR target/47551 + * config/arm/arm.c (coproc_secondary_reload_class): Handle + structure modes. Don't check neon_vector_mem_operand for + vector or structure modes. + + gcc/testsuite/ + PR target/47551 + * gcc.target/arm/neon-modes-2.c: New test. + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2011-02-21 14:04:51 +0000 ++++ new/gcc/config/arm/arm.c 2011-03-02 11:38:43 +0000 +@@ -9139,11 +9139,14 @@ + return GENERAL_REGS; + } + ++ /* The neon move patterns handle all legitimate vector and struct ++ addresses. */ + if (TARGET_NEON ++ && MEM_P (x) + && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT +- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) +- && neon_vector_mem_operand (x, 0)) +- return NO_REGS; ++ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT ++ || VALID_NEON_STRUCT_MODE (mode))) ++ return NO_REGS; + + if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) + return NO_REGS; + +=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-2.c' +--- old/gcc/testsuite/gcc.target/arm/neon-modes-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-modes-2.c 2011-02-02 10:02:45 +0000 +@@ -0,0 +1,24 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O1" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++ ++#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20) ++#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1) ++#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A) ++ ++#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5) ++ ++void ++bar (uint32_t *ptr, int y) ++{ ++ uint32x2x3_t MANY (SETUP); ++ int *x = __builtin_alloca (y); ++ int z[0x1000]; ++ foo (x, z); ++ MANY (MODIFY); ++ foo (x, z); ++ MANY (STORE); ++} + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch new file mode 100644 index 0000000000..465d09c1a0 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106729.patch @@ -0,0 +1,32 @@ +2011-03-22 Andrew Stubbs + + Backport from FSF: + + 2011-03-21 Daniel Jacobowitz + + gcc/ + * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test + for barrier handlers. + +=== modified file 'gcc/config/arm/unwind-arm.c' +--- old/gcc/config/arm/unwind-arm.c 2009-10-30 14:55:10 +0000 ++++ new/gcc/config/arm/unwind-arm.c 2011-03-22 10:59:10 +0000 +@@ -1196,8 +1196,6 @@ + ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1]; + + if (data[0] & uint32_highbit) +- phase2_call_unexpected_after_unwind = 1; +- else + { + data += rtti_count + 1; + /* Setup for entry to the handler. */ +@@ -1207,6 +1205,8 @@ + _Unwind_SetGR (context, 0, (_uw) ucbp); + return _URC_INSTALL_CONTEXT; + } ++ else ++ phase2_call_unexpected_after_unwind = 1; + } + if (data[0] & uint32_highbit) + data++; + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch new file mode 100644 index 0000000000..4b0079e1dc --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106733.patch @@ -0,0 +1,653 @@ +2011-03-27 Ira Rosen + + gcc/ + * doc/invoke.texi (max-stores-to-sink): Document. + * params.h (MAX_STORES_TO_SINK): Define. + * opts.c (finish_options): Set MAX_STORES_TO_SINK to 0 + if either vectorization or if-conversion is disabled. + * tree-data-ref.c (dr_equal_offsets_p1): Moved and renamed from + tree-vect-data-refs.c vect_equal_offsets. + (dr_equal_offsets_p): New function. + (find_data_references_in_bb): Remove static. + * tree-data-ref.h (find_data_references_in_bb): Declare. + (dr_equal_offsets_p): Likewise. + * tree-vect-data-refs.c (vect_equal_offsets): Move to tree-data-ref.c. + (vect_drs_dependent_in_basic_block): Update calls to + vect_equal_offsets. + (vect_check_interleaving): Likewise. + * tree-ssa-phiopt.c: Include cfgloop.h and tree-data-ref.h. + (cond_if_else_store_replacement): Rename to... + (cond_if_else_store_replacement_1): ... this. Change arguments and + documentation. + (cond_if_else_store_replacement): New function. + * Makefile.in (tree-ssa-phiopt.o): Adjust dependencies. + * params.def (PARAM_MAX_STORES_TO_SINK): Define. + + gcc/testsuite/ + * gcc.dg/vect/vect-cselim-1.c: New test. + * gcc.dg/vect/vect-cselim-2.c: New test. + +=== modified file 'gcc/Makefile.in' +--- old/gcc/Makefile.in 2011-03-26 09:20:34 +0000 ++++ new/gcc/Makefile.in 2011-04-18 11:31:29 +0000 +@@ -2422,7 +2422,8 @@ + tree-ssa-phiopt.o : tree-ssa-phiopt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) $(GGC_H) $(TREE_H) $(TM_P_H) $(BASIC_BLOCK_H) \ + $(TREE_FLOW_H) $(TREE_PASS_H) $(TREE_DUMP_H) langhooks.h $(FLAGS_H) \ +- $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h ++ $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h $(CFGLOOP_H) \ ++ $(TREE_DATA_REF_H) + tree-nrv.o : tree-nrv.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) $(TREE_H) $(FUNCTION_H) $(BASIC_BLOCK_H) $(FLAGS_H) \ + $(DIAGNOSTIC_H) $(TREE_FLOW_H) $(TIMEVAR_H) $(TREE_DUMP_H) $(TREE_PASS_H) \ + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2011-03-29 14:24:42 +0000 ++++ new/gcc/doc/invoke.texi 2011-04-18 11:31:29 +0000 +@@ -8909,6 +8909,11 @@ + The maximum number of namespaces to consult for suggestions when C++ + name lookup fails for an identifier. The default is 1000. + ++@item max-stores-to-sink ++The maximum number of conditional stores paires that can be sunk. Set to 0 ++if either vectorization (@option{-ftree-vectorize}) or if-conversion ++(@option{-ftree-loop-if-convert}) is disabled. The default is 2. ++ + @end table + @end table + + +=== modified file 'gcc/opts.c' +--- old/gcc/opts.c 2011-02-17 22:51:57 +0000 ++++ new/gcc/opts.c 2011-03-27 09:38:18 +0000 +@@ -823,6 +823,12 @@ + opts->x_flag_split_stack = 0; + } + } ++ ++ /* Set PARAM_MAX_STORES_TO_SINK to 0 if either vectorization or if-conversion ++ is disabled. */ ++ if (!opts->x_flag_tree_vectorize || !opts->x_flag_tree_loop_if_convert) ++ maybe_set_param_value (PARAM_MAX_STORES_TO_SINK, 0, ++ opts->x_param_values, opts_set->x_param_values); + } + + #define LEFT_COLUMN 27 + +=== modified file 'gcc/params.def' +--- old/gcc/params.def 2011-03-26 09:20:34 +0000 ++++ new/gcc/params.def 2011-04-18 11:31:29 +0000 +@@ -883,6 +883,13 @@ + "name lookup fails", + 1000, 0, 0) + ++/* Maximum number of conditional store pairs that can be sunk. */ ++DEFPARAM (PARAM_MAX_STORES_TO_SINK, ++ "max-stores-to-sink", ++ "Maximum number of conditional store pairs that can be sunk", ++ 2, 0, 0) ++ ++ + /* + Local variables: + mode:c + +=== modified file 'gcc/params.h' +--- old/gcc/params.h 2011-01-13 13:41:03 +0000 ++++ new/gcc/params.h 2011-03-27 09:38:18 +0000 +@@ -206,4 +206,6 @@ + PARAM_VALUE (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO) + #define MIN_NONDEBUG_INSN_UID \ + PARAM_VALUE (PARAM_MIN_NONDEBUG_INSN_UID) ++#define MAX_STORES_TO_SINK \ ++ PARAM_VALUE (PARAM_MAX_STORES_TO_SINK) + #endif /* ! GCC_PARAMS_H */ + +=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-03-27 09:38:18 +0000 +@@ -0,0 +1,86 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 50 ++ ++typedef struct { ++ short a; ++ short b; ++} data; ++ ++data in1[N], in2[N], out[N]; ++short result[N*2] = {7,-7,9,-6,11,-5,13,-4,15,-3,17,-2,19,-1,21,0,23,1,25,2,27,3,29,4,31,5,33,6,35,7,37,8,39,9,41,10,43,11,45,12,47,13,49,14,51,15,53,16,55,17,57,18,59,19,61,20,63,21,65,22,67,23,69,24,71,25,73,26,75,27,77,28,79,29,81,30,83,31,85,32,87,33,89,34,91,35,93,36,95,37,97,38,99,39,101,40,103,41,105,42}; ++short out1[N], out2[N]; ++ ++__attribute__ ((noinline)) void ++foo () ++{ ++ int i; ++ short c, d; ++ ++ /* Vectorizable with conditional store sinking. */ ++ for (i = 0; i < N; i++) ++ { ++ c = in1[i].b; ++ d = in2[i].b; ++ ++ if (c >= d) ++ { ++ out[i].b = c; ++ out[i].a = d + 5; ++ } ++ else ++ { ++ out[i].b = d - 12; ++ out[i].a = c + d; ++ } ++ } ++ ++ /* Not vectorizable. */ ++ for (i = 0; i < N; i++) ++ { ++ c = in1[i].b; ++ d = in2[i].b; ++ ++ if (c >= d) ++ { ++ out1[i] = c; ++ } ++ else ++ { ++ out2[i] = c + d; ++ } ++ } ++} ++ ++int ++main (void) ++{ ++ int i; ++ ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ { ++ in1[i].a = i; ++ in1[i].b = i + 2; ++ in2[i].a = 5; ++ in2[i].b = i + 5; ++ __asm__ volatile (""); ++ } ++ ++ foo (); ++ ++ for (i = 0; i < N; i++) ++ { ++ if (out[i].a != result[2*i] || out[i].b != result[2*i+1]) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c 2011-03-27 09:38:18 +0000 +@@ -0,0 +1,65 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 50 ++ ++int a[N], b[N], in1[N], in2[N]; ++int result[2*N] = {5,-7,7,-6,9,-5,11,-4,13,-3,15,-2,17,-1,19,0,21,1,23,2,25,3,27,4,29,5,31,6,33,7,35,8,37,9,39,10,41,11,43,12,45,13,47,14,49,15,51,16,53,17,55,18,57,19,59,20,61,21,63,22,65,23,67,24,69,25,71,26,73,27,75,28,77,29,79,30,81,31,83,32,85,33,87,34,89,35,91,36,93,37,95,38,97,39,99,40,101,41,103,42}; ++ ++__attribute__ ((noinline)) void ++foo (int *pa, int *pb) ++{ ++ int i; ++ int c, d; ++ ++ /* Store sinking should not work here since the pointers may alias. */ ++ for (i = 0; i < N; i++) ++ { ++ c = in1[i]; ++ d = in2[i]; ++ ++ if (c >= d) ++ { ++ *pa = c; ++ *pb = d + 5; ++ } ++ else ++ { ++ *pb = d - 12; ++ *pa = c + d; ++ } ++ ++ pa++; ++ pb++; ++ } ++} ++ ++int ++main (void) ++{ ++ int i; ++ ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ { ++ in1[i] = i; ++ in2[i] = i + 5; ++ __asm__ volatile (""); ++ } ++ ++ foo (a, b); ++ ++ for (i = 0; i < N; i++) ++ { ++ if (a[i] != result[2*i] || b[i] != result[2*i+1]) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/tree-data-ref.c' +--- old/gcc/tree-data-ref.c 2011-02-05 01:39:20 +0000 ++++ new/gcc/tree-data-ref.c 2011-03-27 09:38:18 +0000 +@@ -991,6 +991,48 @@ + return dr; + } + ++/* Check if OFFSET1 and OFFSET2 (DR_OFFSETs of some data-refs) are identical ++ expressions. */ ++static bool ++dr_equal_offsets_p1 (tree offset1, tree offset2) ++{ ++ bool res; ++ ++ STRIP_NOPS (offset1); ++ STRIP_NOPS (offset2); ++ ++ if (offset1 == offset2) ++ return true; ++ ++ if (TREE_CODE (offset1) != TREE_CODE (offset2) ++ || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1))) ++ return false; ++ ++ res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 0), ++ TREE_OPERAND (offset2, 0)); ++ ++ if (!res || !BINARY_CLASS_P (offset1)) ++ return res; ++ ++ res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 1), ++ TREE_OPERAND (offset2, 1)); ++ ++ return res; ++} ++ ++/* Check if DRA and DRB have equal offsets. */ ++bool ++dr_equal_offsets_p (struct data_reference *dra, ++ struct data_reference *drb) ++{ ++ tree offset1, offset2; ++ ++ offset1 = DR_OFFSET (dra); ++ offset2 = DR_OFFSET (drb); ++ ++ return dr_equal_offsets_p1 (offset1, offset2); ++} ++ + /* Returns true if FNA == FNB. */ + + static bool +@@ -4294,7 +4336,7 @@ + DATAREFS. Returns chrec_dont_know when failing to analyze a + difficult case, returns NULL_TREE otherwise. */ + +-static tree ++tree + find_data_references_in_bb (struct loop *loop, basic_block bb, + VEC (data_reference_p, heap) **datarefs) + { + +=== modified file 'gcc/tree-data-ref.h' +--- old/gcc/tree-data-ref.h 2011-01-25 21:24:23 +0000 ++++ new/gcc/tree-data-ref.h 2011-03-27 09:38:18 +0000 +@@ -426,10 +426,14 @@ + extern void compute_all_dependences (VEC (data_reference_p, heap) *, + VEC (ddr_p, heap) **, VEC (loop_p, heap) *, + bool); ++extern tree find_data_references_in_bb (struct loop *, basic_block, ++ VEC (data_reference_p, heap) **); + + extern void create_rdg_vertices (struct graph *, VEC (gimple, heap) *); + extern bool dr_may_alias_p (const struct data_reference *, + const struct data_reference *); ++extern bool dr_equal_offsets_p (struct data_reference *, ++ struct data_reference *); + + + /* Return true when the base objects of data references A and B are + +=== modified file 'gcc/tree-ssa-phiopt.c' +--- old/gcc/tree-ssa-phiopt.c 2010-11-03 15:18:50 +0000 ++++ new/gcc/tree-ssa-phiopt.c 2011-03-27 09:38:18 +0000 +@@ -34,6 +34,8 @@ + #include "langhooks.h" + #include "pointer-set.h" + #include "domwalk.h" ++#include "cfgloop.h" ++#include "tree-data-ref.h" + + static unsigned int tree_ssa_phiopt (void); + static unsigned int tree_ssa_phiopt_worker (bool); +@@ -1292,35 +1294,18 @@ + return true; + } + +-/* Do the main work of conditional store replacement. We already know +- that the recognized pattern looks like so: +- +- split: +- if (cond) goto THEN_BB; else goto ELSE_BB (edge E1) +- THEN_BB: +- X = Y; +- goto JOIN_BB; +- ELSE_BB: +- X = Z; +- fallthrough (edge E0) +- JOIN_BB: +- some more +- +- We check that THEN_BB and ELSE_BB contain only one store +- that the stores have a "simple" RHS. */ ++/* Do the main work of conditional store replacement. */ + + static bool +-cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb, +- basic_block join_bb) ++cond_if_else_store_replacement_1 (basic_block then_bb, basic_block else_bb, ++ basic_block join_bb, gimple then_assign, ++ gimple else_assign) + { +- gimple then_assign = last_and_only_stmt (then_bb); +- gimple else_assign = last_and_only_stmt (else_bb); + tree lhs_base, lhs, then_rhs, else_rhs; + source_location then_locus, else_locus; + gimple_stmt_iterator gsi; + gimple newphi, new_stmt; + +- /* Check if then_bb and else_bb contain only one store each. */ + if (then_assign == NULL + || !gimple_assign_single_p (then_assign) + || else_assign == NULL +@@ -1385,6 +1370,190 @@ + return true; + } + ++/* Conditional store replacement. We already know ++ that the recognized pattern looks like so: ++ ++ split: ++ if (cond) goto THEN_BB; else goto ELSE_BB (edge E1) ++ THEN_BB: ++ ... ++ X = Y; ++ ... ++ goto JOIN_BB; ++ ELSE_BB: ++ ... ++ X = Z; ++ ... ++ fallthrough (edge E0) ++ JOIN_BB: ++ some more ++ ++ We check that it is safe to sink the store to JOIN_BB by verifying that ++ there are no read-after-write or write-after-write dependencies in ++ THEN_BB and ELSE_BB. */ ++ ++static bool ++cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb, ++ basic_block join_bb) ++{ ++ gimple then_assign = last_and_only_stmt (then_bb); ++ gimple else_assign = last_and_only_stmt (else_bb); ++ VEC (data_reference_p, heap) *then_datarefs, *else_datarefs; ++ VEC (ddr_p, heap) *then_ddrs, *else_ddrs; ++ gimple then_store, else_store; ++ bool found, ok = false, res; ++ struct data_dependence_relation *ddr; ++ data_reference_p then_dr, else_dr; ++ int i, j; ++ tree then_lhs, else_lhs; ++ VEC (gimple, heap) *then_stores, *else_stores; ++ basic_block blocks[3]; ++ ++ if (MAX_STORES_TO_SINK == 0) ++ return false; ++ ++ /* Handle the case with single statement in THEN_BB and ELSE_BB. */ ++ if (then_assign && else_assign) ++ return cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb, ++ then_assign, else_assign); ++ ++ /* Find data references. */ ++ then_datarefs = VEC_alloc (data_reference_p, heap, 1); ++ else_datarefs = VEC_alloc (data_reference_p, heap, 1); ++ if ((find_data_references_in_bb (NULL, then_bb, &then_datarefs) ++ == chrec_dont_know) ++ || !VEC_length (data_reference_p, then_datarefs) ++ || (find_data_references_in_bb (NULL, else_bb, &else_datarefs) ++ == chrec_dont_know) ++ || !VEC_length (data_reference_p, else_datarefs)) ++ { ++ free_data_refs (then_datarefs); ++ free_data_refs (else_datarefs); ++ return false; ++ } ++ ++ /* Find pairs of stores with equal LHS. */ ++ then_stores = VEC_alloc (gimple, heap, 1); ++ else_stores = VEC_alloc (gimple, heap, 1); ++ FOR_EACH_VEC_ELT (data_reference_p, then_datarefs, i, then_dr) ++ { ++ if (DR_IS_READ (then_dr)) ++ continue; ++ ++ then_store = DR_STMT (then_dr); ++ then_lhs = gimple_assign_lhs (then_store); ++ found = false; ++ ++ FOR_EACH_VEC_ELT (data_reference_p, else_datarefs, j, else_dr) ++ { ++ if (DR_IS_READ (else_dr)) ++ continue; ++ ++ else_store = DR_STMT (else_dr); ++ else_lhs = gimple_assign_lhs (else_store); ++ ++ if (operand_equal_p (then_lhs, else_lhs, 0)) ++ { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) ++ continue; ++ ++ VEC_safe_push (gimple, heap, then_stores, then_store); ++ VEC_safe_push (gimple, heap, else_stores, else_store); ++ } ++ ++ /* No pairs of stores found. */ ++ if (!VEC_length (gimple, then_stores) ++ || VEC_length (gimple, then_stores) > (unsigned) MAX_STORES_TO_SINK) ++ { ++ free_data_refs (then_datarefs); ++ free_data_refs (else_datarefs); ++ VEC_free (gimple, heap, then_stores); ++ VEC_free (gimple, heap, else_stores); ++ return false; ++ } ++ ++ /* Compute and check data dependencies in both basic blocks. */ ++ then_ddrs = VEC_alloc (ddr_p, heap, 1); ++ else_ddrs = VEC_alloc (ddr_p, heap, 1); ++ compute_all_dependences (then_datarefs, &then_ddrs, NULL, false); ++ compute_all_dependences (else_datarefs, &else_ddrs, NULL, false); ++ blocks[0] = then_bb; ++ blocks[1] = else_bb; ++ blocks[2] = join_bb; ++ renumber_gimple_stmt_uids_in_blocks (blocks, 3); ++ ++ /* Check that there are no read-after-write or write-after-write dependencies ++ in THEN_BB. */ ++ FOR_EACH_VEC_ELT (ddr_p, then_ddrs, i, ddr) ++ { ++ struct data_reference *dra = DDR_A (ddr); ++ struct data_reference *drb = DDR_B (ddr); ++ ++ if (DDR_ARE_DEPENDENT (ddr) != chrec_known ++ && ((DR_IS_READ (dra) && DR_IS_WRITE (drb) ++ && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb))) ++ || (DR_IS_READ (drb) && DR_IS_WRITE (dra) ++ && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra))) ++ || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb)))) ++ { ++ free_dependence_relations (then_ddrs); ++ free_dependence_relations (else_ddrs); ++ free_data_refs (then_datarefs); ++ free_data_refs (else_datarefs); ++ VEC_free (gimple, heap, then_stores); ++ VEC_free (gimple, heap, else_stores); ++ return false; ++ } ++ } ++ ++ /* Check that there are no read-after-write or write-after-write dependencies ++ in ELSE_BB. */ ++ FOR_EACH_VEC_ELT (ddr_p, else_ddrs, i, ddr) ++ { ++ struct data_reference *dra = DDR_A (ddr); ++ struct data_reference *drb = DDR_B (ddr); ++ ++ if (DDR_ARE_DEPENDENT (ddr) != chrec_known ++ && ((DR_IS_READ (dra) && DR_IS_WRITE (drb) ++ && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb))) ++ || (DR_IS_READ (drb) && DR_IS_WRITE (dra) ++ && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra))) ++ || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb)))) ++ { ++ free_dependence_relations (then_ddrs); ++ free_dependence_relations (else_ddrs); ++ free_data_refs (then_datarefs); ++ free_data_refs (else_datarefs); ++ VEC_free (gimple, heap, then_stores); ++ VEC_free (gimple, heap, else_stores); ++ return false; ++ } ++ } ++ ++ /* Sink stores with same LHS. */ ++ FOR_EACH_VEC_ELT (gimple, then_stores, i, then_store) ++ { ++ else_store = VEC_index (gimple, else_stores, i); ++ res = cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb, ++ then_store, else_store); ++ ok = ok || res; ++ } ++ ++ free_dependence_relations (then_ddrs); ++ free_dependence_relations (else_ddrs); ++ free_data_refs (then_datarefs); ++ free_data_refs (else_datarefs); ++ VEC_free (gimple, heap, then_stores); ++ VEC_free (gimple, heap, else_stores); ++ ++ return ok; ++} ++ + /* Always do these optimizations if we have SSA + trees to work on. */ + static bool + +=== modified file 'gcc/tree-vect-data-refs.c' +--- old/gcc/tree-vect-data-refs.c 2011-02-25 11:18:14 +0000 ++++ new/gcc/tree-vect-data-refs.c 2011-03-27 09:38:18 +0000 +@@ -289,39 +289,6 @@ + } + } + +- +-/* Function vect_equal_offsets. +- +- Check if OFFSET1 and OFFSET2 are identical expressions. */ +- +-static bool +-vect_equal_offsets (tree offset1, tree offset2) +-{ +- bool res; +- +- STRIP_NOPS (offset1); +- STRIP_NOPS (offset2); +- +- if (offset1 == offset2) +- return true; +- +- if (TREE_CODE (offset1) != TREE_CODE (offset2) +- || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1))) +- return false; +- +- res = vect_equal_offsets (TREE_OPERAND (offset1, 0), +- TREE_OPERAND (offset2, 0)); +- +- if (!res || !BINARY_CLASS_P (offset1)) +- return res; +- +- res = vect_equal_offsets (TREE_OPERAND (offset1, 1), +- TREE_OPERAND (offset2, 1)); +- +- return res; +-} +- +- + /* Check dependence between DRA and DRB for basic block vectorization. + If the accesses share same bases and offsets, we can compare their initial + constant offsets to decide whether they differ or not. In case of a read- +@@ -352,7 +319,7 @@ + || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR + || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0) + != TREE_OPERAND (DR_BASE_ADDRESS (drb),0))) +- || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb))) ++ || !dr_equal_offsets_p (dra, drb)) + return true; + + /* Check the types. */ +@@ -402,7 +369,7 @@ + || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR + || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0) + != TREE_OPERAND (DR_BASE_ADDRESS (drb),0))) +- || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb)) ++ || !dr_equal_offsets_p (dra, drb) + || !tree_int_cst_compare (DR_INIT (dra), DR_INIT (drb)) + || DR_IS_READ (dra) != DR_IS_READ (drb)) + return false; + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch new file mode 100644 index 0000000000..017b1df7e3 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106737.patch @@ -0,0 +1,126 @@ +2011-04-21 Andrew Stubbs + + Backport from FSF: + + 2008-12-03 Daniel Jacobowitz + + gcc/testsuite/ + * gcc.dg/vect/vect-shift-3.c, gcc.dg/vect/vect-shift-4.c: New. + * lib/target-supports.exp (check_effective_target_vect_shift_char): New + function. + +=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 2011-04-21 13:51:06 +0000 +@@ -0,0 +1,37 @@ ++/* { dg-require-effective-target vect_shift } */ ++/* { dg-require-effective-target vect_int } */ ++ ++#include "tree-vect.h" ++ ++#define N 32 ++ ++unsigned short dst[N] __attribute__((aligned(N))); ++unsigned short src[N] __attribute__((aligned(N))); ++ ++__attribute__ ((noinline)) ++void array_shift(void) ++{ ++ int i; ++ for (i = 0; i < N; i++) ++ dst[i] = src[i] >> 3; ++} ++ ++int main() ++{ ++ volatile int i; ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ src[i] = i << 3; ++ ++ array_shift (); ++ ++ for (i = 0; i < N; i++) ++ if (dst[i] != i) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 2011-04-21 13:51:06 +0000 +@@ -0,0 +1,37 @@ ++/* { dg-require-effective-target vect_shift_char } */ ++/* { dg-require-effective-target vect_int } */ ++ ++#include "tree-vect.h" ++ ++#define N 32 ++ ++unsigned char dst[N] __attribute__((aligned(N))); ++unsigned char src[N] __attribute__((aligned(N))); ++ ++__attribute__ ((noinline)) ++void array_shift(void) ++{ ++ int i; ++ for (i = 0; i < N; i++) ++ dst[i] = src[i] >> 3; ++} ++ ++int main() ++{ ++ volatile int i; ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ src[i] = i << 3; ++ ++ array_shift (); ++ ++ for (i = 0; i < N; i++) ++ if (dst[i] != i) ++ abort (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/lib/target-supports.exp' +--- old/gcc/testsuite/lib/target-supports.exp 2011-02-19 15:31:15 +0000 ++++ new/gcc/testsuite/lib/target-supports.exp 2011-04-21 13:51:06 +0000 +@@ -2308,6 +2308,26 @@ + } + + ++# Return 1 if the target supports hardware vector shift operation for char. ++ ++proc check_effective_target_vect_shift_char { } { ++ global et_vect_shift_char_saved ++ ++ if [info exists et_vect_shift_char_saved] { ++ verbose "check_effective_target_vect_shift_char: using cached result" 2 ++ } else { ++ set et_vect_shift_char_saved 0 ++ if { ([istarget powerpc*-*-*] ++ && ![istarget powerpc-*-linux*paired*]) ++ || [check_effective_target_arm32] } { ++ set et_vect_shift_char_saved 1 ++ } ++ } ++ ++ verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2 ++ return $et_vect_shift_char_saved ++} ++ + # Return 1 if the target supports hardware vectors of long, 0 otherwise. + # + # This can change for different subtargets so do not cache the result. + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch new file mode 100644 index 0000000000..3dde3b29a1 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106738.patch @@ -0,0 +1,177 @@ +2011-04-27 Ira Rosen + + Backport from FSF: + + 2011-04-03 Richard Guenther + Ira Rosen + + gcc/ + * tree-if-conv.c (memrefs_read_or_written_unconditionally): Strip all + non-variable offsets and compare the remaining bases of the two + accesses instead of looking for exact same data-ref. + + gcc/testsuite/ + * gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: New test. + * gcc.dg/vect/vect.exp: Run if-cvt-stores-vect* tests with + -ftree-loop-if-convert-stores. + +=== added file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c' +--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-04-24 07:45:49 +0000 +@@ -0,0 +1,69 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 50 ++ ++typedef struct { ++ short a; ++ short b; ++} data; ++ ++data in1[N], in2[N], out[N]; ++short result[N*2] = {10,-7,11,-6,12,-5,13,-4,14,-3,15,-2,16,-1,17,0,18,1,19,2,20,3,21,4,22,5,23,6,24,7,25,8,26,9,27,10,28,11,29,12,30,13,31,14,32,15,33,16,34,17,35,18,36,19,37,20,38,21,39,22,40,23,41,24,42,25,43,26,44,27,45,28,46,29,47,30,48,31,49,32,50,33,51,34,52,35,53,36,54,37,55,38,56,39,57,40,58,41,59,42}; ++short out1[N], out2[N]; ++ ++__attribute__ ((noinline)) void ++foo () ++{ ++ int i; ++ short c, d; ++ ++ for (i = 0; i < N; i++) ++ { ++ c = in1[i].b; ++ d = in2[i].b; ++ ++ if (c >= d) ++ { ++ out[i].b = in1[i].a; ++ out[i].a = d + 5; ++ } ++ else ++ { ++ out[i].b = d - 12; ++ out[i].a = in2[i].a + d; ++ } ++ } ++} ++ ++int ++main (void) ++{ ++ int i; ++ ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ { ++ in1[i].a = i; ++ in1[i].b = i + 2; ++ in2[i].a = 5; ++ in2[i].b = i + 5; ++ __asm__ volatile (""); ++ } ++ ++ foo (); ++ ++ for (i = 0; i < N; i++) ++ { ++ if (out[i].a != result[2*i] || out[i].b != result[2*i+1]) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp' +--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2010-11-22 21:49:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-04-24 07:45:49 +0000 +@@ -210,6 +210,12 @@ + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/ggc-*.\[cS\]]] \ + "" $DEFAULT_VECTCFLAGS + ++# -ftree-loop-if-convert-stores ++set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS ++lappend DEFAULT_VECTCFLAGS "-ftree-loop-if-convert-stores" ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/if-cvt-stores-vect-*.\[cS\]]] \ ++ "" $DEFAULT_VECTCFLAGS ++ + # With -O3. + # Don't allow IPA cloning, because it throws our counts out of whack. + set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS + +=== modified file 'gcc/tree-if-conv.c' +--- old/gcc/tree-if-conv.c 2011-02-23 16:49:52 +0000 ++++ new/gcc/tree-if-conv.c 2011-04-24 07:45:49 +0000 +@@ -464,8 +464,8 @@ + /* Returns true when the memory references of STMT are read or written + unconditionally. In other words, this function returns true when + for every data reference A in STMT there exist other accesses to +- the same data reference with predicates that add up (OR-up) to the +- true predicate: this ensures that the data reference A is touched ++ a data reference with the same base with predicates that add up (OR-up) to ++ the true predicate: this ensures that the data reference A is touched + (read or written) on every iteration of the if-converted loop. */ + + static bool +@@ -489,21 +489,38 @@ + continue; + + for (j = 0; VEC_iterate (data_reference_p, drs, j, b); j++) +- if (DR_STMT (b) != stmt +- && same_data_refs (a, b)) +- { +- tree cb = bb_predicate (gimple_bb (DR_STMT (b))); +- +- if (DR_RW_UNCONDITIONALLY (b) == 1 +- || is_true_predicate (cb) +- || is_true_predicate (ca = fold_or_predicates (EXPR_LOCATION (cb), +- ca, cb))) +- { +- DR_RW_UNCONDITIONALLY (a) = 1; +- DR_RW_UNCONDITIONALLY (b) = 1; +- found = true; +- break; +- } ++ { ++ tree ref_base_a = DR_REF (a); ++ tree ref_base_b = DR_REF (b); ++ ++ if (DR_STMT (b) == stmt) ++ continue; ++ ++ while (TREE_CODE (ref_base_a) == COMPONENT_REF ++ || TREE_CODE (ref_base_a) == IMAGPART_EXPR ++ || TREE_CODE (ref_base_a) == REALPART_EXPR) ++ ref_base_a = TREE_OPERAND (ref_base_a, 0); ++ ++ while (TREE_CODE (ref_base_b) == COMPONENT_REF ++ || TREE_CODE (ref_base_b) == IMAGPART_EXPR ++ || TREE_CODE (ref_base_b) == REALPART_EXPR) ++ ref_base_b = TREE_OPERAND (ref_base_b, 0); ++ ++ if (!operand_equal_p (ref_base_a, ref_base_b, 0)) ++ { ++ tree cb = bb_predicate (gimple_bb (DR_STMT (b))); ++ ++ if (DR_RW_UNCONDITIONALLY (b) == 1 ++ || is_true_predicate (cb) ++ || is_true_predicate (ca ++ = fold_or_predicates (EXPR_LOCATION (cb), ca, cb))) ++ { ++ DR_RW_UNCONDITIONALLY (a) = 1; ++ DR_RW_UNCONDITIONALLY (b) = 1; ++ found = true; ++ break; ++ } ++ } + } + + if (!found) + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch new file mode 100644 index 0000000000..2c14ceb8cb --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106739.patch @@ -0,0 +1,140 @@ +2011-05-02 Ira Rosen + + Backport from FSF: + + 2011-03-27 Ira Rosen + + gcc/ + * config/arm/arm.c (arm_autovectorize_vector_sizes): New function. + (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define. + + gcc/testsuite/ + * gcc.dg/vect/vect-outer-5.c: Reduce the distance between data + accesses to preserve the meaning of the test for doubleword vectors. + * gcc.dg/vect/no-vfa-pr29145.c: Likewise. + * gcc.dg/vect/slp-3.c: Reduce the loop bound for the same reason. + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2011-03-02 11:38:43 +0000 ++++ new/gcc/config/arm/arm.c 2011-04-28 11:46:58 +0000 +@@ -250,6 +250,7 @@ + bool is_packed); + static void arm_conditional_register_usage (void); + static reg_class_t arm_preferred_rename_class (reg_class_t rclass); ++static unsigned int arm_autovectorize_vector_sizes (void); + + + /* Table of machine attributes. */ +@@ -395,6 +396,9 @@ + #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p + #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE + #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode ++#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES ++#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \ ++ arm_autovectorize_vector_sizes + + #undef TARGET_MACHINE_DEPENDENT_REORG + #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg +@@ -23511,6 +23515,12 @@ + } + } + ++static unsigned int ++arm_autovectorize_vector_sizes (void) ++{ ++ return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0; ++} ++ + static bool + arm_vector_alignment_reachable (const_tree type, bool is_packed) + { + +=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c' +--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2010-10-04 14:59:30 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2011-04-28 11:46:58 +0000 +@@ -8,7 +8,7 @@ + void with_restrict(int * __restrict p) + { + int i; +- int *q = p - 2; ++ int *q = p - 1; + + for (i = 0; i < 1000; ++i) { + p[i] = q[i]; +@@ -19,7 +19,7 @@ + void without_restrict(int * p) + { + int i; +- int *q = p - 2; ++ int *q = p - 1; + + for (i = 0; i < 1000; ++i) { + p[i] = q[i]; +@@ -38,8 +38,8 @@ + a[i] = b[i] = i; + } + +- with_restrict(a + 2); +- without_restrict(b + 2); ++ with_restrict(a + 1); ++ without_restrict(b + 1); + + for (i = 0; i < 1002; ++i) { + if (a[i] != b[i]) + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-3.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-3.c 2011-04-28 11:46:58 +0000 +@@ -4,9 +4,9 @@ + #include + #include "tree-vect.h" + +-#define N 8 ++#define N 12 + +-unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31}; + + int + main1 () +@@ -101,7 +101,7 @@ + } + + /* SLP with unrolling by 8. */ +- for (i = 0; i < N/2; i++) ++ for (i = 0; i < N/4; i++) + { + out[i*9] = in[i*9]; + out[i*9 + 1] = in[i*9 + 1]; +@@ -115,7 +115,7 @@ + } + + /* check results: */ +- for (i = 0; i < N/2; i++) ++ for (i = 0; i < N/4; i++) + { + if (out[i*9] != in[i*9] + || out[i*9 + 1] != in[i*9 + 1] + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2011-04-28 11:46:58 +0000 +@@ -17,7 +17,7 @@ + float B[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + float C[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + float D[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); +- float E[4] = {0,1,2,480}; ++ float E[4] = {0,480,960,1440}; + float s; + + int i, j; +@@ -55,7 +55,7 @@ + s = 0; + for (j=0; j + + Backport from mainline: + + 2011-03-29 Richard Sandiford + + PR debug/48190 + * dwarf2out.c (dw_loc_list_node): Add resolved_addr and replaced. + (cached_dw_loc_list_def): New structure. + (cached_dw_loc_list): New typedef. + (cached_dw_loc_list_table): New variable. + (cached_dw_loc_list_table_hash): New function. + (cached_dw_loc_list_table_eq): Likewise. + (add_location_or_const_value_attribute): Take a bool cache_p. + Cache the list when the parameter is true. + (gen_formal_parameter_die): Update caller. + (gen_variable_die): Likewise. + (dwarf2out_finish): Likewise. + (dwarf2out_abstract_function): Nullify cached_dw_loc_list_table + while generating debug info for the decl. + (dwarf2out_function_decl): Clear cached_dw_loc_list_table. + (dwarf2out_init): Initialize cached_dw_loc_list_table. + (resolve_addr): Cache the result of resolving a chain of + location lists. + +=== modified file 'gcc/dwarf2out.c' +--- old/gcc/dwarf2out.c 2011-03-29 22:47:59 +0000 ++++ new/gcc/dwarf2out.c 2011-05-04 13:20:12 +0000 +@@ -4427,6 +4427,11 @@ + const char *section; /* Section this loclist is relative to */ + dw_loc_descr_ref expr; + hashval_t hash; ++ /* True if all addresses in this and subsequent lists are known to be ++ resolved. */ ++ bool resolved_addr; ++ /* True if this list has been replaced by dw_loc_next. */ ++ bool replaced; + bool emitted; + } dw_loc_list_node; + +@@ -6087,6 +6092,19 @@ + /* Table of decl location linked lists. */ + static GTY ((param_is (var_loc_list))) htab_t decl_loc_table; + ++/* A cached location list. */ ++struct GTY (()) cached_dw_loc_list_def { ++ /* The DECL_UID of the decl that this entry describes. */ ++ unsigned int decl_id; ++ ++ /* The cached location list. */ ++ dw_loc_list_ref loc_list; ++}; ++typedef struct cached_dw_loc_list_def cached_dw_loc_list; ++ ++/* Table of cached location lists. */ ++static GTY ((param_is (cached_dw_loc_list))) htab_t cached_dw_loc_list_table; ++ + /* A pointer to the base of a list of references to DIE's that + are uniquely identified by their tag, presence/absence of + children DIE's, and list of attribute/value pairs. */ +@@ -6434,7 +6452,7 @@ + static void insert_double (double_int, unsigned char *); + static void insert_float (const_rtx, unsigned char *); + static rtx rtl_for_decl_location (tree); +-static bool add_location_or_const_value_attribute (dw_die_ref, tree, ++static bool add_location_or_const_value_attribute (dw_die_ref, tree, bool, + enum dwarf_attribute); + static bool tree_add_const_value_attribute (dw_die_ref, tree); + static bool tree_add_const_value_attribute_for_decl (dw_die_ref, tree); +@@ -8168,6 +8186,24 @@ + htab_find_with_hash (decl_loc_table, decl, DECL_UID (decl)); + } + ++/* Returns a hash value for X (which really is a cached_dw_loc_list_list). */ ++ ++static hashval_t ++cached_dw_loc_list_table_hash (const void *x) ++{ ++ return (hashval_t) ((const cached_dw_loc_list *) x)->decl_id; ++} ++ ++/* Return nonzero if decl_id of cached_dw_loc_list X is the same as ++ UID of decl *Y. */ ++ ++static int ++cached_dw_loc_list_table_eq (const void *x, const void *y) ++{ ++ return (((const cached_dw_loc_list *) x)->decl_id ++ == DECL_UID ((const_tree) y)); ++} ++ + /* Equate a DIE to a particular declaration. */ + + static void +@@ -16965,15 +17001,22 @@ + these things can crop up in other ways also.) Note that one type of + constant value which can be passed into an inlined function is a constant + pointer. This can happen for example if an actual argument in an inlined +- function call evaluates to a compile-time constant address. */ ++ function call evaluates to a compile-time constant address. ++ ++ CACHE_P is true if it is worth caching the location list for DECL, ++ so that future calls can reuse it rather than regenerate it from scratch. ++ This is true for BLOCK_NONLOCALIZED_VARS in inlined subroutines, ++ since we will need to refer to them each time the function is inlined. */ + + static bool +-add_location_or_const_value_attribute (dw_die_ref die, tree decl, ++add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p, + enum dwarf_attribute attr) + { + rtx rtl; + dw_loc_list_ref list; + var_loc_list *loc_list; ++ cached_dw_loc_list *cache; ++ void **slot; + + if (TREE_CODE (decl) == ERROR_MARK) + return false; +@@ -17010,7 +17053,33 @@ + && add_const_value_attribute (die, rtl)) + return true; + } +- list = loc_list_from_tree (decl, decl_by_reference_p (decl) ? 0 : 2); ++ /* If this decl is from BLOCK_NONLOCALIZED_VARS, we might need its ++ list several times. See if we've already cached the contents. */ ++ list = NULL; ++ if (loc_list == NULL || cached_dw_loc_list_table == NULL) ++ cache_p = false; ++ if (cache_p) ++ { ++ cache = (cached_dw_loc_list *) ++ htab_find_with_hash (cached_dw_loc_list_table, decl, DECL_UID (decl)); ++ if (cache) ++ list = cache->loc_list; ++ } ++ if (list == NULL) ++ { ++ list = loc_list_from_tree (decl, decl_by_reference_p (decl) ? 0 : 2); ++ /* It is usually worth caching this result if the decl is from ++ BLOCK_NONLOCALIZED_VARS and if the list has at least two elements. */ ++ if (cache_p && list && list->dw_loc_next) ++ { ++ slot = htab_find_slot_with_hash (cached_dw_loc_list_table, decl, ++ DECL_UID (decl), INSERT); ++ cache = ggc_alloc_cleared_cached_dw_loc_list (); ++ cache->decl_id = DECL_UID (decl); ++ cache->loc_list = list; ++ *slot = cache; ++ } ++ } + if (list) + { + add_AT_location_description (die, attr, list); +@@ -18702,7 +18771,7 @@ + equate_decl_number_to_die (node, parm_die); + if (! DECL_ABSTRACT (node_or_origin)) + add_location_or_const_value_attribute (parm_die, node_or_origin, +- DW_AT_location); ++ node == NULL, DW_AT_location); + + break; + +@@ -18887,6 +18956,7 @@ + tree context; + int was_abstract; + htab_t old_decl_loc_table; ++ htab_t old_cached_dw_loc_list_table; + + /* Make sure we have the actual abstract inline, not a clone. */ + decl = DECL_ORIGIN (decl); +@@ -18901,6 +18971,8 @@ + get locations in abstract instantces. */ + old_decl_loc_table = decl_loc_table; + decl_loc_table = NULL; ++ old_cached_dw_loc_list_table = cached_dw_loc_list_table; ++ cached_dw_loc_list_table = NULL; + + /* Be sure we've emitted the in-class declaration DIE (if any) first, so + we don't get confused by DECL_ABSTRACT. */ +@@ -18925,6 +18997,7 @@ + + current_function_decl = save_fn; + decl_loc_table = old_decl_loc_table; ++ cached_dw_loc_list_table = old_cached_dw_loc_list_table; + pop_cfun (); + } + +@@ -19709,9 +19782,8 @@ + && !TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl_or_origin))) + defer_location (decl_or_origin, var_die); + else +- add_location_or_const_value_attribute (var_die, +- decl_or_origin, +- DW_AT_location); ++ add_location_or_const_value_attribute (var_die, decl_or_origin, ++ decl == NULL, DW_AT_location); + add_pubname (decl_or_origin, var_die); + } + else +@@ -21498,6 +21570,7 @@ + dwarf2out_decl (decl); + + htab_empty (decl_loc_table); ++ htab_empty (cached_dw_loc_list_table); + } + + /* Output a marker (i.e. a label) for the beginning of the generated code for +@@ -22230,6 +22303,11 @@ + decl_loc_table = htab_create_ggc (10, decl_loc_table_hash, + decl_loc_table_eq, NULL); + ++ /* Allocate the cached_dw_loc_list_table. */ ++ cached_dw_loc_list_table ++ = htab_create_ggc (10, cached_dw_loc_list_table_hash, ++ cached_dw_loc_list_table_eq, NULL); ++ + /* Allocate the initial hunk of the decl_scope_table. */ + decl_scope_table = VEC_alloc (tree, gc, 256); + +@@ -22870,30 +22948,53 @@ + { + dw_die_ref c; + dw_attr_ref a; +- dw_loc_list_ref *curr; ++ dw_loc_list_ref *curr, *start, loc; + unsigned ix; + + FOR_EACH_VEC_ELT (dw_attr_node, die->die_attr, ix, a) + switch (AT_class (a)) + { + case dw_val_class_loc_list: +- curr = AT_loc_list_ptr (a); +- while (*curr) ++ start = curr = AT_loc_list_ptr (a); ++ loc = *curr; ++ gcc_assert (loc); ++ /* The same list can be referenced more than once. See if we have ++ already recorded the result from a previous pass. */ ++ if (loc->replaced) ++ *curr = loc->dw_loc_next; ++ else if (!loc->resolved_addr) + { +- if (!resolve_addr_in_expr ((*curr)->expr)) ++ /* As things stand, we do not expect or allow one die to ++ reference a suffix of another die's location list chain. ++ References must be identical or completely separate. ++ There is therefore no need to cache the result of this ++ pass on any list other than the first; doing so ++ would lead to unnecessary writes. */ ++ while (*curr) + { +- dw_loc_list_ref next = (*curr)->dw_loc_next; +- if (next && (*curr)->ll_symbol) ++ gcc_assert (!(*curr)->replaced && !(*curr)->resolved_addr); ++ if (!resolve_addr_in_expr ((*curr)->expr)) + { +- gcc_assert (!next->ll_symbol); +- next->ll_symbol = (*curr)->ll_symbol; ++ dw_loc_list_ref next = (*curr)->dw_loc_next; ++ if (next && (*curr)->ll_symbol) ++ { ++ gcc_assert (!next->ll_symbol); ++ next->ll_symbol = (*curr)->ll_symbol; ++ } ++ *curr = next; + } +- *curr = next; ++ else ++ curr = &(*curr)->dw_loc_next; + } ++ if (loc == *start) ++ loc->resolved_addr = 1; + else +- curr = &(*curr)->dw_loc_next; ++ { ++ loc->replaced = 1; ++ loc->dw_loc_next = *start; ++ } + } +- if (!AT_loc_list (a)) ++ if (!*start) + { + remove_AT (die, a->dw_attr); + ix--; +@@ -23322,6 +23423,7 @@ + add_location_or_const_value_attribute ( + VEC_index (deferred_locations, deferred_locations_list, i)->die, + VEC_index (deferred_locations, deferred_locations_list, i)->variable, ++ false, + DW_AT_location); + } + + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch new file mode 100644 index 0000000000..84f6f64989 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106741.patch @@ -0,0 +1,254 @@ +2011-04-26 Andrew Stubbs + + Backport from FSF: + + 2011-04-15 Maxim Kuvyrkov + + gcc/ + * combine.c (subst, combine_simlify_rtx): Add new argument, use it + to track processing of conditionals. Update all callers. + (try_combine, simplify_if_then_else): Update. + + 2011-04-25 Maxim Kuvyrkov + Eric Botcazou + + gcc/ + * combine.c (combine_simplify_rtx): Avoid mis-simplifying conditionals + for STORE_FLAG_VALUE==-1 case. + +=== modified file 'gcc/combine.c' +--- old/gcc/combine.c 2011-02-15 19:46:26 +0000 ++++ new/gcc/combine.c 2011-04-26 17:03:58 +0000 +@@ -391,8 +391,8 @@ + static void undo_all (void); + static void undo_commit (void); + static rtx *find_split_point (rtx *, rtx, bool); +-static rtx subst (rtx, rtx, rtx, int, int); +-static rtx combine_simplify_rtx (rtx, enum machine_mode, int); ++static rtx subst (rtx, rtx, rtx, int, int, int); ++static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int); + static rtx simplify_if_then_else (rtx); + static rtx simplify_set (rtx); + static rtx simplify_logical (rtx); +@@ -3086,12 +3086,12 @@ + if (i1) + { + subst_low_luid = DF_INSN_LUID (i1); +- i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); ++ i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); + } + else + { + subst_low_luid = DF_INSN_LUID (i2); +- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); ++ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); + } + } + +@@ -3103,7 +3103,7 @@ + self-referential RTL when we will be substituting I1SRC for I1DEST + later. Likewise if I0 feeds into I2, either directly or indirectly + through I1, and I0DEST is in I0SRC. */ +- newpat = subst (PATTERN (i3), i2dest, i2src, 0, ++ newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0, + (i1_feeds_i2_n && i1dest_in_i1src) + || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) + && i0dest_in_i0src)); +@@ -3142,7 +3142,7 @@ + copy of I1SRC each time we substitute it, in order to avoid creating + self-referential RTL when we will be substituting I0SRC for I0DEST + later. */ +- newpat = subst (newpat, i1dest, i1src, 0, ++ newpat = subst (newpat, i1dest, i1src, 0, 0, + i0_feeds_i1_n && i0dest_in_i0src); + substed_i1 = 1; + +@@ -3172,7 +3172,7 @@ + + n_occurrences = 0; + subst_low_luid = DF_INSN_LUID (i0); +- newpat = subst (newpat, i0dest, i0src, 0, 0); ++ newpat = subst (newpat, i0dest, i0src, 0, 0, 0); + substed_i0 = 1; + } + +@@ -3234,7 +3234,7 @@ + { + rtx t = i1pat; + if (i0_feeds_i1_n) +- t = subst (t, i0dest, i0src, 0, 0); ++ t = subst (t, i0dest, i0src, 0, 0, 0); + + XVECEXP (newpat, 0, --total_sets) = t; + } +@@ -3242,10 +3242,10 @@ + { + rtx t = i2pat; + if (i1_feeds_i2_n) +- t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, ++ t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0, + i0_feeds_i1_n && i0dest_in_i0src); + if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n) +- t = subst (t, i0dest, i0src, 0, 0); ++ t = subst (t, i0dest, i0src, 0, 0, 0); + + XVECEXP (newpat, 0, --total_sets) = t; + } +@@ -4914,11 +4914,13 @@ + + IN_DEST is nonzero if we are processing the SET_DEST of a SET. + ++ IN_COND is nonzero if we are on top level of the condition. ++ + UNIQUE_COPY is nonzero if each substitution must be unique. We do this + by copying if `n_occurrences' is nonzero. */ + + static rtx +-subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy) ++subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy) + { + enum rtx_code code = GET_CODE (x); + enum machine_mode op0_mode = VOIDmode; +@@ -4979,7 +4981,7 @@ + && GET_CODE (XVECEXP (x, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) + { +- new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); ++ new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy); + + /* If this substitution failed, this whole thing fails. */ + if (GET_CODE (new_rtx) == CLOBBER +@@ -4996,7 +4998,7 @@ + && GET_CODE (dest) != CC0 + && GET_CODE (dest) != PC) + { +- new_rtx = subst (dest, from, to, 0, unique_copy); ++ new_rtx = subst (dest, from, to, 0, 0, unique_copy); + + /* If this substitution failed, this whole thing fails. */ + if (GET_CODE (new_rtx) == CLOBBER +@@ -5042,8 +5044,8 @@ + } + else + { +- new_rtx = subst (XVECEXP (x, i, j), from, to, 0, +- unique_copy); ++ new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0, ++ unique_copy); + + /* If this substitution failed, this whole thing + fails. */ +@@ -5120,7 +5122,9 @@ + && (code == SUBREG || code == STRICT_LOW_PART + || code == ZERO_EXTRACT)) + || code == SET) +- && i == 0), unique_copy); ++ && i == 0), ++ code == IF_THEN_ELSE && i == 0, ++ unique_copy); + + /* If we found that we will have to reject this combination, + indicate that by returning the CLOBBER ourselves, rather than +@@ -5177,7 +5181,7 @@ + /* If X is sufficiently simple, don't bother trying to do anything + with it. */ + if (code != CONST_INT && code != REG && code != CLOBBER) +- x = combine_simplify_rtx (x, op0_mode, in_dest); ++ x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond); + + if (GET_CODE (x) == code) + break; +@@ -5197,10 +5201,12 @@ + expression. + + OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero +- if we are inside a SET_DEST. */ ++ if we are inside a SET_DEST. IN_COND is nonzero if we are on the top level ++ of a condition. */ + + static rtx +-combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest) ++combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest, ++ int in_cond) + { + enum rtx_code code = GET_CODE (x); + enum machine_mode mode = GET_MODE (x); +@@ -5255,8 +5261,8 @@ + false arms to store-flag values. Be careful to use copy_rtx + here since true_rtx or false_rtx might share RTL with x as a + result of the if_then_else_cond call above. */ +- true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0); +- false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0); ++ true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0); ++ false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0); + + /* If true_rtx and false_rtx are not general_operands, an if_then_else + is unlikely to be simpler. */ +@@ -5600,7 +5606,7 @@ + { + /* Try to simplify the expression further. */ + rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); +- temp = combine_simplify_rtx (tor, mode, in_dest); ++ temp = combine_simplify_rtx (tor, mode, in_dest, 0); + + /* If we could, great. If not, do not go ahead with the IOR + replacement, since PLUS appears in many special purpose +@@ -5693,7 +5699,16 @@ + ZERO_EXTRACT is indeed appropriate, it will be placed back by + the call to make_compound_operation in the SET case. */ + +- if (STORE_FLAG_VALUE == 1 ++ if (in_cond) ++ /* Don't apply below optimizations if the caller would ++ prefer a comparison rather than a value. ++ E.g., for the condition in an IF_THEN_ELSE most targets need ++ an explicit comparison. */ ++ { ++ ; ++ } ++ ++ else if (STORE_FLAG_VALUE == 1 + && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT + && op1 == const0_rtx + && mode == GET_MODE (op0) +@@ -5739,7 +5754,10 @@ + + /* If STORE_FLAG_VALUE is -1, we have cases similar to + those above. */ +- if (STORE_FLAG_VALUE == -1 ++ if (in_cond) ++ ; ++ ++ else if (STORE_FLAG_VALUE == -1 + && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT + && op1 == const0_rtx + && (num_sign_bit_copies (op0, mode) +@@ -5937,11 +5955,11 @@ + if (reg_mentioned_p (from, true_rtx)) + true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, + from, true_val), +- pc_rtx, pc_rtx, 0, 0); ++ pc_rtx, pc_rtx, 0, 0, 0); + if (reg_mentioned_p (from, false_rtx)) + false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, + from, false_val), +- pc_rtx, pc_rtx, 0, 0); ++ pc_rtx, pc_rtx, 0, 0, 0); + + SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); + SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); +@@ -6158,11 +6176,11 @@ + { + temp = subst (simplify_gen_relational (true_code, m, VOIDmode, + cond_op0, cond_op1), +- pc_rtx, pc_rtx, 0, 0); ++ pc_rtx, pc_rtx, 0, 0, 0); + temp = simplify_gen_binary (MULT, m, temp, + simplify_gen_binary (MULT, m, c1, + const_true_rtx)); +- temp = subst (temp, pc_rtx, pc_rtx, 0, 0); ++ temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0); + temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); + + if (extend_op != UNKNOWN) + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch new file mode 100644 index 0000000000..d14f06c3ff --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106742.patch @@ -0,0 +1,6123 @@ +2011-05-03 Richard Sandiford + + gcc/testsuite/ + From Richard Earnshaw + + PR target/46329 + * gcc.target/arm/pr46329.c: New test. + + gcc/ + PR target/46329 + * config/arm/arm.c (arm_legitimate_constant_p_1): Return false + for all Neon struct constants. + +2011-05-03 Richard Sandiford + + gcc/ + * targhooks.h (default_legitimate_constant_p); Declare. + * targhooks.c (default_legitimate_constant_p): New function. + + Backport from mainline: + 2011-04-21 Richard Sandiford + + * target.def (legitimate_constant_p): New hook. + * doc/tm.texi.in (LEGITIMATE_CONSTANT_P): Replace with... + (TARGET_LEGITIMATE_CONSTANT_P): ...this. + * doc/tm.texi: Regenerate. + * calls.c (precompute_register_parameters): Replace uses of + LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p. + (emit_library_call_value_1): Likewise. + * expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn) + (compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise. + * recog.c (general_operand, immediate_operand): Likewise. + * reload.c (find_reloads_toplev, find_reloads_address_part): Likewise. + * reload1.c (init_eliminable_invariants): Likewise. + + * config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete. + * config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise. + (THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise. + * config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define. + (arm_legitimate_constant_p_1, thumb_legitimate_constant_p) + (arm_legitimate_constant_p): New functions. + (arm_cannot_force_const_mem): Make static. + +2011-05-03 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-05-03 Richard Sandiford + + * hooks.h (hook_bool_mode_uhwi_false): Declare. + * hooks.c (hook_bool_mode_uhwi_false): New function. + * target.def (array_mode_supported_p): New hook. + * doc/tm.texi.in (TARGET_ARRAY_MODE_SUPPORTED_P): Add @hook. + * doc/tm.texi: Regenerate. + * stor-layout.c (mode_for_array): New function. + (layout_type): Use it. + * config/arm/arm.c (arm_array_mode_supported_p): New function. + (TARGET_ARRAY_MODE_SUPPORTED_P): Define. + +2011-05-03 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-04-12 Richard Sandiford + + * config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the + size of a '%A' memory reference. + (T_DREG, T_QREG): New neon_builtin_type_bits. + (arm_init_neon_builtins): Assert that the load and store operands + are neon_struct_operands. + (locate_neon_builtin_icode): Provide the neon_builtin_type_bits. + (NEON_ARG_MEMORY): New builtin_arg. + (neon_dereference_pointer): New function. + (arm_expand_neon_args): Add a neon_builtin_type_bits argument. + Handle NEON_ARG_MEMORY. + (arm_expand_neon_builtin): Update after above interface changes. + Use NEON_ARG_MEMORY for loads and stores. + * config/arm/predicates.md (neon_struct_operand): New predicate. + * config/arm/iterators.md (V_two_elem): Tweak formatting. + (V_three_elem): Use BLKmode for accesses that have no associated mode. + (V_four_elem): Tweak formatting. + * config/arm/neon.md (neon_vld1, neon_vld1_dup) + (neon_vst1_lane, neon_vst1, neon_vld2) + (neon_vld2_lane, neon_vld2_dup, neon_vst2) + (neon_vst2_lane, neon_vld3, neon_vld3_lane) + (neon_vld3_dup, neon_vst3, neon_vst3_lane) + (neon_vld4, neon_vld4_lane, neon_vld4_dup) + (neon_vst4): Replace pointer operand with a memory operand. + Use %A in the output template. + (neon_vld3qa, neon_vld3qb, neon_vst3qa) + (neon_vst3qb, neon_vld4qa, neon_vld4qb) + (neon_vst4qa, neon_vst4qb): Likewise, but halve + the width of the memory access. Remove post-increment. + * config/arm/neon-testgen.ml: Allow addresses to have an alignment. + + gcc/testsuite/ + Backport from mainline: + + 2011-04-12 Richard Sandiford + + * gcc.target/arm/neon-vld3-1.c: New test. + * gcc.target/arm/neon-vst3-1.c: New test. + * gcc.target/arm/neon/v*.c: Regenerate. + +2011-05-03 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-03-30 Richard Sandiford + Ramana Radhakrishnan + + PR target/43590 + * config/arm/neon.md (neon_vld3qa, neon_vld4qa): Remove + operand 1 and reshuffle the operands to match. + (neon_vld3, neon_vld4): Update accordingly. + +=== modified file 'gcc/calls.c' +--- old/gcc/calls.c 2011-03-03 21:56:58 +0000 ++++ new/gcc/calls.c 2011-05-03 15:17:25 +0000 +@@ -684,7 +684,7 @@ + /* If the value is a non-legitimate constant, force it into a + pseudo now. TLS symbols sometimes need a call to resolve. */ + if (CONSTANT_P (args[i].value) +- && !LEGITIMATE_CONSTANT_P (args[i].value)) ++ && !targetm.legitimate_constant_p (args[i].mode, args[i].value)) + args[i].value = force_reg (args[i].mode, args[i].value); + + /* If we are to promote the function arg to a wider mode, +@@ -3447,7 +3447,8 @@ + + /* Make sure it is a reasonable operand for a move or push insn. */ + if (!REG_P (addr) && !MEM_P (addr) +- && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr))) ++ && !(CONSTANT_P (addr) ++ && targetm.legitimate_constant_p (Pmode, addr))) + addr = force_operand (addr, NULL_RTX); + + argvec[count].value = addr; +@@ -3488,7 +3489,7 @@ + + /* Make sure it is a reasonable operand for a move or push insn. */ + if (!REG_P (val) && !MEM_P (val) +- && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val))) ++ && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val))) + val = force_operand (val, NULL_RTX); + + if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1)) + +=== modified file 'gcc/config/arm/arm-protos.h' +--- old/gcc/config/arm/arm-protos.h 2011-01-29 03:20:57 +0000 ++++ new/gcc/config/arm/arm-protos.h 2011-05-03 15:17:25 +0000 +@@ -81,7 +81,6 @@ + extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx, + bool); + extern bool arm_tls_referenced_p (rtx); +-extern bool arm_cannot_force_const_mem (rtx); + + extern int cirrus_memory_offset (rtx); + extern int arm_coproc_mem_operand (rtx, bool); + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2011-04-28 11:46:58 +0000 ++++ new/gcc/config/arm/arm.c 2011-05-03 15:18:07 +0000 +@@ -143,6 +143,8 @@ + static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, + tree); + static bool arm_have_conditional_execution (void); ++static bool arm_cannot_force_const_mem (rtx); ++static bool arm_legitimate_constant_p (enum machine_mode, rtx); + static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); + static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); + static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); +@@ -241,6 +243,8 @@ + static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *); + static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *); + static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *); ++static bool arm_array_mode_supported_p (enum machine_mode, ++ unsigned HOST_WIDE_INT); + static enum machine_mode arm_preferred_simd_mode (enum machine_mode); + static bool arm_class_likely_spilled_p (reg_class_t); + static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); +@@ -394,6 +398,8 @@ + #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask + #undef TARGET_VECTOR_MODE_SUPPORTED_P + #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p ++#undef TARGET_ARRAY_MODE_SUPPORTED_P ++#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p + #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE + #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode + #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES +@@ -523,6 +529,9 @@ + #undef TARGET_HAVE_CONDITIONAL_EXECUTION + #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution + ++#undef TARGET_LEGITIMATE_CONSTANT_P ++#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p ++ + #undef TARGET_CANNOT_FORCE_CONST_MEM + #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem + +@@ -6539,9 +6548,47 @@ + return for_each_rtx (&x, arm_tls_operand_p_1, NULL); + } + ++/* Implement TARGET_LEGITIMATE_CONSTANT_P. ++ ++ On the ARM, allow any integer (invalid ones are removed later by insn ++ patterns), nice doubles and symbol_refs which refer to the function's ++ constant pool XXX. ++ ++ When generating pic allow anything. */ ++ ++static bool ++arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x) ++{ ++ /* At present, we have no support for Neon structure constants, so forbid ++ them here. It might be possible to handle simple cases like 0 and -1 ++ in future. */ ++ if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)) ++ return false; ++ ++ return flag_pic || !label_mentioned_p (x); ++} ++ ++static bool ++thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) ++{ ++ return (GET_CODE (x) == CONST_INT ++ || GET_CODE (x) == CONST_DOUBLE ++ || CONSTANT_ADDRESS_P (x) ++ || flag_pic); ++} ++ ++static bool ++arm_legitimate_constant_p (enum machine_mode mode, rtx x) ++{ ++ return (!arm_cannot_force_const_mem (x) ++ && (TARGET_32BIT ++ ? arm_legitimate_constant_p_1 (mode, x) ++ : thumb_legitimate_constant_p (mode, x))); ++} ++ + /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ + +-bool ++static bool + arm_cannot_force_const_mem (rtx x) + { + rtx base, offset; +@@ -16598,7 +16645,7 @@ + { + rtx addr; + bool postinc = FALSE; +- unsigned align, modesize, align_bits; ++ unsigned align, memsize, align_bits; + + gcc_assert (GET_CODE (x) == MEM); + addr = XEXP (x, 0); +@@ -16613,12 +16660,12 @@ + instruction (for some alignments) as an aid to the memory subsystem + of the target. */ + align = MEM_ALIGN (x) >> 3; +- modesize = GET_MODE_SIZE (GET_MODE (x)); ++ memsize = INTVAL (MEM_SIZE (x)); + + /* Only certain alignment specifiers are supported by the hardware. */ +- if (modesize == 16 && (align % 32) == 0) ++ if (memsize == 16 && (align % 32) == 0) + align_bits = 256; +- else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) ++ else if ((memsize == 8 || memsize == 16) && (align % 16) == 0) + align_bits = 128; + else if ((align % 8) == 0) + align_bits = 64; +@@ -18278,12 +18325,14 @@ + T_V2SI = 0x0004, + T_V2SF = 0x0008, + T_DI = 0x0010, ++ T_DREG = 0x001F, + T_V16QI = 0x0020, + T_V8HI = 0x0040, + T_V4SI = 0x0080, + T_V4SF = 0x0100, + T_V2DI = 0x0200, + T_TI = 0x0400, ++ T_QREG = 0x07E0, + T_EI = 0x0800, + T_OI = 0x1000 + }; +@@ -18929,10 +18978,9 @@ + if (is_load && k == 1) + { + /* Neon load patterns always have the memory operand +- (a SImode pointer) in the operand 1 position. We +- want a const pointer to the element type in that +- position. */ +- gcc_assert (insn_data[icode].operand[k].mode == SImode); ++ in the operand 1 position. */ ++ gcc_assert (insn_data[icode].operand[k].predicate ++ == neon_struct_operand); + + switch (1 << j) + { +@@ -18967,10 +19015,9 @@ + else if (is_store && k == 0) + { + /* Similarly, Neon store patterns use operand 0 as +- the memory location to store to (a SImode pointer). +- Use a pointer to the element type of the store in +- that position. */ +- gcc_assert (insn_data[icode].operand[k].mode == SImode); ++ the memory location to store to. */ ++ gcc_assert (insn_data[icode].operand[k].predicate ++ == neon_struct_operand); + + switch (1 << j) + { +@@ -19290,12 +19337,13 @@ + } + + static enum insn_code +-locate_neon_builtin_icode (int fcode, neon_itype *itype) ++locate_neon_builtin_icode (int fcode, neon_itype *itype, ++ enum neon_builtin_type_bits *type_bit) + { + neon_builtin_datum key + = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 }; + neon_builtin_datum *found; +- int idx; ++ int idx, type, ntypes; + + key.base_fcode = fcode; + found = (neon_builtin_datum *) +@@ -19308,20 +19356,84 @@ + if (itype) + *itype = found->itype; + ++ if (type_bit) ++ { ++ ntypes = 0; ++ for (type = 0; type < T_MAX; type++) ++ if (found->bits & (1 << type)) ++ { ++ if (ntypes == idx) ++ break; ++ ntypes++; ++ } ++ gcc_assert (type < T_MAX); ++ *type_bit = (enum neon_builtin_type_bits) (1 << type); ++ } + return found->codes[idx]; + } + + typedef enum { + NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, ++ NEON_ARG_MEMORY, + NEON_ARG_STOP + } builtin_arg; + + #define NEON_MAX_BUILTIN_ARGS 5 + ++/* EXP is a pointer argument to a Neon load or store intrinsic. Derive ++ and return an expression for the accessed memory. ++ ++ The intrinsic function operates on a block of registers that has ++ mode REG_MODE. This block contains vectors of type TYPE_BIT. ++ The function references the memory at EXP in mode MEM_MODE; ++ this mode may be BLKmode if no more suitable mode is available. */ ++ ++static tree ++neon_dereference_pointer (tree exp, enum machine_mode mem_mode, ++ enum machine_mode reg_mode, ++ enum neon_builtin_type_bits type_bit) ++{ ++ HOST_WIDE_INT reg_size, vector_size, nvectors, nelems; ++ tree elem_type, upper_bound, array_type; ++ ++ /* Work out the size of the register block in bytes. */ ++ reg_size = GET_MODE_SIZE (reg_mode); ++ ++ /* Work out the size of each vector in bytes. */ ++ gcc_assert (type_bit & (T_DREG | T_QREG)); ++ vector_size = (type_bit & T_QREG ? 16 : 8); ++ ++ /* Work out how many vectors there are. */ ++ gcc_assert (reg_size % vector_size == 0); ++ nvectors = reg_size / vector_size; ++ ++ /* Work out how many elements are being loaded or stored. ++ MEM_MODE == REG_MODE implies a one-to-one mapping between register ++ and memory elements; anything else implies a lane load or store. */ ++ if (mem_mode == reg_mode) ++ nelems = vector_size * nvectors; ++ else ++ nelems = nvectors; ++ ++ /* Work out the type of each element. */ ++ gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp))); ++ elem_type = TREE_TYPE (TREE_TYPE (exp)); ++ ++ /* Create a type that describes the full access. */ ++ upper_bound = build_int_cst (size_type_node, nelems - 1); ++ array_type = build_array_type (elem_type, build_index_type (upper_bound)); ++ ++ /* Dereference EXP using that type. */ ++ exp = convert (build_pointer_type (array_type), exp); ++ return fold_build2 (MEM_REF, array_type, exp, ++ build_int_cst (TREE_TYPE (exp), 0)); ++} ++ + /* Expand a Neon builtin. */ + static rtx + arm_expand_neon_args (rtx target, int icode, int have_retval, ++ enum neon_builtin_type_bits type_bit, + tree exp, ...) + { + va_list ap; +@@ -19330,7 +19442,9 @@ + rtx op[NEON_MAX_BUILTIN_ARGS]; + enum machine_mode tmode = insn_data[icode].operand[0].mode; + enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; ++ enum machine_mode other_mode; + int argc = 0; ++ int opno; + + if (have_retval + && (!target +@@ -19348,26 +19462,46 @@ + break; + else + { ++ opno = argc + have_retval; ++ mode[argc] = insn_data[icode].operand[opno].mode; + arg[argc] = CALL_EXPR_ARG (exp, argc); ++ if (thisarg == NEON_ARG_MEMORY) ++ { ++ other_mode = insn_data[icode].operand[1 - opno].mode; ++ arg[argc] = neon_dereference_pointer (arg[argc], mode[argc], ++ other_mode, type_bit); ++ } + op[argc] = expand_normal (arg[argc]); +- mode[argc] = insn_data[icode].operand[argc + have_retval].mode; + + switch (thisarg) + { + case NEON_ARG_COPY_TO_REG: + /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ +- if (!(*insn_data[icode].operand[argc + have_retval].predicate) ++ if (!(*insn_data[icode].operand[opno].predicate) + (op[argc], mode[argc])) + op[argc] = copy_to_mode_reg (mode[argc], op[argc]); + break; + + case NEON_ARG_CONSTANT: + /* FIXME: This error message is somewhat unhelpful. */ +- if (!(*insn_data[icode].operand[argc + have_retval].predicate) ++ if (!(*insn_data[icode].operand[opno].predicate) + (op[argc], mode[argc])) + error ("argument must be a constant"); + break; + ++ case NEON_ARG_MEMORY: ++ gcc_assert (MEM_P (op[argc])); ++ PUT_MODE (op[argc], mode[argc]); ++ /* ??? arm_neon.h uses the same built-in functions for signed ++ and unsigned accesses, casting where necessary. This isn't ++ alias safe. */ ++ set_mem_alias_set (op[argc], 0); ++ if (!(*insn_data[icode].operand[opno].predicate) ++ (op[argc], mode[argc])) ++ op[argc] = (replace_equiv_address ++ (op[argc], force_reg (Pmode, XEXP (op[argc], 0)))); ++ break; ++ + case NEON_ARG_STOP: + gcc_unreachable (); + } +@@ -19446,14 +19580,15 @@ + arm_expand_neon_builtin (int fcode, tree exp, rtx target) + { + neon_itype itype; +- enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); ++ enum neon_builtin_type_bits type_bit; ++ enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit); + + switch (itype) + { + case NEON_UNOP: + case NEON_CONVERT: + case NEON_DUPLANE: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_BINOP: +@@ -19463,90 +19598,90 @@ + case NEON_SCALARMULH: + case NEON_SHIFTINSERT: + case NEON_LOGICBINOP: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + + case NEON_TERNOP: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_GETLANE: + case NEON_FIXCONV: + case NEON_SHIFTIMM: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + + case NEON_CREATE: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_DUP: + case NEON_SPLIT: + case NEON_REINTERP: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_COMBINE: + case NEON_VTBL: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_RESULTPAIR: +- return arm_expand_neon_args (target, icode, 0, exp, ++ return arm_expand_neon_args (target, icode, 0, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_STOP); + + case NEON_LANEMUL: + case NEON_LANEMULL: + case NEON_LANEMULH: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_LANEMAC: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_SHIFTACC: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_SCALARMAC: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_CONSTANT, NEON_ARG_STOP); + + case NEON_SELECT: + case NEON_VTBX: +- return arm_expand_neon_args (target, icode, 1, exp, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, + NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, + NEON_ARG_STOP); + + case NEON_LOAD1: + case NEON_LOADSTRUCT: +- return arm_expand_neon_args (target, icode, 1, exp, +- NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, ++ NEON_ARG_MEMORY, NEON_ARG_STOP); + + case NEON_LOAD1LANE: + case NEON_LOADSTRUCTLANE: +- return arm_expand_neon_args (target, icode, 1, exp, +- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, ++ return arm_expand_neon_args (target, icode, 1, type_bit, exp, ++ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + + case NEON_STORE1: + case NEON_STORESTRUCT: +- return arm_expand_neon_args (target, icode, 0, exp, +- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); ++ return arm_expand_neon_args (target, icode, 0, type_bit, exp, ++ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); + + case NEON_STORE1LANE: + case NEON_STORESTRUCTLANE: +- return arm_expand_neon_args (target, icode, 0, exp, +- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, ++ return arm_expand_neon_args (target, icode, 0, type_bit, exp, ++ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, + NEON_ARG_STOP); + } + +@@ -22267,6 +22402,20 @@ + return false; + } + ++/* Implements target hook array_mode_supported_p. */ ++ ++static bool ++arm_array_mode_supported_p (enum machine_mode mode, ++ unsigned HOST_WIDE_INT nelems) ++{ ++ if (TARGET_NEON ++ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) ++ && (nelems >= 2 && nelems <= 4)) ++ return true; ++ ++ return false; ++} ++ + /* Use the option -mvectorize-with-neon-quad to override the use of doubleword + registers when autovectorizing for Neon, at least until multiple vector + widths are supported properly by the middle-end. */ + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2011-02-21 14:04:51 +0000 ++++ new/gcc/config/arm/arm.h 2011-05-03 15:17:25 +0000 +@@ -1775,27 +1775,6 @@ + #define TARGET_DEFAULT_WORD_RELOCATIONS 0 + #endif + +-/* Nonzero if the constant value X is a legitimate general operand. +- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. +- +- On the ARM, allow any integer (invalid ones are removed later by insn +- patterns), nice doubles and symbol_refs which refer to the function's +- constant pool XXX. +- +- When generating pic allow anything. */ +-#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) +- +-#define THUMB_LEGITIMATE_CONSTANT_P(X) \ +- ( GET_CODE (X) == CONST_INT \ +- || GET_CODE (X) == CONST_DOUBLE \ +- || CONSTANT_ADDRESS_P (X) \ +- || flag_pic) +- +-#define LEGITIMATE_CONSTANT_P(X) \ +- (!arm_cannot_force_const_mem (X) \ +- && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ +- : THUMB_LEGITIMATE_CONSTANT_P (X))) +- + #ifndef SUBTARGET_NAME_ENCODING_LENGTHS + #define SUBTARGET_NAME_ENCODING_LENGTHS + #endif + +=== modified file 'gcc/config/arm/iterators.md' +--- old/gcc/config/arm/iterators.md 2010-09-21 13:11:03 +0000 ++++ new/gcc/config/arm/iterators.md 2011-05-03 15:14:56 +0000 +@@ -194,24 +194,22 @@ + + ;; Mode of pair of elements for each vector mode, to define transfer + ;; size for structure lane/dup loads and stores. +-(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") +- (V4HI "SI") (V8HI "SI") ++(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") ++ (V4HI "SI") (V8HI "SI") + (V2SI "V2SI") (V4SI "V2SI") + (V2SF "V2SF") (V4SF "V2SF") + (DI "V2DI") (V2DI "V2DI")]) + + ;; Similar, for three elements. +-;; ??? Should we define extra modes so that sizes of all three-element +-;; accesses can be accurately represented? +-(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI") +- (V4HI "V4HI") (V8HI "V4HI") +- (V2SI "V4SI") (V4SI "V4SI") +- (V2SF "V4SF") (V4SF "V4SF") +- (DI "EI") (V2DI "EI")]) ++(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") ++ (V4HI "BLK") (V8HI "BLK") ++ (V2SI "BLK") (V4SI "BLK") ++ (V2SF "BLK") (V4SF "BLK") ++ (DI "EI") (V2DI "EI")]) + + ;; Similar, for four elements. + (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") +- (V4HI "V4HI") (V8HI "V4HI") ++ (V4HI "V4HI") (V8HI "V4HI") + (V2SI "V4SI") (V4SI "V4SI") + (V2SF "V4SF") (V4SF "V4SF") + (DI "OI") (V2DI "OI")]) + +=== modified file 'gcc/config/arm/neon-testgen.ml' +--- old/gcc/config/arm/neon-testgen.ml 2010-05-24 18:36:31 +0000 ++++ new/gcc/config/arm/neon-testgen.ml 2011-05-03 15:14:56 +0000 +@@ -177,7 +177,7 @@ + let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in + "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}" + | (PtrTo elt | CstPtrTo elt) -> +- "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]" ++ "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]" + | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" + | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" + | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]" + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2011-01-03 20:52:22 +0000 ++++ new/gcc/config/arm/neon.md 2011-05-03 15:14:56 +0000 +@@ -4247,16 +4247,16 @@ + + (define_insn "neon_vld1" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") +- (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))] ++ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")] + UNSPEC_VLD1))] + "TARGET_NEON" +- "vld1.\t%h0, [%1]" ++ "vld1.\t%h0, %A1" + [(set_attr "neon_type" "neon_vld1_1_2_regs")] + ) + + (define_insn "neon_vld1_lane" + [(set (match_operand:VDX 0 "s_register_operand" "=w") +- (unspec:VDX [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:VDX [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:VDX 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VLD1_LANE))] +@@ -4267,9 +4267,9 @@ + if (lane < 0 || lane >= max) + error ("lane out of range"); + if (max == 1) +- return "vld1.\t%P0, [%1]"; ++ return "vld1.\t%P0, %A1"; + else +- return "vld1.\t{%P0[%c3]}, [%1]"; ++ return "vld1.\t{%P0[%c3]}, %A1"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_int 2)) +@@ -4279,7 +4279,7 @@ + + (define_insn "neon_vld1_lane" + [(set (match_operand:VQX 0 "s_register_operand" "=w") +- (unspec:VQX [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:VQX [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:VQX 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i")] + UNSPEC_VLD1_LANE))] +@@ -4298,9 +4298,9 @@ + } + operands[0] = gen_rtx_REG (mode, regno); + if (max == 2) +- return "vld1.\t%P0, [%1]"; ++ return "vld1.\t%P0, %A1"; + else +- return "vld1.\t{%P0[%c3]}, [%1]"; ++ return "vld1.\t{%P0[%c3]}, %A1"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_int 2)) +@@ -4310,14 +4310,14 @@ + + (define_insn "neon_vld1_dup" + [(set (match_operand:VDX 0 "s_register_operand" "=w") +- (unspec:VDX [(mem: (match_operand:SI 1 "s_register_operand" "r"))] ++ (unspec:VDX [(match_operand: 1 "neon_struct_operand" "Um")] + UNSPEC_VLD1_DUP))] + "TARGET_NEON" + { + if (GET_MODE_NUNITS (mode) > 1) +- return "vld1.\t{%P0[]}, [%1]"; ++ return "vld1.\t{%P0[]}, %A1"; + else +- return "vld1.\t%h0, [%1]"; ++ return "vld1.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (gt (const_string "") (const_string "1")) +@@ -4327,14 +4327,14 @@ + + (define_insn "neon_vld1_dup" + [(set (match_operand:VQX 0 "s_register_operand" "=w") +- (unspec:VQX [(mem: (match_operand:SI 1 "s_register_operand" "r"))] ++ (unspec:VQX [(match_operand: 1 "neon_struct_operand" "Um")] + UNSPEC_VLD1_DUP))] + "TARGET_NEON" + { + if (GET_MODE_NUNITS (mode) > 2) +- return "vld1.\t{%e0[], %f0[]}, [%1]"; ++ return "vld1.\t{%e0[], %f0[]}, %A1"; + else +- return "vld1.\t%h0, [%1]"; ++ return "vld1.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (gt (const_string "") (const_string "1")) +@@ -4343,15 +4343,15 @@ + ) + + (define_insn "neon_vst1" +- [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")] + UNSPEC_VST1))] + "TARGET_NEON" +- "vst1.\t%h1, [%0]" ++ "vst1.\t%h1, %A0" + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) + + (define_insn "neon_vst1_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (vec_select: + (match_operand:VDX 1 "s_register_operand" "w") + (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] +@@ -4362,9 +4362,9 @@ + if (lane < 0 || lane >= max) + error ("lane out of range"); + if (max == 1) +- return "vst1.\t{%P1}, [%0]"; ++ return "vst1.\t{%P1}, %A0"; + else +- return "vst1.\t{%P1[%c2]}, [%0]"; ++ return "vst1.\t{%P1[%c2]}, %A0"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_int 1)) +@@ -4372,7 +4372,7 @@ + (const_string "neon_vst1_vst2_lane")))]) + + (define_insn "neon_vst1_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (vec_select: + (match_operand:VQX 1 "s_register_operand" "w") + (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] +@@ -4391,24 +4391,24 @@ + } + operands[1] = gen_rtx_REG (mode, regno); + if (max == 2) +- return "vst1.\t{%P1}, [%0]"; ++ return "vst1.\t{%P1}, %A0"; + else +- return "vst1.\t{%P1[%c2]}, [%0]"; ++ return "vst1.\t{%P1[%c2]}, %A0"; + } + [(set_attr "neon_type" "neon_vst1_vst2_lane")] + ) + + (define_insn "neon_vld2" + [(set (match_operand:TI 0 "s_register_operand" "=w") +- (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2))] + "TARGET_NEON" + { + if ( == 64) +- return "vld1.64\t%h0, [%1]"; ++ return "vld1.64\t%h0, %A1"; + else +- return "vld2.\t%h0, [%1]"; ++ return "vld2.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_string "64")) +@@ -4418,16 +4418,16 @@ + + (define_insn "neon_vld2" + [(set (match_operand:OI 0 "s_register_operand" "=w") +- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2))] + "TARGET_NEON" +- "vld2.\t%h0, [%1]" ++ "vld2.\t%h0, %A1" + [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]) + + (define_insn "neon_vld2_lane" + [(set (match_operand:TI 0 "s_register_operand" "=w") +- (unspec:TI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:TI [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:TI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +@@ -4444,7 +4444,7 @@ + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = operands[1]; + ops[3] = operands[3]; +- output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, [%2]", ops); ++ output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, %A2", ops); + return ""; + } + [(set_attr "neon_type" "neon_vld1_vld2_lane")] +@@ -4452,7 +4452,7 @@ + + (define_insn "neon_vld2_lane" + [(set (match_operand:OI 0 "s_register_operand" "=w") +- (unspec:OI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:OI [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:OI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +@@ -4474,7 +4474,7 @@ + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = operands[1]; + ops[3] = GEN_INT (lane); +- output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, [%2]", ops); ++ output_asm_insn ("vld2.\t{%P0[%c3], %P1[%c3]}, %A2", ops); + return ""; + } + [(set_attr "neon_type" "neon_vld1_vld2_lane")] +@@ -4482,15 +4482,15 @@ + + (define_insn "neon_vld2_dup" + [(set (match_operand:TI 0 "s_register_operand" "=w") +- (unspec:TI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:TI [(match_operand: 1 "neon_struct_operand" "Um") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD2_DUP))] + "TARGET_NEON" + { + if (GET_MODE_NUNITS (mode) > 1) +- return "vld2.\t{%e0[], %f0[]}, [%1]"; ++ return "vld2.\t{%e0[], %f0[]}, %A1"; + else +- return "vld1.\t%h0, [%1]"; ++ return "vld1.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (gt (const_string "") (const_string "1")) +@@ -4499,16 +4499,16 @@ + ) + + (define_insn "neon_vst2" +- [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand:TI 0 "neon_struct_operand" "=Um") + (unspec:TI [(match_operand:TI 1 "s_register_operand" "w") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST2))] + "TARGET_NEON" + { + if ( == 64) +- return "vst1.64\t%h1, [%0]"; ++ return "vst1.64\t%h1, %A0"; + else +- return "vst2.\t%h1, [%0]"; ++ return "vst2.\t%h1, %A0"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_string "64")) +@@ -4517,17 +4517,17 @@ + ) + + (define_insn "neon_vst2" +- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um") + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST2))] + "TARGET_NEON" +- "vst2.\t%h1, [%0]" ++ "vst2.\t%h1, %A0" + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")] + ) + + (define_insn "neon_vst2_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (unspec: + [(match_operand:TI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") +@@ -4545,14 +4545,14 @@ + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = operands[2]; +- output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, [%0]", ops); ++ output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, %A0", ops); + return ""; + } + [(set_attr "neon_type" "neon_vst1_vst2_lane")] + ) + + (define_insn "neon_vst2_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (unspec: + [(match_operand:OI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") +@@ -4575,7 +4575,7 @@ + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = GEN_INT (lane); +- output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, [%0]", ops); ++ output_asm_insn ("vst2.\t{%P1[%c3], %P2[%c3]}, %A0", ops); + return ""; + } + [(set_attr "neon_type" "neon_vst1_vst2_lane")] +@@ -4583,15 +4583,15 @@ + + (define_insn "neon_vld3" + [(set (match_operand:EI 0 "s_register_operand" "=w") +- (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3))] + "TARGET_NEON" + { + if ( == 64) +- return "vld1.64\t%h0, [%1]"; ++ return "vld1.64\t%h0, %A1"; + else +- return "vld3.\t%h0, [%1]"; ++ return "vld3.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_string "64")) +@@ -4600,27 +4600,25 @@ + ) + + (define_expand "neon_vld3" +- [(match_operand:CI 0 "s_register_operand" "=w") +- (match_operand:SI 1 "s_register_operand" "+r") ++ [(match_operand:CI 0 "s_register_operand") ++ (match_operand:CI 1 "neon_struct_operand") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" + { +- emit_insn (gen_neon_vld3qa (operands[0], operands[0], +- operands[1], operands[1])); +- emit_insn (gen_neon_vld3qb (operands[0], operands[0], +- operands[1], operands[1])); ++ rtx mem; ++ ++ mem = adjust_address (operands[1], EImode, 0); ++ emit_insn (gen_neon_vld3qa (operands[0], mem)); ++ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode)); ++ emit_insn (gen_neon_vld3qb (operands[0], mem, operands[0])); + DONE; + }) + + (define_insn "neon_vld3qa" + [(set (match_operand:CI 0 "s_register_operand" "=w") +- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2")) +- (match_operand:CI 1 "s_register_operand" "0") ++ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VLD3A)) +- (set (match_operand:SI 2 "s_register_operand" "=r") +- (plus:SI (match_dup 3) +- (const_int 24)))] ++ UNSPEC_VLD3A))] + "TARGET_NEON" + { + int regno = REGNO (operands[0]); +@@ -4628,8 +4626,8 @@ + ops[0] = gen_rtx_REG (DImode, regno); + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = gen_rtx_REG (DImode, regno + 8); +- ops[3] = operands[2]; +- output_asm_insn ("vld3.\t{%P0, %P1, %P2}, [%3]!", ops); ++ ops[3] = operands[1]; ++ output_asm_insn ("vld3.\t{%P0, %P1, %P2}, %A3", ops); + return ""; + } + [(set_attr "neon_type" "neon_vld3_vld4")] +@@ -4637,13 +4635,10 @@ + + (define_insn "neon_vld3qb" + [(set (match_operand:CI 0 "s_register_operand" "=w") +- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2")) +- (match_operand:CI 1 "s_register_operand" "0") ++ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") ++ (match_operand:CI 2 "s_register_operand" "0") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VLD3B)) +- (set (match_operand:SI 2 "s_register_operand" "=r") +- (plus:SI (match_dup 3) +- (const_int 24)))] ++ UNSPEC_VLD3B))] + "TARGET_NEON" + { + int regno = REGNO (operands[0]); +@@ -4651,8 +4646,8 @@ + ops[0] = gen_rtx_REG (DImode, regno + 2); + ops[1] = gen_rtx_REG (DImode, regno + 6); + ops[2] = gen_rtx_REG (DImode, regno + 10); +- ops[3] = operands[2]; +- output_asm_insn ("vld3.\t{%P0, %P1, %P2}, [%3]!", ops); ++ ops[3] = operands[1]; ++ output_asm_insn ("vld3.\t{%P0, %P1, %P2}, %A3", ops); + return ""; + } + [(set_attr "neon_type" "neon_vld3_vld4")] +@@ -4660,7 +4655,7 @@ + + (define_insn "neon_vld3_lane" + [(set (match_operand:EI 0 "s_register_operand" "=w") +- (unspec:EI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:EI [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:EI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +@@ -4678,7 +4673,7 @@ + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = operands[1]; + ops[4] = operands[3]; +- output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", ++ output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3", + ops); + return ""; + } +@@ -4687,7 +4682,7 @@ + + (define_insn "neon_vld3_lane" + [(set (match_operand:CI 0 "s_register_operand" "=w") +- (unspec:CI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:CI [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:CI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +@@ -4710,7 +4705,7 @@ + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = operands[1]; + ops[4] = GEN_INT (lane); +- output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", ++ output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3", + ops); + return ""; + } +@@ -4719,7 +4714,7 @@ + + (define_insn "neon_vld3_dup" + [(set (match_operand:EI 0 "s_register_operand" "=w") +- (unspec:EI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:EI [(match_operand: 1 "neon_struct_operand" "Um") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD3_DUP))] + "TARGET_NEON" +@@ -4732,11 +4727,11 @@ + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = operands[1]; +- output_asm_insn ("vld3.\t{%P0[], %P1[], %P2[]}, [%3]", ops); ++ output_asm_insn ("vld3.\t{%P0[], %P1[], %P2[]}, %A3", ops); + return ""; + } + else +- return "vld1.\t%h0, [%1]"; ++ return "vld1.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (gt (const_string "") (const_string "1")) +@@ -4744,16 +4739,16 @@ + (const_string "neon_vld1_1_2_regs")))]) + + (define_insn "neon_vst3" +- [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand:EI 0 "neon_struct_operand" "=Um") + (unspec:EI [(match_operand:EI 1 "s_register_operand" "w") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST3))] + "TARGET_NEON" + { + if ( == 64) +- return "vst1.64\t%h1, [%0]"; ++ return "vst1.64\t%h1, %A0"; + else +- return "vst3.\t%h1, [%0]"; ++ return "vst3.\t%h1, %A0"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_string "64")) +@@ -4761,62 +4756,60 @@ + (const_string "neon_vst2_4_regs_vst3_vst4")))]) + + (define_expand "neon_vst3" +- [(match_operand:SI 0 "s_register_operand" "+r") +- (match_operand:CI 1 "s_register_operand" "w") ++ [(match_operand:CI 0 "neon_struct_operand") ++ (match_operand:CI 1 "s_register_operand") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" + { +- emit_insn (gen_neon_vst3qa (operands[0], operands[0], operands[1])); +- emit_insn (gen_neon_vst3qb (operands[0], operands[0], operands[1])); ++ rtx mem; ++ ++ mem = adjust_address (operands[0], EImode, 0); ++ emit_insn (gen_neon_vst3qa (mem, operands[1])); ++ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode)); ++ emit_insn (gen_neon_vst3qb (mem, operands[1])); + DONE; + }) + + (define_insn "neon_vst3qa" +- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) +- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w") ++ [(set (match_operand:EI 0 "neon_struct_operand" "=Um") ++ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VST3A)) +- (set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (match_dup 1) +- (const_int 24)))] ++ UNSPEC_VST3A))] + "TARGET_NEON" + { +- int regno = REGNO (operands[2]); ++ int regno = REGNO (operands[1]); + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 8); +- output_asm_insn ("vst3.\t{%P1, %P2, %P3}, [%0]!", ops); ++ output_asm_insn ("vst3.\t{%P1, %P2, %P3}, %A0", ops); + return ""; + } + [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + ) + + (define_insn "neon_vst3qb" +- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) +- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w") ++ [(set (match_operand:EI 0 "neon_struct_operand" "=Um") ++ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VST3B)) +- (set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (match_dup 1) +- (const_int 24)))] ++ UNSPEC_VST3B))] + "TARGET_NEON" + { +- int regno = REGNO (operands[2]); ++ int regno = REGNO (operands[1]); + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 6); + ops[3] = gen_rtx_REG (DImode, regno + 10); +- output_asm_insn ("vst3.\t{%P1, %P2, %P3}, [%0]!", ops); ++ output_asm_insn ("vst3.\t{%P1, %P2, %P3}, %A0", ops); + return ""; + } + [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + ) + + (define_insn "neon_vst3_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (unspec: + [(match_operand:EI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") +@@ -4835,7 +4828,7 @@ + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = gen_rtx_REG (DImode, regno + 4); + ops[4] = operands[2]; +- output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", ++ output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0", + ops); + return ""; + } +@@ -4843,7 +4836,7 @@ + ) + + (define_insn "neon_vst3_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (unspec: + [(match_operand:CI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") +@@ -4867,7 +4860,7 @@ + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 8); + ops[4] = GEN_INT (lane); +- output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", ++ output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0", + ops); + return ""; + } +@@ -4875,15 +4868,15 @@ + + (define_insn "neon_vld4" + [(set (match_operand:OI 0 "s_register_operand" "=w") +- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4))] + "TARGET_NEON" + { + if ( == 64) +- return "vld1.64\t%h0, [%1]"; ++ return "vld1.64\t%h0, %A1"; + else +- return "vld4.\t%h0, [%1]"; ++ return "vld4.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_string "64")) +@@ -4892,27 +4885,25 @@ + ) + + (define_expand "neon_vld4" +- [(match_operand:XI 0 "s_register_operand" "=w") +- (match_operand:SI 1 "s_register_operand" "+r") ++ [(match_operand:XI 0 "s_register_operand") ++ (match_operand:XI 1 "neon_struct_operand") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" + { +- emit_insn (gen_neon_vld4qa (operands[0], operands[0], +- operands[1], operands[1])); +- emit_insn (gen_neon_vld4qb (operands[0], operands[0], +- operands[1], operands[1])); ++ rtx mem; ++ ++ mem = adjust_address (operands[1], OImode, 0); ++ emit_insn (gen_neon_vld4qa (operands[0], mem)); ++ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode)); ++ emit_insn (gen_neon_vld4qb (operands[0], mem, operands[0])); + DONE; + }) + + (define_insn "neon_vld4qa" + [(set (match_operand:XI 0 "s_register_operand" "=w") +- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2")) +- (match_operand:XI 1 "s_register_operand" "0") ++ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VLD4A)) +- (set (match_operand:SI 2 "s_register_operand" "=r") +- (plus:SI (match_dup 3) +- (const_int 32)))] ++ UNSPEC_VLD4A))] + "TARGET_NEON" + { + int regno = REGNO (operands[0]); +@@ -4921,8 +4912,8 @@ + ops[1] = gen_rtx_REG (DImode, regno + 4); + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = gen_rtx_REG (DImode, regno + 12); +- ops[4] = operands[2]; +- output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, [%4]!", ops); ++ ops[4] = operands[1]; ++ output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, %A4", ops); + return ""; + } + [(set_attr "neon_type" "neon_vld3_vld4")] +@@ -4930,13 +4921,10 @@ + + (define_insn "neon_vld4qb" + [(set (match_operand:XI 0 "s_register_operand" "=w") +- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2")) +- (match_operand:XI 1 "s_register_operand" "0") ++ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um") ++ (match_operand:XI 2 "s_register_operand" "0") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VLD4B)) +- (set (match_operand:SI 2 "s_register_operand" "=r") +- (plus:SI (match_dup 3) +- (const_int 32)))] ++ UNSPEC_VLD4B))] + "TARGET_NEON" + { + int regno = REGNO (operands[0]); +@@ -4945,8 +4933,8 @@ + ops[1] = gen_rtx_REG (DImode, regno + 6); + ops[2] = gen_rtx_REG (DImode, regno + 10); + ops[3] = gen_rtx_REG (DImode, regno + 14); +- ops[4] = operands[2]; +- output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, [%4]!", ops); ++ ops[4] = operands[1]; ++ output_asm_insn ("vld4.\t{%P0, %P1, %P2, %P3}, %A4", ops); + return ""; + } + [(set_attr "neon_type" "neon_vld3_vld4")] +@@ -4954,7 +4942,7 @@ + + (define_insn "neon_vld4_lane" + [(set (match_operand:OI 0 "s_register_operand" "=w") +- (unspec:OI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:OI [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:OI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +@@ -4973,7 +4961,7 @@ + ops[3] = gen_rtx_REG (DImode, regno + 6); + ops[4] = operands[1]; + ops[5] = operands[3]; +- output_asm_insn ("vld4.\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", ++ output_asm_insn ("vld4.\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4", + ops); + return ""; + } +@@ -4982,7 +4970,7 @@ + + (define_insn "neon_vld4_lane" + [(set (match_operand:XI 0 "s_register_operand" "=w") +- (unspec:XI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:XI [(match_operand: 1 "neon_struct_operand" "Um") + (match_operand:XI 2 "s_register_operand" "0") + (match_operand:SI 3 "immediate_operand" "i") + (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +@@ -5006,7 +4994,7 @@ + ops[3] = gen_rtx_REG (DImode, regno + 12); + ops[4] = operands[1]; + ops[5] = GEN_INT (lane); +- output_asm_insn ("vld4.\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", ++ output_asm_insn ("vld4.\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4", + ops); + return ""; + } +@@ -5015,7 +5003,7 @@ + + (define_insn "neon_vld4_dup" + [(set (match_operand:OI 0 "s_register_operand" "=w") +- (unspec:OI [(mem: (match_operand:SI 1 "s_register_operand" "r")) ++ (unspec:OI [(match_operand: 1 "neon_struct_operand" "Um") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD4_DUP))] + "TARGET_NEON" +@@ -5029,12 +5017,12 @@ + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 6); + ops[4] = operands[1]; +- output_asm_insn ("vld4.\t{%P0[], %P1[], %P2[], %P3[]}, [%4]", ++ output_asm_insn ("vld4.\t{%P0[], %P1[], %P2[], %P3[]}, %A4", + ops); + return ""; + } + else +- return "vld1.\t%h0, [%1]"; ++ return "vld1.\t%h0, %A1"; + } + [(set (attr "neon_type") + (if_then_else (gt (const_string "") (const_string "1")) +@@ -5043,16 +5031,16 @@ + ) + + (define_insn "neon_vst4" +- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um") + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") + (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST4))] + "TARGET_NEON" + { + if ( == 64) +- return "vst1.64\t%h1, [%0]"; ++ return "vst1.64\t%h1, %A0"; + else +- return "vst4.\t%h1, [%0]"; ++ return "vst4.\t%h1, %A0"; + } + [(set (attr "neon_type") + (if_then_else (eq (const_string "") (const_string "64")) +@@ -5061,64 +5049,62 @@ + ) + + (define_expand "neon_vst4" +- [(match_operand:SI 0 "s_register_operand" "+r") +- (match_operand:XI 1 "s_register_operand" "w") ++ [(match_operand:XI 0 "neon_struct_operand") ++ (match_operand:XI 1 "s_register_operand") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + "TARGET_NEON" + { +- emit_insn (gen_neon_vst4qa (operands[0], operands[0], operands[1])); +- emit_insn (gen_neon_vst4qb (operands[0], operands[0], operands[1])); ++ rtx mem; ++ ++ mem = adjust_address (operands[0], OImode, 0); ++ emit_insn (gen_neon_vst4qa (mem, operands[1])); ++ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode)); ++ emit_insn (gen_neon_vst4qb (mem, operands[1])); + DONE; + }) + + (define_insn "neon_vst4qa" +- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) +- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w") ++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um") ++ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VST4A)) +- (set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (match_dup 1) +- (const_int 32)))] ++ UNSPEC_VST4A))] + "TARGET_NEON" + { +- int regno = REGNO (operands[2]); ++ int regno = REGNO (operands[1]); + rtx ops[5]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 4); + ops[3] = gen_rtx_REG (DImode, regno + 8); + ops[4] = gen_rtx_REG (DImode, regno + 12); +- output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, [%0]!", ops); ++ output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, %A0", ops); + return ""; + } + [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + ) + + (define_insn "neon_vst4qb" +- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) +- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w") ++ [(set (match_operand:OI 0 "neon_struct_operand" "=Um") ++ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w") + (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] +- UNSPEC_VST4B)) +- (set (match_operand:SI 0 "s_register_operand" "=r") +- (plus:SI (match_dup 1) +- (const_int 32)))] ++ UNSPEC_VST4B))] + "TARGET_NEON" + { +- int regno = REGNO (operands[2]); ++ int regno = REGNO (operands[1]); + rtx ops[5]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno + 2); + ops[2] = gen_rtx_REG (DImode, regno + 6); + ops[3] = gen_rtx_REG (DImode, regno + 10); + ops[4] = gen_rtx_REG (DImode, regno + 14); +- output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, [%0]!", ops); ++ output_asm_insn ("vst4.\t{%P1, %P2, %P3, %P4}, %A0", ops); + return ""; + } + [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] + ) + + (define_insn "neon_vst4_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (unspec: + [(match_operand:OI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") +@@ -5138,7 +5124,7 @@ + ops[3] = gen_rtx_REG (DImode, regno + 4); + ops[4] = gen_rtx_REG (DImode, regno + 6); + ops[5] = operands[2]; +- output_asm_insn ("vst4.\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", ++ output_asm_insn ("vst4.\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0", + ops); + return ""; + } +@@ -5146,7 +5132,7 @@ + ) + + (define_insn "neon_vst4_lane" +- [(set (mem: (match_operand:SI 0 "s_register_operand" "r")) ++ [(set (match_operand: 0 "neon_struct_operand" "=Um") + (unspec: + [(match_operand:XI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i") +@@ -5171,7 +5157,7 @@ + ops[3] = gen_rtx_REG (DImode, regno + 8); + ops[4] = gen_rtx_REG (DImode, regno + 12); + ops[5] = GEN_INT (lane); +- output_asm_insn ("vst4.\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", ++ output_asm_insn ("vst4.\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0", + ops); + return ""; + } + +=== modified file 'gcc/config/arm/predicates.md' +--- old/gcc/config/arm/predicates.md 2011-04-07 10:52:12 +0000 ++++ new/gcc/config/arm/predicates.md 2011-05-03 15:14:56 +0000 +@@ -683,3 +683,7 @@ + } + return true; + }) ++ ++(define_special_predicate "neon_struct_operand" ++ (and (match_code "mem") ++ (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) + +=== modified file 'gcc/doc/tm.texi' +--- old/gcc/doc/tm.texi 2011-01-22 19:35:10 +0000 ++++ new/gcc/doc/tm.texi 2011-05-03 15:17:25 +0000 +@@ -2533,7 +2533,7 @@ + register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when + @var{x} is a floating-point constant. If the constant can't be loaded + into any kind of register, code generation will be better if +-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead ++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead + of using @code{TARGET_PREFERRED_RELOAD_CLASS}. + + If an insn has pseudos in it after register allocation, reload will go +@@ -2570,8 +2570,8 @@ + register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when + @var{x} is a floating-point constant. If the constant can't be loaded + into any kind of register, code generation will be better if +-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead +-of using @code{PREFERRED_RELOAD_CLASS}. ++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead ++of using @code{TARGET_PREFERRED_RELOAD_CLASS}. + + If an insn has pseudos in it after register allocation, reload will go + through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS} +@@ -4319,6 +4319,34 @@ + must have move patterns for this mode. + @end deftypefn + ++@deftypefn {Target Hook} bool TARGET_ARRAY_MODE_SUPPORTED_P (enum machine_mode @var{mode}, unsigned HOST_WIDE_INT @var{nelems}) ++Return true if GCC should try to use a scalar mode to store an array ++of @var{nelems} elements, given that each element has mode @var{mode}. ++Returning true here overrides the usual @code{MAX_FIXED_MODE} limit ++and allows GCC to use any defined integer mode. ++ ++One use of this hook is to support vector load and store operations ++that operate on several homogeneous vectors. For example, ARM NEON ++has operations like: ++ ++@smallexample ++int8x8x3_t vld3_s8 (const int8_t *) ++@end smallexample ++ ++where the return type is defined as: ++ ++@smallexample ++typedef struct int8x8x3_t ++@{ ++ int8x8_t val[3]; ++@} int8x8x3_t; ++@end smallexample ++ ++If this hook allows @code{val} to have a scalar mode, then ++@code{int8x8x3_t} can have the same mode. GCC can then store ++@code{int8x8x3_t}s in registers rather than forcing them onto the stack. ++@end deftypefn ++ + @deftypefn {Target Hook} bool TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P (enum machine_mode @var{mode}) + Define this to return nonzero for machine modes for which the port has + small register classes. If this target hook returns nonzero for a given +@@ -5577,13 +5605,13 @@ + @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook. + @end defmac + +-@defmac LEGITIMATE_CONSTANT_P (@var{x}) +-A C expression that is nonzero if @var{x} is a legitimate constant for +-an immediate operand on the target machine. You can assume that +-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact, +-@samp{1} is a suitable definition for this macro on machines where +-anything @code{CONSTANT_P} is valid. +-@end defmac ++@deftypefn {Target Hook} bool TARGET_LEGITIMATE_CONSTANT_P (enum machine_mode @var{mode}, rtx @var{x}) ++This hook returns true if @var{x} is a legitimate constant for a ++@var{mode}-mode immediate operand on the target machine. You can assume that ++@var{x} satisfies @code{CONSTANT_P}, so you need not check this. ++ ++The default definition returns true. ++@end deftypefn + + @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x}) + This hook is used to undo the possibly obfuscating effects of the + +=== modified file 'gcc/doc/tm.texi.in' +--- old/gcc/doc/tm.texi.in 2011-01-22 19:35:10 +0000 ++++ new/gcc/doc/tm.texi.in 2011-05-03 15:17:25 +0000 +@@ -2521,7 +2521,7 @@ + register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when + @var{x} is a floating-point constant. If the constant can't be loaded + into any kind of register, code generation will be better if +-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead ++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead + of using @code{TARGET_PREFERRED_RELOAD_CLASS}. + + If an insn has pseudos in it after register allocation, reload will go +@@ -2558,8 +2558,8 @@ + register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when + @var{x} is a floating-point constant. If the constant can't be loaded + into any kind of register, code generation will be better if +-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead +-of using @code{PREFERRED_RELOAD_CLASS}. ++@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead ++of using @code{TARGET_PREFERRED_RELOAD_CLASS}. + + If an insn has pseudos in it after register allocation, reload will go + through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS} +@@ -4305,6 +4305,8 @@ + must have move patterns for this mode. + @end deftypefn + ++@hook TARGET_ARRAY_MODE_SUPPORTED_P ++ + @hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P + Define this to return nonzero for machine modes for which the port has + small register classes. If this target hook returns nonzero for a given +@@ -5555,13 +5557,13 @@ + @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook. + @end defmac + +-@defmac LEGITIMATE_CONSTANT_P (@var{x}) +-A C expression that is nonzero if @var{x} is a legitimate constant for +-an immediate operand on the target machine. You can assume that +-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact, +-@samp{1} is a suitable definition for this macro on machines where +-anything @code{CONSTANT_P} is valid. +-@end defmac ++@hook TARGET_LEGITIMATE_CONSTANT_P ++This hook returns true if @var{x} is a legitimate constant for a ++@var{mode}-mode immediate operand on the target machine. You can assume that ++@var{x} satisfies @code{CONSTANT_P}, so you need not check this. ++ ++The default definition returns true. ++@end deftypefn + + @hook TARGET_DELEGITIMIZE_ADDRESS + This hook is used to undo the possibly obfuscating effects of the + +=== modified file 'gcc/expr.c' +--- old/gcc/expr.c 2011-04-05 16:18:11 +0000 ++++ new/gcc/expr.c 2011-05-03 15:17:25 +0000 +@@ -1497,7 +1497,7 @@ + if (nregs == 0) + return; + +- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x)) ++ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x)) + x = validize_mem (force_const_mem (mode, x)); + + /* See if the machine can do this with a load multiple insn. */ +@@ -2308,7 +2308,7 @@ + offset -= size; + + cst = (*constfun) (constfundata, offset, mode); +- if (!LEGITIMATE_CONSTANT_P (cst)) ++ if (!targetm.legitimate_constant_p (mode, cst)) + return 0; + + if (!reverse) +@@ -3363,7 +3363,7 @@ + + y_cst = y; + +- if (!LEGITIMATE_CONSTANT_P (y)) ++ if (!targetm.legitimate_constant_p (mode, y)) + { + y = force_const_mem (mode, y); + +@@ -3419,7 +3419,7 @@ + + REAL_VALUE_FROM_CONST_DOUBLE (r, y); + +- if (LEGITIMATE_CONSTANT_P (y)) ++ if (targetm.legitimate_constant_p (dstmode, y)) + oldcost = rtx_cost (y, SET, speed); + else + oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed); +@@ -3442,7 +3442,7 @@ + + trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode); + +- if (LEGITIMATE_CONSTANT_P (trunc_y)) ++ if (targetm.legitimate_constant_p (srcmode, trunc_y)) + { + /* Skip if the target needs extra instructions to perform + the extension. */ +@@ -3855,7 +3855,7 @@ + by setting SKIP to 0. */ + skip = (reg_parm_stack_space == 0) ? 0 : not_stack; + +- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x)) ++ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x)) + x = validize_mem (force_const_mem (mode, x)); + + /* If X is a hard register in a non-integer mode, copy it into a pseudo; +@@ -9066,7 +9066,7 @@ + constant and we don't need a memory reference. */ + if (CONSTANT_P (op0) + && mode2 != BLKmode +- && LEGITIMATE_CONSTANT_P (op0) ++ && targetm.legitimate_constant_p (mode2, op0) + && !must_force_mem) + op0 = force_reg (mode2, op0); + + +=== modified file 'gcc/hooks.c' +--- old/gcc/hooks.c 2010-11-25 13:16:03 +0000 ++++ new/gcc/hooks.c 2011-05-03 15:16:01 +0000 +@@ -101,6 +101,15 @@ + return true; + } + ++/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT) ++ and returns false. */ ++bool ++hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED, ++ unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED) ++{ ++ return false; ++} ++ + /* Generic hook that takes (FILE *, const char *) and does nothing. */ + void + hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED) + +=== modified file 'gcc/hooks.h' +--- old/gcc/hooks.h 2010-11-25 13:16:03 +0000 ++++ new/gcc/hooks.h 2011-05-03 15:16:01 +0000 +@@ -34,6 +34,8 @@ + extern bool hook_bool_mode_true (enum machine_mode); + extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx); + extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx); ++extern bool hook_bool_mode_uhwi_false (enum machine_mode, ++ unsigned HOST_WIDE_INT); + extern bool hook_bool_tree_false (tree); + extern bool hook_bool_const_tree_false (const_tree); + extern bool hook_bool_tree_true (tree); + +=== modified file 'gcc/recog.c' +--- old/gcc/recog.c 2010-11-30 16:36:19 +0000 ++++ new/gcc/recog.c 2011-05-03 15:17:25 +0000 +@@ -930,7 +930,9 @@ + return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode + || mode == VOIDmode) + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) +- && LEGITIMATE_CONSTANT_P (op)); ++ && targetm.legitimate_constant_p (mode == VOIDmode ++ ? GET_MODE (op) ++ : mode, op)); + + /* Except for certain constants with VOIDmode, already checked for, + OP's mode must match MODE if MODE specifies a mode. */ +@@ -1107,7 +1109,9 @@ + && (GET_MODE (op) == mode || mode == VOIDmode + || GET_MODE (op) == VOIDmode) + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) +- && LEGITIMATE_CONSTANT_P (op)); ++ && targetm.legitimate_constant_p (mode == VOIDmode ++ ? GET_MODE (op) ++ : mode, op)); + } + + /* Returns 1 if OP is an operand that is a CONST_INT. */ + +=== modified file 'gcc/reload.c' +--- old/gcc/reload.c 2011-02-02 16:52:21 +0000 ++++ new/gcc/reload.c 2011-05-03 15:17:25 +0000 +@@ -4721,7 +4721,8 @@ + simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno], + GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); + gcc_assert (tem); +- if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem)) ++ if (CONSTANT_P (tem) ++ && !targetm.legitimate_constant_p (GET_MODE (x), tem)) + { + tem = force_const_mem (GET_MODE (x), tem); + i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), +@@ -6049,7 +6050,7 @@ + enum reload_type type, int ind_levels) + { + if (CONSTANT_P (x) +- && (! LEGITIMATE_CONSTANT_P (x) ++ && (!targetm.legitimate_constant_p (mode, x) + || targetm.preferred_reload_class (x, rclass) == NO_REGS)) + { + x = force_const_mem (mode, x); +@@ -6059,7 +6060,7 @@ + + else if (GET_CODE (x) == PLUS + && CONSTANT_P (XEXP (x, 1)) +- && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) ++ && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1)) + || targetm.preferred_reload_class (XEXP (x, 1), rclass) + == NO_REGS)) + { + +=== modified file 'gcc/reload1.c' +--- old/gcc/reload1.c 2011-01-23 21:11:24 +0000 ++++ new/gcc/reload1.c 2011-05-03 15:17:25 +0000 +@@ -4155,6 +4155,9 @@ + } + else if (function_invariant_p (x)) + { ++ enum machine_mode mode; ++ ++ mode = GET_MODE (SET_DEST (set)); + if (GET_CODE (x) == PLUS) + { + /* This is PLUS of frame pointer and a constant, +@@ -4167,12 +4170,11 @@ + reg_equiv_invariant[i] = x; + num_eliminable_invariants++; + } +- else if (LEGITIMATE_CONSTANT_P (x)) ++ else if (targetm.legitimate_constant_p (mode, x)) + reg_equiv_constant[i] = x; + else + { +- reg_equiv_memory_loc[i] +- = force_const_mem (GET_MODE (SET_DEST (set)), x); ++ reg_equiv_memory_loc[i] = force_const_mem (mode, x); + if (! reg_equiv_memory_loc[i]) + reg_equiv_init[i] = NULL_RTX; + } + +=== modified file 'gcc/stor-layout.c' +--- old/gcc/stor-layout.c 2011-03-10 22:37:22 +0000 ++++ new/gcc/stor-layout.c 2011-05-03 15:16:01 +0000 +@@ -546,6 +546,34 @@ + return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT)); + } + ++/* Return the natural mode of an array, given that it is SIZE bytes in ++ total and has elements of type ELEM_TYPE. */ ++ ++static enum machine_mode ++mode_for_array (tree elem_type, tree size) ++{ ++ tree elem_size; ++ unsigned HOST_WIDE_INT int_size, int_elem_size; ++ bool limit_p; ++ ++ /* One-element arrays get the component type's mode. */ ++ elem_size = TYPE_SIZE (elem_type); ++ if (simple_cst_equal (size, elem_size)) ++ return TYPE_MODE (elem_type); ++ ++ limit_p = true; ++ if (host_integerp (size, 1) && host_integerp (elem_size, 1)) ++ { ++ int_size = tree_low_cst (size, 1); ++ int_elem_size = tree_low_cst (elem_size, 1); ++ if (int_elem_size > 0 ++ && int_size % int_elem_size == 0 ++ && targetm.array_mode_supported_p (TYPE_MODE (elem_type), ++ int_size / int_elem_size)) ++ limit_p = false; ++ } ++ return mode_for_size_tree (size, MODE_INT, limit_p); ++} + + /* Subroutine of layout_decl: Force alignment required for the data type. + But if the decl itself wants greater alignment, don't override that. */ +@@ -2039,14 +2067,8 @@ + && (TYPE_MODE (TREE_TYPE (type)) != BLKmode + || TYPE_NO_FORCE_BLK (TREE_TYPE (type)))) + { +- /* One-element arrays get the component type's mode. */ +- if (simple_cst_equal (TYPE_SIZE (type), +- TYPE_SIZE (TREE_TYPE (type)))) +- SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type))); +- else +- SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type), +- MODE_INT, 1)); +- ++ SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type), ++ TYPE_SIZE (type))); + if (TYPE_MODE (type) != BLKmode + && STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT + && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type))) + +=== modified file 'gcc/target.def' +--- old/gcc/target.def 2011-01-22 19:35:10 +0000 ++++ new/gcc/target.def 2011-05-03 15:17:25 +0000 +@@ -1344,6 +1344,13 @@ + unsigned, (unsigned nunroll, struct loop *loop), + NULL) + ++/* True if X is a legitimate MODE-mode immediate operand. */ ++DEFHOOK ++(legitimate_constant_p, ++ "", ++ bool, (enum machine_mode mode, rtx x), ++ default_legitimate_constant_p) ++ + /* True if the constant X cannot be placed in the constant pool. */ + DEFHOOK + (cannot_force_const_mem, +@@ -1611,6 +1618,38 @@ + bool, (enum machine_mode mode), + hook_bool_mode_false) + ++/* True if we should try to use a scalar mode to represent an array, ++ overriding the usual MAX_FIXED_MODE limit. */ ++DEFHOOK ++(array_mode_supported_p, ++ "Return true if GCC should try to use a scalar mode to store an array\n\ ++of @var{nelems} elements, given that each element has mode @var{mode}.\n\ ++Returning true here overrides the usual @code{MAX_FIXED_MODE} limit\n\ ++and allows GCC to use any defined integer mode.\n\ ++\n\ ++One use of this hook is to support vector load and store operations\n\ ++that operate on several homogeneous vectors. For example, ARM NEON\n\ ++has operations like:\n\ ++\n\ ++@smallexample\n\ ++int8x8x3_t vld3_s8 (const int8_t *)\n\ ++@end smallexample\n\ ++\n\ ++where the return type is defined as:\n\ ++\n\ ++@smallexample\n\ ++typedef struct int8x8x3_t\n\ ++@{\n\ ++ int8x8_t val[3];\n\ ++@} int8x8x3_t;\n\ ++@end smallexample\n\ ++\n\ ++If this hook allows @code{val} to have a scalar mode, then\n\ ++@code{int8x8x3_t} can have the same mode. GCC can then store\n\ ++@code{int8x8x3_t}s in registers rather than forcing them onto the stack.", ++ bool, (enum machine_mode mode, unsigned HOST_WIDE_INT nelems), ++ hook_bool_mode_uhwi_false) ++ + /* Compute cost of moving data from a register of class FROM to one of + TO, using MODE. */ + DEFHOOK + +=== modified file 'gcc/targhooks.c' +--- old/gcc/targhooks.c 2011-01-14 15:02:20 +0000 ++++ new/gcc/targhooks.c 2011-05-03 15:17:25 +0000 +@@ -1519,4 +1519,15 @@ + { OPT_LEVELS_NONE, 0, NULL, 0 } + }; + ++bool ++default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, ++ rtx x ATTRIBUTE_UNUSED) ++{ ++#ifdef LEGITIMATE_CONSTANT_P ++ return LEGITIMATE_CONSTANT_P (x); ++#else ++ return true; ++#endif ++} ++ + #include "gt-targhooks.h" + +=== modified file 'gcc/targhooks.h' +--- old/gcc/targhooks.h 2011-01-14 15:02:20 +0000 ++++ new/gcc/targhooks.h 2011-05-03 15:17:25 +0000 +@@ -183,3 +183,4 @@ + + extern void *default_get_pch_validity (size_t *); + extern const char *default_pch_valid_p (const void *, size_t); ++extern bool default_legitimate_constant_p (enum machine_mode, rtx); + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vld3-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 2011-05-03 15:14:56 +0000 +@@ -0,0 +1,27 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++ ++uint32_t buffer[12]; ++ ++void __attribute__((noinline)) ++foo (uint32_t *a) ++{ ++ uint32x4x3_t x; ++ ++ x = vld3q_u32 (a); ++ x.val[0] = vaddq_u32 (x.val[0], x.val[1]); ++ vst3q_u32 (a, x); ++} ++ ++int ++main (void) ++{ ++ buffer[0] = 1; ++ buffer[1] = 2; ++ foo (buffer); ++ return buffer[0] != 3; ++} + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vst3-1.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 2011-05-03 15:14:56 +0000 +@@ -0,0 +1,25 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target arm_neon_hw } */ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++#include "arm_neon.h" ++ ++uint32_t buffer[64]; ++ ++void __attribute__((noinline)) ++foo (uint32_t *a) ++{ ++ uint32x4x3_t x; ++ ++ x = vld3q_u32 (a); ++ a[35] = 1; ++ vst3q_lane_u32 (a + 32, x, 1); ++} ++ ++int ++main (void) ++{ ++ foo (buffer); ++ return buffer[35] != 1; ++} + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x4_t = vld1q_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x8_t = vld1q_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x16_t = vld1q_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x8_t = vld1q_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x4_t = vld1q_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x2_t = vld1q_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x16_t = vld1q_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x8_t = vld1q_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x4_t = vld1q_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x2_t = vld1q_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x16_t = vld1q_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x4_t = vld1q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x8_t = vld1q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x16_t = vld1q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x8_t = vld1q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x4_t = vld1q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x2_t = vld1q_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x16_t = vld1q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x8_t = vld1q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x4_t = vld1q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x2_t = vld1q_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x16_t = vld1q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2_t = vld1_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4_t = vld1_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8_t = vld1_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4_t = vld1_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2_t = vld1_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1_t = vld1_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8_t = vld1_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4_t = vld1_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2_t = vld1_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1_t = vld1_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8_t = vld1_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2_t = vld1_f32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4_t = vld1_p16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8_t = vld1_p8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4_t = vld1_s16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2_t = vld1_s32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1_t = vld1_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8_t = vld1_s8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4_t = vld1_u16 (0); + } + +-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2_t = vld1_u32 (0); + } + +-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1_t = vld1_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8_t = vld1_u8 (0); + } + +-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_float32x4x2_t = vld2q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_poly16x8x2_t = vld2q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_poly8x16x2_t = vld2q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int16x8x2_t = vld2q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int32x4x2_t = vld2q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int8x16x2_t = vld2q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint16x8x2_t = vld2q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint32x4x2_t = vld2q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint8x16x2_t = vld2q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x2_t = vld2_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x2_t = vld2_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x2_t = vld2_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x2_t = vld2_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x2_t = vld2_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x2_t = vld2_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x2_t = vld2_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x2_t = vld2_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x2_t = vld2_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x2_t = vld2_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x2_t = vld2_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x2_t = vld2_f32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x2_t = vld2_p16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x2_t = vld2_p8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x2_t = vld2_s16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x2_t = vld2_s32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x2_t = vld2_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x2_t = vld2_s8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x2_t = vld2_u16 (0); + } + +-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x2_t = vld2_u32 (0); + } + +-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x2_t = vld2_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x2_t = vld2_u8 (0); + } + +-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_float32x4x3_t = vld3q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_poly16x8x3_t = vld3q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_poly8x16x3_t = vld3q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int16x8x3_t = vld3q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int32x4x3_t = vld3q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int8x16x3_t = vld3q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint16x8x3_t = vld3q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint32x4x3_t = vld3q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint8x16x3_t = vld3q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x3_t = vld3_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x3_t = vld3_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x3_t = vld3_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x3_t = vld3_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x3_t = vld3_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x3_t = vld3_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x3_t = vld3_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x3_t = vld3_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x3_t = vld3_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x3_t = vld3_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x3_t = vld3_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x3_t = vld3_f32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x3_t = vld3_p16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x3_t = vld3_p8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x3_t = vld3_s16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x3_t = vld3_s32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x3_t = vld3_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x3_t = vld3_s8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x3_t = vld3_u16 (0); + } + +-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x3_t = vld3_u32 (0); + } + +-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x3_t = vld3_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x3_t = vld3_u8 (0); + } + +-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_float32x4x4_t = vld4q_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_poly16x8x4_t = vld4q_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_poly8x16x4_t = vld4q_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int16x8x4_t = vld4q_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int32x4x4_t = vld4q_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_int8x16x4_t = vld4q_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint16x8x4_t = vld4q_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint32x4x4_t = vld4q_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-05-03 15:14:56 +0000 +@@ -15,6 +15,6 @@ + out_uint8x16x4_t = vld4q_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x4_t = vld4_dup_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x4_t = vld4_dup_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x4_t = vld4_dup_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x4_t = vld4_dup_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x4_t = vld4_dup_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x4_t = vld4_dup_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x4_t = vld4_dup_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x4_t = vld4_dup_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x4_t = vld4_dup_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x4_t = vld4_dup_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x4_t = vld4_dup_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_float32x2x4_t = vld4_f32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly16x4x4_t = vld4_p16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_poly8x8x4_t = vld4_p8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int16x4x4_t = vld4_s16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int32x2x4_t = vld4_s32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int64x1x4_t = vld4_s64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_int8x8x4_t = vld4_s8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint16x4x4_t = vld4_u16 (0); + } + +-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint32x2x4_t = vld4_u32 (0); + } + +-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint64x1x4_t = vld4_u64 (0); + } + +-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-05-03 15:14:56 +0000 +@@ -15,5 +15,5 @@ + out_uint8x8x4_t = vld4_u8 (0); + } + +-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_f32 (arg0_float32_t, arg1_float32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_s16 (arg0_int16_t, arg1_int16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_s32 (arg0_int32_t, arg1_int32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_s64 (arg0_int64_t, arg1_int64x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_s8 (arg0_int8_t, arg1_int8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_f32 (arg0_float32_t, arg1_float32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_s16 (arg0_int16_t, arg1_int16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_s32 (arg0_int32_t, arg1_int32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_s64 (arg0_int64_t, arg1_int64x1_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_s8 (arg0_int8_t, arg1_int8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); + } + +-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); + } + +-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); + } + +-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-05-03 15:14:56 +0000 +@@ -16,6 +16,6 @@ + vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); + } + +-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c' +--- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-05-24 18:36:31 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-05-03 15:14:56 +0000 +@@ -16,5 +16,5 @@ + vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); + } + +-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ ++/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ + /* { dg-final { cleanup-saved-temps } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/pr46329.c' +--- old/gcc/testsuite/gcc.target/arm/pr46329.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/pr46329.c 2011-05-03 15:18:07 +0000 +@@ -0,0 +1,9 @@ ++/* { dg-options "-O2" } */ ++/* { dg-add-options arm_neon } */ ++ ++int __attribute__ ((vector_size (32))) x; ++void ++foo (void) ++{ ++ x <<= x; ++} + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch new file mode 100644 index 0000000000..aba2a497e7 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106743.patch @@ -0,0 +1,25 @@ +2011-04-26 Andrew Stubbs + + Backport from FSF: + + 2011-04-05 Tom de Vries + + PR target/43920 + gcc/ + * config/arm/arm.h (BRANCH_COST): Set to 1 for Thumb-2 when optimizing + for size. + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2011-05-03 15:17:25 +0000 ++++ new/gcc/config/arm/arm.h 2011-04-26 14:42:21 +0000 +@@ -2018,7 +2018,8 @@ + /* Try to generate sequences that don't involve branches, we can then use + conditional instructions */ + #define BRANCH_COST(speed_p, predictable_p) \ +- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) ++ (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \ ++ : (optimize > 0 ? 2 : 0)) + + /* Position Independent Code. */ + /* We decide which register to use based on the compilation options and + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch new file mode 100644 index 0000000000..004f0131cf --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106744.patch @@ -0,0 +1,21 @@ +2011-05-06 Richard Sandiford + + gcc/ + From Sergey Grechanik , approved for mainline + + * config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS + for constant vectors. + +=== modified file 'gcc/config/arm/arm.c' +--- old/gcc/config/arm/arm.c 2011-05-03 15:18:07 +0000 ++++ new/gcc/config/arm/arm.c 2011-05-06 11:33:02 +0000 +@@ -9193,7 +9193,7 @@ + /* The neon move patterns handle all legitimate vector and struct + addresses. */ + if (TARGET_NEON +- && MEM_P (x) ++ && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR) + && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT + || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + || VALID_NEON_STRUCT_MODE (mode))) + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch new file mode 100644 index 0000000000..ce0272431d --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106746.patch @@ -0,0 +1,24 @@ +2011-05-12 Michael Hope + + gcc/ + Backport from mainline: + + 2011-05-05 Michael Hope + + PR pch/45979 + * config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for + __ARM_EABI__ hosts. + +=== modified file 'gcc/config/host-linux.c' +--- old/gcc/config/host-linux.c 2010-11-29 14:09:41 +0000 ++++ new/gcc/config/host-linux.c 2011-05-06 20:19:30 +0000 +@@ -84,6 +84,8 @@ + # define TRY_EMPTY_VM_SPACE 0x60000000 + #elif defined(__mc68000__) + # define TRY_EMPTY_VM_SPACE 0x40000000 ++#elif defined(__ARM_EABI__) ++# define TRY_EMPTY_VM_SPACE 0x60000000 + #else + # define TRY_EMPTY_VM_SPACE 0 + #endif + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch new file mode 100644 index 0000000000..7885b7af49 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106747.patch @@ -0,0 +1,640 @@ +2011-05-13 Revital Eres + + gcc/ + * loop-doloop.c (doloop_condition_get): Support new form of + doloop pattern and use prev_nondebug_insn instead of PREV_INSN. + * config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*". + (doloop_end): New. + * config/arm/arm.md (*addsi3_compare0): Remove "*". + * params.def (sms-min-sc): New param flag. + * doc/invoke.texi (sms-min-sc): Document it. + * ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge + enters the branch create an anti edge in the opposite direction + to prevent the creation of reg-moves. + * modulo-sched.c: Adjust comment to reflect the fact we are + scheduling closing branch. + (PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine. + (stage_count): New field in struct partial_schedule. + (calculate_stage_count): New function. + (normalize_sched_times): Rename to reset_sched_times and handle + incrementing the sched time of the nodes by a constant value + passed as parameter. + (duplicate_insns_of_cycles): Skip closing branch. + (sms_schedule_by_order): Schedule closing branch. + (ps_insn_find_column): Handle closing branch. + (sms_schedule): Call reset_sched_times and adjust the code to + support scheduling of the closing branch. Use sms-min-sc. + Support new form of doloop pattern. + (ps_insert_empty_row): Update calls to normalize_sched_times + and rotate_partial_schedule functions. + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2011-05-06 11:28:27 +0000 ++++ new/gcc/config/arm/arm.md 2011-05-13 13:42:39 +0000 +@@ -791,7 +791,7 @@ + "" + ) + +-(define_insn "*addsi3_compare0" ++(define_insn "addsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV + (plus:SI (match_operand:SI 1 "s_register_operand" "r, r") + +=== modified file 'gcc/config/arm/thumb2.md' +--- old/gcc/config/arm/thumb2.md 2011-01-03 20:52:22 +0000 ++++ new/gcc/config/arm/thumb2.md 2011-05-11 07:15:47 +0000 +@@ -836,7 +836,7 @@ + "operands[4] = GEN_INT (- INTVAL (operands[2]));" + ) + +-(define_insn "*thumb2_addsi3_compare0" ++(define_insn "thumb2_addsi3_compare0" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV + (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") +@@ -1118,3 +1118,54 @@ + " + operands[2] = GEN_INT (32 - INTVAL (operands[2])); + ") ++ ++;; Define the subtract-one-and-jump insns so loop.c ++;; knows what to generate. ++(define_expand "doloop_end" ++ [(use (match_operand 0 "" "")) ; loop pseudo ++ (use (match_operand 1 "" "")) ; iterations; zero if unknown ++ (use (match_operand 2 "" "")) ; max iterations ++ (use (match_operand 3 "" "")) ; loop level ++ (use (match_operand 4 "" ""))] ; label ++ "TARGET_32BIT" ++ " ++ { ++ /* Currently SMS relies on the do-loop pattern to recognize loops ++ where (1) the control part consists of all insns defining and/or ++ using a certain 'count' register and (2) the loop count can be ++ adjusted by modifying this register prior to the loop. ++ ??? The possible introduction of a new block to initialize the ++ new IV can potentially affect branch optimizations. */ ++ if (optimize > 0 && flag_modulo_sched) ++ { ++ rtx s0; ++ rtx bcomp; ++ rtx loc_ref; ++ rtx cc_reg; ++ rtx insn; ++ rtx cmp; ++ ++ /* Only use this on innermost loops. */ ++ if (INTVAL (operands[3]) > 1) ++ FAIL; ++ if (GET_MODE (operands[0]) != SImode) ++ FAIL; ++ ++ s0 = operands [0]; ++ if (TARGET_THUMB2) ++ insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1))); ++ else ++ insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1))); ++ ++ cmp = XVECEXP (PATTERN (insn), 0, 0); ++ cc_reg = SET_DEST (cmp); ++ bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx); ++ loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]); ++ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, ++ gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp, ++ loc_ref, pc_rtx))); ++ DONE; ++ }else ++ FAIL; ++}") ++ + +=== modified file 'gcc/ddg.c' +--- old/gcc/ddg.c 2010-11-30 11:41:24 +0000 ++++ new/gcc/ddg.c 2011-05-11 07:15:47 +0000 +@@ -197,6 +197,11 @@ + } + } + ++ /* If a true dep edge enters the branch create an anti edge in the ++ opposite direction to prevent the creation of reg-moves. */ ++ if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn)) ++ create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1); ++ + latency = dep_cost (link); + e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance); + add_edge_to_ddg (g, e); + +=== modified file 'gcc/doc/invoke.texi' +--- old/gcc/doc/invoke.texi 2011-04-18 11:31:29 +0000 ++++ new/gcc/doc/invoke.texi 2011-05-11 07:15:47 +0000 +@@ -8730,6 +8730,10 @@ + The maximum number of best instructions in the ready list that are considered + for renaming in the selective scheduler. The default value is 2. + ++@item sms-min-sc ++The minimum value of stage count that swing modulo scheduler will ++generate. The default value is 2. ++ + @item max-last-value-rtl + The maximum size measured as number of RTLs that can be recorded in an expression + in combiner for a pseudo register as last known value of that register. The default + +=== modified file 'gcc/loop-doloop.c' +--- old/gcc/loop-doloop.c 2010-11-30 11:41:24 +0000 ++++ new/gcc/loop-doloop.c 2011-05-11 07:15:47 +0000 +@@ -78,6 +78,8 @@ + rtx inc_src; + rtx condition; + rtx pattern; ++ rtx cc_reg = NULL_RTX; ++ rtx reg_orig = NULL_RTX; + + /* The canonical doloop pattern we expect has one of the following + forms: +@@ -96,7 +98,16 @@ + 2) (set (reg) (plus (reg) (const_int -1)) + (set (pc) (if_then_else (reg != 0) + (label_ref (label)) +- (pc))). */ ++ (pc))). ++ ++ Some targets (ARM) do the comparison before the branch, as in the ++ following form: ++ ++ 3) (parallel [(set (cc) (compare ((plus (reg) (const_int -1), 0))) ++ (set (reg) (plus (reg) (const_int -1)))]) ++ (set (pc) (if_then_else (cc == NE) ++ (label_ref (label)) ++ (pc))) */ + + pattern = PATTERN (doloop_pat); + +@@ -104,19 +115,47 @@ + { + rtx cond; + rtx prev_insn = prev_nondebug_insn (doloop_pat); ++ rtx cmp_arg1, cmp_arg2; ++ rtx cmp_orig; + +- /* We expect the decrement to immediately precede the branch. */ ++ /* In case the pattern is not PARALLEL we expect two forms ++ of doloop which are cases 2) and 3) above: in case 2) the ++ decrement immediately precedes the branch, while in case 3) ++ the compare and decrement instructions immediately precede ++ the branch. */ + + if (prev_insn == NULL_RTX || !INSN_P (prev_insn)) + return 0; + + cmp = pattern; +- inc = PATTERN (PREV_INSN (doloop_pat)); ++ if (GET_CODE (PATTERN (prev_insn)) == PARALLEL) ++ { ++ /* The third case: the compare and decrement instructions ++ immediately precede the branch. */ ++ cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0); ++ if (GET_CODE (cmp_orig) != SET) ++ return 0; ++ if (GET_CODE (SET_SRC (cmp_orig)) != COMPARE) ++ return 0; ++ cmp_arg1 = XEXP (SET_SRC (cmp_orig), 0); ++ cmp_arg2 = XEXP (SET_SRC (cmp_orig), 1); ++ if (cmp_arg2 != const0_rtx ++ || GET_CODE (cmp_arg1) != PLUS) ++ return 0; ++ reg_orig = XEXP (cmp_arg1, 0); ++ if (XEXP (cmp_arg1, 1) != GEN_INT (-1) ++ || !REG_P (reg_orig)) ++ return 0; ++ cc_reg = SET_DEST (cmp_orig); ++ ++ inc = XVECEXP (PATTERN (prev_insn), 0, 1); ++ } ++ else ++ inc = PATTERN (prev_insn); + /* We expect the condition to be of the form (reg != 0) */ + cond = XEXP (SET_SRC (cmp), 0); + if (GET_CODE (cond) != NE || XEXP (cond, 1) != const0_rtx) + return 0; +- + } + else + { +@@ -162,11 +201,15 @@ + return 0; + + if ((XEXP (condition, 0) == reg) ++ /* For the third case: */ ++ || ((cc_reg != NULL_RTX) ++ && (XEXP (condition, 0) == cc_reg) ++ && (reg_orig == reg)) + || (GET_CODE (XEXP (condition, 0)) == PLUS +- && XEXP (XEXP (condition, 0), 0) == reg)) ++ && XEXP (XEXP (condition, 0), 0) == reg)) + { + if (GET_CODE (pattern) != PARALLEL) +- /* The second form we expect: ++ /* For the second form we expect: + + (set (reg) (plus (reg) (const_int -1)) + (set (pc) (if_then_else (reg != 0) +@@ -181,7 +224,24 @@ + (set (reg) (plus (reg) (const_int -1))) + (additional clobbers and uses)]) + +- So we return that form instead. ++ For the third form we expect: ++ ++ (parallel [(set (cc) (compare ((plus (reg) (const_int -1)), 0)) ++ (set (reg) (plus (reg) (const_int -1)))]) ++ (set (pc) (if_then_else (cc == NE) ++ (label_ref (label)) ++ (pc))) ++ ++ which is equivalent to the following: ++ ++ (parallel [(set (cc) (compare (reg, 1)) ++ (set (reg) (plus (reg) (const_int -1))) ++ (set (pc) (if_then_else (NE == cc) ++ (label_ref (label)) ++ (pc))))]) ++ ++ So we return the second form instead for the two cases. ++ + */ + condition = gen_rtx_fmt_ee (NE, VOIDmode, inc_src, const1_rtx); + + +=== modified file 'gcc/modulo-sched.c' +--- old/gcc/modulo-sched.c 2011-02-14 17:59:10 +0000 ++++ new/gcc/modulo-sched.c 2011-05-11 07:15:47 +0000 +@@ -84,14 +84,13 @@ + II cycles (i.e. use register copies to prevent a def from overwriting + itself before reaching the use). + +- SMS works with countable loops (1) whose control part can be easily +- decoupled from the rest of the loop and (2) whose loop count can +- be easily adjusted. This is because we peel a constant number of +- iterations into a prologue and epilogue for which we want to avoid +- emitting the control part, and a kernel which is to iterate that +- constant number of iterations less than the original loop. So the +- control part should be a set of insns clearly identified and having +- its own iv, not otherwise used in the loop (at-least for now), which ++ SMS works with countable loops whose loop count can be easily ++ adjusted. This is because we peel a constant number of iterations ++ into a prologue and epilogue for which we want to avoid emitting ++ the control part, and a kernel which is to iterate that constant ++ number of iterations less than the original loop. So the control ++ part should be a set of insns clearly identified and having its ++ own iv, not otherwise used in the loop (at-least for now), which + initializes a register before the loop to the number of iterations. + Currently SMS relies on the do-loop pattern to recognize such loops, + where (1) the control part comprises of all insns defining and/or +@@ -116,8 +115,10 @@ + + /* The number of different iterations the nodes in ps span, assuming + the stage boundaries are placed efficiently. */ +-#define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \ +- + 1 + (ps)->ii - 1) / (ps)->ii) ++#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \ ++ + 1 + ii - 1) / ii) ++/* The stage count of ps. */ ++#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count) + + /* A single instruction in the partial schedule. */ + struct ps_insn +@@ -155,6 +156,8 @@ + int max_cycle; + + ddg_ptr g; /* The DDG of the insns in the partial schedule. */ ++ ++ int stage_count; /* The stage count of the partial schedule. */ + }; + + /* We use this to record all the register replacements we do in +@@ -195,7 +198,7 @@ + rtx, rtx); + static void duplicate_insns_of_cycles (partial_schedule_ptr, + int, int, int, rtx); +- ++static int calculate_stage_count (partial_schedule_ptr ps); + #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap) + #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time) + #define SCHED_FIRST_REG_MOVE(x) \ +@@ -310,10 +313,10 @@ + either a single (parallel) branch-on-count or a (non-parallel) + branch immediately preceded by a single (decrement) insn. */ + first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail +- : PREV_INSN (tail)); ++ : prev_nondebug_insn (tail)); + + for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn)) +- if (reg_mentioned_p (reg, insn)) ++ if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn)) + { + if (dump_file) + { +@@ -569,13 +572,12 @@ + } + } + +-/* Bump the SCHED_TIMEs of all nodes to start from zero. Set the values +- of SCHED_ROW and SCHED_STAGE. */ ++/* Bump the SCHED_TIMEs of all nodes by AMOUNT. Set the values of ++ SCHED_ROW and SCHED_STAGE. */ + static void +-normalize_sched_times (partial_schedule_ptr ps) ++reset_sched_times (partial_schedule_ptr ps, int amount) + { + int row; +- int amount = PS_MIN_CYCLE (ps); + int ii = ps->ii; + ps_insn_ptr crr_insn; + +@@ -584,19 +586,43 @@ + { + ddg_node_ptr u = crr_insn->node; + int normalized_time = SCHED_TIME (u) - amount; ++ int new_min_cycle = PS_MIN_CYCLE (ps) - amount; ++ int sc_until_cycle_zero, stage; + +- if (dump_file) +- fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\ +- min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME +- (u), ps->min_cycle); ++ if (dump_file) ++ { ++ /* Print the scheduling times after the rotation. */ ++ fprintf (dump_file, "crr_insn->node=%d (insn id %d), " ++ "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid, ++ INSN_UID (crr_insn->node->insn), SCHED_TIME (u), ++ normalized_time); ++ if (JUMP_P (crr_insn->node->insn)) ++ fprintf (dump_file, " (branch)"); ++ fprintf (dump_file, "\n"); ++ } ++ + gcc_assert (SCHED_TIME (u) >= ps->min_cycle); + gcc_assert (SCHED_TIME (u) <= ps->max_cycle); + SCHED_TIME (u) = normalized_time; +- SCHED_ROW (u) = normalized_time % ii; +- SCHED_STAGE (u) = normalized_time / ii; ++ SCHED_ROW (u) = SMODULO (normalized_time, ii); ++ ++ /* The calculation of stage count is done adding the number ++ of stages before cycle zero and after cycle zero. */ ++ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii); ++ ++ if (SCHED_TIME (u) < 0) ++ { ++ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii); ++ SCHED_STAGE (u) = sc_until_cycle_zero - stage; ++ } ++ else ++ { ++ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii); ++ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1; ++ } + } + } +- ++ + /* Set SCHED_COLUMN of each node according to its position in PS. */ + static void + set_columns_for_ps (partial_schedule_ptr ps) +@@ -646,9 +672,12 @@ + + /* Do not duplicate any insn which refers to count_reg as it + belongs to the control part. ++ The closing branch is scheduled as well and thus should ++ be ignored. + TODO: This should be done by analyzing the control part of + the loop. */ +- if (reg_mentioned_p (count_reg, u_node->insn)) ++ if (reg_mentioned_p (count_reg, u_node->insn) ++ || JUMP_P (ps_ij->node->insn)) + continue; + + if (for_prolog) +@@ -1009,9 +1038,11 @@ + continue; + } + +- /* Don't handle BBs with calls or barriers, or !single_set insns, +- or auto-increment insns (to avoid creating invalid reg-moves +- for the auto-increment insns). ++ /* Don't handle BBs with calls or barriers or auto-increment insns ++ (to avoid creating invalid reg-moves for the auto-increment insns), ++ or !single_set with the exception of instructions that include ++ count_reg---these instructions are part of the control part ++ that do-loop recognizes. + ??? Should handle auto-increment insns. + ??? Should handle insns defining subregs. */ + for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn)) +@@ -1021,7 +1052,8 @@ + if (CALL_P (insn) + || BARRIER_P (insn) + || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn) +- && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE) ++ && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE ++ && !reg_mentioned_p (count_reg, insn)) + || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0) + || (INSN_P (insn) && (set = single_set (insn)) + && GET_CODE (SET_DEST (set)) == SUBREG)) +@@ -1049,7 +1081,11 @@ + continue; + } + +- if (! (g = create_ddg (bb, 0))) ++ /* Always schedule the closing branch with the rest of the ++ instructions. The branch is rotated to be in row ii-1 at the ++ end of the scheduling procedure to make sure it's the last ++ instruction in the iteration. */ ++ if (! (g = create_ddg (bb, 1))) + { + if (dump_file) + fprintf (dump_file, "SMS create_ddg failed\n"); +@@ -1157,14 +1193,17 @@ + + ps = sms_schedule_by_order (g, mii, maxii, node_order); + +- if (ps){ +- stage_count = PS_STAGE_COUNT (ps); +- gcc_assert(stage_count >= 1); +- } ++ if (ps) ++ { ++ stage_count = calculate_stage_count (ps); ++ gcc_assert(stage_count >= 1); ++ PS_STAGE_COUNT(ps) = stage_count; ++ } + +- /* Stage count of 1 means that there is no interleaving between +- iterations, let the scheduling passes do the job. */ +- if (stage_count <= 1 ++ /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of ++ 1 means that there is no interleaving between iterations thus ++ we let the scheduling passes do the job in this case. */ ++ if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC) + || (count_init && (loop_count <= stage_count)) + || (flag_branch_probabilities && (trip_count <= stage_count))) + { +@@ -1182,32 +1221,24 @@ + else + { + struct undo_replace_buff_elem *reg_move_replaces; +- +- if (dump_file) +- { ++ int amount = SCHED_TIME (g->closing_branch) + 1; ++ ++ /* Set the stage boundaries. The closing_branch was scheduled ++ and should appear in the last (ii-1) row. */ ++ reset_sched_times (ps, amount); ++ rotate_partial_schedule (ps, amount); ++ set_columns_for_ps (ps); ++ ++ canon_loop (loop); ++ ++ if (dump_file) ++ { + fprintf (dump_file, + "SMS succeeded %d %d (with ii, sc)\n", ps->ii, + stage_count); + print_partial_schedule (ps, dump_file); +- fprintf (dump_file, +- "SMS Branch (%d) will later be scheduled at cycle %d.\n", +- g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1); + } +- +- /* Set the stage boundaries. If the DDG is built with closing_branch_deps, +- the closing_branch was scheduled and should appear in the last (ii-1) +- row. Otherwise, we are free to schedule the branch, and we let nodes +- that were scheduled at the first PS_MIN_CYCLE cycle appear in the first +- row; this should reduce stage_count to minimum. +- TODO: Revisit the issue of scheduling the insns of the +- control part relative to the branch when the control part +- has more than one insn. */ +- normalize_sched_times (ps); +- rotate_partial_schedule (ps, PS_MIN_CYCLE (ps)); +- set_columns_for_ps (ps); +- +- canon_loop (loop); +- ++ + /* case the BCT count is not known , Do loop-versioning */ + if (count_reg && ! count_init) + { +@@ -1760,12 +1791,6 @@ + continue; + } + +- if (JUMP_P (insn)) /* Closing branch handled later. */ +- { +- RESET_BIT (tobe_scheduled, u); +- continue; +- } +- + if (TEST_BIT (sched_nodes, u)) + continue; + +@@ -1893,8 +1918,8 @@ + if (dump_file) + fprintf (dump_file, "split_row=%d\n", split_row); + +- normalize_sched_times (ps); +- rotate_partial_schedule (ps, ps->min_cycle); ++ reset_sched_times (ps, PS_MIN_CYCLE (ps)); ++ rotate_partial_schedule (ps, PS_MIN_CYCLE (ps)); + + rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr)); + for (row = 0; row < split_row; row++) +@@ -2571,6 +2596,7 @@ + ps_insn_ptr next_ps_i; + ps_insn_ptr first_must_follow = NULL; + ps_insn_ptr last_must_precede = NULL; ++ ps_insn_ptr last_in_row = NULL; + int row; + + if (! ps_i) +@@ -2597,8 +2623,37 @@ + else + last_must_precede = next_ps_i; + } ++ /* The closing branch must be the last in the row. */ ++ if (must_precede ++ && TEST_BIT (must_precede, next_ps_i->node->cuid) ++ && JUMP_P (next_ps_i->node->insn)) ++ return false; ++ ++ last_in_row = next_ps_i; + } + ++ /* The closing branch is scheduled as well. Make sure there is no ++ dependent instruction after it as the branch should be the last ++ instruction in the row. */ ++ if (JUMP_P (ps_i->node->insn)) ++ { ++ if (first_must_follow) ++ return false; ++ if (last_in_row) ++ { ++ /* Make the branch the last in the row. New instructions ++ will be inserted at the beginning of the row or after the ++ last must_precede instruction thus the branch is guaranteed ++ to remain the last instruction in the row. */ ++ last_in_row->next_in_row = ps_i; ++ ps_i->prev_in_row = last_in_row; ++ ps_i->next_in_row = NULL; ++ } ++ else ++ ps->rows[row] = ps_i; ++ return true; ++ } ++ + /* Now insert the node after INSERT_AFTER_PSI. */ + + if (! last_must_precede) +@@ -2820,6 +2875,24 @@ + return ps_i; + } + ++/* Calculate the stage count of the partial schedule PS. The calculation ++ takes into account the rotation to bring the closing branch to row ++ ii-1. */ ++int ++calculate_stage_count (partial_schedule_ptr ps) ++{ ++ int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1; ++ int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount; ++ int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount; ++ int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii); ++ ++ /* The calculation of stage count is done adding the number of stages ++ before cycle zero and after cycle zero. */ ++ stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii); ++ ++ return stage_count; ++} ++ + /* Rotate the rows of PS such that insns scheduled at time + START_CYCLE will appear in row 0. Updates max/min_cycles. */ + void + +=== modified file 'gcc/params.def' +--- old/gcc/params.def 2011-04-18 11:31:29 +0000 ++++ new/gcc/params.def 2011-05-11 07:15:47 +0000 +@@ -344,6 +344,11 @@ + "sms-max-ii-factor", + "A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop", + 100, 0, 0) ++/* The minimum value of stage count that swing modulo scheduler will generate. */ ++DEFPARAM(PARAM_SMS_MIN_SC, ++ "sms-min-sc", ++ "The minimum value of stage count that swing modulo scheduler will generate.", ++ 2, 1, 1) + DEFPARAM(PARAM_SMS_DFA_HISTORY, + "sms-dfa-history", + "The number of cycles the swing modulo scheduler considers when checking conflicts using DFA", + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch new file mode 100644 index 0000000000..9c62102db5 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106750.patch @@ -0,0 +1,30 @@ + 2011-05-13 Revital Eres + + gcc/ + * ddg.c (free_ddg_all_sccs): Free sccs field in struct ddg_all_sccs. + * modulo-sched.c (sms_schedule): Avoid unfreed memory when SMS fails. + +=== modified file 'gcc/ddg.c' +--- old/gcc/ddg.c 2011-05-11 07:15:47 +0000 ++++ new/gcc/ddg.c 2011-05-13 16:03:40 +0000 +@@ -1016,6 +1016,7 @@ + for (i = 0; i < all_sccs->num_sccs; i++) + free_scc (all_sccs->sccs[i]); + ++ free (all_sccs->sccs); + free (all_sccs); + } + + +=== modified file 'gcc/modulo-sched.c' +--- old/gcc/modulo-sched.c 2011-05-11 07:15:47 +0000 ++++ new/gcc/modulo-sched.c 2011-05-13 16:03:40 +0000 +@@ -1216,7 +1216,6 @@ + fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count); + fprintf (dump_file, ")\n"); + } +- continue; + } + else + { + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch new file mode 100644 index 0000000000..c26ee5bde4 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106751.patch @@ -0,0 +1,134 @@ +2011-06-02 Chung-Lin Tang + + Backport from mainline: + + 2011-03-21 Chung-Lin Tang + + gcc/ + * simplify-rtx.c (simplify_binary_operation_1): Handle + (xor (and A B) C) case when B and C are both constants. + + gcc/testsuite/ + * gcc.target/arm/xor-and.c: New. + + 2011-03-18 Chung-Lin Tang + + gcc/ + * combine.c (try_combine): Do simplification only call of + subst() on i2 even when i1 is present. Update comments. + + gcc/testsuite/ + * gcc.target/arm/unsigned-extend-1.c: New. + +=== modified file 'gcc/combine.c' +--- old/gcc/combine.c 2011-05-06 11:28:27 +0000 ++++ new/gcc/combine.c 2011-05-27 14:31:18 +0000 +@@ -3089,7 +3089,7 @@ + /* It is possible that the source of I2 or I1 may be performing + an unneeded operation, such as a ZERO_EXTEND of something + that is known to have the high part zero. Handle that case +- by letting subst look at the innermost one of them. ++ by letting subst look at the inner insns. + + Another way to do this would be to have a function that tries + to simplify a single insn instead of merging two or more +@@ -3114,11 +3114,9 @@ + subst_low_luid = DF_INSN_LUID (i1); + i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); + } +- else +- { +- subst_low_luid = DF_INSN_LUID (i2); +- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); +- } ++ ++ subst_low_luid = DF_INSN_LUID (i2); ++ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); + } + + n_occurrences = 0; /* `subst' counts here */ + +=== modified file 'gcc/simplify-rtx.c' +--- old/gcc/simplify-rtx.c 2011-03-26 09:24:06 +0000 ++++ new/gcc/simplify-rtx.c 2011-05-27 14:31:18 +0000 +@@ -2484,6 +2484,46 @@ + XEXP (op0, 1), mode), + op1); + ++ /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P), ++ we can transform like this: ++ (A&B)^C == ~(A&B)&C | ~C&(A&B) ++ == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law ++ == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order ++ Attempt a few simplifications when B and C are both constants. */ ++ if (GET_CODE (op0) == AND ++ && CONST_INT_P (op1) ++ && CONST_INT_P (XEXP (op0, 1))) ++ { ++ rtx a = XEXP (op0, 0); ++ rtx b = XEXP (op0, 1); ++ rtx c = op1; ++ HOST_WIDE_INT bval = INTVAL (b); ++ HOST_WIDE_INT cval = INTVAL (c); ++ ++ rtx na_c ++ = simplify_binary_operation (AND, mode, ++ simplify_gen_unary (NOT, mode, a, mode), ++ c); ++ if ((~cval & bval) == 0) ++ { ++ /* Try to simplify ~A&C | ~B&C. */ ++ if (na_c != NULL_RTX) ++ return simplify_gen_binary (IOR, mode, na_c, ++ GEN_INT (~bval & cval)); ++ } ++ else ++ { ++ /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */ ++ if (na_c == const0_rtx) ++ { ++ rtx a_nc_b = simplify_gen_binary (AND, mode, a, ++ GEN_INT (~cval & bval)); ++ return simplify_gen_binary (IOR, mode, a_nc_b, ++ GEN_INT (~bval & cval)); ++ } ++ } ++ } ++ + /* (xor (comparison foo bar) (const_int 1)) can become the reversed + comparison if STORE_FLAG_VALUE is 1. */ + if (STORE_FLAG_VALUE == 1 + +=== added file 'gcc/testsuite/gcc.target/arm/unsigned-extend-1.c' +--- old/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 2011-05-27 14:31:18 +0000 +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv6" } */ ++ ++unsigned char foo (unsigned char c) ++{ ++ return (c >= '0') && (c <= '9'); ++} ++ ++/* { dg-final { scan-assembler-not "uxtb" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/xor-and.c' +--- old/gcc/testsuite/gcc.target/arm/xor-and.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/xor-and.c 2011-05-27 14:31:18 +0000 +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O -march=armv6" } */ ++ ++unsigned short foo (unsigned short x) ++{ ++ x ^= 0x4002; ++ x >>= 1; ++ x |= 0x8000; ++ return x; ++} ++ ++/* { dg-final { scan-assembler "orr" } } */ ++/* { dg-final { scan-assembler-not "mvn" } } */ ++/* { dg-final { scan-assembler-not "uxth" } } */ + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch new file mode 100644 index 0000000000..bda39e8faa --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106753.patch @@ -0,0 +1,5027 @@ +2001-06-02 Richard Sandiford + + gcc/ + * gimple.c (gimple_build_call_internal_1): Add missing call to + gimple_call_reset_alias_info. + +2001-06-02 Richard Sandiford + + gcc/testsuite/ + Backport from mainline: + + 2011-05-03 Richard Sandiford + + * gcc.dg/vect/vect-strided-u16-i3.c: New test. + +2001-06-02 Richard Sandiford + + gcc/testsuite/ + Backport from mainline: + + 2011-05-03 Richard Sandiford + + * lib/target-supports.exp (check_effective_target_vect_strided): + Replace with... + (check_effective_target_vect_strided2) + (check_effective_target_vect_strided3) + (check_effective_target_vect_strided4) + (check_effective_target_vect_strided8): ...these new functions. + + * gcc.dg/vect/O3-pr39675-2.c: Update accordingly. + * gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c: Likewise. + * gcc.dg/vect/fast-math-slp-27.c: Likewise. + * gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: Likewise. + * gcc.dg/vect/pr37539.c: Likewise. + * gcc.dg/vect/slp-11a.c: Likewise. + * gcc.dg/vect/slp-11b.c: Likewise. + * gcc.dg/vect/slp-11c.c: Likewise. + * gcc.dg/vect/slp-12a.c: Likewise. + * gcc.dg/vect/slp-12b.c: Likewise. + * gcc.dg/vect/slp-18.c: Likewise. + * gcc.dg/vect/slp-19a.c: Likewise. + * gcc.dg/vect/slp-19b.c: Likewise. + * gcc.dg/vect/slp-21.c: Likewise. + * gcc.dg/vect/slp-23.c: Likewise. + * gcc.dg/vect/vect-cselim-1.c: Likewise. + + * gcc.dg/vect/fast-math-vect-complex-3.c: Use vect_stridedN + instead of vect_interleave && vect_extract_even_odd. + * gcc.dg/vect/no-scevccp-outer-10a.c: Likewise. + * gcc.dg/vect/no-scevccp-outer-10b.c: Likewise. + * gcc.dg/vect/no-scevccp-outer-20.c: Likewise. + * gcc.dg/vect/vect-1.c: Likewise. + * gcc.dg/vect/vect-10.c: Likewise. + * gcc.dg/vect/vect-98.c: Likewise. + * gcc.dg/vect/vect-107.c: Likewise. + * gcc.dg/vect/vect-strided-a-mult.c: Likewise. + * gcc.dg/vect/vect-strided-a-u16-i2.c: Likewise. + * gcc.dg/vect/vect-strided-a-u16-i4.c: Likewise. + * gcc.dg/vect/vect-strided-a-u16-mult.c: Likewise. + * gcc.dg/vect/vect-strided-a-u32-mult.c: Likewise. + * gcc.dg/vect/vect-strided-a-u8-i2-gap.c: Likewise. + * gcc.dg/vect/vect-strided-a-u8-i8-gap2.c: Likewise. + * gcc.dg/vect/vect-strided-a-u8-i8-gap7.c: Likewise. + * gcc.dg/vect/vect-strided-float.c: Likewise. + * gcc.dg/vect/vect-strided-mult-char-ls.c: Likewise. + * gcc.dg/vect/vect-strided-mult.c: Likewise. + * gcc.dg/vect/vect-strided-same-dr.c: Likewise. + * gcc.dg/vect/vect-strided-u16-i2.c: Likewise. + * gcc.dg/vect/vect-strided-u16-i4.c: Likewise. + * gcc.dg/vect/vect-strided-u32-i4.c: Likewise. + * gcc.dg/vect/vect-strided-u32-i8.c: Likewise. + * gcc.dg/vect/vect-strided-u32-mult.c: Likewise. + * gcc.dg/vect/vect-strided-u8-i2-gap.c: Likewise. + * gcc.dg/vect/vect-strided-u8-i2.c: Likewise. + * gcc.dg/vect/vect-strided-u8-i8-gap2.c: Likewise. + * gcc.dg/vect/vect-strided-u8-i8-gap4.c: Likewise. + * gcc.dg/vect/vect-strided-u8-i8-gap7.c: Likewise. + * gcc.dg/vect/vect-strided-u8-i8.c: Likewise. + * gcc.dg/vect/vect-vfa-03.c: Likewise. + + * gcc.dg/vect/no-scevccp-outer-18.c: Add vect_stridedN to the + target condition. + * gcc.dg/vect/pr30843.c: Likewise. + * gcc.dg/vect/pr33866.c: Likewise. + * gcc.dg/vect/slp-reduc-6.c: Likewise. + * gcc.dg/vect/vect-strided-store-a-u8-i2.c: Likewise. + * gcc.dg/vect/vect-strided-store-u16-i4.c: Likewise. + * gcc.dg/vect/vect-strided-store-u32-i2.c: Likewise. + +2001-06-02 Richard Sandiford + + gcc/testsuite/ + Backport from mainline: + + 2011-05-03 Richard Sandiford + + * gcc.dg/vect/slp-11.c: Split into... + * gcc.dg/vect/slp-11a.c, gcc.dg/vect/slp-11b.c, + gcc.dg/vect/slp-11c.c: ...these tests. + * gcc.dg/vect/slp-12a.c: Split 4-stride loop into... + * gcc.dg/vect/slp-12c.c: ...this new test. + * gcc.dg/vect/slp-19.c: Split into... + * gcc.dg/vect/slp-19a.c, gcc.dg/vect/slp-19b.c, + gcc.dg/vect/slp-19c.c: ...these new tests. + +2001-06-02 Richard Sandiford + + gcc/testsuite/ + Backport from mainline: + + 2011-05-03 Richard Sandiford + + * lib/target-supports.exp + (check_effective_target_vect_extract_even_odd_wide): Delete. + (check_effective_target_vect_strided_wide): Likewise. + * gcc.dg/vect/O3-pr39675-2.c: Use the non-wide versions instead. + * gcc.dg/vect/fast-math-pr35982.c: Likewise. + * gcc.dg/vect/fast-math-vect-complex-3.c: Likewise. + * gcc.dg/vect/pr37539.c: Likewise. + * gcc.dg/vect/slp-11.c: Likewise. + * gcc.dg/vect/slp-12a.c: Likewise. + * gcc.dg/vect/slp-12b.c: Likewise. + * gcc.dg/vect/slp-19.c: Likewise. + * gcc.dg/vect/slp-23.c: Likewise. + * gcc.dg/vect/vect-1.c: Likewise. + * gcc.dg/vect/vect-98.c: Likewise. + * gcc.dg/vect/vect-107.c: Likewise. + * gcc.dg/vect/vect-strided-float.c: Likewise. + +2001-06-02 Richard Sandiford + + gcc/testsuite/ + Backport from mainline: + + 2011-04-21 Richard Sandiford + + * gcc.dg/vect/vect.exp: Run the main tests twice, one with -flto + and once without. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainlie: + + 2011-05-03 Richard Sandiford + + * config/arm/neon.md (vec_load_lanes): New expanders, + (vec_store_lanes): Likewise. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-05-03 Richard Sandiford + + * doc/md.texi (vec_load_lanes, vec_store_lanes): Document. + * optabs.h (COI_vec_load_lanes, COI_vec_store_lanes): New + convert_optab_index values. + (vec_load_lanes_optab, vec_store_lanes_optab): New convert optabs. + * genopinit.c (optabs): Initialize the new optabs. + * internal-fn.def (LOAD_LANES, STORE_LANES): New internal functions. + * internal-fn.c (get_multi_vector_move, expand_LOAD_LANES) + (expand_STORE_LANES): New functions. + * tree.h (build_array_type_nelts): Declare. + * tree.c (build_array_type_nelts): New function. + * tree-vectorizer.h (vect_model_store_cost): Add a bool argument. + (vect_model_load_cost): Likewise. + (vect_store_lanes_supported, vect_load_lanes_supported) + (vect_record_strided_load_vectors): Declare. + * tree-vect-data-refs.c (vect_lanes_optab_supported_p) + (vect_store_lanes_supported, vect_load_lanes_supported): New functions. + (vect_transform_strided_load): Split out statement recording into... + (vect_record_strided_load_vectors): ...this new function. + * tree-vect-stmts.c (create_vector_array, read_vector_array) + (write_vector_array, create_array_ref): New functions. + (vect_model_store_cost): Add store_lanes_p argument. + (vect_model_load_cost): Add load_lanes_p argument. + (vectorizable_store): Try to use store-lanes functions for + interleaved stores. + (vectorizable_load): Likewise load-lanes and loads. + * tree-vect-slp.c (vect_get_and_check_slp_defs): Update call + to vect_model_store_cost. + (vect_build_slp_tree): Likewise vect_model_load_cost. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-04-20 Richard Sandiford + + * tree-vect-stmts.c (vectorizable_store): Only chain one related + statement per copy. + +2001-06-02 Richard Sandiford + + gcc/ + * tree-inline.c (estimate_num_insns): Likewise. + + Backport from mainline: + + 2011-04-20 Richard Sandiford + + * Makefile.in (INTERNAL_FN_DEF, INTERNAL_FN_H): Define. + (GIMPLE_H): Include $(INTERNAL_FN_H). + (OBJS-common): Add internal-fn.o. + (internal-fn.o): New rule. + * internal-fn.def: New file. + * internal-fn.h: Likewise. + * internal-fn.c: Likewise. + * gimple.h: Include internal-fn.h. + (GF_CALL_INTERNAL): New gf_mask. + (gimple_statement_call): Put fntype into a union with a new + internal_fn field. + (gimple_build_call_internal): Declare. + (gimple_build_call_internal_vec): Likewise. + (gimple_call_same_target_p): Likewise. + (gimple_call_internal_p): New function. + (gimple_call_internal_fn): Likewise. + (gimple_call_set_fn): Assert that the function is not internal. + (gimple_call_set_fndecl): Likewise. + (gimple_call_set_internal_fn): New function. + (gimple_call_addr_fndecl): Handle null functions. + (gimple_call_return_type): Likewise. + [---- Plus backport adjustments: + (GF_CALL_INTERNAL_FN_SHIFT): New macro. + (GF_CALL_INTERNAL_FN): New gf_mask. + ----] + * gimple.c (gimple_build_call_internal_1): New function. + (gimple_build_call_internal): Likewise. + (gimple_build_call_internal_vec): Likewise. + (gimple_call_same_target_p): Likewise. + (gimple_call_flags): Handle calls to internal functions. + (gimple_call_fnspec): New function. + (gimple_call_arg_flags, gimple_call_return_flags): Use it. + (gimple_has_side_effects): Handle null functions. + (gimple_rhs_has_side_effects): Likewise. + (gimple_call_copy_skip_args): Handle calls to internal functions. + * cfgexpand.c (expand_call_stmt): Likewise. + * expr.c (expand_expr_real_1): Assert that the call isn't internal. + * gimple-low.c (gimple_check_call_args): Handle calls to internal + functions. + * gimple-pretty-print.c (dump_gimple_call): Likewise. + * ipa-prop.c (ipa_analyze_call_uses): Handle null functions. + * tree-cfg.c (verify_gimple_call): Handle calls to internal functions. + (do_warn_unused_result): Likewise. + [---- Plus backport adjustments: + (verify_stmt): Likewise. + ----] + * tree-eh.c (same_handler_p): Use gimple_call_same_target_p. + * tree-ssa-ccp.c (ccp_fold_stmt): Handle calls to internal functions. + [---- Plus backport adjustments: + (fold_gimple_call): Likewise. + ----] + * tree-ssa-dom.c (hashable_expr): Use the gimple statement to record + the target of a call. + (initialize_hash_element): Update accordingly. + (hashable_expr_equal_p): Use gimple_call_same_target_p. + (iterative_hash_hashable_expr): Handle calls to internal functions. + (print_expr_hash_elt): Likewise. + * tree-ssa-pre.c (can_value_number_call): Likewise. + (eliminate): Handle null functions. + * tree-ssa-sccvn.c (visit_use): Handle calls to internal functions. + * tree-ssa-structalias.c (find_func_aliases): Likewise. + * value-prof.c (gimple_ic_transform): Likewise. + (gimple_indirect_call_to_profile): Likewise. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-04-14 Richard Sandiford + + * tree-vectorizer.h (vect_strided_store_supported): Add a + HOST_WIDE_INT argument. + (vect_strided_load_supported): Likewise. + (vect_permute_store_chain): Return void. + (vect_transform_strided_load): Likewise. + (vect_permute_load_chain): Delete. + * tree-vect-data-refs.c (vect_strided_store_supported): Take a + count argument. Check that the count is a power of two. + (vect_strided_load_supported): Likewise. + (vect_permute_store_chain): Return void. Update after above changes. + Assert that the access is supported. + (vect_permute_load_chain): Likewise. + (vect_transform_strided_load): Return void. + * tree-vect-stmts.c (vectorizable_store): Update calls after + above interface changes. + (vectorizable_load): Likewise. + (vect_analyze_stmt): Don't check for strided powers of two here. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-04-14 Richard Sandiford + + * tree-vectorizer.h (vect_create_data_ref_ptr): Add an extra + type parameter. + * tree-vect-data-refs.c (vect_create_data_ref_ptr): Add an aggr_type + parameter. Generalise code to handle arrays as well as vectors. + (vect_setup_realignment): Update accordingly. + * tree-vect-stmts.c (vectorizable_store): Likewise. + (vectorizable_load): Likewise. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-04-14 Richard Sandiford + + * tree-vect-stmts.c (vectorizable_load): Allocate and free dr_chain + within the per-copy loop. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-04-14 Richard Sandiford + + * tree-vect-stmts.c (vectorizable_load): Print the number of copies + in the dump file. + +2001-06-02 Richard Sandiford + + gcc/ + Backport from mainline: + + 2011-03-25 Richard Sandiford + + * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS + case to VFPv1. + +=== modified file 'gcc/Makefile.in' +--- old/gcc/Makefile.in 2011-05-26 14:27:33 +0000 ++++ new/gcc/Makefile.in 2011-06-02 12:12:00 +0000 +@@ -888,6 +888,8 @@ + READ_MD_H = $(OBSTACK_H) $(HASHTAB_H) read-md.h + PARAMS_H = params.h params.def + BUILTINS_DEF = builtins.def sync-builtins.def omp-builtins.def ++INTERNAL_FN_DEF = internal-fn.def ++INTERNAL_FN_H = internal-fn.h $(INTERNAL_FN_DEF) + TREE_H = tree.h all-tree.def tree.def c-family/c-common.def \ + $(lang_tree_files) $(MACHMODE_H) tree-check.h $(BUILTINS_DEF) \ + $(INPUT_H) statistics.h $(VEC_H) treestruct.def $(HASHTAB_H) \ +@@ -897,7 +899,7 @@ + BASIC_BLOCK_H = basic-block.h $(PREDICT_H) $(VEC_H) $(FUNCTION_H) cfghooks.h + GIMPLE_H = gimple.h gimple.def gsstruct.def pointer-set.h $(VEC_H) \ + $(GGC_H) $(BASIC_BLOCK_H) $(TARGET_H) tree-ssa-operands.h \ +- tree-ssa-alias.h vecir.h ++ tree-ssa-alias.h vecir.h $(INTERNAL_FN_H) + GCOV_IO_H = gcov-io.h gcov-iov.h auto-host.h + COVERAGE_H = coverage.h $(GCOV_IO_H) + DEMANGLE_H = $(srcdir)/../include/demangle.h +@@ -1269,6 +1271,7 @@ + init-regs.o \ + input.o \ + integrate.o \ ++ internal-fn.o \ + intl.o \ + ira.o \ + ira-build.o \ +@@ -2751,6 +2754,8 @@ + $(TM_H) $(TREE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) $(TREE_FLOW_H) \ + $(TREE_PASS_H) tree-ssa-propagate.h tree-pretty-print.h \ + gimple-pretty-print.h ++internal-fn.o : internal-fn.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ ++ $(GIMPLE_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H) + gimple.o : gimple.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \ + $(GGC_H) $(GIMPLE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) gt-gimple.h \ + $(TREE_FLOW_H) value-prof.h $(FLAGS_H) $(DEMANGLE_H) \ + +=== modified file 'gcc/cfgexpand.c' +--- old/gcc/cfgexpand.c 2011-04-20 11:18:50 +0000 ++++ new/gcc/cfgexpand.c 2011-06-02 12:12:00 +0000 +@@ -1839,12 +1839,17 @@ + static void + expand_call_stmt (gimple stmt) + { +- tree exp; +- tree lhs = gimple_call_lhs (stmt); ++ tree exp, lhs; + size_t i; + bool builtin_p; + tree decl; + ++ if (gimple_call_internal_p (stmt)) ++ { ++ expand_internal_call (stmt); ++ return; ++ } ++ + exp = build_vl_exp (CALL_EXPR, gimple_call_num_args (stmt) + 3); + + CALL_EXPR_FN (exp) = gimple_call_fn (stmt); +@@ -1882,6 +1887,7 @@ + SET_EXPR_LOCATION (exp, gimple_location (stmt)); + TREE_BLOCK (exp) = gimple_block (stmt); + ++ lhs = gimple_call_lhs (stmt); + if (lhs) + expand_assignment (lhs, exp, false); + else + +=== modified file 'gcc/config/arm/arm.h' +--- old/gcc/config/arm/arm.h 2011-04-26 14:42:21 +0000 ++++ new/gcc/config/arm/arm.h 2011-06-02 12:12:00 +0000 +@@ -1169,12 +1169,12 @@ + } + + /* FPA registers can't do subreg as all values are reformatted to internal +- precision. VFP registers may only be accessed in the mode they +- were set. */ +-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ +- (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ +- ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ +- || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ ++ precision. In VFPv1, VFP registers could only be accessed in the mode ++ they were set, so subregs would be invalid there too. However, we don't ++ support VFPv1 at the moment, and the restriction was lifted in VFPv2. */ ++#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ ++ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ ++ ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ + : 0) + + /* The class value for index registers, and the one for base regs. */ + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2011-05-06 11:28:27 +0000 ++++ new/gcc/config/arm/neon.md 2011-06-02 12:12:00 +0000 +@@ -4248,6 +4248,12 @@ + DONE; + }) + ++(define_expand "vec_load_lanes" ++ [(set (match_operand:VDQX 0 "s_register_operand") ++ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand")] ++ UNSPEC_VLD1))] ++ "TARGET_NEON") ++ + (define_insn "neon_vld1" + [(set (match_operand:VDQX 0 "s_register_operand" "=w") + (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")] +@@ -4345,6 +4351,12 @@ + (const_string "neon_vld1_1_2_regs")))] + ) + ++(define_expand "vec_store_lanes" ++ [(set (match_operand:VDQX 0 "neon_struct_operand") ++ (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand")] ++ UNSPEC_VST1))] ++ "TARGET_NEON") ++ + (define_insn "neon_vst1" + [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um") + (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")] +@@ -4401,6 +4413,13 @@ + [(set_attr "neon_type" "neon_vst1_vst2_lane")] + ) + ++(define_expand "vec_load_lanesti" ++ [(set (match_operand:TI 0 "s_register_operand") ++ (unspec:TI [(match_operand:TI 1 "neon_struct_operand") ++ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VLD2))] ++ "TARGET_NEON") ++ + (define_insn "neon_vld2" + [(set (match_operand:TI 0 "s_register_operand" "=w") + (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um") +@@ -4419,6 +4438,13 @@ + (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")))] + ) + ++(define_expand "vec_load_lanesoi" ++ [(set (match_operand:OI 0 "s_register_operand") ++ (unspec:OI [(match_operand:OI 1 "neon_struct_operand") ++ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VLD2))] ++ "TARGET_NEON") ++ + (define_insn "neon_vld2" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") +@@ -4501,6 +4527,13 @@ + (const_string "neon_vld1_1_2_regs")))] + ) + ++(define_expand "vec_store_lanesti" ++ [(set (match_operand:TI 0 "neon_struct_operand") ++ (unspec:TI [(match_operand:TI 1 "s_register_operand") ++ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VST2))] ++ "TARGET_NEON") ++ + (define_insn "neon_vst2" + [(set (match_operand:TI 0 "neon_struct_operand" "=Um") + (unspec:TI [(match_operand:TI 1 "s_register_operand" "w") +@@ -4519,6 +4552,13 @@ + (const_string "neon_vst1_1_2_regs_vst2_2_regs")))] + ) + ++(define_expand "vec_store_lanesoi" ++ [(set (match_operand:OI 0 "neon_struct_operand") ++ (unspec:OI [(match_operand:OI 1 "s_register_operand") ++ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VST2))] ++ "TARGET_NEON") ++ + (define_insn "neon_vst2" + [(set (match_operand:OI 0 "neon_struct_operand" "=Um") + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") +@@ -4584,6 +4624,13 @@ + [(set_attr "neon_type" "neon_vst1_vst2_lane")] + ) + ++(define_expand "vec_load_lanesei" ++ [(set (match_operand:EI 0 "s_register_operand") ++ (unspec:EI [(match_operand:EI 1 "neon_struct_operand") ++ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VLD3))] ++ "TARGET_NEON") ++ + (define_insn "neon_vld3" + [(set (match_operand:EI 0 "s_register_operand" "=w") + (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um") +@@ -4602,6 +4649,16 @@ + (const_string "neon_vld3_vld4")))] + ) + ++(define_expand "vec_load_lanesci" ++ [(match_operand:CI 0 "s_register_operand") ++ (match_operand:CI 1 "neon_struct_operand") ++ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_neon_vld3 (operands[0], operands[1])); ++ DONE; ++}) ++ + (define_expand "neon_vld3" + [(match_operand:CI 0 "s_register_operand") + (match_operand:CI 1 "neon_struct_operand") +@@ -4741,6 +4798,13 @@ + (const_string "neon_vld3_vld4_all_lanes") + (const_string "neon_vld1_1_2_regs")))]) + ++(define_expand "vec_store_lanesei" ++ [(set (match_operand:EI 0 "neon_struct_operand") ++ (unspec:EI [(match_operand:EI 1 "s_register_operand") ++ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VST3))] ++ "TARGET_NEON") ++ + (define_insn "neon_vst3" + [(set (match_operand:EI 0 "neon_struct_operand" "=Um") + (unspec:EI [(match_operand:EI 1 "s_register_operand" "w") +@@ -4758,6 +4822,16 @@ + (const_string "neon_vst1_1_2_regs_vst2_2_regs") + (const_string "neon_vst2_4_regs_vst3_vst4")))]) + ++(define_expand "vec_store_lanesci" ++ [(match_operand:CI 0 "neon_struct_operand") ++ (match_operand:CI 1 "s_register_operand") ++ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_neon_vst3 (operands[0], operands[1])); ++ DONE; ++}) ++ + (define_expand "neon_vst3" + [(match_operand:CI 0 "neon_struct_operand") + (match_operand:CI 1 "s_register_operand") +@@ -4869,6 +4943,13 @@ + } + [(set_attr "neon_type" "neon_vst3_vst4_lane")]) + ++(define_expand "vec_load_lanesoi" ++ [(set (match_operand:OI 0 "s_register_operand") ++ (unspec:OI [(match_operand:OI 1 "neon_struct_operand") ++ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VLD4))] ++ "TARGET_NEON") ++ + (define_insn "neon_vld4" + [(set (match_operand:OI 0 "s_register_operand" "=w") + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") +@@ -4887,6 +4968,16 @@ + (const_string "neon_vld3_vld4")))] + ) + ++(define_expand "vec_load_lanesxi" ++ [(match_operand:XI 0 "s_register_operand") ++ (match_operand:XI 1 "neon_struct_operand") ++ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_neon_vld4 (operands[0], operands[1])); ++ DONE; ++}) ++ + (define_expand "neon_vld4" + [(match_operand:XI 0 "s_register_operand") + (match_operand:XI 1 "neon_struct_operand") +@@ -5033,6 +5124,13 @@ + (const_string "neon_vld1_1_2_regs")))] + ) + ++(define_expand "vec_store_lanesoi" ++ [(set (match_operand:OI 0 "neon_struct_operand") ++ (unspec:OI [(match_operand:OI 1 "s_register_operand") ++ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ UNSPEC_VST4))] ++ "TARGET_NEON") ++ + (define_insn "neon_vst4" + [(set (match_operand:OI 0 "neon_struct_operand" "=Um") + (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") +@@ -5051,6 +5149,16 @@ + (const_string "neon_vst2_4_regs_vst3_vst4")))] + ) + ++(define_expand "vec_store_lanesxi" ++ [(match_operand:XI 0 "neon_struct_operand") ++ (match_operand:XI 1 "s_register_operand") ++ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] ++ "TARGET_NEON" ++{ ++ emit_insn (gen_neon_vst4 (operands[0], operands[1])); ++ DONE; ++}) ++ + (define_expand "neon_vst4" + [(match_operand:XI 0 "neon_struct_operand") + (match_operand:XI 1 "s_register_operand") + +=== modified file 'gcc/doc/md.texi' +--- old/gcc/doc/md.texi 2011-01-03 20:52:22 +0000 ++++ new/gcc/doc/md.texi 2011-05-05 15:43:06 +0000 +@@ -3935,6 +3935,48 @@ + consecutive memory locations, operand 1 is the first register, and + operand 2 is a constant: the number of consecutive registers. + ++@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern ++@item @samp{vec_load_lanes@var{m}@var{n}} ++Perform an interleaved load of several vectors from memory operand 1 ++into register operand 0. Both operands have mode @var{m}. The register ++operand is viewed as holding consecutive vectors of mode @var{n}, ++while the memory operand is a flat array that contains the same number ++of elements. The operation is equivalent to: ++ ++@smallexample ++int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); ++for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) ++ for (i = 0; i < c; i++) ++ operand0[i][j] = operand1[j * c + i]; ++@end smallexample ++ ++For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values ++from memory into a register of mode @samp{TI}@. The register ++contains two consecutive vectors of mode @samp{V4HI}@. ++ ++This pattern can only be used if: ++@smallexample ++TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c}) ++@end smallexample ++is true. GCC assumes that, if a target supports this kind of ++instruction for some mode @var{n}, it also supports unaligned ++loads for vectors of mode @var{n}. ++ ++@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern ++@item @samp{vec_store_lanes@var{m}@var{n}} ++Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory ++and register operands reversed. That is, the instruction is ++equivalent to: ++ ++@smallexample ++int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); ++for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) ++ for (i = 0; i < c; i++) ++ operand0[j * c + i] = operand1[i][j]; ++@end smallexample ++ ++for a memory operand 0 and register operand 1. ++ + @cindex @code{vec_set@var{m}} instruction pattern + @item @samp{vec_set@var{m}} + Set given field in the vector value. Operand 0 is the vector to modify, + +=== modified file 'gcc/expr.c' +--- old/gcc/expr.c 2011-05-26 14:27:33 +0000 ++++ new/gcc/expr.c 2011-06-02 12:12:00 +0000 +@@ -8537,10 +8537,13 @@ + if (code == SSA_NAME + && (g = SSA_NAME_DEF_STMT (ssa_name)) + && gimple_code (g) == GIMPLE_CALL) +- pmode = promote_function_mode (type, mode, &unsignedp, +- TREE_TYPE +- (TREE_TYPE (gimple_call_fn (g))), +- 2); ++ { ++ gcc_assert (!gimple_call_internal_p (g)); ++ pmode = promote_function_mode (type, mode, &unsignedp, ++ TREE_TYPE ++ (TREE_TYPE (gimple_call_fn (g))), ++ 2); ++ } + else + pmode = promote_decl_mode (exp, &unsignedp); + gcc_assert (GET_MODE (decl_rtl) == pmode); + +=== modified file 'gcc/genopinit.c' +--- old/gcc/genopinit.c 2011-01-03 20:52:22 +0000 ++++ new/gcc/genopinit.c 2011-05-05 15:43:06 +0000 +@@ -74,6 +74,8 @@ + "set_convert_optab_handler (fractuns_optab, $B, $A, CODE_FOR_$(fractuns$Q$a$I$b2$))", + "set_convert_optab_handler (satfract_optab, $B, $A, CODE_FOR_$(satfract$a$Q$b2$))", + "set_convert_optab_handler (satfractuns_optab, $B, $A, CODE_FOR_$(satfractuns$I$a$Q$b2$))", ++ "set_convert_optab_handler (vec_load_lanes_optab, $A, $B, CODE_FOR_$(vec_load_lanes$a$b$))", ++ "set_convert_optab_handler (vec_store_lanes_optab, $A, $B, CODE_FOR_$(vec_store_lanes$a$b$))", + "set_optab_handler (add_optab, $A, CODE_FOR_$(add$P$a3$))", + "set_optab_handler (addv_optab, $A, CODE_FOR_$(add$F$a3$)),\n\ + set_optab_handler (add_optab, $A, CODE_FOR_$(add$F$a3$))", + +=== modified file 'gcc/gimple-low.c' +--- old/gcc/gimple-low.c 2011-02-08 11:15:53 +0000 ++++ new/gcc/gimple-low.c 2011-05-05 15:42:22 +0000 +@@ -218,6 +218,10 @@ + tree fndecl, parms, p; + unsigned int i, nargs; + ++ /* Calls to internal functions always match their signature. */ ++ if (gimple_call_internal_p (stmt)) ++ return true; ++ + nargs = gimple_call_num_args (stmt); + + /* Get argument types for verification. */ + +=== modified file 'gcc/gimple-pretty-print.c' +--- old/gcc/gimple-pretty-print.c 2011-02-15 18:36:16 +0000 ++++ new/gcc/gimple-pretty-print.c 2011-05-05 15:42:22 +0000 +@@ -596,8 +596,12 @@ + + if (flags & TDF_RAW) + { +- dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T", +- gs, gimple_call_fn (gs), lhs); ++ if (gimple_call_internal_p (gs)) ++ dump_gimple_fmt (buffer, spc, flags, "%G <%s, %T", gs, ++ internal_fn_name (gimple_call_internal_fn (gs)), lhs); ++ else ++ dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T", ++ gs, gimple_call_fn (gs), lhs); + if (gimple_call_num_args (gs) > 0) + { + pp_string (buffer, ", "); +@@ -617,7 +621,10 @@ + + pp_space (buffer); + } +- print_call_name (buffer, gimple_call_fn (gs), flags); ++ if (gimple_call_internal_p (gs)) ++ pp_string (buffer, internal_fn_name (gimple_call_internal_fn (gs))); ++ else ++ print_call_name (buffer, gimple_call_fn (gs), flags); + pp_string (buffer, " ("); + dump_gimple_call_args (buffer, gs, flags); + pp_character (buffer, ')'); + +=== modified file 'gcc/gimple.c' +--- old/gcc/gimple.c 2011-05-18 13:33:53 +0000 ++++ new/gcc/gimple.c 2011-06-02 12:12:00 +0000 +@@ -276,6 +276,59 @@ + } + + ++/* Helper for gimple_build_call_internal and gimple_build_call_internal_vec. ++ Build the basic components of a GIMPLE_CALL statement to internal ++ function FN with NARGS arguments. */ ++ ++static inline gimple ++gimple_build_call_internal_1 (enum internal_fn fn, unsigned nargs) ++{ ++ gimple s = gimple_build_with_ops (GIMPLE_CALL, ERROR_MARK, nargs + 3); ++ s->gsbase.subcode |= GF_CALL_INTERNAL; ++ gimple_call_set_internal_fn (s, fn); ++ gimple_call_reset_alias_info (s); ++ return s; ++} ++ ++ ++/* Build a GIMPLE_CALL statement to internal function FN. NARGS is ++ the number of arguments. The ... are the arguments. */ ++ ++gimple ++gimple_build_call_internal (enum internal_fn fn, unsigned nargs, ...) ++{ ++ va_list ap; ++ gimple call; ++ unsigned i; ++ ++ call = gimple_build_call_internal_1 (fn, nargs); ++ va_start (ap, nargs); ++ for (i = 0; i < nargs; i++) ++ gimple_call_set_arg (call, i, va_arg (ap, tree)); ++ va_end (ap); ++ ++ return call; ++} ++ ++ ++/* Build a GIMPLE_CALL statement to internal function FN with the arguments ++ specified in vector ARGS. */ ++ ++gimple ++gimple_build_call_internal_vec (enum internal_fn fn, VEC(tree, heap) *args) ++{ ++ unsigned i, nargs; ++ gimple call; ++ ++ nargs = VEC_length (tree, args); ++ call = gimple_build_call_internal_1 (fn, nargs); ++ for (i = 0; i < nargs; i++) ++ gimple_call_set_arg (call, i, VEC_index (tree, args, i)); ++ ++ return call; ++} ++ ++ + /* Build a GIMPLE_CALL statement from CALL_EXPR T. Note that T is + assumed to be in GIMPLE form already. Minimal checking is done of + this fact. */ +@@ -1774,6 +1827,20 @@ + return (gimple_body (fndecl) || (fn && fn->cfg)); + } + ++/* Return true if calls C1 and C2 are known to go to the same function. */ ++ ++bool ++gimple_call_same_target_p (const_gimple c1, const_gimple c2) ++{ ++ if (gimple_call_internal_p (c1)) ++ return (gimple_call_internal_p (c2) ++ && gimple_call_internal_fn (c1) == gimple_call_internal_fn (c2)); ++ else ++ return (gimple_call_fn (c1) == gimple_call_fn (c2) ++ || (gimple_call_fndecl (c1) ++ && gimple_call_fndecl (c1) == gimple_call_fndecl (c2))); ++} ++ + /* Detect flags from a GIMPLE_CALL. This is just like + call_expr_flags, but for gimple tuples. */ + +@@ -1786,6 +1853,8 @@ + + if (decl) + flags = flags_from_decl_or_type (decl); ++ else if (gimple_call_internal_p (stmt)) ++ flags = internal_fn_flags (gimple_call_internal_fn (stmt)); + else + { + t = TREE_TYPE (gimple_call_fn (stmt)); +@@ -1801,18 +1870,35 @@ + return flags; + } + ++/* Return the "fn spec" string for call STMT. */ ++ ++static tree ++gimple_call_fnspec (const_gimple stmt) ++{ ++ tree fn, type, attr; ++ ++ fn = gimple_call_fn (stmt); ++ if (!fn) ++ return NULL_TREE; ++ ++ type = TREE_TYPE (TREE_TYPE (fn)); ++ if (!type) ++ return NULL_TREE; ++ ++ attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type)); ++ if (!attr) ++ return NULL_TREE; ++ ++ return TREE_VALUE (TREE_VALUE (attr)); ++} ++ + /* Detects argument flags for argument number ARG on call STMT. */ + + int + gimple_call_arg_flags (const_gimple stmt, unsigned arg) + { +- tree type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt))); +- tree attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type)); +- if (!attr) +- return 0; +- +- attr = TREE_VALUE (TREE_VALUE (attr)); +- if (1 + arg >= (unsigned) TREE_STRING_LENGTH (attr)) ++ tree attr = gimple_call_fnspec (stmt); ++ if (!attr || 1 + arg >= (unsigned) TREE_STRING_LENGTH (attr)) + return 0; + + switch (TREE_STRING_POINTER (attr)[1 + arg]) +@@ -1850,13 +1936,8 @@ + if (gimple_call_flags (stmt) & ECF_MALLOC) + return ERF_NOALIAS; + +- type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt))); +- attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type)); +- if (!attr) +- return 0; +- +- attr = TREE_VALUE (TREE_VALUE (attr)); +- if (TREE_STRING_LENGTH (attr) < 1) ++ attr = gimple_call_fnspec (stmt); ++ if (!attr || TREE_STRING_LENGTH (attr) < 1) + return 0; + + switch (TREE_STRING_POINTER (attr)[0]) +@@ -2293,6 +2374,7 @@ + if (is_gimple_call (s)) + { + unsigned nargs = gimple_call_num_args (s); ++ tree fn; + + if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE))) + return true; +@@ -2307,7 +2389,8 @@ + return true; + } + +- if (TREE_SIDE_EFFECTS (gimple_call_fn (s))) ++ fn = gimple_call_fn (s); ++ if (fn && TREE_SIDE_EFFECTS (fn)) + return true; + + for (i = 0; i < nargs; i++) +@@ -2349,14 +2432,15 @@ + if (is_gimple_call (s)) + { + unsigned nargs = gimple_call_num_args (s); ++ tree fn; + + if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE))) + return true; + + /* We cannot use gimple_has_volatile_ops here, + because we must ignore a volatile LHS. */ +- if (TREE_SIDE_EFFECTS (gimple_call_fn (s)) +- || TREE_THIS_VOLATILE (gimple_call_fn (s))) ++ fn = gimple_call_fn (s); ++ if (fn && (TREE_SIDE_EFFECTS (fn) || TREE_THIS_VOLATILE (fn))) + { + gcc_assert (gimple_has_volatile_ops (s)); + return true; +@@ -3113,7 +3197,6 @@ + gimple_call_copy_skip_args (gimple stmt, bitmap args_to_skip) + { + int i; +- tree fn = gimple_call_fn (stmt); + int nargs = gimple_call_num_args (stmt); + VEC(tree, heap) *vargs = VEC_alloc (tree, heap, nargs); + gimple new_stmt; +@@ -3122,7 +3205,11 @@ + if (!bitmap_bit_p (args_to_skip, i)) + VEC_quick_push (tree, vargs, gimple_call_arg (stmt, i)); + +- new_stmt = gimple_build_call_vec (fn, vargs); ++ if (gimple_call_internal_p (stmt)) ++ new_stmt = gimple_build_call_internal_vec (gimple_call_internal_fn (stmt), ++ vargs); ++ else ++ new_stmt = gimple_build_call_vec (gimple_call_fn (stmt), vargs); + VEC_free (tree, heap, vargs); + if (gimple_call_lhs (stmt)) + gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt)); + +=== modified file 'gcc/gimple.h' +--- old/gcc/gimple.h 2011-04-18 21:58:03 +0000 ++++ new/gcc/gimple.h 2011-06-02 12:12:00 +0000 +@@ -30,6 +30,7 @@ + #include "basic-block.h" + #include "tree-ssa-operands.h" + #include "tree-ssa-alias.h" ++#include "internal-fn.h" + + struct gimple_seq_node_d; + typedef struct gimple_seq_node_d *gimple_seq_node; +@@ -82,6 +83,8 @@ + name, a _DECL, a _REF, etc. */ + }; + ++#define GF_CALL_INTERNAL_FN_SHIFT 8 ++ + /* Specific flags for individual GIMPLE statements. These flags are + always stored in gimple_statement_base.subcode and they may only be + defined for statement codes that do not use sub-codes. +@@ -102,6 +105,8 @@ + GF_CALL_TAILCALL = 1 << 3, + GF_CALL_VA_ARG_PACK = 1 << 4, + GF_CALL_NOTHROW = 1 << 5, ++ GF_CALL_INTERNAL = 1 << 6, ++ GF_CALL_INTERNAL_FN = 0xff << GF_CALL_INTERNAL_FN_SHIFT, + GF_OMP_PARALLEL_COMBINED = 1 << 0, + + /* True on an GIMPLE_OMP_RETURN statement if the return does not require +@@ -817,6 +822,8 @@ + + gimple gimple_build_call_vec (tree, VEC(tree, heap) *); + gimple gimple_build_call (tree, unsigned, ...); ++gimple gimple_build_call_internal (enum internal_fn, unsigned, ...); ++gimple gimple_build_call_internal_vec (enum internal_fn, VEC(tree, heap) *); + gimple gimple_build_call_from_tree (tree); + gimple gimplify_assign (tree, tree, gimple_seq *); + gimple gimple_build_cond (enum tree_code, tree, tree, tree, tree); +@@ -861,6 +868,7 @@ + void gimple_seq_free (gimple_seq); + void gimple_seq_add_seq (gimple_seq *, gimple_seq); + gimple_seq gimple_seq_copy (gimple_seq); ++bool gimple_call_same_target_p (const_gimple, const_gimple); + int gimple_call_flags (const_gimple); + int gimple_call_return_flags (const_gimple); + int gimple_call_arg_flags (const_gimple, unsigned); +@@ -2012,6 +2020,27 @@ + } + + ++/* Return true if call GS calls an internal-only function, as enumerated ++ by internal_fn. */ ++ ++static inline bool ++gimple_call_internal_p (const_gimple gs) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_CALL); ++ return (gs->gsbase.subcode & GF_CALL_INTERNAL) != 0; ++} ++ ++ ++/* Return the target of internal call GS. */ ++ ++static inline enum internal_fn ++gimple_call_internal_fn (const_gimple gs) ++{ ++ gcc_assert (gimple_call_internal_p (gs)); ++ return (enum internal_fn) (gs->gsbase.subcode >> GF_CALL_INTERNAL_FN_SHIFT); ++} ++ ++ + /* Return a pointer to the tree node representing the function called by call + statement GS. */ + +@@ -2029,6 +2058,7 @@ + gimple_call_set_fn (gimple gs, tree fn) + { + GIMPLE_CHECK (gs, GIMPLE_CALL); ++ gcc_assert (!gimple_call_internal_p (gs)); + gimple_set_op (gs, 1, fn); + } + +@@ -2039,10 +2069,23 @@ + gimple_call_set_fndecl (gimple gs, tree decl) + { + GIMPLE_CHECK (gs, GIMPLE_CALL); ++ gcc_assert (!gimple_call_internal_p (gs)); + gimple_set_op (gs, 1, build_fold_addr_expr_loc (gimple_location (gs), decl)); + } + + ++/* Set internal function FN to be the function called by call statement GS. */ ++ ++static inline void ++gimple_call_set_internal_fn (gimple gs, enum internal_fn fn) ++{ ++ GIMPLE_CHECK (gs, GIMPLE_CALL); ++ gcc_assert (gimple_call_internal_p (gs)); ++ gs->gsbase.subcode &= ~GF_CALL_INTERNAL_FN; ++ gs->gsbase.subcode |= (int) fn << GF_CALL_INTERNAL_FN_SHIFT; ++} ++ ++ + /* If a given GIMPLE_CALL's callee is a FUNCTION_DECL, return it. + Otherwise return NULL. This function is analogous to + get_callee_fndecl in tree land. */ +@@ -2051,7 +2094,7 @@ + gimple_call_fndecl (const_gimple gs) + { + tree addr = gimple_call_fn (gs); +- if (TREE_CODE (addr) == ADDR_EXPR) ++ if (addr && TREE_CODE (addr) == ADDR_EXPR) + { + tree fndecl = TREE_OPERAND (addr, 0); + if (TREE_CODE (fndecl) == MEM_REF) +@@ -2073,8 +2116,13 @@ + static inline tree + gimple_call_return_type (const_gimple gs) + { +- tree fn = gimple_call_fn (gs); +- tree type = TREE_TYPE (fn); ++ tree fn, type; ++ ++ fn = gimple_call_fn (gs); ++ if (fn == NULL_TREE) ++ return TREE_TYPE (gimple_call_lhs (gs)); ++ ++ type = TREE_TYPE (fn); + + /* See through the pointer. */ + type = TREE_TYPE (type); + +=== added file 'gcc/internal-fn.c' +--- old/gcc/internal-fn.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/internal-fn.c 2011-05-05 15:43:06 +0000 +@@ -0,0 +1,147 @@ ++/* Internal functions. ++ Copyright (C) 2011 Free Software Foundation, Inc. ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++ ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++#include "config.h" ++#include "system.h" ++#include "coretypes.h" ++#include "gimple.h" ++#include "tree.h" ++#include "expr.h" ++#include "optabs.h" ++#include "recog.h" ++ ++/* The names of each internal function, indexed by function number. */ ++const char *const internal_fn_name_array[] = { ++#define DEF_INTERNAL_FN(CODE, FLAGS) #CODE, ++#include "internal-fn.def" ++#undef DEF_INTERNAL_FN ++ "" ++}; ++ ++/* The ECF_* flags of each internal function, indexed by function number. */ ++const int internal_fn_flags_array[] = { ++#define DEF_INTERNAL_FN(CODE, FLAGS) FLAGS, ++#include "internal-fn.def" ++#undef DEF_INTERNAL_FN ++ 0 ++}; ++ ++/* ARRAY_TYPE is an array of vector modes. Return the associated insn ++ for load-lanes-style optab OPTAB. The insn must exist. */ ++ ++static enum insn_code ++get_multi_vector_move (tree array_type, convert_optab optab) ++{ ++ enum insn_code icode; ++ enum machine_mode imode; ++ enum machine_mode vmode; ++ ++ gcc_assert (TREE_CODE (array_type) == ARRAY_TYPE); ++ imode = TYPE_MODE (array_type); ++ vmode = TYPE_MODE (TREE_TYPE (array_type)); ++ ++ icode = convert_optab_handler (optab, imode, vmode); ++ gcc_assert (icode != CODE_FOR_nothing); ++ return icode; ++} ++ ++/* Expand LOAD_LANES call STMT. */ ++ ++static void ++expand_LOAD_LANES (gimple stmt) ++{ ++ tree type, lhs, rhs; ++ rtx target, mem; ++ enum insn_code icode; ++ const struct insn_operand_data *operand; ++ ++ lhs = gimple_call_lhs (stmt); ++ rhs = gimple_call_arg (stmt, 0); ++ type = TREE_TYPE (lhs); ++ ++ target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE); ++ mem = expand_normal (rhs); ++ ++ gcc_assert (REG_P (target)); ++ gcc_assert (MEM_P (mem)); ++ PUT_MODE (mem, TYPE_MODE (type)); ++ ++ icode = get_multi_vector_move (type, vec_load_lanes_optab); ++ ++ operand = &insn_data[(int) icode].operand[1]; ++ if (operand->predicate && !operand->predicate (mem, operand->mode)) ++ mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0))); ++ ++ emit_insn (GEN_FCN (icode) (target, mem)); ++} ++ ++/* Expand STORE_LANES call STMT. */ ++ ++static void ++expand_STORE_LANES (gimple stmt) ++{ ++ tree type, lhs, rhs; ++ rtx target, reg; ++ enum insn_code icode; ++ const struct insn_operand_data *operand; ++ ++ lhs = gimple_call_lhs (stmt); ++ rhs = gimple_call_arg (stmt, 0); ++ type = TREE_TYPE (rhs); ++ ++ target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE); ++ reg = expand_normal (rhs); ++ ++ gcc_assert (MEM_P (target)); ++ PUT_MODE (target, TYPE_MODE (type)); ++ ++ icode = get_multi_vector_move (type, vec_store_lanes_optab); ++ ++ operand = &insn_data[(int) icode].operand[0]; ++ if (operand->predicate && !operand->predicate (target, operand->mode)) ++ target = replace_equiv_address (target, ++ force_reg (Pmode, XEXP (target, 0))); ++ ++ operand = &insn_data[(int) icode].operand[1]; ++ if (operand->predicate && !operand->predicate (reg, operand->mode)) ++ reg = force_reg (TYPE_MODE (type), reg); ++ ++ emit_insn (GEN_FCN (icode) (target, reg)); ++} ++ ++/* Routines to expand each internal function, indexed by function number. ++ Each routine has the prototype: ++ ++ expand_ (gimple stmt) ++ ++ where STMT is the statement that performs the call. */ ++static void (*const internal_fn_expanders[]) (gimple) = { ++#define DEF_INTERNAL_FN(CODE, FLAGS) expand_##CODE, ++#include "internal-fn.def" ++#undef DEF_INTERNAL_FN ++ 0 ++}; ++ ++/* Expand STMT, which is a call to internal function FN. */ ++ ++void ++expand_internal_call (gimple stmt) ++{ ++ internal_fn_expanders[(int) gimple_call_internal_fn (stmt)] (stmt); ++} + +=== added file 'gcc/internal-fn.def' +--- old/gcc/internal-fn.def 1970-01-01 00:00:00 +0000 ++++ new/gcc/internal-fn.def 2011-05-05 15:43:06 +0000 +@@ -0,0 +1,42 @@ ++/* Internal functions. ++ Copyright (C) 2011 Free Software Foundation, Inc. ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++ ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++/* This file specifies a list of internal "functions". These functions ++ differ from built-in functions in that they have no linkage and cannot ++ be called directly by the user. They represent operations that are only ++ synthesised by GCC itself. ++ ++ Internal functions are used instead of tree codes if the operation ++ and its operands are more naturally represented as a GIMPLE_CALL ++ than a GIMPLE_ASSIGN. ++ ++ Each entry in this file has the form: ++ ++ DEF_INTERNAL_FN (NAME, FLAGS) ++ ++ where NAME is the name of the function and FLAGS is a set of ++ ECF_* flags. Each entry must have a corresponding expander ++ of the form: ++ ++ void expand_NAME (gimple stmt) ++ ++ where STMT is the statement that performs the call. */ ++ ++DEF_INTERNAL_FN (LOAD_LANES, ECF_CONST | ECF_LEAF) ++DEF_INTERNAL_FN (STORE_LANES, ECF_CONST | ECF_LEAF) + +=== added file 'gcc/internal-fn.h' +--- old/gcc/internal-fn.h 1970-01-01 00:00:00 +0000 ++++ new/gcc/internal-fn.h 2011-05-05 15:42:22 +0000 +@@ -0,0 +1,52 @@ ++/* Internal functions. ++ Copyright (C) 2011 Free Software Foundation, Inc. ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++ ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++#ifndef GCC_INTERNAL_FN_H ++#define GCC_INTERNAL_FN_H ++ ++enum internal_fn { ++#define DEF_INTERNAL_FN(CODE, FLAGS) IFN_##CODE, ++#include "internal-fn.def" ++#undef DEF_INTERNAL_FN ++ IFN_LAST ++}; ++ ++extern const char *const internal_fn_name_array[]; ++extern const int internal_fn_flags_array[]; ++ ++/* Return the name of internal function FN. The name is only meaningful ++ for dumps; it has no linkage. */ ++ ++static inline const char * ++internal_fn_name (enum internal_fn fn) ++{ ++ return internal_fn_name_array[(int) fn]; ++} ++ ++/* Return the ECF_* flags for function FN. */ ++ ++static inline int ++internal_fn_flags (enum internal_fn fn) ++{ ++ return internal_fn_flags_array[(int) fn]; ++} ++ ++extern void expand_internal_call (gimple); ++ ++#endif + +=== modified file 'gcc/ipa-prop.c' +--- old/gcc/ipa-prop.c 2011-04-18 21:58:03 +0000 ++++ new/gcc/ipa-prop.c 2011-06-02 12:12:00 +0000 +@@ -1418,6 +1418,8 @@ + { + tree target = gimple_call_fn (call); + ++ if (!target) ++ return; + if (TREE_CODE (target) == SSA_NAME) + ipa_analyze_indirect_call_uses (node, info, parms_info, call, target); + else if (TREE_CODE (target) == OBJ_TYPE_REF) + +=== modified file 'gcc/optabs.h' +--- old/gcc/optabs.h 2011-01-03 20:52:22 +0000 ++++ new/gcc/optabs.h 2011-05-05 15:43:06 +0000 +@@ -578,6 +578,9 @@ + COI_satfract, + COI_satfractuns, + ++ COI_vec_load_lanes, ++ COI_vec_store_lanes, ++ + COI_MAX + }; + +@@ -598,6 +601,8 @@ + #define fractuns_optab (&convert_optab_table[COI_fractuns]) + #define satfract_optab (&convert_optab_table[COI_satfract]) + #define satfractuns_optab (&convert_optab_table[COI_satfractuns]) ++#define vec_load_lanes_optab (&convert_optab_table[COI_vec_load_lanes]) ++#define vec_store_lanes_optab (&convert_optab_table[COI_vec_store_lanes]) + + /* Contains the optab used for each rtx code. */ + extern optab code_to_optab[NUM_RTX_CODE + 1]; + +=== modified file 'gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c' +--- old/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c 2009-04-20 10:26:18 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c 2011-05-05 15:46:10 +0000 +@@ -26,7 +26,7 @@ + } + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided_wide } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided_wide } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c' +--- old/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c 2011-05-05 15:46:10 +0000 +@@ -113,7 +113,7 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" {target { vect_strided && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" {target { vect_strided8 && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided8 && vect_int_mult } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c' +--- old/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c 2008-08-26 08:14:37 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c 2011-05-05 15:44:00 +0000 +@@ -20,7 +20,7 @@ + return avg; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c' +--- old/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c 2010-08-26 11:13:58 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c 2011-05-05 15:46:10 +0000 +@@ -13,5 +13,5 @@ + } + } + +-/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided } } } */ ++/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c' +--- old/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c 2011-05-05 15:46:10 +0000 +@@ -56,5 +56,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c' +--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-04-24 07:45:49 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-05-05 15:46:10 +0000 +@@ -65,5 +65,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || { ! vect_strided2 } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c' +--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c 2011-05-05 15:46:10 +0000 +@@ -54,5 +54,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c' +--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c 2011-05-05 15:46:10 +0000 +@@ -53,5 +53,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c' +--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c 2007-10-21 09:01:16 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c 2011-05-05 15:46:10 +0000 +@@ -47,5 +47,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_interleave } } } */ ++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave || vect_strided2 } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c' +--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c 2011-05-05 15:46:10 +0000 +@@ -50,5 +50,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/pr30843.c' +--- old/gcc/testsuite/gcc.dg/vect/pr30843.c 2007-02-22 12:30:12 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/pr30843.c 2011-05-05 15:46:10 +0000 +@@ -20,6 +20,6 @@ + } + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided4 } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/pr33866.c' +--- old/gcc/testsuite/gcc.dg/vect/pr33866.c 2007-10-30 08:26:14 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/pr33866.c 2011-05-05 15:46:10 +0000 +@@ -27,6 +27,6 @@ + } + + /* Needs interleaving support. */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/pr37539.c' +--- old/gcc/testsuite/gcc.dg/vect/pr37539.c 2009-11-26 02:03:50 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/pr37539.c 2011-05-05 15:46:10 +0000 +@@ -40,7 +40,7 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_strided_wide } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_strided4 && vect_strided2 } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + + +=== removed file 'gcc/testsuite/gcc.dg/vect/slp-11.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-11.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-11.c 1970-01-01 00:00:00 +0000 +@@ -1,113 +0,0 @@ +-/* { dg-require-effective-target vect_int } */ +- +-#include +-#include "tree-vect.h" +- +-#define N 8 +- +-int +-main1 () +-{ +- int i; +- unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7; +- unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; +- float out2[N*8]; +- +- /* Different operations - not SLPable. */ +- for (i = 0; i < N; i++) +- { +- a0 = in[i*8] + 5; +- a1 = in[i*8 + 1] * 6; +- a2 = in[i*8 + 2] + 7; +- a3 = in[i*8 + 3] + 8; +- a4 = in[i*8 + 4] + 9; +- a5 = in[i*8 + 5] + 10; +- a6 = in[i*8 + 6] + 11; +- a7 = in[i*8 + 7] + 12; +- +- b0 = a0 * 3; +- b1 = a1 * 2; +- b2 = a2 * 12; +- b3 = a3 * 5; +- b4 = a4 * 8; +- b5 = a5 * 4; +- b6 = a6 * 3; +- b7 = a7 * 2; +- +- out[i*8] = b0 - 2; +- out[i*8 + 1] = b1 - 3; +- out[i*8 + 2] = b2 - 2; +- out[i*8 + 3] = b3 - 1; +- out[i*8 + 4] = b4 - 8; +- out[i*8 + 5] = b5 - 7; +- out[i*8 + 6] = b6 - 3; +- out[i*8 + 7] = b7 - 7; +- } +- +- /* check results: */ +- for (i = 0; i < N; i++) +- { +- if (out[i*8] != (in[i*8] + 5) * 3 - 2 +- || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3 +- || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2 +- || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1 +- || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8 +- || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7 +- || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3 +- || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7) +- abort (); +- } +- +- /* Requires permutation - not SLPable. */ +- for (i = 0; i < N*2; i++) +- { +- out[i*4] = (in[i*4] + 2) * 3; +- out[i*4 + 1] = (in[i*4 + 2] + 2) * 7; +- out[i*4 + 2] = (in[i*4 + 1] + 7) * 3; +- out[i*4 + 3] = (in[i*4 + 3] + 3) * 4; +- } +- +- /* check results: */ +- for (i = 0; i < N*2; i++) +- { +- if (out[i*4] != (in[i*4] + 2) * 3 +- || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7 +- || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3 +- || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4) +- abort (); +- } +- +- /* Different operations - not SLPable. */ +- for (i = 0; i < N*4; i++) +- { +- out2[i*2] = ((float) in[i*2] * 2 + 6) ; +- out2[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7); +- } +- +- /* check results: */ +- for (i = 0; i < N*4; i++) +- { +- if (out2[i*2] != ((float) in[i*2] * 2 + 6) +- || out2[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7)) +- abort (); +- } +- +- +- return 0; +-} +- +-int main (void) +-{ +- check_vect (); +- +- main1 (); +- +- return 0; +-} +- +-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { { vect_uintfloat_cvt && vect_strided_wide } && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { { { ! vect_uintfloat_cvt } && vect_strided_wide } && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! { vect_int_mult && vect_strided_wide } } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */ +-/* { dg-final { cleanup-tree-dump "vect" } } */ +- + +=== added file 'gcc/testsuite/gcc.dg/vect/slp-11a.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-11a.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-11a.c 2011-05-05 15:46:10 +0000 +@@ -0,0 +1,75 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 8 ++ ++int ++main1 () ++{ ++ int i; ++ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7; ++ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++ ++ /* Different operations - not SLPable. */ ++ for (i = 0; i < N; i++) ++ { ++ a0 = in[i*8] + 5; ++ a1 = in[i*8 + 1] * 6; ++ a2 = in[i*8 + 2] + 7; ++ a3 = in[i*8 + 3] + 8; ++ a4 = in[i*8 + 4] + 9; ++ a5 = in[i*8 + 5] + 10; ++ a6 = in[i*8 + 6] + 11; ++ a7 = in[i*8 + 7] + 12; ++ ++ b0 = a0 * 3; ++ b1 = a1 * 2; ++ b2 = a2 * 12; ++ b3 = a3 * 5; ++ b4 = a4 * 8; ++ b5 = a5 * 4; ++ b6 = a6 * 3; ++ b7 = a7 * 2; ++ ++ out[i*8] = b0 - 2; ++ out[i*8 + 1] = b1 - 3; ++ out[i*8 + 2] = b2 - 2; ++ out[i*8 + 3] = b3 - 1; ++ out[i*8 + 4] = b4 - 8; ++ out[i*8 + 5] = b5 - 7; ++ out[i*8 + 6] = b6 - 3; ++ out[i*8 + 7] = b7 - 7; ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N; i++) ++ { ++ if (out[i*8] != (in[i*8] + 5) * 3 - 2 ++ || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3 ++ || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2 ++ || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1 ++ || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8 ++ || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7 ++ || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3 ++ || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++int main (void) ++{ ++ check_vect (); ++ ++ main1 (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== added file 'gcc/testsuite/gcc.dg/vect/slp-11b.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-11b.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-11b.c 2011-05-05 15:46:10 +0000 +@@ -0,0 +1,49 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 8 ++ ++int ++main1 () ++{ ++ int i; ++ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7; ++ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++ ++ /* Requires permutation - not SLPable. */ ++ for (i = 0; i < N*2; i++) ++ { ++ out[i*4] = (in[i*4] + 2) * 3; ++ out[i*4 + 1] = (in[i*4 + 2] + 2) * 7; ++ out[i*4 + 2] = (in[i*4 + 1] + 7) * 3; ++ out[i*4 + 3] = (in[i*4 + 3] + 3) * 4; ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N*2; i++) ++ { ++ if (out[i*4] != (in[i*4] + 2) * 3 ++ || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7 ++ || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3 ++ || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++int main (void) ++{ ++ check_vect (); ++ ++ main1 (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided4 && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided4 && vect_int_mult } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== added file 'gcc/testsuite/gcc.dg/vect/slp-11c.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-11c.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-11c.c 2011-05-05 15:46:10 +0000 +@@ -0,0 +1,46 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 8 ++ ++int ++main1 () ++{ ++ int i; ++ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++ float out[N*8]; ++ ++ /* Different operations - not SLPable. */ ++ for (i = 0; i < N*4; i++) ++ { ++ out[i*2] = ((float) in[i*2] * 2 + 6) ; ++ out[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7); ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N*4; i++) ++ { ++ if (out[i*2] != ((float) in[i*2] * 2 + 6) ++ || out[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7)) ++ abort (); ++ } ++ ++ ++ return 0; ++} ++ ++int main (void) ++{ ++ check_vect (); ++ ++ main1 (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12a.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-12a.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-12a.c 2011-05-05 15:46:10 +0000 +@@ -11,7 +11,7 @@ + int i; + unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7; + unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; +- unsigned int ia[N], ib[N*2]; ++ unsigned int ia[N]; + + for (i = 0; i < N; i++) + { +@@ -61,27 +61,6 @@ + abort (); + } + +- for (i = 0; i < N*2; i++) +- { +- out[i*4] = (in[i*4] + 2) * 3; +- out[i*4 + 1] = (in[i*4 + 1] + 2) * 7; +- out[i*4 + 2] = (in[i*4 + 2] + 7) * 3; +- out[i*4 + 3] = (in[i*4 + 3] + 7) * 7; +- +- ib[i] = 7; +- } +- +- /* check results: */ +- for (i = 0; i < N*2; i++) +- { +- if (out[i*4] != (in[i*4] + 2) * 3 +- || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7 +- || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3 +- || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7 +- || ib[i] != 7) +- abort (); +- } +- + return 0; + } + +@@ -94,11 +73,8 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult} } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {target { vect_strided_wide && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { ! vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ +- + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12b.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-12b.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-12b.c 2011-05-05 15:46:10 +0000 +@@ -43,9 +43,9 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided2 && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided2 && vect_int_mult } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_strided2 && vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided2 && vect_int_mult } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== added file 'gcc/testsuite/gcc.dg/vect/slp-12c.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-12c.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-12c.c 2011-05-05 15:44:41 +0000 +@@ -0,0 +1,53 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 8 ++ ++int ++main1 () ++{ ++ int i; ++ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7; ++ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++ unsigned int ia[N*2]; ++ ++ for (i = 0; i < N*2; i++) ++ { ++ out[i*4] = (in[i*4] + 2) * 3; ++ out[i*4 + 1] = (in[i*4 + 1] + 2) * 7; ++ out[i*4 + 2] = (in[i*4 + 2] + 7) * 3; ++ out[i*4 + 3] = (in[i*4 + 3] + 7) * 7; ++ ++ ia[i] = 7; ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N*2; i++) ++ { ++ if (out[i*4] != (in[i*4] + 2) * 3 ++ || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7 ++ || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3 ++ || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7 ++ || ia[i] != 7) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++int main (void) ++{ ++ check_vect (); ++ ++ main1 (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_int_mult } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_int_mult } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_int_mult } } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-18.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-18.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-18.c 2011-05-05 15:46:10 +0000 +@@ -91,7 +91,7 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_strided } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== removed file 'gcc/testsuite/gcc.dg/vect/slp-19.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-19.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-19.c 1970-01-01 00:00:00 +0000 +@@ -1,154 +0,0 @@ +-/* { dg-require-effective-target vect_int } */ +- +-#include +-#include "tree-vect.h" +- +-#define N 16 +- +-int +-main1 () +-{ +- unsigned int i; +- unsigned int out[N*8]; +- unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; +- unsigned int ia[N*2], a0, a1, a2, a3; +- +- for (i = 0; i < N; i++) +- { +- out[i*8] = in[i*8]; +- out[i*8 + 1] = in[i*8 + 1]; +- out[i*8 + 2] = in[i*8 + 2]; +- out[i*8 + 3] = in[i*8 + 3]; +- out[i*8 + 4] = in[i*8 + 4]; +- out[i*8 + 5] = in[i*8 + 5]; +- out[i*8 + 6] = in[i*8 + 6]; +- out[i*8 + 7] = in[i*8 + 7]; +- +- ia[i] = in[i*8 + 2]; +- } +- +- /* check results: */ +- for (i = 0; i < N; i++) +- { +- if (out[i*8] != in[i*8] +- || out[i*8 + 1] != in[i*8 + 1] +- || out[i*8 + 2] != in[i*8 + 2] +- || out[i*8 + 3] != in[i*8 + 3] +- || out[i*8 + 4] != in[i*8 + 4] +- || out[i*8 + 5] != in[i*8 + 5] +- || out[i*8 + 6] != in[i*8 + 6] +- || out[i*8 + 7] != in[i*8 + 7] +- || ia[i] != in[i*8 + 2]) +- abort (); +- } +- +- for (i = 0; i < N*2; i++) +- { +- a0 = in[i*4] + 1; +- a1 = in[i*4 + 1] + 2; +- a2 = in[i*4 + 2] + 3; +- a3 = in[i*4 + 3] + 4; +- +- out[i*4] = a0; +- out[i*4 + 1] = a1; +- out[i*4 + 2] = a2; +- out[i*4 + 3] = a3; +- +- ia[i] = a2; +- } +- +- /* check results: */ +- for (i = 0; i < N*2; i++) +- { +- if (out[i*4] != in[i*4] + 1 +- || out[i*4 + 1] != in[i*4 + 1] + 2 +- || out[i*4 + 2] != in[i*4 + 2] + 3 +- || out[i*4 + 3] != in[i*4 + 3] + 4 +- || ia[i] != in[i*4 + 2] + 3) +- abort (); +- } +- +- /* The last stmt requires interleaving of not power of 2 size - not +- vectorizable. */ +- for (i = 0; i < N/2; i++) +- { +- out[i*12] = in[i*12]; +- out[i*12 + 1] = in[i*12 + 1]; +- out[i*12 + 2] = in[i*12 + 2]; +- out[i*12 + 3] = in[i*12 + 3]; +- out[i*12 + 4] = in[i*12 + 4]; +- out[i*12 + 5] = in[i*12 + 5]; +- out[i*12 + 6] = in[i*12 + 6]; +- out[i*12 + 7] = in[i*12 + 7]; +- out[i*12 + 8] = in[i*12 + 8]; +- out[i*12 + 9] = in[i*12 + 9]; +- out[i*12 + 10] = in[i*12 + 10]; +- out[i*12 + 11] = in[i*12 + 11]; +- +- ia[i] = in[i*12 + 7]; +- } +- +- /* check results: */ +- for (i = 0; i < N/2; i++) +- { +- if (out[i*12] != in[i*12] +- || out[i*12 + 1] != in[i*12 + 1] +- || out[i*12 + 2] != in[i*12 + 2] +- || out[i*12 + 3] != in[i*12 + 3] +- || out[i*12 + 4] != in[i*12 + 4] +- || out[i*12 + 5] != in[i*12 + 5] +- || out[i*12 + 6] != in[i*12 + 6] +- || out[i*12 + 7] != in[i*12 + 7] +- || out[i*12 + 8] != in[i*12 + 8] +- || out[i*12 + 9] != in[i*12 + 9] +- || out[i*12 + 10] != in[i*12 + 10] +- || out[i*12 + 11] != in[i*12 + 11] +- || ia[i] != in[i*12 + 7]) +- abort (); +- } +- +- /* Hybrid SLP with unrolling by 2. */ +- for (i = 0; i < N; i++) +- { +- out[i*6] = in[i*6]; +- out[i*6 + 1] = in[i*6 + 1]; +- out[i*6 + 2] = in[i*6 + 2]; +- out[i*6 + 3] = in[i*6 + 3]; +- out[i*6 + 4] = in[i*6 + 4]; +- out[i*6 + 5] = in[i*6 + 5]; +- +- ia[i] = i; +- } +- +- /* check results: */ +- for (i = 0; i < N/2; i++) +- { +- if (out[i*6] != in[i*6] +- || out[i*6 + 1] != in[i*6 + 1] +- || out[i*6 + 2] != in[i*6 + 2] +- || out[i*6 + 3] != in[i*6 + 3] +- || out[i*6 + 4] != in[i*6 + 4] +- || out[i*6 + 5] != in[i*6 + 5] +- || ia[i] != i) +- abort (); +- } +- +- +- return 0; +-} +- +-int main (void) +-{ +- check_vect (); +- +- main1 (); +- +- return 0; +-} +- +-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target vect_strided_wide } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide } } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" { target vect_strided_wide } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! { vect_strided_wide } } } } } */ +-/* { dg-final { cleanup-tree-dump "vect" } } */ +- + +=== added file 'gcc/testsuite/gcc.dg/vect/slp-19a.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-19a.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-19a.c 2011-05-05 15:46:10 +0000 +@@ -0,0 +1,61 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 16 ++ ++int ++main1 () ++{ ++ unsigned int i; ++ unsigned int out[N*8]; ++ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++ unsigned int ia[N*2]; ++ ++ for (i = 0; i < N; i++) ++ { ++ out[i*8] = in[i*8]; ++ out[i*8 + 1] = in[i*8 + 1]; ++ out[i*8 + 2] = in[i*8 + 2]; ++ out[i*8 + 3] = in[i*8 + 3]; ++ out[i*8 + 4] = in[i*8 + 4]; ++ out[i*8 + 5] = in[i*8 + 5]; ++ out[i*8 + 6] = in[i*8 + 6]; ++ out[i*8 + 7] = in[i*8 + 7]; ++ ++ ia[i] = in[i*8 + 2]; ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N; i++) ++ { ++ if (out[i*8] != in[i*8] ++ || out[i*8 + 1] != in[i*8 + 1] ++ || out[i*8 + 2] != in[i*8 + 2] ++ || out[i*8 + 3] != in[i*8 + 3] ++ || out[i*8 + 4] != in[i*8 + 4] ++ || out[i*8 + 5] != in[i*8 + 5] ++ || out[i*8 + 6] != in[i*8 + 6] ++ || out[i*8 + 7] != in[i*8 + 7] ++ || ia[i] != in[i*8 + 2]) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++int main (void) ++{ ++ check_vect (); ++ ++ main1 (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided8 } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided8 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided8} } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== added file 'gcc/testsuite/gcc.dg/vect/slp-19b.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-19b.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-19b.c 2011-05-05 15:46:10 +0000 +@@ -0,0 +1,58 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 16 ++ ++int ++main1 () ++{ ++ unsigned int i; ++ unsigned int out[N*8]; ++ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++ unsigned int ia[N*2], a0, a1, a2, a3; ++ ++ for (i = 0; i < N*2; i++) ++ { ++ a0 = in[i*4] + 1; ++ a1 = in[i*4 + 1] + 2; ++ a2 = in[i*4 + 2] + 3; ++ a3 = in[i*4 + 3] + 4; ++ ++ out[i*4] = a0; ++ out[i*4 + 1] = a1; ++ out[i*4 + 2] = a2; ++ out[i*4 + 3] = a3; ++ ++ ia[i] = a2; ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N*2; i++) ++ { ++ if (out[i*4] != in[i*4] + 1 ++ || out[i*4 + 1] != in[i*4 + 1] + 2 ++ || out[i*4 + 2] != in[i*4 + 2] + 3 ++ || out[i*4 + 3] != in[i*4 + 3] + 4 ++ || ia[i] != in[i*4 + 2] + 3) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++int main (void) ++{ ++ check_vect (); ++ ++ main1 (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided4 } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided4 } } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== added file 'gcc/testsuite/gcc.dg/vect/slp-19c.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-19c.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-19c.c 2011-05-05 15:44:41 +0000 +@@ -0,0 +1,95 @@ ++/* { dg-require-effective-target vect_int } */ ++ ++#include ++#include "tree-vect.h" ++ ++#define N 16 ++ ++int ++main1 () ++{ ++ unsigned int i; ++ unsigned int out[N*8]; ++ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63}; ++ unsigned int ia[N*2], a0, a1, a2, a3; ++ ++ /* The last stmt requires interleaving of not power of 2 size - not ++ vectorizable. */ ++ for (i = 0; i < N/2; i++) ++ { ++ out[i*12] = in[i*12]; ++ out[i*12 + 1] = in[i*12 + 1]; ++ out[i*12 + 2] = in[i*12 + 2]; ++ out[i*12 + 3] = in[i*12 + 3]; ++ out[i*12 + 4] = in[i*12 + 4]; ++ out[i*12 + 5] = in[i*12 + 5]; ++ out[i*12 + 6] = in[i*12 + 6]; ++ out[i*12 + 7] = in[i*12 + 7]; ++ out[i*12 + 8] = in[i*12 + 8]; ++ out[i*12 + 9] = in[i*12 + 9]; ++ out[i*12 + 10] = in[i*12 + 10]; ++ out[i*12 + 11] = in[i*12 + 11]; ++ ++ ia[i] = in[i*12 + 7]; ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N/2; i++) ++ { ++ if (out[i*12] != in[i*12] ++ || out[i*12 + 1] != in[i*12 + 1] ++ || out[i*12 + 2] != in[i*12 + 2] ++ || out[i*12 + 3] != in[i*12 + 3] ++ || out[i*12 + 4] != in[i*12 + 4] ++ || out[i*12 + 5] != in[i*12 + 5] ++ || out[i*12 + 6] != in[i*12 + 6] ++ || out[i*12 + 7] != in[i*12 + 7] ++ || out[i*12 + 8] != in[i*12 + 8] ++ || out[i*12 + 9] != in[i*12 + 9] ++ || out[i*12 + 10] != in[i*12 + 10] ++ || out[i*12 + 11] != in[i*12 + 11] ++ || ia[i] != in[i*12 + 7]) ++ abort (); ++ } ++ ++ /* Hybrid SLP with unrolling by 2. */ ++ for (i = 0; i < N; i++) ++ { ++ out[i*6] = in[i*6]; ++ out[i*6 + 1] = in[i*6 + 1]; ++ out[i*6 + 2] = in[i*6 + 2]; ++ out[i*6 + 3] = in[i*6 + 3]; ++ out[i*6 + 4] = in[i*6 + 4]; ++ out[i*6 + 5] = in[i*6 + 5]; ++ ++ ia[i] = i; ++ } ++ ++ /* check results: */ ++ for (i = 0; i < N/2; i++) ++ { ++ if (out[i*6] != in[i*6] ++ || out[i*6 + 1] != in[i*6 + 1] ++ || out[i*6 + 2] != in[i*6 + 2] ++ || out[i*6 + 3] != in[i*6 + 3] ++ || out[i*6 + 4] != in[i*6 + 4] ++ || out[i*6 + 5] != in[i*6 + 5] ++ || ia[i] != i) ++ abort (); ++ } ++ ++ return 0; ++} ++ ++int main (void) ++{ ++ check_vect (); ++ ++ main1 (); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-21.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-21.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-21.c 2011-05-05 15:46:10 +0000 +@@ -199,9 +199,9 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target { vect_strided || vect_extract_even_odd } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided || vect_extract_even_odd } } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided } } } */ +-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target { vect_strided4 || vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided4 || vect_extract_even_odd } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided4 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided4 } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-23.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-23.c 2011-01-10 12:51:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-23.c 2011-05-05 15:46:10 +0000 +@@ -106,8 +106,8 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided_wide } && {! { vect_no_align} } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide || vect_no_align} } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided8 && { ! { vect_no_align} } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided8 || vect_no_align } } } } } */ + /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/slp-reduc-6.c' +--- old/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c 2011-05-05 15:46:10 +0000 +@@ -42,7 +42,7 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! vect_unpack } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! { vect_unpack || vect_strided2 } } } } } } */ + /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */ + /* { dg-final { scan-tree-dump-times "different interleaving chains in one node" 1 "vect" { target { ! vect_no_int_add } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-1.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-1.c 2010-08-19 10:23:50 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-1.c 2011-05-05 15:46:10 +0000 +@@ -85,6 +85,6 @@ + fbar (a); + } + +-/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_strided2 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-10.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-10.c 2010-05-27 12:23:45 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-10.c 2011-05-05 15:46:10 +0000 +@@ -22,5 +22,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_strided2 } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-107.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-107.c 2008-08-19 08:06:54 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-107.c 2011-05-05 15:46:10 +0000 +@@ -40,6 +40,6 @@ + return main1 (); + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-98.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-98.c 2008-08-02 11:05:47 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-98.c 2011-05-05 15:46:10 +0000 +@@ -38,6 +38,6 @@ + } + + /* Needs interleaving support. */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail vect_strided4 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-03-27 09:38:18 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-05-05 15:46:10 +0000 +@@ -82,5 +82,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || { ! vect_strided2 } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c 2011-05-05 15:46:10 +0000 +@@ -71,6 +71,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c 2011-05-05 15:46:10 +0000 +@@ -55,6 +55,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c 2011-05-05 15:46:10 +0000 +@@ -68,6 +68,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c 2011-05-05 15:46:10 +0000 +@@ -62,6 +62,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c 2010-05-27 12:23:45 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c 2011-05-05 15:46:10 +0000 +@@ -61,6 +61,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c 2011-05-05 15:46:10 +0000 +@@ -69,6 +69,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c 2011-05-05 15:46:10 +0000 +@@ -76,6 +76,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c 2011-05-05 15:46:10 +0000 +@@ -81,6 +81,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-float.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-float.c 2008-08-19 08:06:54 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-float.c 2011-05-05 15:46:10 +0000 +@@ -39,7 +39,7 @@ + } + + /* Needs interleaving support. */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c 2011-05-05 15:46:10 +0000 +@@ -71,6 +71,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c 2011-05-05 15:46:10 +0000 +@@ -71,6 +71,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c 2011-05-05 15:46:10 +0000 +@@ -72,5 +72,5 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c 2008-08-12 05:31:57 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c 2011-05-05 15:46:10 +0000 +@@ -55,6 +55,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c 2007-10-21 09:01:16 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c 2011-05-05 15:46:10 +0000 +@@ -65,8 +65,8 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_interleave && vect_pack_trunc } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { ! { vect_interleave } } && { vect_pack_trunc } } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_interleave || vect_strided4 } && vect_pack_trunc } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { ! { vect_interleave || vect_strided4 } } && { vect_pack_trunc } } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c 2011-05-05 15:46:10 +0000 +@@ -39,7 +39,7 @@ + } + + /* Needs interleaving support. */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave || vect_strided2 } } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c 2011-05-05 15:46:10 +0000 +@@ -55,6 +55,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== added file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c 2011-05-05 15:46:25 +0000 +@@ -0,0 +1,112 @@ ++#include ++#include "tree-vect.h" ++ ++#define N 128 ++ ++typedef struct { ++ unsigned short a; ++ unsigned short b; ++ unsigned short c; ++} s; ++ ++#define A(I) (I) ++#define B(I) ((I) * 2) ++#define C(I) ((unsigned short) ~((I) ^ 0x18)) ++ ++void __attribute__ ((noinline)) ++check1 (s *res) ++{ ++ int i; ++ ++ for (i = 0; i < N; i++) ++ if (res[i].a != C (i) ++ || res[i].b != A (i) ++ || res[i].c != B (i)) ++ abort (); ++} ++ ++void __attribute__ ((noinline)) ++check2 (unsigned short *res) ++{ ++ int i; ++ ++ for (i = 0; i < N; i++) ++ if (res[i] != (unsigned short) (A (i) + B (i) + C (i))) ++ abort (); ++} ++ ++void __attribute__ ((noinline)) ++check3 (s *res) ++{ ++ int i; ++ ++ for (i = 0; i < N; i++) ++ if (res[i].a != i ++ || res[i].b != i ++ || res[i].c != i) ++ abort (); ++} ++ ++void __attribute__ ((noinline)) ++check4 (unsigned short *res) ++{ ++ int i; ++ ++ for (i = 0; i < N; i++) ++ if (res[i] != (unsigned short) (A (i) + B (i))) ++ abort (); ++} ++ ++void __attribute__ ((noinline)) ++main1 (s *arr) ++{ ++ int i; ++ s *ptr = arr; ++ s res1[N]; ++ unsigned short res2[N]; ++ ++ for (i = 0; i < N; i++) ++ { ++ res1[i].a = arr[i].c; ++ res1[i].b = arr[i].a; ++ res1[i].c = arr[i].b; ++ } ++ check1 (res1); ++ ++ for (i = 0; i < N; i++) ++ res2[i] = arr[i].a + arr[i].b + arr[i].c; ++ check2 (res2); ++ ++ for (i = 0; i < N; i++) ++ { ++ res1[i].a = i; ++ res1[i].b = i; ++ res1[i].c = i; ++ } ++ check3 (res1); ++ ++ for (i = 0; i < N; i++) ++ res2[i] = arr[i].a + arr[i].b; ++ check4 (res2); ++} ++ ++int main (void) ++{ ++ int i; ++ s arr[N]; ++ ++ check_vect (); ++ ++ for (i = 0; i < N; i++) ++ { ++ arr[i].a = A (i); ++ arr[i].b = B (i); ++ arr[i].c = C (i); ++ } ++ main1 (arr); ++ ++ return 0; ++} ++ ++/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target vect_strided3 } } } */ ++/* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c 2011-05-05 15:46:10 +0000 +@@ -68,6 +68,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c 2011-05-05 15:46:10 +0000 +@@ -63,6 +63,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c 2011-05-05 15:46:10 +0000 +@@ -77,6 +77,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c 2010-05-27 12:23:45 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c 2011-05-05 15:46:10 +0000 +@@ -60,6 +60,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c 2011-05-05 15:46:10 +0000 +@@ -71,6 +71,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c 2011-05-05 15:46:10 +0000 +@@ -54,6 +54,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c 2011-05-05 15:46:10 +0000 +@@ -78,6 +78,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c 2011-05-05 15:46:10 +0000 +@@ -98,6 +98,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c 2007-09-04 12:05:19 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c 2011-05-05 15:46:10 +0000 +@@ -83,6 +83,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c 2010-11-22 12:16:52 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c 2011-05-05 15:46:10 +0000 +@@ -85,6 +85,6 @@ + return 0; + } + +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect-vfa-03.c' +--- old/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c 2007-09-09 07:46:12 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c 2011-05-05 15:46:10 +0000 +@@ -53,6 +53,6 @@ + } + + /* Needs interleaving support. */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */ +-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd } } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail vect_strided2 } } } */ + /* { dg-final { cleanup-tree-dump "vect" } } */ + +=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp' +--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2011-04-24 07:45:49 +0000 ++++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-05-05 15:43:31 +0000 +@@ -75,15 +75,20 @@ + lappend VECT_SLP_CFLAGS "-fdump-tree-slp-details" + + # Main loop. +-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]] \ +- "" $DEFAULT_VECTCFLAGS +-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]] \ +- "" $DEFAULT_VECTCFLAGS +-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]] \ +- "" $DEFAULT_VECTCFLAGS +-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]] \ +- "" $VECT_SLP_CFLAGS +- ++set VECT_ADDITIONAL_FLAGS [list ""] ++if { [check_effective_target_lto] } { ++ lappend VECT_ADDITIONAL_FLAGS "-flto" ++} ++foreach flags $VECT_ADDITIONAL_FLAGS { ++ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]] \ ++ $flags $DEFAULT_VECTCFLAGS ++ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]] \ ++ $flags $DEFAULT_VECTCFLAGS ++ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]] \ ++ $flags $DEFAULT_VECTCFLAGS ++ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]] \ ++ $flags $VECT_SLP_CFLAGS ++} + + #### Tests with special options + global SAVED_DEFAULT_VECTCFLAGS + +=== modified file 'gcc/testsuite/lib/target-supports.exp' +--- old/gcc/testsuite/lib/target-supports.exp 2011-05-06 11:28:27 +0000 ++++ new/gcc/testsuite/lib/target-supports.exp 2011-06-02 12:12:00 +0000 +@@ -3139,29 +3139,6 @@ + return $et_vect_extract_even_odd_saved + } + +-# Return 1 if the target supports vector even/odd elements extraction of +-# vectors with SImode elements or larger, 0 otherwise. +- +-proc check_effective_target_vect_extract_even_odd_wide { } { +- global et_vect_extract_even_odd_wide_saved +- +- if [info exists et_vect_extract_even_odd_wide_saved] { +- verbose "check_effective_target_vect_extract_even_odd_wide: using cached result" 2 +- } else { +- set et_vect_extract_even_odd_wide_saved 0 +- if { [istarget powerpc*-*-*] +- || [istarget i?86-*-*] +- || [istarget x86_64-*-*] +- || [istarget ia64-*-*] +- || [istarget spu-*-*] } { +- set et_vect_extract_even_odd_wide_saved 1 +- } +- } +- +- verbose "check_effective_target_vect_extract_even_wide_odd: returning $et_vect_extract_even_odd_wide_saved" 2 +- return $et_vect_extract_even_odd_wide_saved +-} +- + # Return 1 if the target supports vector interleaving, 0 otherwise. + + proc check_effective_target_vect_interleave { } { +@@ -3184,41 +3161,30 @@ + return $et_vect_interleave_saved + } + +-# Return 1 if the target supports vector interleaving and extract even/odd, 0 otherwise. +-proc check_effective_target_vect_strided { } { +- global et_vect_strided_saved +- +- if [info exists et_vect_strided_saved] { +- verbose "check_effective_target_vect_strided: using cached result" 2 +- } else { +- set et_vect_strided_saved 0 +- if { [check_effective_target_vect_interleave] +- && [check_effective_target_vect_extract_even_odd] } { +- set et_vect_strided_saved 1 +- } +- } +- +- verbose "check_effective_target_vect_strided: returning $et_vect_strided_saved" 2 +- return $et_vect_strided_saved +-} +- +-# Return 1 if the target supports vector interleaving and extract even/odd +-# for wide element types, 0 otherwise. +-proc check_effective_target_vect_strided_wide { } { +- global et_vect_strided_wide_saved +- +- if [info exists et_vect_strided_wide_saved] { +- verbose "check_effective_target_vect_strided_wide: using cached result" 2 +- } else { +- set et_vect_strided_wide_saved 0 +- if { [check_effective_target_vect_interleave] +- && [check_effective_target_vect_extract_even_odd_wide] } { +- set et_vect_strided_wide_saved 1 +- } +- } +- +- verbose "check_effective_target_vect_strided_wide: returning $et_vect_strided_wide_saved" 2 +- return $et_vect_strided_wide_saved ++foreach N {2 3 4 8} { ++ eval [string map [list N $N] { ++ # Return 1 if the target supports 2-vector interleaving ++ proc check_effective_target_vect_stridedN { } { ++ global et_vect_stridedN_saved ++ ++ if [info exists et_vect_stridedN_saved] { ++ verbose "check_effective_target_vect_stridedN: using cached result" 2 ++ } else { ++ set et_vect_stridedN_saved 0 ++ if { (N & -N) == N ++ && [check_effective_target_vect_interleave] ++ && [check_effective_target_vect_extract_even_odd] } { ++ set et_vect_stridedN_saved 1 ++ } ++ if { [istarget arm*-*-*] && N >= 2 && N <= 4 } { ++ set et_vect_stridedN_saved 1 ++ } ++ } ++ ++ verbose "check_effective_target_vect_stridedN: returning $et_vect_stridedN_saved" 2 ++ return $et_vect_stridedN_saved ++ } ++ }] + } + + # Return 1 if the target supports section-anchors + +=== modified file 'gcc/tree-cfg.c' +--- old/gcc/tree-cfg.c 2011-02-12 21:11:33 +0000 ++++ new/gcc/tree-cfg.c 2011-05-05 15:42:22 +0000 +@@ -3046,7 +3046,26 @@ + tree fntype; + unsigned i; + +- if (TREE_CODE (fn) != OBJ_TYPE_REF ++ if (gimple_call_internal_p (stmt)) ++ { ++ if (fn) ++ { ++ error ("gimple call has two targets"); ++ debug_generic_stmt (fn); ++ return true; ++ } ++ } ++ else ++ { ++ if (!fn) ++ { ++ error ("gimple call has no target"); ++ return true; ++ } ++ } ++ ++ if (fn ++ && TREE_CODE (fn) != OBJ_TYPE_REF + && !is_gimple_val (fn)) + { + error ("invalid function in gimple call"); +@@ -3054,9 +3073,10 @@ + return true; + } + +- if (!POINTER_TYPE_P (TREE_TYPE (fn)) +- || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE +- && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE)) ++ if (fn ++ && (!POINTER_TYPE_P (TREE_TYPE (fn)) ++ || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE ++ && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE))) + { + error ("non-function in gimple call"); + return true; +@@ -3076,8 +3096,12 @@ + return true; + } + +- fntype = TREE_TYPE (TREE_TYPE (fn)); +- if (gimple_call_lhs (stmt) ++ if (fn) ++ fntype = TREE_TYPE (TREE_TYPE (fn)); ++ else ++ fntype = NULL_TREE; ++ if (fntype ++ && gimple_call_lhs (stmt) + && !useless_type_conversion_p (TREE_TYPE (gimple_call_lhs (stmt)), + TREE_TYPE (fntype)) + /* ??? At least C++ misses conversions at assignments from +@@ -4130,9 +4154,10 @@ + didn't see a function declaration before the call. */ + if (is_gimple_call (stmt)) + { +- tree decl; ++ tree fn, decl; + +- if (!is_gimple_call_addr (gimple_call_fn (stmt))) ++ fn = gimple_call_fn (stmt); ++ if (fn && !is_gimple_call_addr (fn)) + { + error ("invalid function in call statement"); + return true; +@@ -7484,6 +7509,8 @@ + case GIMPLE_CALL: + if (gimple_call_lhs (g)) + break; ++ if (gimple_call_internal_p (g)) ++ break; + + /* This is a naked call, as opposed to a GIMPLE_CALL with an + LHS. All calls whose value is ignored should be + +=== modified file 'gcc/tree-eh.c' +--- old/gcc/tree-eh.c 2011-05-10 06:31:59 +0000 ++++ new/gcc/tree-eh.c 2011-06-02 12:12:00 +0000 +@@ -2745,7 +2745,7 @@ + || gimple_call_lhs (twos) + || gimple_call_chain (ones) + || gimple_call_chain (twos) +- || !operand_equal_p (gimple_call_fn (ones), gimple_call_fn (twos), 0) ++ || !gimple_call_same_target_p (ones, twos) + || gimple_call_num_args (ones) != gimple_call_num_args (twos)) + return false; + + +=== modified file 'gcc/tree-inline.c' +--- old/gcc/tree-inline.c 2011-05-05 21:02:06 +0000 ++++ new/gcc/tree-inline.c 2011-06-02 12:12:00 +0000 +@@ -3471,10 +3471,13 @@ + { + tree decl = gimple_call_fndecl (stmt); + tree addr = gimple_call_fn (stmt); +- tree funtype = TREE_TYPE (addr); ++ tree funtype = NULL_TREE; + bool stdarg = false; + +- if (POINTER_TYPE_P (funtype)) ++ if (addr) ++ funtype = TREE_TYPE (addr); ++ ++ if (funtype && POINTER_TYPE_P (funtype)) + funtype = TREE_TYPE (funtype); + + /* Do not special case builtins where we see the body. +@@ -3514,7 +3517,7 @@ + if (decl) + funtype = TREE_TYPE (decl); + +- if (!VOID_TYPE_P (TREE_TYPE (funtype))) ++ if (funtype && !VOID_TYPE_P (TREE_TYPE (funtype))) + cost += estimate_move_cost (TREE_TYPE (funtype)); + + if (funtype) + +=== modified file 'gcc/tree-ssa-ccp.c' +--- old/gcc/tree-ssa-ccp.c 2011-01-31 16:52:22 +0000 ++++ new/gcc/tree-ssa-ccp.c 2011-05-05 15:42:22 +0000 +@@ -1279,7 +1279,10 @@ + + case GIMPLE_CALL: + { +- tree fn = valueize_op (gimple_call_fn (stmt)); ++ tree fn = gimple_call_fn (stmt); ++ if (!fn) ++ return NULL_TREE; ++ fn = valueize_op (fn); + if (TREE_CODE (fn) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL + && DECL_BUILT_IN (TREE_OPERAND (fn, 0))) +@@ -2310,6 +2313,11 @@ + return true; + } + ++ /* Internal calls provide no argument types, so the extra laxity ++ for normal calls does not apply. */ ++ if (gimple_call_internal_p (stmt)) ++ return false; ++ + /* Propagate into the call arguments. Compared to replace_uses_in + this can use the argument slot types for type verification + instead of the current argument type. We also can safely + +=== modified file 'gcc/tree-ssa-dom.c' +--- old/gcc/tree-ssa-dom.c 2011-02-14 17:59:10 +0000 ++++ new/gcc/tree-ssa-dom.c 2011-05-05 15:42:22 +0000 +@@ -64,7 +64,7 @@ + struct { enum tree_code op; tree opnd; } unary; + struct { enum tree_code op; tree opnd0, opnd1; } binary; + struct { enum tree_code op; tree opnd0, opnd1, opnd2; } ternary; +- struct { tree fn; bool pure; size_t nargs; tree *args; } call; ++ struct { gimple fn_from; bool pure; size_t nargs; tree *args; } call; + } ops; + }; + +@@ -258,7 +258,7 @@ + + expr->type = TREE_TYPE (gimple_call_lhs (stmt)); + expr->kind = EXPR_CALL; +- expr->ops.call.fn = gimple_call_fn (stmt); ++ expr->ops.call.fn_from = stmt; + + if (gimple_call_flags (stmt) & (ECF_CONST | ECF_PURE)) + expr->ops.call.pure = true; +@@ -422,8 +422,8 @@ + + /* If the calls are to different functions, then they + clearly cannot be equal. */ +- if (! operand_equal_p (expr0->ops.call.fn, +- expr1->ops.call.fn, 0)) ++ if (!gimple_call_same_target_p (expr0->ops.call.fn_from, ++ expr1->ops.call.fn_from)) + return false; + + if (! expr0->ops.call.pure) +@@ -503,9 +503,15 @@ + { + size_t i; + enum tree_code code = CALL_EXPR; ++ gimple fn_from; + + val = iterative_hash_object (code, val); +- val = iterative_hash_expr (expr->ops.call.fn, val); ++ fn_from = expr->ops.call.fn_from; ++ if (gimple_call_internal_p (fn_from)) ++ val = iterative_hash_hashval_t ++ ((hashval_t) gimple_call_internal_fn (fn_from), val); ++ else ++ val = iterative_hash_expr (gimple_call_fn (fn_from), val); + for (i = 0; i < expr->ops.call.nargs; i++) + val = iterative_hash_expr (expr->ops.call.args[i], val); + } +@@ -565,8 +571,14 @@ + { + size_t i; + size_t nargs = element->expr.ops.call.nargs; ++ gimple fn_from; + +- print_generic_expr (stream, element->expr.ops.call.fn, 0); ++ fn_from = element->expr.ops.call.fn_from; ++ if (gimple_call_internal_p (fn_from)) ++ fputs (internal_fn_name (gimple_call_internal_fn (fn_from)), ++ stream); ++ else ++ print_generic_expr (stream, gimple_call_fn (fn_from), 0); + fprintf (stream, " ("); + for (i = 0; i < nargs; i++) + { + +=== modified file 'gcc/tree-ssa-pre.c' +--- old/gcc/tree-ssa-pre.c 2011-02-15 13:04:47 +0000 ++++ new/gcc/tree-ssa-pre.c 2011-05-05 15:42:22 +0000 +@@ -2657,11 +2657,13 @@ + } + + /* Return true if we can value number the call in STMT. This is true +- if we have a pure or constant call. */ ++ if we have a pure or constant call to a real function. */ + + static bool + can_value_number_call (gimple stmt) + { ++ if (gimple_call_internal_p (stmt)) ++ return false; + if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST)) + return true; + return false; +@@ -4187,6 +4189,7 @@ + gimple_stmt_iterator gsi; + gimple stmt; + unsigned i; ++ tree fn; + + FOR_EACH_BB (b) + { +@@ -4378,9 +4381,10 @@ + /* Visit indirect calls and turn them into direct calls if + possible. */ + if (is_gimple_call (stmt) +- && TREE_CODE (gimple_call_fn (stmt)) == SSA_NAME) ++ && (fn = gimple_call_fn (stmt)) ++ && TREE_CODE (fn) == SSA_NAME) + { +- tree fn = VN_INFO (gimple_call_fn (stmt))->valnum; ++ fn = VN_INFO (fn)->valnum; + if (TREE_CODE (fn) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL) + { + +=== modified file 'gcc/tree-ssa-sccvn.c' +--- old/gcc/tree-ssa-sccvn.c 2011-05-12 14:08:00 +0000 ++++ new/gcc/tree-ssa-sccvn.c 2011-06-02 12:12:00 +0000 +@@ -2982,7 +2982,8 @@ + /* ??? We should handle stores from calls. */ + else if (TREE_CODE (lhs) == SSA_NAME) + { +- if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST)) ++ if (!gimple_call_internal_p (stmt) ++ && gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST)) + changed = visit_reference_op_call (lhs, stmt); + else + changed = defs_to_varying (stmt); + +=== modified file 'gcc/tree-ssa-structalias.c' +--- old/gcc/tree-ssa-structalias.c 2011-02-10 15:29:52 +0000 ++++ new/gcc/tree-ssa-structalias.c 2011-05-05 15:42:22 +0000 +@@ -4319,6 +4319,7 @@ + /* Fallthru to general call handling. */; + } + if (!in_ipa_mode ++ || gimple_call_internal_p (t) + || (fndecl + && (!(fi = lookup_vi_for_tree (fndecl)) + || !fi->is_fn_info))) + +=== modified file 'gcc/tree-vect-data-refs.c' +--- old/gcc/tree-vect-data-refs.c 2011-05-06 11:28:27 +0000 ++++ new/gcc/tree-vect-data-refs.c 2011-06-02 12:12:00 +0000 +@@ -43,6 +43,45 @@ + #include "expr.h" + #include "optabs.h" + ++/* Return true if load- or store-lanes optab OPTAB is implemented for ++ COUNT vectors of type VECTYPE. NAME is the name of OPTAB. */ ++ ++static bool ++vect_lanes_optab_supported_p (const char *name, convert_optab optab, ++ tree vectype, unsigned HOST_WIDE_INT count) ++{ ++ enum machine_mode mode, array_mode; ++ bool limit_p; ++ ++ mode = TYPE_MODE (vectype); ++ limit_p = !targetm.array_mode_supported_p (mode, count); ++ array_mode = mode_for_size (count * GET_MODE_BITSIZE (mode), ++ MODE_INT, limit_p); ++ ++ if (array_mode == BLKmode) ++ { ++ if (vect_print_dump_info (REPORT_DETAILS)) ++ fprintf (vect_dump, "no array mode for %s[" HOST_WIDE_INT_PRINT_DEC "]", ++ GET_MODE_NAME (mode), count); ++ return false; ++ } ++ ++ if (convert_optab_handler (optab, array_mode, mode) == CODE_FOR_nothing) ++ { ++ if (vect_print_dump_info (REPORT_DETAILS)) ++ fprintf (vect_dump, "cannot use %s<%s><%s>", ++ name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode)); ++ return false; ++ } ++ ++ if (vect_print_dump_info (REPORT_DETAILS)) ++ fprintf (vect_dump, "can use %s<%s><%s>", ++ name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode)); ++ ++ return true; ++} ++ ++ + /* Return the smallest scalar part of STMT. + This is used to determine the vectype of the stmt. We generally set the + vectype according to the type of the result (lhs). For stmts whose +@@ -2196,19 +2235,6 @@ + return false; + } + +- /* FORNOW: we handle only interleaving that is a power of 2. +- We don't fail here if it may be still possible to vectorize the +- group using SLP. If not, the size of the group will be checked in +- vect_analyze_operations, and the vectorization will fail. */ +- if (exact_log2 (stride) == -1) +- { +- if (vect_print_dump_info (REPORT_DETAILS)) +- fprintf (vect_dump, "interleaving is not a power of 2"); +- +- if (slp_impossible) +- return false; +- } +- + if (stride == 0) + stride = count; + +@@ -2911,31 +2937,33 @@ + + /* Function vect_create_data_ref_ptr. + +- Create a new pointer to vector type (vp), that points to the first location +- accessed in the loop by STMT, along with the def-use update chain to +- appropriately advance the pointer through the loop iterations. Also set +- aliasing information for the pointer. This vector pointer is used by the +- callers to this function to create a memory reference expression for vector +- load/store access. ++ Create a new pointer-to-AGGR_TYPE variable (ap), that points to the first ++ location accessed in the loop by STMT, along with the def-use update ++ chain to appropriately advance the pointer through the loop iterations. ++ Also set aliasing information for the pointer. This pointer is used by ++ the callers to this function to create a memory reference expression for ++ vector load/store access. + + Input: + 1. STMT: a stmt that references memory. Expected to be of the form + GIMPLE_ASSIGN or + GIMPLE_ASSIGN . +- 2. AT_LOOP: the loop where the vector memref is to be created. +- 3. OFFSET (optional): an offset to be added to the initial address accessed ++ 2. AGGR_TYPE: the type of the reference, which should be either a vector ++ or an array. ++ 3. AT_LOOP: the loop where the vector memref is to be created. ++ 4. OFFSET (optional): an offset to be added to the initial address accessed + by the data-ref in STMT. +- 4. ONLY_INIT: indicate if vp is to be updated in the loop, or remain ++ 5. ONLY_INIT: indicate if vp is to be updated in the loop, or remain + pointing to the initial address. +- 5. TYPE: if not NULL indicates the required type of the data-ref. ++ 6. TYPE: if not NULL indicates the required type of the data-ref. + + Output: + 1. Declare a new ptr to vector_type, and have it point to the base of the + data reference (initial addressed accessed by the data reference). + For example, for vector of type V8HI, the following code is generated: + +- v8hi *vp; +- vp = (v8hi *)initial_address; ++ v8hi *ap; ++ ap = (v8hi *)initial_address; + + if OFFSET is not supplied: + initial_address = &a[init]; +@@ -2955,7 +2983,7 @@ + 4. Return the pointer. */ + + tree +-vect_create_data_ref_ptr (gimple stmt, struct loop *at_loop, ++vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop, + tree offset, tree *initial_address, gimple *ptr_incr, + bool only_init, bool *inv_p) + { +@@ -2965,17 +2993,16 @@ + struct loop *loop = NULL; + bool nested_in_vect_loop = false; + struct loop *containing_loop = NULL; +- tree vectype = STMT_VINFO_VECTYPE (stmt_info); +- tree vect_ptr_type; +- tree vect_ptr; ++ tree aggr_ptr_type; ++ tree aggr_ptr; + tree new_temp; + gimple vec_stmt; + gimple_seq new_stmt_list = NULL; + edge pe = NULL; + basic_block new_bb; +- tree vect_ptr_init; ++ tree aggr_ptr_init; + struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info); +- tree vptr; ++ tree aptr; + gimple_stmt_iterator incr_gsi; + bool insert_after; + bool negative; +@@ -2986,6 +3013,9 @@ + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + tree base; + ++ gcc_assert (TREE_CODE (aggr_type) == ARRAY_TYPE ++ || TREE_CODE (aggr_type) == VECTOR_TYPE); ++ + if (loop_vinfo) + { + loop = LOOP_VINFO_LOOP (loop_vinfo); +@@ -3020,8 +3050,9 @@ + if (vect_print_dump_info (REPORT_DETAILS)) + { + tree data_ref_base = base_name; +- fprintf (vect_dump, "create vector-pointer variable to type: "); +- print_generic_expr (vect_dump, vectype, TDF_SLIM); ++ fprintf (vect_dump, "create %s-pointer variable to type: ", ++ tree_code_name[(int) TREE_CODE (aggr_type)]); ++ print_generic_expr (vect_dump, aggr_type, TDF_SLIM); + if (TREE_CODE (data_ref_base) == VAR_DECL + || TREE_CODE (data_ref_base) == ARRAY_REF) + fprintf (vect_dump, " vectorizing an array ref: "); +@@ -3032,27 +3063,28 @@ + print_generic_expr (vect_dump, base_name, TDF_SLIM); + } + +- /* (1) Create the new vector-pointer variable. */ +- vect_ptr_type = build_pointer_type (vectype); ++ /* (1) Create the new aggregate-pointer variable. */ ++ aggr_ptr_type = build_pointer_type (aggr_type); + base = get_base_address (DR_REF (dr)); + if (base + && TREE_CODE (base) == MEM_REF) +- vect_ptr_type +- = build_qualified_type (vect_ptr_type, ++ aggr_ptr_type ++ = build_qualified_type (aggr_ptr_type, + TYPE_QUALS (TREE_TYPE (TREE_OPERAND (base, 0)))); +- vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var, ++ aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var, + get_name (base_name)); + +- /* Vector types inherit the alias set of their component type by default so +- we need to use a ref-all pointer if the data reference does not conflict +- with the created vector data reference because it is not addressable. */ +- if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr), ++ /* Vector and array types inherit the alias set of their component ++ type by default so we need to use a ref-all pointer if the data ++ reference does not conflict with the created aggregated data ++ reference because it is not addressable. */ ++ if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr), + get_alias_set (DR_REF (dr)))) + { +- vect_ptr_type +- = build_pointer_type_for_mode (vectype, +- TYPE_MODE (vect_ptr_type), true); +- vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var, ++ aggr_ptr_type ++ = build_pointer_type_for_mode (aggr_type, ++ TYPE_MODE (aggr_ptr_type), true); ++ aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var, + get_name (base_name)); + } + +@@ -3063,14 +3095,14 @@ + do + { + tree lhs = gimple_assign_lhs (orig_stmt); +- if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr), ++ if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr), + get_alias_set (lhs))) + { +- vect_ptr_type +- = build_pointer_type_for_mode (vectype, +- TYPE_MODE (vect_ptr_type), true); +- vect_ptr +- = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var, ++ aggr_ptr_type ++ = build_pointer_type_for_mode (aggr_type, ++ TYPE_MODE (aggr_ptr_type), true); ++ aggr_ptr ++ = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var, + get_name (base_name)); + break; + } +@@ -3080,7 +3112,7 @@ + while (orig_stmt); + } + +- add_referenced_var (vect_ptr); ++ add_referenced_var (aggr_ptr); + + /* Note: If the dataref is in an inner-loop nested in LOOP, and we are + vectorizing LOOP (i.e., outer-loop vectorization), we need to create two +@@ -3113,8 +3145,8 @@ + vp2 = vp1 + step + if () goto LOOP */ + +- /* (2) Calculate the initial address the vector-pointer, and set +- the vector-pointer to point to it before the loop. */ ++ /* (2) Calculate the initial address of the aggregate-pointer, and set ++ the aggregate-pointer to point to it before the loop. */ + + /* Create: (&(base[init_val+offset]) in the loop preheader. */ + +@@ -3133,17 +3165,17 @@ + + *initial_address = new_temp; + +- /* Create: p = (vectype *) initial_base */ ++ /* Create: p = (aggr_type *) initial_base */ + if (TREE_CODE (new_temp) != SSA_NAME +- || !useless_type_conversion_p (vect_ptr_type, TREE_TYPE (new_temp))) ++ || !useless_type_conversion_p (aggr_ptr_type, TREE_TYPE (new_temp))) + { +- vec_stmt = gimple_build_assign (vect_ptr, +- fold_convert (vect_ptr_type, new_temp)); +- vect_ptr_init = make_ssa_name (vect_ptr, vec_stmt); ++ vec_stmt = gimple_build_assign (aggr_ptr, ++ fold_convert (aggr_ptr_type, new_temp)); ++ aggr_ptr_init = make_ssa_name (aggr_ptr, vec_stmt); + /* Copy the points-to information if it exists. */ + if (DR_PTR_INFO (dr)) +- duplicate_ssa_name_ptr_info (vect_ptr_init, DR_PTR_INFO (dr)); +- gimple_assign_set_lhs (vec_stmt, vect_ptr_init); ++ duplicate_ssa_name_ptr_info (aggr_ptr_init, DR_PTR_INFO (dr)); ++ gimple_assign_set_lhs (vec_stmt, aggr_ptr_init); + if (pe) + { + new_bb = gsi_insert_on_edge_immediate (pe, vec_stmt); +@@ -3153,19 +3185,19 @@ + gsi_insert_before (&gsi, vec_stmt, GSI_SAME_STMT); + } + else +- vect_ptr_init = new_temp; ++ aggr_ptr_init = new_temp; + +- /* (3) Handle the updating of the vector-pointer inside the loop. ++ /* (3) Handle the updating of the aggregate-pointer inside the loop. + This is needed when ONLY_INIT is false, and also when AT_LOOP is the + inner-loop nested in LOOP (during outer-loop vectorization). */ + + /* No update in loop is required. */ + if (only_init && (!loop_vinfo || at_loop == loop)) +- vptr = vect_ptr_init; ++ aptr = aggr_ptr_init; + else + { +- /* The step of the vector pointer is the Vector Size. */ +- tree step = TYPE_SIZE_UNIT (vectype); ++ /* The step of the aggregate pointer is the type size. */ ++ tree step = TYPE_SIZE_UNIT (aggr_type); + /* One exception to the above is when the scalar step of the load in + LOOP is zero. In this case the step here is also zero. */ + if (*inv_p) +@@ -3175,9 +3207,9 @@ + + standard_iv_increment_position (loop, &incr_gsi, &insert_after); + +- create_iv (vect_ptr_init, +- fold_convert (vect_ptr_type, step), +- vect_ptr, loop, &incr_gsi, insert_after, ++ create_iv (aggr_ptr_init, ++ fold_convert (aggr_ptr_type, step), ++ aggr_ptr, loop, &incr_gsi, insert_after, + &indx_before_incr, &indx_after_incr); + incr = gsi_stmt (incr_gsi); + set_vinfo_for_stmt (incr, new_stmt_vec_info (incr, loop_vinfo, NULL)); +@@ -3191,14 +3223,14 @@ + if (ptr_incr) + *ptr_incr = incr; + +- vptr = indx_before_incr; ++ aptr = indx_before_incr; + } + + if (!nested_in_vect_loop || only_init) +- return vptr; +- +- +- /* (4) Handle the updating of the vector-pointer inside the inner-loop ++ return aptr; ++ ++ ++ /* (4) Handle the updating of the aggregate-pointer inside the inner-loop + nested in LOOP, if exists. */ + + gcc_assert (nested_in_vect_loop); +@@ -3206,7 +3238,7 @@ + { + standard_iv_increment_position (containing_loop, &incr_gsi, + &insert_after); +- create_iv (vptr, fold_convert (vect_ptr_type, DR_STEP (dr)), vect_ptr, ++ create_iv (aptr, fold_convert (aggr_ptr_type, DR_STEP (dr)), aggr_ptr, + containing_loop, &incr_gsi, insert_after, &indx_before_incr, + &indx_after_incr); + incr = gsi_stmt (incr_gsi); +@@ -3343,13 +3375,22 @@ + and FALSE otherwise. */ + + bool +-vect_strided_store_supported (tree vectype) ++vect_strided_store_supported (tree vectype, unsigned HOST_WIDE_INT count) + { + optab interleave_high_optab, interleave_low_optab; + enum machine_mode mode; + + mode = TYPE_MODE (vectype); + ++ /* vect_permute_store_chain requires the group size to be a power of two. */ ++ if (exact_log2 (count) == -1) ++ { ++ if (vect_print_dump_info (REPORT_DETAILS)) ++ fprintf (vect_dump, "the size of the group of strided accesses" ++ " is not a power of 2"); ++ return false; ++ } ++ + /* Check that the operation is supported. */ + interleave_high_optab = optab_for_tree_code (VEC_INTERLEAVE_HIGH_EXPR, + vectype, optab_default); +@@ -3374,6 +3415,18 @@ + } + + ++/* Return TRUE if vec_store_lanes is available for COUNT vectors of ++ type VECTYPE. */ ++ ++bool ++vect_store_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count) ++{ ++ return vect_lanes_optab_supported_p ("vec_store_lanes", ++ vec_store_lanes_optab, ++ vectype, count); ++} ++ ++ + /* Function vect_permute_store_chain. + + Given a chain of interleaved stores in DR_CHAIN of LENGTH that must be +@@ -3435,7 +3488,7 @@ + I3: 4 12 20 28 5 13 21 30 + I4: 6 14 22 30 7 15 23 31. */ + +-bool ++void + vect_permute_store_chain (VEC(tree,heap) *dr_chain, + unsigned int length, + gimple stmt, +@@ -3449,9 +3502,7 @@ + unsigned int j; + enum tree_code high_code, low_code; + +- /* Check that the operation is supported. */ +- if (!vect_strided_store_supported (vectype)) +- return false; ++ gcc_assert (vect_strided_store_supported (vectype, length)); + + *result_chain = VEC_copy (tree, heap, dr_chain); + +@@ -3504,7 +3555,6 @@ + } + dr_chain = VEC_copy (tree, heap, *result_chain); + } +- return true; + } + + /* Function vect_setup_realignment +@@ -3674,8 +3724,9 @@ + + gcc_assert (!compute_in_loop); + vec_dest = vect_create_destination_var (scalar_dest, vectype); +- ptr = vect_create_data_ref_ptr (stmt, loop_for_initial_load, NULL_TREE, +- &init_addr, &inc, true, &inv_p); ++ ptr = vect_create_data_ref_ptr (stmt, vectype, loop_for_initial_load, ++ NULL_TREE, &init_addr, &inc, ++ true, &inv_p); + new_stmt = gimple_build_assign_with_ops + (BIT_AND_EXPR, NULL_TREE, ptr, + build_int_cst (TREE_TYPE (ptr), +@@ -3780,13 +3831,22 @@ + and FALSE otherwise. */ + + bool +-vect_strided_load_supported (tree vectype) ++vect_strided_load_supported (tree vectype, unsigned HOST_WIDE_INT count) + { + optab perm_even_optab, perm_odd_optab; + enum machine_mode mode; + + mode = TYPE_MODE (vectype); + ++ /* vect_permute_load_chain requires the group size to be a power of two. */ ++ if (exact_log2 (count) == -1) ++ { ++ if (vect_print_dump_info (REPORT_DETAILS)) ++ fprintf (vect_dump, "the size of the group of strided accesses" ++ " is not a power of 2"); ++ return false; ++ } ++ + perm_even_optab = optab_for_tree_code (VEC_EXTRACT_EVEN_EXPR, vectype, + optab_default); + if (!perm_even_optab) +@@ -3821,6 +3881,16 @@ + return true; + } + ++/* Return TRUE if vec_load_lanes is available for COUNT vectors of ++ type VECTYPE. */ ++ ++bool ++vect_load_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count) ++{ ++ return vect_lanes_optab_supported_p ("vec_load_lanes", ++ vec_load_lanes_optab, ++ vectype, count); ++} + + /* Function vect_permute_load_chain. + +@@ -3898,7 +3968,7 @@ + 3rd vec (E2): 2 6 10 14 18 22 26 30 + 4th vec (E4): 3 7 11 15 19 23 27 31. */ + +-bool ++static void + vect_permute_load_chain (VEC(tree,heap) *dr_chain, + unsigned int length, + gimple stmt, +@@ -3911,9 +3981,7 @@ + int i; + unsigned int j; + +- /* Check that the operation is supported. */ +- if (!vect_strided_load_supported (vectype)) +- return false; ++ gcc_assert (vect_strided_load_supported (vectype, length)); + + *result_chain = VEC_copy (tree, heap, dr_chain); + for (i = 0; i < exact_log2 (length); i++) +@@ -3956,7 +4024,6 @@ + } + dr_chain = VEC_copy (tree, heap, *result_chain); + } +- return true; + } + + +@@ -3967,24 +4034,32 @@ + the scalar statements. + */ + +-bool ++void + vect_transform_strided_load (gimple stmt, VEC(tree,heap) *dr_chain, int size, + gimple_stmt_iterator *gsi) + { +- stmt_vec_info stmt_info = vinfo_for_stmt (stmt); +- gimple first_stmt = DR_GROUP_FIRST_DR (stmt_info); +- gimple next_stmt, new_stmt; + VEC(tree,heap) *result_chain = NULL; +- unsigned int i, gap_count; +- tree tmp_data_ref; + + /* DR_CHAIN contains input data-refs that are a part of the interleaving. + RESULT_CHAIN is the output of vect_permute_load_chain, it contains permuted + vectors, that are ready for vector computation. */ + result_chain = VEC_alloc (tree, heap, size); +- /* Permute. */ +- if (!vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain)) +- return false; ++ vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain); ++ vect_record_strided_load_vectors (stmt, result_chain); ++ VEC_free (tree, heap, result_chain); ++} ++ ++/* RESULT_CHAIN contains the output of a group of strided loads that were ++ generated as part of the vectorization of STMT. Assign the statement ++ for each vector to the associated scalar statement. */ ++ ++void ++vect_record_strided_load_vectors (gimple stmt, VEC(tree,heap) *result_chain) ++{ ++ gimple first_stmt = DR_GROUP_FIRST_DR (vinfo_for_stmt (stmt)); ++ gimple next_stmt, new_stmt; ++ unsigned int i, gap_count; ++ tree tmp_data_ref; + + /* Put a permuted data-ref in the VECTORIZED_STMT field. + Since we scan the chain starting from it's first node, their order +@@ -4046,9 +4121,6 @@ + break; + } + } +- +- VEC_free (tree, heap, result_chain); +- return true; + } + + /* Function vect_force_dr_alignment_p. + +=== modified file 'gcc/tree-vect-slp.c' +--- old/gcc/tree-vect-slp.c 2010-12-23 16:25:52 +0000 ++++ new/gcc/tree-vect-slp.c 2011-05-05 15:43:06 +0000 +@@ -215,7 +215,8 @@ + vect_model_simple_cost (stmt_info, ncopies_for_cost, dt, slp_node); + else + /* Store. */ +- vect_model_store_cost (stmt_info, ncopies_for_cost, dt[0], slp_node); ++ vect_model_store_cost (stmt_info, ncopies_for_cost, false, ++ dt[0], slp_node); + } + + else +@@ -579,7 +580,7 @@ + + /* Analyze costs (for the first stmt in the group). */ + vect_model_load_cost (vinfo_for_stmt (stmt), +- ncopies_for_cost, *node); ++ ncopies_for_cost, false, *node); + } + + /* Store the place of this load in the interleaving chain. In + +=== modified file 'gcc/tree-vect-stmts.c' +--- old/gcc/tree-vect-stmts.c 2011-04-18 07:38:11 +0000 ++++ new/gcc/tree-vect-stmts.c 2011-06-02 12:12:00 +0000 +@@ -42,6 +42,82 @@ + #include "langhooks.h" + + ++/* Return a variable of type ELEM_TYPE[NELEMS]. */ ++ ++static tree ++create_vector_array (tree elem_type, unsigned HOST_WIDE_INT nelems) ++{ ++ return create_tmp_var (build_array_type_nelts (elem_type, nelems), ++ "vect_array"); ++} ++ ++/* ARRAY is an array of vectors created by create_vector_array. ++ Return an SSA_NAME for the vector in index N. The reference ++ is part of the vectorization of STMT and the vector is associated ++ with scalar destination SCALAR_DEST. */ ++ ++static tree ++read_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree scalar_dest, ++ tree array, unsigned HOST_WIDE_INT n) ++{ ++ tree vect_type, vect, vect_name, array_ref; ++ gimple new_stmt; ++ ++ gcc_assert (TREE_CODE (TREE_TYPE (array)) == ARRAY_TYPE); ++ vect_type = TREE_TYPE (TREE_TYPE (array)); ++ vect = vect_create_destination_var (scalar_dest, vect_type); ++ array_ref = build4 (ARRAY_REF, vect_type, array, ++ build_int_cst (size_type_node, n), ++ NULL_TREE, NULL_TREE); ++ ++ new_stmt = gimple_build_assign (vect, array_ref); ++ vect_name = make_ssa_name (vect, new_stmt); ++ gimple_assign_set_lhs (new_stmt, vect_name); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ mark_symbols_for_renaming (new_stmt); ++ ++ return vect_name; ++} ++ ++/* ARRAY is an array of vectors created by create_vector_array. ++ Emit code to store SSA_NAME VECT in index N of the array. ++ The store is part of the vectorization of STMT. */ ++ ++static void ++write_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree vect, ++ tree array, unsigned HOST_WIDE_INT n) ++{ ++ tree array_ref; ++ gimple new_stmt; ++ ++ array_ref = build4 (ARRAY_REF, TREE_TYPE (vect), array, ++ build_int_cst (size_type_node, n), ++ NULL_TREE, NULL_TREE); ++ ++ new_stmt = gimple_build_assign (array_ref, vect); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ mark_symbols_for_renaming (new_stmt); ++} ++ ++/* PTR is a pointer to an array of type TYPE. Return a representation ++ of *PTR. The memory reference replaces those in FIRST_DR ++ (and its group). */ ++ ++static tree ++create_array_ref (tree type, tree ptr, struct data_reference *first_dr) ++{ ++ struct ptr_info_def *pi; ++ tree mem_ref, alias_ptr_type; ++ ++ alias_ptr_type = reference_alias_ptr_type (DR_REF (first_dr)); ++ mem_ref = build2 (MEM_REF, type, ptr, build_int_cst (alias_ptr_type, 0)); ++ /* Arrays have the same alignment as their type. */ ++ pi = get_ptr_info (ptr); ++ pi->align = TYPE_ALIGN_UNIT (type); ++ pi->misalign = 0; ++ return mem_ref; ++} ++ + /* Utility functions used by vect_mark_stmts_to_be_vectorized. */ + + /* Function vect_mark_relevant. +@@ -648,7 +724,8 @@ + + void + vect_model_store_cost (stmt_vec_info stmt_info, int ncopies, +- enum vect_def_type dt, slp_tree slp_node) ++ bool store_lanes_p, enum vect_def_type dt, ++ slp_tree slp_node) + { + int group_size; + unsigned int inside_cost = 0, outside_cost = 0; +@@ -685,9 +762,11 @@ + first_dr = STMT_VINFO_DATA_REF (stmt_info); + } + +- /* Is this an access in a group of stores, which provide strided access? +- If so, add in the cost of the permutes. */ +- if (group_size > 1) ++ /* We assume that the cost of a single store-lanes instruction is ++ equivalent to the cost of GROUP_SIZE separate stores. If a strided ++ access is instead being provided by a permute-and-store operation, ++ include the cost of the permutes. */ ++ if (!store_lanes_p && group_size > 1) + { + /* Uses a high and low interleave operation for each needed permute. */ + inside_cost = ncopies * exact_log2(group_size) * group_size +@@ -763,8 +842,8 @@ + access scheme chosen. */ + + void +-vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, slp_tree slp_node) +- ++vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, bool load_lanes_p, ++ slp_tree slp_node) + { + int group_size; + gimple first_stmt; +@@ -789,9 +868,11 @@ + first_dr = dr; + } + +- /* Is this an access in a group of loads providing strided access? +- If so, add in the cost of the permutes. */ +- if (group_size > 1) ++ /* We assume that the cost of a single load-lanes instruction is ++ equivalent to the cost of GROUP_SIZE separate loads. If a strided ++ access is instead being provided by a load-and-permute operation, ++ include the cost of the permutes. */ ++ if (!load_lanes_p && group_size > 1) + { + /* Uses an even and odd extract operations for each needed permute. */ + inside_cost = ncopies * exact_log2(group_size) * group_size +@@ -3329,6 +3410,7 @@ + stmt_vec_info stmt_info = vinfo_for_stmt (stmt); + struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr = NULL; + tree vectype = STMT_VINFO_VECTYPE (stmt_info); ++ tree elem_type; + loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info); + struct loop *loop = NULL; + enum machine_mode vec_mode; +@@ -3344,6 +3426,7 @@ + int j; + gimple next_stmt, first_stmt = NULL; + bool strided_store = false; ++ bool store_lanes_p = false; + unsigned int group_size, i; + VEC(tree,heap) *dr_chain = NULL, *oprnds = NULL, *result_chain = NULL; + bool inv_p; +@@ -3351,6 +3434,7 @@ + bool slp = (slp_node != NULL); + unsigned int vec_num; + bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info); ++ tree aggr_type; + + if (loop_vinfo) + loop = LOOP_VINFO_LOOP (loop_vinfo); +@@ -3404,7 +3488,8 @@ + + /* The scalar rhs type needs to be trivially convertible to the vector + component type. This should always be the case. */ +- if (!useless_type_conversion_p (TREE_TYPE (vectype), TREE_TYPE (op))) ++ elem_type = TREE_TYPE (vectype); ++ if (!useless_type_conversion_p (elem_type, TREE_TYPE (op))) + { + if (vect_print_dump_info (REPORT_DETAILS)) + fprintf (vect_dump, "??? operands of different types"); +@@ -3431,9 +3516,14 @@ + { + strided_store = true; + first_stmt = DR_GROUP_FIRST_DR (stmt_info); +- if (!vect_strided_store_supported (vectype) +- && !PURE_SLP_STMT (stmt_info) && !slp) +- return false; ++ if (!slp && !PURE_SLP_STMT (stmt_info)) ++ { ++ group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt)); ++ if (vect_store_lanes_supported (vectype, group_size)) ++ store_lanes_p = true; ++ else if (!vect_strided_store_supported (vectype, group_size)) ++ return false; ++ } + + if (first_stmt == stmt) + { +@@ -3459,7 +3549,7 @@ + if (!vec_stmt) /* transformation not required. */ + { + STMT_VINFO_TYPE (stmt_info) = store_vec_info_type; +- vect_model_store_cost (stmt_info, ncopies, dt, NULL); ++ vect_model_store_cost (stmt_info, ncopies, store_lanes_p, dt, NULL); + return true; + } + +@@ -3514,6 +3604,16 @@ + + alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false); + gcc_assert (alignment_support_scheme); ++ /* Targets with store-lane instructions must not require explicit ++ realignment. */ ++ gcc_assert (!store_lanes_p ++ || alignment_support_scheme == dr_aligned ++ || alignment_support_scheme == dr_unaligned_supported); ++ ++ if (store_lanes_p) ++ aggr_type = build_array_type_nelts (elem_type, vec_num * nunits); ++ else ++ aggr_type = vectype; + + /* In case the vectorization factor (VF) is bigger than the number + of elements that we can fit in a vectype (nunits), we have to generate +@@ -3602,9 +3702,9 @@ + /* We should have catched mismatched types earlier. */ + gcc_assert (useless_type_conversion_p (vectype, + TREE_TYPE (vec_oprnd))); +- dataref_ptr = vect_create_data_ref_ptr (first_stmt, NULL, NULL_TREE, +- &dummy, &ptr_incr, false, +- &inv_p); ++ dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, NULL, ++ NULL_TREE, &dummy, ++ &ptr_incr, false, &inv_p); + gcc_assert (bb_vinfo || !inv_p); + } + else +@@ -3625,76 +3725,101 @@ + VEC_replace(tree, dr_chain, i, vec_oprnd); + VEC_replace(tree, oprnds, i, vec_oprnd); + } +- dataref_ptr = +- bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE); +- } +- +- if (strided_store) +- { +- result_chain = VEC_alloc (tree, heap, group_size); +- /* Permute. */ +- if (!vect_permute_store_chain (dr_chain, group_size, stmt, gsi, +- &result_chain)) +- return false; +- } +- +- next_stmt = first_stmt; +- for (i = 0; i < vec_num; i++) +- { +- struct ptr_info_def *pi; +- +- if (i > 0) +- /* Bump the vector pointer. */ +- dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, +- NULL_TREE); +- +- if (slp) +- vec_oprnd = VEC_index (tree, vec_oprnds, i); +- else if (strided_store) +- /* For strided stores vectorized defs are interleaved in +- vect_permute_store_chain(). */ +- vec_oprnd = VEC_index (tree, result_chain, i); +- +- data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr, +- build_int_cst (reference_alias_ptr_type +- (DR_REF (first_dr)), 0)); +- pi = get_ptr_info (dataref_ptr); +- pi->align = TYPE_ALIGN_UNIT (vectype); +- if (aligned_access_p (first_dr)) +- pi->misalign = 0; +- else if (DR_MISALIGNMENT (first_dr) == -1) +- { +- TREE_TYPE (data_ref) +- = build_aligned_type (TREE_TYPE (data_ref), +- TYPE_ALIGN (TREE_TYPE (vectype))); +- pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype)); +- pi->misalign = 0; +- } +- else +- { +- TREE_TYPE (data_ref) +- = build_aligned_type (TREE_TYPE (data_ref), +- TYPE_ALIGN (TREE_TYPE (vectype))); +- pi->misalign = DR_MISALIGNMENT (first_dr); +- } +- +- /* Arguments are ready. Create the new vector stmt. */ +- new_stmt = gimple_build_assign (data_ref, vec_oprnd); ++ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, ++ TYPE_SIZE_UNIT (aggr_type)); ++ } ++ ++ if (store_lanes_p) ++ { ++ tree vec_array; ++ ++ /* Combine all the vectors into an array. */ ++ vec_array = create_vector_array (vectype, vec_num); ++ for (i = 0; i < vec_num; i++) ++ { ++ vec_oprnd = VEC_index (tree, dr_chain, i); ++ write_vector_array (stmt, gsi, vec_oprnd, vec_array, i); ++ } ++ ++ /* Emit: ++ MEM_REF[...all elements...] = STORE_LANES (VEC_ARRAY). */ ++ data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr); ++ new_stmt = gimple_build_call_internal (IFN_STORE_LANES, 1, vec_array); ++ gimple_call_set_lhs (new_stmt, data_ref); + vect_finish_stmt_generation (stmt, new_stmt, gsi); + mark_symbols_for_renaming (new_stmt); +- +- if (slp) +- continue; +- +- if (j == 0) +- STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt; ++ } ++ else ++ { ++ new_stmt = NULL; ++ if (strided_store) ++ { ++ result_chain = VEC_alloc (tree, heap, group_size); ++ /* Permute. */ ++ vect_permute_store_chain (dr_chain, group_size, stmt, gsi, ++ &result_chain); ++ } ++ ++ next_stmt = first_stmt; ++ for (i = 0; i < vec_num; i++) ++ { ++ struct ptr_info_def *pi; ++ ++ if (i > 0) ++ /* Bump the vector pointer. */ ++ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, ++ stmt, NULL_TREE); ++ ++ if (slp) ++ vec_oprnd = VEC_index (tree, vec_oprnds, i); ++ else if (strided_store) ++ /* For strided stores vectorized defs are interleaved in ++ vect_permute_store_chain(). */ ++ vec_oprnd = VEC_index (tree, result_chain, i); ++ ++ data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr, ++ build_int_cst (reference_alias_ptr_type ++ (DR_REF (first_dr)), 0)); ++ pi = get_ptr_info (dataref_ptr); ++ pi->align = TYPE_ALIGN_UNIT (vectype); ++ if (aligned_access_p (first_dr)) ++ pi->misalign = 0; ++ else if (DR_MISALIGNMENT (first_dr) == -1) ++ { ++ TREE_TYPE (data_ref) ++ = build_aligned_type (TREE_TYPE (data_ref), ++ TYPE_ALIGN (elem_type)); ++ pi->align = TYPE_ALIGN_UNIT (elem_type); ++ pi->misalign = 0; ++ } ++ else ++ { ++ TREE_TYPE (data_ref) ++ = build_aligned_type (TREE_TYPE (data_ref), ++ TYPE_ALIGN (elem_type)); ++ pi->misalign = DR_MISALIGNMENT (first_dr); ++ } ++ ++ /* Arguments are ready. Create the new vector stmt. */ ++ new_stmt = gimple_build_assign (data_ref, vec_oprnd); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ mark_symbols_for_renaming (new_stmt); ++ ++ if (slp) ++ continue; ++ ++ next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt)); ++ if (!next_stmt) ++ break; ++ } ++ } ++ if (!slp) ++ { ++ if (j == 0) ++ STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt; + else + STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt; +- + prev_stmt_info = vinfo_for_stmt (new_stmt); +- next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt)); +- if (!next_stmt) +- break; + } + } + +@@ -3805,6 +3930,7 @@ + bool nested_in_vect_loop = false; + struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr; + tree vectype = STMT_VINFO_VECTYPE (stmt_info); ++ tree elem_type; + tree new_temp; + enum machine_mode mode; + gimple new_stmt = NULL; +@@ -3821,6 +3947,7 @@ + gimple phi = NULL; + VEC(tree,heap) *dr_chain = NULL; + bool strided_load = false; ++ bool load_lanes_p = false; + gimple first_stmt; + tree scalar_type; + bool inv_p; +@@ -3833,6 +3960,7 @@ + enum tree_code code; + bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info); + int vf; ++ tree aggr_type; + + if (loop_vinfo) + { +@@ -3909,7 +4037,8 @@ + + /* The vector component type needs to be trivially convertible to the + scalar lhs. This should always be the case. */ +- if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), TREE_TYPE (vectype))) ++ elem_type = TREE_TYPE (vectype); ++ if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), elem_type)) + { + if (vect_print_dump_info (REPORT_DETAILS)) + fprintf (vect_dump, "??? operands of different types"); +@@ -3923,10 +4052,15 @@ + /* FORNOW */ + gcc_assert (! nested_in_vect_loop); + +- /* Check if interleaving is supported. */ +- if (!vect_strided_load_supported (vectype) +- && !PURE_SLP_STMT (stmt_info) && !slp) +- return false; ++ first_stmt = DR_GROUP_FIRST_DR (stmt_info); ++ if (!slp && !PURE_SLP_STMT (stmt_info)) ++ { ++ group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt)); ++ if (vect_load_lanes_supported (vectype, group_size)) ++ load_lanes_p = true; ++ else if (!vect_strided_load_supported (vectype, group_size)) ++ return false; ++ } + } + + if (negative) +@@ -3951,12 +4085,12 @@ + if (!vec_stmt) /* transformation not required. */ + { + STMT_VINFO_TYPE (stmt_info) = load_vec_info_type; +- vect_model_load_cost (stmt_info, ncopies, NULL); ++ vect_model_load_cost (stmt_info, ncopies, load_lanes_p, NULL); + return true; + } + + if (vect_print_dump_info (REPORT_DETAILS)) +- fprintf (vect_dump, "transform load."); ++ fprintf (vect_dump, "transform load. ncopies = %d", ncopies); + + /** Transform. **/ + +@@ -3982,8 +4116,6 @@ + } + else + vec_num = group_size; +- +- dr_chain = VEC_alloc (tree, heap, vec_num); + } + else + { +@@ -3994,6 +4126,11 @@ + + alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false); + gcc_assert (alignment_support_scheme); ++ /* Targets with load-lane instructions must not require explicit ++ realignment. */ ++ gcc_assert (!load_lanes_p ++ || alignment_support_scheme == dr_aligned ++ || alignment_support_scheme == dr_unaligned_supported); + + /* In case the vectorization factor (VF) is bigger than the number + of elements that we can fit in a vectype (nunits), we have to generate +@@ -4125,208 +4262,252 @@ + if (negative) + offset = size_int (-TYPE_VECTOR_SUBPARTS (vectype) + 1); + ++ if (load_lanes_p) ++ aggr_type = build_array_type_nelts (elem_type, vec_num * nunits); ++ else ++ aggr_type = vectype; ++ + prev_stmt_info = NULL; + for (j = 0; j < ncopies; j++) + { + /* 1. Create the vector pointer update chain. */ + if (j == 0) +- dataref_ptr = vect_create_data_ref_ptr (first_stmt, ++ dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, + at_loop, offset, + &dummy, &ptr_incr, false, + &inv_p); + else +- dataref_ptr = +- bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE); +- +- for (i = 0; i < vec_num; i++) ++ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, ++ TYPE_SIZE_UNIT (aggr_type)); ++ ++ if (strided_load || slp_perm) ++ dr_chain = VEC_alloc (tree, heap, vec_num); ++ ++ if (load_lanes_p) + { +- if (i > 0) +- dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, +- NULL_TREE); +- +- /* 2. Create the vector-load in the loop. */ +- switch (alignment_support_scheme) +- { +- case dr_aligned: +- case dr_unaligned_supported: +- { +- struct ptr_info_def *pi; +- data_ref +- = build2 (MEM_REF, vectype, dataref_ptr, +- build_int_cst (reference_alias_ptr_type +- (DR_REF (first_dr)), 0)); +- pi = get_ptr_info (dataref_ptr); +- pi->align = TYPE_ALIGN_UNIT (vectype); +- if (alignment_support_scheme == dr_aligned) +- { +- gcc_assert (aligned_access_p (first_dr)); +- pi->misalign = 0; +- } +- else if (DR_MISALIGNMENT (first_dr) == -1) +- { +- TREE_TYPE (data_ref) +- = build_aligned_type (TREE_TYPE (data_ref), +- TYPE_ALIGN (TREE_TYPE (vectype))); +- pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype)); +- pi->misalign = 0; +- } +- else +- { +- TREE_TYPE (data_ref) +- = build_aligned_type (TREE_TYPE (data_ref), +- TYPE_ALIGN (TREE_TYPE (vectype))); +- pi->misalign = DR_MISALIGNMENT (first_dr); +- } +- break; +- } +- case dr_explicit_realign: +- { +- tree ptr, bump; +- tree vs_minus_1 = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1); +- +- if (compute_in_loop) +- msq = vect_setup_realignment (first_stmt, gsi, +- &realignment_token, +- dr_explicit_realign, +- dataref_ptr, NULL); +- +- new_stmt = gimple_build_assign_with_ops +- (BIT_AND_EXPR, NULL_TREE, dataref_ptr, +- build_int_cst +- (TREE_TYPE (dataref_ptr), +- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype))); +- ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt); +- gimple_assign_set_lhs (new_stmt, ptr); +- vect_finish_stmt_generation (stmt, new_stmt, gsi); +- data_ref +- = build2 (MEM_REF, vectype, ptr, +- build_int_cst (reference_alias_ptr_type +- (DR_REF (first_dr)), 0)); +- vec_dest = vect_create_destination_var (scalar_dest, vectype); +- new_stmt = gimple_build_assign (vec_dest, data_ref); +- new_temp = make_ssa_name (vec_dest, new_stmt); +- gimple_assign_set_lhs (new_stmt, new_temp); +- gimple_set_vdef (new_stmt, gimple_vdef (stmt)); +- gimple_set_vuse (new_stmt, gimple_vuse (stmt)); +- vect_finish_stmt_generation (stmt, new_stmt, gsi); +- msq = new_temp; +- +- bump = size_binop (MULT_EXPR, vs_minus_1, +- TYPE_SIZE_UNIT (scalar_type)); +- ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump); +- new_stmt = gimple_build_assign_with_ops +- (BIT_AND_EXPR, NULL_TREE, ptr, +- build_int_cst +- (TREE_TYPE (ptr), +- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype))); +- ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt); +- gimple_assign_set_lhs (new_stmt, ptr); +- vect_finish_stmt_generation (stmt, new_stmt, gsi); +- data_ref +- = build2 (MEM_REF, vectype, ptr, +- build_int_cst (reference_alias_ptr_type +- (DR_REF (first_dr)), 0)); +- break; +- } +- case dr_explicit_realign_optimized: +- new_stmt = gimple_build_assign_with_ops +- (BIT_AND_EXPR, NULL_TREE, dataref_ptr, +- build_int_cst +- (TREE_TYPE (dataref_ptr), +- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype))); +- new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt); +- gimple_assign_set_lhs (new_stmt, new_temp); +- vect_finish_stmt_generation (stmt, new_stmt, gsi); +- data_ref +- = build2 (MEM_REF, vectype, new_temp, +- build_int_cst (reference_alias_ptr_type +- (DR_REF (first_dr)), 0)); +- break; +- default: +- gcc_unreachable (); +- } +- vec_dest = vect_create_destination_var (scalar_dest, vectype); +- new_stmt = gimple_build_assign (vec_dest, data_ref); +- new_temp = make_ssa_name (vec_dest, new_stmt); +- gimple_assign_set_lhs (new_stmt, new_temp); ++ tree vec_array; ++ ++ vec_array = create_vector_array (vectype, vec_num); ++ ++ /* Emit: ++ VEC_ARRAY = LOAD_LANES (MEM_REF[...all elements...]). */ ++ data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr); ++ new_stmt = gimple_build_call_internal (IFN_LOAD_LANES, 1, data_ref); ++ gimple_call_set_lhs (new_stmt, vec_array); + vect_finish_stmt_generation (stmt, new_stmt, gsi); + mark_symbols_for_renaming (new_stmt); + +- /* 3. Handle explicit realignment if necessary/supported. Create in +- loop: vec_dest = realign_load (msq, lsq, realignment_token) */ +- if (alignment_support_scheme == dr_explicit_realign_optimized +- || alignment_support_scheme == dr_explicit_realign) +- { +- tree tmp; +- +- lsq = gimple_assign_lhs (new_stmt); +- if (!realignment_token) +- realignment_token = dataref_ptr; ++ /* Extract each vector into an SSA_NAME. */ ++ for (i = 0; i < vec_num; i++) ++ { ++ new_temp = read_vector_array (stmt, gsi, scalar_dest, ++ vec_array, i); ++ VEC_quick_push (tree, dr_chain, new_temp); ++ } ++ ++ /* Record the mapping between SSA_NAMEs and statements. */ ++ vect_record_strided_load_vectors (stmt, dr_chain); ++ } ++ else ++ { ++ for (i = 0; i < vec_num; i++) ++ { ++ if (i > 0) ++ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, ++ stmt, NULL_TREE); ++ ++ /* 2. Create the vector-load in the loop. */ ++ switch (alignment_support_scheme) ++ { ++ case dr_aligned: ++ case dr_unaligned_supported: ++ { ++ struct ptr_info_def *pi; ++ data_ref ++ = build2 (MEM_REF, vectype, dataref_ptr, ++ build_int_cst (reference_alias_ptr_type ++ (DR_REF (first_dr)), 0)); ++ pi = get_ptr_info (dataref_ptr); ++ pi->align = TYPE_ALIGN_UNIT (vectype); ++ if (alignment_support_scheme == dr_aligned) ++ { ++ gcc_assert (aligned_access_p (first_dr)); ++ pi->misalign = 0; ++ } ++ else if (DR_MISALIGNMENT (first_dr) == -1) ++ { ++ TREE_TYPE (data_ref) ++ = build_aligned_type (TREE_TYPE (data_ref), ++ TYPE_ALIGN (elem_type)); ++ pi->align = TYPE_ALIGN_UNIT (elem_type); ++ pi->misalign = 0; ++ } ++ else ++ { ++ TREE_TYPE (data_ref) ++ = build_aligned_type (TREE_TYPE (data_ref), ++ TYPE_ALIGN (elem_type)); ++ pi->misalign = DR_MISALIGNMENT (first_dr); ++ } ++ break; ++ } ++ case dr_explicit_realign: ++ { ++ tree ptr, bump; ++ tree vs_minus_1 ++ = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1); ++ ++ if (compute_in_loop) ++ msq = vect_setup_realignment (first_stmt, gsi, ++ &realignment_token, ++ dr_explicit_realign, ++ dataref_ptr, NULL); ++ ++ new_stmt = gimple_build_assign_with_ops ++ (BIT_AND_EXPR, NULL_TREE, dataref_ptr, ++ build_int_cst ++ (TREE_TYPE (dataref_ptr), ++ -(HOST_WIDE_INT) ++ TYPE_ALIGN_UNIT (vectype))); ++ ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt); ++ gimple_assign_set_lhs (new_stmt, ptr); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ data_ref ++ = build2 (MEM_REF, vectype, ptr, ++ build_int_cst (reference_alias_ptr_type ++ (DR_REF (first_dr)), 0)); ++ vec_dest = vect_create_destination_var (scalar_dest, ++ vectype); ++ new_stmt = gimple_build_assign (vec_dest, data_ref); ++ new_temp = make_ssa_name (vec_dest, new_stmt); ++ gimple_assign_set_lhs (new_stmt, new_temp); ++ gimple_set_vdef (new_stmt, gimple_vdef (stmt)); ++ gimple_set_vuse (new_stmt, gimple_vuse (stmt)); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ msq = new_temp; ++ ++ bump = size_binop (MULT_EXPR, vs_minus_1, ++ TYPE_SIZE_UNIT (scalar_type)); ++ ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump); ++ new_stmt = gimple_build_assign_with_ops ++ (BIT_AND_EXPR, NULL_TREE, ptr, ++ build_int_cst ++ (TREE_TYPE (ptr), ++ -(HOST_WIDE_INT) ++ TYPE_ALIGN_UNIT (vectype))); ++ ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt); ++ gimple_assign_set_lhs (new_stmt, ptr); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ data_ref ++ = build2 (MEM_REF, vectype, ptr, ++ build_int_cst (reference_alias_ptr_type ++ (DR_REF (first_dr)), 0)); ++ break; ++ } ++ case dr_explicit_realign_optimized: ++ new_stmt = gimple_build_assign_with_ops ++ (BIT_AND_EXPR, NULL_TREE, dataref_ptr, ++ build_int_cst ++ (TREE_TYPE (dataref_ptr), ++ -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype))); ++ new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr), ++ new_stmt); ++ gimple_assign_set_lhs (new_stmt, new_temp); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ data_ref ++ = build2 (MEM_REF, vectype, new_temp, ++ build_int_cst (reference_alias_ptr_type ++ (DR_REF (first_dr)), 0)); ++ break; ++ default: ++ gcc_unreachable (); ++ } + vec_dest = vect_create_destination_var (scalar_dest, vectype); +- tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq, +- realignment_token); +- new_stmt = gimple_build_assign (vec_dest, tmp); ++ new_stmt = gimple_build_assign (vec_dest, data_ref); + new_temp = make_ssa_name (vec_dest, new_stmt); + gimple_assign_set_lhs (new_stmt, new_temp); + vect_finish_stmt_generation (stmt, new_stmt, gsi); +- +- if (alignment_support_scheme == dr_explicit_realign_optimized) +- { +- gcc_assert (phi); +- if (i == vec_num - 1 && j == ncopies - 1) +- add_phi_arg (phi, lsq, loop_latch_edge (containing_loop), +- UNKNOWN_LOCATION); +- msq = lsq; +- } +- } +- +- /* 4. Handle invariant-load. */ +- if (inv_p && !bb_vinfo) +- { +- gcc_assert (!strided_load); +- gcc_assert (nested_in_vect_loop_p (loop, stmt)); +- if (j == 0) +- { +- int k; +- tree t = NULL_TREE; +- tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type); +- +- /* CHECKME: bitpos depends on endianess? */ +- bitpos = bitsize_zero_node; +- vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp, +- bitsize, bitpos); +- vec_dest = +- vect_create_destination_var (scalar_dest, NULL_TREE); +- new_stmt = gimple_build_assign (vec_dest, vec_inv); +- new_temp = make_ssa_name (vec_dest, new_stmt); ++ mark_symbols_for_renaming (new_stmt); ++ ++ /* 3. Handle explicit realignment if necessary/supported. ++ Create in loop: ++ vec_dest = realign_load (msq, lsq, realignment_token) */ ++ if (alignment_support_scheme == dr_explicit_realign_optimized ++ || alignment_support_scheme == dr_explicit_realign) ++ { ++ tree tmp; ++ ++ lsq = gimple_assign_lhs (new_stmt); ++ if (!realignment_token) ++ realignment_token = dataref_ptr; ++ vec_dest = vect_create_destination_var (scalar_dest, vectype); ++ tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq, ++ realignment_token); ++ new_stmt = gimple_build_assign (vec_dest, tmp); ++ new_temp = make_ssa_name (vec_dest, new_stmt); + gimple_assign_set_lhs (new_stmt, new_temp); + vect_finish_stmt_generation (stmt, new_stmt, gsi); + +- for (k = nunits - 1; k >= 0; --k) +- t = tree_cons (NULL_TREE, new_temp, t); +- /* FIXME: use build_constructor directly. */ +- vec_inv = build_constructor_from_list (vectype, t); +- new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi); ++ if (alignment_support_scheme == dr_explicit_realign_optimized) ++ { ++ gcc_assert (phi); ++ if (i == vec_num - 1 && j == ncopies - 1) ++ add_phi_arg (phi, lsq, ++ loop_latch_edge (containing_loop), ++ UNKNOWN_LOCATION); ++ msq = lsq; ++ } ++ } ++ ++ /* 4. Handle invariant-load. */ ++ if (inv_p && !bb_vinfo) ++ { ++ gcc_assert (!strided_load); ++ gcc_assert (nested_in_vect_loop_p (loop, stmt)); ++ if (j == 0) ++ { ++ int k; ++ tree t = NULL_TREE; ++ tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type); ++ ++ /* CHECKME: bitpos depends on endianess? */ ++ bitpos = bitsize_zero_node; ++ vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp, ++ bitsize, bitpos); ++ vec_dest = vect_create_destination_var (scalar_dest, ++ NULL_TREE); ++ new_stmt = gimple_build_assign (vec_dest, vec_inv); ++ new_temp = make_ssa_name (vec_dest, new_stmt); ++ gimple_assign_set_lhs (new_stmt, new_temp); ++ vect_finish_stmt_generation (stmt, new_stmt, gsi); ++ ++ for (k = nunits - 1; k >= 0; --k) ++ t = tree_cons (NULL_TREE, new_temp, t); ++ /* FIXME: use build_constructor directly. */ ++ vec_inv = build_constructor_from_list (vectype, t); ++ new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi); ++ new_stmt = SSA_NAME_DEF_STMT (new_temp); ++ } ++ else ++ gcc_unreachable (); /* FORNOW. */ ++ } ++ ++ if (negative) ++ { ++ new_temp = reverse_vec_elements (new_temp, stmt, gsi); + new_stmt = SSA_NAME_DEF_STMT (new_temp); + } +- else +- gcc_unreachable (); /* FORNOW. */ +- } +- +- if (negative) +- { +- new_temp = reverse_vec_elements (new_temp, stmt, gsi); +- new_stmt = SSA_NAME_DEF_STMT (new_temp); +- } +- +- /* Collect vector loads and later create their permutation in +- vect_transform_strided_load (). */ +- if (strided_load || slp_perm) +- VEC_quick_push (tree, dr_chain, new_temp); +- +- /* Store vector loads in the corresponding SLP_NODE. */ +- if (slp && !slp_perm) +- VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node), new_stmt); ++ ++ /* Collect vector loads and later create their permutation in ++ vect_transform_strided_load (). */ ++ if (strided_load || slp_perm) ++ VEC_quick_push (tree, dr_chain, new_temp); ++ ++ /* Store vector loads in the corresponding SLP_NODE. */ ++ if (slp && !slp_perm) ++ VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node), ++ new_stmt); ++ } + } + + if (slp && !slp_perm) +@@ -4345,12 +4526,9 @@ + { + if (strided_load) + { +- if (!vect_transform_strided_load (stmt, dr_chain, group_size, gsi)) +- return false; +- ++ if (!load_lanes_p) ++ vect_transform_strided_load (stmt, dr_chain, group_size, gsi); + *vec_stmt = STMT_VINFO_VEC_STMT (stmt_info); +- VEC_free (tree, heap, dr_chain); +- dr_chain = VEC_alloc (tree, heap, group_size); + } + else + { +@@ -4361,11 +4539,10 @@ + prev_stmt_info = vinfo_for_stmt (new_stmt); + } + } ++ if (dr_chain) ++ VEC_free (tree, heap, dr_chain); + } + +- if (dr_chain) +- VEC_free (tree, heap, dr_chain); +- + return true; + } + +@@ -4769,27 +4946,6 @@ + return false; + } + +- if (!PURE_SLP_STMT (stmt_info)) +- { +- /* Groups of strided accesses whose size is not a power of 2 are not +- vectorizable yet using loop-vectorization. Therefore, if this stmt +- feeds non-SLP-able stmts (i.e., this stmt has to be both SLPed and +- loop-based vectorized), the loop cannot be vectorized. */ +- if (STMT_VINFO_STRIDED_ACCESS (stmt_info) +- && exact_log2 (DR_GROUP_SIZE (vinfo_for_stmt ( +- DR_GROUP_FIRST_DR (stmt_info)))) == -1) +- { +- if (vect_print_dump_info (REPORT_DETAILS)) +- { +- fprintf (vect_dump, "not vectorized: the size of group " +- "of strided accesses is not a power of 2"); +- print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM); +- } +- +- return false; +- } +- } +- + return true; + } + + +=== modified file 'gcc/tree-vectorizer.h' +--- old/gcc/tree-vectorizer.h 2010-12-23 16:25:52 +0000 ++++ new/gcc/tree-vectorizer.h 2011-05-05 15:43:06 +0000 +@@ -788,9 +788,9 @@ + extern tree vectorizable_function (gimple, tree, tree); + extern void vect_model_simple_cost (stmt_vec_info, int, enum vect_def_type *, + slp_tree); +-extern void vect_model_store_cost (stmt_vec_info, int, enum vect_def_type, +- slp_tree); +-extern void vect_model_load_cost (stmt_vec_info, int, slp_tree); ++extern void vect_model_store_cost (stmt_vec_info, int, bool, ++ enum vect_def_type, slp_tree); ++extern void vect_model_load_cost (stmt_vec_info, int, bool, slp_tree); + extern void vect_finish_stmt_generation (gimple, gimple, + gimple_stmt_iterator *); + extern bool vect_mark_stmts_to_be_vectorized (loop_vec_info); +@@ -823,21 +823,22 @@ + extern bool vect_analyze_data_ref_accesses (loop_vec_info, bb_vec_info); + extern bool vect_prune_runtime_alias_test_list (loop_vec_info); + extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *); +-extern tree vect_create_data_ref_ptr (gimple, struct loop *, tree, tree *, +- gimple *, bool, bool *); ++extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree, ++ tree *, gimple *, bool, bool *); + extern tree bump_vector_ptr (tree, gimple, gimple_stmt_iterator *, gimple, tree); + extern tree vect_create_destination_var (tree, tree); +-extern bool vect_strided_store_supported (tree); +-extern bool vect_strided_load_supported (tree); +-extern bool vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple, ++extern bool vect_strided_store_supported (tree, unsigned HOST_WIDE_INT); ++extern bool vect_store_lanes_supported (tree, unsigned HOST_WIDE_INT); ++extern bool vect_strided_load_supported (tree, unsigned HOST_WIDE_INT); ++extern bool vect_load_lanes_supported (tree, unsigned HOST_WIDE_INT); ++extern void vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple, + gimple_stmt_iterator *, VEC(tree,heap) **); + extern tree vect_setup_realignment (gimple, gimple_stmt_iterator *, tree *, + enum dr_alignment_support, tree, + struct loop **); +-extern bool vect_permute_load_chain (VEC(tree,heap) *,unsigned int, gimple, +- gimple_stmt_iterator *, VEC(tree,heap) **); +-extern bool vect_transform_strided_load (gimple, VEC(tree,heap) *, int, ++extern void vect_transform_strided_load (gimple, VEC(tree,heap) *, int, + gimple_stmt_iterator *); ++extern void vect_record_strided_load_vectors (gimple, VEC(tree,heap) *); + extern int vect_get_place_in_interleaving_chain (gimple, gimple); + extern tree vect_get_new_vect_var (tree, enum vect_var_kind, const char *); + extern tree vect_create_addr_base_for_vector_ref (gimple, gimple_seq *, + +=== modified file 'gcc/tree.c' +--- old/gcc/tree.c 2011-05-18 13:29:24 +0000 ++++ new/gcc/tree.c 2011-06-02 12:12:00 +0000 +@@ -7321,6 +7321,15 @@ + return build_array_type_1 (elt_type, index_type, false); + } + ++/* Return a representation of ELT_TYPE[NELTS], using indices of type ++ sizetype. */ ++ ++tree ++build_array_type_nelts (tree elt_type, unsigned HOST_WIDE_INT nelts) ++{ ++ return build_array_type (elt_type, build_index_type (size_int (nelts - 1))); ++} ++ + /* Recursively examines the array elements of TYPE, until a non-array + element type is found. */ + + +=== modified file 'gcc/tree.h' +--- old/gcc/tree.h 2011-03-11 22:38:58 +0000 ++++ new/gcc/tree.h 2011-05-05 15:43:06 +0000 +@@ -4192,6 +4192,7 @@ + extern tree build_index_type (tree); + extern tree build_array_type (tree, tree); + extern tree build_nonshared_array_type (tree, tree); ++extern tree build_array_type_nelts (tree, unsigned HOST_WIDE_INT); + extern tree build_function_type (tree, tree); + extern tree build_function_type_list (tree, ...); + extern tree build_function_type_skip_args (tree, bitmap); + +=== modified file 'gcc/value-prof.c' +--- old/gcc/value-prof.c 2011-01-29 03:54:56 +0000 ++++ new/gcc/value-prof.c 2011-05-05 15:42:22 +0000 +@@ -1242,6 +1242,9 @@ + if (TREE_CODE (callee) == FUNCTION_DECL) + return false; + ++ if (gimple_call_internal_p (stmt)) ++ return false; ++ + histogram = gimple_histogram_value_of_type (cfun, stmt, HIST_TYPE_INDIR_CALL); + if (!histogram) + return false; +@@ -1630,6 +1633,7 @@ + tree callee; + + if (gimple_code (stmt) != GIMPLE_CALL ++ || gimple_call_internal_p (stmt) + || gimple_call_fndecl (stmt) != NULL_TREE) + return; + + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch new file mode 100644 index 0000000000..b64991836b --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106754.patch @@ -0,0 +1,329 @@ +2011-06-07 Andrew Stubbs + + Backport from FSF: + + 2011-06-07 Andrew Stubbs + + gcc/ + * config/arm/arm.md (*maddhidi4tb, *maddhidi4tt): New define_insns. + (*maddhisi4tb, *maddhisi4tt): New define_insns. + + gcc/testsuite/ + * gcc.target/arm/smlatb-1.c: New file. + * gcc.target/arm/smlatt-1.c: New file. + * gcc.target/arm/smlaltb-1.c: New file. + * gcc.target/arm/smlaltt-1.c: New file. + +2011-06-07 Andrew Stubbs + + Backport from FSF: + + 2011-06-07 Bernd Schmidt + Andrew Stubbs + + gcc/ + * simplify-rtx.c (simplify_unary_operation_1): Canonicalize widening + multiplies. + * doc/md.texi (Canonicalization of Instructions): Document widening + multiply canonicalization. + + gcc/testsuite/ + * gcc.target/arm/mla-2.c: New test. + +=== modified file 'gcc/config/arm/arm.md' +--- old/gcc/config/arm/arm.md 2011-05-13 13:42:39 +0000 ++++ new/gcc/config/arm/arm.md 2011-06-02 15:58:33 +0000 +@@ -1809,6 +1809,36 @@ + (set_attr "predicable" "yes")] + ) + ++;; Note: there is no maddhisi4ibt because this one is canonical form ++(define_insn "*maddhisi4tb" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (plus:SI (mult:SI (ashiftrt:SI ++ (match_operand:SI 1 "s_register_operand" "r") ++ (const_int 16)) ++ (sign_extend:SI ++ (match_operand:HI 2 "s_register_operand" "r"))) ++ (match_operand:SI 3 "s_register_operand" "r")))] ++ "TARGET_DSP_MULTIPLY" ++ "smlatb%?\\t%0, %1, %2, %3" ++ [(set_attr "insn" "smlaxy") ++ (set_attr "predicable" "yes")] ++) ++ ++(define_insn "*maddhisi4tt" ++ [(set (match_operand:SI 0 "s_register_operand" "=r") ++ (plus:SI (mult:SI (ashiftrt:SI ++ (match_operand:SI 1 "s_register_operand" "r") ++ (const_int 16)) ++ (ashiftrt:SI ++ (match_operand:SI 2 "s_register_operand" "r") ++ (const_int 16))) ++ (match_operand:SI 3 "s_register_operand" "r")))] ++ "TARGET_DSP_MULTIPLY" ++ "smlatt%?\\t%0, %1, %2, %3" ++ [(set_attr "insn" "smlaxy") ++ (set_attr "predicable" "yes")] ++) ++ + (define_insn "*maddhidi4" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI +@@ -1822,6 +1852,39 @@ + [(set_attr "insn" "smlalxy") + (set_attr "predicable" "yes")]) + ++;; Note: there is no maddhidi4ibt because this one is canonical form ++(define_insn "*maddhidi4tb" ++ [(set (match_operand:DI 0 "s_register_operand" "=r") ++ (plus:DI ++ (mult:DI (sign_extend:DI ++ (ashiftrt:SI ++ (match_operand:SI 1 "s_register_operand" "r") ++ (const_int 16))) ++ (sign_extend:DI ++ (match_operand:HI 2 "s_register_operand" "r"))) ++ (match_operand:DI 3 "s_register_operand" "0")))] ++ "TARGET_DSP_MULTIPLY" ++ "smlaltb%?\\t%Q0, %R0, %1, %2" ++ [(set_attr "insn" "smlalxy") ++ (set_attr "predicable" "yes")]) ++ ++(define_insn "*maddhidi4tt" ++ [(set (match_operand:DI 0 "s_register_operand" "=r") ++ (plus:DI ++ (mult:DI (sign_extend:DI ++ (ashiftrt:SI ++ (match_operand:SI 1 "s_register_operand" "r") ++ (const_int 16))) ++ (sign_extend:DI ++ (ashiftrt:SI ++ (match_operand:SI 2 "s_register_operand" "r") ++ (const_int 16)))) ++ (match_operand:DI 3 "s_register_operand" "0")))] ++ "TARGET_DSP_MULTIPLY" ++ "smlaltt%?\\t%Q0, %R0, %1, %2" ++ [(set_attr "insn" "smlalxy") ++ (set_attr "predicable" "yes")]) ++ + (define_expand "mulsf3" + [(set (match_operand:SF 0 "s_register_operand" "") + (mult:SF (match_operand:SF 1 "s_register_operand" "") + +=== modified file 'gcc/doc/md.texi' +--- old/gcc/doc/md.texi 2011-05-05 15:43:06 +0000 ++++ new/gcc/doc/md.texi 2011-06-07 11:18:20 +0000 +@@ -5929,6 +5929,23 @@ + will be written using @code{zero_extract} rather than the equivalent + @code{and} or @code{sign_extract} operations. + ++@cindex @code{mult}, canonicalization of ++@item ++@code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x}) ++(sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1} ++(sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise ++for @code{zero_extend}. ++ ++@item ++@code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2} ++@var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted ++to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2} ++@var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for ++patterns using @code{zero_extend} and @code{lshiftrt}. If the second ++operand of @code{mult} is also a shift, then that is extended also. ++This transformation is only applied when it can be proven that the ++original operation had sufficient precision to prevent overflow. ++ + @end itemize + + Further canonicalization rules are defined in the function + +=== modified file 'gcc/simplify-rtx.c' +--- old/gcc/simplify-rtx.c 2011-05-27 14:31:18 +0000 ++++ new/gcc/simplify-rtx.c 2011-06-02 12:32:16 +0000 +@@ -1000,6 +1000,48 @@ + && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF) + return XEXP (op, 0); + ++ /* Extending a widening multiplication should be canonicalized to ++ a wider widening multiplication. */ ++ if (GET_CODE (op) == MULT) ++ { ++ rtx lhs = XEXP (op, 0); ++ rtx rhs = XEXP (op, 1); ++ enum rtx_code lcode = GET_CODE (lhs); ++ enum rtx_code rcode = GET_CODE (rhs); ++ ++ /* Widening multiplies usually extend both operands, but sometimes ++ they use a shift to extract a portion of a register. */ ++ if ((lcode == SIGN_EXTEND ++ || (lcode == ASHIFTRT && CONST_INT_P (XEXP (lhs, 1)))) ++ && (rcode == SIGN_EXTEND ++ || (rcode == ASHIFTRT && CONST_INT_P (XEXP (rhs, 1))))) ++ { ++ enum machine_mode lmode = GET_MODE (lhs); ++ enum machine_mode rmode = GET_MODE (rhs); ++ int bits; ++ ++ if (lcode == ASHIFTRT) ++ /* Number of bits not shifted off the end. */ ++ bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1)); ++ else /* lcode == SIGN_EXTEND */ ++ /* Size of inner mode. */ ++ bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0))); ++ ++ if (rcode == ASHIFTRT) ++ bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1)); ++ else /* rcode == SIGN_EXTEND */ ++ bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0))); ++ ++ /* We can only widen multiplies if the result is mathematiclly ++ equivalent. I.e. if overflow was impossible. */ ++ if (bits <= GET_MODE_PRECISION (GET_MODE (op))) ++ return simplify_gen_binary ++ (MULT, mode, ++ simplify_gen_unary (SIGN_EXTEND, mode, lhs, lmode), ++ simplify_gen_unary (SIGN_EXTEND, mode, rhs, rmode)); ++ } ++ } ++ + /* Check for a sign extension of a subreg of a promoted + variable, where the promotion is sign-extended, and the + target mode is the same as the variable's promotion. */ +@@ -1071,6 +1113,48 @@ + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))) + return rtl_hooks.gen_lowpart_no_emit (mode, op); + ++ /* Extending a widening multiplication should be canonicalized to ++ a wider widening multiplication. */ ++ if (GET_CODE (op) == MULT) ++ { ++ rtx lhs = XEXP (op, 0); ++ rtx rhs = XEXP (op, 1); ++ enum rtx_code lcode = GET_CODE (lhs); ++ enum rtx_code rcode = GET_CODE (rhs); ++ ++ /* Widening multiplies usually extend both operands, but sometimes ++ they use a shift to extract a portion of a register. */ ++ if ((lcode == ZERO_EXTEND ++ || (lcode == LSHIFTRT && CONST_INT_P (XEXP (lhs, 1)))) ++ && (rcode == ZERO_EXTEND ++ || (rcode == LSHIFTRT && CONST_INT_P (XEXP (rhs, 1))))) ++ { ++ enum machine_mode lmode = GET_MODE (lhs); ++ enum machine_mode rmode = GET_MODE (rhs); ++ int bits; ++ ++ if (lcode == LSHIFTRT) ++ /* Number of bits not shifted off the end. */ ++ bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1)); ++ else /* lcode == ZERO_EXTEND */ ++ /* Size of inner mode. */ ++ bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0))); ++ ++ if (rcode == LSHIFTRT) ++ bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1)); ++ else /* rcode == ZERO_EXTEND */ ++ bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0))); ++ ++ /* We can only widen multiplies if the result is mathematiclly ++ equivalent. I.e. if overflow was impossible. */ ++ if (bits <= GET_MODE_PRECISION (GET_MODE (op))) ++ return simplify_gen_binary ++ (MULT, mode, ++ simplify_gen_unary (ZERO_EXTEND, mode, lhs, lmode), ++ simplify_gen_unary (ZERO_EXTEND, mode, rhs, rmode)); ++ } ++ } ++ + /* (zero_extend:M (zero_extend:N )) is (zero_extend:M ). */ + if (GET_CODE (op) == ZERO_EXTEND) + return simplify_gen_unary (ZERO_EXTEND, mode, XEXP (op, 0), + +=== added file 'gcc/testsuite/gcc.target/arm/mla-2.c' +--- old/gcc/testsuite/gcc.target/arm/mla-2.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/mla-2.c 2011-06-02 12:32:16 +0000 +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv7-a" } */ ++ ++long long foolong (long long x, short *a, short *b) ++{ ++ return x + *a * *b; ++} ++ ++/* { dg-final { scan-assembler "smlalbb" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/smlaltb-1.c' +--- old/gcc/testsuite/gcc.target/arm/smlaltb-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/smlaltb-1.c 2011-06-02 15:58:33 +0000 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv7-a" } */ ++ ++long long int ++foo (long long x, int in) ++{ ++ short a = in & 0xffff; ++ short b = (in & 0xffff0000) >> 16; ++ ++ return x + b * a; ++} ++ ++/* { dg-final { scan-assembler "smlaltb" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/smlaltt-1.c' +--- old/gcc/testsuite/gcc.target/arm/smlaltt-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/smlaltt-1.c 2011-06-02 15:58:33 +0000 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv7-a" } */ ++ ++long long int ++foo (long long x, int in1, int in2) ++{ ++ short a = (in1 & 0xffff0000) >> 16; ++ short b = (in2 & 0xffff0000) >> 16; ++ ++ return x + b * a; ++} ++ ++/* { dg-final { scan-assembler "smlaltt" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/smlatb-1.c' +--- old/gcc/testsuite/gcc.target/arm/smlatb-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/smlatb-1.c 2011-06-02 15:58:33 +0000 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv7-a" } */ ++ ++int ++foo (int x, int in) ++{ ++ short a = in & 0xffff; ++ short b = (in & 0xffff0000) >> 16; ++ ++ return x + b * a; ++} ++ ++/* { dg-final { scan-assembler "smlatb" } } */ + +=== added file 'gcc/testsuite/gcc.target/arm/smlatt-1.c' +--- old/gcc/testsuite/gcc.target/arm/smlatt-1.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/smlatt-1.c 2011-06-02 15:58:33 +0000 +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=armv7-a" } */ ++ ++int ++foo (int x, int in1, int in2) ++{ ++ short a = (in1 & 0xffff0000) >> 16; ++ short b = (in2 & 0xffff0000) >> 16; ++ ++ return x + b * a; ++} ++ ++/* { dg-final { scan-assembler "smlatt" } } */ + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch new file mode 100644 index 0000000000..b8f587c9f4 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-4.6.0/linaro/gcc-4.6-linaro-r106755.patch @@ -0,0 +1,120 @@ +2011-06-10 Ramana Radhakrishnan + + Backport from mainline: + gcc/ + 2011-06-02 Ramana Radhakrishnan + * config/arm/neon.md (orndi3_neon): Actually split it. + + +2011-06-10 Ramana Radhakrishnan + + Backport from mainline. + gcc/ + 2011-05-26 Ramana Radhakrishnan + + * config/arm/neon.md ("orn3_neon"): Canonicalize not. + ("orndi3_neon"): Likewise. + ("bic3_neon"): Likewise. + + gcc/testsuite + 2011-05-26 Ramana Radhakrishnan + + * gcc.target/arm/neon-vorn-vbic.c: New test. + +=== modified file 'gcc/config/arm/neon.md' +--- old/gcc/config/arm/neon.md 2011-06-02 12:12:00 +0000 ++++ new/gcc/config/arm/neon.md 2011-06-04 00:04:47 +0000 +@@ -783,30 +783,57 @@ + + (define_insn "orn3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") +- (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w") +- (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))] ++ (ior:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w")) ++ (match_operand:VDQ 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vorn\t%0, %1, %2" + [(set_attr "neon_type" "neon_int_1")] + ) + +-(define_insn "orndi3_neon" +- [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") +- (ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0") +- (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))] ++;; TODO: investigate whether we should disable ++;; this and bicdi3_neon for the A8 in line with the other ++;; changes above. ++(define_insn_and_split "orndi3_neon" ++ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r") ++ (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r")) ++ (match_operand:DI 1 "s_register_operand" "w,r,r,0")))] + "TARGET_NEON" + "@ + vorn\t%P0, %P1, %P2 + # ++ # + #" +- [(set_attr "neon_type" "neon_int_1,*,*") +- (set_attr "length" "*,8,8")] ++ "reload_completed && ++ (TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))" ++ [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1))) ++ (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))] ++ " ++ { ++ if (TARGET_THUMB2) ++ { ++ operands[3] = gen_highpart (SImode, operands[0]); ++ operands[0] = gen_lowpart (SImode, operands[0]); ++ operands[4] = gen_highpart (SImode, operands[2]); ++ operands[2] = gen_lowpart (SImode, operands[2]); ++ operands[5] = gen_highpart (SImode, operands[1]); ++ operands[1] = gen_lowpart (SImode, operands[1]); ++ } ++ else ++ { ++ emit_insn (gen_one_cmpldi2 (operands[0], operands[2])); ++ emit_insn (gen_iordi3 (operands[0], operands[1], operands[0])); ++ DONE; ++ } ++ }" ++ [(set_attr "neon_type" "neon_int_1,*,*,*") ++ (set_attr "length" "*,16,8,8") ++ (set_attr "arch" "any,a,t2,t2")] + ) + + (define_insn "bic3_neon" + [(set (match_operand:VDQ 0 "s_register_operand" "=w") +- (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w") +- (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))] ++ (and:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w")) ++ (match_operand:VDQ 1 "s_register_operand" "w")))] + "TARGET_NEON" + "vbic\t%0, %1, %2" + [(set_attr "neon_type" "neon_int_1")] + +=== added file 'gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c' +--- old/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c 1970-01-01 00:00:00 +0000 ++++ new/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c 2011-06-03 23:50:02 +0000 +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target arm_neon_ok } */ ++/* { dg-options "-O2 -ftree-vectorize" } */ ++/* { dg-add-options arm_neon } */ ++ ++void bor (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b) ++{ ++ int i; ++ for (i = 0; i < 9; i++) ++ c[i] = b[i] | (~a[i]); ++} ++void bic (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b) ++{ ++ int i; ++ for (i = 0; i < 9; i++) ++ c[i] = b[i] & (~a[i]); ++} ++ ++/* { dg-final { scan-assembler "vorn\\t" } } */ ++/* { dg-final { scan-assembler "vbic\\t" } } */ + diff --git a/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc b/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc index 5f506f00d7..e3f6114e5d 100644 --- a/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +++ b/meta-oe/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc @@ -2,7 +2,6 @@ GCC-4_6-BRANCH-LINARO-BACKPORTS = " \ file://linaro/gcc-4.6-linaro-r106720.patch \ file://linaro/gcc-4.6-linaro-r106723.patch \ file://linaro/gcc-4.6-linaro-r106729.patch \ -file://linaro/gcc-4.6-linaro-r106731.patch \ file://linaro/gcc-4.6-linaro-r106733.patch \ file://linaro/gcc-4.6-linaro-r106737.patch \ file://linaro/gcc-4.6-linaro-r106738.patch \ @@ -15,4 +14,8 @@ file://linaro/gcc-4.6-linaro-r106744.patch \ file://linaro/gcc-4.6-linaro-r106746.patch \ file://linaro/gcc-4.6-linaro-r106747.patch \ file://linaro/gcc-4.6-linaro-r106750.patch \ +file://linaro/gcc-4.6-linaro-r106751.patch \ +file://linaro/gcc-4.6-linaro-r106753.patch \ +file://linaro/gcc-4.6-linaro-r106754.patch \ +file://linaro/gcc-4.6-linaro-r106755.patch \ " diff --git a/meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc b/meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc new file mode 100644 index 0000000000..38167bf303 --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-common-4.6.inc @@ -0,0 +1,3 @@ +# this will prepend this layer to FILESPATH +FILESEXTRAPATHS := "${THISDIR}/gcc-4.6.0" +PRINC = "0" diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-cross-canadian_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-cross-initial_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-cross-intermediate_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-cross_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-crosssdk_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc-runtime_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/gcc_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" diff --git a/meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend b/meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend new file mode 100644 index 0000000000..fc419b62bd --- /dev/null +++ b/meta-oe/recipes-devtools/gcc/libgcc_4.6.0.bbappend @@ -0,0 +1,3 @@ +require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc +require recipes-devtools/gcc/gcc-common-4.6.inc +SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}" -- cgit v1.2.3-54-g00ecf