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From 0c4ba4947d1630f2e13fc260399f0892b2c9b323 Mon Sep 17 00:00:00 2001
From: Naveen Saini <naveen.kumar.saini@intel.com>
Date: Fri, 27 Aug 2021 10:55:13 +0800
Subject: [PATCH 1/2] This patch is needed for ISPC for Gen only
1. Transformation of add to or is not safe for VC backend.
2. bswap intrinsics is not supported in VC backend yet.
Upstream-Status: Backport [Taken from ispc, https://github.com/ispc/ispc/blob/v1.16.1/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch]
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
---
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 10 +++++++---
.../lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 9 ++++++---
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index bacb8689892a..f3d0120db256 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -15,6 +15,7 @@
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/InstructionSimplify.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/IR/Constant.h"
@@ -1363,9 +1364,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
}
}
- // A+B --> A|B iff A and B have no bits set in common.
- if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
- return BinaryOperator::CreateOr(LHS, RHS);
+ // Disable this transformation for ISPC SPIR-V
+ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
+ // A+B --> A|B iff A and B have no bits set in common.
+ if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
+ return BinaryOperator::CreateOr(LHS, RHS);
+ }
// add (select X 0 (sub n A)) A --> select X A n
{
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 68c4156af2c4..b145b863ca84 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2584,9 +2584,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
return FoldedLogic;
- if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
- /*MatchBitReversals*/ false))
- return BSwap;
+ // Disable this transformation for ISPC SPIR-V
+ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
+ if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
+ /*MatchBitReversals*/ false))
+ return BSwap;
+ }
if (Instruction *Funnel = matchFunnelShift(I, *this))
return Funnel;
--
2.17.1
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