1 files changed, 47 insertions, 0 deletions

diff --git a/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0007-ispc-11_0_11_1_disable-A-B-A-B-in-InstCombine.patch b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0007-ispc-11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
new file mode 100644
index 00000000..dcf26bc9
--- /dev/null
+++ b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm11-0007-ispc-11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
@@ -0,0 +1,47 @@
+From ef2b930a8e33078449737a93e7d522b2280ec58c Mon Sep 17 00:00:00 2001
+From: Naveen Saini <naveen.kumar.saini@intel.com>
+Date: Fri, 27 Aug 2021 11:39:16 +0800
+Subject: [PATCH 1/2] This patch is needed for ISPC for Gen only
+
+Transformation of add to or is not safe for VC backend.
+
+Upstream-Status: Backport [Taken from ispc,https://github.com/ispc/ispc/blob/v1.16.1/llvm_patches/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch]
+
+Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
+---
+ .../lib/Transforms/InstCombine/InstCombineAddSub.cpp | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+index a7f5e0a7774d..bf02b0f70827 100644
+--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
++++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+@@ -15,6 +15,7 @@
+ #include "llvm/ADT/APInt.h"
+ #include "llvm/ADT/STLExtras.h"
+ #include "llvm/ADT/SmallVector.h"
++#include "llvm/ADT/Triple.h"
+ #include "llvm/Analysis/InstructionSimplify.h"
+ #include "llvm/Analysis/ValueTracking.h"
+ #include "llvm/IR/Constant.h"
+@@ -1324,10 +1325,13 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
+       return BinaryOperator::CreateSRem(RHS, NewRHS);
+     }
+   }
+-
+-  // A+B --> A|B iff A and B have no bits set in common.
+-  if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
+-    return BinaryOperator::CreateOr(LHS, RHS);
++  
++  // Disable this transformation for ISPC SPIR-V
++  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++    // A+B --> A|B iff A and B have no bits set in common.
++    if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
++      return BinaryOperator::CreateOr(LHS, RHS);
++  }
+ 
+   // FIXME: We already did a check for ConstantInt RHS above this.
+   // FIXME: Is this pattern covered by another fold? No regression tests fail on
+-- 
+2.17.1
+