1 files changed, 0 insertions, 61 deletions

diff --git a/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch
deleted file mode 100644
index e03c279f..00000000
--- a/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 9cdff0785d5cf9effc8e922d3330311c4d3dda78 Mon Sep 17 00:00:00 2001
-From: Naveen Saini <naveen.kumar.saini@intel.com>
-Date: Fri, 27 Aug 2021 12:09:42 +0800
-Subject: [PATCH 2/2] This patch is needed for avx512skx-i8x64 and
- avx512skx-i16x32 targets.
-
-This is combination of two commits:
-- 0cd6712a7af0fa2702b5d4cc733500eb5e62e7d0 - stability fix.
-- d8ad7cc0885f32104a7cd83c77191aec15fd684f - performance follow up.
-
-Upstream-Status: Backport
-
-Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
----
- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 23 +++++++++++++++++--
- 1 file changed, 21 insertions(+), 2 deletions(-)
-
-diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-index 439a8367dabe..b1639c7f275d 100644
---- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
-@@ -18471,6 +18471,26 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
- 
-   // Allow targets to opt-out.
-   EVT VT = Extract->getValueType(0);
-+
-+  // We can only create byte sized loads.
-+  if (!VT.isByteSized())
-+    return SDValue();
-+
-+  unsigned Index = ExtIdx->getZExtValue();
-+  unsigned NumElts = VT.getVectorNumElements();
-+
-+  // If the index is a multiple of the extract element count, we can offset the
-+  // address by the store size multiplied by the subvector index. Otherwise if
-+  // the scalar type is byte sized, we can just use the index multiplied by
-+  // the element size in bytes as the offset.
-+  unsigned Offset;
-+  if (Index % NumElts == 0)
-+    Offset = (Index / NumElts) * VT.getStoreSize();
-+  else if (VT.getScalarType().isByteSized())
-+    Offset = Index * VT.getScalarType().getStoreSize();
-+  else
-+    return SDValue();
-+
-   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-   if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT))
-     return SDValue();
-@@ -18478,8 +18498,7 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
-   // The narrow load will be offset from the base address of the old load if
-   // we are extracting from something besides index 0 (little-endian).
-   SDLoc DL(Extract);
--  SDValue BaseAddr = Ld->getOperand(1);
--  unsigned Offset = ExtIdx->getZExtValue() * VT.getScalarType().getStoreSize();
-+  SDValue BaseAddr = Ld->getBasePtr();
- 
-   // TODO: Use "BaseIndexOffset" to make this more effective.
-   SDValue NewAddr = DAG.getMemBasePlusOffset(BaseAddr, Offset, DL);
--- 
-2.17.1
-