diff options
| author | Saul Wold <sgw@linux.intel.com> | 2015-05-11 11:18:41 -0700 |
|---|---|---|
| committer | Saul Wold <sgw@linux.intel.com> | 2015-05-11 11:18:41 -0700 |
| commit | afbba3222cb66c92d43e458330055f06380e29f0 (patch) | |
| tree | c81b0cb5e38d3aa1e7b7c9aad34f0561ff7d1096 /conf/machine | |
| parent | 1c807bdf9fc3e7ad323a4e244d0149559e6b5103 (diff) | |
| download | meta-intel-afbba3222cb66c92d43e458330055f06380e29f0.tar.gz | |
linux-yocto_3.19: Update to the Intel i915 driver
0befa35 drm/i915/chv: Remove DPIO force latency causing interpair skew issue
184e037 drm/i915: Fix chv cdclk support
e2a99b9 drm/i915: Increase the range of sideband address.
9d5d55e drm/i915: Disable DDR DVFS on CHV
96cce94 drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
b5005319 drm/i915: Program PFI credits for VLV
c7aa33e drm/i915: Rewrite VLV/CHV watermark code
a421d8b drm/i915: Make sure PND deadline mode is enabled on VLV/CHV
631afc9 drm/i915: Read out display FIFO size on VLV/CHV
e0dcdc0 drm/i915: Pass plane to vlv_compute_drain_latency()
a6a5562 drm/i915: Reorganize VLV DDL setup
bb662a4 drm/i915: Hide VLV DDL precision handling
3d2d932 drm/i915: Simplify VLV drain latency computation
f686147 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
86c658c drm/i915: Reduce CHV DDL multiplier to 16/8
8c4cdd9 drm/i915: Allow pixel clock up to 95% of cdclk on CHV
d9d4fb8 drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Diffstat (limited to 'conf/machine')
0 files changed, 0 insertions, 0 deletions