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1 files changed, 1970 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot-2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch b/recipes-bsp/u-boot/u-boot-2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch
new file mode 100644
index 0000000..0787939
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch
@@ -0,0 +1,1970 @@
1From a849600b9d2b702acf3d1b21b96bc3df8ea53e6d Mon Sep 17 00:00:00 2001
2From: Fabio Estevam <festevam@gmail.com>
3Date: Sun, 29 Apr 2012 08:11:13 +0000
4Subject: [PATCH 16/56] imx-common: Factor out get_ahb_clk()
5
6get_ahb_clk() is a common function between mx5 and mx6.
7
8Place it into imx-common directory.
9
10Cc: Dirk Behme <dirk.behme@googlemail.com>
11Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
12---
13 arch/arm/cpu/armv7/imx-common/cpu.c | 13 +
14 arch/arm/cpu/armv7/mx5/clock.c | 19 +-
15 arch/arm/cpu/armv7/mx6/clock.c | 19 +-
16 arch/arm/include/asm/arch-mx5/sys_proto.h | 2 +
17 arch/arm/include/asm/arch-mx6/ccm_regs.h | 892 -----------------------------
18 arch/arm/include/asm/arch-mx6/crm_regs.h | 892 +++++++++++++++++++++++++++++
19 arch/arm/include/asm/arch-mx6/sys_proto.h | 3 +-
20 7 files changed, 915 insertions(+), 925 deletions(-)
21 delete mode 100644 arch/arm/include/asm/arch-mx6/ccm_regs.h
22 create mode 100644 arch/arm/include/asm/arch-mx6/crm_regs.h
23
24diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
25index 3d58d8a..b96fa5b 100644
26--- a/arch/arm/cpu/armv7/imx-common/cpu.c
27+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
28@@ -29,6 +29,7 @@
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/sys_proto.h>
32+#include <asm/arch/crm_regs.h>
33
34 #ifdef CONFIG_FSL_ESDHC
35 #include <fsl_esdhc.h>
36@@ -127,3 +128,15 @@ void reset_cpu(ulong addr)
37 {
38 __raw_writew(4, WDOG1_BASE_ADDR);
39 }
40+
41+u32 get_ahb_clk(void)
42+{
43+ struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
44+ u32 reg, ahb_podf;
45+
46+ reg = __raw_readl(&imx_ccm->cbcdr);
47+ reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
48+ ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
49+
50+ return get_periph_clk() / (ahb_podf + 1);
51+}
52diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
53index d769a4d..903e207 100644
54--- a/arch/arm/cpu/armv7/mx5/clock.c
55+++ b/arch/arm/cpu/armv7/mx5/clock.c
56@@ -30,6 +30,7 @@
57 #include <asm/arch/crm_regs.h>
58 #include <asm/arch/clock.h>
59 #include <div64.h>
60+#include <asm/arch/sys_proto.h>
61
62 enum pll_clocks {
63 PLL1_CLOCK = 0,
64@@ -192,7 +193,7 @@ u32 get_mcu_main_clk(void)
65 /*
66 * Get the rate of peripheral's root clock.
67 */
68-static u32 get_periph_clk(void)
69+u32 get_periph_clk(void)
70 {
71 u32 reg;
72
73@@ -213,22 +214,6 @@ static u32 get_periph_clk(void)
74 }
75
76 /*
77- * Get the rate of ahb clock.
78- */
79-static u32 get_ahb_clk(void)
80-{
81- uint32_t freq, div, reg;
82-
83- freq = get_periph_clk();
84-
85- reg = __raw_readl(&mxc_ccm->cbcdr);
86- div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
87- MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
88-
89- return freq / div;
90-}
91-
92-/*
93 * Get the rate of ipg clock.
94 */
95 static u32 get_ipg_clk(void)
96diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
97index ef98563..0f05432 100644
98--- a/arch/arm/cpu/armv7/mx6/clock.c
99+++ b/arch/arm/cpu/armv7/mx6/clock.c
100@@ -24,8 +24,9 @@
101 #include <asm/io.h>
102 #include <asm/errno.h>
103 #include <asm/arch/imx-regs.h>
104-#include <asm/arch/ccm_regs.h>
105+#include <asm/arch/crm_regs.h>
106 #include <asm/arch/clock.h>
107+#include <asm/arch/sys_proto.h>
108
109 enum pll_clocks {
110 PLL_SYS, /* System PLL */
111@@ -34,7 +35,7 @@ enum pll_clocks {
112 PLL_ENET, /* ENET PLL */
113 };
114
115-struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
116+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
117
118 void enable_usboh3_clk(unsigned char enable)
119 {
120@@ -92,7 +93,7 @@ static u32 get_mcu_main_clk(void)
121 return freq / (reg + 1);
122 }
123
124-static u32 get_periph_clk(void)
125+u32 get_periph_clk(void)
126 {
127 u32 reg, freq = 0;
128
129@@ -139,18 +140,6 @@ static u32 get_periph_clk(void)
130 return freq;
131 }
132
133-
134-static u32 get_ahb_clk(void)
135-{
136- u32 reg, ahb_podf;
137-
138- reg = __raw_readl(&imx_ccm->cbcdr);
139- reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
140- ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
141-
142- return get_periph_clk() / (ahb_podf + 1);
143-}
144-
145 static u32 get_ipg_clk(void)
146 {
147 u32 reg, ipg_podf;
148diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
149index 13d12ee..3f10d29 100644
150--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
151+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
152@@ -35,5 +35,7 @@ void set_chipselect_size(int const);
153 */
154
155 int fecmxc_initialize(bd_t *bis);
156+u32 get_ahb_clk(void);
157+u32 get_periph_clk(void);
158
159 #endif
160diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/ccm_regs.h
161deleted file mode 100644
162index 4af0b90..0000000
163--- a/arch/arm/include/asm/arch-mx6/ccm_regs.h
164+++ /dev/null
165@@ -1,892 +0,0 @@
166-/*
167- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
168- *
169- * This program is free software; you can redistribute it and/or modify
170- * it under the terms of the GNU General Public License as published by
171- * the Free Software Foundation; either version 2 of the License, or
172- * (at your option) any later version.
173- *
174- * This program is distributed in the hope that it will be useful,
175- * but WITHOUT ANY WARRANTY; without even the implied warranty of
176- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
177- * GNU General Public License for more details.
178- *
179- * You should have received a copy of the GNU General Public License
180- * along with this program; if not, write to the Free Software
181- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
182- *
183- */
184-
185-#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
186-#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
187-
188-struct imx_ccm_reg {
189- u32 ccr; /* 0x0000 */
190- u32 ccdr;
191- u32 csr;
192- u32 ccsr;
193- u32 cacrr; /* 0x0010*/
194- u32 cbcdr;
195- u32 cbcmr;
196- u32 cscmr1;
197- u32 cscmr2; /* 0x0020 */
198- u32 cscdr1;
199- u32 cs1cdr;
200- u32 cs2cdr;
201- u32 cdcdr; /* 0x0030 */
202- u32 chscdr;
203- u32 cscdr2;
204- u32 cscdr3;
205- u32 cscdr4; /* 0x0040 */
206- u32 resv0;
207- u32 cdhipr;
208- u32 cdcr;
209- u32 ctor; /* 0x0050 */
210- u32 clpcr;
211- u32 cisr;
212- u32 cimr;
213- u32 ccosr; /* 0x0060 */
214- u32 cgpr;
215- u32 CCGR0;
216- u32 CCGR1;
217- u32 CCGR2; /* 0x0070 */
218- u32 CCGR3;
219- u32 CCGR4;
220- u32 CCGR5;
221- u32 CCGR6; /* 0x0080 */
222- u32 CCGR7;
223- u32 cmeor;
224- u32 resv[0xfdd];
225- u32 analog_pll_sys; /* 0x4000 */
226- u32 analog_pll_sys_set;
227- u32 analog_pll_sys_clr;
228- u32 analog_pll_sys_tog;
229- u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
230- u32 analog_usb1_pll_480_ctrl_set;
231- u32 analog_usb1_pll_480_ctrl_clr;
232- u32 analog_usb1_pll_480_ctrl_tog;
233- u32 analog_reserved0[4];
234- u32 analog_pll_528; /* 0x4030 */
235- u32 analog_pll_528_set;
236- u32 analog_pll_528_clr;
237- u32 analog_pll_528_tog;
238- u32 analog_pll_528_ss; /* 0x4040 */
239- u32 analog_reserved1[3];
240- u32 analog_pll_528_num; /* 0x4050 */
241- u32 analog_reserved2[3];
242- u32 analog_pll_528_denom; /* 0x4060 */
243- u32 analog_reserved3[3];
244- u32 analog_pll_audio; /* 0x4070 */
245- u32 analog_pll_audio_set;
246- u32 analog_pll_audio_clr;
247- u32 analog_pll_audio_tog;
248- u32 analog_pll_audio_num; /* 0x4080*/
249- u32 analog_reserved4[3];
250- u32 analog_pll_audio_denom; /* 0x4090 */
251- u32 analog_reserved5[3];
252- u32 analog_pll_video; /* 0x40a0 */
253- u32 analog_pll_video_set;
254- u32 analog_pll_video_clr;
255- u32 analog_pll_video_tog;
256- u32 analog_pll_video_num; /* 0x40b0 */
257- u32 analog_reserved6[3];
258- u32 analog_pll_vedio_denon; /* 0x40c0 */
259- u32 analog_reserved7[7];
260- u32 analog_pll_enet; /* 0x40e0 */
261- u32 analog_pll_enet_set;
262- u32 analog_pll_enet_clr;
263- u32 analog_pll_enet_tog;
264- u32 analog_pfd_480; /* 0x40f0 */
265- u32 analog_pfd_480_set;
266- u32 analog_pfd_480_clr;
267- u32 analog_pfd_480_tog;
268- u32 analog_pfd_528; /* 0x4100 */
269- u32 analog_pfd_528_set;
270- u32 analog_pfd_528_clr;
271- u32 analog_pfd_528_tog;
272-};
273-
274-/* Define the bits in register CCR */
275-#define MXC_CCM_CCR_RBC_EN (1 << 27)
276-#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
277-#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
278-#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
279-#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
280-#define MXC_CCM_CCR_COSC_EN (1 << 12)
281-#define MXC_CCM_CCR_OSCNT_MASK 0xFF
282-#define MXC_CCM_CCR_OSCNT_OFFSET 0
283-
284-/* Define the bits in register CCDR */
285-#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
286-#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
287-
288-/* Define the bits in register CSR */
289-#define MXC_CCM_CSR_COSC_READY (1 << 5)
290-#define MXC_CCM_CSR_REF_EN_B (1 << 0)
291-
292-/* Define the bits in register CCSR */
293-#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
294-#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
295-#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
296-#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
297-#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
298-#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
299-#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
300-#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
301-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
302-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
303-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
304-
305-/* Define the bits in register CACRR */
306-#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
307-#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
308-
309-/* Define the bits in register CBCDR */
310-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
311-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
312-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
313-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
314-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
315-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
316-#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
317-#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
318-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
319-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
320-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
321-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
322-#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
323-#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
324-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
325-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
326-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
327-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
328-
329-/* Define the bits in register CBCMR */
330-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
331-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
332-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
333-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
334-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
335-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
336-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
337-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
338-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
339-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
340-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
341-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
342-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
343-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
344-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
345-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
346-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
347-#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
348-#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
349-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
350-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
351-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
352-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
353-#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
354-#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
355-
356-/* Define the bits in register CSCMR1 */
357-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
358-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
359-#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
360-#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
361-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
362-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
363-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
364-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
365-#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
366-#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
367-#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
368-#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
369-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
370-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
371-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
372-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
373-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
374-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
375-#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
376-
377-/* Define the bits in register CSCMR2 */
378-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
379-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
380-#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
381-#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
382-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
383-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
384-
385-/* Define the bits in register CSCDR1 */
386-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
387-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
388-#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
389-#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
390-#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
391-#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
392-#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
393-#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
394-#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
395-#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
396-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
397-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
398-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
399-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
400-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
401-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
402-
403-/* Define the bits in register CS1CDR */
404-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
405-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
406-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
407-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
408-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
409-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
410-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
411-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
412-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
413-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
414-
415-/* Define the bits in register CS2CDR */
416-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
417-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
418-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
419-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
420-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
421-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
422-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
423-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
424-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
425-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
426-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
427-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
428-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
429-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
430-
431-/* Define the bits in register CDCDR */
432-#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
433-#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
434-#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
435-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
436-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
437-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
438-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
439-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
440-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
441-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
442-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
443-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
444-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
445-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
446-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
447-
448-/* Define the bits in register CHSCCDR */
449-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
450-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
451-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
452-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
453-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
454-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
455-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
456-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
457-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
458-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
459-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
460-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
461-
462-/* Define the bits in register CSCDR2 */
463-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
464-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
465-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
466-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
467-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
468-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
469-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
470-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
471-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
472-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
473-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
474-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
475-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
476-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
477-
478-/* Define the bits in register CSCDR3 */
479-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
480-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
481-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
482-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
483-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
484-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
485-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
486-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
487-
488-/* Define the bits in register CDHIPR */
489-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
490-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
491-#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
492-#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
493-#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
494-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
495-#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
496-
497-/* Define the bits in register CLPCR */
498-#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
499-#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
500-#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
501-#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
502-#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
503-#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
504-#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
505-#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
506-#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
507-#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
508-#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
509-#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
510-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
511-#define MXC_CCM_CLPCR_VSTBY (1 << 8)
512-#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
513-#define MXC_CCM_CLPCR_SBYOS (1 << 6)
514-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
515-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
516-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
517-#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
518-#define MXC_CCM_CLPCR_LPM_MASK 0x3
519-#define MXC_CCM_CLPCR_LPM_OFFSET 0
520-
521-/* Define the bits in register CISR */
522-#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
523-#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
524-#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
525-#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
526-#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
527-#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
528-#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
529-#define MXC_CCM_CISR_COSC_READY (1 << 6)
530-#define MXC_CCM_CISR_LRF_PLL 1
531-
532-/* Define the bits in register CIMR */
533-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
534-#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
535-#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
536-#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
537-#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
538-#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
539-#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
540-#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
541-#define MXC_CCM_CIMR_MASK_LRF_PLL 1
542-
543-/* Define the bits in register CCOSR */
544-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
545-#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
546-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
547-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
548-#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
549-#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
550-#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
551-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
552-#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
553-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
554-
555-/* Define the bits in registers CGPR */
556-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
557-#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
558-#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
559-
560-/* Define the bits in registers CCGRx */
561-#define MXC_CCM_CCGR_CG_MASK 3
562-
563-#define MXC_CCM_CCGR0_CG15_OFFSET 30
564-#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
565-#define MXC_CCM_CCGR0_CG14_OFFSET 28
566-#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
567-#define MXC_CCM_CCGR0_CG13_OFFSET 26
568-#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
569-#define MXC_CCM_CCGR0_CG12_OFFSET 24
570-#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
571-#define MXC_CCM_CCGR0_CG11_OFFSET 22
572-#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
573-#define MXC_CCM_CCGR0_CG10_OFFSET 20
574-#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
575-#define MXC_CCM_CCGR0_CG9_OFFSET 18
576-#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
577-#define MXC_CCM_CCGR0_CG8_OFFSET 16
578-#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
579-#define MXC_CCM_CCGR0_CG7_OFFSET 14
580-#define MXC_CCM_CCGR0_CG6_OFFSET 12
581-#define MXC_CCM_CCGR0_CG5_OFFSET 10
582-#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
583-#define MXC_CCM_CCGR0_CG4_OFFSET 8
584-#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
585-#define MXC_CCM_CCGR0_CG3_OFFSET 6
586-#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
587-#define MXC_CCM_CCGR0_CG2_OFFSET 4
588-#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
589-#define MXC_CCM_CCGR0_CG1_OFFSET 2
590-#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
591-#define MXC_CCM_CCGR0_CG0_OFFSET 0
592-#define MXC_CCM_CCGR0_CG0_MASK 3
593-
594-#define MXC_CCM_CCGR1_CG15_OFFSET 30
595-#define MXC_CCM_CCGR1_CG14_OFFSET 28
596-#define MXC_CCM_CCGR1_CG13_OFFSET 26
597-#define MXC_CCM_CCGR1_CG12_OFFSET 24
598-#define MXC_CCM_CCGR1_CG11_OFFSET 22
599-#define MXC_CCM_CCGR1_CG10_OFFSET 20
600-#define MXC_CCM_CCGR1_CG9_OFFSET 18
601-#define MXC_CCM_CCGR1_CG8_OFFSET 16
602-#define MXC_CCM_CCGR1_CG7_OFFSET 14
603-#define MXC_CCM_CCGR1_CG6_OFFSET 12
604-#define MXC_CCM_CCGR1_CG5_OFFSET 10
605-#define MXC_CCM_CCGR1_CG4_OFFSET 8
606-#define MXC_CCM_CCGR1_CG3_OFFSET 6
607-#define MXC_CCM_CCGR1_CG2_OFFSET 4
608-#define MXC_CCM_CCGR1_CG1_OFFSET 2
609-#define MXC_CCM_CCGR1_CG0_OFFSET 0
610-
611-#define MXC_CCM_CCGR2_CG15_OFFSET 30
612-#define MXC_CCM_CCGR2_CG14_OFFSET 28
613-#define MXC_CCM_CCGR2_CG13_OFFSET 26
614-#define MXC_CCM_CCGR2_CG12_OFFSET 24
615-#define MXC_CCM_CCGR2_CG11_OFFSET 22
616-#define MXC_CCM_CCGR2_CG10_OFFSET 20
617-#define MXC_CCM_CCGR2_CG9_OFFSET 18
618-#define MXC_CCM_CCGR2_CG8_OFFSET 16
619-#define MXC_CCM_CCGR2_CG7_OFFSET 14
620-#define MXC_CCM_CCGR2_CG6_OFFSET 12
621-#define MXC_CCM_CCGR2_CG5_OFFSET 10
622-#define MXC_CCM_CCGR2_CG4_OFFSET 8
623-#define MXC_CCM_CCGR2_CG3_OFFSET 6
624-#define MXC_CCM_CCGR2_CG2_OFFSET 4
625-#define MXC_CCM_CCGR2_CG1_OFFSET 2
626-#define MXC_CCM_CCGR2_CG0_OFFSET 0
627-
628-#define MXC_CCM_CCGR3_CG15_OFFSET 30
629-#define MXC_CCM_CCGR3_CG14_OFFSET 28
630-#define MXC_CCM_CCGR3_CG13_OFFSET 26
631-#define MXC_CCM_CCGR3_CG12_OFFSET 24
632-#define MXC_CCM_CCGR3_CG11_OFFSET 22
633-#define MXC_CCM_CCGR3_CG10_OFFSET 20
634-#define MXC_CCM_CCGR3_CG9_OFFSET 18
635-#define MXC_CCM_CCGR3_CG8_OFFSET 16
636-#define MXC_CCM_CCGR3_CG7_OFFSET 14
637-#define MXC_CCM_CCGR3_CG6_OFFSET 12
638-#define MXC_CCM_CCGR3_CG5_OFFSET 10
639-#define MXC_CCM_CCGR3_CG4_OFFSET 8
640-#define MXC_CCM_CCGR3_CG3_OFFSET 6
641-#define MXC_CCM_CCGR3_CG2_OFFSET 4
642-#define MXC_CCM_CCGR3_CG1_OFFSET 2
643-#define MXC_CCM_CCGR3_CG0_OFFSET 0
644-
645-#define MXC_CCM_CCGR4_CG15_OFFSET 30
646-#define MXC_CCM_CCGR4_CG14_OFFSET 28
647-#define MXC_CCM_CCGR4_CG13_OFFSET 26
648-#define MXC_CCM_CCGR4_CG12_OFFSET 24
649-#define MXC_CCM_CCGR4_CG11_OFFSET 22
650-#define MXC_CCM_CCGR4_CG10_OFFSET 20
651-#define MXC_CCM_CCGR4_CG9_OFFSET 18
652-#define MXC_CCM_CCGR4_CG8_OFFSET 16
653-#define MXC_CCM_CCGR4_CG7_OFFSET 14
654-#define MXC_CCM_CCGR4_CG6_OFFSET 12
655-#define MXC_CCM_CCGR4_CG5_OFFSET 10
656-#define MXC_CCM_CCGR4_CG4_OFFSET 8
657-#define MXC_CCM_CCGR4_CG3_OFFSET 6
658-#define MXC_CCM_CCGR4_CG2_OFFSET 4
659-#define MXC_CCM_CCGR4_CG1_OFFSET 2
660-#define MXC_CCM_CCGR4_CG0_OFFSET 0
661-
662-#define MXC_CCM_CCGR5_CG15_OFFSET 30
663-#define MXC_CCM_CCGR5_CG14_OFFSET 28
664-#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
665-#define MXC_CCM_CCGR5_CG13_OFFSET 26
666-#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
667-#define MXC_CCM_CCGR5_CG12_OFFSET 24
668-#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
669-#define MXC_CCM_CCGR5_CG11_OFFSET 22
670-#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
671-#define MXC_CCM_CCGR5_CG10_OFFSET 20
672-#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
673-#define MXC_CCM_CCGR5_CG9_OFFSET 18
674-#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
675-#define MXC_CCM_CCGR5_CG8_OFFSET 16
676-#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
677-#define MXC_CCM_CCGR5_CG7_OFFSET 14
678-#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
679-#define MXC_CCM_CCGR5_CG6_OFFSET 12
680-#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
681-#define MXC_CCM_CCGR5_CG5_OFFSET 10
682-#define MXC_CCM_CCGR5_CG4_OFFSET 8
683-#define MXC_CCM_CCGR5_CG3_OFFSET 6
684-#define MXC_CCM_CCGR5_CG2_OFFSET 4
685-#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
686-#define MXC_CCM_CCGR5_CG1_OFFSET 2
687-#define MXC_CCM_CCGR5_CG0_OFFSET 0
688-
689-#define MXC_CCM_CCGR6_CG15_OFFSET 30
690-#define MXC_CCM_CCGR6_CG14_OFFSET 28
691-#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
692-#define MXC_CCM_CCGR6_CG13_OFFSET 26
693-#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
694-#define MXC_CCM_CCGR6_CG12_OFFSET 24
695-#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
696-#define MXC_CCM_CCGR6_CG11_OFFSET 22
697-#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
698-#define MXC_CCM_CCGR6_CG10_OFFSET 20
699-#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
700-#define MXC_CCM_CCGR6_CG9_OFFSET 18
701-#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
702-#define MXC_CCM_CCGR6_CG8_OFFSET 16
703-#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
704-#define MXC_CCM_CCGR6_CG7_OFFSET 14
705-#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
706-#define MXC_CCM_CCGR6_CG6_OFFSET 12
707-#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
708-#define MXC_CCM_CCGR6_CG5_OFFSET 10
709-#define MXC_CCM_CCGR6_CG4_OFFSET 8
710-#define MXC_CCM_CCGR6_CG3_OFFSET 6
711-#define MXC_CCM_CCGR6_CG2_OFFSET 4
712-#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
713-#define MXC_CCM_CCGR6_CG1_OFFSET 2
714-#define MXC_CCM_CCGR6_CG0_OFFSET 0
715-
716-#define MXC_CCM_CCGR7_CG15_OFFSET 30
717-#define MXC_CCM_CCGR7_CG14_OFFSET 28
718-#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
719-#define MXC_CCM_CCGR7_CG13_OFFSET 26
720-#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
721-#define MXC_CCM_CCGR7_CG12_OFFSET 24
722-#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
723-#define MXC_CCM_CCGR7_CG11_OFFSET 22
724-#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
725-#define MXC_CCM_CCGR7_CG10_OFFSET 20
726-#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
727-#define MXC_CCM_CCGR7_CG9_OFFSET 18
728-#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
729-#define MXC_CCM_CCGR7_CG8_OFFSET 16
730-#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
731-#define MXC_CCM_CCGR7_CG7_OFFSET 14
732-#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
733-#define MXC_CCM_CCGR7_CG6_OFFSET 12
734-#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
735-#define MXC_CCM_CCGR7_CG5_OFFSET 10
736-#define MXC_CCM_CCGR7_CG4_OFFSET 8
737-#define MXC_CCM_CCGR7_CG3_OFFSET 6
738-#define MXC_CCM_CCGR7_CG2_OFFSET 4
739-#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
740-#define MXC_CCM_CCGR7_CG1_OFFSET 2
741-#define MXC_CCM_CCGR7_CG0_OFFSET 0
742-#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
743-#define BP_ANADIG_PLL_SYS_RSVD0 20
744-#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
745-#define BF_ANADIG_PLL_SYS_RSVD0(v) \
746- (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
747-#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
748-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
749-#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
750-#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
751-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
752-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
753-#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
754- (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
755-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
756-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
757-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
758-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
759-#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
760-#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
761-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
762-#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
763-#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
764-#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
765-#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
766-#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
767-#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
768-#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
769- (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
770-
771-#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
772-#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
773-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
774-#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
775- (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
776-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
777-#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
778-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
779-#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
780- (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
781-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
782-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
783-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
784-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
785-#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
786-#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
787-#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
788-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
789-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
790-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
791-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
792-#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
793-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
794-#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
795-#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
796-#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
797- (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
798-#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
799-#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
800-#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
801- (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
802-
803-#define BM_ANADIG_PLL_528_LOCK 0x80000000
804-#define BP_ANADIG_PLL_528_RSVD1 19
805-#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
806-#define BF_ANADIG_PLL_528_RSVD1(v) \
807- (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
808-#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
809-#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
810-#define BM_ANADIG_PLL_528_BYPASS 0x00010000
811-#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
812-#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
813-#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
814- (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
815-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
816-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
817-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
818-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
819-#define BM_ANADIG_PLL_528_ENABLE 0x00002000
820-#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
821-#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
822-#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
823-#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
824-#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
825-#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
826-#define BP_ANADIG_PLL_528_RSVD0 1
827-#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
828-#define BF_ANADIG_PLL_528_RSVD0(v) \
829- (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
830-#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
831-
832-#define BP_ANADIG_PLL_528_SS_STOP 16
833-#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
834-#define BF_ANADIG_PLL_528_SS_STOP(v) \
835- (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
836-#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
837-#define BP_ANADIG_PLL_528_SS_STEP 0
838-#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
839-#define BF_ANADIG_PLL_528_SS_STEP(v) \
840- (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
841-
842-#define BP_ANADIG_PLL_528_NUM_RSVD0 30
843-#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
844-#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
845- (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
846-#define BP_ANADIG_PLL_528_NUM_A 0
847-#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
848-#define BF_ANADIG_PLL_528_NUM_A(v) \
849- (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
850-
851-#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
852-#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
853-#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
854- (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
855-#define BP_ANADIG_PLL_528_DENOM_B 0
856-#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
857-#define BF_ANADIG_PLL_528_DENOM_B(v) \
858- (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
859-
860-#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
861-#define BP_ANADIG_PLL_AUDIO_RSVD0 22
862-#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
863-#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
864- (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
865-#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
866-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
867-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
868-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
869- (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
870-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
871-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
872-#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
873-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
874-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
875-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
876- (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
877-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
878-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
879-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
880-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
881-#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
882-#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
883-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
884-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
885-#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
886-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
887-#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
888-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
889-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
890-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
891- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
892-
893-#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
894-#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
895-#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
896- (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
897-#define BP_ANADIG_PLL_AUDIO_NUM_A 0
898-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
899-#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
900- (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
901-
902-#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
903-#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
904-#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
905- (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
906-#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
907-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
908-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
909- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
910-
911-#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
912-#define BP_ANADIG_PLL_VIDEO_RSVD0 22
913-#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
914-#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
915- (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
916-#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
917-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
918-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
919-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
920- (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
921-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
922-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
923-#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
924-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
925-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
926-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
927- (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
928-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
929-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
930-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
931-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
932-#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
933-#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
934-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
935-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
936-#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
937-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
938-#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
939-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
940-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
941-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
942- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
943-
944-#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
945-#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
946-#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
947- (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
948-#define BP_ANADIG_PLL_VIDEO_NUM_A 0
949-#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
950-#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
951- (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
952-
953-#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
954-#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
955-#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
956- (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
957-#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
958-#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
959-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
960- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
961-
962-#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
963-#define BP_ANADIG_PLL_ENET_RSVD1 21
964-#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
965-#define BF_ANADIG_PLL_ENET_RSVD1(v) \
966- (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
967-#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
968-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
969-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
970-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
971-#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
972-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
973-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
974-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
975- (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
976-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
977-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
978-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
979-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
980-#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
981-#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
982-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
983-#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
984-#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
985-#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
986-#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
987-#define BP_ANADIG_PLL_ENET_RSVD0 2
988-#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
989-#define BF_ANADIG_PLL_ENET_RSVD0(v) \
990- (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
991-#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
992-#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
993-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
994- (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
995-
996-#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
997-#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
998-#define BP_ANADIG_PFD_480_PFD3_FRAC 24
999-#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1000-#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1001- (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1002-#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1003-#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1004-#define BP_ANADIG_PFD_480_PFD2_FRAC 16
1005-#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1006-#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1007- (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1008-#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1009-#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1010-#define BP_ANADIG_PFD_480_PFD1_FRAC 8
1011-#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1012-#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1013- (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1014-#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1015-#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1016-#define BP_ANADIG_PFD_480_PFD0_FRAC 0
1017-#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1018-#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1019- (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1020-
1021-#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1022-#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1023-#define BP_ANADIG_PFD_528_PFD3_FRAC 24
1024-#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1025-#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1026- (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1027-#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1028-#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1029-#define BP_ANADIG_PFD_528_PFD2_FRAC 16
1030-#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1031-#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1032- (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1033-#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1034-#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1035-#define BP_ANADIG_PFD_528_PFD1_FRAC 8
1036-#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1037-#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1038- (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1039-#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1040-#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1041-#define BP_ANADIG_PFD_528_PFD0_FRAC 0
1042-#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1043-#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1044- (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1045-
1046-#define PLL2_PFD0_FREQ 352000000
1047-#define PLL2_PFD1_FREQ 594000000
1048-#define PLL2_PFD2_FREQ 400000000
1049-#define PLL2_PFD2_DIV_FREQ 200000000
1050-#define PLL3_PFD0_FREQ 720000000
1051-#define PLL3_PFD1_FREQ 540000000
1052-#define PLL3_PFD2_FREQ 508200000
1053-#define PLL3_PFD3_FREQ 454700000
1054-#define PLL3_80M 80000000
1055-#define PLL3_60M 60000000
1056-
1057-#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
1058diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
1059new file mode 100644
1060index 0000000..0e605c2
1061--- /dev/null
1062+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
1063@@ -0,0 +1,892 @@
1064+/*
1065+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
1066+ *
1067+ * This program is free software; you can redistribute it and/or modify
1068+ * it under the terms of the GNU General Public License as published by
1069+ * the Free Software Foundation; either version 2 of the License, or
1070+ * (at your option) any later version.
1071+ *
1072+ * This program is distributed in the hope that it will be useful,
1073+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1074+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1075+ * GNU General Public License for more details.
1076+ *
1077+ * You should have received a copy of the GNU General Public License
1078+ * along with this program; if not, write to the Free Software
1079+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1080+ *
1081+ */
1082+
1083+#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
1084+#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
1085+
1086+struct mxc_ccm_reg {
1087+ u32 ccr; /* 0x0000 */
1088+ u32 ccdr;
1089+ u32 csr;
1090+ u32 ccsr;
1091+ u32 cacrr; /* 0x0010*/
1092+ u32 cbcdr;
1093+ u32 cbcmr;
1094+ u32 cscmr1;
1095+ u32 cscmr2; /* 0x0020 */
1096+ u32 cscdr1;
1097+ u32 cs1cdr;
1098+ u32 cs2cdr;
1099+ u32 cdcdr; /* 0x0030 */
1100+ u32 chscdr;
1101+ u32 cscdr2;
1102+ u32 cscdr3;
1103+ u32 cscdr4; /* 0x0040 */
1104+ u32 resv0;
1105+ u32 cdhipr;
1106+ u32 cdcr;
1107+ u32 ctor; /* 0x0050 */
1108+ u32 clpcr;
1109+ u32 cisr;
1110+ u32 cimr;
1111+ u32 ccosr; /* 0x0060 */
1112+ u32 cgpr;
1113+ u32 CCGR0;
1114+ u32 CCGR1;
1115+ u32 CCGR2; /* 0x0070 */
1116+ u32 CCGR3;
1117+ u32 CCGR4;
1118+ u32 CCGR5;
1119+ u32 CCGR6; /* 0x0080 */
1120+ u32 CCGR7;
1121+ u32 cmeor;
1122+ u32 resv[0xfdd];
1123+ u32 analog_pll_sys; /* 0x4000 */
1124+ u32 analog_pll_sys_set;
1125+ u32 analog_pll_sys_clr;
1126+ u32 analog_pll_sys_tog;
1127+ u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
1128+ u32 analog_usb1_pll_480_ctrl_set;
1129+ u32 analog_usb1_pll_480_ctrl_clr;
1130+ u32 analog_usb1_pll_480_ctrl_tog;
1131+ u32 analog_reserved0[4];
1132+ u32 analog_pll_528; /* 0x4030 */
1133+ u32 analog_pll_528_set;
1134+ u32 analog_pll_528_clr;
1135+ u32 analog_pll_528_tog;
1136+ u32 analog_pll_528_ss; /* 0x4040 */
1137+ u32 analog_reserved1[3];
1138+ u32 analog_pll_528_num; /* 0x4050 */
1139+ u32 analog_reserved2[3];
1140+ u32 analog_pll_528_denom; /* 0x4060 */
1141+ u32 analog_reserved3[3];
1142+ u32 analog_pll_audio; /* 0x4070 */
1143+ u32 analog_pll_audio_set;
1144+ u32 analog_pll_audio_clr;
1145+ u32 analog_pll_audio_tog;
1146+ u32 analog_pll_audio_num; /* 0x4080*/
1147+ u32 analog_reserved4[3];
1148+ u32 analog_pll_audio_denom; /* 0x4090 */
1149+ u32 analog_reserved5[3];
1150+ u32 analog_pll_video; /* 0x40a0 */
1151+ u32 analog_pll_video_set;
1152+ u32 analog_pll_video_clr;
1153+ u32 analog_pll_video_tog;
1154+ u32 analog_pll_video_num; /* 0x40b0 */
1155+ u32 analog_reserved6[3];
1156+ u32 analog_pll_vedio_denon; /* 0x40c0 */
1157+ u32 analog_reserved7[7];
1158+ u32 analog_pll_enet; /* 0x40e0 */
1159+ u32 analog_pll_enet_set;
1160+ u32 analog_pll_enet_clr;
1161+ u32 analog_pll_enet_tog;
1162+ u32 analog_pfd_480; /* 0x40f0 */
1163+ u32 analog_pfd_480_set;
1164+ u32 analog_pfd_480_clr;
1165+ u32 analog_pfd_480_tog;
1166+ u32 analog_pfd_528; /* 0x4100 */
1167+ u32 analog_pfd_528_set;
1168+ u32 analog_pfd_528_clr;
1169+ u32 analog_pfd_528_tog;
1170+};
1171+
1172+/* Define the bits in register CCR */
1173+#define MXC_CCM_CCR_RBC_EN (1 << 27)
1174+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
1175+#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
1176+#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
1177+#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
1178+#define MXC_CCM_CCR_COSC_EN (1 << 12)
1179+#define MXC_CCM_CCR_OSCNT_MASK 0xFF
1180+#define MXC_CCM_CCR_OSCNT_OFFSET 0
1181+
1182+/* Define the bits in register CCDR */
1183+#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
1184+#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
1185+
1186+/* Define the bits in register CSR */
1187+#define MXC_CCM_CSR_COSC_READY (1 << 5)
1188+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
1189+
1190+/* Define the bits in register CCSR */
1191+#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
1192+#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
1193+#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
1194+#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
1195+#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
1196+#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
1197+#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
1198+#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
1199+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
1200+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
1201+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
1202+
1203+/* Define the bits in register CACRR */
1204+#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
1205+#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
1206+
1207+/* Define the bits in register CBCDR */
1208+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
1209+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
1210+#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
1211+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
1212+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
1213+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
1214+#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
1215+#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
1216+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
1217+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
1218+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
1219+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
1220+#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
1221+#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
1222+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
1223+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
1224+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
1225+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
1226+
1227+/* Define the bits in register CBCMR */
1228+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
1229+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
1230+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
1231+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
1232+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
1233+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
1234+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
1235+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
1236+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
1237+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
1238+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
1239+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
1240+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
1241+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
1242+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
1243+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
1244+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
1245+#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
1246+#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
1247+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
1248+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
1249+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
1250+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
1251+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
1252+#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
1253+
1254+/* Define the bits in register CSCMR1 */
1255+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
1256+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
1257+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
1258+#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
1259+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
1260+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
1261+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
1262+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
1263+#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
1264+#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
1265+#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
1266+#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
1267+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
1268+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
1269+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
1270+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
1271+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
1272+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
1273+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
1274+
1275+/* Define the bits in register CSCMR2 */
1276+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
1277+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
1278+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
1279+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
1280+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
1281+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
1282+
1283+/* Define the bits in register CSCDR1 */
1284+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
1285+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
1286+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
1287+#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
1288+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
1289+#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
1290+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
1291+#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
1292+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
1293+#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
1294+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
1295+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
1296+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
1297+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
1298+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
1299+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
1300+
1301+/* Define the bits in register CS1CDR */
1302+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
1303+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
1304+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
1305+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
1306+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
1307+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
1308+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
1309+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
1310+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
1311+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
1312+
1313+/* Define the bits in register CS2CDR */
1314+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
1315+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
1316+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
1317+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
1318+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
1319+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
1320+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
1321+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
1322+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
1323+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
1324+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
1325+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
1326+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
1327+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
1328+
1329+/* Define the bits in register CDCDR */
1330+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
1331+#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
1332+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
1333+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
1334+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
1335+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
1336+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
1337+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
1338+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
1339+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
1340+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
1341+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
1342+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
1343+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
1344+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
1345+
1346+/* Define the bits in register CHSCCDR */
1347+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
1348+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
1349+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
1350+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
1351+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
1352+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
1353+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
1354+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
1355+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
1356+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
1357+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
1358+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
1359+
1360+/* Define the bits in register CSCDR2 */
1361+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
1362+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
1363+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
1364+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
1365+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
1366+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
1367+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
1368+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
1369+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
1370+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
1371+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
1372+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
1373+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
1374+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
1375+
1376+/* Define the bits in register CSCDR3 */
1377+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
1378+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
1379+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
1380+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
1381+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
1382+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
1383+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
1384+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
1385+
1386+/* Define the bits in register CDHIPR */
1387+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
1388+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
1389+#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
1390+#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
1391+#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
1392+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
1393+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
1394+
1395+/* Define the bits in register CLPCR */
1396+#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
1397+#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
1398+#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
1399+#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
1400+#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
1401+#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
1402+#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
1403+#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
1404+#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
1405+#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
1406+#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
1407+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
1408+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
1409+#define MXC_CCM_CLPCR_VSTBY (1 << 8)
1410+#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
1411+#define MXC_CCM_CLPCR_SBYOS (1 << 6)
1412+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
1413+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
1414+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
1415+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
1416+#define MXC_CCM_CLPCR_LPM_MASK 0x3
1417+#define MXC_CCM_CLPCR_LPM_OFFSET 0
1418+
1419+/* Define the bits in register CISR */
1420+#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
1421+#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
1422+#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
1423+#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
1424+#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
1425+#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
1426+#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
1427+#define MXC_CCM_CISR_COSC_READY (1 << 6)
1428+#define MXC_CCM_CISR_LRF_PLL 1
1429+
1430+/* Define the bits in register CIMR */
1431+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
1432+#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
1433+#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
1434+#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
1435+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
1436+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
1437+#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
1438+#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
1439+#define MXC_CCM_CIMR_MASK_LRF_PLL 1
1440+
1441+/* Define the bits in register CCOSR */
1442+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
1443+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
1444+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
1445+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
1446+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
1447+#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
1448+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
1449+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
1450+#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
1451+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
1452+
1453+/* Define the bits in registers CGPR */
1454+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
1455+#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
1456+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
1457+
1458+/* Define the bits in registers CCGRx */
1459+#define MXC_CCM_CCGR_CG_MASK 3
1460+
1461+#define MXC_CCM_CCGR0_CG15_OFFSET 30
1462+#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
1463+#define MXC_CCM_CCGR0_CG14_OFFSET 28
1464+#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
1465+#define MXC_CCM_CCGR0_CG13_OFFSET 26
1466+#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
1467+#define MXC_CCM_CCGR0_CG12_OFFSET 24
1468+#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
1469+#define MXC_CCM_CCGR0_CG11_OFFSET 22
1470+#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
1471+#define MXC_CCM_CCGR0_CG10_OFFSET 20
1472+#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
1473+#define MXC_CCM_CCGR0_CG9_OFFSET 18
1474+#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
1475+#define MXC_CCM_CCGR0_CG8_OFFSET 16
1476+#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
1477+#define MXC_CCM_CCGR0_CG7_OFFSET 14
1478+#define MXC_CCM_CCGR0_CG6_OFFSET 12
1479+#define MXC_CCM_CCGR0_CG5_OFFSET 10
1480+#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
1481+#define MXC_CCM_CCGR0_CG4_OFFSET 8
1482+#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
1483+#define MXC_CCM_CCGR0_CG3_OFFSET 6
1484+#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
1485+#define MXC_CCM_CCGR0_CG2_OFFSET 4
1486+#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
1487+#define MXC_CCM_CCGR0_CG1_OFFSET 2
1488+#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
1489+#define MXC_CCM_CCGR0_CG0_OFFSET 0
1490+#define MXC_CCM_CCGR0_CG0_MASK 3
1491+
1492+#define MXC_CCM_CCGR1_CG15_OFFSET 30
1493+#define MXC_CCM_CCGR1_CG14_OFFSET 28
1494+#define MXC_CCM_CCGR1_CG13_OFFSET 26
1495+#define MXC_CCM_CCGR1_CG12_OFFSET 24
1496+#define MXC_CCM_CCGR1_CG11_OFFSET 22
1497+#define MXC_CCM_CCGR1_CG10_OFFSET 20
1498+#define MXC_CCM_CCGR1_CG9_OFFSET 18
1499+#define MXC_CCM_CCGR1_CG8_OFFSET 16
1500+#define MXC_CCM_CCGR1_CG7_OFFSET 14
1501+#define MXC_CCM_CCGR1_CG6_OFFSET 12
1502+#define MXC_CCM_CCGR1_CG5_OFFSET 10
1503+#define MXC_CCM_CCGR1_CG4_OFFSET 8
1504+#define MXC_CCM_CCGR1_CG3_OFFSET 6
1505+#define MXC_CCM_CCGR1_CG2_OFFSET 4
1506+#define MXC_CCM_CCGR1_CG1_OFFSET 2
1507+#define MXC_CCM_CCGR1_CG0_OFFSET 0
1508+
1509+#define MXC_CCM_CCGR2_CG15_OFFSET 30
1510+#define MXC_CCM_CCGR2_CG14_OFFSET 28
1511+#define MXC_CCM_CCGR2_CG13_OFFSET 26
1512+#define MXC_CCM_CCGR2_CG12_OFFSET 24
1513+#define MXC_CCM_CCGR2_CG11_OFFSET 22
1514+#define MXC_CCM_CCGR2_CG10_OFFSET 20
1515+#define MXC_CCM_CCGR2_CG9_OFFSET 18
1516+#define MXC_CCM_CCGR2_CG8_OFFSET 16
1517+#define MXC_CCM_CCGR2_CG7_OFFSET 14
1518+#define MXC_CCM_CCGR2_CG6_OFFSET 12
1519+#define MXC_CCM_CCGR2_CG5_OFFSET 10
1520+#define MXC_CCM_CCGR2_CG4_OFFSET 8
1521+#define MXC_CCM_CCGR2_CG3_OFFSET 6
1522+#define MXC_CCM_CCGR2_CG2_OFFSET 4
1523+#define MXC_CCM_CCGR2_CG1_OFFSET 2
1524+#define MXC_CCM_CCGR2_CG0_OFFSET 0
1525+
1526+#define MXC_CCM_CCGR3_CG15_OFFSET 30
1527+#define MXC_CCM_CCGR3_CG14_OFFSET 28
1528+#define MXC_CCM_CCGR3_CG13_OFFSET 26
1529+#define MXC_CCM_CCGR3_CG12_OFFSET 24
1530+#define MXC_CCM_CCGR3_CG11_OFFSET 22
1531+#define MXC_CCM_CCGR3_CG10_OFFSET 20
1532+#define MXC_CCM_CCGR3_CG9_OFFSET 18
1533+#define MXC_CCM_CCGR3_CG8_OFFSET 16
1534+#define MXC_CCM_CCGR3_CG7_OFFSET 14
1535+#define MXC_CCM_CCGR3_CG6_OFFSET 12
1536+#define MXC_CCM_CCGR3_CG5_OFFSET 10
1537+#define MXC_CCM_CCGR3_CG4_OFFSET 8
1538+#define MXC_CCM_CCGR3_CG3_OFFSET 6
1539+#define MXC_CCM_CCGR3_CG2_OFFSET 4
1540+#define MXC_CCM_CCGR3_CG1_OFFSET 2
1541+#define MXC_CCM_CCGR3_CG0_OFFSET 0
1542+
1543+#define MXC_CCM_CCGR4_CG15_OFFSET 30
1544+#define MXC_CCM_CCGR4_CG14_OFFSET 28
1545+#define MXC_CCM_CCGR4_CG13_OFFSET 26
1546+#define MXC_CCM_CCGR4_CG12_OFFSET 24
1547+#define MXC_CCM_CCGR4_CG11_OFFSET 22
1548+#define MXC_CCM_CCGR4_CG10_OFFSET 20
1549+#define MXC_CCM_CCGR4_CG9_OFFSET 18
1550+#define MXC_CCM_CCGR4_CG8_OFFSET 16
1551+#define MXC_CCM_CCGR4_CG7_OFFSET 14
1552+#define MXC_CCM_CCGR4_CG6_OFFSET 12
1553+#define MXC_CCM_CCGR4_CG5_OFFSET 10
1554+#define MXC_CCM_CCGR4_CG4_OFFSET 8
1555+#define MXC_CCM_CCGR4_CG3_OFFSET 6
1556+#define MXC_CCM_CCGR4_CG2_OFFSET 4
1557+#define MXC_CCM_CCGR4_CG1_OFFSET 2
1558+#define MXC_CCM_CCGR4_CG0_OFFSET 0
1559+
1560+#define MXC_CCM_CCGR5_CG15_OFFSET 30
1561+#define MXC_CCM_CCGR5_CG14_OFFSET 28
1562+#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
1563+#define MXC_CCM_CCGR5_CG13_OFFSET 26
1564+#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
1565+#define MXC_CCM_CCGR5_CG12_OFFSET 24
1566+#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
1567+#define MXC_CCM_CCGR5_CG11_OFFSET 22
1568+#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
1569+#define MXC_CCM_CCGR5_CG10_OFFSET 20
1570+#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
1571+#define MXC_CCM_CCGR5_CG9_OFFSET 18
1572+#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
1573+#define MXC_CCM_CCGR5_CG8_OFFSET 16
1574+#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
1575+#define MXC_CCM_CCGR5_CG7_OFFSET 14
1576+#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
1577+#define MXC_CCM_CCGR5_CG6_OFFSET 12
1578+#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
1579+#define MXC_CCM_CCGR5_CG5_OFFSET 10
1580+#define MXC_CCM_CCGR5_CG4_OFFSET 8
1581+#define MXC_CCM_CCGR5_CG3_OFFSET 6
1582+#define MXC_CCM_CCGR5_CG2_OFFSET 4
1583+#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
1584+#define MXC_CCM_CCGR5_CG1_OFFSET 2
1585+#define MXC_CCM_CCGR5_CG0_OFFSET 0
1586+
1587+#define MXC_CCM_CCGR6_CG15_OFFSET 30
1588+#define MXC_CCM_CCGR6_CG14_OFFSET 28
1589+#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
1590+#define MXC_CCM_CCGR6_CG13_OFFSET 26
1591+#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
1592+#define MXC_CCM_CCGR6_CG12_OFFSET 24
1593+#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
1594+#define MXC_CCM_CCGR6_CG11_OFFSET 22
1595+#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
1596+#define MXC_CCM_CCGR6_CG10_OFFSET 20
1597+#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
1598+#define MXC_CCM_CCGR6_CG9_OFFSET 18
1599+#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
1600+#define MXC_CCM_CCGR6_CG8_OFFSET 16
1601+#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
1602+#define MXC_CCM_CCGR6_CG7_OFFSET 14
1603+#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
1604+#define MXC_CCM_CCGR6_CG6_OFFSET 12
1605+#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
1606+#define MXC_CCM_CCGR6_CG5_OFFSET 10
1607+#define MXC_CCM_CCGR6_CG4_OFFSET 8
1608+#define MXC_CCM_CCGR6_CG3_OFFSET 6
1609+#define MXC_CCM_CCGR6_CG2_OFFSET 4
1610+#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
1611+#define MXC_CCM_CCGR6_CG1_OFFSET 2
1612+#define MXC_CCM_CCGR6_CG0_OFFSET 0
1613+
1614+#define MXC_CCM_CCGR7_CG15_OFFSET 30
1615+#define MXC_CCM_CCGR7_CG14_OFFSET 28
1616+#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
1617+#define MXC_CCM_CCGR7_CG13_OFFSET 26
1618+#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
1619+#define MXC_CCM_CCGR7_CG12_OFFSET 24
1620+#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
1621+#define MXC_CCM_CCGR7_CG11_OFFSET 22
1622+#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
1623+#define MXC_CCM_CCGR7_CG10_OFFSET 20
1624+#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
1625+#define MXC_CCM_CCGR7_CG9_OFFSET 18
1626+#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
1627+#define MXC_CCM_CCGR7_CG8_OFFSET 16
1628+#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
1629+#define MXC_CCM_CCGR7_CG7_OFFSET 14
1630+#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
1631+#define MXC_CCM_CCGR7_CG6_OFFSET 12
1632+#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
1633+#define MXC_CCM_CCGR7_CG5_OFFSET 10
1634+#define MXC_CCM_CCGR7_CG4_OFFSET 8
1635+#define MXC_CCM_CCGR7_CG3_OFFSET 6
1636+#define MXC_CCM_CCGR7_CG2_OFFSET 4
1637+#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
1638+#define MXC_CCM_CCGR7_CG1_OFFSET 2
1639+#define MXC_CCM_CCGR7_CG0_OFFSET 0
1640+#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
1641+#define BP_ANADIG_PLL_SYS_RSVD0 20
1642+#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
1643+#define BF_ANADIG_PLL_SYS_RSVD0(v) \
1644+ (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
1645+#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
1646+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
1647+#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
1648+#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
1649+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
1650+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
1651+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
1652+ (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
1653+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
1654+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
1655+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
1656+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
1657+#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
1658+#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
1659+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
1660+#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
1661+#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
1662+#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
1663+#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
1664+#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
1665+#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
1666+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
1667+ (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
1668+
1669+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
1670+#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
1671+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
1672+#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
1673+ (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
1674+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
1675+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
1676+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
1677+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
1678+ (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
1679+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1680+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1681+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1682+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1683+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
1684+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
1685+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
1686+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
1687+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
1688+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
1689+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
1690+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
1691+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
1692+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
1693+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
1694+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
1695+ (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
1696+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
1697+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
1698+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
1699+ (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1700+
1701+#define BM_ANADIG_PLL_528_LOCK 0x80000000
1702+#define BP_ANADIG_PLL_528_RSVD1 19
1703+#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
1704+#define BF_ANADIG_PLL_528_RSVD1(v) \
1705+ (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
1706+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
1707+#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
1708+#define BM_ANADIG_PLL_528_BYPASS 0x00010000
1709+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
1710+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
1711+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
1712+ (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1713+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1714+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1715+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1716+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1717+#define BM_ANADIG_PLL_528_ENABLE 0x00002000
1718+#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
1719+#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
1720+#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
1721+#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
1722+#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
1723+#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
1724+#define BP_ANADIG_PLL_528_RSVD0 1
1725+#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
1726+#define BF_ANADIG_PLL_528_RSVD0(v) \
1727+ (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1728+#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
1729+
1730+#define BP_ANADIG_PLL_528_SS_STOP 16
1731+#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
1732+#define BF_ANADIG_PLL_528_SS_STOP(v) \
1733+ (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1734+#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
1735+#define BP_ANADIG_PLL_528_SS_STEP 0
1736+#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
1737+#define BF_ANADIG_PLL_528_SS_STEP(v) \
1738+ (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1739+
1740+#define BP_ANADIG_PLL_528_NUM_RSVD0 30
1741+#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
1742+#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
1743+ (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1744+#define BP_ANADIG_PLL_528_NUM_A 0
1745+#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
1746+#define BF_ANADIG_PLL_528_NUM_A(v) \
1747+ (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1748+
1749+#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
1750+#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
1751+#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
1752+ (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1753+#define BP_ANADIG_PLL_528_DENOM_B 0
1754+#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
1755+#define BF_ANADIG_PLL_528_DENOM_B(v) \
1756+ (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1757+
1758+#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
1759+#define BP_ANADIG_PLL_AUDIO_RSVD0 22
1760+#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
1761+#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
1762+ (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1763+#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
1764+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
1765+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
1766+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
1767+ (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1768+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
1769+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
1770+#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
1771+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
1772+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
1773+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
1774+ (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1775+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1776+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1777+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1778+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1779+#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
1780+#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
1781+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
1782+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
1783+#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
1784+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
1785+#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
1786+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1787+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
1788+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
1789+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1790+
1791+#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
1792+#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
1793+#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
1794+ (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1795+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
1796+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
1797+#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
1798+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1799+
1800+#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
1801+#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
1802+#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
1803+ (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1804+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1805+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
1806+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
1807+ (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1808+
1809+#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
1810+#define BP_ANADIG_PLL_VIDEO_RSVD0 22
1811+#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
1812+#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
1813+ (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1814+#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
1815+#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
1816+#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
1817+#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
1818+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
1819+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
1820+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
1821+#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
1822+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
1823+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
1824+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
1825+ (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1826+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1827+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1828+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1829+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1830+#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
1831+#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
1832+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
1833+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
1834+#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
1835+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
1836+#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
1837+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1838+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
1839+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
1840+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1841+
1842+#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
1843+#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
1844+#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
1845+ (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1846+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
1847+#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
1848+#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
1849+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1850+
1851+#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
1852+#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
1853+#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
1854+ (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1855+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1856+#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
1857+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
1858+ (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1859+
1860+#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
1861+#define BP_ANADIG_PLL_ENET_RSVD1 21
1862+#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
1863+#define BF_ANADIG_PLL_ENET_RSVD1(v) \
1864+ (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1865+#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
1866+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
1867+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
1868+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
1869+#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
1870+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1871+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
1872+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1873+ (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1874+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1875+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1876+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1877+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1878+#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1879+#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1880+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1881+#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1882+#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1883+#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1884+#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1885+#define BP_ANADIG_PLL_ENET_RSVD0 2
1886+#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1887+#define BF_ANADIG_PLL_ENET_RSVD0(v) \
1888+ (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1889+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1890+#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1891+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1892+ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1893+
1894+#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1895+#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1896+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
1897+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1898+#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1899+ (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1900+#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1901+#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1902+#define BP_ANADIG_PFD_480_PFD2_FRAC 16
1903+#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1904+#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1905+ (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1906+#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1907+#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1908+#define BP_ANADIG_PFD_480_PFD1_FRAC 8
1909+#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1910+#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1911+ (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1912+#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1913+#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1914+#define BP_ANADIG_PFD_480_PFD0_FRAC 0
1915+#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1916+#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1917+ (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1918+
1919+#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1920+#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1921+#define BP_ANADIG_PFD_528_PFD3_FRAC 24
1922+#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1923+#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1924+ (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1925+#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1926+#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1927+#define BP_ANADIG_PFD_528_PFD2_FRAC 16
1928+#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1929+#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1930+ (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1931+#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1932+#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1933+#define BP_ANADIG_PFD_528_PFD1_FRAC 8
1934+#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1935+#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1936+ (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1937+#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1938+#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1939+#define BP_ANADIG_PFD_528_PFD0_FRAC 0
1940+#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1941+#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1942+ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1943+
1944+#define PLL2_PFD0_FREQ 352000000
1945+#define PLL2_PFD1_FREQ 594000000
1946+#define PLL2_PFD2_FREQ 400000000
1947+#define PLL2_PFD2_DIV_FREQ 200000000
1948+#define PLL3_PFD0_FREQ 720000000
1949+#define PLL3_PFD1_FREQ 540000000
1950+#define PLL3_PFD2_FREQ 508200000
1951+#define PLL3_PFD3_FREQ 454700000
1952+#define PLL3_80M 80000000
1953+#define PLL3_60M 60000000
1954+
1955+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
1956diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
1957index 668e77a..69687a8 100644
1958--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
1959+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
1960@@ -34,5 +34,6 @@ u32 get_cpu_rev(void);
1961 */
1962
1963 int fecmxc_initialize(bd_t *bis);
1964-
1965+u32 get_ahb_clk(void);
1966+u32 get_periph_clk(void);
1967 #endif
1968--
19691.7.10
1970
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