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author | Thomas Elste <thomas.elste@imms.de> | 2014-06-13 15:46:26 +0200 |
---|---|---|
committer | Otavio Salvador <otavio@ossystems.com.br> | 2014-06-16 09:31:40 -0300 |
commit | 8d0b2b7252589e3f652a600e52704009c1769d81 (patch) | |
tree | d049d437b42e93d12b713cb0ce0f2f7b73aac18c /recipes-graphics/drm | |
parent | 668e467beb4b8d7b9fb9a14dfa0dd677d08214f3 (diff) | |
download | meta-fsl-arm-8d0b2b7252589e3f652a600e52704009c1769d81.tar.gz |
libdrm: Add ite instruction to mx6 ARM patch
Building with Angstrom toolchain fails on inline assembler added by
drm-update-arm.patch because of missing ite instruction. Insert
instruction to make the inline assembler block Thumb2 compatible.
Signed-off-by: Thomas Elste <thomas.elste@imms.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat (limited to 'recipes-graphics/drm')
-rw-r--r-- | recipes-graphics/drm/libdrm/mx6/drm-update-arm.patch | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/recipes-graphics/drm/libdrm/mx6/drm-update-arm.patch b/recipes-graphics/drm/libdrm/mx6/drm-update-arm.patch index 4389fe4..1160cd1 100644 --- a/recipes-graphics/drm/libdrm/mx6/drm-update-arm.patch +++ b/recipes-graphics/drm/libdrm/mx6/drm-update-arm.patch | |||
@@ -9,7 +9,7 @@ Signed-off-by: Evan Kotara <evan.kotara@freescale.com> | |||
9 | diff --git a/xf86drm.h b/xf86drm.h | 9 | diff --git a/xf86drm.h b/xf86drm.h |
10 | --- a/xf86drm.h | 10 | --- a/xf86drm.h |
11 | +++ b/xf86drm.h | 11 | +++ b/xf86drm.h |
12 | @@ -455,6 +455,22 @@ do { register unsigned int __old __asm("o0"); \ | 12 | @@ -461,6 +461,23 @@ do { register unsigned int __old __asm(" |
13 | : "cr0", "memory"); \ | 13 | : "cr0", "memory"); \ |
14 | } while (0) | 14 | } while (0) |
15 | 15 | ||
@@ -22,6 +22,7 @@ diff --git a/xf86drm.h b/xf86drm.h | |||
22 | + __asm__ __volatile__ ( \ | 22 | + __asm__ __volatile__ ( \ |
23 | + "1: ldrex %0, [%1]\n" \ | 23 | + "1: ldrex %0, [%1]\n" \ |
24 | + " teq %0, %2\n" \ | 24 | + " teq %0, %2\n" \ |
25 | + " ite eq\n" \ | ||
25 | + " strexeq %0, %3, [%1]\n" \ | 26 | + " strexeq %0, %3, [%1]\n" \ |
26 | + " movne %0, #1\n" \ | 27 | + " movne %0, #1\n" \ |
27 | + : "=&r" (__ret) \ | 28 | + : "=&r" (__ret) \ |