diff options
author | Otavio Salvador <otavio@ossystems.com.br> | 2012-05-29 13:29:12 -0300 |
---|---|---|
committer | Otavio Salvador <otavio@ossystems.com.br> | 2012-05-29 13:29:12 -0300 |
commit | d0d8a61566fb5d76cd469474eb3318976de46132 (patch) | |
tree | 8e8e763627343cc7e1bc0bfd73f4d26ba05bc57f | |
parent | 8e411a93315bd86d41af71783a10ec5bf717ee33 (diff) | |
download | meta-fsl-arm-d0d8a61566fb5d76cd469474eb3318976de46132.tar.gz |
u-boot: move to use github's tree for tracking the changes
This has the same patches as before but avoid using many patch files.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
57 files changed, 3 insertions, 9223 deletions
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0001-MX5-Add-definitions-for-SATA-controller.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0001-MX5-Add-definitions-for-SATA-controller.patch deleted file mode 100644 index a4da345..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0001-MX5-Add-definitions-for-SATA-controller.patch +++ /dev/null | |||
@@ -1,57 +0,0 @@ | |||
1 | From 4a7ee25e3f89d77a8ced081b73aebfb7a882302c Mon Sep 17 00:00:00 2001 | ||
2 | From: Stefano Babic <sbabic@denx.de> | ||
3 | Date: Wed, 22 Feb 2012 00:24:36 +0000 | ||
4 | Subject: [PATCH 01/56] MX5: Add definitions for SATA controller | ||
5 | |||
6 | Add base address and MXC_SATA_CLK to return | ||
7 | the clock used for the SATA controller. | ||
8 | |||
9 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
10 | CC: Fabio Estevam <fabio.estevam@freescale.com> | ||
11 | CC: Dirk Behme <dirk.behme@de.bosch.com> | ||
12 | --- | ||
13 | arch/arm/cpu/armv7/mx5/clock.c | 2 ++ | ||
14 | arch/arm/include/asm/arch-mx5/clock.h | 1 + | ||
15 | arch/arm/include/asm/arch-mx5/imx-regs.h | 1 + | ||
16 | 3 files changed, 4 insertions(+) | ||
17 | |||
18 | diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c | ||
19 | index e92f106..8f8d01c 100644 | ||
20 | --- a/arch/arm/cpu/armv7/mx5/clock.c | ||
21 | +++ b/arch/arm/cpu/armv7/mx5/clock.c | ||
22 | @@ -380,6 +380,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) | ||
23 | case MXC_FEC_CLK: | ||
24 | return decode_pll(mxc_plls[PLL1_CLOCK], | ||
25 | CONFIG_SYS_MX5_HCLK); | ||
26 | + case MXC_SATA_CLK: | ||
27 | + return get_ahb_clk(); | ||
28 | default: | ||
29 | break; | ||
30 | } | ||
31 | diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h | ||
32 | index ea972a3..f9f82f3 100644 | ||
33 | --- a/arch/arm/include/asm/arch-mx5/clock.h | ||
34 | +++ b/arch/arm/include/asm/arch-mx5/clock.h | ||
35 | @@ -32,6 +32,7 @@ enum mxc_clock { | ||
36 | MXC_UART_CLK, | ||
37 | MXC_CSPI_CLK, | ||
38 | MXC_FEC_CLK, | ||
39 | + MXC_SATA_CLK, | ||
40 | }; | ||
41 | |||
42 | unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); | ||
43 | diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h | ||
44 | index 4fa6658..262517e 100644 | ||
45 | --- a/arch/arm/include/asm/arch-mx5/imx-regs.h | ||
46 | +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h | ||
47 | @@ -43,6 +43,7 @@ | ||
48 | #define NFC_BASE_ADDR_AXI 0xF7FF0000 | ||
49 | #define IRAM_BASE_ADDR 0xF8000000 | ||
50 | #define CS1_BASE_ADDR 0xF4000000 | ||
51 | +#define SATA_BASE_ADDR 0x10000000 | ||
52 | #else | ||
53 | #error "CPU_TYPE not defined" | ||
54 | #endif | ||
55 | -- | ||
56 | 1.7.10 | ||
57 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0002-SATA-check-for-return-value-from-sata-functions.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0002-SATA-check-for-return-value-from-sata-functions.patch deleted file mode 100644 index 98135d7..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0002-SATA-check-for-return-value-from-sata-functions.patch +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | From 5b37d183ef45f83c23f7a85d3bc87708fb07598a Mon Sep 17 00:00:00 2001 | ||
2 | From: Stefano Babic <sbabic@denx.de> | ||
3 | Date: Wed, 22 Feb 2012 00:24:37 +0000 | ||
4 | Subject: [PATCH 02/56] SATA: check for return value from sata functions | ||
5 | |||
6 | sata functions are called even if previous functions failed | ||
7 | because return value is not checked. | ||
8 | |||
9 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
10 | CC: Dirk Behme <dirk.behme@de.bosch.com> | ||
11 | CC: Fabio Estevam <fabio.estevam@freescale.com> | ||
12 | --- | ||
13 | common/cmd_sata.c | 9 ++++++--- | ||
14 | 1 file changed, 6 insertions(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/common/cmd_sata.c b/common/cmd_sata.c | ||
17 | index 7b1703f..3f98235 100644 | ||
18 | --- a/common/cmd_sata.c | ||
19 | +++ b/common/cmd_sata.c | ||
20 | @@ -48,9 +48,12 @@ int __sata_initialize(void) | ||
21 | sata_dev_desc[i].block_write = sata_write; | ||
22 | |||
23 | rc = init_sata(i); | ||
24 | - rc = scan_sata(i); | ||
25 | - if ((sata_dev_desc[i].lba > 0) && (sata_dev_desc[i].blksz > 0)) | ||
26 | - init_part(&sata_dev_desc[i]); | ||
27 | + if (!rc) { | ||
28 | + rc = scan_sata(i); | ||
29 | + if (!rc && (sata_dev_desc[i].lba > 0) && | ||
30 | + (sata_dev_desc[i].blksz > 0)) | ||
31 | + init_part(&sata_dev_desc[i]); | ||
32 | + } | ||
33 | } | ||
34 | sata_curr_device = 0; | ||
35 | return rc; | ||
36 | -- | ||
37 | 1.7.10 | ||
38 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0003-MX53-add-function-to-set-SATA-clock-to-internal.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0003-MX53-add-function-to-set-SATA-clock-to-internal.patch deleted file mode 100644 index 2a4eb94..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0003-MX53-add-function-to-set-SATA-clock-to-internal.patch +++ /dev/null | |||
@@ -1,77 +0,0 @@ | |||
1 | From b22729b27625107061733c718cb49a394fd41a4a Mon Sep 17 00:00:00 2001 | ||
2 | From: Stefano Babic <sbabic@denx.de> | ||
3 | Date: Wed, 22 Feb 2012 00:24:38 +0000 | ||
4 | Subject: [PATCH 03/56] MX53: add function to set SATA clock to internal | ||
5 | |||
6 | The MX53 SATA interface can use an internal clock (USB PHY1) | ||
7 | instead of an external clock. This is an undocumented feature, but used | ||
8 | on most Freescale's evaluation boards, such as MX53-loco. | ||
9 | |||
10 | As stated by Freescale's support: | ||
11 | |||
12 | Fuses (but not pins) may be used to configure SATA clocks. | ||
13 | Particularly the i.MX53 Fuse_Map contains the next information | ||
14 | about configuring SATA clocks : | ||
15 | SATA_ALT_REF_CLK[1:0] (offset 0x180C) | ||
16 | |||
17 | '00' - 100MHz (External) | ||
18 | '01' - 50MHz (External) | ||
19 | '10' - 120MHz, internal (USB PHY) | ||
20 | '11' - Reserved | ||
21 | |||
22 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
23 | CC: Fabio Estevam <fabio.estevam@freescale.com> | ||
24 | --- | ||
25 | arch/arm/cpu/armv7/mx5/clock.c | 24 ++++++++++++++++++++++++ | ||
26 | arch/arm/include/asm/arch-mx5/clock.h | 1 + | ||
27 | 2 files changed, 25 insertions(+) | ||
28 | |||
29 | diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c | ||
30 | index 8f8d01c..d769a4d 100644 | ||
31 | --- a/arch/arm/cpu/armv7/mx5/clock.c | ||
32 | +++ b/arch/arm/cpu/armv7/mx5/clock.c | ||
33 | @@ -399,6 +399,30 @@ u32 imx_get_fecclk(void) | ||
34 | return mxc_get_clock(MXC_IPG_CLK); | ||
35 | } | ||
36 | |||
37 | +#ifdef CONFIG_MX53 | ||
38 | +/* | ||
39 | + * The clock for the external interface can be set to use internal clock | ||
40 | + * if fuse bank 4, row 3, bit 2 is set. | ||
41 | + * This is an undocumented feature and it was confirmed by Freescale's support: | ||
42 | + * Fuses (but not pins) may be used to configure SATA clocks. | ||
43 | + * Particularly the i.MX53 Fuse_Map contains the next information | ||
44 | + * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) | ||
45 | + * '00' - 100MHz (External) | ||
46 | + * '01' - 50MHz (External) | ||
47 | + * '10' - 120MHz, internal (USB PHY) | ||
48 | + * '11' - Reserved | ||
49 | +*/ | ||
50 | +void mxc_set_sata_internal_clock(void) | ||
51 | +{ | ||
52 | + u32 *tmp_base = | ||
53 | + (u32 *)(IIM_BASE_ADDR + 0x180c); | ||
54 | + | ||
55 | + set_usb_phy1_clk(); | ||
56 | + | ||
57 | + writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base); | ||
58 | +} | ||
59 | +#endif | ||
60 | + | ||
61 | /* | ||
62 | * Dump some core clockes. | ||
63 | */ | ||
64 | diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h | ||
65 | index f9f82f3..e822809 100644 | ||
66 | --- a/arch/arm/include/asm/arch-mx5/clock.h | ||
67 | +++ b/arch/arm/include/asm/arch-mx5/clock.h | ||
68 | @@ -45,5 +45,6 @@ void set_usb_phy2_clk(void); | ||
69 | void enable_usb_phy2_clk(unsigned char enable); | ||
70 | void set_usboh3_clk(void); | ||
71 | void enable_usboh3_clk(unsigned char enable); | ||
72 | +void mxc_set_sata_internal_clock(void); | ||
73 | |||
74 | #endif /* __ASM_ARCH_CLOCK_H */ | ||
75 | -- | ||
76 | 1.7.10 | ||
77 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0004-SATA-add-driver-for-MX5-MX6-SOCs.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0004-SATA-add-driver-for-MX5-MX6-SOCs.patch deleted file mode 100644 index e4e93a6..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0004-SATA-add-driver-for-MX5-MX6-SOCs.patch +++ /dev/null | |||
@@ -1,1372 +0,0 @@ | |||
1 | From 160e7d7c3fbbcbb60ba71eb984f633db26494646 Mon Sep 17 00:00:00 2001 | ||
2 | From: Stefano Babic <sbabic@denx.de> | ||
3 | Date: Wed, 22 Feb 2012 00:24:39 +0000 | ||
4 | Subject: [PATCH 04/56] SATA: add driver for MX5 / MX6 SOCs | ||
5 | |||
6 | This driver is part of Freescale's LTIB for | ||
7 | MX5 / MX6. | ||
8 | |||
9 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
10 | Signed-off-by: Terry Lv <r65388@freescale.com> | ||
11 | CC: Fabio Estevam <fabio.estevam@freescale.com> | ||
12 | CC: Dirk Behme <dirk.behme@de.bosch.com> | ||
13 | --- | ||
14 | drivers/block/Makefile | 1 + | ||
15 | drivers/block/dwc_ahsata.c | 969 ++++++++++++++++++++++++++++++++++++++++++++ | ||
16 | drivers/block/dwc_ahsata.h | 335 +++++++++++++++ | ||
17 | include/ahci.h | 5 +- | ||
18 | 4 files changed, 1308 insertions(+), 2 deletions(-) | ||
19 | create mode 100644 drivers/block/dwc_ahsata.c | ||
20 | create mode 100644 drivers/block/dwc_ahsata.h | ||
21 | |||
22 | diff --git a/drivers/block/Makefile b/drivers/block/Makefile | ||
23 | index 98560ef..b9c2047 100644 | ||
24 | --- a/drivers/block/Makefile | ||
25 | +++ b/drivers/block/Makefile | ||
26 | @@ -27,6 +27,7 @@ LIB := $(obj)libblock.o | ||
27 | |||
28 | COBJS-$(CONFIG_SCSI_AHCI) += ahci.o | ||
29 | COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o | ||
30 | +COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o | ||
31 | COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o | ||
32 | COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o | ||
33 | COBJS-$(CONFIG_LIBATA) += libata.o | ||
34 | diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c | ||
35 | new file mode 100644 | ||
36 | index 0000000..2703d3d | ||
37 | --- /dev/null | ||
38 | +++ b/drivers/block/dwc_ahsata.c | ||
39 | @@ -0,0 +1,969 @@ | ||
40 | +/* | ||
41 | + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | ||
42 | + * Terry Lv <r65388@freescale.com> | ||
43 | + * | ||
44 | + * See file CREDITS for list of people who contributed to this | ||
45 | + * project. | ||
46 | + * | ||
47 | + * This program is free software; you can redistribute it and/or | ||
48 | + * modify it under the terms of the GNU General Public License as | ||
49 | + * published by the Free Software Foundation; either version 2 of | ||
50 | + * the License, or (at your option) any later version. | ||
51 | + * | ||
52 | + * This program is distributed in the hope that it will be useful, | ||
53 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
54 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
55 | + * GNU General Public License for more details. | ||
56 | + * | ||
57 | + * You should have received a copy of the GNU General Public License | ||
58 | + * along with this program; if not, write to the Free Software | ||
59 | + * Foundation, Inc. | ||
60 | + * | ||
61 | + */ | ||
62 | + | ||
63 | +#include <libata.h> | ||
64 | +#include <ahci.h> | ||
65 | +#include <fis.h> | ||
66 | + | ||
67 | +#include <common.h> | ||
68 | +#include <malloc.h> | ||
69 | +#include <linux/ctype.h> | ||
70 | +#include <asm/errno.h> | ||
71 | +#include <asm/io.h> | ||
72 | +#include <linux/bitops.h> | ||
73 | +#include <asm/arch/clock.h> | ||
74 | +#include "dwc_ahsata.h" | ||
75 | + | ||
76 | +struct sata_port_regs { | ||
77 | + u32 clb; | ||
78 | + u32 clbu; | ||
79 | + u32 fb; | ||
80 | + u32 fbu; | ||
81 | + u32 is; | ||
82 | + u32 ie; | ||
83 | + u32 cmd; | ||
84 | + u32 res1[1]; | ||
85 | + u32 tfd; | ||
86 | + u32 sig; | ||
87 | + u32 ssts; | ||
88 | + u32 sctl; | ||
89 | + u32 serr; | ||
90 | + u32 sact; | ||
91 | + u32 ci; | ||
92 | + u32 sntf; | ||
93 | + u32 res2[1]; | ||
94 | + u32 dmacr; | ||
95 | + u32 res3[1]; | ||
96 | + u32 phycr; | ||
97 | + u32 physr; | ||
98 | +}; | ||
99 | + | ||
100 | +struct sata_host_regs { | ||
101 | + u32 cap; | ||
102 | + u32 ghc; | ||
103 | + u32 is; | ||
104 | + u32 pi; | ||
105 | + u32 vs; | ||
106 | + u32 ccc_ctl; | ||
107 | + u32 ccc_ports; | ||
108 | + u32 res1[2]; | ||
109 | + u32 cap2; | ||
110 | + u32 res2[30]; | ||
111 | + u32 bistafr; | ||
112 | + u32 bistcr; | ||
113 | + u32 bistfctr; | ||
114 | + u32 bistsr; | ||
115 | + u32 bistdecr; | ||
116 | + u32 res3[2]; | ||
117 | + u32 oobr; | ||
118 | + u32 res4[8]; | ||
119 | + u32 timer1ms; | ||
120 | + u32 res5[1]; | ||
121 | + u32 gparam1r; | ||
122 | + u32 gparam2r; | ||
123 | + u32 pparamr; | ||
124 | + u32 testr; | ||
125 | + u32 versionr; | ||
126 | + u32 idr; | ||
127 | +}; | ||
128 | + | ||
129 | +#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) | ||
130 | +#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) | ||
131 | + | ||
132 | +#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) | ||
133 | + | ||
134 | +static int is_ready; | ||
135 | + | ||
136 | +static inline u32 ahci_port_base(u32 base, u32 port) | ||
137 | +{ | ||
138 | + return base + 0x100 + (port * 0x80); | ||
139 | +} | ||
140 | + | ||
141 | +static int waiting_for_cmd_completed(u8 *offset, | ||
142 | + int timeout_msec, | ||
143 | + u32 sign) | ||
144 | +{ | ||
145 | + int i; | ||
146 | + u32 status; | ||
147 | + | ||
148 | + for (i = 0; | ||
149 | + ((status = readl(offset)) & sign) && i < timeout_msec; | ||
150 | + ++i) | ||
151 | + mdelay(1); | ||
152 | + | ||
153 | + return (i < timeout_msec) ? 0 : -1; | ||
154 | +} | ||
155 | + | ||
156 | +static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent, | ||
157 | + int clk) | ||
158 | +{ | ||
159 | + struct sata_host_regs *host_mmio = | ||
160 | + (struct sata_host_regs *)probe_ent->mmio_base; | ||
161 | + | ||
162 | + writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr)); | ||
163 | + writel(0x02060b14, &(host_mmio->oobr)); | ||
164 | + | ||
165 | + return 0; | ||
166 | +} | ||
167 | + | ||
168 | +static int ahci_host_init(struct ahci_probe_ent *probe_ent) | ||
169 | +{ | ||
170 | + u32 tmp, cap_save, num_ports; | ||
171 | + int i, j, timeout = 1000; | ||
172 | + struct sata_port_regs *port_mmio = NULL; | ||
173 | + struct sata_host_regs *host_mmio = | ||
174 | + (struct sata_host_regs *)probe_ent->mmio_base; | ||
175 | + int clk = mxc_get_clock(MXC_SATA_CLK); | ||
176 | + | ||
177 | + cap_save = readl(&(host_mmio->cap)); | ||
178 | + cap_save |= SATA_HOST_CAP_SSS; | ||
179 | + | ||
180 | + /* global controller reset */ | ||
181 | + tmp = readl(&(host_mmio->ghc)); | ||
182 | + if ((tmp & SATA_HOST_GHC_HR) == 0) | ||
183 | + writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc)); | ||
184 | + | ||
185 | + while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR) | ||
186 | + && --timeout) | ||
187 | + ; | ||
188 | + | ||
189 | + if (timeout <= 0) { | ||
190 | + debug("controller reset failed (0x%x)\n", tmp); | ||
191 | + return -1; | ||
192 | + } | ||
193 | + | ||
194 | + /* Set timer 1ms */ | ||
195 | + writel(clk / 1000, &(host_mmio->timer1ms)); | ||
196 | + | ||
197 | + ahci_setup_oobr(probe_ent, 0); | ||
198 | + | ||
199 | + writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc)); | ||
200 | + writel(cap_save, &(host_mmio->cap)); | ||
201 | + num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; | ||
202 | + writel_with_flush((1 << num_ports) - 1, | ||
203 | + &(host_mmio->pi)); | ||
204 | + | ||
205 | + /* | ||
206 | + * Determine which Ports are implemented by the DWC_ahsata, | ||
207 | + * by reading the PI register. This bit map value aids the | ||
208 | + * software to determine how many Ports are available and | ||
209 | + * which Port registers need to be initialized. | ||
210 | + */ | ||
211 | + probe_ent->cap = readl(&(host_mmio->cap)); | ||
212 | + probe_ent->port_map = readl(&(host_mmio->pi)); | ||
213 | + | ||
214 | + /* Determine how many command slots the HBA supports */ | ||
215 | + probe_ent->n_ports = | ||
216 | + (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1; | ||
217 | + | ||
218 | + debug("cap 0x%x port_map 0x%x n_ports %d\n", | ||
219 | + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); | ||
220 | + | ||
221 | + for (i = 0; i < probe_ent->n_ports; i++) { | ||
222 | + probe_ent->port[i].port_mmio = | ||
223 | + ahci_port_base((u32)host_mmio, i); | ||
224 | + port_mmio = | ||
225 | + (struct sata_port_regs *)probe_ent->port[i].port_mmio; | ||
226 | + | ||
227 | + /* Ensure that the DWC_ahsata is in idle state */ | ||
228 | + tmp = readl(&(port_mmio->cmd)); | ||
229 | + | ||
230 | + /* | ||
231 | + * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR | ||
232 | + * are all cleared, the Port is in an idle state. | ||
233 | + */ | ||
234 | + if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | | ||
235 | + SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { | ||
236 | + | ||
237 | + /* | ||
238 | + * System software places a Port into the idle state by | ||
239 | + * clearing P#CMD.ST and waiting for P#CMD.CR to return | ||
240 | + * 0 when read. | ||
241 | + */ | ||
242 | + tmp &= ~SATA_PORT_CMD_ST; | ||
243 | + writel_with_flush(tmp, &(port_mmio->cmd)); | ||
244 | + | ||
245 | + /* | ||
246 | + * spec says 500 msecs for each bit, so | ||
247 | + * this is slightly incorrect. | ||
248 | + */ | ||
249 | + mdelay(500); | ||
250 | + | ||
251 | + timeout = 1000; | ||
252 | + while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR) | ||
253 | + && --timeout) | ||
254 | + ; | ||
255 | + | ||
256 | + if (timeout <= 0) { | ||
257 | + debug("port reset failed (0x%x)\n", tmp); | ||
258 | + return -1; | ||
259 | + } | ||
260 | + } | ||
261 | + | ||
262 | + /* Spin-up device */ | ||
263 | + tmp = readl(&(port_mmio->cmd)); | ||
264 | + writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd)); | ||
265 | + | ||
266 | + /* Wait for spin-up to finish */ | ||
267 | + timeout = 1000; | ||
268 | + while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD) | ||
269 | + && --timeout) | ||
270 | + ; | ||
271 | + if (timeout <= 0) { | ||
272 | + debug("Spin-Up can't finish!\n"); | ||
273 | + return -1; | ||
274 | + } | ||
275 | + | ||
276 | + for (j = 0; j < 100; ++j) { | ||
277 | + mdelay(10); | ||
278 | + tmp = readl(&(port_mmio->ssts)); | ||
279 | + if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || | ||
280 | + ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) | ||
281 | + break; | ||
282 | + } | ||
283 | + | ||
284 | + /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ | ||
285 | + timeout = 1000; | ||
286 | + while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X) | ||
287 | + && --timeout) | ||
288 | + ; | ||
289 | + if (timeout <= 0) { | ||
290 | + debug("Can't find DIAG_X set!\n"); | ||
291 | + return -1; | ||
292 | + } | ||
293 | + | ||
294 | + /* | ||
295 | + * For each implemented Port, clear the P#SERR | ||
296 | + * register, by writing ones to each implemented\ | ||
297 | + * bit location. | ||
298 | + */ | ||
299 | + tmp = readl(&(port_mmio->serr)); | ||
300 | + debug("P#SERR 0x%x\n", | ||
301 | + tmp); | ||
302 | + writel(tmp, &(port_mmio->serr)); | ||
303 | + | ||
304 | + /* Ack any pending irq events for this port */ | ||
305 | + tmp = readl(&(host_mmio->is)); | ||
306 | + debug("IS 0x%x\n", tmp); | ||
307 | + if (tmp) | ||
308 | + writel(tmp, &(host_mmio->is)); | ||
309 | + | ||
310 | + writel(1 << i, &(host_mmio->is)); | ||
311 | + | ||
312 | + /* set irq mask (enables interrupts) */ | ||
313 | + writel(DEF_PORT_IRQ, &(port_mmio->ie)); | ||
314 | + | ||
315 | + /* register linkup ports */ | ||
316 | + tmp = readl(&(port_mmio->ssts)); | ||
317 | + debug("Port %d status: 0x%x\n", i, tmp); | ||
318 | + if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) | ||
319 | + probe_ent->link_port_map |= (0x01 << i); | ||
320 | + } | ||
321 | + | ||
322 | + tmp = readl(&(host_mmio->ghc)); | ||
323 | + debug("GHC 0x%x\n", tmp); | ||
324 | + writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc)); | ||
325 | + tmp = readl(&(host_mmio->ghc)); | ||
326 | + debug("GHC 0x%x\n", tmp); | ||
327 | + | ||
328 | + return 0; | ||
329 | +} | ||
330 | + | ||
331 | +static void ahci_print_info(struct ahci_probe_ent *probe_ent) | ||
332 | +{ | ||
333 | + struct sata_host_regs *host_mmio = | ||
334 | + (struct sata_host_regs *)probe_ent->mmio_base; | ||
335 | + u32 vers, cap, impl, speed; | ||
336 | + const char *speed_s; | ||
337 | + const char *scc_s; | ||
338 | + | ||
339 | + vers = readl(&(host_mmio->vs)); | ||
340 | + cap = probe_ent->cap; | ||
341 | + impl = probe_ent->port_map; | ||
342 | + | ||
343 | + speed = (cap & SATA_HOST_CAP_ISS_MASK) | ||
344 | + >> SATA_HOST_CAP_ISS_OFFSET; | ||
345 | + if (speed == 1) | ||
346 | + speed_s = "1.5"; | ||
347 | + else if (speed == 2) | ||
348 | + speed_s = "3"; | ||
349 | + else | ||
350 | + speed_s = "?"; | ||
351 | + | ||
352 | + scc_s = "SATA"; | ||
353 | + | ||
354 | + printf("AHCI %02x%02x.%02x%02x " | ||
355 | + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | ||
356 | + (vers >> 24) & 0xff, | ||
357 | + (vers >> 16) & 0xff, | ||
358 | + (vers >> 8) & 0xff, | ||
359 | + vers & 0xff, | ||
360 | + ((cap >> 8) & 0x1f) + 1, | ||
361 | + (cap & 0x1f) + 1, | ||
362 | + speed_s, | ||
363 | + impl, | ||
364 | + scc_s); | ||
365 | + | ||
366 | + printf("flags: " | ||
367 | + "%s%s%s%s%s%s" | ||
368 | + "%s%s%s%s%s%s%s\n", | ||
369 | + cap & (1 << 31) ? "64bit " : "", | ||
370 | + cap & (1 << 30) ? "ncq " : "", | ||
371 | + cap & (1 << 28) ? "ilck " : "", | ||
372 | + cap & (1 << 27) ? "stag " : "", | ||
373 | + cap & (1 << 26) ? "pm " : "", | ||
374 | + cap & (1 << 25) ? "led " : "", | ||
375 | + cap & (1 << 24) ? "clo " : "", | ||
376 | + cap & (1 << 19) ? "nz " : "", | ||
377 | + cap & (1 << 18) ? "only " : "", | ||
378 | + cap & (1 << 17) ? "pmp " : "", | ||
379 | + cap & (1 << 15) ? "pio " : "", | ||
380 | + cap & (1 << 14) ? "slum " : "", | ||
381 | + cap & (1 << 13) ? "part " : ""); | ||
382 | +} | ||
383 | + | ||
384 | +static int ahci_init_one(int pdev) | ||
385 | +{ | ||
386 | + int rc; | ||
387 | + struct ahci_probe_ent *probe_ent = NULL; | ||
388 | + | ||
389 | + probe_ent = malloc(sizeof(struct ahci_probe_ent)); | ||
390 | + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); | ||
391 | + probe_ent->dev = pdev; | ||
392 | + | ||
393 | + probe_ent->host_flags = ATA_FLAG_SATA | ||
394 | + | ATA_FLAG_NO_LEGACY | ||
395 | + | ATA_FLAG_MMIO | ||
396 | + | ATA_FLAG_PIO_DMA | ||
397 | + | ATA_FLAG_NO_ATAPI; | ||
398 | + | ||
399 | + probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR; | ||
400 | + | ||
401 | + /* initialize adapter */ | ||
402 | + rc = ahci_host_init(probe_ent); | ||
403 | + if (rc) | ||
404 | + goto err_out; | ||
405 | + | ||
406 | + ahci_print_info(probe_ent); | ||
407 | + | ||
408 | + /* Save the private struct to block device struct */ | ||
409 | + sata_dev_desc[pdev].priv = (void *)probe_ent; | ||
410 | + | ||
411 | + return 0; | ||
412 | + | ||
413 | +err_out: | ||
414 | + return rc; | ||
415 | +} | ||
416 | + | ||
417 | +static int ahci_fill_sg(struct ahci_probe_ent *probe_ent, | ||
418 | + u8 port, unsigned char *buf, int buf_len) | ||
419 | +{ | ||
420 | + struct ahci_ioports *pp = &(probe_ent->port[port]); | ||
421 | + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; | ||
422 | + u32 sg_count, max_bytes; | ||
423 | + int i; | ||
424 | + | ||
425 | + max_bytes = MAX_DATA_BYTES_PER_SG; | ||
426 | + sg_count = ((buf_len - 1) / max_bytes) + 1; | ||
427 | + if (sg_count > AHCI_MAX_SG) { | ||
428 | + printf("Error:Too much sg!\n"); | ||
429 | + return -1; | ||
430 | + } | ||
431 | + | ||
432 | + for (i = 0; i < sg_count; i++) { | ||
433 | + ahci_sg->addr = | ||
434 | + cpu_to_le32((u32)buf + i * max_bytes); | ||
435 | + ahci_sg->addr_hi = 0; | ||
436 | + ahci_sg->flags_size = cpu_to_le32(0x3fffff & | ||
437 | + (buf_len < max_bytes | ||
438 | + ? (buf_len - 1) | ||
439 | + : (max_bytes - 1))); | ||
440 | + ahci_sg++; | ||
441 | + buf_len -= max_bytes; | ||
442 | + } | ||
443 | + | ||
444 | + return sg_count; | ||
445 | +} | ||
446 | + | ||
447 | +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) | ||
448 | +{ | ||
449 | + struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + | ||
450 | + AHCI_CMD_SLOT_SZ * cmd_slot); | ||
451 | + | ||
452 | + memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); | ||
453 | + cmd_hdr->opts = cpu_to_le32(opts); | ||
454 | + cmd_hdr->status = 0; | ||
455 | + cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); | ||
456 | + cmd_hdr->tbl_addr_hi = 0; | ||
457 | +} | ||
458 | + | ||
459 | +#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) | ||
460 | + | ||
461 | +static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent, | ||
462 | + u8 port, struct sata_fis_h2d *cfis, | ||
463 | + u8 *buf, u32 buf_len, s32 is_write) | ||
464 | +{ | ||
465 | + struct ahci_ioports *pp = &(probe_ent->port[port]); | ||
466 | + struct sata_port_regs *port_mmio = | ||
467 | + (struct sata_port_regs *)pp->port_mmio; | ||
468 | + u32 opts; | ||
469 | + int sg_count = 0, cmd_slot = 0; | ||
470 | + | ||
471 | + cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci))); | ||
472 | + if (32 == cmd_slot) { | ||
473 | + printf("Can't find empty command slot!\n"); | ||
474 | + return 0; | ||
475 | + } | ||
476 | + | ||
477 | + /* Check xfer length */ | ||
478 | + if (buf_len > MAX_BYTES_PER_TRANS) { | ||
479 | + printf("Max transfer length is %dB\n\r", | ||
480 | + MAX_BYTES_PER_TRANS); | ||
481 | + return 0; | ||
482 | + } | ||
483 | + | ||
484 | + memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); | ||
485 | + if (buf && buf_len) | ||
486 | + sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len); | ||
487 | + opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); | ||
488 | + if (is_write) | ||
489 | + opts |= 0x40; | ||
490 | + ahci_fill_cmd_slot(pp, cmd_slot, opts); | ||
491 | + | ||
492 | + writel_with_flush(1 << cmd_slot, &(port_mmio->ci)); | ||
493 | + | ||
494 | + if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci), | ||
495 | + 10000, 0x1 << cmd_slot)) { | ||
496 | + printf("timeout exit!\n"); | ||
497 | + return -1; | ||
498 | + } | ||
499 | + debug("ahci_exec_ata_cmd: %d byte transferred.\n", | ||
500 | + pp->cmd_slot->status); | ||
501 | + | ||
502 | + return buf_len; | ||
503 | +} | ||
504 | + | ||
505 | +static void ahci_set_feature(u8 dev, u8 port) | ||
506 | +{ | ||
507 | + struct ahci_probe_ent *probe_ent = | ||
508 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
509 | + struct sata_fis_h2d h2d, *cfis = &h2d; | ||
510 | + | ||
511 | + memset(cfis, 0, sizeof(struct sata_fis_h2d)); | ||
512 | + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | ||
513 | + cfis->pm_port_c = 1 << 7; | ||
514 | + cfis->command = ATA_CMD_SET_FEATURES; | ||
515 | + cfis->features = SETFEATURES_XFER; | ||
516 | + cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e; | ||
517 | + | ||
518 | + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD); | ||
519 | +} | ||
520 | + | ||
521 | +static int ahci_port_start(struct ahci_probe_ent *probe_ent, | ||
522 | + u8 port) | ||
523 | +{ | ||
524 | + struct ahci_ioports *pp = &(probe_ent->port[port]); | ||
525 | + struct sata_port_regs *port_mmio = | ||
526 | + (struct sata_port_regs *)pp->port_mmio; | ||
527 | + u32 port_status; | ||
528 | + u32 mem; | ||
529 | + int timeout = 10000000; | ||
530 | + | ||
531 | + debug("Enter start port: %d\n", port); | ||
532 | + port_status = readl(&(port_mmio->ssts)); | ||
533 | + debug("Port %d status: %x\n", port, port_status); | ||
534 | + if ((port_status & 0xf) != 0x03) { | ||
535 | + printf("No Link on this port!\n"); | ||
536 | + return -1; | ||
537 | + } | ||
538 | + | ||
539 | + mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); | ||
540 | + if (!mem) { | ||
541 | + free(pp); | ||
542 | + printf("No mem for table!\n"); | ||
543 | + return -ENOMEM; | ||
544 | + } | ||
545 | + | ||
546 | + mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ | ||
547 | + memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); | ||
548 | + | ||
549 | + /* | ||
550 | + * First item in chunk of DMA memory: 32-slot command table, | ||
551 | + * 32 bytes each in size | ||
552 | + */ | ||
553 | + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; | ||
554 | + debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); | ||
555 | + mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); | ||
556 | + | ||
557 | + /* | ||
558 | + * Second item: Received-FIS area, 256-Byte aligned | ||
559 | + */ | ||
560 | + pp->rx_fis = mem; | ||
561 | + mem += AHCI_RX_FIS_SZ; | ||
562 | + | ||
563 | + /* | ||
564 | + * Third item: data area for storing a single command | ||
565 | + * and its scatter-gather table | ||
566 | + */ | ||
567 | + pp->cmd_tbl = mem; | ||
568 | + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); | ||
569 | + | ||
570 | + mem += AHCI_CMD_TBL_HDR; | ||
571 | + | ||
572 | + writel_with_flush(0x00004444, &(port_mmio->dmacr)); | ||
573 | + pp->cmd_tbl_sg = (struct ahci_sg *)mem; | ||
574 | + writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb)); | ||
575 | + writel_with_flush(pp->rx_fis, &(port_mmio->fb)); | ||
576 | + | ||
577 | + /* Enable FRE */ | ||
578 | + writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))), | ||
579 | + &(port_mmio->cmd)); | ||
580 | + | ||
581 | + /* Wait device ready */ | ||
582 | + while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR | | ||
583 | + SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) | ||
584 | + && --timeout) | ||
585 | + ; | ||
586 | + if (timeout <= 0) { | ||
587 | + debug("Device not ready for BSY, DRQ and" | ||
588 | + "ERR in TFD!\n"); | ||
589 | + return -1; | ||
590 | + } | ||
591 | + | ||
592 | + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | ||
593 | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | | ||
594 | + PORT_CMD_START, &(port_mmio->cmd)); | ||
595 | + | ||
596 | + debug("Exit start port %d\n", port); | ||
597 | + | ||
598 | + return 0; | ||
599 | +} | ||
600 | + | ||
601 | +int init_sata(int dev) | ||
602 | +{ | ||
603 | + int i; | ||
604 | + u32 linkmap; | ||
605 | + struct ahci_probe_ent *probe_ent = NULL; | ||
606 | + | ||
607 | + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { | ||
608 | + printf("The sata index %d is out of ranges\n\r", dev); | ||
609 | + return -1; | ||
610 | + } | ||
611 | + | ||
612 | + ahci_init_one(dev); | ||
613 | + | ||
614 | + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
615 | + linkmap = probe_ent->link_port_map; | ||
616 | + | ||
617 | + if (0 == linkmap) { | ||
618 | + printf("No port device detected!\n"); | ||
619 | + return 1; | ||
620 | + } | ||
621 | + | ||
622 | + for (i = 0; i < probe_ent->n_ports; i++) { | ||
623 | + if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { | ||
624 | + if (ahci_port_start(probe_ent, (u8)i)) { | ||
625 | + printf("Can not start port %d\n", i); | ||
626 | + return 1; | ||
627 | + } | ||
628 | + probe_ent->hard_port_no = i; | ||
629 | + break; | ||
630 | + } | ||
631 | + } | ||
632 | + | ||
633 | + return 0; | ||
634 | +} | ||
635 | + | ||
636 | +static void dwc_ahsata_print_info(int dev) | ||
637 | +{ | ||
638 | + block_dev_desc_t *pdev = &(sata_dev_desc[dev]); | ||
639 | + | ||
640 | + printf("SATA Device Info:\n\r"); | ||
641 | +#ifdef CONFIG_SYS_64BIT_LBA | ||
642 | + printf("S/N: %s\n\rProduct model number: %s\n\r" | ||
643 | + "Firmware version: %s\n\rCapacity: %lld sectors\n\r", | ||
644 | + pdev->product, pdev->vendor, pdev->revision, pdev->lba); | ||
645 | +#else | ||
646 | + printf("S/N: %s\n\rProduct model number: %s\n\r" | ||
647 | + "Firmware version: %s\n\rCapacity: %ld sectors\n\r", | ||
648 | + pdev->product, pdev->vendor, pdev->revision, pdev->lba); | ||
649 | +#endif | ||
650 | +} | ||
651 | + | ||
652 | +static void dwc_ahsata_identify(int dev, u16 *id) | ||
653 | +{ | ||
654 | + struct ahci_probe_ent *probe_ent = | ||
655 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
656 | + struct sata_fis_h2d h2d, *cfis = &h2d; | ||
657 | + u8 port = probe_ent->hard_port_no; | ||
658 | + | ||
659 | + memset(cfis, 0, sizeof(struct sata_fis_h2d)); | ||
660 | + | ||
661 | + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | ||
662 | + cfis->pm_port_c = 0x80; /* is command */ | ||
663 | + cfis->command = ATA_CMD_ID_ATA; | ||
664 | + | ||
665 | + ahci_exec_ata_cmd(probe_ent, port, cfis, | ||
666 | + (u8 *)id, ATA_ID_WORDS * 2, READ_CMD); | ||
667 | + ata_swap_buf_le16(id, ATA_ID_WORDS); | ||
668 | +} | ||
669 | + | ||
670 | +static void dwc_ahsata_xfer_mode(int dev, u16 *id) | ||
671 | +{ | ||
672 | + struct ahci_probe_ent *probe_ent = | ||
673 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
674 | + | ||
675 | + probe_ent->pio_mask = id[ATA_ID_PIO_MODES]; | ||
676 | + probe_ent->udma_mask = id[ATA_ID_UDMA_MODES]; | ||
677 | + debug("pio %04x, udma %04x\n\r", | ||
678 | + probe_ent->pio_mask, probe_ent->udma_mask); | ||
679 | +} | ||
680 | + | ||
681 | +static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt, | ||
682 | + u8 *buffer, int is_write) | ||
683 | +{ | ||
684 | + struct ahci_probe_ent *probe_ent = | ||
685 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
686 | + struct sata_fis_h2d h2d, *cfis = &h2d; | ||
687 | + u8 port = probe_ent->hard_port_no; | ||
688 | + u32 block; | ||
689 | + | ||
690 | + block = start; | ||
691 | + | ||
692 | + memset(cfis, 0, sizeof(struct sata_fis_h2d)); | ||
693 | + | ||
694 | + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | ||
695 | + cfis->pm_port_c = 0x80; /* is command */ | ||
696 | + cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; | ||
697 | + cfis->device = ATA_LBA; | ||
698 | + | ||
699 | + cfis->device |= (block >> 24) & 0xf; | ||
700 | + cfis->lba_high = (block >> 16) & 0xff; | ||
701 | + cfis->lba_mid = (block >> 8) & 0xff; | ||
702 | + cfis->lba_low = block & 0xff; | ||
703 | + cfis->sector_count = (u8)(blkcnt & 0xff); | ||
704 | + | ||
705 | + if (ahci_exec_ata_cmd(probe_ent, port, cfis, | ||
706 | + buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0) | ||
707 | + return blkcnt; | ||
708 | + else | ||
709 | + return 0; | ||
710 | +} | ||
711 | + | ||
712 | +void dwc_ahsata_flush_cache(int dev) | ||
713 | +{ | ||
714 | + struct ahci_probe_ent *probe_ent = | ||
715 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
716 | + struct sata_fis_h2d h2d, *cfis = &h2d; | ||
717 | + u8 port = probe_ent->hard_port_no; | ||
718 | + | ||
719 | + memset(cfis, 0, sizeof(struct sata_fis_h2d)); | ||
720 | + | ||
721 | + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | ||
722 | + cfis->pm_port_c = 0x80; /* is command */ | ||
723 | + cfis->command = ATA_CMD_FLUSH; | ||
724 | + | ||
725 | + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0); | ||
726 | +} | ||
727 | + | ||
728 | +static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt, | ||
729 | + u8 *buffer, int is_write) | ||
730 | +{ | ||
731 | + struct ahci_probe_ent *probe_ent = | ||
732 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
733 | + struct sata_fis_h2d h2d, *cfis = &h2d; | ||
734 | + u8 port = probe_ent->hard_port_no; | ||
735 | + u64 block; | ||
736 | + | ||
737 | + block = (u64)start; | ||
738 | + | ||
739 | + memset(cfis, 0, sizeof(struct sata_fis_h2d)); | ||
740 | + | ||
741 | + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | ||
742 | + cfis->pm_port_c = 0x80; /* is command */ | ||
743 | + | ||
744 | + cfis->command = (is_write) ? ATA_CMD_WRITE_EXT | ||
745 | + : ATA_CMD_READ_EXT; | ||
746 | + | ||
747 | + cfis->lba_high_exp = (block >> 40) & 0xff; | ||
748 | + cfis->lba_mid_exp = (block >> 32) & 0xff; | ||
749 | + cfis->lba_low_exp = (block >> 24) & 0xff; | ||
750 | + cfis->lba_high = (block >> 16) & 0xff; | ||
751 | + cfis->lba_mid = (block >> 8) & 0xff; | ||
752 | + cfis->lba_low = block & 0xff; | ||
753 | + cfis->device = ATA_LBA; | ||
754 | + cfis->sector_count_exp = (blkcnt >> 8) & 0xff; | ||
755 | + cfis->sector_count = blkcnt & 0xff; | ||
756 | + | ||
757 | + if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer, | ||
758 | + ATA_SECT_SIZE * blkcnt, is_write) > 0) | ||
759 | + return blkcnt; | ||
760 | + else | ||
761 | + return 0; | ||
762 | +} | ||
763 | + | ||
764 | +u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt, | ||
765 | + u8 *buffer, int is_write) | ||
766 | +{ | ||
767 | + struct ahci_probe_ent *probe_ent = | ||
768 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
769 | + struct sata_fis_h2d h2d, *cfis = &h2d; | ||
770 | + u8 port = probe_ent->hard_port_no; | ||
771 | + u64 block; | ||
772 | + | ||
773 | + if (sata_dev_desc[dev].lba48 != 1) { | ||
774 | + printf("execute FPDMA command on non-LBA48 hard disk\n\r"); | ||
775 | + return -1; | ||
776 | + } | ||
777 | + | ||
778 | + block = (u64)start; | ||
779 | + | ||
780 | + memset(cfis, 0, sizeof(struct sata_fis_h2d)); | ||
781 | + | ||
782 | + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | ||
783 | + cfis->pm_port_c = 0x80; /* is command */ | ||
784 | + | ||
785 | + cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE | ||
786 | + : ATA_CMD_FPDMA_READ; | ||
787 | + | ||
788 | + cfis->lba_high_exp = (block >> 40) & 0xff; | ||
789 | + cfis->lba_mid_exp = (block >> 32) & 0xff; | ||
790 | + cfis->lba_low_exp = (block >> 24) & 0xff; | ||
791 | + cfis->lba_high = (block >> 16) & 0xff; | ||
792 | + cfis->lba_mid = (block >> 8) & 0xff; | ||
793 | + cfis->lba_low = block & 0xff; | ||
794 | + | ||
795 | + cfis->device = ATA_LBA; | ||
796 | + cfis->features_exp = (blkcnt >> 8) & 0xff; | ||
797 | + cfis->features = blkcnt & 0xff; | ||
798 | + | ||
799 | + /* Use the latest queue */ | ||
800 | + ahci_exec_ata_cmd(probe_ent, port, cfis, | ||
801 | + buffer, ATA_SECT_SIZE * blkcnt, is_write); | ||
802 | + | ||
803 | + return blkcnt; | ||
804 | +} | ||
805 | + | ||
806 | +void dwc_ahsata_flush_cache_ext(int dev) | ||
807 | +{ | ||
808 | + struct ahci_probe_ent *probe_ent = | ||
809 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
810 | + struct sata_fis_h2d h2d, *cfis = &h2d; | ||
811 | + u8 port = probe_ent->hard_port_no; | ||
812 | + | ||
813 | + memset(cfis, 0, sizeof(struct sata_fis_h2d)); | ||
814 | + | ||
815 | + cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | ||
816 | + cfis->pm_port_c = 0x80; /* is command */ | ||
817 | + cfis->command = ATA_CMD_FLUSH_EXT; | ||
818 | + | ||
819 | + ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0); | ||
820 | +} | ||
821 | + | ||
822 | +static void dwc_ahsata_init_wcache(int dev, u16 *id) | ||
823 | +{ | ||
824 | + struct ahci_probe_ent *probe_ent = | ||
825 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
826 | + | ||
827 | + if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) | ||
828 | + probe_ent->flags |= SATA_FLAG_WCACHE; | ||
829 | + if (ata_id_has_flush(id)) | ||
830 | + probe_ent->flags |= SATA_FLAG_FLUSH; | ||
831 | + if (ata_id_has_flush_ext(id)) | ||
832 | + probe_ent->flags |= SATA_FLAG_FLUSH_EXT; | ||
833 | +} | ||
834 | + | ||
835 | +u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt, | ||
836 | + void *buffer, int is_write) | ||
837 | +{ | ||
838 | + u32 start, blks; | ||
839 | + u8 *addr; | ||
840 | + int max_blks; | ||
841 | + | ||
842 | + start = blknr; | ||
843 | + blks = blkcnt; | ||
844 | + addr = (u8 *)buffer; | ||
845 | + | ||
846 | + max_blks = ATA_MAX_SECTORS_LBA48; | ||
847 | + | ||
848 | + do { | ||
849 | + if (blks > max_blks) { | ||
850 | + if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start, | ||
851 | + max_blks, addr, is_write)) | ||
852 | + return 0; | ||
853 | + start += max_blks; | ||
854 | + blks -= max_blks; | ||
855 | + addr += ATA_SECT_SIZE * max_blks; | ||
856 | + } else { | ||
857 | + if (blks != dwc_ahsata_rw_cmd_ext(dev, start, | ||
858 | + blks, addr, is_write)) | ||
859 | + return 0; | ||
860 | + start += blks; | ||
861 | + blks = 0; | ||
862 | + addr += ATA_SECT_SIZE * blks; | ||
863 | + } | ||
864 | + } while (blks != 0); | ||
865 | + | ||
866 | + return blkcnt; | ||
867 | +} | ||
868 | + | ||
869 | +u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, | ||
870 | + void *buffer, int is_write) | ||
871 | +{ | ||
872 | + u32 start, blks; | ||
873 | + u8 *addr; | ||
874 | + int max_blks; | ||
875 | + | ||
876 | + start = blknr; | ||
877 | + blks = blkcnt; | ||
878 | + addr = (u8 *)buffer; | ||
879 | + | ||
880 | + max_blks = ATA_MAX_SECTORS; | ||
881 | + do { | ||
882 | + if (blks > max_blks) { | ||
883 | + if (max_blks != dwc_ahsata_rw_cmd(dev, start, | ||
884 | + max_blks, addr, is_write)) | ||
885 | + return 0; | ||
886 | + start += max_blks; | ||
887 | + blks -= max_blks; | ||
888 | + addr += ATA_SECT_SIZE * max_blks; | ||
889 | + } else { | ||
890 | + if (blks != dwc_ahsata_rw_cmd(dev, start, | ||
891 | + blks, addr, is_write)) | ||
892 | + return 0; | ||
893 | + start += blks; | ||
894 | + blks = 0; | ||
895 | + addr += ATA_SECT_SIZE * blks; | ||
896 | + } | ||
897 | + } while (blks != 0); | ||
898 | + | ||
899 | + return blkcnt; | ||
900 | +} | ||
901 | + | ||
902 | +/* | ||
903 | + * SATA interface between low level driver and command layer | ||
904 | + */ | ||
905 | +ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer) | ||
906 | +{ | ||
907 | + u32 rc; | ||
908 | + | ||
909 | + if (sata_dev_desc[dev].lba48) | ||
910 | + rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, | ||
911 | + buffer, READ_CMD); | ||
912 | + else | ||
913 | + rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, | ||
914 | + buffer, READ_CMD); | ||
915 | + return rc; | ||
916 | +} | ||
917 | + | ||
918 | +ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer) | ||
919 | +{ | ||
920 | + u32 rc; | ||
921 | + struct ahci_probe_ent *probe_ent = | ||
922 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
923 | + u32 flags = probe_ent->flags; | ||
924 | + | ||
925 | + if (sata_dev_desc[dev].lba48) { | ||
926 | + rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, | ||
927 | + buffer, WRITE_CMD); | ||
928 | + if ((flags & SATA_FLAG_WCACHE) && | ||
929 | + (flags & SATA_FLAG_FLUSH_EXT)) | ||
930 | + dwc_ahsata_flush_cache_ext(dev); | ||
931 | + } else { | ||
932 | + rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, | ||
933 | + buffer, WRITE_CMD); | ||
934 | + if ((flags & SATA_FLAG_WCACHE) && | ||
935 | + (flags & SATA_FLAG_FLUSH)) | ||
936 | + dwc_ahsata_flush_cache(dev); | ||
937 | + } | ||
938 | + return rc; | ||
939 | +} | ||
940 | + | ||
941 | +int scan_sata(int dev) | ||
942 | +{ | ||
943 | + u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; | ||
944 | + u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; | ||
945 | + u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; | ||
946 | + u16 *id; | ||
947 | + u64 n_sectors; | ||
948 | + struct ahci_probe_ent *probe_ent = | ||
949 | + (struct ahci_probe_ent *)sata_dev_desc[dev].priv; | ||
950 | + u8 port = probe_ent->hard_port_no; | ||
951 | + block_dev_desc_t *pdev = &(sata_dev_desc[dev]); | ||
952 | + | ||
953 | + id = (u16 *)malloc(ATA_ID_WORDS * 2); | ||
954 | + if (!id) { | ||
955 | + printf("id malloc failed\n\r"); | ||
956 | + return -1; | ||
957 | + } | ||
958 | + | ||
959 | + /* Identify device to get information */ | ||
960 | + dwc_ahsata_identify(dev, id); | ||
961 | + | ||
962 | + /* Serial number */ | ||
963 | + ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); | ||
964 | + memcpy(pdev->product, serial, sizeof(serial)); | ||
965 | + | ||
966 | + /* Firmware version */ | ||
967 | + ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); | ||
968 | + memcpy(pdev->revision, firmware, sizeof(firmware)); | ||
969 | + | ||
970 | + /* Product model */ | ||
971 | + ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); | ||
972 | + memcpy(pdev->vendor, product, sizeof(product)); | ||
973 | + | ||
974 | + /* Totoal sectors */ | ||
975 | + n_sectors = ata_id_n_sectors(id); | ||
976 | + pdev->lba = (u32)n_sectors; | ||
977 | + | ||
978 | + pdev->type = DEV_TYPE_HARDDISK; | ||
979 | + pdev->blksz = ATA_SECT_SIZE; | ||
980 | + pdev->lun = 0 ; | ||
981 | + | ||
982 | + /* Check if support LBA48 */ | ||
983 | + if (ata_id_has_lba48(id)) { | ||
984 | + pdev->lba48 = 1; | ||
985 | + debug("Device support LBA48\n\r"); | ||
986 | + } | ||
987 | + | ||
988 | + /* Get the NCQ queue depth from device */ | ||
989 | + probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK); | ||
990 | + probe_ent->flags |= ata_id_queue_depth(id); | ||
991 | + | ||
992 | + /* Get the xfer mode from device */ | ||
993 | + dwc_ahsata_xfer_mode(dev, id); | ||
994 | + | ||
995 | + /* Get the write cache status from device */ | ||
996 | + dwc_ahsata_init_wcache(dev, id); | ||
997 | + | ||
998 | + /* Set the xfer mode to highest speed */ | ||
999 | + ahci_set_feature(dev, port); | ||
1000 | + | ||
1001 | + free((void *)id); | ||
1002 | + | ||
1003 | + dwc_ahsata_print_info(dev); | ||
1004 | + | ||
1005 | + is_ready = 1; | ||
1006 | + | ||
1007 | + return 0; | ||
1008 | +} | ||
1009 | diff --git a/drivers/block/dwc_ahsata.h b/drivers/block/dwc_ahsata.h | ||
1010 | new file mode 100644 | ||
1011 | index 0000000..84860ea | ||
1012 | --- /dev/null | ||
1013 | +++ b/drivers/block/dwc_ahsata.h | ||
1014 | @@ -0,0 +1,335 @@ | ||
1015 | +/* | ||
1016 | + * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
1017 | + * Terry Lv <r65388@freescale.com> | ||
1018 | + * | ||
1019 | + * This program is free software; you can redistribute it and/or | ||
1020 | + * modify it under the terms of the GNU General Public License as | ||
1021 | + * published by the Free Software Foundation; either version 2 of | ||
1022 | + * the License, or (at your option) any later version. | ||
1023 | + * | ||
1024 | + * This program is distributed in the hope that it will be useful, | ||
1025 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
1026 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
1027 | + * GNU General Public License for more details. | ||
1028 | + * | ||
1029 | + * You should have received a copy of the GNU General Public License | ||
1030 | + * along with this program; if not, write to the Free Software | ||
1031 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
1032 | + * MA 02111-1307 USA | ||
1033 | + */ | ||
1034 | + | ||
1035 | +#ifndef __FSL_SATA_H__ | ||
1036 | +#define __FSL_SATA_H__ | ||
1037 | + | ||
1038 | +#define DWC_AHSATA_MAX_CMD_SLOTS 32 | ||
1039 | + | ||
1040 | +/* Max host controller numbers */ | ||
1041 | +#define SATA_HC_MAX_NUM 4 | ||
1042 | +/* Max command queue depth per host controller */ | ||
1043 | +#define DWC_AHSATA_HC_MAX_CMD 32 | ||
1044 | +/* Max port number per host controller */ | ||
1045 | +#define SATA_HC_MAX_PORT 16 | ||
1046 | + | ||
1047 | +/* Generic Host Register */ | ||
1048 | + | ||
1049 | +/* HBA Capabilities Register */ | ||
1050 | +#define SATA_HOST_CAP_S64A 0x80000000 | ||
1051 | +#define SATA_HOST_CAP_SNCQ 0x40000000 | ||
1052 | +#define SATA_HOST_CAP_SSNTF 0x20000000 | ||
1053 | +#define SATA_HOST_CAP_SMPS 0x10000000 | ||
1054 | +#define SATA_HOST_CAP_SSS 0x08000000 | ||
1055 | +#define SATA_HOST_CAP_SALP 0x04000000 | ||
1056 | +#define SATA_HOST_CAP_SAL 0x02000000 | ||
1057 | +#define SATA_HOST_CAP_SCLO 0x01000000 | ||
1058 | +#define SATA_HOST_CAP_ISS_MASK 0x00f00000 | ||
1059 | +#define SATA_HOST_CAP_ISS_OFFSET 20 | ||
1060 | +#define SATA_HOST_CAP_SNZO 0x00080000 | ||
1061 | +#define SATA_HOST_CAP_SAM 0x00040000 | ||
1062 | +#define SATA_HOST_CAP_SPM 0x00020000 | ||
1063 | +#define SATA_HOST_CAP_PMD 0x00008000 | ||
1064 | +#define SATA_HOST_CAP_SSC 0x00004000 | ||
1065 | +#define SATA_HOST_CAP_PSC 0x00002000 | ||
1066 | +#define SATA_HOST_CAP_NCS 0x00001f00 | ||
1067 | +#define SATA_HOST_CAP_CCCS 0x00000080 | ||
1068 | +#define SATA_HOST_CAP_EMS 0x00000040 | ||
1069 | +#define SATA_HOST_CAP_SXS 0x00000020 | ||
1070 | +#define SATA_HOST_CAP_NP_MASK 0x0000001f | ||
1071 | + | ||
1072 | +/* Global HBA Control Register */ | ||
1073 | +#define SATA_HOST_GHC_AE 0x80000000 | ||
1074 | +#define SATA_HOST_GHC_IE 0x00000002 | ||
1075 | +#define SATA_HOST_GHC_HR 0x00000001 | ||
1076 | + | ||
1077 | +/* Interrupt Status Register */ | ||
1078 | + | ||
1079 | +/* Ports Implemented Register */ | ||
1080 | + | ||
1081 | +/* AHCI Version Register */ | ||
1082 | +#define SATA_HOST_VS_MJR_MASK 0xffff0000 | ||
1083 | +#define SATA_HOST_VS_MJR_OFFSET 16 | ||
1084 | +#define SATA_HOST_VS_MJR_MNR 0x0000ffff | ||
1085 | + | ||
1086 | +/* Command Completion Coalescing Control */ | ||
1087 | +#define SATA_HOST_CCC_CTL_TV_MASK 0xffff0000 | ||
1088 | +#define SATA_HOST_CCC_CTL_TV_OFFSET 16 | ||
1089 | +#define SATA_HOST_CCC_CTL_CC_MASK 0x0000ff00 | ||
1090 | +#define SATA_HOST_CCC_CTL_CC_OFFSET 8 | ||
1091 | +#define SATA_HOST_CCC_CTL_INT_MASK 0x000000f8 | ||
1092 | +#define SATA_HOST_CCC_CTL_INT_OFFSET 3 | ||
1093 | +#define SATA_HOST_CCC_CTL_EN 0x00000001 | ||
1094 | + | ||
1095 | +/* Command Completion Coalescing Ports */ | ||
1096 | + | ||
1097 | +/* HBA Capabilities Extended Register */ | ||
1098 | +#define SATA_HOST_CAP2_APST 0x00000004 | ||
1099 | + | ||
1100 | +/* BIST Activate FIS Register */ | ||
1101 | +#define SATA_HOST_BISTAFR_NCP_MASK 0x0000ff00 | ||
1102 | +#define SATA_HOST_BISTAFR_NCP_OFFSET 8 | ||
1103 | +#define SATA_HOST_BISTAFR_PD_MASK 0x000000ff | ||
1104 | +#define SATA_HOST_BISTAFR_PD_OFFSET 0 | ||
1105 | + | ||
1106 | +/* BIST Control Register */ | ||
1107 | +#define SATA_HOST_BISTCR_FERLB 0x00100000 | ||
1108 | +#define SATA_HOST_BISTCR_TXO 0x00040000 | ||
1109 | +#define SATA_HOST_BISTCR_CNTCLR 0x00020000 | ||
1110 | +#define SATA_HOST_BISTCR_NEALB 0x00010000 | ||
1111 | +#define SATA_HOST_BISTCR_LLC_MASK 0x00000700 | ||
1112 | +#define SATA_HOST_BISTCR_LLC_OFFSET 8 | ||
1113 | +#define SATA_HOST_BISTCR_ERREN 0x00000040 | ||
1114 | +#define SATA_HOST_BISTCR_FLIP 0x00000020 | ||
1115 | +#define SATA_HOST_BISTCR_PV 0x00000010 | ||
1116 | +#define SATA_HOST_BISTCR_PATTERN_MASK 0x0000000f | ||
1117 | +#define SATA_HOST_BISTCR_PATTERN_OFFSET 0 | ||
1118 | + | ||
1119 | +/* BIST FIS Count Register */ | ||
1120 | + | ||
1121 | +/* BIST Status Register */ | ||
1122 | +#define SATA_HOST_BISTSR_FRAMERR_MASK 0x0000ffff | ||
1123 | +#define SATA_HOST_BISTSR_FRAMERR_OFFSET 0 | ||
1124 | +#define SATA_HOST_BISTSR_BRSTERR_MASK 0x00ff0000 | ||
1125 | +#define SATA_HOST_BISTSR_BRSTERR_OFFSET 16 | ||
1126 | + | ||
1127 | +/* BIST DWORD Error Count Register */ | ||
1128 | + | ||
1129 | +/* OOB Register*/ | ||
1130 | +#define SATA_HOST_OOBR_WE 0x80000000 | ||
1131 | +#define SATA_HOST_OOBR_cwMin_MASK 0x7f000000 | ||
1132 | +#define SATA_HOST_OOBR_cwMAX_MASK 0x00ff0000 | ||
1133 | +#define SATA_HOST_OOBR_ciMin_MASK 0x0000ff00 | ||
1134 | +#define SATA_HOST_OOBR_ciMax_MASK 0x000000ff | ||
1135 | + | ||
1136 | +/* Timer 1-ms Register */ | ||
1137 | + | ||
1138 | +/* Global Parameter 1 Register */ | ||
1139 | +#define SATA_HOST_GPARAM1R_ALIGN_M 0x80000000 | ||
1140 | +#define SATA_HOST_GPARAM1R_RX_BUFFER 0x40000000 | ||
1141 | +#define SATA_HOST_GPARAM1R_PHY_DATA_MASK 0x30000000 | ||
1142 | +#define SATA_HOST_GPARAM1R_PHY_RST 0x08000000 | ||
1143 | +#define SATA_HOST_GPARAM1R_PHY_CTRL_MASK 0x07e00000 | ||
1144 | +#define SATA_HOST_GPARAM1R_PHY_STAT_MASK 0x001f8000 | ||
1145 | +#define SATA_HOST_GPARAM1R_LATCH_M 0x00004000 | ||
1146 | +#define SATA_HOST_GPARAM1R_BIST_M 0x00002000 | ||
1147 | +#define SATA_HOST_GPARAM1R_PHY_TYPE 0x00001000 | ||
1148 | +#define SATA_HOST_GPARAM1R_RETURN_ERR 0x00000400 | ||
1149 | +#define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK 0x00000300 | ||
1150 | +#define SATA_HOST_GPARAM1R_S_HADDR 0X00000080 | ||
1151 | +#define SATA_HOST_GPARAM1R_M_HADDR 0X00000040 | ||
1152 | + | ||
1153 | +/* Global Parameter 2 Register */ | ||
1154 | +#define SATA_HOST_GPARAM2R_DEV_CP 0x00004000 | ||
1155 | +#define SATA_HOST_GPARAM2R_DEV_MP 0x00002000 | ||
1156 | +#define SATA_HOST_GPARAM2R_DEV_ENCODE_M 0x00001000 | ||
1157 | +#define SATA_HOST_GPARAM2R_RXOOB_CLK_M 0x00000800 | ||
1158 | +#define SATA_HOST_GPARAM2R_RXOOB_M 0x00000400 | ||
1159 | +#define SATA_HOST_GPARAM2R_TX_OOB_M 0x00000200 | ||
1160 | +#define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK 0x000001ff | ||
1161 | + | ||
1162 | +/* Port Parameter Register */ | ||
1163 | +#define SATA_HOST_PPARAMR_TX_MEM_M 0x00000200 | ||
1164 | +#define SATA_HOST_PPARAMR_TX_MEM_S 0x00000100 | ||
1165 | +#define SATA_HOST_PPARAMR_RX_MEM_M 0x00000080 | ||
1166 | +#define SATA_HOST_PPARAMR_RX_MEM_S 0x00000040 | ||
1167 | +#define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK 0x00000038 | ||
1168 | +#define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK 0x00000007 | ||
1169 | + | ||
1170 | +/* Test Register */ | ||
1171 | +#define SATA_HOST_TESTR_PSEL_MASK 0x00070000 | ||
1172 | +#define SATA_HOST_TESTR_TEST_IF 0x00000001 | ||
1173 | + | ||
1174 | +/* Port Register Descriptions */ | ||
1175 | +/* Port# Command List Base Address Register */ | ||
1176 | +#define SATA_PORT_CLB_CLB_MASK 0xfffffc00 | ||
1177 | + | ||
1178 | +/* Port# Command List Base Address Upper 32-Bits Register */ | ||
1179 | + | ||
1180 | +/* Port# FIS Base Address Register */ | ||
1181 | +#define SATA_PORT_FB_FB_MASK 0xfffffff0 | ||
1182 | + | ||
1183 | +/* Port# FIS Base Address Upper 32-Bits Register */ | ||
1184 | + | ||
1185 | +/* Port# Interrupt Status Register */ | ||
1186 | +#define SATA_PORT_IS_CPDS 0x80000000 | ||
1187 | +#define SATA_PORT_IS_TFES 0x40000000 | ||
1188 | +#define SATA_PORT_IS_HBFS 0x20000000 | ||
1189 | +#define SATA_PORT_IS_HBDS 0x10000000 | ||
1190 | +#define SATA_PORT_IS_IFS 0x08000000 | ||
1191 | +#define SATA_PORT_IS_INFS 0x04000000 | ||
1192 | +#define SATA_PORT_IS_OFS 0x01000000 | ||
1193 | +#define SATA_PORT_IS_IPMS 0x00800000 | ||
1194 | +#define SATA_PORT_IS_PRCS 0x00400000 | ||
1195 | +#define SATA_PORT_IS_DMPS 0x00000080 | ||
1196 | +#define SATA_PORT_IS_PCS 0x00000040 | ||
1197 | +#define SATA_PORT_IS_DPS 0x00000020 | ||
1198 | +#define SATA_PORT_IS_UFS 0x00000010 | ||
1199 | +#define SATA_PORT_IS_SDBS 0x00000008 | ||
1200 | +#define SATA_PORT_IS_DSS 0x00000004 | ||
1201 | +#define SATA_PORT_IS_PSS 0x00000002 | ||
1202 | +#define SATA_PORT_IS_DHRS 0x00000001 | ||
1203 | + | ||
1204 | +/* Port# Interrupt Enable Register */ | ||
1205 | +#define SATA_PORT_IE_CPDE 0x80000000 | ||
1206 | +#define SATA_PORT_IE_TFEE 0x40000000 | ||
1207 | +#define SATA_PORT_IE_HBFE 0x20000000 | ||
1208 | +#define SATA_PORT_IE_HBDE 0x10000000 | ||
1209 | +#define SATA_PORT_IE_IFE 0x08000000 | ||
1210 | +#define SATA_PORT_IE_INFE 0x04000000 | ||
1211 | +#define SATA_PORT_IE_OFE 0x01000000 | ||
1212 | +#define SATA_PORT_IE_IPME 0x00800000 | ||
1213 | +#define SATA_PORT_IE_PRCE 0x00400000 | ||
1214 | +#define SATA_PORT_IE_DMPE 0x00000080 | ||
1215 | +#define SATA_PORT_IE_PCE 0x00000040 | ||
1216 | +#define SATA_PORT_IE_DPE 0x00000020 | ||
1217 | +#define SATA_PORT_IE_UFE 0x00000010 | ||
1218 | +#define SATA_PORT_IE_SDBE 0x00000008 | ||
1219 | +#define SATA_PORT_IE_DSE 0x00000004 | ||
1220 | +#define SATA_PORT_IE_PSE 0x00000002 | ||
1221 | +#define SATA_PORT_IE_DHRE 0x00000001 | ||
1222 | + | ||
1223 | +/* Port# Command Register */ | ||
1224 | +#define SATA_PORT_CMD_ICC_MASK 0xf0000000 | ||
1225 | +#define SATA_PORT_CMD_ASP 0x08000000 | ||
1226 | +#define SATA_PORT_CMD_ALPE 0x04000000 | ||
1227 | +#define SATA_PORT_CMD_DLAE 0x02000000 | ||
1228 | +#define SATA_PORT_CMD_ATAPI 0x01000000 | ||
1229 | +#define SATA_PORT_CMD_APSTE 0x00800000 | ||
1230 | +#define SATA_PORT_CMD_ESP 0x00200000 | ||
1231 | +#define SATA_PORT_CMD_CPD 0x00100000 | ||
1232 | +#define SATA_PORT_CMD_MPSP 0x00080000 | ||
1233 | +#define SATA_PORT_CMD_HPCP 0x00040000 | ||
1234 | +#define SATA_PORT_CMD_PMA 0x00020000 | ||
1235 | +#define SATA_PORT_CMD_CPS 0x00010000 | ||
1236 | +#define SATA_PORT_CMD_CR 0x00008000 | ||
1237 | +#define SATA_PORT_CMD_FR 0x00004000 | ||
1238 | +#define SATA_PORT_CMD_MPSS 0x00002000 | ||
1239 | +#define SATA_PORT_CMD_CCS_MASK 0x00001f00 | ||
1240 | +#define SATA_PORT_CMD_FRE 0x00000010 | ||
1241 | +#define SATA_PORT_CMD_CLO 0x00000008 | ||
1242 | +#define SATA_PORT_CMD_POD 0x00000004 | ||
1243 | +#define SATA_PORT_CMD_SUD 0x00000002 | ||
1244 | +#define SATA_PORT_CMD_ST 0x00000001 | ||
1245 | + | ||
1246 | +/* Port# Task File Data Register */ | ||
1247 | +#define SATA_PORT_TFD_ERR_MASK 0x0000ff00 | ||
1248 | +#define SATA_PORT_TFD_STS_MASK 0x000000ff | ||
1249 | +#define SATA_PORT_TFD_STS_ERR 0x00000001 | ||
1250 | +#define SATA_PORT_TFD_STS_DRQ 0x00000008 | ||
1251 | +#define SATA_PORT_TFD_STS_BSY 0x00000080 | ||
1252 | + | ||
1253 | +/* Port# Signature Register */ | ||
1254 | + | ||
1255 | +/* Port# Serial ATA Status {SStatus} Register */ | ||
1256 | +#define SATA_PORT_SSTS_IPM_MASK 0x00000f00 | ||
1257 | +#define SATA_PORT_SSTS_SPD_MASK 0x000000f0 | ||
1258 | +#define SATA_PORT_SSTS_DET_MASK 0x0000000f | ||
1259 | + | ||
1260 | +/* Port# Serial ATA Control {SControl} Register */ | ||
1261 | +#define SATA_PORT_SCTL_IPM_MASK 0x00000f00 | ||
1262 | +#define SATA_PORT_SCTL_SPD_MASK 0x000000f0 | ||
1263 | +#define SATA_PORT_SCTL_DET_MASK 0x0000000f | ||
1264 | + | ||
1265 | +/* Port# Serial ATA Error {SError} Register */ | ||
1266 | +#define SATA_PORT_SERR_DIAG_X 0x04000000 | ||
1267 | +#define SATA_PORT_SERR_DIAG_F 0x02000000 | ||
1268 | +#define SATA_PORT_SERR_DIAG_T 0x01000000 | ||
1269 | +#define SATA_PORT_SERR_DIAG_S 0x00800000 | ||
1270 | +#define SATA_PORT_SERR_DIAG_H 0x00400000 | ||
1271 | +#define SATA_PORT_SERR_DIAG_C 0x00200000 | ||
1272 | +#define SATA_PORT_SERR_DIAG_D 0x00100000 | ||
1273 | +#define SATA_PORT_SERR_DIAG_B 0x00080000 | ||
1274 | +#define SATA_PORT_SERR_DIAG_W 0x00040000 | ||
1275 | +#define SATA_PORT_SERR_DIAG_I 0x00020000 | ||
1276 | +#define SATA_PORT_SERR_DIAG_N 0x00010000 | ||
1277 | +#define SATA_PORT_SERR_ERR_E 0x00000800 | ||
1278 | +#define SATA_PORT_SERR_ERR_P 0x00000400 | ||
1279 | +#define SATA_PORT_SERR_ERR_C 0x00000200 | ||
1280 | +#define SATA_PORT_SERR_ERR_T 0x00000100 | ||
1281 | +#define SATA_PORT_SERR_ERR_M 0x00000002 | ||
1282 | +#define SATA_PORT_SERR_ERR_I 0x00000001 | ||
1283 | + | ||
1284 | +/* Port# Serial ATA Active {SActive} Register */ | ||
1285 | + | ||
1286 | +/* Port# Command Issue Register */ | ||
1287 | + | ||
1288 | +/* Port# Serial ATA Notification Register */ | ||
1289 | + | ||
1290 | +/* Port# DMA Control Register */ | ||
1291 | +#define SATA_PORT_DMACR_RXABL_MASK 0x0000f000 | ||
1292 | +#define SATA_PORT_DMACR_TXABL_MASK 0x00000f00 | ||
1293 | +#define SATA_PORT_DMACR_RXTS_MASK 0x000000f0 | ||
1294 | +#define SATA_PORT_DMACR_TXTS_MASK 0x0000000f | ||
1295 | + | ||
1296 | +/* Port# PHY Control Register */ | ||
1297 | + | ||
1298 | +/* Port# PHY Status Register */ | ||
1299 | + | ||
1300 | +#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) | ||
1301 | + | ||
1302 | +/* DW0 | ||
1303 | +*/ | ||
1304 | +#define CMD_HDR_DI_CFL_MASK 0x0000001f | ||
1305 | +#define CMD_HDR_DI_CFL_OFFSET 0 | ||
1306 | +#define CMD_HDR_DI_A 0x00000020 | ||
1307 | +#define CMD_HDR_DI_W 0x00000040 | ||
1308 | +#define CMD_HDR_DI_P 0x00000080 | ||
1309 | +#define CMD_HDR_DI_R 0x00000100 | ||
1310 | +#define CMD_HDR_DI_B 0x00000200 | ||
1311 | +#define CMD_HDR_DI_C 0x00000400 | ||
1312 | +#define CMD_HDR_DI_PMP_MASK 0x0000f000 | ||
1313 | +#define CMD_HDR_DI_PMP_OFFSET 12 | ||
1314 | +#define CMD_HDR_DI_PRDTL 0xffff0000 | ||
1315 | +#define CMD_HDR_DI_PRDTL_OFFSET 16 | ||
1316 | + | ||
1317 | +/* prde_fis_len | ||
1318 | +*/ | ||
1319 | +#define CMD_HDR_PRD_ENTRY_SHIFT 16 | ||
1320 | +#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000 | ||
1321 | +#define CMD_HDR_FIS_LEN_SHIFT 2 | ||
1322 | + | ||
1323 | +/* attribute | ||
1324 | +*/ | ||
1325 | +#define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */ | ||
1326 | +#define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */ | ||
1327 | +/* Snoop enable for all descriptor */ | ||
1328 | +#define CMD_HDR_ATTR_SNOOP 0x00000200 | ||
1329 | +#define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */ | ||
1330 | +#define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */ | ||
1331 | +/* BIST - require the host to enter BIST mode */ | ||
1332 | +#define CMD_HDR_ATTR_BIST 0x00000040 | ||
1333 | +#define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */ | ||
1334 | +#define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */ | ||
1335 | + | ||
1336 | +#define FLAGS_DMA 0x00000000 | ||
1337 | +#define FLAGS_FPDMA 0x00000001 | ||
1338 | + | ||
1339 | +#define SATA_FLAG_Q_DEP_MASK 0x0000000f | ||
1340 | +#define SATA_FLAG_WCACHE 0x00000100 | ||
1341 | +#define SATA_FLAG_FLUSH 0x00000200 | ||
1342 | +#define SATA_FLAG_FLUSH_EXT 0x00000400 | ||
1343 | + | ||
1344 | +#define READ_CMD 0 | ||
1345 | +#define WRITE_CMD 1 | ||
1346 | + | ||
1347 | +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; | ||
1348 | + | ||
1349 | +#endif /* __FSL_SATA_H__ */ | ||
1350 | diff --git a/include/ahci.h b/include/ahci.h | ||
1351 | index 465ea7f..c4fb9e7 100644 | ||
1352 | --- a/include/ahci.h | ||
1353 | +++ b/include/ahci.h | ||
1354 | @@ -30,12 +30,13 @@ | ||
1355 | #define AHCI_PCI_BAR 0x24 | ||
1356 | #define AHCI_MAX_SG 56 /* hardware max is 64K */ | ||
1357 | #define AHCI_CMD_SLOT_SZ 32 | ||
1358 | +#define AHCI_MAX_CMD_SLOT 32 | ||
1359 | #define AHCI_RX_FIS_SZ 256 | ||
1360 | #define AHCI_CMD_TBL_HDR 0x80 | ||
1361 | #define AHCI_CMD_TBL_CDB 0x40 | ||
1362 | #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) | ||
1363 | -#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ | ||
1364 | - + AHCI_RX_FIS_SZ | ||
1365 | +#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ | ||
1366 | + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) | ||
1367 | #define AHCI_CMD_ATAPI (1 << 5) | ||
1368 | #define AHCI_CMD_WRITE (1 << 6) | ||
1369 | #define AHCI_CMD_PREFETCH (1 << 7) | ||
1370 | -- | ||
1371 | 1.7.10 | ||
1372 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch deleted file mode 100644 index 25114ca..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0005-MX53-Add-support-to-ESG-ima3-board.patch +++ /dev/null | |||
@@ -1,781 +0,0 @@ | |||
1 | From 4b78125dda9413f121aadc8ddb3a2ae2238de006 Mon Sep 17 00:00:00 2001 | ||
2 | From: Stefano Babic <sbabic@denx.de> | ||
3 | Date: Wed, 22 Feb 2012 00:24:40 +0000 | ||
4 | Subject: [PATCH 05/56] MX53: Add support to ESG ima3 board | ||
5 | |||
6 | The ESG ima3-mx53 board is based on the Freescale | ||
7 | i.MX53 SOC. It boots from NOR (128 MB) and | ||
8 | supports Ethernet (FEC), SATA. | ||
9 | |||
10 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
11 | --- | ||
12 | board/esg/ima3-mx53/Makefile | 41 ++++++ | ||
13 | board/esg/ima3-mx53/ima3-mx53.c | 302 ++++++++++++++++++++++++++++++++++++++ | ||
14 | board/esg/ima3-mx53/imximage.cfg | 108 ++++++++++++++ | ||
15 | boards.cfg | 1 + | ||
16 | include/configs/ima3-mx53.h | 269 +++++++++++++++++++++++++++++++++ | ||
17 | 5 files changed, 721 insertions(+) | ||
18 | create mode 100644 board/esg/ima3-mx53/Makefile | ||
19 | create mode 100644 board/esg/ima3-mx53/ima3-mx53.c | ||
20 | create mode 100644 board/esg/ima3-mx53/imximage.cfg | ||
21 | create mode 100644 include/configs/ima3-mx53.h | ||
22 | |||
23 | diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile | ||
24 | new file mode 100644 | ||
25 | index 0000000..f3b13bc | ||
26 | --- /dev/null | ||
27 | +++ b/board/esg/ima3-mx53/Makefile | ||
28 | @@ -0,0 +1,41 @@ | ||
29 | +# | ||
30 | +# Copyright (C) 2012, Stefano Babic <sbabic@denx.de> | ||
31 | +# | ||
32 | +# Based on ti/evm/Makefile | ||
33 | +# | ||
34 | +# This program is free software; you can redistribute it and/or | ||
35 | +# modify it under the terms of the GNU General Public License as | ||
36 | +# published by the Free Software Foundation; either version 2 of | ||
37 | +# the License, or (at your option) any later version. | ||
38 | +# | ||
39 | +# This program is distributed in the hope that it will be useful, | ||
40 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
41 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
42 | +# GNU General Public License for more details. | ||
43 | +# | ||
44 | +# You should have received a copy of the GNU General Public License | ||
45 | +# along with this program; if not, write to the Free Software | ||
46 | +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
47 | +# MA 02111-1307 USA | ||
48 | +# | ||
49 | + | ||
50 | +include $(TOPDIR)/config.mk | ||
51 | + | ||
52 | +LIB = $(obj)lib$(BOARD).o | ||
53 | + | ||
54 | +COBJS := ima3-mx53.o | ||
55 | + | ||
56 | +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) | ||
57 | +OBJS := $(addprefix $(obj),$(COBJS)) | ||
58 | + | ||
59 | +$(LIB): $(obj).depend $(OBJS) | ||
60 | + $(call cmd_link_o_target, $(OBJS)) | ||
61 | + | ||
62 | +######################################################################### | ||
63 | + | ||
64 | +# defines $(obj).depend target | ||
65 | +include $(SRCTREE)/rules.mk | ||
66 | + | ||
67 | +sinclude $(obj).depend | ||
68 | + | ||
69 | +######################################################################### | ||
70 | diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c | ||
71 | new file mode 100644 | ||
72 | index 0000000..9ecf31d | ||
73 | --- /dev/null | ||
74 | +++ b/board/esg/ima3-mx53/ima3-mx53.c | ||
75 | @@ -0,0 +1,302 @@ | ||
76 | +/* | ||
77 | + * (C) Copyright 2012, Stefano Babic <sbabic@denx.de> | ||
78 | + * | ||
79 | + * (C) Copyright 2010 Freescale Semiconductor, Inc. | ||
80 | + * | ||
81 | + * See file CREDITS for list of people who contributed to this | ||
82 | + * project. | ||
83 | + * | ||
84 | + * This program is free software; you can redistribute it and/or | ||
85 | + * modify it under the terms of the GNU General Public License as | ||
86 | + * published by the Free Software Foundation; either version 2 of | ||
87 | + * the License, or (at your option) any later version. | ||
88 | + * | ||
89 | + * This program is distributed in the hope that it will be useful, | ||
90 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
91 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
92 | + * GNU General Public License for more details. | ||
93 | + * | ||
94 | + * You should have received a copy of the GNU General Public License | ||
95 | + * along with this program; if not, write to the Free Software | ||
96 | + * Foundation, Inc. | ||
97 | + */ | ||
98 | +#include <common.h> | ||
99 | +#include <asm/io.h> | ||
100 | +#include <asm/arch/imx-regs.h> | ||
101 | +#include <asm/arch/mx5x_pins.h> | ||
102 | +#include <asm/arch/sys_proto.h> | ||
103 | +#include <asm/arch/crm_regs.h> | ||
104 | +#include <asm/arch/clock.h> | ||
105 | +#include <asm/arch/iomux.h> | ||
106 | +#include <asm/errno.h> | ||
107 | +#include <netdev.h> | ||
108 | +#include <mmc.h> | ||
109 | +#include <fsl_esdhc.h> | ||
110 | +#include <asm/gpio.h> | ||
111 | + | ||
112 | +/* NOR flash configuration */ | ||
113 | +#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2)) | ||
114 | +#define IMA3_MX53_CS0GCR2 0 | ||
115 | +#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15)) | ||
116 | +#define IMA3_MX53_CS0RCR2 0 | ||
117 | +#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15)) | ||
118 | +#define IMA3_MX53_CS0WCR2 0 | ||
119 | + | ||
120 | +DECLARE_GLOBAL_DATA_PTR; | ||
121 | + | ||
122 | +static void weim_nor_settings(void) | ||
123 | +{ | ||
124 | + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; | ||
125 | + | ||
126 | + writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1); | ||
127 | + writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2); | ||
128 | + writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1); | ||
129 | + writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2); | ||
130 | + writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1); | ||
131 | + writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2); | ||
132 | + writel(0x0, &weim_regs->wcr); | ||
133 | + | ||
134 | + set_chipselect_size(CS0_128); | ||
135 | +} | ||
136 | + | ||
137 | +int dram_init(void) | ||
138 | +{ | ||
139 | + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, | ||
140 | + PHYS_SDRAM_1_SIZE); | ||
141 | + return 0; | ||
142 | +} | ||
143 | + | ||
144 | +static void setup_iomux_uart(void) | ||
145 | +{ | ||
146 | + /* UART4 RXD */ | ||
147 | + mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2); | ||
148 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D13, | ||
149 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | | ||
150 | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | | ||
151 | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); | ||
152 | + mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); | ||
153 | + | ||
154 | + /* UART4 TXD */ | ||
155 | + mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2); | ||
156 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D12, | ||
157 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | | ||
158 | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | | ||
159 | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); | ||
160 | +} | ||
161 | + | ||
162 | +static void setup_iomux_fec(void) | ||
163 | +{ | ||
164 | + /*FEC_MDIO*/ | ||
165 | + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); | ||
166 | + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, | ||
167 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | | ||
168 | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | | ||
169 | + PAD_CTL_ODE_OPENDRAIN_ENABLE); | ||
170 | + mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); | ||
171 | + | ||
172 | + /*FEC_MDC*/ | ||
173 | + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); | ||
174 | + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); | ||
175 | + | ||
176 | + /* FEC RXD3 */ | ||
177 | + mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); | ||
178 | + mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE | | ||
179 | + PAD_CTL_PKE_ENABLE); | ||
180 | + | ||
181 | + /* FEC RXD2 */ | ||
182 | + mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); | ||
183 | + mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE | | ||
184 | + PAD_CTL_PKE_ENABLE); | ||
185 | + | ||
186 | + /* FEC RXD1 */ | ||
187 | + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); | ||
188 | + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE | | ||
189 | + PAD_CTL_PKE_ENABLE); | ||
190 | + | ||
191 | + /* FEC RXD0 */ | ||
192 | + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); | ||
193 | + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE | | ||
194 | + PAD_CTL_PKE_ENABLE); | ||
195 | + | ||
196 | + /* FEC TXD3 */ | ||
197 | + mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6); | ||
198 | + mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH); | ||
199 | + | ||
200 | + /* FEC TXD2 */ | ||
201 | + mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); | ||
202 | + mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH); | ||
203 | + | ||
204 | + /* FEC TXD1 */ | ||
205 | + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); | ||
206 | + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); | ||
207 | + | ||
208 | + /* FEC TXD0 */ | ||
209 | + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); | ||
210 | + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); | ||
211 | + | ||
212 | + /* FEC TX_EN */ | ||
213 | + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); | ||
214 | + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); | ||
215 | + | ||
216 | + /* FEC TX_CLK */ | ||
217 | + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); | ||
218 | + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE | | ||
219 | + PAD_CTL_PKE_ENABLE); | ||
220 | + | ||
221 | + /* FEC RX_ER */ | ||
222 | + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); | ||
223 | + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE | | ||
224 | + PAD_CTL_PKE_ENABLE); | ||
225 | + | ||
226 | + /* FEC RX_DV */ | ||
227 | + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); | ||
228 | + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE | | ||
229 | + PAD_CTL_PKE_ENABLE); | ||
230 | + | ||
231 | + /* FEC CRS */ | ||
232 | + mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); | ||
233 | + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE | | ||
234 | + PAD_CTL_PKE_ENABLE); | ||
235 | + | ||
236 | + /* FEC COL */ | ||
237 | + mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); | ||
238 | + mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE | | ||
239 | + PAD_CTL_PKE_ENABLE); | ||
240 | + mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0); | ||
241 | + | ||
242 | + /* FEC RX_CLK */ | ||
243 | + mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); | ||
244 | + mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE | | ||
245 | + PAD_CTL_PKE_ENABLE); | ||
246 | + mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0); | ||
247 | +} | ||
248 | + | ||
249 | +#ifdef CONFIG_FSL_ESDHC | ||
250 | +struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 }; | ||
251 | + | ||
252 | +int board_mmc_getcd(struct mmc *mmc) | ||
253 | +{ | ||
254 | + int ret; | ||
255 | + | ||
256 | + ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); | ||
257 | + | ||
258 | + return ret; | ||
259 | +} | ||
260 | + | ||
261 | +int board_mmc_init(bd_t *bis) | ||
262 | +{ | ||
263 | + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); | ||
264 | + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); | ||
265 | + mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); | ||
266 | + mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); | ||
267 | + mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); | ||
268 | + mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); | ||
269 | + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); | ||
270 | + mxc_iomux_set_pad(MX53_PIN_GPIO_1, | ||
271 | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | | ||
272 | + PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | | ||
273 | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE); | ||
274 | + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); | ||
275 | + | ||
276 | + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, | ||
277 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
278 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); | ||
279 | + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, | ||
280 | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | | ||
281 | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH); | ||
282 | + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, | ||
283 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
284 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
285 | + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, | ||
286 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
287 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
288 | + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, | ||
289 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
290 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
291 | + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, | ||
292 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
293 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
294 | + | ||
295 | + return fsl_esdhc_initialize(bis, &esdhc_cfg); | ||
296 | +} | ||
297 | +#endif | ||
298 | + | ||
299 | +static void setup_iomux_spi(void) | ||
300 | +{ | ||
301 | + /* SCLK */ | ||
302 | + mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3); | ||
303 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, | ||
304 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
305 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
306 | + mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1); | ||
307 | + /* MOSI */ | ||
308 | + mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3); | ||
309 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, | ||
310 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
311 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
312 | + mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1); | ||
313 | + /* MISO */ | ||
314 | + mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3); | ||
315 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D10, | ||
316 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
317 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
318 | + mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1); | ||
319 | + /* SSEL 0 */ | ||
320 | + mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO); | ||
321 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D11, | ||
322 | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | | ||
323 | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); | ||
324 | + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1); | ||
325 | +} | ||
326 | + | ||
327 | +int board_early_init_f(void) | ||
328 | +{ | ||
329 | + /* configure I/O pads */ | ||
330 | + setup_iomux_uart(); | ||
331 | + setup_iomux_fec(); | ||
332 | + | ||
333 | + weim_nor_settings(); | ||
334 | + | ||
335 | + /* configure spi */ | ||
336 | + setup_iomux_spi(); | ||
337 | + | ||
338 | + return 0; | ||
339 | +} | ||
340 | + | ||
341 | +int board_init(void) | ||
342 | +{ | ||
343 | + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | ||
344 | + | ||
345 | + mxc_set_sata_internal_clock(); | ||
346 | + | ||
347 | + return 0; | ||
348 | +} | ||
349 | + | ||
350 | +#if defined(CONFIG_RESET_PHY_R) | ||
351 | +#include <miiphy.h> | ||
352 | + | ||
353 | +void reset_phy(void) | ||
354 | +{ | ||
355 | + unsigned short reg; | ||
356 | + | ||
357 | + /* reset the phy */ | ||
358 | + miiphy_reset("FEC", CONFIG_PHY_ADDR); | ||
359 | + | ||
360 | + /* set hard link to 100Mbit, full-duplex */ | ||
361 | + miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®); | ||
362 | + reg &= ~BMCR_ANENABLE; | ||
363 | + reg |= (BMCR_SPEED100 | BMCR_FULLDPLX); | ||
364 | + miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg); | ||
365 | + | ||
366 | + miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®); | ||
367 | + reg |= (1 << 5); | ||
368 | + miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg); | ||
369 | +} | ||
370 | +#endif | ||
371 | + | ||
372 | +int checkboard(void) | ||
373 | +{ | ||
374 | + puts("Board: IMA3_MX53\n"); | ||
375 | + | ||
376 | + return 0; | ||
377 | +} | ||
378 | diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg | ||
379 | new file mode 100644 | ||
380 | index 0000000..fa6b42d | ||
381 | --- /dev/null | ||
382 | +++ b/board/esg/ima3-mx53/imximage.cfg | ||
383 | @@ -0,0 +1,108 @@ | ||
384 | +# | ||
385 | +# (C) Copyright 2012 | ||
386 | +# Stefano Babic DENX Software Engineering sbabic@denx.de. | ||
387 | +# | ||
388 | +# See file CREDITS for list of people who contributed to this | ||
389 | +# project. | ||
390 | +# | ||
391 | +# This program is free software; you can redistribute it and/or | ||
392 | +# modify it under the terms of the GNU General Public License as | ||
393 | +# published by the Free Software Foundation; either version 2 of | ||
394 | +# the License or (at your option) any later version. | ||
395 | +# | ||
396 | +# This program is distributed in the hope that it will be useful, | ||
397 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
398 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
399 | +# GNU General Public License for more details. | ||
400 | +# | ||
401 | +# You should have received a copy of the GNU General Public License | ||
402 | +# along with this program; if not write to the Free Software | ||
403 | +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, | ||
404 | +# MA 02110-1301 USA | ||
405 | +# | ||
406 | +# Refer docs/README.imxmage for more details about how-to configure | ||
407 | +# and create imximage boot image | ||
408 | +# | ||
409 | +# The syntax is taken as close as possible with the kwbimage | ||
410 | + | ||
411 | +# image version | ||
412 | + | ||
413 | +IMAGE_VERSION 2 | ||
414 | + | ||
415 | +# Boot Device : one of | ||
416 | +# spi, sd (the board has no nand neither onenand) | ||
417 | + | ||
418 | +BOOT_FROM nor | ||
419 | + | ||
420 | +# Device Configuration Data (DCD) | ||
421 | +# | ||
422 | +# Each entry must have the format: | ||
423 | +# Addr-type Address Value | ||
424 | +# | ||
425 | +# where: | ||
426 | +# Addr-type register length (1,2 or 4 bytes) | ||
427 | +# Address absolute address of the register | ||
428 | +# value value to be stored in the register | ||
429 | + | ||
430 | +# IOMUX for RAM only | ||
431 | +DATA 4 0x53fa8554 0x300020 | ||
432 | +DATA 4 0x53fa8560 0x300020 | ||
433 | +DATA 4 0x53fa8594 0x300020 | ||
434 | +DATA 4 0x53fa8584 0x300020 | ||
435 | +DATA 4 0x53fa8558 0x300040 | ||
436 | +DATA 4 0x53fa8568 0x300040 | ||
437 | +DATA 4 0x53fa8590 0x300040 | ||
438 | +DATA 4 0x53fa857c 0x300040 | ||
439 | +DATA 4 0x53fa8564 0x300040 | ||
440 | +DATA 4 0x53fa8580 0x300040 | ||
441 | +DATA 4 0x53fa8570 0x300220 | ||
442 | +DATA 4 0x53fa8578 0x300220 | ||
443 | +DATA 4 0x53fa872c 0x300000 | ||
444 | +DATA 4 0x53fa8728 0x300000 | ||
445 | +DATA 4 0x53fa871c 0x300000 | ||
446 | +DATA 4 0x53fa8718 0x300000 | ||
447 | +DATA 4 0x53fa8574 0x300020 | ||
448 | +DATA 4 0x53fa8588 0x300020 | ||
449 | +DATA 4 0x53fa855c 0x0 | ||
450 | +DATA 4 0x53fa858c 0x0 | ||
451 | +DATA 4 0x53fa856c 0x300040 | ||
452 | +DATA 4 0x53fa86f0 0x300000 | ||
453 | +DATA 4 0x53fa8720 0x300000 | ||
454 | +DATA 4 0x53fa86fc 0x0 | ||
455 | +DATA 4 0x53fa86f4 0x0 | ||
456 | +DATA 4 0x53fa8714 0x0 | ||
457 | +DATA 4 0x53fa8724 0x4000000 | ||
458 | +# | ||
459 | +# DDR RAM | ||
460 | +DATA 4 0x63fd9088 0x40404040 | ||
461 | +DATA 4 0x63fd9090 0x40404040 | ||
462 | +DATA 4 0x63fd907C 0x01420143 | ||
463 | +DATA 4 0x63fd9080 0x01450146 | ||
464 | +DATA 4 0x63fd9018 0x00111740 | ||
465 | +DATA 4 0x63fd9000 0x84190000 | ||
466 | +# esdcfgX | ||
467 | +DATA 4 0x63fd900C 0x9f5152e3 | ||
468 | +DATA 4 0x63fd9010 0xb68e8a63 | ||
469 | +DATA 4 0x63fd9014 0x01ff00db | ||
470 | +# Read/Write command delay | ||
471 | +DATA 4 0x63fd902c 0x000026d2 | ||
472 | +# Out of reset delays | ||
473 | +DATA 4 0x63fd9030 0x00ff0e21 | ||
474 | +# ESDCTL ODT timing control | ||
475 | +DATA 4 0x63fd9008 0x12273030 | ||
476 | +# ESDCTL power down control | ||
477 | +DATA 4 0x63fd9004 0x0002002d | ||
478 | +# Set registers in DDR memory chips | ||
479 | +DATA 4 0x63fd901c 0x00008032 | ||
480 | +DATA 4 0x63fd901c 0x00008033 | ||
481 | +DATA 4 0x63fd901c 0x00028031 | ||
482 | +DATA 4 0x63fd901c 0x052080b0 | ||
483 | +DATA 4 0x63fd901c 0x04008040 | ||
484 | +# ESDCTL refresh control | ||
485 | +DATA 4 0x63fd9020 0x00005800 | ||
486 | +# PHY ZQ HW control | ||
487 | +DATA 4 0x63fd9040 0x05380003 | ||
488 | +# PHY ODT control | ||
489 | +DATA 4 0x63fd9058 0x00022222 | ||
490 | +# start DDR3 | ||
491 | +DATA 4 0x63fd901c 0x00000000 | ||
492 | diff --git a/boards.cfg b/boards.cfg | ||
493 | index 3cf75c3..93ecae6 100644 | ||
494 | --- a/boards.cfg | ||
495 | +++ b/boards.cfg | ||
496 | @@ -189,6 +189,7 @@ mx53ard arm armv7 mx53ard freesca | ||
497 | mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg | ||
498 | mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg | ||
499 | mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg | ||
500 | +ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg | ||
501 | vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg | ||
502 | mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg | ||
503 | mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg | ||
504 | diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h | ||
505 | new file mode 100644 | ||
506 | index 0000000..ea48d64 | ||
507 | --- /dev/null | ||
508 | +++ b/include/configs/ima3-mx53.h | ||
509 | @@ -0,0 +1,269 @@ | ||
510 | +/* | ||
511 | + * (C) Copyright 2012, Stefano Babic <sbabic@denx.de> | ||
512 | + * | ||
513 | + * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
514 | + * | ||
515 | + * Configuration settings for the MX53-EVK Freescale board. | ||
516 | + * | ||
517 | + * This program is free software; you can redistribute it and/or | ||
518 | + * modify it under the terms of the GNU General Public License as | ||
519 | + * published by the Free Software Foundation; either version 2 of | ||
520 | + * the License, or (at your option) any later version. | ||
521 | + * | ||
522 | + * This program is distributed in the hope that it will be useful, | ||
523 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
524 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
525 | + * GNU General Public License for more details. | ||
526 | + * | ||
527 | + * You should have received a copy of the GNU General Public License | ||
528 | + * along with this program; if not, write to the Free Software | ||
529 | + * Foundation, Inc. | ||
530 | + */ | ||
531 | + | ||
532 | +#ifndef __CONFIG_H | ||
533 | +#define __CONFIG_H | ||
534 | + | ||
535 | +/* SOC type must be included before imx-regs.h */ | ||
536 | +#define CONFIG_MX53 | ||
537 | +#include <asm/arch/imx-regs.h> | ||
538 | +#include <asm/arch/mx5x_pins.h> | ||
539 | + | ||
540 | +#define CONFIG_SYS_MX5_HCLK 24000000 | ||
541 | +#define CONFIG_SYS_MX5_CLK32 32768 | ||
542 | + | ||
543 | +#define CONFIG_DISPLAY_CPUINFO | ||
544 | +#define CONFIG_DISPLAY_BOARDINFO | ||
545 | + | ||
546 | +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | ||
547 | +#define CONFIG_SETUP_MEMORY_TAGS | ||
548 | +#define CONFIG_INITRD_TAG | ||
549 | + | ||
550 | +#define CONFIG_OF_LIBFDT | ||
551 | + | ||
552 | +/* Size of malloc() pool */ | ||
553 | +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | ||
554 | + | ||
555 | +#define CONFIG_BOARD_EARLY_INIT_F | ||
556 | + | ||
557 | +/* Enable GPIOs */ | ||
558 | +#define CONFIG_MXC_GPIO | ||
559 | + | ||
560 | +/* UART */ | ||
561 | +#define CONFIG_MXC_UART | ||
562 | +#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR | ||
563 | + | ||
564 | +/* MMC */ | ||
565 | +#define CONFIG_FSL_ESDHC | ||
566 | +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 | ||
567 | +#define CONFIG_SYS_FSL_ESDHC_NUM 1 | ||
568 | + | ||
569 | +#define CONFIG_MMC | ||
570 | +#define CONFIG_GENERIC_MMC | ||
571 | +#define CONFIG_DOS_PARTITION | ||
572 | + | ||
573 | +/* Ethernet on FEC */ | ||
574 | +#define CONFIG_NET_MULTI | ||
575 | +#define CONFIG_MII | ||
576 | +#define CONFIG_DISCOVER_PHY | ||
577 | + | ||
578 | +#define CONFIG_FEC_MXC | ||
579 | +#define IMX_FEC_BASE FEC_BASE_ADDR | ||
580 | +#define CONFIG_FEC_MXC_PHYADDR 0x01 | ||
581 | +#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR | ||
582 | +#define CONFIG_RESET_PHY_R | ||
583 | +#define CONFIG_FEC_MXC_NO_ANEG | ||
584 | +#define CONFIG_PRIME "FEC0" | ||
585 | + | ||
586 | +/* SPI */ | ||
587 | +#define CONFIG_HARD_SPI | ||
588 | +#define CONFIG_MXC_SPI | ||
589 | +#define CONFIG_DEFAULT_SPI_BUS 1 | ||
590 | +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 | ||
591 | + | ||
592 | +/* SPI FLASH - not used for environment */ | ||
593 | +#define CONFIG_SPI_FLASH | ||
594 | +#define CONFIG_SPI_FLASH_STMICRO | ||
595 | +#define CONFIG_SPI_FLASH_CS (IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \ | ||
596 | + << 8) | 0 | ||
597 | +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | ||
598 | +#define CONFIG_SF_DEFAULT_SPEED 25000000 | ||
599 | + | ||
600 | +/* allow to overwrite serial and ethaddr */ | ||
601 | +#define CONFIG_ENV_OVERWRITE | ||
602 | +#define CONFIG_CONS_INDEX 1 | ||
603 | +#define CONFIG_BAUDRATE 115200 | ||
604 | +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} | ||
605 | + | ||
606 | +/* Command definition */ | ||
607 | +#include <config_cmd_default.h> | ||
608 | +#define CONFIG_CMD_PING | ||
609 | +#define CONFIG_CMD_DHCP | ||
610 | +#define CONFIG_CMD_MII | ||
611 | +#define CONFIG_CMD_MMC | ||
612 | +#define CONFIG_CMD_FAT | ||
613 | +#define CONFIG_CMD_EXT2 | ||
614 | +#define CONFIG_CMD_MTDPARTS | ||
615 | +#define CONFIG_CMD_SPI | ||
616 | +#define CONFIG_CMD_SF | ||
617 | +#define CONFIG_CMD_GPIO | ||
618 | + | ||
619 | +#define CONFIG_BOOTDELAY 3 | ||
620 | + | ||
621 | +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ | ||
622 | +#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */ | ||
623 | + | ||
624 | +#define CONFIG_ARP_TIMEOUT 200UL | ||
625 | + | ||
626 | +/* Miscellaneous configurable options */ | ||
627 | +#define CONFIG_SYS_LONGHELP /* undef to save memory */ | ||
628 | +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | ||
629 | +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | ||
630 | +#define CONFIG_SYS_PROMPT "IMA3 MX53 U-Boot > " | ||
631 | +#define CONFIG_AUTO_COMPLETE | ||
632 | +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | ||
633 | + | ||
634 | +/* Print Buffer Size */ | ||
635 | +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | ||
636 | +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | ||
637 | +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | ||
638 | + | ||
639 | +#define CONFIG_SYS_MEMTEST_START 0x70000000 | ||
640 | +#define CONFIG_SYS_MEMTEST_END 0x10000 | ||
641 | + | ||
642 | +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | ||
643 | + | ||
644 | +#define CONFIG_SYS_HZ 1000 | ||
645 | +#define CONFIG_CMDLINE_EDITING | ||
646 | + | ||
647 | +/* Stack sizes */ | ||
648 | +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ | ||
649 | + | ||
650 | +/* Physical Memory Map */ | ||
651 | +#define CONFIG_NR_DRAM_BANKS 1 | ||
652 | +#define PHYS_SDRAM_1 CSD0_BASE_ADDR | ||
653 | +#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) | ||
654 | + | ||
655 | +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | ||
656 | +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | ||
657 | +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | ||
658 | + | ||
659 | +#define CONFIG_SYS_INIT_SP_OFFSET \ | ||
660 | + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | ||
661 | +#define CONFIG_SYS_INIT_SP_ADDR \ | ||
662 | + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | ||
663 | + | ||
664 | +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | ||
665 | +#define MTDIDS_DEFAULT "nor0=f0000000.flash" | ||
666 | + | ||
667 | +/* FLASH and environment organization */ | ||
668 | + | ||
669 | +#define CONFIG_SYS_FLASH_BASE 0xF0000000 | ||
670 | +#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ | ||
671 | +#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ | ||
672 | +#define CONFIG_FLASH_CFI_MTD /* with MTD support */ | ||
673 | +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | ||
674 | +#define CONFIG_SYS_MAX_FLASH_BANKS 1 | ||
675 | +#define CONFIG_SYS_MAX_FLASH_SECT 1024 | ||
676 | + | ||
677 | +#define CONFIG_SYS_FLASH_EMPTY_INFO | ||
678 | +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | ||
679 | + | ||
680 | +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | ||
681 | +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) | ||
682 | + | ||
683 | +#define CONFIG_ENV_SIZE (8 * 1024) | ||
684 | +#define CONFIG_ENV_IS_IN_FLASH | ||
685 | +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | ||
686 | + CONFIG_SYS_MONITOR_LEN) | ||
687 | +#define CONFIG_ENV_SECT_SIZE 0x20000 | ||
688 | +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ | ||
689 | + CONFIG_ENV_SECT_SIZE) | ||
690 | +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | ||
691 | + | ||
692 | +/* | ||
693 | + * Default environment and default scripts | ||
694 | + * to update uboot and load kernel | ||
695 | + */ | ||
696 | + | ||
697 | +#define HOSTNAME ima3-mx53 | ||
698 | +#define xstr(s) str(s) | ||
699 | +#define str(s) #s | ||
700 | + | ||
701 | +#define CONFIG_HOSTNAME ima3-mx53 | ||
702 | +#define CONFIG_EXTRA_ENV_SETTINGS \ | ||
703 | + "netdev=eth0\0" \ | ||
704 | + "nfsargs=setenv bootargs root=/dev/nfs rw " \ | ||
705 | + "nfsroot=${serverip}:${rootpath}\0" \ | ||
706 | + "ramargs=setenv bootargs root=/dev/ram0 rw\0" \ | ||
707 | + "addip_sta=setenv bootargs ${bootargs} " \ | ||
708 | + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | ||
709 | + ":${hostname}:${netdev}:off panic=1\0" \ | ||
710 | + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ | ||
711 | + "addip=if test -n ${ipdyn};then run addip_dyn;" \ | ||
712 | + "else run addip_sta;fi\0" \ | ||
713 | + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | ||
714 | + "addtty=setenv bootargs ${bootargs}" \ | ||
715 | + " console=${console},${baudrate}\0" \ | ||
716 | + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ | ||
717 | + "console=ttymxc3\0" \ | ||
718 | + "loadaddr=70800000\0" \ | ||
719 | + "kernel_addr_r=70800000\0" \ | ||
720 | + "ramdisk_addr_r=71000000\0" \ | ||
721 | + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ | ||
722 | + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ | ||
723 | + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ | ||
724 | + "mmcargs=setenv bootargs root=${mmcroot} " \ | ||
725 | + "rootfstype=${mmcrootfstype}\0" \ | ||
726 | + "mmcroot=/dev/mmcblk0p3 rw\0" \ | ||
727 | + "mmcboot=echo Booting from mmc ...; " \ | ||
728 | + "run mmcargs addip addtty addmtd addmisc mmcload;" \ | ||
729 | + "bootm\0" \ | ||
730 | + "mmcload=fatload mmc ${mmcdev}:${mmcpart} " \ | ||
731 | + "${loadaddr} ${uimage}\0" \ | ||
732 | + "mmcrootfstype=ext3 rootwait\0" \ | ||
733 | + "flash_self=run ramargs addip addtty addmtd addmisc;" \ | ||
734 | + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | ||
735 | + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ | ||
736 | + "bootm ${kernel_addr}\0" \ | ||
737 | + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | ||
738 | + "run nfsargs addip addtty addmtd addmisc;" \ | ||
739 | + "bootm ${kernel_addr_r}\0" \ | ||
740 | + "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \ | ||
741 | + "tftp ${kernel_addr_r} ${bootfile}\0" \ | ||
742 | + "net_self=if run net_self_load;then " \ | ||
743 | + "run ramargs addip addtty addmtd addmisc;" \ | ||
744 | + "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ | ||
745 | + "else echo Images not loades;fi\0" \ | ||
746 | + "satargs=setenv bootargs root=/dev/sda1\0" \ | ||
747 | + "satafile=boot/uImage\0" \ | ||
748 | + "ssdboot=echo Booting from ssd ...; " \ | ||
749 | + "run satargs addip addtty addmtd addmisc;" \ | ||
750 | + "sata init;ext2load sata 0:1 ${kernel_addr_r} " \ | ||
751 | + "${satafile};bootm\0" \ | ||
752 | + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0" \ | ||
753 | + "uimage=uImage\0" \ | ||
754 | + "load=tftp ${loadaddr} ${u-boot}\0" \ | ||
755 | + "uboot_addr=0xf0001000\0" \ | ||
756 | + "update=protect off 0xf0000000 +60000;" \ | ||
757 | + "erase ${uboot_addr} +60000;" \ | ||
758 | + "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ | ||
759 | + "upd=if run load;then echo Updating u-boot;if run update;" \ | ||
760 | + "then echo U-Boot updated;" \ | ||
761 | + "else echo Error updating u-boot !;" \ | ||
762 | + "echo Board without bootloader !!;" \ | ||
763 | + "fi;" \ | ||
764 | + "else echo U-Boot not downloaded..exiting;fi\0" \ | ||
765 | + "bootcmd=run net_nfs\0" | ||
766 | + | ||
767 | + | ||
768 | +#define CONFIG_CMD_SATA | ||
769 | +#ifdef CONFIG_CMD_SATA | ||
770 | + #define CONFIG_DWC_AHSATA | ||
771 | + #define CONFIG_SYS_SATA_MAX_DEVICE 1 | ||
772 | + #define CONFIG_DWC_AHSATA_PORT_ID 0 | ||
773 | + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | ||
774 | + #define CONFIG_LBA48 | ||
775 | + #define CONFIG_LIBATA | ||
776 | +#endif | ||
777 | + | ||
778 | +#endif /* __CONFIG_H */ | ||
779 | -- | ||
780 | 1.7.10 | ||
781 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0006-MX53-mx53loco-Add-SATA-support.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0006-MX53-mx53loco-Add-SATA-support.patch deleted file mode 100644 index 54b69b0..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0006-MX53-mx53loco-Add-SATA-support.patch +++ /dev/null | |||
@@ -1,64 +0,0 @@ | |||
1 | From d3ba981cb9e1e71abd34a23c06fa1d76ee722f77 Mon Sep 17 00:00:00 2001 | ||
2 | From: Stefano Babic <sbabic@denx.de> | ||
3 | Date: Wed, 22 Feb 2012 00:24:41 +0000 | ||
4 | Subject: [PATCH 06/56] MX53: mx53loco: Add SATA support | ||
5 | |||
6 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
7 | CC: Jason Liu <jason.hui@linaro.org> | ||
8 | Acked-by: Jason Liu <jason.hui@linaro.org> | ||
9 | --- | ||
10 | board/freescale/mx53loco/mx53loco.c | 3 +++ | ||
11 | include/configs/mx53loco.h | 11 +++++++++++ | ||
12 | 2 files changed, 14 insertions(+) | ||
13 | |||
14 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
15 | index d736141..7ea9f6e 100644 | ||
16 | --- a/board/freescale/mx53loco/mx53loco.c | ||
17 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
18 | @@ -27,6 +27,7 @@ | ||
19 | #include <asm/arch/mx5x_pins.h> | ||
20 | #include <asm/arch/sys_proto.h> | ||
21 | #include <asm/arch/crm_regs.h> | ||
22 | +#include <asm/arch/clock.h> | ||
23 | #include <asm/arch/iomux.h> | ||
24 | #include <asm/arch/clock.h> | ||
25 | #include <asm/errno.h> | ||
26 | @@ -302,6 +303,8 @@ int board_init(void) | ||
27 | { | ||
28 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | ||
29 | |||
30 | + mxc_set_sata_internal_clock(); | ||
31 | + | ||
32 | return 0; | ||
33 | } | ||
34 | |||
35 | diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h | ||
36 | index 34a4edd..af59307 100644 | ||
37 | --- a/include/configs/mx53loco.h | ||
38 | +++ b/include/configs/mx53loco.h | ||
39 | @@ -56,6 +56,7 @@ | ||
40 | #define CONFIG_CMD_MMC | ||
41 | #define CONFIG_GENERIC_MMC | ||
42 | #define CONFIG_CMD_FAT | ||
43 | +#define CONFIG_CMD_EXT2 | ||
44 | #define CONFIG_DOS_PARTITION | ||
45 | |||
46 | /* Eth Configs */ | ||
47 | @@ -193,4 +194,14 @@ | ||
48 | |||
49 | #define CONFIG_OF_LIBFDT | ||
50 | |||
51 | +#define CONFIG_CMD_SATA | ||
52 | +#ifdef CONFIG_CMD_SATA | ||
53 | + #define CONFIG_DWC_AHSATA | ||
54 | + #define CONFIG_SYS_SATA_MAX_DEVICE 1 | ||
55 | + #define CONFIG_DWC_AHSATA_PORT_ID 0 | ||
56 | + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | ||
57 | + #define CONFIG_LBA48 | ||
58 | + #define CONFIG_LIBATA | ||
59 | +#endif | ||
60 | + | ||
61 | #endif /* __CONFIG_H */ | ||
62 | -- | ||
63 | 1.7.10 | ||
64 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch deleted file mode 100644 index cf73354..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch +++ /dev/null | |||
@@ -1,267 +0,0 @@ | |||
1 | From 15675c7082f3a80ee2a67b436fdbb6bc800e6662 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Tue, 20 Mar 2012 11:40:06 +0000 | ||
4 | Subject: [PATCH 07/56] pmic: Add support for the Dialog DA9053 PMIC | ||
5 | |||
6 | Add support for the Dialog DA9053 PMIC. | ||
7 | |||
8 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | --- | ||
10 | drivers/misc/Makefile | 1 + | ||
11 | drivers/misc/pmic_dialog.c | 37 +++++++++ | ||
12 | include/dialog_pmic.h | 187 ++++++++++++++++++++++++++++++++++++++++++++ | ||
13 | 3 files changed, 225 insertions(+) | ||
14 | create mode 100644 drivers/misc/pmic_dialog.c | ||
15 | create mode 100644 include/dialog_pmic.h | ||
16 | |||
17 | diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile | ||
18 | index a709707..29d768b 100644 | ||
19 | --- a/drivers/misc/Makefile | ||
20 | +++ b/drivers/misc/Makefile | ||
21 | @@ -35,6 +35,7 @@ COBJS-$(CONFIG_PDSP188x) += pdsp188x.o | ||
22 | COBJS-$(CONFIG_STATUS_LED) += status_led.o | ||
23 | COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o | ||
24 | COBJS-$(CONFIG_PMIC) += pmic_core.o | ||
25 | +COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o | ||
26 | COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o | ||
27 | COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o | ||
28 | COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o | ||
29 | diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c | ||
30 | new file mode 100644 | ||
31 | index 0000000..7242073 | ||
32 | --- /dev/null | ||
33 | +++ b/drivers/misc/pmic_dialog.c | ||
34 | @@ -0,0 +1,37 @@ | ||
35 | +/* | ||
36 | + * Copyright (C) 2011 Samsung Electronics | ||
37 | + * Lukasz Majewski <l.majewski@samsung.com> | ||
38 | + * | ||
39 | + * See file CREDITS for list of people who contributed to this | ||
40 | + * project. | ||
41 | + * | ||
42 | + * This program is free software; you can redistribute it and/or | ||
43 | + * modify it under the terms of the GNU General Public License as | ||
44 | + * published by the Free Software Foundation; either version 2 of | ||
45 | + * the License, or (at your option) any later version. | ||
46 | + * | ||
47 | + * This program is distributed in the hope that it will be useful, | ||
48 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
49 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
50 | + * GNU General Public License for more details. | ||
51 | + */ | ||
52 | + | ||
53 | +#include <common.h> | ||
54 | +#include <pmic.h> | ||
55 | +#include <dialog_pmic.h> | ||
56 | + | ||
57 | +int pmic_init(void) | ||
58 | +{ | ||
59 | + struct pmic *p = get_pmic(); | ||
60 | + static const char name[] = "DIALOG_PMIC"; | ||
61 | + | ||
62 | + p->name = name; | ||
63 | + p->number_of_regs = PMIC_NUM_OF_REGS; | ||
64 | + | ||
65 | + p->interface = PMIC_I2C; | ||
66 | + p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR; | ||
67 | + p->hw.i2c.tx_num = 1; | ||
68 | + p->bus = I2C_PMIC; | ||
69 | + | ||
70 | + return 0; | ||
71 | +} | ||
72 | diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h | ||
73 | new file mode 100644 | ||
74 | index 0000000..b0925f5 | ||
75 | --- /dev/null | ||
76 | +++ b/include/dialog_pmic.h | ||
77 | @@ -0,0 +1,187 @@ | ||
78 | +/* | ||
79 | + * da9053 register declarations. | ||
80 | + * | ||
81 | + * Copyright(c) 2009 Dialog Semiconductor Ltd. | ||
82 | + * | ||
83 | + * This program is free software; you can redistribute it and/or modify | ||
84 | + * it under the terms of the GNU General Public License as published by | ||
85 | + * the Free Software Foundation; either version 2 of the License, or | ||
86 | + * (at your option) any later version. | ||
87 | + * | ||
88 | + * This program is distributed in the hope that it will be useful, | ||
89 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
90 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
91 | + * GNU General Public License for more details. | ||
92 | + * | ||
93 | + * You should have received a copy of the GNU General Public License | ||
94 | + * along with this program; if not, write to the Free Software | ||
95 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
96 | + * | ||
97 | + */ | ||
98 | + | ||
99 | +#ifndef __DIALOG_PMIC_H__ | ||
100 | +#define __DIALOG_PMIC_H__ | ||
101 | + | ||
102 | +enum { | ||
103 | + DA9053_PAGECON0_REG = 0, | ||
104 | + DA9053_STATUSA_REG, | ||
105 | + DA9053_STATUSB_REG, | ||
106 | + DA9053_STATUSC_REG, | ||
107 | + DA9053_STATUSD_REG, | ||
108 | + DA9053_EVENTA_REG, | ||
109 | + DA9053_EVENTB_REG, | ||
110 | + DA9053_EVENTC_REG, | ||
111 | + DA9053_EVENTD_REG, | ||
112 | + DA9053_FAULTLOG_REG, | ||
113 | + DA9053_IRQMASKA_REG, | ||
114 | + DA9053_IRQMASKB_REG, | ||
115 | + DA9053_IRQMASKC_REG, | ||
116 | + DA9053_IRQMASKD_REG, | ||
117 | + DA9053_CONTROLA_REG, | ||
118 | + DA9053_CONTROLB_REG, | ||
119 | + DA9053_CONTROLC_REG, | ||
120 | + DA9053_CONTROLD_REG, | ||
121 | + DA9053_PDDIS_REG, | ||
122 | + DA9053_INTERFACE_REG, | ||
123 | + DA9053_RESET_REG, | ||
124 | + DA9053_GPIO0001_REG, | ||
125 | + DA9053_GPIO0203_REG, | ||
126 | + DA9053_GPIO0405_REG, | ||
127 | + DA9053_GPIO0607_REG, | ||
128 | + DA9053_GPIO0809_REG, | ||
129 | + DA9053_GPIO1011_REG, | ||
130 | + DA9053_GPIO1213_REG, | ||
131 | + DA9053_GPIO1415_REG, | ||
132 | + DA9053_ID01_REG, | ||
133 | + DA9053_ID23_REG, | ||
134 | + DA9053_ID45_REG, | ||
135 | + DA9053_ID67_REG, | ||
136 | + DA9053_ID89_REG, | ||
137 | + DA9053_ID1011_REG, | ||
138 | + DA9053_ID1213_REG, | ||
139 | + DA9053_ID1415_REG, | ||
140 | + DA9053_ID1617_REG, | ||
141 | + DA9053_ID1819_REG, | ||
142 | + DA9053_ID2021_REG, | ||
143 | + DA9053_SEQSTATUS_REG, | ||
144 | + DA9053_SEQA_REG, | ||
145 | + DA9053_SEQB_REG, | ||
146 | + DA9053_SEQTIMER_REG, | ||
147 | + DA9053_BUCKA_REG, | ||
148 | + DA9053_BUCKB_REG, | ||
149 | + DA9053_BUCKCORE_REG, | ||
150 | + DA9053_BUCKPRO_REG, | ||
151 | + DA9053_BUCKMEM_REG, | ||
152 | + DA9053_BUCKPERI_REG, | ||
153 | + DA9053_LDO1_REG, | ||
154 | + DA9053_LDO2_REG, | ||
155 | + DA9053_LDO3_REG, | ||
156 | + DA9053_LDO4_REG, | ||
157 | + DA9053_LDO5_REG, | ||
158 | + DA9053_LDO6_REG, | ||
159 | + DA9053_LDO7_REG, | ||
160 | + DA9053_LDO8_REG, | ||
161 | + DA9053_LDO9_REG, | ||
162 | + DA9053_LDO10_REG, | ||
163 | + DA9053_SUPPLY_REG, | ||
164 | + DA9053_PULLDOWN_REG, | ||
165 | + DA9053_CHGBUCK_REG, | ||
166 | + DA9053_WAITCONT_REG, | ||
167 | + DA9053_ISET_REG, | ||
168 | + DA9053_BATCHG_REG, | ||
169 | + DA9053_CHGCONT_REG, | ||
170 | + DA9053_INPUTCONT_REG, | ||
171 | + DA9053_CHGTIME_REG, | ||
172 | + DA9053_BBATCONT_REG, | ||
173 | + DA9053_BOOST_REG, | ||
174 | + DA9053_LEDCONT_REG, | ||
175 | + DA9053_LEDMIN123_REG, | ||
176 | + DA9053_LED1CONF_REG, | ||
177 | + DA9053_LED2CONF_REG, | ||
178 | + DA9053_LED3CONF_REG, | ||
179 | + DA9053_LED1CONT_REG, | ||
180 | + DA9053_LED2CONT_REG, | ||
181 | + DA9053_LED3CONT_REG, | ||
182 | + DA9053_LED4CONT_REG, | ||
183 | + DA9053_LED5CONT_REG, | ||
184 | + DA9053_ADCMAN_REG, | ||
185 | + DA9053_ADCCONT_REG, | ||
186 | + DA9053_ADCRESL_REG, | ||
187 | + DA9053_ADCRESH_REG, | ||
188 | + DA9053_VDDRES_REG, | ||
189 | + DA9053_VDDMON_REG, | ||
190 | + DA9053_ICHGAV_REG, | ||
191 | + DA9053_ICHGTHD_REG, | ||
192 | + DA9053_ICHGEND_REG, | ||
193 | + DA9053_TBATRES_REG, | ||
194 | + DA9053_TBATHIGHP_REG, | ||
195 | + DA9053_TBATHIGHIN_REG, | ||
196 | + DA9053_TBATLOW_REG, | ||
197 | + DA9053_TOFFSET_REG, | ||
198 | + DA9053_ADCIN4RES_REG, | ||
199 | + DA9053_AUTO4HIGH_REG, | ||
200 | + DA9053_AUTO4LOW_REG, | ||
201 | + DA9053_ADCIN5RES_REG, | ||
202 | + DA9053_AUTO5HIGH_REG, | ||
203 | + DA9053_AUTO5LOW_REG, | ||
204 | + DA9053_ADCIN6RES_REG, | ||
205 | + DA9053_AUTO6HIGH_REG, | ||
206 | + DA9053_AUTO6LOW_REG, | ||
207 | + DA9053_TJUNCRES_REG, | ||
208 | + DA9053_TSICONTA_REG, | ||
209 | + DA9053_TSICONTB_REG, | ||
210 | + DA9053_TSIXMSB_REG, | ||
211 | + DA9053_TSIYMSB_REG, | ||
212 | + DA9053_TSILSB_REG, | ||
213 | + DA9053_TSIZMSB_REG, | ||
214 | + DA9053_COUNTS_REG, | ||
215 | + DA9053_COUNTMI_REG, | ||
216 | + DA9053_COUNTH_REG, | ||
217 | + DA9053_COUNTD_REG, | ||
218 | + DA9053_COUNTMO_REG, | ||
219 | + DA9053_COUNTY_REG, | ||
220 | + DA9053_ALARMMI_REG, | ||
221 | + DA9053_ALARMH_REG, | ||
222 | + DA9053_ALARMD_REG, | ||
223 | + DA9053_ALARMMO_REG, | ||
224 | + DA9053_ALARMY_REG, | ||
225 | + DA9053_SECONDA_REG, | ||
226 | + DA9053_SECONDB_REG, | ||
227 | + DA9053_SECONDC_REG, | ||
228 | + DA9053_SECONDD_REG, | ||
229 | + DA9053_PAGECON128_REG, | ||
230 | + DA9053_CHIPID_REG, | ||
231 | + DA9053_CONFIGID_REG, | ||
232 | + DA9053_OTPCONT_REG, | ||
233 | + DA9053_OSCTRIM_REG, | ||
234 | + DA9053_GPID0_REG, | ||
235 | + DA9053_GPID1_REG, | ||
236 | + DA9053_GPID2_REG, | ||
237 | + DA9053_GPID3_REG, | ||
238 | + DA9053_GPID4_REG, | ||
239 | + DA9053_GPID5_REG, | ||
240 | + DA9053_GPID6_REG, | ||
241 | + DA9053_GPID7_REG, | ||
242 | + DA9053_GPID8_REG, | ||
243 | + DA9053_GPID9_REG, | ||
244 | + PMIC_NUM_OF_REGS, | ||
245 | +}; | ||
246 | + | ||
247 | +#define DA_BUCKCORE_VBCORE_1_250V 0x1E | ||
248 | + | ||
249 | +/* BUCKCORE REGISTER */ | ||
250 | +#define DA9052_BUCKCORE_BCORECONF (1 << 7) | ||
251 | +#define DA9052_BUCKCORE_BCOREEN (1 << 6) | ||
252 | +#define DA9052_BUCKCORE_VBCORE 63 | ||
253 | + | ||
254 | +/* SUPPLY REGISTER */ | ||
255 | +#define DA9052_SUPPLY_VLOCK (1 << 7) | ||
256 | +#define DA9052_SUPPLY_VMEMSWEN (1 << 6) | ||
257 | +#define DA9052_SUPPLY_VPERISWEN (1 << 5) | ||
258 | +#define DA9052_SUPPLY_VLDO3GO (1 << 4) | ||
259 | +#define DA9052_SUPPLY_VLDO2GO (1 << 3) | ||
260 | +#define DA9052_SUPPLY_VBMEMGO (1 << 2) | ||
261 | +#define DA9052_SUPPLY_VBPROGO (1 << 1) | ||
262 | +#define DA9052_SUPPLY_VBCOREGO (1 << 0) | ||
263 | + | ||
264 | +#endif /* __DIALOG_PMIC_H__ */ | ||
265 | -- | ||
266 | 1.7.10 | ||
267 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch deleted file mode 100644 index 5514e23..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | From 7bca215d56396abf4173e101f6a292117db2d373 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <festevam@gmail.com> | ||
3 | Date: Wed, 11 Apr 2012 10:22:24 +0000 | ||
4 | Subject: [PATCH 08/56] mx6qsabrelite: No need to set the direction for | ||
5 | GPIO3_23 again | ||
6 | |||
7 | There is a 'gpio_direction_output(87, 0);' call previously, so the GPIO direction is | ||
8 | already established. | ||
9 | |||
10 | Use gpio_set_value() for changing the GPIO output then. | ||
11 | |||
12 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
13 | Acked-by: Dirk Behme <dirk.behme@googlemail.com> | ||
14 | --- | ||
15 | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 2 +- | ||
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
19 | index fda3e41..b4d9519 100644 | ||
20 | --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
21 | +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
22 | @@ -135,7 +135,7 @@ static void setup_iomux_enet(void) | ||
23 | |||
24 | /* Need delay 10ms according to KSZ9021 spec */ | ||
25 | udelay(1000 * 10); | ||
26 | - gpio_direction_output(87, 1); /* GPIO 3-23 */ | ||
27 | + gpio_set_value(87, 1); /* GPIO 3-23 */ | ||
28 | |||
29 | imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); | ||
30 | } | ||
31 | -- | ||
32 | 1.7.10 | ||
33 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0009-mx28evk-Allow-to-booting-a-dt-kernel.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0009-mx28evk-Allow-to-booting-a-dt-kernel.patch deleted file mode 100644 index 29cfdb0..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0009-mx28evk-Allow-to-booting-a-dt-kernel.patch +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | From aff99e861996d61fda4ea4158f727cf2657abc52 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 06:06:28 +0000 | ||
4 | Subject: [PATCH 09/56] mx28evk: Allow to booting a dt kernel | ||
5 | |||
6 | Allow to booting a dt kernel. | ||
7 | |||
8 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | --- | ||
10 | include/configs/mx28evk.h | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h | ||
14 | index 02f3366..cb4ff37 100644 | ||
15 | --- a/include/configs/mx28evk.h | ||
16 | +++ b/include/configs/mx28evk.h | ||
17 | @@ -225,6 +225,7 @@ | ||
18 | #define CONFIG_BOOTCOMMAND "run bootcmd_net" | ||
19 | #define CONFIG_LOADADDR 0x42000000 | ||
20 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | ||
21 | +#define CONFIG_OF_LIBFDT | ||
22 | |||
23 | /* | ||
24 | * Extra Environments | ||
25 | -- | ||
26 | 1.7.10 | ||
27 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0010-m28evk-Allow-to-booting-a-dt-kernel.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0010-m28evk-Allow-to-booting-a-dt-kernel.patch deleted file mode 100644 index cf0ba98..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0010-m28evk-Allow-to-booting-a-dt-kernel.patch +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | From 8b35d52540a88bc8ed2576a59c29cbe13619665d Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 06:06:29 +0000 | ||
4 | Subject: [PATCH 10/56] m28evk: Allow to booting a dt kernel | ||
5 | |||
6 | Allow to booting a dt kernel. | ||
7 | |||
8 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | --- | ||
10 | include/configs/m28evk.h | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h | ||
14 | index 012381a..39d6a07 100644 | ||
15 | --- a/include/configs/m28evk.h | ||
16 | +++ b/include/configs/m28evk.h | ||
17 | @@ -279,6 +279,7 @@ | ||
18 | #define CONFIG_BOOTCOMMAND "run bootcmd_net" | ||
19 | #define CONFIG_LOADADDR 0x42000000 | ||
20 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | ||
21 | +#define CONFIG_OF_LIBFDT | ||
22 | |||
23 | /* | ||
24 | * Extra Environments | ||
25 | -- | ||
26 | 1.7.10 | ||
27 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0011-mx28evk-Allow-booting-a-zImage-kernel.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0011-mx28evk-Allow-booting-a-zImage-kernel.patch deleted file mode 100644 index 6c23534..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0011-mx28evk-Allow-booting-a-zImage-kernel.patch +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | From bd41d70b1e3cb9188b387a37cd738782602ea611 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 06:31:15 +0000 | ||
4 | Subject: [PATCH 11/56] mx28evk: Allow booting a zImage kernel | ||
5 | |||
6 | Allow booting a zImage kernel. | ||
7 | |||
8 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | --- | ||
10 | include/configs/mx28evk.h | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h | ||
14 | index cb4ff37..31dc718 100644 | ||
15 | --- a/include/configs/mx28evk.h | ||
16 | +++ b/include/configs/mx28evk.h | ||
17 | @@ -67,6 +67,7 @@ | ||
18 | #define CONFIG_CMD_SF | ||
19 | #define CONFIG_CMD_SPI | ||
20 | #define CONFIG_CMD_USB | ||
21 | +#define CONFIG_CMD_BOOTZ | ||
22 | |||
23 | /* | ||
24 | * Memory configurations | ||
25 | -- | ||
26 | 1.7.10 | ||
27 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch deleted file mode 100644 index 03ddeeb..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | From ff7f1a06324041db0598e7439f907fd9f3d2e6a5 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 06:31:16 +0000 | ||
4 | Subject: [PATCH 12/56] mx6qsabrelite: Allow booting a zImage kernel | ||
5 | |||
6 | Allow booting a zImage kernel. | ||
7 | |||
8 | Cc: Jason Liu <r64343@freescale.com> | ||
9 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
10 | --- | ||
11 | include/configs/mx6qsabrelite.h | 1 + | ||
12 | 1 file changed, 1 insertion(+) | ||
13 | |||
14 | diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h | ||
15 | index 3f7e51d..492c618 100644 | ||
16 | --- a/include/configs/mx6qsabrelite.h | ||
17 | +++ b/include/configs/mx6qsabrelite.h | ||
18 | @@ -211,6 +211,7 @@ | ||
19 | #endif | ||
20 | |||
21 | #define CONFIG_OF_LIBFDT | ||
22 | +#define CONFIG_CMD_BOOTZ | ||
23 | |||
24 | #define CONFIG_SYS_DCACHE_OFF | ||
25 | |||
26 | -- | ||
27 | 1.7.10 | ||
28 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch deleted file mode 100644 index 98a94b2..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | From 9d544113fe792e8b8f32b24db33630ba78f8fd47 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 06:31:17 +0000 | ||
4 | Subject: [PATCH 13/56] mx6qarm2: Allow booting a zImage kernel | ||
5 | |||
6 | Allow booting a zImage kernel. | ||
7 | |||
8 | Cc: Jason Liu <r64343@freescale.com> | ||
9 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
10 | Acked-by: Jason Liu <r64343@freescale.com> | ||
11 | --- | ||
12 | include/configs/mx6qarm2.h | 1 + | ||
13 | 1 file changed, 1 insertion(+) | ||
14 | |||
15 | diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h | ||
16 | index e83aec6..90652c6 100644 | ||
17 | --- a/include/configs/mx6qarm2.h | ||
18 | +++ b/include/configs/mx6qarm2.h | ||
19 | @@ -168,6 +168,7 @@ | ||
20 | #define CONFIG_SYS_MMC_ENV_DEV 1 | ||
21 | |||
22 | #define CONFIG_OF_LIBFDT | ||
23 | +#define CONFIG_CMD_BOOTZ | ||
24 | |||
25 | #define CONFIG_SYS_DCACHE_OFF | ||
26 | |||
27 | -- | ||
28 | 1.7.10 | ||
29 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0014-mx31pdk-Allow-booting-a-zImage-kernel.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0014-mx31pdk-Allow-booting-a-zImage-kernel.patch deleted file mode 100644 index 3dc7533..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0014-mx31pdk-Allow-booting-a-zImage-kernel.patch +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | From 4a2f5e4f606146c373d7421e1a340d2bdbb54ffe Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 06:31:18 +0000 | ||
4 | Subject: [PATCH 14/56] mx31pdk: Allow booting a zImage kernel | ||
5 | |||
6 | Allow booting a zImage kernel. | ||
7 | |||
8 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | --- | ||
10 | include/configs/mx31pdk.h | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h | ||
14 | index 49d440b..6ce97bc 100644 | ||
15 | --- a/include/configs/mx31pdk.h | ||
16 | +++ b/include/configs/mx31pdk.h | ||
17 | @@ -99,6 +99,7 @@ | ||
18 | #define CONFIG_CMD_SPI | ||
19 | #define CONFIG_CMD_DATE | ||
20 | #define CONFIG_CMD_NAND | ||
21 | +#define CONFIG_CMD_BOOTZ | ||
22 | |||
23 | /* | ||
24 | * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require | ||
25 | -- | ||
26 | 1.7.10 | ||
27 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch deleted file mode 100644 index 1b263be..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch +++ /dev/null | |||
@@ -1,195 +0,0 @@ | |||
1 | From 92a45a8ec4bf1abe5ff5ac123bf4edd6ccb2f353 Mon Sep 17 00:00:00 2001 | ||
2 | From: Eric Nelson <eric.nelson@boundarydevices.com> | ||
3 | Date: Wed, 25 Apr 2012 14:14:04 +0000 | ||
4 | Subject: [PATCH 15/56] i.MX6Q: mx6qsabrelite: Add keypress support to alter | ||
5 | boot flow | ||
6 | |||
7 | Uses the 'magic_keys' idiom as described in doc/README.kbd: | ||
8 | http://lists.denx.de/pipermail/u-boot/2012-April/122502.html | ||
9 | |||
10 | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> | ||
11 | Acked-by: Marek Vasut <marex@denx.de> | ||
12 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
13 | --- | ||
14 | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 122 ++++++++++++++++++++++++- | ||
15 | include/configs/mx6qsabrelite.h | 3 + | ||
16 | 2 files changed, 123 insertions(+), 2 deletions(-) | ||
17 | |||
18 | diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
19 | index b4d9519..90773aa 100644 | ||
20 | --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
21 | +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
22 | @@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR; | ||
23 | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ | ||
24 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | ||
25 | |||
26 | +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
27 | + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | ||
28 | + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | ||
29 | + | ||
30 | int dram_init(void) | ||
31 | { | ||
32 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); | ||
33 | @@ -122,6 +126,22 @@ iomux_v3_cfg_t enet_pads2[] = { | ||
34 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | ||
35 | }; | ||
36 | |||
37 | +/* Button assignments for J14 */ | ||
38 | +static iomux_v3_cfg_t button_pads[] = { | ||
39 | + /* Menu */ | ||
40 | + MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), | ||
41 | + /* Back */ | ||
42 | + MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), | ||
43 | + /* Labelled Search (mapped to Power under Android) */ | ||
44 | + MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), | ||
45 | + /* Home */ | ||
46 | + MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), | ||
47 | + /* Volume Down */ | ||
48 | + MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), | ||
49 | + /* Volume Up */ | ||
50 | + MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), | ||
51 | +}; | ||
52 | + | ||
53 | static void setup_iomux_enet(void) | ||
54 | { | ||
55 | gpio_direction_output(87, 0); /* GPIO 3-23 */ | ||
56 | @@ -267,11 +287,18 @@ int board_eth_init(bd_t *bis) | ||
57 | return 0; | ||
58 | } | ||
59 | |||
60 | +static void setup_buttons(void) | ||
61 | +{ | ||
62 | + imx_iomux_v3_setup_multiple_pads(button_pads, | ||
63 | + ARRAY_SIZE(button_pads)); | ||
64 | +} | ||
65 | + | ||
66 | int board_early_init_f(void) | ||
67 | { | ||
68 | - setup_iomux_uart(); | ||
69 | + setup_iomux_uart(); | ||
70 | + setup_buttons(); | ||
71 | |||
72 | - return 0; | ||
73 | + return 0; | ||
74 | } | ||
75 | |||
76 | int board_init(void) | ||
77 | @@ -292,3 +319,94 @@ int checkboard(void) | ||
78 | |||
79 | return 0; | ||
80 | } | ||
81 | + | ||
82 | +struct button_key { | ||
83 | + char const *name; | ||
84 | + unsigned gpnum; | ||
85 | + char ident; | ||
86 | +}; | ||
87 | + | ||
88 | +static struct button_key const buttons[] = { | ||
89 | + {"back", GPIO_NUMBER(2, 2), 'B'}, | ||
90 | + {"home", GPIO_NUMBER(2, 4), 'H'}, | ||
91 | + {"menu", GPIO_NUMBER(2, 1), 'M'}, | ||
92 | + {"search", GPIO_NUMBER(2, 3), 'S'}, | ||
93 | + {"volup", GPIO_NUMBER(7, 13), 'V'}, | ||
94 | + {"voldown", GPIO_NUMBER(4, 5), 'v'}, | ||
95 | +}; | ||
96 | + | ||
97 | +/* | ||
98 | + * generate a null-terminated string containing the buttons pressed | ||
99 | + * returns number of keys pressed | ||
100 | + */ | ||
101 | +static int read_keys(char *buf) | ||
102 | +{ | ||
103 | + int i, numpressed = 0; | ||
104 | + for (i = 0; i < ARRAY_SIZE(buttons); i++) { | ||
105 | + if (!gpio_get_value(buttons[i].gpnum)) | ||
106 | + buf[numpressed++] = buttons[i].ident; | ||
107 | + } | ||
108 | + buf[numpressed] = '\0'; | ||
109 | + return numpressed; | ||
110 | +} | ||
111 | + | ||
112 | +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | ||
113 | +{ | ||
114 | + char envvalue[ARRAY_SIZE(buttons)+1]; | ||
115 | + int numpressed = read_keys(envvalue); | ||
116 | + setenv("keybd", envvalue); | ||
117 | + return numpressed == 0; | ||
118 | +} | ||
119 | + | ||
120 | +U_BOOT_CMD( | ||
121 | + kbd, 1, 1, do_kbd, | ||
122 | + "Tests for keypresses, sets 'keybd' environment variable", | ||
123 | + "Returns 0 (true) to shell if key is pressed." | ||
124 | +); | ||
125 | + | ||
126 | +#ifdef CONFIG_PREBOOT | ||
127 | +static char const kbd_magic_prefix[] = "key_magic"; | ||
128 | +static char const kbd_command_prefix[] = "key_cmd"; | ||
129 | + | ||
130 | +static void preboot_keys(void) | ||
131 | +{ | ||
132 | + int numpressed; | ||
133 | + char keypress[ARRAY_SIZE(buttons)+1]; | ||
134 | + numpressed = read_keys(keypress); | ||
135 | + if (numpressed) { | ||
136 | + char *kbd_magic_keys = getenv("magic_keys"); | ||
137 | + char *suffix; | ||
138 | + /* | ||
139 | + * loop over all magic keys | ||
140 | + */ | ||
141 | + for (suffix = kbd_magic_keys; *suffix; ++suffix) { | ||
142 | + char *keys; | ||
143 | + char magic[sizeof(kbd_magic_prefix) + 1]; | ||
144 | + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); | ||
145 | + keys = getenv(magic); | ||
146 | + if (keys) { | ||
147 | + if (!strcmp(keys, keypress)) | ||
148 | + break; | ||
149 | + } | ||
150 | + } | ||
151 | + if (*suffix) { | ||
152 | + char cmd_name[sizeof(kbd_command_prefix) + 1]; | ||
153 | + char *cmd; | ||
154 | + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); | ||
155 | + cmd = getenv(cmd_name); | ||
156 | + if (cmd) { | ||
157 | + setenv("preboot", cmd); | ||
158 | + return; | ||
159 | + } | ||
160 | + } | ||
161 | + } | ||
162 | +} | ||
163 | +#endif | ||
164 | + | ||
165 | +int misc_init_r(void) | ||
166 | +{ | ||
167 | +#ifdef CONFIG_PREBOOT | ||
168 | + preboot_keys(); | ||
169 | +#endif | ||
170 | + return 0; | ||
171 | +} | ||
172 | diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h | ||
173 | index 492c618..48be6e6 100644 | ||
174 | --- a/include/configs/mx6qsabrelite.h | ||
175 | +++ b/include/configs/mx6qsabrelite.h | ||
176 | @@ -42,6 +42,7 @@ | ||
177 | |||
178 | #define CONFIG_ARCH_CPU_INIT | ||
179 | #define CONFIG_BOARD_EARLY_INIT_F | ||
180 | +#define CONFIG_MISC_INIT_R | ||
181 | #define CONFIG_MXC_GPIO | ||
182 | |||
183 | #define CONFIG_MXC_UART | ||
184 | @@ -110,6 +111,8 @@ | ||
185 | |||
186 | #define CONFIG_BOOTDELAY 3 | ||
187 | |||
188 | +#define CONFIG_PREBOOT "" | ||
189 | + | ||
190 | #define CONFIG_LOADADDR 0x10800000 | ||
191 | #define CONFIG_SYS_TEXT_BASE 0x17800000 | ||
192 | |||
193 | -- | ||
194 | 1.7.10 | ||
195 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch deleted file mode 100644 index 0787939..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0016-imx-common-Factor-out-get_ahb_clk.patch +++ /dev/null | |||
@@ -1,1970 +0,0 @@ | |||
1 | From a849600b9d2b702acf3d1b21b96bc3df8ea53e6d Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <festevam@gmail.com> | ||
3 | Date: Sun, 29 Apr 2012 08:11:13 +0000 | ||
4 | Subject: [PATCH 16/56] imx-common: Factor out get_ahb_clk() | ||
5 | |||
6 | get_ahb_clk() is a common function between mx5 and mx6. | ||
7 | |||
8 | Place it into imx-common directory. | ||
9 | |||
10 | Cc: Dirk Behme <dirk.behme@googlemail.com> | ||
11 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
12 | --- | ||
13 | arch/arm/cpu/armv7/imx-common/cpu.c | 13 + | ||
14 | arch/arm/cpu/armv7/mx5/clock.c | 19 +- | ||
15 | arch/arm/cpu/armv7/mx6/clock.c | 19 +- | ||
16 | arch/arm/include/asm/arch-mx5/sys_proto.h | 2 + | ||
17 | arch/arm/include/asm/arch-mx6/ccm_regs.h | 892 ----------------------------- | ||
18 | arch/arm/include/asm/arch-mx6/crm_regs.h | 892 +++++++++++++++++++++++++++++ | ||
19 | arch/arm/include/asm/arch-mx6/sys_proto.h | 3 +- | ||
20 | 7 files changed, 915 insertions(+), 925 deletions(-) | ||
21 | delete mode 100644 arch/arm/include/asm/arch-mx6/ccm_regs.h | ||
22 | create mode 100644 arch/arm/include/asm/arch-mx6/crm_regs.h | ||
23 | |||
24 | diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c | ||
25 | index 3d58d8a..b96fa5b 100644 | ||
26 | --- a/arch/arm/cpu/armv7/imx-common/cpu.c | ||
27 | +++ b/arch/arm/cpu/armv7/imx-common/cpu.c | ||
28 | @@ -29,6 +29,7 @@ | ||
29 | #include <asm/arch/imx-regs.h> | ||
30 | #include <asm/arch/clock.h> | ||
31 | #include <asm/arch/sys_proto.h> | ||
32 | +#include <asm/arch/crm_regs.h> | ||
33 | |||
34 | #ifdef CONFIG_FSL_ESDHC | ||
35 | #include <fsl_esdhc.h> | ||
36 | @@ -127,3 +128,15 @@ void reset_cpu(ulong addr) | ||
37 | { | ||
38 | __raw_writew(4, WDOG1_BASE_ADDR); | ||
39 | } | ||
40 | + | ||
41 | +u32 get_ahb_clk(void) | ||
42 | +{ | ||
43 | + struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | ||
44 | + u32 reg, ahb_podf; | ||
45 | + | ||
46 | + reg = __raw_readl(&imx_ccm->cbcdr); | ||
47 | + reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; | ||
48 | + ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; | ||
49 | + | ||
50 | + return get_periph_clk() / (ahb_podf + 1); | ||
51 | +} | ||
52 | diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c | ||
53 | index d769a4d..903e207 100644 | ||
54 | --- a/arch/arm/cpu/armv7/mx5/clock.c | ||
55 | +++ b/arch/arm/cpu/armv7/mx5/clock.c | ||
56 | @@ -30,6 +30,7 @@ | ||
57 | #include <asm/arch/crm_regs.h> | ||
58 | #include <asm/arch/clock.h> | ||
59 | #include <div64.h> | ||
60 | +#include <asm/arch/sys_proto.h> | ||
61 | |||
62 | enum pll_clocks { | ||
63 | PLL1_CLOCK = 0, | ||
64 | @@ -192,7 +193,7 @@ u32 get_mcu_main_clk(void) | ||
65 | /* | ||
66 | * Get the rate of peripheral's root clock. | ||
67 | */ | ||
68 | -static u32 get_periph_clk(void) | ||
69 | +u32 get_periph_clk(void) | ||
70 | { | ||
71 | u32 reg; | ||
72 | |||
73 | @@ -213,22 +214,6 @@ static u32 get_periph_clk(void) | ||
74 | } | ||
75 | |||
76 | /* | ||
77 | - * Get the rate of ahb clock. | ||
78 | - */ | ||
79 | -static u32 get_ahb_clk(void) | ||
80 | -{ | ||
81 | - uint32_t freq, div, reg; | ||
82 | - | ||
83 | - freq = get_periph_clk(); | ||
84 | - | ||
85 | - reg = __raw_readl(&mxc_ccm->cbcdr); | ||
86 | - div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> | ||
87 | - MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; | ||
88 | - | ||
89 | - return freq / div; | ||
90 | -} | ||
91 | - | ||
92 | -/* | ||
93 | * Get the rate of ipg clock. | ||
94 | */ | ||
95 | static u32 get_ipg_clk(void) | ||
96 | diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c | ||
97 | index ef98563..0f05432 100644 | ||
98 | --- a/arch/arm/cpu/armv7/mx6/clock.c | ||
99 | +++ b/arch/arm/cpu/armv7/mx6/clock.c | ||
100 | @@ -24,8 +24,9 @@ | ||
101 | #include <asm/io.h> | ||
102 | #include <asm/errno.h> | ||
103 | #include <asm/arch/imx-regs.h> | ||
104 | -#include <asm/arch/ccm_regs.h> | ||
105 | +#include <asm/arch/crm_regs.h> | ||
106 | #include <asm/arch/clock.h> | ||
107 | +#include <asm/arch/sys_proto.h> | ||
108 | |||
109 | enum pll_clocks { | ||
110 | PLL_SYS, /* System PLL */ | ||
111 | @@ -34,7 +35,7 @@ enum pll_clocks { | ||
112 | PLL_ENET, /* ENET PLL */ | ||
113 | }; | ||
114 | |||
115 | -struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR; | ||
116 | +struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | ||
117 | |||
118 | void enable_usboh3_clk(unsigned char enable) | ||
119 | { | ||
120 | @@ -92,7 +93,7 @@ static u32 get_mcu_main_clk(void) | ||
121 | return freq / (reg + 1); | ||
122 | } | ||
123 | |||
124 | -static u32 get_periph_clk(void) | ||
125 | +u32 get_periph_clk(void) | ||
126 | { | ||
127 | u32 reg, freq = 0; | ||
128 | |||
129 | @@ -139,18 +140,6 @@ static u32 get_periph_clk(void) | ||
130 | return freq; | ||
131 | } | ||
132 | |||
133 | - | ||
134 | -static u32 get_ahb_clk(void) | ||
135 | -{ | ||
136 | - u32 reg, ahb_podf; | ||
137 | - | ||
138 | - reg = __raw_readl(&imx_ccm->cbcdr); | ||
139 | - reg &= MXC_CCM_CBCDR_AHB_PODF_MASK; | ||
140 | - ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET; | ||
141 | - | ||
142 | - return get_periph_clk() / (ahb_podf + 1); | ||
143 | -} | ||
144 | - | ||
145 | static u32 get_ipg_clk(void) | ||
146 | { | ||
147 | u32 reg, ipg_podf; | ||
148 | diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h | ||
149 | index 13d12ee..3f10d29 100644 | ||
150 | --- a/arch/arm/include/asm/arch-mx5/sys_proto.h | ||
151 | +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h | ||
152 | @@ -35,5 +35,7 @@ void set_chipselect_size(int const); | ||
153 | */ | ||
154 | |||
155 | int fecmxc_initialize(bd_t *bis); | ||
156 | +u32 get_ahb_clk(void); | ||
157 | +u32 get_periph_clk(void); | ||
158 | |||
159 | #endif | ||
160 | diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/ccm_regs.h | ||
161 | deleted file mode 100644 | ||
162 | index 4af0b90..0000000 | ||
163 | --- a/arch/arm/include/asm/arch-mx6/ccm_regs.h | ||
164 | +++ /dev/null | ||
165 | @@ -1,892 +0,0 @@ | ||
166 | -/* | ||
167 | - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
168 | - * | ||
169 | - * This program is free software; you can redistribute it and/or modify | ||
170 | - * it under the terms of the GNU General Public License as published by | ||
171 | - * the Free Software Foundation; either version 2 of the License, or | ||
172 | - * (at your option) any later version. | ||
173 | - * | ||
174 | - * This program is distributed in the hope that it will be useful, | ||
175 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
176 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
177 | - * GNU General Public License for more details. | ||
178 | - * | ||
179 | - * You should have received a copy of the GNU General Public License | ||
180 | - * along with this program; if not, write to the Free Software | ||
181 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
182 | - * | ||
183 | - */ | ||
184 | - | ||
185 | -#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ | ||
186 | -#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ | ||
187 | - | ||
188 | -struct imx_ccm_reg { | ||
189 | - u32 ccr; /* 0x0000 */ | ||
190 | - u32 ccdr; | ||
191 | - u32 csr; | ||
192 | - u32 ccsr; | ||
193 | - u32 cacrr; /* 0x0010*/ | ||
194 | - u32 cbcdr; | ||
195 | - u32 cbcmr; | ||
196 | - u32 cscmr1; | ||
197 | - u32 cscmr2; /* 0x0020 */ | ||
198 | - u32 cscdr1; | ||
199 | - u32 cs1cdr; | ||
200 | - u32 cs2cdr; | ||
201 | - u32 cdcdr; /* 0x0030 */ | ||
202 | - u32 chscdr; | ||
203 | - u32 cscdr2; | ||
204 | - u32 cscdr3; | ||
205 | - u32 cscdr4; /* 0x0040 */ | ||
206 | - u32 resv0; | ||
207 | - u32 cdhipr; | ||
208 | - u32 cdcr; | ||
209 | - u32 ctor; /* 0x0050 */ | ||
210 | - u32 clpcr; | ||
211 | - u32 cisr; | ||
212 | - u32 cimr; | ||
213 | - u32 ccosr; /* 0x0060 */ | ||
214 | - u32 cgpr; | ||
215 | - u32 CCGR0; | ||
216 | - u32 CCGR1; | ||
217 | - u32 CCGR2; /* 0x0070 */ | ||
218 | - u32 CCGR3; | ||
219 | - u32 CCGR4; | ||
220 | - u32 CCGR5; | ||
221 | - u32 CCGR6; /* 0x0080 */ | ||
222 | - u32 CCGR7; | ||
223 | - u32 cmeor; | ||
224 | - u32 resv[0xfdd]; | ||
225 | - u32 analog_pll_sys; /* 0x4000 */ | ||
226 | - u32 analog_pll_sys_set; | ||
227 | - u32 analog_pll_sys_clr; | ||
228 | - u32 analog_pll_sys_tog; | ||
229 | - u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ | ||
230 | - u32 analog_usb1_pll_480_ctrl_set; | ||
231 | - u32 analog_usb1_pll_480_ctrl_clr; | ||
232 | - u32 analog_usb1_pll_480_ctrl_tog; | ||
233 | - u32 analog_reserved0[4]; | ||
234 | - u32 analog_pll_528; /* 0x4030 */ | ||
235 | - u32 analog_pll_528_set; | ||
236 | - u32 analog_pll_528_clr; | ||
237 | - u32 analog_pll_528_tog; | ||
238 | - u32 analog_pll_528_ss; /* 0x4040 */ | ||
239 | - u32 analog_reserved1[3]; | ||
240 | - u32 analog_pll_528_num; /* 0x4050 */ | ||
241 | - u32 analog_reserved2[3]; | ||
242 | - u32 analog_pll_528_denom; /* 0x4060 */ | ||
243 | - u32 analog_reserved3[3]; | ||
244 | - u32 analog_pll_audio; /* 0x4070 */ | ||
245 | - u32 analog_pll_audio_set; | ||
246 | - u32 analog_pll_audio_clr; | ||
247 | - u32 analog_pll_audio_tog; | ||
248 | - u32 analog_pll_audio_num; /* 0x4080*/ | ||
249 | - u32 analog_reserved4[3]; | ||
250 | - u32 analog_pll_audio_denom; /* 0x4090 */ | ||
251 | - u32 analog_reserved5[3]; | ||
252 | - u32 analog_pll_video; /* 0x40a0 */ | ||
253 | - u32 analog_pll_video_set; | ||
254 | - u32 analog_pll_video_clr; | ||
255 | - u32 analog_pll_video_tog; | ||
256 | - u32 analog_pll_video_num; /* 0x40b0 */ | ||
257 | - u32 analog_reserved6[3]; | ||
258 | - u32 analog_pll_vedio_denon; /* 0x40c0 */ | ||
259 | - u32 analog_reserved7[7]; | ||
260 | - u32 analog_pll_enet; /* 0x40e0 */ | ||
261 | - u32 analog_pll_enet_set; | ||
262 | - u32 analog_pll_enet_clr; | ||
263 | - u32 analog_pll_enet_tog; | ||
264 | - u32 analog_pfd_480; /* 0x40f0 */ | ||
265 | - u32 analog_pfd_480_set; | ||
266 | - u32 analog_pfd_480_clr; | ||
267 | - u32 analog_pfd_480_tog; | ||
268 | - u32 analog_pfd_528; /* 0x4100 */ | ||
269 | - u32 analog_pfd_528_set; | ||
270 | - u32 analog_pfd_528_clr; | ||
271 | - u32 analog_pfd_528_tog; | ||
272 | -}; | ||
273 | - | ||
274 | -/* Define the bits in register CCR */ | ||
275 | -#define MXC_CCM_CCR_RBC_EN (1 << 27) | ||
276 | -#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) | ||
277 | -#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 | ||
278 | -#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 | ||
279 | -#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) | ||
280 | -#define MXC_CCM_CCR_COSC_EN (1 << 12) | ||
281 | -#define MXC_CCM_CCR_OSCNT_MASK 0xFF | ||
282 | -#define MXC_CCM_CCR_OSCNT_OFFSET 0 | ||
283 | - | ||
284 | -/* Define the bits in register CCDR */ | ||
285 | -#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) | ||
286 | -#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) | ||
287 | - | ||
288 | -/* Define the bits in register CSR */ | ||
289 | -#define MXC_CCM_CSR_COSC_READY (1 << 5) | ||
290 | -#define MXC_CCM_CSR_REF_EN_B (1 << 0) | ||
291 | - | ||
292 | -/* Define the bits in register CCSR */ | ||
293 | -#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) | ||
294 | -#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) | ||
295 | -#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) | ||
296 | -#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) | ||
297 | -#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) | ||
298 | -#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) | ||
299 | -#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) | ||
300 | -#define MXC_CCM_CCSR_STEP_SEL (1 << 8) | ||
301 | -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) | ||
302 | -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) | ||
303 | -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) | ||
304 | - | ||
305 | -/* Define the bits in register CACRR */ | ||
306 | -#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 | ||
307 | -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 | ||
308 | - | ||
309 | -/* Define the bits in register CBCDR */ | ||
310 | -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) | ||
311 | -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 | ||
312 | -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) | ||
313 | -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) | ||
314 | -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) | ||
315 | -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 | ||
316 | -#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) | ||
317 | -#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 | ||
318 | -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) | ||
319 | -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 | ||
320 | -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) | ||
321 | -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 | ||
322 | -#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) | ||
323 | -#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) | ||
324 | -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) | ||
325 | -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 | ||
326 | -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) | ||
327 | -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 | ||
328 | - | ||
329 | -/* Define the bits in register CBCMR */ | ||
330 | -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) | ||
331 | -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 | ||
332 | -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) | ||
333 | -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 | ||
334 | -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) | ||
335 | -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 | ||
336 | -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) | ||
337 | -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 | ||
338 | -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) | ||
339 | -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) | ||
340 | -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 | ||
341 | -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) | ||
342 | -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 | ||
343 | -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) | ||
344 | -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 | ||
345 | -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) | ||
346 | -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 | ||
347 | -#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) | ||
348 | -#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) | ||
349 | -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) | ||
350 | -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 | ||
351 | -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) | ||
352 | -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 | ||
353 | -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) | ||
354 | -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) | ||
355 | - | ||
356 | -/* Define the bits in register CSCMR1 */ | ||
357 | -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) | ||
358 | -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 | ||
359 | -#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) | ||
360 | -#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 | ||
361 | -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) | ||
362 | -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 | ||
363 | -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) | ||
364 | -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 | ||
365 | -#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) | ||
366 | -#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) | ||
367 | -#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) | ||
368 | -#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) | ||
369 | -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) | ||
370 | -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 | ||
371 | -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) | ||
372 | -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 | ||
373 | -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) | ||
374 | -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 | ||
375 | -#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F | ||
376 | - | ||
377 | -/* Define the bits in register CSCMR2 */ | ||
378 | -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) | ||
379 | -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 | ||
380 | -#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) | ||
381 | -#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) | ||
382 | -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) | ||
383 | -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 | ||
384 | - | ||
385 | -/* Define the bits in register CSCDR1 */ | ||
386 | -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) | ||
387 | -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 | ||
388 | -#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) | ||
389 | -#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 | ||
390 | -#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) | ||
391 | -#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 | ||
392 | -#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) | ||
393 | -#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 | ||
394 | -#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) | ||
395 | -#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 | ||
396 | -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 | ||
397 | -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) | ||
398 | -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 | ||
399 | -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) | ||
400 | -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F | ||
401 | -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 | ||
402 | - | ||
403 | -/* Define the bits in register CS1CDR */ | ||
404 | -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) | ||
405 | -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 | ||
406 | -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) | ||
407 | -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 | ||
408 | -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) | ||
409 | -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 | ||
410 | -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) | ||
411 | -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 | ||
412 | -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F | ||
413 | -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 | ||
414 | - | ||
415 | -/* Define the bits in register CS2CDR */ | ||
416 | -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) | ||
417 | -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 | ||
418 | -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) | ||
419 | -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 | ||
420 | -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) | ||
421 | -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 | ||
422 | -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) | ||
423 | -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 | ||
424 | -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) | ||
425 | -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 | ||
426 | -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) | ||
427 | -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 | ||
428 | -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F | ||
429 | -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 | ||
430 | - | ||
431 | -/* Define the bits in register CDCDR */ | ||
432 | -#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) | ||
433 | -#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 | ||
434 | -#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) | ||
435 | -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) | ||
436 | -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 | ||
437 | -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) | ||
438 | -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 | ||
439 | -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) | ||
440 | -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 | ||
441 | -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) | ||
442 | -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 | ||
443 | -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) | ||
444 | -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 | ||
445 | -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) | ||
446 | -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 | ||
447 | - | ||
448 | -/* Define the bits in register CHSCCDR */ | ||
449 | -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) | ||
450 | -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 | ||
451 | -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) | ||
452 | -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 | ||
453 | -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) | ||
454 | -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 | ||
455 | -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) | ||
456 | -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 | ||
457 | -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) | ||
458 | -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 | ||
459 | -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) | ||
460 | -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 | ||
461 | - | ||
462 | -/* Define the bits in register CSCDR2 */ | ||
463 | -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) | ||
464 | -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 | ||
465 | -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) | ||
466 | -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 | ||
467 | -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) | ||
468 | -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 | ||
469 | -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) | ||
470 | -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 | ||
471 | -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) | ||
472 | -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 | ||
473 | -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) | ||
474 | -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 | ||
475 | -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 | ||
476 | -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 | ||
477 | - | ||
478 | -/* Define the bits in register CSCDR3 */ | ||
479 | -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) | ||
480 | -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 | ||
481 | -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) | ||
482 | -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 | ||
483 | -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) | ||
484 | -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 | ||
485 | -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) | ||
486 | -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 | ||
487 | - | ||
488 | -/* Define the bits in register CDHIPR */ | ||
489 | -#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) | ||
490 | -#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) | ||
491 | -#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) | ||
492 | -#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) | ||
493 | -#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) | ||
494 | -#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) | ||
495 | -#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 | ||
496 | - | ||
497 | -/* Define the bits in register CLPCR */ | ||
498 | -#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) | ||
499 | -#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) | ||
500 | -#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) | ||
501 | -#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) | ||
502 | -#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) | ||
503 | -#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) | ||
504 | -#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) | ||
505 | -#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) | ||
506 | -#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) | ||
507 | -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) | ||
508 | -#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) | ||
509 | -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) | ||
510 | -#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 | ||
511 | -#define MXC_CCM_CLPCR_VSTBY (1 << 8) | ||
512 | -#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) | ||
513 | -#define MXC_CCM_CLPCR_SBYOS (1 << 6) | ||
514 | -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) | ||
515 | -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) | ||
516 | -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 | ||
517 | -#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) | ||
518 | -#define MXC_CCM_CLPCR_LPM_MASK 0x3 | ||
519 | -#define MXC_CCM_CLPCR_LPM_OFFSET 0 | ||
520 | - | ||
521 | -/* Define the bits in register CISR */ | ||
522 | -#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) | ||
523 | -#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) | ||
524 | -#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) | ||
525 | -#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) | ||
526 | -#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) | ||
527 | -#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) | ||
528 | -#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) | ||
529 | -#define MXC_CCM_CISR_COSC_READY (1 << 6) | ||
530 | -#define MXC_CCM_CISR_LRF_PLL 1 | ||
531 | - | ||
532 | -/* Define the bits in register CIMR */ | ||
533 | -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) | ||
534 | -#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) | ||
535 | -#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) | ||
536 | -#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) | ||
537 | -#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) | ||
538 | -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) | ||
539 | -#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) | ||
540 | -#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) | ||
541 | -#define MXC_CCM_CIMR_MASK_LRF_PLL 1 | ||
542 | - | ||
543 | -/* Define the bits in register CCOSR */ | ||
544 | -#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) | ||
545 | -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) | ||
546 | -#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 | ||
547 | -#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 | ||
548 | -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) | ||
549 | -#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) | ||
550 | -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) | ||
551 | -#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 | ||
552 | -#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF | ||
553 | -#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 | ||
554 | - | ||
555 | -/* Define the bits in registers CGPR */ | ||
556 | -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) | ||
557 | -#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) | ||
558 | -#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 | ||
559 | - | ||
560 | -/* Define the bits in registers CCGRx */ | ||
561 | -#define MXC_CCM_CCGR_CG_MASK 3 | ||
562 | - | ||
563 | -#define MXC_CCM_CCGR0_CG15_OFFSET 30 | ||
564 | -#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) | ||
565 | -#define MXC_CCM_CCGR0_CG14_OFFSET 28 | ||
566 | -#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) | ||
567 | -#define MXC_CCM_CCGR0_CG13_OFFSET 26 | ||
568 | -#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) | ||
569 | -#define MXC_CCM_CCGR0_CG12_OFFSET 24 | ||
570 | -#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) | ||
571 | -#define MXC_CCM_CCGR0_CG11_OFFSET 22 | ||
572 | -#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) | ||
573 | -#define MXC_CCM_CCGR0_CG10_OFFSET 20 | ||
574 | -#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) | ||
575 | -#define MXC_CCM_CCGR0_CG9_OFFSET 18 | ||
576 | -#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) | ||
577 | -#define MXC_CCM_CCGR0_CG8_OFFSET 16 | ||
578 | -#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) | ||
579 | -#define MXC_CCM_CCGR0_CG7_OFFSET 14 | ||
580 | -#define MXC_CCM_CCGR0_CG6_OFFSET 12 | ||
581 | -#define MXC_CCM_CCGR0_CG5_OFFSET 10 | ||
582 | -#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) | ||
583 | -#define MXC_CCM_CCGR0_CG4_OFFSET 8 | ||
584 | -#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) | ||
585 | -#define MXC_CCM_CCGR0_CG3_OFFSET 6 | ||
586 | -#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) | ||
587 | -#define MXC_CCM_CCGR0_CG2_OFFSET 4 | ||
588 | -#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) | ||
589 | -#define MXC_CCM_CCGR0_CG1_OFFSET 2 | ||
590 | -#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) | ||
591 | -#define MXC_CCM_CCGR0_CG0_OFFSET 0 | ||
592 | -#define MXC_CCM_CCGR0_CG0_MASK 3 | ||
593 | - | ||
594 | -#define MXC_CCM_CCGR1_CG15_OFFSET 30 | ||
595 | -#define MXC_CCM_CCGR1_CG14_OFFSET 28 | ||
596 | -#define MXC_CCM_CCGR1_CG13_OFFSET 26 | ||
597 | -#define MXC_CCM_CCGR1_CG12_OFFSET 24 | ||
598 | -#define MXC_CCM_CCGR1_CG11_OFFSET 22 | ||
599 | -#define MXC_CCM_CCGR1_CG10_OFFSET 20 | ||
600 | -#define MXC_CCM_CCGR1_CG9_OFFSET 18 | ||
601 | -#define MXC_CCM_CCGR1_CG8_OFFSET 16 | ||
602 | -#define MXC_CCM_CCGR1_CG7_OFFSET 14 | ||
603 | -#define MXC_CCM_CCGR1_CG6_OFFSET 12 | ||
604 | -#define MXC_CCM_CCGR1_CG5_OFFSET 10 | ||
605 | -#define MXC_CCM_CCGR1_CG4_OFFSET 8 | ||
606 | -#define MXC_CCM_CCGR1_CG3_OFFSET 6 | ||
607 | -#define MXC_CCM_CCGR1_CG2_OFFSET 4 | ||
608 | -#define MXC_CCM_CCGR1_CG1_OFFSET 2 | ||
609 | -#define MXC_CCM_CCGR1_CG0_OFFSET 0 | ||
610 | - | ||
611 | -#define MXC_CCM_CCGR2_CG15_OFFSET 30 | ||
612 | -#define MXC_CCM_CCGR2_CG14_OFFSET 28 | ||
613 | -#define MXC_CCM_CCGR2_CG13_OFFSET 26 | ||
614 | -#define MXC_CCM_CCGR2_CG12_OFFSET 24 | ||
615 | -#define MXC_CCM_CCGR2_CG11_OFFSET 22 | ||
616 | -#define MXC_CCM_CCGR2_CG10_OFFSET 20 | ||
617 | -#define MXC_CCM_CCGR2_CG9_OFFSET 18 | ||
618 | -#define MXC_CCM_CCGR2_CG8_OFFSET 16 | ||
619 | -#define MXC_CCM_CCGR2_CG7_OFFSET 14 | ||
620 | -#define MXC_CCM_CCGR2_CG6_OFFSET 12 | ||
621 | -#define MXC_CCM_CCGR2_CG5_OFFSET 10 | ||
622 | -#define MXC_CCM_CCGR2_CG4_OFFSET 8 | ||
623 | -#define MXC_CCM_CCGR2_CG3_OFFSET 6 | ||
624 | -#define MXC_CCM_CCGR2_CG2_OFFSET 4 | ||
625 | -#define MXC_CCM_CCGR2_CG1_OFFSET 2 | ||
626 | -#define MXC_CCM_CCGR2_CG0_OFFSET 0 | ||
627 | - | ||
628 | -#define MXC_CCM_CCGR3_CG15_OFFSET 30 | ||
629 | -#define MXC_CCM_CCGR3_CG14_OFFSET 28 | ||
630 | -#define MXC_CCM_CCGR3_CG13_OFFSET 26 | ||
631 | -#define MXC_CCM_CCGR3_CG12_OFFSET 24 | ||
632 | -#define MXC_CCM_CCGR3_CG11_OFFSET 22 | ||
633 | -#define MXC_CCM_CCGR3_CG10_OFFSET 20 | ||
634 | -#define MXC_CCM_CCGR3_CG9_OFFSET 18 | ||
635 | -#define MXC_CCM_CCGR3_CG8_OFFSET 16 | ||
636 | -#define MXC_CCM_CCGR3_CG7_OFFSET 14 | ||
637 | -#define MXC_CCM_CCGR3_CG6_OFFSET 12 | ||
638 | -#define MXC_CCM_CCGR3_CG5_OFFSET 10 | ||
639 | -#define MXC_CCM_CCGR3_CG4_OFFSET 8 | ||
640 | -#define MXC_CCM_CCGR3_CG3_OFFSET 6 | ||
641 | -#define MXC_CCM_CCGR3_CG2_OFFSET 4 | ||
642 | -#define MXC_CCM_CCGR3_CG1_OFFSET 2 | ||
643 | -#define MXC_CCM_CCGR3_CG0_OFFSET 0 | ||
644 | - | ||
645 | -#define MXC_CCM_CCGR4_CG15_OFFSET 30 | ||
646 | -#define MXC_CCM_CCGR4_CG14_OFFSET 28 | ||
647 | -#define MXC_CCM_CCGR4_CG13_OFFSET 26 | ||
648 | -#define MXC_CCM_CCGR4_CG12_OFFSET 24 | ||
649 | -#define MXC_CCM_CCGR4_CG11_OFFSET 22 | ||
650 | -#define MXC_CCM_CCGR4_CG10_OFFSET 20 | ||
651 | -#define MXC_CCM_CCGR4_CG9_OFFSET 18 | ||
652 | -#define MXC_CCM_CCGR4_CG8_OFFSET 16 | ||
653 | -#define MXC_CCM_CCGR4_CG7_OFFSET 14 | ||
654 | -#define MXC_CCM_CCGR4_CG6_OFFSET 12 | ||
655 | -#define MXC_CCM_CCGR4_CG5_OFFSET 10 | ||
656 | -#define MXC_CCM_CCGR4_CG4_OFFSET 8 | ||
657 | -#define MXC_CCM_CCGR4_CG3_OFFSET 6 | ||
658 | -#define MXC_CCM_CCGR4_CG2_OFFSET 4 | ||
659 | -#define MXC_CCM_CCGR4_CG1_OFFSET 2 | ||
660 | -#define MXC_CCM_CCGR4_CG0_OFFSET 0 | ||
661 | - | ||
662 | -#define MXC_CCM_CCGR5_CG15_OFFSET 30 | ||
663 | -#define MXC_CCM_CCGR5_CG14_OFFSET 28 | ||
664 | -#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) | ||
665 | -#define MXC_CCM_CCGR5_CG13_OFFSET 26 | ||
666 | -#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) | ||
667 | -#define MXC_CCM_CCGR5_CG12_OFFSET 24 | ||
668 | -#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) | ||
669 | -#define MXC_CCM_CCGR5_CG11_OFFSET 22 | ||
670 | -#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) | ||
671 | -#define MXC_CCM_CCGR5_CG10_OFFSET 20 | ||
672 | -#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) | ||
673 | -#define MXC_CCM_CCGR5_CG9_OFFSET 18 | ||
674 | -#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) | ||
675 | -#define MXC_CCM_CCGR5_CG8_OFFSET 16 | ||
676 | -#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) | ||
677 | -#define MXC_CCM_CCGR5_CG7_OFFSET 14 | ||
678 | -#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) | ||
679 | -#define MXC_CCM_CCGR5_CG6_OFFSET 12 | ||
680 | -#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) | ||
681 | -#define MXC_CCM_CCGR5_CG5_OFFSET 10 | ||
682 | -#define MXC_CCM_CCGR5_CG4_OFFSET 8 | ||
683 | -#define MXC_CCM_CCGR5_CG3_OFFSET 6 | ||
684 | -#define MXC_CCM_CCGR5_CG2_OFFSET 4 | ||
685 | -#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) | ||
686 | -#define MXC_CCM_CCGR5_CG1_OFFSET 2 | ||
687 | -#define MXC_CCM_CCGR5_CG0_OFFSET 0 | ||
688 | - | ||
689 | -#define MXC_CCM_CCGR6_CG15_OFFSET 30 | ||
690 | -#define MXC_CCM_CCGR6_CG14_OFFSET 28 | ||
691 | -#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) | ||
692 | -#define MXC_CCM_CCGR6_CG13_OFFSET 26 | ||
693 | -#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) | ||
694 | -#define MXC_CCM_CCGR6_CG12_OFFSET 24 | ||
695 | -#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) | ||
696 | -#define MXC_CCM_CCGR6_CG11_OFFSET 22 | ||
697 | -#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) | ||
698 | -#define MXC_CCM_CCGR6_CG10_OFFSET 20 | ||
699 | -#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) | ||
700 | -#define MXC_CCM_CCGR6_CG9_OFFSET 18 | ||
701 | -#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) | ||
702 | -#define MXC_CCM_CCGR6_CG8_OFFSET 16 | ||
703 | -#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) | ||
704 | -#define MXC_CCM_CCGR6_CG7_OFFSET 14 | ||
705 | -#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) | ||
706 | -#define MXC_CCM_CCGR6_CG6_OFFSET 12 | ||
707 | -#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) | ||
708 | -#define MXC_CCM_CCGR6_CG5_OFFSET 10 | ||
709 | -#define MXC_CCM_CCGR6_CG4_OFFSET 8 | ||
710 | -#define MXC_CCM_CCGR6_CG3_OFFSET 6 | ||
711 | -#define MXC_CCM_CCGR6_CG2_OFFSET 4 | ||
712 | -#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) | ||
713 | -#define MXC_CCM_CCGR6_CG1_OFFSET 2 | ||
714 | -#define MXC_CCM_CCGR6_CG0_OFFSET 0 | ||
715 | - | ||
716 | -#define MXC_CCM_CCGR7_CG15_OFFSET 30 | ||
717 | -#define MXC_CCM_CCGR7_CG14_OFFSET 28 | ||
718 | -#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) | ||
719 | -#define MXC_CCM_CCGR7_CG13_OFFSET 26 | ||
720 | -#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) | ||
721 | -#define MXC_CCM_CCGR7_CG12_OFFSET 24 | ||
722 | -#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) | ||
723 | -#define MXC_CCM_CCGR7_CG11_OFFSET 22 | ||
724 | -#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) | ||
725 | -#define MXC_CCM_CCGR7_CG10_OFFSET 20 | ||
726 | -#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) | ||
727 | -#define MXC_CCM_CCGR7_CG9_OFFSET 18 | ||
728 | -#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) | ||
729 | -#define MXC_CCM_CCGR7_CG8_OFFSET 16 | ||
730 | -#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) | ||
731 | -#define MXC_CCM_CCGR7_CG7_OFFSET 14 | ||
732 | -#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) | ||
733 | -#define MXC_CCM_CCGR7_CG6_OFFSET 12 | ||
734 | -#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) | ||
735 | -#define MXC_CCM_CCGR7_CG5_OFFSET 10 | ||
736 | -#define MXC_CCM_CCGR7_CG4_OFFSET 8 | ||
737 | -#define MXC_CCM_CCGR7_CG3_OFFSET 6 | ||
738 | -#define MXC_CCM_CCGR7_CG2_OFFSET 4 | ||
739 | -#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) | ||
740 | -#define MXC_CCM_CCGR7_CG1_OFFSET 2 | ||
741 | -#define MXC_CCM_CCGR7_CG0_OFFSET 0 | ||
742 | -#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 | ||
743 | -#define BP_ANADIG_PLL_SYS_RSVD0 20 | ||
744 | -#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 | ||
745 | -#define BF_ANADIG_PLL_SYS_RSVD0(v) \ | ||
746 | - (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) | ||
747 | -#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 | ||
748 | -#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 | ||
749 | -#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 | ||
750 | -#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 | ||
751 | -#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 | ||
752 | -#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 | ||
753 | -#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ | ||
754 | - (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) | ||
755 | -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
756 | -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
757 | -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
758 | -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 | ||
759 | -#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 | ||
760 | -#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 | ||
761 | -#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 | ||
762 | -#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 | ||
763 | -#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 | ||
764 | -#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 | ||
765 | -#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 | ||
766 | -#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 | ||
767 | -#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F | ||
768 | -#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ | ||
769 | - (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) | ||
770 | - | ||
771 | -#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 | ||
772 | -#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 | ||
773 | -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 | ||
774 | -#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ | ||
775 | - (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) | ||
776 | -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 | ||
777 | -#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 | ||
778 | -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 | ||
779 | -#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ | ||
780 | - (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) | ||
781 | -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
782 | -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
783 | -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
784 | -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 | ||
785 | -#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 | ||
786 | -#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 | ||
787 | -#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 | ||
788 | -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 | ||
789 | -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 | ||
790 | -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 | ||
791 | -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 | ||
792 | -#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 | ||
793 | -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 | ||
794 | -#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 | ||
795 | -#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C | ||
796 | -#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ | ||
797 | - (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) | ||
798 | -#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 | ||
799 | -#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 | ||
800 | -#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ | ||
801 | - (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) | ||
802 | - | ||
803 | -#define BM_ANADIG_PLL_528_LOCK 0x80000000 | ||
804 | -#define BP_ANADIG_PLL_528_RSVD1 19 | ||
805 | -#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 | ||
806 | -#define BF_ANADIG_PLL_528_RSVD1(v) \ | ||
807 | - (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) | ||
808 | -#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 | ||
809 | -#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 | ||
810 | -#define BM_ANADIG_PLL_528_BYPASS 0x00010000 | ||
811 | -#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 | ||
812 | -#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 | ||
813 | -#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ | ||
814 | - (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) | ||
815 | -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
816 | -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
817 | -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
818 | -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 | ||
819 | -#define BM_ANADIG_PLL_528_ENABLE 0x00002000 | ||
820 | -#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 | ||
821 | -#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 | ||
822 | -#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 | ||
823 | -#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 | ||
824 | -#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 | ||
825 | -#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 | ||
826 | -#define BP_ANADIG_PLL_528_RSVD0 1 | ||
827 | -#define BM_ANADIG_PLL_528_RSVD0 0x0000007E | ||
828 | -#define BF_ANADIG_PLL_528_RSVD0(v) \ | ||
829 | - (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) | ||
830 | -#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 | ||
831 | - | ||
832 | -#define BP_ANADIG_PLL_528_SS_STOP 16 | ||
833 | -#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 | ||
834 | -#define BF_ANADIG_PLL_528_SS_STOP(v) \ | ||
835 | - (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) | ||
836 | -#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 | ||
837 | -#define BP_ANADIG_PLL_528_SS_STEP 0 | ||
838 | -#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF | ||
839 | -#define BF_ANADIG_PLL_528_SS_STEP(v) \ | ||
840 | - (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) | ||
841 | - | ||
842 | -#define BP_ANADIG_PLL_528_NUM_RSVD0 30 | ||
843 | -#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 | ||
844 | -#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ | ||
845 | - (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) | ||
846 | -#define BP_ANADIG_PLL_528_NUM_A 0 | ||
847 | -#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF | ||
848 | -#define BF_ANADIG_PLL_528_NUM_A(v) \ | ||
849 | - (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) | ||
850 | - | ||
851 | -#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 | ||
852 | -#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 | ||
853 | -#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ | ||
854 | - (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) | ||
855 | -#define BP_ANADIG_PLL_528_DENOM_B 0 | ||
856 | -#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF | ||
857 | -#define BF_ANADIG_PLL_528_DENOM_B(v) \ | ||
858 | - (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) | ||
859 | - | ||
860 | -#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 | ||
861 | -#define BP_ANADIG_PLL_AUDIO_RSVD0 22 | ||
862 | -#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 | ||
863 | -#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ | ||
864 | - (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) | ||
865 | -#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 | ||
866 | -#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 | ||
867 | -#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 | ||
868 | -#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ | ||
869 | - (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) | ||
870 | -#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 | ||
871 | -#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 | ||
872 | -#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 | ||
873 | -#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 | ||
874 | -#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 | ||
875 | -#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ | ||
876 | - (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) | ||
877 | -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
878 | -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
879 | -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
880 | -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 | ||
881 | -#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 | ||
882 | -#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 | ||
883 | -#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 | ||
884 | -#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 | ||
885 | -#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 | ||
886 | -#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 | ||
887 | -#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 | ||
888 | -#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 | ||
889 | -#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F | ||
890 | -#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ | ||
891 | - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) | ||
892 | - | ||
893 | -#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 | ||
894 | -#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 | ||
895 | -#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ | ||
896 | - (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) | ||
897 | -#define BP_ANADIG_PLL_AUDIO_NUM_A 0 | ||
898 | -#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF | ||
899 | -#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ | ||
900 | - (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) | ||
901 | - | ||
902 | -#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 | ||
903 | -#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 | ||
904 | -#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ | ||
905 | - (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) | ||
906 | -#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 | ||
907 | -#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF | ||
908 | -#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ | ||
909 | - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) | ||
910 | - | ||
911 | -#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 | ||
912 | -#define BP_ANADIG_PLL_VIDEO_RSVD0 22 | ||
913 | -#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 | ||
914 | -#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ | ||
915 | - (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) | ||
916 | -#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 | ||
917 | -#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 | ||
918 | -#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 | ||
919 | -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ | ||
920 | - (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) | ||
921 | -#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 | ||
922 | -#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 | ||
923 | -#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 | ||
924 | -#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 | ||
925 | -#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 | ||
926 | -#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ | ||
927 | - (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) | ||
928 | -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
929 | -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
930 | -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
931 | -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 | ||
932 | -#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 | ||
933 | -#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 | ||
934 | -#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 | ||
935 | -#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 | ||
936 | -#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 | ||
937 | -#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 | ||
938 | -#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 | ||
939 | -#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 | ||
940 | -#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F | ||
941 | -#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ | ||
942 | - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) | ||
943 | - | ||
944 | -#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 | ||
945 | -#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 | ||
946 | -#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ | ||
947 | - (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) | ||
948 | -#define BP_ANADIG_PLL_VIDEO_NUM_A 0 | ||
949 | -#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF | ||
950 | -#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ | ||
951 | - (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) | ||
952 | - | ||
953 | -#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 | ||
954 | -#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 | ||
955 | -#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ | ||
956 | - (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) | ||
957 | -#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 | ||
958 | -#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF | ||
959 | -#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ | ||
960 | - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) | ||
961 | - | ||
962 | -#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 | ||
963 | -#define BP_ANADIG_PLL_ENET_RSVD1 21 | ||
964 | -#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 | ||
965 | -#define BF_ANADIG_PLL_ENET_RSVD1(v) \ | ||
966 | - (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) | ||
967 | -#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 | ||
968 | -#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 | ||
969 | -#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 | ||
970 | -#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 | ||
971 | -#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 | ||
972 | -#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 | ||
973 | -#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 | ||
974 | -#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ | ||
975 | - (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) | ||
976 | -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
977 | -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
978 | -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
979 | -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 | ||
980 | -#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 | ||
981 | -#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 | ||
982 | -#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 | ||
983 | -#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 | ||
984 | -#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 | ||
985 | -#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 | ||
986 | -#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 | ||
987 | -#define BP_ANADIG_PLL_ENET_RSVD0 2 | ||
988 | -#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C | ||
989 | -#define BF_ANADIG_PLL_ENET_RSVD0(v) \ | ||
990 | - (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) | ||
991 | -#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 | ||
992 | -#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 | ||
993 | -#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ | ||
994 | - (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) | ||
995 | - | ||
996 | -#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 | ||
997 | -#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 | ||
998 | -#define BP_ANADIG_PFD_480_PFD3_FRAC 24 | ||
999 | -#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 | ||
1000 | -#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ | ||
1001 | - (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) | ||
1002 | -#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 | ||
1003 | -#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 | ||
1004 | -#define BP_ANADIG_PFD_480_PFD2_FRAC 16 | ||
1005 | -#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 | ||
1006 | -#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ | ||
1007 | - (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) | ||
1008 | -#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 | ||
1009 | -#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 | ||
1010 | -#define BP_ANADIG_PFD_480_PFD1_FRAC 8 | ||
1011 | -#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 | ||
1012 | -#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ | ||
1013 | - (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) | ||
1014 | -#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 | ||
1015 | -#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 | ||
1016 | -#define BP_ANADIG_PFD_480_PFD0_FRAC 0 | ||
1017 | -#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F | ||
1018 | -#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ | ||
1019 | - (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) | ||
1020 | - | ||
1021 | -#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 | ||
1022 | -#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 | ||
1023 | -#define BP_ANADIG_PFD_528_PFD3_FRAC 24 | ||
1024 | -#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 | ||
1025 | -#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ | ||
1026 | - (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) | ||
1027 | -#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 | ||
1028 | -#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 | ||
1029 | -#define BP_ANADIG_PFD_528_PFD2_FRAC 16 | ||
1030 | -#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 | ||
1031 | -#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ | ||
1032 | - (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) | ||
1033 | -#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 | ||
1034 | -#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 | ||
1035 | -#define BP_ANADIG_PFD_528_PFD1_FRAC 8 | ||
1036 | -#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 | ||
1037 | -#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ | ||
1038 | - (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) | ||
1039 | -#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 | ||
1040 | -#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 | ||
1041 | -#define BP_ANADIG_PFD_528_PFD0_FRAC 0 | ||
1042 | -#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F | ||
1043 | -#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ | ||
1044 | - (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) | ||
1045 | - | ||
1046 | -#define PLL2_PFD0_FREQ 352000000 | ||
1047 | -#define PLL2_PFD1_FREQ 594000000 | ||
1048 | -#define PLL2_PFD2_FREQ 400000000 | ||
1049 | -#define PLL2_PFD2_DIV_FREQ 200000000 | ||
1050 | -#define PLL3_PFD0_FREQ 720000000 | ||
1051 | -#define PLL3_PFD1_FREQ 540000000 | ||
1052 | -#define PLL3_PFD2_FREQ 508200000 | ||
1053 | -#define PLL3_PFD3_FREQ 454700000 | ||
1054 | -#define PLL3_80M 80000000 | ||
1055 | -#define PLL3_60M 60000000 | ||
1056 | - | ||
1057 | -#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ | ||
1058 | diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h | ||
1059 | new file mode 100644 | ||
1060 | index 0000000..0e605c2 | ||
1061 | --- /dev/null | ||
1062 | +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h | ||
1063 | @@ -0,0 +1,892 @@ | ||
1064 | +/* | ||
1065 | + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
1066 | + * | ||
1067 | + * This program is free software; you can redistribute it and/or modify | ||
1068 | + * it under the terms of the GNU General Public License as published by | ||
1069 | + * the Free Software Foundation; either version 2 of the License, or | ||
1070 | + * (at your option) any later version. | ||
1071 | + * | ||
1072 | + * This program is distributed in the hope that it will be useful, | ||
1073 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
1074 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
1075 | + * GNU General Public License for more details. | ||
1076 | + * | ||
1077 | + * You should have received a copy of the GNU General Public License | ||
1078 | + * along with this program; if not, write to the Free Software | ||
1079 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
1080 | + * | ||
1081 | + */ | ||
1082 | + | ||
1083 | +#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ | ||
1084 | +#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ | ||
1085 | + | ||
1086 | +struct mxc_ccm_reg { | ||
1087 | + u32 ccr; /* 0x0000 */ | ||
1088 | + u32 ccdr; | ||
1089 | + u32 csr; | ||
1090 | + u32 ccsr; | ||
1091 | + u32 cacrr; /* 0x0010*/ | ||
1092 | + u32 cbcdr; | ||
1093 | + u32 cbcmr; | ||
1094 | + u32 cscmr1; | ||
1095 | + u32 cscmr2; /* 0x0020 */ | ||
1096 | + u32 cscdr1; | ||
1097 | + u32 cs1cdr; | ||
1098 | + u32 cs2cdr; | ||
1099 | + u32 cdcdr; /* 0x0030 */ | ||
1100 | + u32 chscdr; | ||
1101 | + u32 cscdr2; | ||
1102 | + u32 cscdr3; | ||
1103 | + u32 cscdr4; /* 0x0040 */ | ||
1104 | + u32 resv0; | ||
1105 | + u32 cdhipr; | ||
1106 | + u32 cdcr; | ||
1107 | + u32 ctor; /* 0x0050 */ | ||
1108 | + u32 clpcr; | ||
1109 | + u32 cisr; | ||
1110 | + u32 cimr; | ||
1111 | + u32 ccosr; /* 0x0060 */ | ||
1112 | + u32 cgpr; | ||
1113 | + u32 CCGR0; | ||
1114 | + u32 CCGR1; | ||
1115 | + u32 CCGR2; /* 0x0070 */ | ||
1116 | + u32 CCGR3; | ||
1117 | + u32 CCGR4; | ||
1118 | + u32 CCGR5; | ||
1119 | + u32 CCGR6; /* 0x0080 */ | ||
1120 | + u32 CCGR7; | ||
1121 | + u32 cmeor; | ||
1122 | + u32 resv[0xfdd]; | ||
1123 | + u32 analog_pll_sys; /* 0x4000 */ | ||
1124 | + u32 analog_pll_sys_set; | ||
1125 | + u32 analog_pll_sys_clr; | ||
1126 | + u32 analog_pll_sys_tog; | ||
1127 | + u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ | ||
1128 | + u32 analog_usb1_pll_480_ctrl_set; | ||
1129 | + u32 analog_usb1_pll_480_ctrl_clr; | ||
1130 | + u32 analog_usb1_pll_480_ctrl_tog; | ||
1131 | + u32 analog_reserved0[4]; | ||
1132 | + u32 analog_pll_528; /* 0x4030 */ | ||
1133 | + u32 analog_pll_528_set; | ||
1134 | + u32 analog_pll_528_clr; | ||
1135 | + u32 analog_pll_528_tog; | ||
1136 | + u32 analog_pll_528_ss; /* 0x4040 */ | ||
1137 | + u32 analog_reserved1[3]; | ||
1138 | + u32 analog_pll_528_num; /* 0x4050 */ | ||
1139 | + u32 analog_reserved2[3]; | ||
1140 | + u32 analog_pll_528_denom; /* 0x4060 */ | ||
1141 | + u32 analog_reserved3[3]; | ||
1142 | + u32 analog_pll_audio; /* 0x4070 */ | ||
1143 | + u32 analog_pll_audio_set; | ||
1144 | + u32 analog_pll_audio_clr; | ||
1145 | + u32 analog_pll_audio_tog; | ||
1146 | + u32 analog_pll_audio_num; /* 0x4080*/ | ||
1147 | + u32 analog_reserved4[3]; | ||
1148 | + u32 analog_pll_audio_denom; /* 0x4090 */ | ||
1149 | + u32 analog_reserved5[3]; | ||
1150 | + u32 analog_pll_video; /* 0x40a0 */ | ||
1151 | + u32 analog_pll_video_set; | ||
1152 | + u32 analog_pll_video_clr; | ||
1153 | + u32 analog_pll_video_tog; | ||
1154 | + u32 analog_pll_video_num; /* 0x40b0 */ | ||
1155 | + u32 analog_reserved6[3]; | ||
1156 | + u32 analog_pll_vedio_denon; /* 0x40c0 */ | ||
1157 | + u32 analog_reserved7[7]; | ||
1158 | + u32 analog_pll_enet; /* 0x40e0 */ | ||
1159 | + u32 analog_pll_enet_set; | ||
1160 | + u32 analog_pll_enet_clr; | ||
1161 | + u32 analog_pll_enet_tog; | ||
1162 | + u32 analog_pfd_480; /* 0x40f0 */ | ||
1163 | + u32 analog_pfd_480_set; | ||
1164 | + u32 analog_pfd_480_clr; | ||
1165 | + u32 analog_pfd_480_tog; | ||
1166 | + u32 analog_pfd_528; /* 0x4100 */ | ||
1167 | + u32 analog_pfd_528_set; | ||
1168 | + u32 analog_pfd_528_clr; | ||
1169 | + u32 analog_pfd_528_tog; | ||
1170 | +}; | ||
1171 | + | ||
1172 | +/* Define the bits in register CCR */ | ||
1173 | +#define MXC_CCM_CCR_RBC_EN (1 << 27) | ||
1174 | +#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) | ||
1175 | +#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 | ||
1176 | +#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 | ||
1177 | +#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) | ||
1178 | +#define MXC_CCM_CCR_COSC_EN (1 << 12) | ||
1179 | +#define MXC_CCM_CCR_OSCNT_MASK 0xFF | ||
1180 | +#define MXC_CCM_CCR_OSCNT_OFFSET 0 | ||
1181 | + | ||
1182 | +/* Define the bits in register CCDR */ | ||
1183 | +#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) | ||
1184 | +#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) | ||
1185 | + | ||
1186 | +/* Define the bits in register CSR */ | ||
1187 | +#define MXC_CCM_CSR_COSC_READY (1 << 5) | ||
1188 | +#define MXC_CCM_CSR_REF_EN_B (1 << 0) | ||
1189 | + | ||
1190 | +/* Define the bits in register CCSR */ | ||
1191 | +#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) | ||
1192 | +#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) | ||
1193 | +#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) | ||
1194 | +#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) | ||
1195 | +#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) | ||
1196 | +#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) | ||
1197 | +#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) | ||
1198 | +#define MXC_CCM_CCSR_STEP_SEL (1 << 8) | ||
1199 | +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) | ||
1200 | +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) | ||
1201 | +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) | ||
1202 | + | ||
1203 | +/* Define the bits in register CACRR */ | ||
1204 | +#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 | ||
1205 | +#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 | ||
1206 | + | ||
1207 | +/* Define the bits in register CBCDR */ | ||
1208 | +#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) | ||
1209 | +#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 | ||
1210 | +#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) | ||
1211 | +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) | ||
1212 | +#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) | ||
1213 | +#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 | ||
1214 | +#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) | ||
1215 | +#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 | ||
1216 | +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) | ||
1217 | +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 | ||
1218 | +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) | ||
1219 | +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 | ||
1220 | +#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) | ||
1221 | +#define MXC_CCM_CBCDR_AXI_SEL (1 << 6) | ||
1222 | +#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) | ||
1223 | +#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 | ||
1224 | +#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) | ||
1225 | +#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 | ||
1226 | + | ||
1227 | +/* Define the bits in register CBCMR */ | ||
1228 | +#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) | ||
1229 | +#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 | ||
1230 | +#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) | ||
1231 | +#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 | ||
1232 | +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) | ||
1233 | +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 | ||
1234 | +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) | ||
1235 | +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 | ||
1236 | +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) | ||
1237 | +#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) | ||
1238 | +#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 | ||
1239 | +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) | ||
1240 | +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 | ||
1241 | +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) | ||
1242 | +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 | ||
1243 | +#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) | ||
1244 | +#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 | ||
1245 | +#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) | ||
1246 | +#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) | ||
1247 | +#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) | ||
1248 | +#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 | ||
1249 | +#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) | ||
1250 | +#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 | ||
1251 | +#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) | ||
1252 | +#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) | ||
1253 | + | ||
1254 | +/* Define the bits in register CSCMR1 */ | ||
1255 | +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) | ||
1256 | +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 | ||
1257 | +#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) | ||
1258 | +#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 | ||
1259 | +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) | ||
1260 | +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 | ||
1261 | +#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) | ||
1262 | +#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 | ||
1263 | +#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) | ||
1264 | +#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) | ||
1265 | +#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) | ||
1266 | +#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) | ||
1267 | +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) | ||
1268 | +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 | ||
1269 | +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) | ||
1270 | +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 | ||
1271 | +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) | ||
1272 | +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 | ||
1273 | +#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F | ||
1274 | + | ||
1275 | +/* Define the bits in register CSCMR2 */ | ||
1276 | +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) | ||
1277 | +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 | ||
1278 | +#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) | ||
1279 | +#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) | ||
1280 | +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) | ||
1281 | +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 | ||
1282 | + | ||
1283 | +/* Define the bits in register CSCDR1 */ | ||
1284 | +#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) | ||
1285 | +#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 | ||
1286 | +#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) | ||
1287 | +#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 | ||
1288 | +#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) | ||
1289 | +#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 | ||
1290 | +#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) | ||
1291 | +#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 | ||
1292 | +#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) | ||
1293 | +#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 | ||
1294 | +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 | ||
1295 | +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) | ||
1296 | +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 | ||
1297 | +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) | ||
1298 | +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F | ||
1299 | +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 | ||
1300 | + | ||
1301 | +/* Define the bits in register CS1CDR */ | ||
1302 | +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) | ||
1303 | +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 | ||
1304 | +#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) | ||
1305 | +#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 | ||
1306 | +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) | ||
1307 | +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 | ||
1308 | +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) | ||
1309 | +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 | ||
1310 | +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F | ||
1311 | +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 | ||
1312 | + | ||
1313 | +/* Define the bits in register CS2CDR */ | ||
1314 | +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) | ||
1315 | +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 | ||
1316 | +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) | ||
1317 | +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 | ||
1318 | +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) | ||
1319 | +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 | ||
1320 | +#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) | ||
1321 | +#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 | ||
1322 | +#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) | ||
1323 | +#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 | ||
1324 | +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) | ||
1325 | +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 | ||
1326 | +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F | ||
1327 | +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 | ||
1328 | + | ||
1329 | +/* Define the bits in register CDCDR */ | ||
1330 | +#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) | ||
1331 | +#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 | ||
1332 | +#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) | ||
1333 | +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) | ||
1334 | +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 | ||
1335 | +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) | ||
1336 | +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 | ||
1337 | +#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) | ||
1338 | +#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 | ||
1339 | +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) | ||
1340 | +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 | ||
1341 | +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) | ||
1342 | +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 | ||
1343 | +#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) | ||
1344 | +#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 | ||
1345 | + | ||
1346 | +/* Define the bits in register CHSCCDR */ | ||
1347 | +#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) | ||
1348 | +#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 | ||
1349 | +#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) | ||
1350 | +#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 | ||
1351 | +#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) | ||
1352 | +#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 | ||
1353 | +#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) | ||
1354 | +#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 | ||
1355 | +#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) | ||
1356 | +#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 | ||
1357 | +#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) | ||
1358 | +#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 | ||
1359 | + | ||
1360 | +/* Define the bits in register CSCDR2 */ | ||
1361 | +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) | ||
1362 | +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 | ||
1363 | +#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) | ||
1364 | +#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 | ||
1365 | +#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) | ||
1366 | +#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 | ||
1367 | +#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) | ||
1368 | +#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 | ||
1369 | +#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) | ||
1370 | +#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 | ||
1371 | +#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) | ||
1372 | +#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 | ||
1373 | +#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 | ||
1374 | +#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 | ||
1375 | + | ||
1376 | +/* Define the bits in register CSCDR3 */ | ||
1377 | +#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) | ||
1378 | +#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 | ||
1379 | +#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) | ||
1380 | +#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 | ||
1381 | +#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) | ||
1382 | +#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 | ||
1383 | +#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) | ||
1384 | +#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 | ||
1385 | + | ||
1386 | +/* Define the bits in register CDHIPR */ | ||
1387 | +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) | ||
1388 | +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) | ||
1389 | +#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) | ||
1390 | +#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) | ||
1391 | +#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) | ||
1392 | +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) | ||
1393 | +#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 | ||
1394 | + | ||
1395 | +/* Define the bits in register CLPCR */ | ||
1396 | +#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) | ||
1397 | +#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) | ||
1398 | +#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) | ||
1399 | +#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) | ||
1400 | +#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) | ||
1401 | +#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) | ||
1402 | +#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) | ||
1403 | +#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) | ||
1404 | +#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) | ||
1405 | +#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) | ||
1406 | +#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) | ||
1407 | +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) | ||
1408 | +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 | ||
1409 | +#define MXC_CCM_CLPCR_VSTBY (1 << 8) | ||
1410 | +#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) | ||
1411 | +#define MXC_CCM_CLPCR_SBYOS (1 << 6) | ||
1412 | +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) | ||
1413 | +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) | ||
1414 | +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 | ||
1415 | +#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) | ||
1416 | +#define MXC_CCM_CLPCR_LPM_MASK 0x3 | ||
1417 | +#define MXC_CCM_CLPCR_LPM_OFFSET 0 | ||
1418 | + | ||
1419 | +/* Define the bits in register CISR */ | ||
1420 | +#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) | ||
1421 | +#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) | ||
1422 | +#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) | ||
1423 | +#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) | ||
1424 | +#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) | ||
1425 | +#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) | ||
1426 | +#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) | ||
1427 | +#define MXC_CCM_CISR_COSC_READY (1 << 6) | ||
1428 | +#define MXC_CCM_CISR_LRF_PLL 1 | ||
1429 | + | ||
1430 | +/* Define the bits in register CIMR */ | ||
1431 | +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) | ||
1432 | +#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) | ||
1433 | +#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) | ||
1434 | +#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) | ||
1435 | +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) | ||
1436 | +#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) | ||
1437 | +#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) | ||
1438 | +#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) | ||
1439 | +#define MXC_CCM_CIMR_MASK_LRF_PLL 1 | ||
1440 | + | ||
1441 | +/* Define the bits in register CCOSR */ | ||
1442 | +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) | ||
1443 | +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) | ||
1444 | +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 | ||
1445 | +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 | ||
1446 | +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) | ||
1447 | +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) | ||
1448 | +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) | ||
1449 | +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 | ||
1450 | +#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF | ||
1451 | +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 | ||
1452 | + | ||
1453 | +/* Define the bits in registers CGPR */ | ||
1454 | +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) | ||
1455 | +#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) | ||
1456 | +#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 | ||
1457 | + | ||
1458 | +/* Define the bits in registers CCGRx */ | ||
1459 | +#define MXC_CCM_CCGR_CG_MASK 3 | ||
1460 | + | ||
1461 | +#define MXC_CCM_CCGR0_CG15_OFFSET 30 | ||
1462 | +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) | ||
1463 | +#define MXC_CCM_CCGR0_CG14_OFFSET 28 | ||
1464 | +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) | ||
1465 | +#define MXC_CCM_CCGR0_CG13_OFFSET 26 | ||
1466 | +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) | ||
1467 | +#define MXC_CCM_CCGR0_CG12_OFFSET 24 | ||
1468 | +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) | ||
1469 | +#define MXC_CCM_CCGR0_CG11_OFFSET 22 | ||
1470 | +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) | ||
1471 | +#define MXC_CCM_CCGR0_CG10_OFFSET 20 | ||
1472 | +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) | ||
1473 | +#define MXC_CCM_CCGR0_CG9_OFFSET 18 | ||
1474 | +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) | ||
1475 | +#define MXC_CCM_CCGR0_CG8_OFFSET 16 | ||
1476 | +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) | ||
1477 | +#define MXC_CCM_CCGR0_CG7_OFFSET 14 | ||
1478 | +#define MXC_CCM_CCGR0_CG6_OFFSET 12 | ||
1479 | +#define MXC_CCM_CCGR0_CG5_OFFSET 10 | ||
1480 | +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) | ||
1481 | +#define MXC_CCM_CCGR0_CG4_OFFSET 8 | ||
1482 | +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) | ||
1483 | +#define MXC_CCM_CCGR0_CG3_OFFSET 6 | ||
1484 | +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) | ||
1485 | +#define MXC_CCM_CCGR0_CG2_OFFSET 4 | ||
1486 | +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) | ||
1487 | +#define MXC_CCM_CCGR0_CG1_OFFSET 2 | ||
1488 | +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) | ||
1489 | +#define MXC_CCM_CCGR0_CG0_OFFSET 0 | ||
1490 | +#define MXC_CCM_CCGR0_CG0_MASK 3 | ||
1491 | + | ||
1492 | +#define MXC_CCM_CCGR1_CG15_OFFSET 30 | ||
1493 | +#define MXC_CCM_CCGR1_CG14_OFFSET 28 | ||
1494 | +#define MXC_CCM_CCGR1_CG13_OFFSET 26 | ||
1495 | +#define MXC_CCM_CCGR1_CG12_OFFSET 24 | ||
1496 | +#define MXC_CCM_CCGR1_CG11_OFFSET 22 | ||
1497 | +#define MXC_CCM_CCGR1_CG10_OFFSET 20 | ||
1498 | +#define MXC_CCM_CCGR1_CG9_OFFSET 18 | ||
1499 | +#define MXC_CCM_CCGR1_CG8_OFFSET 16 | ||
1500 | +#define MXC_CCM_CCGR1_CG7_OFFSET 14 | ||
1501 | +#define MXC_CCM_CCGR1_CG6_OFFSET 12 | ||
1502 | +#define MXC_CCM_CCGR1_CG5_OFFSET 10 | ||
1503 | +#define MXC_CCM_CCGR1_CG4_OFFSET 8 | ||
1504 | +#define MXC_CCM_CCGR1_CG3_OFFSET 6 | ||
1505 | +#define MXC_CCM_CCGR1_CG2_OFFSET 4 | ||
1506 | +#define MXC_CCM_CCGR1_CG1_OFFSET 2 | ||
1507 | +#define MXC_CCM_CCGR1_CG0_OFFSET 0 | ||
1508 | + | ||
1509 | +#define MXC_CCM_CCGR2_CG15_OFFSET 30 | ||
1510 | +#define MXC_CCM_CCGR2_CG14_OFFSET 28 | ||
1511 | +#define MXC_CCM_CCGR2_CG13_OFFSET 26 | ||
1512 | +#define MXC_CCM_CCGR2_CG12_OFFSET 24 | ||
1513 | +#define MXC_CCM_CCGR2_CG11_OFFSET 22 | ||
1514 | +#define MXC_CCM_CCGR2_CG10_OFFSET 20 | ||
1515 | +#define MXC_CCM_CCGR2_CG9_OFFSET 18 | ||
1516 | +#define MXC_CCM_CCGR2_CG8_OFFSET 16 | ||
1517 | +#define MXC_CCM_CCGR2_CG7_OFFSET 14 | ||
1518 | +#define MXC_CCM_CCGR2_CG6_OFFSET 12 | ||
1519 | +#define MXC_CCM_CCGR2_CG5_OFFSET 10 | ||
1520 | +#define MXC_CCM_CCGR2_CG4_OFFSET 8 | ||
1521 | +#define MXC_CCM_CCGR2_CG3_OFFSET 6 | ||
1522 | +#define MXC_CCM_CCGR2_CG2_OFFSET 4 | ||
1523 | +#define MXC_CCM_CCGR2_CG1_OFFSET 2 | ||
1524 | +#define MXC_CCM_CCGR2_CG0_OFFSET 0 | ||
1525 | + | ||
1526 | +#define MXC_CCM_CCGR3_CG15_OFFSET 30 | ||
1527 | +#define MXC_CCM_CCGR3_CG14_OFFSET 28 | ||
1528 | +#define MXC_CCM_CCGR3_CG13_OFFSET 26 | ||
1529 | +#define MXC_CCM_CCGR3_CG12_OFFSET 24 | ||
1530 | +#define MXC_CCM_CCGR3_CG11_OFFSET 22 | ||
1531 | +#define MXC_CCM_CCGR3_CG10_OFFSET 20 | ||
1532 | +#define MXC_CCM_CCGR3_CG9_OFFSET 18 | ||
1533 | +#define MXC_CCM_CCGR3_CG8_OFFSET 16 | ||
1534 | +#define MXC_CCM_CCGR3_CG7_OFFSET 14 | ||
1535 | +#define MXC_CCM_CCGR3_CG6_OFFSET 12 | ||
1536 | +#define MXC_CCM_CCGR3_CG5_OFFSET 10 | ||
1537 | +#define MXC_CCM_CCGR3_CG4_OFFSET 8 | ||
1538 | +#define MXC_CCM_CCGR3_CG3_OFFSET 6 | ||
1539 | +#define MXC_CCM_CCGR3_CG2_OFFSET 4 | ||
1540 | +#define MXC_CCM_CCGR3_CG1_OFFSET 2 | ||
1541 | +#define MXC_CCM_CCGR3_CG0_OFFSET 0 | ||
1542 | + | ||
1543 | +#define MXC_CCM_CCGR4_CG15_OFFSET 30 | ||
1544 | +#define MXC_CCM_CCGR4_CG14_OFFSET 28 | ||
1545 | +#define MXC_CCM_CCGR4_CG13_OFFSET 26 | ||
1546 | +#define MXC_CCM_CCGR4_CG12_OFFSET 24 | ||
1547 | +#define MXC_CCM_CCGR4_CG11_OFFSET 22 | ||
1548 | +#define MXC_CCM_CCGR4_CG10_OFFSET 20 | ||
1549 | +#define MXC_CCM_CCGR4_CG9_OFFSET 18 | ||
1550 | +#define MXC_CCM_CCGR4_CG8_OFFSET 16 | ||
1551 | +#define MXC_CCM_CCGR4_CG7_OFFSET 14 | ||
1552 | +#define MXC_CCM_CCGR4_CG6_OFFSET 12 | ||
1553 | +#define MXC_CCM_CCGR4_CG5_OFFSET 10 | ||
1554 | +#define MXC_CCM_CCGR4_CG4_OFFSET 8 | ||
1555 | +#define MXC_CCM_CCGR4_CG3_OFFSET 6 | ||
1556 | +#define MXC_CCM_CCGR4_CG2_OFFSET 4 | ||
1557 | +#define MXC_CCM_CCGR4_CG1_OFFSET 2 | ||
1558 | +#define MXC_CCM_CCGR4_CG0_OFFSET 0 | ||
1559 | + | ||
1560 | +#define MXC_CCM_CCGR5_CG15_OFFSET 30 | ||
1561 | +#define MXC_CCM_CCGR5_CG14_OFFSET 28 | ||
1562 | +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) | ||
1563 | +#define MXC_CCM_CCGR5_CG13_OFFSET 26 | ||
1564 | +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) | ||
1565 | +#define MXC_CCM_CCGR5_CG12_OFFSET 24 | ||
1566 | +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) | ||
1567 | +#define MXC_CCM_CCGR5_CG11_OFFSET 22 | ||
1568 | +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) | ||
1569 | +#define MXC_CCM_CCGR5_CG10_OFFSET 20 | ||
1570 | +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) | ||
1571 | +#define MXC_CCM_CCGR5_CG9_OFFSET 18 | ||
1572 | +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) | ||
1573 | +#define MXC_CCM_CCGR5_CG8_OFFSET 16 | ||
1574 | +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) | ||
1575 | +#define MXC_CCM_CCGR5_CG7_OFFSET 14 | ||
1576 | +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) | ||
1577 | +#define MXC_CCM_CCGR5_CG6_OFFSET 12 | ||
1578 | +#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) | ||
1579 | +#define MXC_CCM_CCGR5_CG5_OFFSET 10 | ||
1580 | +#define MXC_CCM_CCGR5_CG4_OFFSET 8 | ||
1581 | +#define MXC_CCM_CCGR5_CG3_OFFSET 6 | ||
1582 | +#define MXC_CCM_CCGR5_CG2_OFFSET 4 | ||
1583 | +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) | ||
1584 | +#define MXC_CCM_CCGR5_CG1_OFFSET 2 | ||
1585 | +#define MXC_CCM_CCGR5_CG0_OFFSET 0 | ||
1586 | + | ||
1587 | +#define MXC_CCM_CCGR6_CG15_OFFSET 30 | ||
1588 | +#define MXC_CCM_CCGR6_CG14_OFFSET 28 | ||
1589 | +#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) | ||
1590 | +#define MXC_CCM_CCGR6_CG13_OFFSET 26 | ||
1591 | +#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) | ||
1592 | +#define MXC_CCM_CCGR6_CG12_OFFSET 24 | ||
1593 | +#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) | ||
1594 | +#define MXC_CCM_CCGR6_CG11_OFFSET 22 | ||
1595 | +#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) | ||
1596 | +#define MXC_CCM_CCGR6_CG10_OFFSET 20 | ||
1597 | +#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) | ||
1598 | +#define MXC_CCM_CCGR6_CG9_OFFSET 18 | ||
1599 | +#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) | ||
1600 | +#define MXC_CCM_CCGR6_CG8_OFFSET 16 | ||
1601 | +#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) | ||
1602 | +#define MXC_CCM_CCGR6_CG7_OFFSET 14 | ||
1603 | +#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) | ||
1604 | +#define MXC_CCM_CCGR6_CG6_OFFSET 12 | ||
1605 | +#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) | ||
1606 | +#define MXC_CCM_CCGR6_CG5_OFFSET 10 | ||
1607 | +#define MXC_CCM_CCGR6_CG4_OFFSET 8 | ||
1608 | +#define MXC_CCM_CCGR6_CG3_OFFSET 6 | ||
1609 | +#define MXC_CCM_CCGR6_CG2_OFFSET 4 | ||
1610 | +#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) | ||
1611 | +#define MXC_CCM_CCGR6_CG1_OFFSET 2 | ||
1612 | +#define MXC_CCM_CCGR6_CG0_OFFSET 0 | ||
1613 | + | ||
1614 | +#define MXC_CCM_CCGR7_CG15_OFFSET 30 | ||
1615 | +#define MXC_CCM_CCGR7_CG14_OFFSET 28 | ||
1616 | +#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) | ||
1617 | +#define MXC_CCM_CCGR7_CG13_OFFSET 26 | ||
1618 | +#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) | ||
1619 | +#define MXC_CCM_CCGR7_CG12_OFFSET 24 | ||
1620 | +#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) | ||
1621 | +#define MXC_CCM_CCGR7_CG11_OFFSET 22 | ||
1622 | +#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) | ||
1623 | +#define MXC_CCM_CCGR7_CG10_OFFSET 20 | ||
1624 | +#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) | ||
1625 | +#define MXC_CCM_CCGR7_CG9_OFFSET 18 | ||
1626 | +#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) | ||
1627 | +#define MXC_CCM_CCGR7_CG8_OFFSET 16 | ||
1628 | +#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) | ||
1629 | +#define MXC_CCM_CCGR7_CG7_OFFSET 14 | ||
1630 | +#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) | ||
1631 | +#define MXC_CCM_CCGR7_CG6_OFFSET 12 | ||
1632 | +#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) | ||
1633 | +#define MXC_CCM_CCGR7_CG5_OFFSET 10 | ||
1634 | +#define MXC_CCM_CCGR7_CG4_OFFSET 8 | ||
1635 | +#define MXC_CCM_CCGR7_CG3_OFFSET 6 | ||
1636 | +#define MXC_CCM_CCGR7_CG2_OFFSET 4 | ||
1637 | +#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) | ||
1638 | +#define MXC_CCM_CCGR7_CG1_OFFSET 2 | ||
1639 | +#define MXC_CCM_CCGR7_CG0_OFFSET 0 | ||
1640 | +#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 | ||
1641 | +#define BP_ANADIG_PLL_SYS_RSVD0 20 | ||
1642 | +#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 | ||
1643 | +#define BF_ANADIG_PLL_SYS_RSVD0(v) \ | ||
1644 | + (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) | ||
1645 | +#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 | ||
1646 | +#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 | ||
1647 | +#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 | ||
1648 | +#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 | ||
1649 | +#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 | ||
1650 | +#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 | ||
1651 | +#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ | ||
1652 | + (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) | ||
1653 | +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
1654 | +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
1655 | +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
1656 | +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 | ||
1657 | +#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 | ||
1658 | +#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 | ||
1659 | +#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 | ||
1660 | +#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 | ||
1661 | +#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 | ||
1662 | +#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 | ||
1663 | +#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 | ||
1664 | +#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 | ||
1665 | +#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F | ||
1666 | +#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ | ||
1667 | + (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) | ||
1668 | + | ||
1669 | +#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 | ||
1670 | +#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 | ||
1671 | +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 | ||
1672 | +#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ | ||
1673 | + (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) | ||
1674 | +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 | ||
1675 | +#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 | ||
1676 | +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 | ||
1677 | +#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ | ||
1678 | + (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) | ||
1679 | +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
1680 | +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
1681 | +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
1682 | +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 | ||
1683 | +#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 | ||
1684 | +#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 | ||
1685 | +#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 | ||
1686 | +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 | ||
1687 | +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 | ||
1688 | +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 | ||
1689 | +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 | ||
1690 | +#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 | ||
1691 | +#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 | ||
1692 | +#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 | ||
1693 | +#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C | ||
1694 | +#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ | ||
1695 | + (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) | ||
1696 | +#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 | ||
1697 | +#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 | ||
1698 | +#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ | ||
1699 | + (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) | ||
1700 | + | ||
1701 | +#define BM_ANADIG_PLL_528_LOCK 0x80000000 | ||
1702 | +#define BP_ANADIG_PLL_528_RSVD1 19 | ||
1703 | +#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 | ||
1704 | +#define BF_ANADIG_PLL_528_RSVD1(v) \ | ||
1705 | + (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) | ||
1706 | +#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 | ||
1707 | +#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 | ||
1708 | +#define BM_ANADIG_PLL_528_BYPASS 0x00010000 | ||
1709 | +#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 | ||
1710 | +#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 | ||
1711 | +#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ | ||
1712 | + (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) | ||
1713 | +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
1714 | +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
1715 | +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
1716 | +#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 | ||
1717 | +#define BM_ANADIG_PLL_528_ENABLE 0x00002000 | ||
1718 | +#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 | ||
1719 | +#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 | ||
1720 | +#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 | ||
1721 | +#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 | ||
1722 | +#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 | ||
1723 | +#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 | ||
1724 | +#define BP_ANADIG_PLL_528_RSVD0 1 | ||
1725 | +#define BM_ANADIG_PLL_528_RSVD0 0x0000007E | ||
1726 | +#define BF_ANADIG_PLL_528_RSVD0(v) \ | ||
1727 | + (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) | ||
1728 | +#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 | ||
1729 | + | ||
1730 | +#define BP_ANADIG_PLL_528_SS_STOP 16 | ||
1731 | +#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 | ||
1732 | +#define BF_ANADIG_PLL_528_SS_STOP(v) \ | ||
1733 | + (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) | ||
1734 | +#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 | ||
1735 | +#define BP_ANADIG_PLL_528_SS_STEP 0 | ||
1736 | +#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF | ||
1737 | +#define BF_ANADIG_PLL_528_SS_STEP(v) \ | ||
1738 | + (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) | ||
1739 | + | ||
1740 | +#define BP_ANADIG_PLL_528_NUM_RSVD0 30 | ||
1741 | +#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 | ||
1742 | +#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ | ||
1743 | + (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) | ||
1744 | +#define BP_ANADIG_PLL_528_NUM_A 0 | ||
1745 | +#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF | ||
1746 | +#define BF_ANADIG_PLL_528_NUM_A(v) \ | ||
1747 | + (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) | ||
1748 | + | ||
1749 | +#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 | ||
1750 | +#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 | ||
1751 | +#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ | ||
1752 | + (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) | ||
1753 | +#define BP_ANADIG_PLL_528_DENOM_B 0 | ||
1754 | +#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF | ||
1755 | +#define BF_ANADIG_PLL_528_DENOM_B(v) \ | ||
1756 | + (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) | ||
1757 | + | ||
1758 | +#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 | ||
1759 | +#define BP_ANADIG_PLL_AUDIO_RSVD0 22 | ||
1760 | +#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 | ||
1761 | +#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ | ||
1762 | + (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) | ||
1763 | +#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 | ||
1764 | +#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 | ||
1765 | +#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 | ||
1766 | +#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ | ||
1767 | + (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) | ||
1768 | +#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 | ||
1769 | +#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 | ||
1770 | +#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 | ||
1771 | +#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 | ||
1772 | +#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 | ||
1773 | +#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ | ||
1774 | + (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) | ||
1775 | +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
1776 | +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
1777 | +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
1778 | +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 | ||
1779 | +#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 | ||
1780 | +#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 | ||
1781 | +#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 | ||
1782 | +#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 | ||
1783 | +#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 | ||
1784 | +#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 | ||
1785 | +#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 | ||
1786 | +#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 | ||
1787 | +#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F | ||
1788 | +#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ | ||
1789 | + (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) | ||
1790 | + | ||
1791 | +#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 | ||
1792 | +#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 | ||
1793 | +#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ | ||
1794 | + (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) | ||
1795 | +#define BP_ANADIG_PLL_AUDIO_NUM_A 0 | ||
1796 | +#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF | ||
1797 | +#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ | ||
1798 | + (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) | ||
1799 | + | ||
1800 | +#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 | ||
1801 | +#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 | ||
1802 | +#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ | ||
1803 | + (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) | ||
1804 | +#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 | ||
1805 | +#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF | ||
1806 | +#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ | ||
1807 | + (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) | ||
1808 | + | ||
1809 | +#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 | ||
1810 | +#define BP_ANADIG_PLL_VIDEO_RSVD0 22 | ||
1811 | +#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 | ||
1812 | +#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ | ||
1813 | + (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) | ||
1814 | +#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 | ||
1815 | +#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 | ||
1816 | +#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 | ||
1817 | +#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ | ||
1818 | + (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) | ||
1819 | +#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 | ||
1820 | +#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 | ||
1821 | +#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 | ||
1822 | +#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 | ||
1823 | +#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 | ||
1824 | +#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ | ||
1825 | + (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) | ||
1826 | +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
1827 | +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
1828 | +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
1829 | +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 | ||
1830 | +#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 | ||
1831 | +#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 | ||
1832 | +#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 | ||
1833 | +#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 | ||
1834 | +#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 | ||
1835 | +#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 | ||
1836 | +#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 | ||
1837 | +#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 | ||
1838 | +#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F | ||
1839 | +#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ | ||
1840 | + (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) | ||
1841 | + | ||
1842 | +#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 | ||
1843 | +#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 | ||
1844 | +#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ | ||
1845 | + (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) | ||
1846 | +#define BP_ANADIG_PLL_VIDEO_NUM_A 0 | ||
1847 | +#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF | ||
1848 | +#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ | ||
1849 | + (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) | ||
1850 | + | ||
1851 | +#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 | ||
1852 | +#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 | ||
1853 | +#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ | ||
1854 | + (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) | ||
1855 | +#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 | ||
1856 | +#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF | ||
1857 | +#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ | ||
1858 | + (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) | ||
1859 | + | ||
1860 | +#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 | ||
1861 | +#define BP_ANADIG_PLL_ENET_RSVD1 21 | ||
1862 | +#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 | ||
1863 | +#define BF_ANADIG_PLL_ENET_RSVD1(v) \ | ||
1864 | + (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) | ||
1865 | +#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 | ||
1866 | +#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 | ||
1867 | +#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 | ||
1868 | +#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 | ||
1869 | +#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 | ||
1870 | +#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 | ||
1871 | +#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 | ||
1872 | +#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ | ||
1873 | + (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) | ||
1874 | +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 | ||
1875 | +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 | ||
1876 | +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 | ||
1877 | +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 | ||
1878 | +#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 | ||
1879 | +#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 | ||
1880 | +#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 | ||
1881 | +#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 | ||
1882 | +#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 | ||
1883 | +#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 | ||
1884 | +#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 | ||
1885 | +#define BP_ANADIG_PLL_ENET_RSVD0 2 | ||
1886 | +#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C | ||
1887 | +#define BF_ANADIG_PLL_ENET_RSVD0(v) \ | ||
1888 | + (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) | ||
1889 | +#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 | ||
1890 | +#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 | ||
1891 | +#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ | ||
1892 | + (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) | ||
1893 | + | ||
1894 | +#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 | ||
1895 | +#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 | ||
1896 | +#define BP_ANADIG_PFD_480_PFD3_FRAC 24 | ||
1897 | +#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 | ||
1898 | +#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ | ||
1899 | + (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) | ||
1900 | +#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 | ||
1901 | +#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 | ||
1902 | +#define BP_ANADIG_PFD_480_PFD2_FRAC 16 | ||
1903 | +#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 | ||
1904 | +#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ | ||
1905 | + (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) | ||
1906 | +#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 | ||
1907 | +#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 | ||
1908 | +#define BP_ANADIG_PFD_480_PFD1_FRAC 8 | ||
1909 | +#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 | ||
1910 | +#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ | ||
1911 | + (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) | ||
1912 | +#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 | ||
1913 | +#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 | ||
1914 | +#define BP_ANADIG_PFD_480_PFD0_FRAC 0 | ||
1915 | +#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F | ||
1916 | +#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ | ||
1917 | + (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) | ||
1918 | + | ||
1919 | +#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 | ||
1920 | +#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 | ||
1921 | +#define BP_ANADIG_PFD_528_PFD3_FRAC 24 | ||
1922 | +#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 | ||
1923 | +#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ | ||
1924 | + (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) | ||
1925 | +#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 | ||
1926 | +#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 | ||
1927 | +#define BP_ANADIG_PFD_528_PFD2_FRAC 16 | ||
1928 | +#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 | ||
1929 | +#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ | ||
1930 | + (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) | ||
1931 | +#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 | ||
1932 | +#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 | ||
1933 | +#define BP_ANADIG_PFD_528_PFD1_FRAC 8 | ||
1934 | +#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 | ||
1935 | +#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ | ||
1936 | + (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) | ||
1937 | +#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 | ||
1938 | +#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 | ||
1939 | +#define BP_ANADIG_PFD_528_PFD0_FRAC 0 | ||
1940 | +#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F | ||
1941 | +#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ | ||
1942 | + (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) | ||
1943 | + | ||
1944 | +#define PLL2_PFD0_FREQ 352000000 | ||
1945 | +#define PLL2_PFD1_FREQ 594000000 | ||
1946 | +#define PLL2_PFD2_FREQ 400000000 | ||
1947 | +#define PLL2_PFD2_DIV_FREQ 200000000 | ||
1948 | +#define PLL3_PFD0_FREQ 720000000 | ||
1949 | +#define PLL3_PFD1_FREQ 540000000 | ||
1950 | +#define PLL3_PFD2_FREQ 508200000 | ||
1951 | +#define PLL3_PFD3_FREQ 454700000 | ||
1952 | +#define PLL3_80M 80000000 | ||
1953 | +#define PLL3_60M 60000000 | ||
1954 | + | ||
1955 | +#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ | ||
1956 | diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h | ||
1957 | index 668e77a..69687a8 100644 | ||
1958 | --- a/arch/arm/include/asm/arch-mx6/sys_proto.h | ||
1959 | +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h | ||
1960 | @@ -34,5 +34,6 @@ u32 get_cpu_rev(void); | ||
1961 | */ | ||
1962 | |||
1963 | int fecmxc_initialize(bd_t *bis); | ||
1964 | - | ||
1965 | +u32 get_ahb_clk(void); | ||
1966 | +u32 get_periph_clk(void); | ||
1967 | #endif | ||
1968 | -- | ||
1969 | 1.7.10 | ||
1970 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0017-mx5-Add-clock-config-interface.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0017-mx5-Add-clock-config-interface.patch deleted file mode 100644 index a995502..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0017-mx5-Add-clock-config-interface.patch +++ /dev/null | |||
@@ -1,574 +0,0 @@ | |||
1 | From a835391f8dddc9ca51c880e5328979577cb0685d Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <festevam@gmail.com> | ||
3 | Date: Mon, 30 Apr 2012 08:12:02 +0000 | ||
4 | Subject: [PATCH 17/56] mx5: Add clock config interface | ||
5 | |||
6 | mx5: Add clock config interface | ||
7 | |||
8 | Add clock config interface support, so that we | ||
9 | can configure CPU or DDR clock in the later init | ||
10 | |||
11 | Signed-off-by: Jason Liu <jason.hui@linaro.org> | ||
12 | Signed-off-by: Eric Miao <eric.miao@linaro.org> | ||
13 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
14 | --- | ||
15 | arch/arm/cpu/armv7/mx5/clock.c | 448 +++++++++++++++++++++++++++++- | ||
16 | arch/arm/include/asm/arch-mx5/clock.h | 5 +- | ||
17 | arch/arm/include/asm/arch-mx5/crm_regs.h | 6 + | ||
18 | 3 files changed, 454 insertions(+), 5 deletions(-) | ||
19 | |||
20 | diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c | ||
21 | index 903e207..fc2406b 100644 | ||
22 | --- a/arch/arm/cpu/armv7/mx5/clock.c | ||
23 | +++ b/arch/arm/cpu/armv7/mx5/clock.c | ||
24 | @@ -49,6 +49,42 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { | ||
25 | #endif | ||
26 | }; | ||
27 | |||
28 | +#define AHB_CLK_ROOT 133333333 | ||
29 | +#define SZ_DEC_1M 1000000 | ||
30 | +#define PLL_PD_MAX 16 /* Actual pd+1 */ | ||
31 | +#define PLL_MFI_MAX 15 | ||
32 | +#define PLL_MFI_MIN 5 | ||
33 | +#define ARM_DIV_MAX 8 | ||
34 | +#define IPG_DIV_MAX 4 | ||
35 | +#define AHB_DIV_MAX 8 | ||
36 | +#define EMI_DIV_MAX 8 | ||
37 | +#define NFC_DIV_MAX 8 | ||
38 | + | ||
39 | +#define MX5_CBCMR 0x00015154 | ||
40 | +#define MX5_CBCDR 0x02888945 | ||
41 | + | ||
42 | +struct fixed_pll_mfd { | ||
43 | + u32 ref_clk_hz; | ||
44 | + u32 mfd; | ||
45 | +}; | ||
46 | + | ||
47 | +const struct fixed_pll_mfd fixed_mfd[] = { | ||
48 | + {CONFIG_SYS_MX5_HCLK, 24 * 16}, | ||
49 | +}; | ||
50 | + | ||
51 | +struct pll_param { | ||
52 | + u32 pd; | ||
53 | + u32 mfi; | ||
54 | + u32 mfn; | ||
55 | + u32 mfd; | ||
56 | +}; | ||
57 | + | ||
58 | +#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) | ||
59 | +#define PLL_FREQ_MIN(ref_clk) \ | ||
60 | + ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) | ||
61 | +#define MAX_DDR_CLK 420000000 | ||
62 | +#define NFC_CLK_MAX 34000000 | ||
63 | + | ||
64 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; | ||
65 | |||
66 | void set_usboh3_clk(void) | ||
67 | @@ -291,7 +327,7 @@ static u32 get_uart_clk(void) | ||
68 | /* | ||
69 | * This function returns the low power audio clock. | ||
70 | */ | ||
71 | -u32 get_lp_apm(void) | ||
72 | +static u32 get_lp_apm(void) | ||
73 | { | ||
74 | u32 ret_val = 0; | ||
75 | u32 ccsr = __raw_readl(&mxc_ccm->ccsr); | ||
76 | @@ -307,7 +343,7 @@ u32 get_lp_apm(void) | ||
77 | /* | ||
78 | * get cspi clock rate. | ||
79 | */ | ||
80 | -u32 imx_get_cspiclk(void) | ||
81 | +static u32 imx_get_cspiclk(void) | ||
82 | { | ||
83 | u32 ret_val = 0, pdf, pre_pdf, clk_sel; | ||
84 | u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); | ||
85 | @@ -344,8 +380,77 @@ u32 imx_get_cspiclk(void) | ||
86 | return ret_val; | ||
87 | } | ||
88 | |||
89 | +static u32 get_axi_a_clk(void) | ||
90 | +{ | ||
91 | + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); | ||
92 | + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \ | ||
93 | + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; | ||
94 | + | ||
95 | + return get_periph_clk() / (pdf + 1); | ||
96 | +} | ||
97 | + | ||
98 | +static u32 get_axi_b_clk(void) | ||
99 | +{ | ||
100 | + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); | ||
101 | + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \ | ||
102 | + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; | ||
103 | + | ||
104 | + return get_periph_clk() / (pdf + 1); | ||
105 | +} | ||
106 | + | ||
107 | +static u32 get_emi_slow_clk(void) | ||
108 | +{ | ||
109 | + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); | ||
110 | + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; | ||
111 | + u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \ | ||
112 | + >> MXC_CCM_CBCDR_EMI_PODF_OFFSET; | ||
113 | + | ||
114 | + if (emi_clk_sel) | ||
115 | + return get_ahb_clk() / (pdf + 1); | ||
116 | + | ||
117 | + return get_periph_clk() / (pdf + 1); | ||
118 | +} | ||
119 | + | ||
120 | +static u32 get_ddr_clk(void) | ||
121 | +{ | ||
122 | + u32 ret_val = 0; | ||
123 | + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); | ||
124 | + u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \ | ||
125 | + >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; | ||
126 | +#ifdef CONFIG_MX51 | ||
127 | + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); | ||
128 | + if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { | ||
129 | + u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \ | ||
130 | + MXC_CCM_CBCDR_DDR_PODF_OFFSET; | ||
131 | + | ||
132 | + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); | ||
133 | + ret_val /= ddr_clk_podf + 1; | ||
134 | + | ||
135 | + return ret_val; | ||
136 | + } | ||
137 | +#endif | ||
138 | + switch (ddr_clk_sel) { | ||
139 | + case 0: | ||
140 | + ret_val = get_axi_a_clk(); | ||
141 | + break; | ||
142 | + case 1: | ||
143 | + ret_val = get_axi_b_clk(); | ||
144 | + break; | ||
145 | + case 2: | ||
146 | + ret_val = get_emi_slow_clk(); | ||
147 | + break; | ||
148 | + case 3: | ||
149 | + ret_val = get_ahb_clk(); | ||
150 | + break; | ||
151 | + default: | ||
152 | + break; | ||
153 | + } | ||
154 | + | ||
155 | + return ret_val; | ||
156 | +} | ||
157 | + | ||
158 | /* | ||
159 | - * The API of get mxc clockes. | ||
160 | + * The API of get mxc clocks. | ||
161 | */ | ||
162 | unsigned int mxc_get_clock(enum mxc_clock clk) | ||
163 | { | ||
164 | @@ -367,10 +472,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) | ||
165 | CONFIG_SYS_MX5_HCLK); | ||
166 | case MXC_SATA_CLK: | ||
167 | return get_ahb_clk(); | ||
168 | + case MXC_DDR_CLK: | ||
169 | + return get_ddr_clk(); | ||
170 | default: | ||
171 | break; | ||
172 | } | ||
173 | - return -1; | ||
174 | + return -EINVAL; | ||
175 | } | ||
176 | |||
177 | u32 imx_get_uartclk(void) | ||
178 | @@ -384,6 +491,338 @@ u32 imx_get_fecclk(void) | ||
179 | return mxc_get_clock(MXC_IPG_CLK); | ||
180 | } | ||
181 | |||
182 | +static int gcd(int m, int n) | ||
183 | +{ | ||
184 | + int t; | ||
185 | + while (m > 0) { | ||
186 | + if (n > m) { | ||
187 | + t = m; | ||
188 | + m = n; | ||
189 | + n = t; | ||
190 | + } /* swap */ | ||
191 | + m -= n; | ||
192 | + } | ||
193 | + return n; | ||
194 | +} | ||
195 | + | ||
196 | +/* | ||
197 | + * This is to calculate various parameters based on reference clock and | ||
198 | + * targeted clock based on the equation: | ||
199 | + * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) | ||
200 | + * This calculation is based on a fixed MFD value for simplicity. | ||
201 | + */ | ||
202 | +static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) | ||
203 | +{ | ||
204 | + u64 pd, mfi = 1, mfn, mfd, t1; | ||
205 | + u32 n_target = target; | ||
206 | + u32 n_ref = ref, i; | ||
207 | + | ||
208 | + /* | ||
209 | + * Make sure targeted freq is in the valid range. | ||
210 | + * Otherwise the following calculation might be wrong!!! | ||
211 | + */ | ||
212 | + if (n_target < PLL_FREQ_MIN(ref) || | ||
213 | + n_target > PLL_FREQ_MAX(ref)) { | ||
214 | + printf("Targeted peripheral clock should be" | ||
215 | + "within [%d - %d]\n", | ||
216 | + PLL_FREQ_MIN(ref) / SZ_DEC_1M, | ||
217 | + PLL_FREQ_MAX(ref) / SZ_DEC_1M); | ||
218 | + return -EINVAL; | ||
219 | + } | ||
220 | + | ||
221 | + for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { | ||
222 | + if (fixed_mfd[i].ref_clk_hz == ref) { | ||
223 | + mfd = fixed_mfd[i].mfd; | ||
224 | + break; | ||
225 | + } | ||
226 | + } | ||
227 | + | ||
228 | + if (i == ARRAY_SIZE(fixed_mfd)) | ||
229 | + return -EINVAL; | ||
230 | + | ||
231 | + /* Use n_target and n_ref to avoid overflow */ | ||
232 | + for (pd = 1; pd <= PLL_PD_MAX; pd++) { | ||
233 | + t1 = n_target * pd; | ||
234 | + do_div(t1, (4 * n_ref)); | ||
235 | + mfi = t1; | ||
236 | + if (mfi > PLL_MFI_MAX) | ||
237 | + return -EINVAL; | ||
238 | + else if (mfi < 5) | ||
239 | + continue; | ||
240 | + break; | ||
241 | + } | ||
242 | + /* | ||
243 | + * Now got pd and mfi already | ||
244 | + * | ||
245 | + * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; | ||
246 | + */ | ||
247 | + t1 = n_target * pd; | ||
248 | + do_div(t1, 4); | ||
249 | + t1 -= n_ref * mfi; | ||
250 | + t1 *= mfd; | ||
251 | + do_div(t1, n_ref); | ||
252 | + mfn = t1; | ||
253 | + debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n", | ||
254 | + ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); | ||
255 | + i = 1; | ||
256 | + if (mfn != 0) | ||
257 | + i = gcd(mfd, mfn); | ||
258 | + pll->pd = (u32)pd; | ||
259 | + pll->mfi = (u32)mfi; | ||
260 | + do_div(mfn, i); | ||
261 | + pll->mfn = (u32)mfn; | ||
262 | + do_div(mfd, i); | ||
263 | + pll->mfd = (u32)mfd; | ||
264 | + | ||
265 | + return 0; | ||
266 | +} | ||
267 | + | ||
268 | +#define calc_div(tgt_clk, src_clk, limit) ({ \ | ||
269 | + u32 v = 0; \ | ||
270 | + if (((src_clk) % (tgt_clk)) <= 100) \ | ||
271 | + v = (src_clk) / (tgt_clk); \ | ||
272 | + else \ | ||
273 | + v = ((src_clk) / (tgt_clk)) + 1;\ | ||
274 | + if (v > limit) \ | ||
275 | + v = limit; \ | ||
276 | + (v - 1); \ | ||
277 | + }) | ||
278 | + | ||
279 | +#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ | ||
280 | + { \ | ||
281 | + __raw_writel(0x1232, &pll->ctrl); \ | ||
282 | + __raw_writel(0x2, &pll->config); \ | ||
283 | + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ | ||
284 | + &pll->op); \ | ||
285 | + __raw_writel(fn, &(pll->mfn)); \ | ||
286 | + __raw_writel((fd) - 1, &pll->mfd); \ | ||
287 | + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ | ||
288 | + &pll->hfs_op); \ | ||
289 | + __raw_writel(fn, &pll->hfs_mfn); \ | ||
290 | + __raw_writel((fd) - 1, &pll->hfs_mfd); \ | ||
291 | + __raw_writel(0x1232, &pll->ctrl); \ | ||
292 | + while (!__raw_readl(&pll->ctrl) & 0x1) \ | ||
293 | + ;\ | ||
294 | + } | ||
295 | + | ||
296 | +static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) | ||
297 | +{ | ||
298 | + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); | ||
299 | + struct mxc_pll_reg *pll = mxc_plls[index]; | ||
300 | + | ||
301 | + switch (index) { | ||
302 | + case PLL1_CLOCK: | ||
303 | + /* Switch ARM to PLL2 clock */ | ||
304 | + __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr); | ||
305 | + CHANGE_PLL_SETTINGS(pll, pll_param->pd, | ||
306 | + pll_param->mfi, pll_param->mfn, | ||
307 | + pll_param->mfd); | ||
308 | + /* Switch back */ | ||
309 | + __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr); | ||
310 | + break; | ||
311 | + case PLL2_CLOCK: | ||
312 | + /* Switch to pll2 bypass clock */ | ||
313 | + __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr); | ||
314 | + CHANGE_PLL_SETTINGS(pll, pll_param->pd, | ||
315 | + pll_param->mfi, pll_param->mfn, | ||
316 | + pll_param->mfd); | ||
317 | + /* Switch back */ | ||
318 | + __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr); | ||
319 | + break; | ||
320 | + case PLL3_CLOCK: | ||
321 | + /* Switch to pll3 bypass clock */ | ||
322 | + __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr); | ||
323 | + CHANGE_PLL_SETTINGS(pll, pll_param->pd, | ||
324 | + pll_param->mfi, pll_param->mfn, | ||
325 | + pll_param->mfd); | ||
326 | + /* Switch back */ | ||
327 | + __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); | ||
328 | + break; | ||
329 | + case PLL4_CLOCK: | ||
330 | + /* Switch to pll4 bypass clock */ | ||
331 | + __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); | ||
332 | + CHANGE_PLL_SETTINGS(pll, pll_param->pd, | ||
333 | + pll_param->mfi, pll_param->mfn, | ||
334 | + pll_param->mfd); | ||
335 | + /* Switch back */ | ||
336 | + __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr); | ||
337 | + break; | ||
338 | + default: | ||
339 | + return -EINVAL; | ||
340 | + } | ||
341 | + | ||
342 | + return 0; | ||
343 | +} | ||
344 | + | ||
345 | +/* Config CPU clock */ | ||
346 | +static int config_core_clk(u32 ref, u32 freq) | ||
347 | +{ | ||
348 | + int ret = 0; | ||
349 | + struct pll_param pll_param; | ||
350 | + | ||
351 | + memset(&pll_param, 0, sizeof(struct pll_param)); | ||
352 | + | ||
353 | + /* The case that periph uses PLL1 is not considered here */ | ||
354 | + ret = calc_pll_params(ref, freq, &pll_param); | ||
355 | + if (ret != 0) { | ||
356 | + printf("Error:Can't find pll parameters: %d\n", ret); | ||
357 | + return ret; | ||
358 | + } | ||
359 | + | ||
360 | + return config_pll_clk(PLL1_CLOCK, &pll_param); | ||
361 | +} | ||
362 | + | ||
363 | +static int config_nfc_clk(u32 nfc_clk) | ||
364 | +{ | ||
365 | + u32 reg; | ||
366 | + u32 parent_rate = get_emi_slow_clk(); | ||
367 | + u32 div = parent_rate / nfc_clk; | ||
368 | + | ||
369 | + if (nfc_clk <= 0) | ||
370 | + return -EINVAL; | ||
371 | + if (div == 0) | ||
372 | + div++; | ||
373 | + if (parent_rate / div > NFC_CLK_MAX) | ||
374 | + div++; | ||
375 | + reg = __raw_readl(&mxc_ccm->cbcdr); | ||
376 | + reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; | ||
377 | + reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; | ||
378 | + __raw_writel(reg, &mxc_ccm->cbcdr); | ||
379 | + while (__raw_readl(&mxc_ccm->cdhipr) != 0) | ||
380 | + ; | ||
381 | + return 0; | ||
382 | +} | ||
383 | + | ||
384 | +/* Config main_bus_clock for periphs */ | ||
385 | +static int config_periph_clk(u32 ref, u32 freq) | ||
386 | +{ | ||
387 | + int ret = 0; | ||
388 | + struct pll_param pll_param; | ||
389 | + | ||
390 | + memset(&pll_param, 0, sizeof(struct pll_param)); | ||
391 | + | ||
392 | + if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { | ||
393 | + ret = calc_pll_params(ref, freq, &pll_param); | ||
394 | + if (ret != 0) { | ||
395 | + printf("Error:Can't find pll parameters: %d\n", | ||
396 | + ret); | ||
397 | + return ret; | ||
398 | + } | ||
399 | + switch ((__raw_readl(&mxc_ccm->cbcmr) & \ | ||
400 | + MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \ | ||
401 | + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { | ||
402 | + case 0: | ||
403 | + return config_pll_clk(PLL1_CLOCK, &pll_param); | ||
404 | + break; | ||
405 | + case 1: | ||
406 | + return config_pll_clk(PLL3_CLOCK, &pll_param); | ||
407 | + break; | ||
408 | + default: | ||
409 | + return -EINVAL; | ||
410 | + } | ||
411 | + } | ||
412 | + | ||
413 | + return 0; | ||
414 | +} | ||
415 | + | ||
416 | +static int config_ddr_clk(u32 emi_clk) | ||
417 | +{ | ||
418 | + u32 clk_src; | ||
419 | + s32 shift = 0, clk_sel, div = 1; | ||
420 | + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); | ||
421 | + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); | ||
422 | + | ||
423 | + if (emi_clk > MAX_DDR_CLK) { | ||
424 | + printf("Warning:DDR clock should not exceed %d MHz\n", | ||
425 | + MAX_DDR_CLK / SZ_DEC_1M); | ||
426 | + emi_clk = MAX_DDR_CLK; | ||
427 | + } | ||
428 | + | ||
429 | + clk_src = get_periph_clk(); | ||
430 | + /* Find DDR clock input */ | ||
431 | + clk_sel = (cbcmr >> 10) & 0x3; | ||
432 | + switch (clk_sel) { | ||
433 | + case 0: | ||
434 | + shift = 16; | ||
435 | + break; | ||
436 | + case 1: | ||
437 | + shift = 19; | ||
438 | + break; | ||
439 | + case 2: | ||
440 | + shift = 22; | ||
441 | + break; | ||
442 | + case 3: | ||
443 | + shift = 10; | ||
444 | + break; | ||
445 | + default: | ||
446 | + return -EINVAL; | ||
447 | + } | ||
448 | + | ||
449 | + if ((clk_src % emi_clk) < 10000000) | ||
450 | + div = clk_src / emi_clk; | ||
451 | + else | ||
452 | + div = (clk_src / emi_clk) + 1; | ||
453 | + if (div > 8) | ||
454 | + div = 8; | ||
455 | + | ||
456 | + cbcdr = cbcdr & ~(0x7 << shift); | ||
457 | + cbcdr |= ((div - 1) << shift); | ||
458 | + __raw_writel(cbcdr, &mxc_ccm->cbcdr); | ||
459 | + while (__raw_readl(&mxc_ccm->cdhipr) != 0) | ||
460 | + ; | ||
461 | + __raw_writel(0x0, &mxc_ccm->ccdr); | ||
462 | + | ||
463 | + return 0; | ||
464 | +} | ||
465 | + | ||
466 | +/* | ||
467 | + * This function assumes the expected core clock has to be changed by | ||
468 | + * modifying the PLL. This is NOT true always but for most of the times, | ||
469 | + * it is. So it assumes the PLL output freq is the same as the expected | ||
470 | + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. | ||
471 | + * In the latter case, it will try to increase the presc value until | ||
472 | + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to | ||
473 | + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based | ||
474 | + * on the targeted PLL and reference input clock to the PLL. Lastly, | ||
475 | + * it sets the register based on these values along with the dividers. | ||
476 | + * Note 1) There is no value checking for the passed-in divider values | ||
477 | + * so the caller has to make sure those values are sensible. | ||
478 | + * 2) Also adjust the NFC divider such that the NFC clock doesn't | ||
479 | + * exceed NFC_CLK_MAX. | ||
480 | + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to | ||
481 | + * 177MHz for higher voltage, this function fixes the max to 133MHz. | ||
482 | + * 4) This function should not have allowed diag_printf() calls since | ||
483 | + * the serial driver has been stoped. But leave then here to allow | ||
484 | + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). | ||
485 | + */ | ||
486 | +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) | ||
487 | +{ | ||
488 | + freq *= SZ_DEC_1M; | ||
489 | + | ||
490 | + switch (clk) { | ||
491 | + case MXC_ARM_CLK: | ||
492 | + if (config_core_clk(ref, freq)) | ||
493 | + return -EINVAL; | ||
494 | + break; | ||
495 | + case MXC_PERIPH_CLK: | ||
496 | + if (config_periph_clk(ref, freq)) | ||
497 | + return -EINVAL; | ||
498 | + break; | ||
499 | + case MXC_DDR_CLK: | ||
500 | + if (config_ddr_clk(freq)) | ||
501 | + return -EINVAL; | ||
502 | + break; | ||
503 | + case MXC_NFC_CLK: | ||
504 | + if (config_nfc_clk(freq)) | ||
505 | + return -EINVAL; | ||
506 | + break; | ||
507 | + default: | ||
508 | + printf("Warning:Unsupported or invalid clock type\n"); | ||
509 | + } | ||
510 | + | ||
511 | + return 0; | ||
512 | +} | ||
513 | + | ||
514 | #ifdef CONFIG_MX53 | ||
515 | /* | ||
516 | * The clock for the external interface can be set to use internal clock | ||
517 | @@ -430,6 +869,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | ||
518 | printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); | ||
519 | printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); | ||
520 | printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); | ||
521 | + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); | ||
522 | |||
523 | return 0; | ||
524 | } | ||
525 | diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h | ||
526 | index e822809..35ee815 100644 | ||
527 | --- a/arch/arm/include/asm/arch-mx5/clock.h | ||
528 | +++ b/arch/arm/include/asm/arch-mx5/clock.h | ||
529 | @@ -33,6 +33,9 @@ enum mxc_clock { | ||
530 | MXC_CSPI_CLK, | ||
531 | MXC_FEC_CLK, | ||
532 | MXC_SATA_CLK, | ||
533 | + MXC_DDR_CLK, | ||
534 | + MXC_NFC_CLK, | ||
535 | + MXC_PERIPH_CLK, | ||
536 | }; | ||
537 | |||
538 | unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); | ||
539 | @@ -40,7 +43,7 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); | ||
540 | u32 imx_get_uartclk(void); | ||
541 | u32 imx_get_fecclk(void); | ||
542 | unsigned int mxc_get_clock(enum mxc_clock clk); | ||
543 | - | ||
544 | +int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); | ||
545 | void set_usb_phy2_clk(void); | ||
546 | void enable_usb_phy2_clk(unsigned char enable); | ||
547 | void set_usboh3_clk(void); | ||
548 | diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h | ||
549 | index bdeafbc..4e0fc1b 100644 | ||
550 | --- a/arch/arm/include/asm/arch-mx5/crm_regs.h | ||
551 | +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h | ||
552 | @@ -76,6 +76,9 @@ struct mxc_ccm_reg { | ||
553 | u32 CCGR4; | ||
554 | u32 CCGR5; | ||
555 | u32 CCGR6; /* 0x0080 */ | ||
556 | +#ifdef CONFIG_MX53 | ||
557 | + u32 CCGR7; /* 0x0084 */ | ||
558 | +#endif | ||
559 | u32 cmeor; | ||
560 | }; | ||
561 | |||
562 | @@ -84,6 +87,9 @@ struct mxc_ccm_reg { | ||
563 | #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 | ||
564 | |||
565 | /* Define the bits in register CBCDR */ | ||
566 | +#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) | ||
567 | +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) | ||
568 | +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 | ||
569 | #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) | ||
570 | #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) | ||
571 | #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 | ||
572 | -- | ||
573 | 1.7.10 | ||
574 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch deleted file mode 100644 index 79fd899..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch +++ /dev/null | |||
@@ -1,93 +0,0 @@ | |||
1 | From 255fe9c082f3a409d366517bb5e92d299fdbf2ff Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <festevam@gmail.com> | ||
3 | Date: Mon, 30 Apr 2012 08:12:03 +0000 | ||
4 | Subject: [PATCH 18/56] mx53loco: Allow to print CPU information at a later | ||
5 | stage | ||
6 | |||
7 | Print CPU information within board_late_init(). | ||
8 | |||
9 | This is in preparation for adding 1GHz support, which requires programming a PMIC | ||
10 | via I2C. As I2C is only available after relocation, print the CPU information | ||
11 | later at board_late_init(), so that the CPU frequency can be printed correctly. | ||
12 | |||
13 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
14 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
15 | --- | ||
16 | arch/arm/cpu/armv7/imx-common/cpu.c | 2 +- | ||
17 | arch/arm/include/asm/arch-mx5/sys_proto.h | 1 + | ||
18 | board/freescale/mx53loco/mx53loco.c | 22 ++++++++++++++++++++++ | ||
19 | include/configs/mx53loco.h | 1 - | ||
20 | 4 files changed, 24 insertions(+), 2 deletions(-) | ||
21 | |||
22 | diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c | ||
23 | index b96fa5b..b3195dd 100644 | ||
24 | --- a/arch/arm/cpu/armv7/imx-common/cpu.c | ||
25 | +++ b/arch/arm/cpu/armv7/imx-common/cpu.c | ||
26 | @@ -35,7 +35,7 @@ | ||
27 | #include <fsl_esdhc.h> | ||
28 | #endif | ||
29 | |||
30 | -static char *get_reset_cause(void) | ||
31 | +char *get_reset_cause(void) | ||
32 | { | ||
33 | u32 cause; | ||
34 | struct src *src_regs = (struct src *)SRC_BASE_ADDR; | ||
35 | diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h | ||
36 | index 3f10d29..7b5246e 100644 | ||
37 | --- a/arch/arm/include/asm/arch-mx5/sys_proto.h | ||
38 | +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h | ||
39 | @@ -37,5 +37,6 @@ void set_chipselect_size(int const); | ||
40 | int fecmxc_initialize(bd_t *bis); | ||
41 | u32 get_ahb_clk(void); | ||
42 | u32 get_periph_clk(void); | ||
43 | +char *get_reset_cause(void); | ||
44 | |||
45 | #endif | ||
46 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
47 | index 7ea9f6e..46aaeb2 100644 | ||
48 | --- a/board/freescale/mx53loco/mx53loco.c | ||
49 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
50 | @@ -299,6 +299,28 @@ int board_early_init_f(void) | ||
51 | return 0; | ||
52 | } | ||
53 | |||
54 | +int print_cpuinfo(void) | ||
55 | +{ | ||
56 | + u32 cpurev; | ||
57 | + | ||
58 | + cpurev = get_cpu_rev(); | ||
59 | + printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", | ||
60 | + (cpurev & 0xFF000) >> 12, | ||
61 | + (cpurev & 0x000F0) >> 4, | ||
62 | + (cpurev & 0x0000F) >> 0, | ||
63 | + mxc_get_clock(MXC_ARM_CLK) / 1000000); | ||
64 | + printf("Reset cause: %s\n", get_reset_cause()); | ||
65 | + return 0; | ||
66 | +} | ||
67 | + | ||
68 | +#ifdef CONFIG_BOARD_LATE_INIT | ||
69 | +int board_late_init(void) | ||
70 | +{ | ||
71 | + print_cpuinfo(); | ||
72 | + return 0; | ||
73 | +} | ||
74 | +#endif | ||
75 | + | ||
76 | int board_init(void) | ||
77 | { | ||
78 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | ||
79 | diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h | ||
80 | index af59307..0778bde 100644 | ||
81 | --- a/include/configs/mx53loco.h | ||
82 | +++ b/include/configs/mx53loco.h | ||
83 | @@ -27,7 +27,6 @@ | ||
84 | |||
85 | #define CONFIG_SYS_MX5_HCLK 24000000 | ||
86 | #define CONFIG_SYS_MX5_CLK32 32768 | ||
87 | -#define CONFIG_DISPLAY_CPUINFO | ||
88 | #define CONFIG_DISPLAY_BOARDINFO | ||
89 | |||
90 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO | ||
91 | -- | ||
92 | 1.7.10 | ||
93 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch deleted file mode 100644 index e9e2c1b..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch +++ /dev/null | |||
@@ -1,155 +0,0 @@ | |||
1 | From f658ecfa1294ec653afde9deb6ebedb1fe7d1afd Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <festevam@gmail.com> | ||
3 | Date: Mon, 30 Apr 2012 08:12:04 +0000 | ||
4 | Subject: [PATCH 19/56] mx53loco: Add support for 1GHz operation for | ||
5 | DA9053-based boards | ||
6 | |||
7 | There are two types of mx53loco boards: initial boards were built with a Dialog | ||
8 | DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC. | ||
9 | |||
10 | Add DA9053 PMIC support and adjust the required voltages and clocks for running | ||
11 | the CPU at 1GHz. | ||
12 | |||
13 | Tested on both versions of mx53loco boards. | ||
14 | |||
15 | In the case of a MC34708-based board the CPU operating voltage remains at 800MHz. | ||
16 | |||
17 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
18 | Acked-by : Stefano Babic <sbabic@denx.de> | ||
19 | --- | ||
20 | board/freescale/mx53loco/mx53loco.c | 71 +++++++++++++++++++++++++++++++++++ | ||
21 | include/configs/mx53loco.h | 14 +++++++ | ||
22 | 2 files changed, 85 insertions(+) | ||
23 | |||
24 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
25 | index 46aaeb2..0dcec9b 100644 | ||
26 | --- a/board/freescale/mx53loco/mx53loco.c | ||
27 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
28 | @@ -36,6 +36,8 @@ | ||
29 | #include <mmc.h> | ||
30 | #include <fsl_esdhc.h> | ||
31 | #include <asm/gpio.h> | ||
32 | +#include <pmic.h> | ||
33 | +#include <dialog_pmic.h> | ||
34 | |||
35 | DECLARE_GLOBAL_DATA_PTR; | ||
36 | |||
37 | @@ -291,6 +293,71 @@ int board_mmc_init(bd_t *bis) | ||
38 | } | ||
39 | #endif | ||
40 | |||
41 | +static void setup_iomux_i2c(void) | ||
42 | +{ | ||
43 | + /* I2C1 SDA */ | ||
44 | + mxc_request_iomux(MX53_PIN_CSI0_D8, | ||
45 | + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); | ||
46 | + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, | ||
47 | + INPUT_CTL_PATH0); | ||
48 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, | ||
49 | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | | ||
50 | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | | ||
51 | + PAD_CTL_PUE_PULL | | ||
52 | + PAD_CTL_ODE_OPENDRAIN_ENABLE); | ||
53 | + /* I2C1 SCL */ | ||
54 | + mxc_request_iomux(MX53_PIN_CSI0_D9, | ||
55 | + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); | ||
56 | + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, | ||
57 | + INPUT_CTL_PATH0); | ||
58 | + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, | ||
59 | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | | ||
60 | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | | ||
61 | + PAD_CTL_PUE_PULL | | ||
62 | + PAD_CTL_ODE_OPENDRAIN_ENABLE); | ||
63 | +} | ||
64 | + | ||
65 | +static int power_init(void) | ||
66 | +{ | ||
67 | + unsigned int val, ret; | ||
68 | + struct pmic *p; | ||
69 | + | ||
70 | + pmic_init(); | ||
71 | + p = get_pmic(); | ||
72 | + | ||
73 | + /* Set VDDA to 1.25V */ | ||
74 | + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; | ||
75 | + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); | ||
76 | + | ||
77 | + ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); | ||
78 | + val |= DA9052_SUPPLY_VBCOREGO; | ||
79 | + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); | ||
80 | + | ||
81 | + /* Set Vcc peripheral to 1.35V */ | ||
82 | + ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); | ||
83 | + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); | ||
84 | + | ||
85 | + return ret; | ||
86 | +} | ||
87 | + | ||
88 | +static void clock_1GHz(void) | ||
89 | +{ | ||
90 | + int ret; | ||
91 | + u32 ref_clk = CONFIG_SYS_MX5_HCLK; | ||
92 | + /* | ||
93 | + * After increasing voltage to 1.25V, we can switch | ||
94 | + * CPU clock to 1GHz and DDR to 400MHz safely | ||
95 | + */ | ||
96 | + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); | ||
97 | + if (ret) | ||
98 | + printf("CPU: Switch CPU clock to 1GHZ failed\n"); | ||
99 | + | ||
100 | + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); | ||
101 | + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); | ||
102 | + if (ret) | ||
103 | + printf("CPU: Switch DDR clock to 400MHz failed\n"); | ||
104 | +} | ||
105 | + | ||
106 | int board_early_init_f(void) | ||
107 | { | ||
108 | setup_iomux_uart(); | ||
109 | @@ -316,7 +383,11 @@ int print_cpuinfo(void) | ||
110 | #ifdef CONFIG_BOARD_LATE_INIT | ||
111 | int board_late_init(void) | ||
112 | { | ||
113 | + setup_iomux_i2c(); | ||
114 | + if (!power_init()) | ||
115 | + clock_1GHz(); | ||
116 | print_cpuinfo(); | ||
117 | + | ||
118 | return 0; | ||
119 | } | ||
120 | #endif | ||
121 | diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h | ||
122 | index 0778bde..8f43eec 100644 | ||
123 | --- a/include/configs/mx53loco.h | ||
124 | +++ b/include/configs/mx53loco.h | ||
125 | @@ -41,6 +41,7 @@ | ||
126 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | ||
127 | |||
128 | #define CONFIG_BOARD_EARLY_INIT_F | ||
129 | +#define CONFIG_BOARD_LATE_INIT | ||
130 | #define CONFIG_MXC_GPIO | ||
131 | |||
132 | #define CONFIG_MXC_UART | ||
133 | @@ -85,6 +86,19 @@ | ||
134 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | ||
135 | #define CONFIG_MXC_USB_FLAGS 0 | ||
136 | |||
137 | +/* I2C Configs */ | ||
138 | +#define CONFIG_HARD_I2C | ||
139 | +#define CONFIG_I2C_MXC | ||
140 | +#define CONFIG_SYS_I2C_MX53_PORT1 | ||
141 | +#define CONFIG_SYS_I2C_SPEED 100000 | ||
142 | +#define CONFIG_SYS_I2C_SLAVE 0xfe | ||
143 | + | ||
144 | +/* PMIC Controller */ | ||
145 | +#define CONFIG_PMIC | ||
146 | +#define CONFIG_PMIC_I2C | ||
147 | +#define CONFIG_DIALOG_PMIC | ||
148 | +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 | ||
149 | + | ||
150 | /* allow to overwrite serial and ethaddr */ | ||
151 | #define CONFIG_ENV_OVERWRITE | ||
152 | #define CONFIG_CONS_INDEX 1 | ||
153 | -- | ||
154 | 1.7.10 | ||
155 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0020-M28-Enable-FDT-support.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0020-M28-Enable-FDT-support.patch deleted file mode 100644 index 9a660d5..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0020-M28-Enable-FDT-support.patch +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | From 8c96682f52e8e9bf7591fad07e9f9bc51e1da7d4 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Thu, 3 May 2012 05:47:21 +0000 | ||
4 | Subject: [PATCH 20/56] M28: Enable FDT support | ||
5 | |||
6 | This will eventually be needed with Linux 3.5, which will be the point when | ||
7 | MXS will be switched to FDT. | ||
8 | |||
9 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
10 | Cc: Wolfgang Denk <wd@denx.de> | ||
11 | Cc: Detlev Zundel <dzu@denx.de> | ||
12 | Cc: Stefano Babic <sbabic@denx.de> | ||
13 | Cc: Fabio Estevam <festevam@gmail.com> | ||
14 | --- | ||
15 | include/configs/m28evk.h | 2 ++ | ||
16 | 1 file changed, 2 insertions(+) | ||
17 | |||
18 | diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h | ||
19 | index 39d6a07..40845d3 100644 | ||
20 | --- a/include/configs/m28evk.h | ||
21 | +++ b/include/configs/m28evk.h | ||
22 | @@ -43,6 +43,8 @@ | ||
23 | #define CONFIG_ARCH_CPU_INIT | ||
24 | #define CONFIG_ARCH_MISC_INIT | ||
25 | |||
26 | +#define CONFIG_OF_LIBFDT | ||
27 | + | ||
28 | /* | ||
29 | * SPL | ||
30 | */ | ||
31 | -- | ||
32 | 1.7.10 | ||
33 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch deleted file mode 100644 index 8ad0bf0..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | From 3dfa10c1a1d49b3b5b7cf6652fe965d088d4abc0 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Thu, 3 May 2012 05:47:18 +0000 | ||
4 | Subject: [PATCH 21/56] Revert "i.MX28: Enable additional DRAM address bits" | ||
5 | |||
6 | This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a. | ||
7 | |||
8 | Apparently, this commit got mainline only because of out-of-tree | ||
9 | port and causes breakage on board that is mainline. Revert. | ||
10 | |||
11 | Reason: | ||
12 | * The OOT board has 512MB of DRAM, enabling this additional address | ||
13 | line enabled it to work fine with 512MB of RAM. | ||
14 | * Every mainline port has max. 256MB of DRAM, therefore this revert | ||
15 | has no impact on any mainline port | ||
16 | * Though this caused a problem with new M28 board with 256MB of DRAM | ||
17 | where the chips are wired differently. The patch-to-be-reverted | ||
18 | caused the DRAM to behave like this: | ||
19 | |||
20 | [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again] | ||
21 | |||
22 | Therefore to retain the current one-memory-init-rules-them-all situation, | ||
23 | revert this patch until another board emerges and will actually be pushed | ||
24 | mainline that needs different setup. | ||
25 | |||
26 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
27 | Cc: Wolfgang Denk <wd@denx.de> | ||
28 | Cc: Detlev Zundel <dzu@denx.de> | ||
29 | Cc: Stefano Babic <sbabic@denx.de> | ||
30 | Cc: Fabio Estevam <festevam@gmail.com> | ||
31 | --- | ||
32 | arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 2 +- | ||
33 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
34 | |||
35 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
36 | index 911bbef..0f825ed 100644 | ||
37 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
38 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
39 | @@ -39,7 +39,7 @@ uint32_t dram_vals[] = { | ||
40 | 0x00000000, 0x00000100, 0x00000000, 0x00000000, | ||
41 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
42 | 0x00000000, 0x00000000, 0x00010101, 0x01010101, | ||
43 | - 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, | ||
44 | + 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, | ||
45 | 0x00000100, 0x00000100, 0x00000000, 0x00000002, | ||
46 | 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, | ||
47 | 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, | ||
48 | -- | ||
49 | 1.7.10 | ||
50 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch deleted file mode 100644 index 1176aea..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | From 0ab1b7fdcbe4fe014ae05f6a803d2ac84f98bd43 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Thu, 3 May 2012 05:47:19 +0000 | ||
4 | Subject: [PATCH 22/56] M28: Scan only first 512 MB of DRAM to avoid memory | ||
5 | wraparound | ||
6 | |||
7 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
8 | Cc: Wolfgang Denk <wd@denx.de> | ||
9 | Cc: Detlev Zundel <dzu@denx.de> | ||
10 | Cc: Stefano Babic <sbabic@denx.de> | ||
11 | Cc: Fabio Estevam <festevam@gmail.com> | ||
12 | --- | ||
13 | include/configs/m28evk.h | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h | ||
17 | index 40845d3..8cd5f31 100644 | ||
18 | --- a/include/configs/m28evk.h | ||
19 | +++ b/include/configs/m28evk.h | ||
20 | @@ -86,7 +86,7 @@ | ||
21 | */ | ||
22 | #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ | ||
23 | #define PHYS_SDRAM_1 0x40000000 /* Base address */ | ||
24 | -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ | ||
25 | +#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ | ||
26 | #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ | ||
27 | #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ | ||
28 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ | ||
29 | -- | ||
30 | 1.7.10 | ||
31 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0023-USB-ehci-mx6-Fix-broken-IO-access.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0023-USB-ehci-mx6-Fix-broken-IO-access.patch deleted file mode 100644 index 3617608..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0023-USB-ehci-mx6-Fix-broken-IO-access.patch +++ /dev/null | |||
@@ -1,42 +0,0 @@ | |||
1 | From 50b03cd90c32aced81d62f9b1c5385dd0bd7173d Mon Sep 17 00:00:00 2001 | ||
2 | From: Wolfgang Grandegger <wg@denx.de> | ||
3 | Date: Wed, 2 May 2012 04:36:39 +0000 | ||
4 | Subject: [PATCH 23/56] USB: ehci-mx6: Fix broken IO access | ||
5 | |||
6 | To get USB working again on the i.MX6, this patch fixes a bug introduced | ||
7 | with commit 522b2a0 "Add proper IO accessors for mx6 usb registers.". | ||
8 | At that occasion, I also added the missing __iomem directive. | ||
9 | |||
10 | Cc: Marek Vasut <marex@denx.de> | ||
11 | CC: Fabio Estevam <festevam@gmail.com> | ||
12 | Signed-off-by: Wolfgang Grandegger <wg@denx.de> | ||
13 | --- | ||
14 | drivers/usb/host/ehci-mx6.c | 5 +++-- | ||
15 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c | ||
18 | index 5dec673..42c77fe 100644 | ||
19 | --- a/drivers/usb/host/ehci-mx6.c | ||
20 | +++ b/drivers/usb/host/ehci-mx6.c | ||
21 | @@ -73,7 +73,8 @@ static void usbh1_internal_phy_clock_gate(int on) | ||
22 | |||
23 | static void usbh1_power_config(void) | ||
24 | { | ||
25 | - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | ||
26 | + struct anatop_regs __iomem *anatop = | ||
27 | + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; | ||
28 | /* | ||
29 | * Some phy and power's special controls for host1 | ||
30 | * 1. The external charger detector needs to be disabled | ||
31 | @@ -87,7 +88,7 @@ static void usbh1_power_config(void) | ||
32 | &anatop->usb2_chrg_detect); | ||
33 | |||
34 | __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, | ||
35 | - &anatop->usb2_pll_480_ctrl); | ||
36 | + &anatop->usb2_pll_480_ctrl_clr); | ||
37 | |||
38 | __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | | ||
39 | ANADIG_USB2_PLL_480_CTRL_POWER | | ||
40 | -- | ||
41 | 1.7.10 | ||
42 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0024-mx28evk-add-NAND-support.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0024-mx28evk-add-NAND-support.patch deleted file mode 100644 index 7cfa72d..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0024-mx28evk-add-NAND-support.patch +++ /dev/null | |||
@@ -1,78 +0,0 @@ | |||
1 | From 292a6fbe8085eb476c9cc6e9b2d23cad5c7e3ae4 Mon Sep 17 00:00:00 2001 | ||
2 | From: Lauri Hintsala <lauri.hintsala@bluegiga.com> | ||
3 | Date: Tue, 17 Apr 2012 00:35:46 +0000 | ||
4 | Subject: [PATCH 24/56] mx28evk: add NAND support | ||
5 | |||
6 | NAND support is not enabled by default because Eval Kit is not delivered | ||
7 | with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config. | ||
8 | |||
9 | Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> | ||
10 | Acked-by: Marek Vasut <marex@denx.de> | ||
11 | --- | ||
12 | board/freescale/mx28evk/iomux.c | 21 +++++++++++++++++++++ | ||
13 | include/configs/mx28evk.h | 10 ++++++++++ | ||
14 | 2 files changed, 31 insertions(+) | ||
15 | |||
16 | diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c | ||
17 | index 396761b..6587c45 100644 | ||
18 | --- a/board/freescale/mx28evk/iomux.c | ||
19 | +++ b/board/freescale/mx28evk/iomux.c | ||
20 | @@ -26,6 +26,7 @@ | ||
21 | #include <asm/arch/sys_proto.h> | ||
22 | |||
23 | #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) | ||
24 | +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) | ||
25 | #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) | ||
26 | #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) | ||
27 | #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) | ||
28 | @@ -55,6 +56,26 @@ const iomux_cfg_t iomux_setup[] = { | ||
29 | MX28_PAD_PWM3__GPIO_3_28 | | ||
30 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
31 | |||
32 | +#ifdef CONFIG_NAND_MXS | ||
33 | + /* GPMI NAND */ | ||
34 | + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, | ||
35 | + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, | ||
36 | + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, | ||
37 | + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, | ||
38 | + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, | ||
39 | + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, | ||
40 | + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, | ||
41 | + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, | ||
42 | + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, | ||
43 | + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, | ||
44 | + MX28_PAD_GPMI_RDN__GPMI_RDN | | ||
45 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), | ||
46 | + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, | ||
47 | + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, | ||
48 | + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, | ||
49 | + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, | ||
50 | +#endif | ||
51 | + | ||
52 | /* FEC0 */ | ||
53 | MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, | ||
54 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, | ||
55 | diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h | ||
56 | index 31dc718..5cd9730 100644 | ||
57 | --- a/include/configs/mx28evk.h | ||
58 | +++ b/include/configs/mx28evk.h | ||
59 | @@ -149,6 +149,16 @@ | ||
60 | #endif | ||
61 | |||
62 | /* | ||
63 | + * NAND Driver | ||
64 | + */ | ||
65 | +#ifdef CONFIG_CMD_NAND | ||
66 | +#define CONFIG_NAND_MXS | ||
67 | +#define CONFIG_SYS_MAX_NAND_DEVICE 1 | ||
68 | +#define CONFIG_SYS_NAND_BASE 0x60000000 | ||
69 | +#define CONFIG_SYS_NAND_5_ADDR_CYCLE | ||
70 | +#endif | ||
71 | + | ||
72 | +/* | ||
73 | * Ethernet on SOC (FEC) | ||
74 | */ | ||
75 | #ifdef CONFIG_CMD_NET | ||
76 | -- | ||
77 | 1.7.10 | ||
78 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0025-i.MX6-Add-ANATOP-regulator-init.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0025-i.MX6-Add-ANATOP-regulator-init.patch deleted file mode 100644 index 65b13bc..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0025-i.MX6-Add-ANATOP-regulator-init.patch +++ /dev/null | |||
@@ -1,84 +0,0 @@ | |||
1 | From 15616b5ca6f7dc2b728930cfc729d787869edc9e Mon Sep 17 00:00:00 2001 | ||
2 | From: Dirk Behme <dirk.behme@de.bosch.com> | ||
3 | Date: Wed, 2 May 2012 02:12:17 +0000 | ||
4 | Subject: [PATCH 25/56] i.MX6: Add ANATOP regulator init | ||
5 | |||
6 | Init the core regulator voltage to 1.2V. This is required for the correct | ||
7 | functioning of the GPU and when the ARM LDO is set to 1.225V. This is a | ||
8 | workaround to fix some memory clock jitter. | ||
9 | |||
10 | Note: This should be but can't be done in the DCD. The bootloader | ||
11 | prevents access to the ANATOP registers. | ||
12 | |||
13 | Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> | ||
14 | CC: Jason Chen <b02280@freescale.com> | ||
15 | CC: Jason Liu <r64343@freescale.com> | ||
16 | CC: Ranjani Vaidyanathan <ra5478@freescale.com> | ||
17 | CC: Stefano Babic <sbabic@denx.de> | ||
18 | CC: Fabio Estevam <festevam@gmail.com> | ||
19 | --- | ||
20 | arch/arm/cpu/armv7/mx6/soc.c | 30 +++++++++++++++++++++++++++++ | ||
21 | arch/arm/include/asm/arch-mx6/sys_proto.h | 2 ++ | ||
22 | 2 files changed, 32 insertions(+) | ||
23 | |||
24 | diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c | ||
25 | index 543b2cc..90f2088 100644 | ||
26 | --- a/arch/arm/cpu/armv7/mx6/soc.c | ||
27 | +++ b/arch/arm/cpu/armv7/mx6/soc.c | ||
28 | @@ -77,10 +77,40 @@ void init_aips(void) | ||
29 | writel(0x00000000, &aips2->opacr4); | ||
30 | } | ||
31 | |||
32 | +/* | ||
33 | + * Set the VDDSOC | ||
34 | + * | ||
35 | + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set | ||
36 | + * them to the specified millivolt level. | ||
37 | + * Possible values are from 0.725V to 1.450V in steps of | ||
38 | + * 0.025V (25mV). | ||
39 | + */ | ||
40 | +void set_vddsoc(u32 mv) | ||
41 | +{ | ||
42 | + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | ||
43 | + u32 val, reg = readl(&anatop->reg_core); | ||
44 | + | ||
45 | + if (mv < 725) | ||
46 | + val = 0x00; /* Power gated off */ | ||
47 | + else if (mv > 1450) | ||
48 | + val = 0x1F; /* Power FET switched full on. No regulation */ | ||
49 | + else | ||
50 | + val = (mv - 700) / 25; | ||
51 | + | ||
52 | + /* | ||
53 | + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) | ||
54 | + * and set them to the calculated value (0.7V + val * 0.25V) | ||
55 | + */ | ||
56 | + reg = (reg & ~(0x1F << 18)) | (val << 18); | ||
57 | + writel(reg, &anatop->reg_core); | ||
58 | +} | ||
59 | + | ||
60 | int arch_cpu_init(void) | ||
61 | { | ||
62 | init_aips(); | ||
63 | |||
64 | + set_vddsoc(1200); /* Set VDDSOC to 1.2V */ | ||
65 | + | ||
66 | return 0; | ||
67 | } | ||
68 | #endif | ||
69 | diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h | ||
70 | index 69687a8..711b30d 100644 | ||
71 | --- a/arch/arm/include/asm/arch-mx6/sys_proto.h | ||
72 | +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h | ||
73 | @@ -28,6 +28,8 @@ | ||
74 | |||
75 | u32 get_cpu_rev(void); | ||
76 | |||
77 | +void set_vddsoc(u32 mv); | ||
78 | + | ||
79 | /* | ||
80 | * Initializes on-chip ethernet controllers. | ||
81 | * to override, implement board_eth_init() | ||
82 | -- | ||
83 | 1.7.10 | ||
84 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0026-i.MX6-add-enable_sata_clock.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0026-i.MX6-add-enable_sata_clock.patch deleted file mode 100644 index cd26a24..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0026-i.MX6-add-enable_sata_clock.patch +++ /dev/null | |||
@@ -1,209 +0,0 @@ | |||
1 | From 46a009987c6ddb738f934e487181b78ea272c104 Mon Sep 17 00:00:00 2001 | ||
2 | From: Eric Nelson <eric.nelson@boundarydevices.com> | ||
3 | Date: Tue, 27 Mar 2012 09:52:21 +0000 | ||
4 | Subject: [PATCH 26/56] i.MX6: add enable_sata_clock() | ||
5 | |||
6 | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> | ||
7 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
8 | --- | ||
9 | arch/arm/cpu/armv7/mx6/clock.c | 31 +++++++++ | ||
10 | arch/arm/include/asm/arch-mx6/clock.h | 1 + | ||
11 | arch/arm/include/asm/arch-mx6/imx-regs.h | 9 +++ | ||
12 | arch/arm/include/asm/arch-mx6/iomux-v3.h | 111 ++++++++++++++++++++++++++++++ | ||
13 | 4 files changed, 152 insertions(+) | ||
14 | |||
15 | diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c | ||
16 | index 0f05432..52d5dc4 100644 | ||
17 | --- a/arch/arm/cpu/armv7/mx6/clock.c | ||
18 | +++ b/arch/arm/cpu/armv7/mx6/clock.c | ||
19 | @@ -292,6 +292,37 @@ u32 imx_get_fecclk(void) | ||
20 | return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK); | ||
21 | } | ||
22 | |||
23 | +int enable_sata_clock(void) | ||
24 | +{ | ||
25 | + u32 reg = 0; | ||
26 | + s32 timeout = 100000; | ||
27 | + struct mxc_ccm_reg *const imx_ccm | ||
28 | + = (struct mxc_ccm_reg *) CCM_BASE_ADDR; | ||
29 | + | ||
30 | + /* Enable sata clock */ | ||
31 | + reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ | ||
32 | + reg |= MXC_CCM_CCGR5_CG2_MASK; | ||
33 | + writel(reg, &imx_ccm->CCGR5); | ||
34 | + | ||
35 | + /* Enable PLLs */ | ||
36 | + reg = readl(&imx_ccm->analog_pll_enet); | ||
37 | + reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; | ||
38 | + writel(reg, &imx_ccm->analog_pll_enet); | ||
39 | + reg |= BM_ANADIG_PLL_SYS_ENABLE; | ||
40 | + while (timeout--) { | ||
41 | + if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) | ||
42 | + break; | ||
43 | + } | ||
44 | + if (timeout <= 0) | ||
45 | + return -EIO; | ||
46 | + reg &= ~BM_ANADIG_PLL_SYS_BYPASS; | ||
47 | + writel(reg, &imx_ccm->analog_pll_enet); | ||
48 | + reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; | ||
49 | + writel(reg, &imx_ccm->analog_pll_enet); | ||
50 | + | ||
51 | + return 0 ; | ||
52 | +} | ||
53 | + | ||
54 | unsigned int mxc_get_clock(enum mxc_clock clk) | ||
55 | { | ||
56 | switch (clk) { | ||
57 | diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h | ||
58 | index 613809b..b91d8bf 100644 | ||
59 | --- a/arch/arm/include/asm/arch-mx6/clock.h | ||
60 | +++ b/arch/arm/include/asm/arch-mx6/clock.h | ||
61 | @@ -47,5 +47,6 @@ u32 imx_get_uartclk(void); | ||
62 | u32 imx_get_fecclk(void); | ||
63 | unsigned int mxc_get_clock(enum mxc_clock clk); | ||
64 | void enable_usboh3_clk(unsigned char enable); | ||
65 | +int enable_sata_clock(void); | ||
66 | |||
67 | #endif /* __ASM_ARCH_CLOCK_H */ | ||
68 | diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h | ||
69 | index 6d25c8d..e165810 100644 | ||
70 | --- a/arch/arm/include/asm/arch-mx6/imx-regs.h | ||
71 | +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h | ||
72 | @@ -436,5 +436,14 @@ struct anatop_regs { | ||
73 | u32 digprog; /* 0x260 */ | ||
74 | }; | ||
75 | |||
76 | +struct iomuxc_base_regs { | ||
77 | + u32 gpr[14]; /* 0x000 */ | ||
78 | + u32 obsrv[5]; /* 0x038 */ | ||
79 | + u32 swmux_ctl[197]; /* 0x04c */ | ||
80 | + u32 swpad_ctl[250]; /* 0x360 */ | ||
81 | + u32 swgrp[26]; /* 0x748 */ | ||
82 | + u32 daisy[104]; /* 0x7b0..94c */ | ||
83 | +}; | ||
84 | + | ||
85 | #endif /* __ASSEMBLER__*/ | ||
86 | #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ | ||
87 | diff --git a/arch/arm/include/asm/arch-mx6/iomux-v3.h b/arch/arm/include/asm/arch-mx6/iomux-v3.h | ||
88 | index 4558f4f..788b413 100644 | ||
89 | --- a/arch/arm/include/asm/arch-mx6/iomux-v3.h | ||
90 | +++ b/arch/arm/include/asm/arch-mx6/iomux-v3.h | ||
91 | @@ -100,4 +100,115 @@ typedef u64 iomux_v3_cfg_t; | ||
92 | int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); | ||
93 | int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); | ||
94 | |||
95 | +/* | ||
96 | + * IOMUXC_GPR13 bit fields | ||
97 | + */ | ||
98 | +#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30) | ||
99 | +#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29) | ||
100 | +#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28) | ||
101 | +#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27) | ||
102 | +#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24) | ||
103 | +#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19) | ||
104 | +#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 | ||
105 | +#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) | ||
106 | +#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15) | ||
107 | +#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14) | ||
108 | +#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11) | ||
109 | +#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7) | ||
110 | +#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) | ||
111 | +#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) | ||
112 | + | ||
113 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24) | ||
114 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24) | ||
115 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24) | ||
116 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24) | ||
117 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24) | ||
118 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24) | ||
119 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24) | ||
120 | +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24) | ||
121 | + | ||
122 | +#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19) | ||
123 | +#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19) | ||
124 | +#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19) | ||
125 | +#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19) | ||
126 | +#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19) | ||
127 | +#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19) | ||
128 | + | ||
129 | +#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) | ||
130 | +#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) | ||
131 | + | ||
132 | +#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14) | ||
133 | +#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14) | ||
134 | + | ||
135 | +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11) | ||
136 | +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11) | ||
137 | +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11) | ||
138 | +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11) | ||
139 | +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) | ||
140 | +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) | ||
141 | + | ||
142 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7) | ||
143 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7) | ||
144 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7) | ||
145 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7) | ||
146 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7) | ||
147 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7) | ||
148 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7) | ||
149 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7) | ||
150 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7) | ||
151 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7) | ||
152 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7) | ||
153 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7) | ||
154 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7) | ||
155 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7) | ||
156 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7) | ||
157 | +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7) | ||
158 | + | ||
159 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2) | ||
160 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2) | ||
161 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2) | ||
162 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2) | ||
163 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2) | ||
164 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2) | ||
165 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2) | ||
166 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2) | ||
167 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2) | ||
168 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2) | ||
169 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2) | ||
170 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2) | ||
171 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2) | ||
172 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2) | ||
173 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2) | ||
174 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2) | ||
175 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2) | ||
176 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2) | ||
177 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2) | ||
178 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2) | ||
179 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2) | ||
180 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2) | ||
181 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2) | ||
182 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2) | ||
183 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2) | ||
184 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2) | ||
185 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2) | ||
186 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2) | ||
187 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2) | ||
188 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2) | ||
189 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2) | ||
190 | +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2) | ||
191 | + | ||
192 | +#define IOMUXC_GPR13_SATA_PHY_1_FAST 0 | ||
193 | +#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 | ||
194 | +#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2 | ||
195 | + | ||
196 | +#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \ | ||
197 | + |IOMUXC_GPR13_SATA_PHY_7_MASK \ | ||
198 | + |IOMUXC_GPR13_SATA_PHY_6_MASK \ | ||
199 | + |IOMUXC_GPR13_SATA_SPEED_MASK \ | ||
200 | + |IOMUXC_GPR13_SATA_PHY_5_MASK \ | ||
201 | + |IOMUXC_GPR13_SATA_PHY_4_MASK \ | ||
202 | + |IOMUXC_GPR13_SATA_PHY_3_MASK \ | ||
203 | + |IOMUXC_GPR13_SATA_PHY_2_MASK \ | ||
204 | + |IOMUXC_GPR13_SATA_PHY_1_MASK) | ||
205 | + | ||
206 | #endif /* __MACH_IOMUX_V3_H__*/ | ||
207 | -- | ||
208 | 1.7.10 | ||
209 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch deleted file mode 100644 index 65c5229..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch +++ /dev/null | |||
@@ -1,96 +0,0 @@ | |||
1 | From 95d9b53d5f0afdfe3487c5bd55a23f9503a2adad Mon Sep 17 00:00:00 2001 | ||
2 | From: Eric Nelson <eric.nelson@boundarydevices.com> | ||
3 | Date: Tue, 1 May 2012 09:55:11 +0000 | ||
4 | Subject: [PATCH 27/56] i.MX6: mx6q_sabrelite: add SATA bindings | ||
5 | |||
6 | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> | ||
7 | Acked-by: Marek Vasut <marex@denx.de> | ||
8 | Acked-by: stefano Babic <sbabic@denx.de> | ||
9 | --- | ||
10 | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 31 +++++++++++++++++++++++++ | ||
11 | include/configs/mx6qsabrelite.h | 13 +++++++++++ | ||
12 | 2 files changed, 44 insertions(+) | ||
13 | |||
14 | diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
15 | index 90773aa..29cbfed 100644 | ||
16 | --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
17 | +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c | ||
18 | @@ -25,6 +25,7 @@ | ||
19 | #include <asm/arch/imx-regs.h> | ||
20 | #include <asm/arch/mx6x_pins.h> | ||
21 | #include <asm/arch/iomux-v3.h> | ||
22 | +#include <asm/arch/clock.h> | ||
23 | #include <asm/errno.h> | ||
24 | #include <asm/gpio.h> | ||
25 | #include <mmc.h> | ||
26 | @@ -293,6 +294,32 @@ static void setup_buttons(void) | ||
27 | ARRAY_SIZE(button_pads)); | ||
28 | } | ||
29 | |||
30 | +#ifdef CONFIG_CMD_SATA | ||
31 | + | ||
32 | +int setup_sata(void) | ||
33 | +{ | ||
34 | + struct iomuxc_base_regs *const iomuxc_regs | ||
35 | + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; | ||
36 | + int ret = enable_sata_clock(); | ||
37 | + if (ret) | ||
38 | + return ret; | ||
39 | + | ||
40 | + clrsetbits_le32(&iomuxc_regs->gpr[13], | ||
41 | + IOMUXC_GPR13_SATA_MASK, | ||
42 | + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB | ||
43 | + |IOMUXC_GPR13_SATA_PHY_7_SATA2M | ||
44 | + |IOMUXC_GPR13_SATA_SPEED_3G | ||
45 | + |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) | ||
46 | + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED | ||
47 | + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 | ||
48 | + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB | ||
49 | + |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V | ||
50 | + |IOMUXC_GPR13_SATA_PHY_1_SLOW); | ||
51 | + | ||
52 | + return 0; | ||
53 | +} | ||
54 | +#endif | ||
55 | + | ||
56 | int board_early_init_f(void) | ||
57 | { | ||
58 | setup_iomux_uart(); | ||
59 | @@ -310,6 +337,10 @@ int board_init(void) | ||
60 | setup_spi(); | ||
61 | #endif | ||
62 | |||
63 | +#ifdef CONFIG_CMD_SATA | ||
64 | + setup_sata(); | ||
65 | +#endif | ||
66 | + | ||
67 | return 0; | ||
68 | } | ||
69 | |||
70 | diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h | ||
71 | index 48be6e6..feabc05 100644 | ||
72 | --- a/include/configs/mx6qsabrelite.h | ||
73 | +++ b/include/configs/mx6qsabrelite.h | ||
74 | @@ -72,6 +72,19 @@ | ||
75 | #define CONFIG_CMD_FAT | ||
76 | #define CONFIG_DOS_PARTITION | ||
77 | |||
78 | +#define CONFIG_CMD_SATA | ||
79 | +/* | ||
80 | + * SATA Configs | ||
81 | + */ | ||
82 | +#ifdef CONFIG_CMD_SATA | ||
83 | +#define CONFIG_DWC_AHSATA | ||
84 | +#define CONFIG_SYS_SATA_MAX_DEVICE 1 | ||
85 | +#define CONFIG_DWC_AHSATA_PORT_ID 0 | ||
86 | +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | ||
87 | +#define CONFIG_LBA48 | ||
88 | +#define CONFIG_LIBATA | ||
89 | +#endif | ||
90 | + | ||
91 | #define CONFIG_CMD_PING | ||
92 | #define CONFIG_CMD_DHCP | ||
93 | #define CONFIG_CMD_MII | ||
94 | -- | ||
95 | 1.7.10 | ||
96 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch deleted file mode 100644 index 4ebbc1b..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch +++ /dev/null | |||
@@ -1,114 +0,0 @@ | |||
1 | From b5e9dc88dbb9636129d3a600d9874477d2059716 Mon Sep 17 00:00:00 2001 | ||
2 | From: Timo Ketola <timo@exertus.fi> | ||
3 | Date: Wed, 18 Apr 2012 22:55:28 +0000 | ||
4 | Subject: [PATCH 28/56] i.MX25: esdhc: Add mxc_get_clock infrastructure | ||
5 | |||
6 | Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's | ||
7 | implement get_clocks function. This is how it seems to be implemented | ||
8 | elsewhere. | ||
9 | |||
10 | Signed-off-by: Timo Ketola <timo@exertus.fi> | ||
11 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
12 | --- | ||
13 | arch/arm/cpu/arm926ejs/mx25/generic.c | 27 +++++++++++++++++++++++++++ | ||
14 | arch/arm/include/asm/arch-mx25/clock.h | 23 +++++++++++++++++++++++ | ||
15 | 2 files changed, 50 insertions(+) | ||
16 | |||
17 | diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c | ||
18 | index 9cadb7c..8b07dae 100644 | ||
19 | --- a/arch/arm/cpu/arm926ejs/mx25/generic.c | ||
20 | +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c | ||
21 | @@ -28,10 +28,15 @@ | ||
22 | #include <asm/io.h> | ||
23 | #include <asm/arch/imx-regs.h> | ||
24 | #include <asm/arch/imx25-pinmux.h> | ||
25 | +#include <asm/arch/clock.h> | ||
26 | #ifdef CONFIG_MXC_MMC | ||
27 | #include <asm/arch/mxcmmc.h> | ||
28 | #endif | ||
29 | |||
30 | +#ifdef CONFIG_FSL_ESDHC | ||
31 | +DECLARE_GLOBAL_DATA_PTR; | ||
32 | +#endif | ||
33 | + | ||
34 | /* | ||
35 | * get the system pll clock in Hz | ||
36 | * | ||
37 | @@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk) | ||
38 | return lldiv(fref, div); | ||
39 | } | ||
40 | |||
41 | +unsigned int mxc_get_clock(enum mxc_clock clk) | ||
42 | +{ | ||
43 | + if (clk >= MXC_CLK_NUM) | ||
44 | + return -1; | ||
45 | + switch (clk) { | ||
46 | + case MXC_ARM_CLK: | ||
47 | + return imx_get_armclk(); | ||
48 | + case MXC_FEC_CLK: | ||
49 | + return imx_get_ahbclk(); | ||
50 | + default: | ||
51 | + return imx_get_perclk(clk); | ||
52 | + } | ||
53 | +} | ||
54 | + | ||
55 | u32 get_cpu_rev(void) | ||
56 | { | ||
57 | u32 srev; | ||
58 | @@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis) | ||
59 | #endif | ||
60 | } | ||
61 | |||
62 | +int get_clocks(void) | ||
63 | +{ | ||
64 | +#ifdef CONFIG_FSL_ESDHC | ||
65 | + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | ||
66 | +#endif | ||
67 | + return 0; | ||
68 | +} | ||
69 | + | ||
70 | /* | ||
71 | * Initializes on-chip MMC controllers. | ||
72 | * to override, implement board_mmc_init() | ||
73 | diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h | ||
74 | index c59f588..0f47eaf 100644 | ||
75 | --- a/arch/arm/include/asm/arch-mx25/clock.h | ||
76 | +++ b/arch/arm/include/asm/arch-mx25/clock.h | ||
77 | @@ -26,11 +26,34 @@ | ||
78 | #ifndef __ASM_ARCH_CLOCK_H | ||
79 | #define __ASM_ARCH_CLOCK_H | ||
80 | |||
81 | +enum mxc_clock { | ||
82 | + MXC_CSI_CLK, | ||
83 | + MXC_EPIT_CLK, | ||
84 | + MXC_ESAI_CLK, | ||
85 | + MXC_ESDHC1_CLK, | ||
86 | + MXC_ESDHC2_CLK, | ||
87 | + MXC_GPT_CLK, | ||
88 | + MXC_I2C_CLK, | ||
89 | + MXC_LCDC_CLK, | ||
90 | + MXC_NFC_CLK, | ||
91 | + MXC_OWIRE_CLK, | ||
92 | + MXC_PWM_CLK, | ||
93 | + MXC_SIM1_CLK, | ||
94 | + MXC_SIM2_CLK, | ||
95 | + MXC_SSI1_CLK, | ||
96 | + MXC_SSI2_CLK, | ||
97 | + MXC_UART_CLK, | ||
98 | + MXC_ARM_CLK, | ||
99 | + MXC_FEC_CLK, | ||
100 | + MXC_CLK_NUM | ||
101 | +}; | ||
102 | + | ||
103 | ulong imx_get_perclk(int clk); | ||
104 | ulong imx_get_ahbclk(void); | ||
105 | |||
106 | #define imx_get_uartclk() imx_get_perclk(15) | ||
107 | #define imx_get_fecclk() (imx_get_ahbclk()/2) | ||
108 | |||
109 | +unsigned int mxc_get_clock(enum mxc_clock clk); | ||
110 | |||
111 | #endif /* __ASM_ARCH_CLOCK_H */ | ||
112 | -- | ||
113 | 1.7.10 | ||
114 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0029-i.MX25-This-architecture-has-a-GPIO4-too.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0029-i.MX25-This-architecture-has-a-GPIO4-too.patch deleted file mode 100644 index 23750ed..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0029-i.MX25-This-architecture-has-a-GPIO4-too.patch +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | From 30a6bfcb371cf21afc98624989fcdb7114069b9d Mon Sep 17 00:00:00 2001 | ||
2 | From: Timo Ketola <timo@exertus.fi> | ||
3 | Date: Wed, 18 Apr 2012 22:55:29 +0000 | ||
4 | Subject: [PATCH 29/56] i.MX25: This architecture has a GPIO4 too | ||
5 | |||
6 | Signed-off-by: Timo Ketola <timo@exertus.fi> | ||
7 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
8 | --- | ||
9 | drivers/gpio/mxc_gpio.c | 3 ++- | ||
10 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
11 | |||
12 | diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c | ||
13 | index f1b1c16..6615535 100644 | ||
14 | --- a/drivers/gpio/mxc_gpio.c | ||
15 | +++ b/drivers/gpio/mxc_gpio.c | ||
16 | @@ -41,7 +41,8 @@ static unsigned long gpio_ports[] = { | ||
17 | [0] = GPIO1_BASE_ADDR, | ||
18 | [1] = GPIO2_BASE_ADDR, | ||
19 | [2] = GPIO3_BASE_ADDR, | ||
20 | -#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q) | ||
21 | +#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ | ||
22 | + defined(CONFIG_MX6Q) | ||
23 | [3] = GPIO4_BASE_ADDR, | ||
24 | #endif | ||
25 | #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q) | ||
26 | -- | ||
27 | 1.7.10 | ||
28 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0030-imx-nand-Support-flash-based-BBT.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0030-imx-nand-Support-flash-based-BBT.patch deleted file mode 100644 index cea0842..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0030-imx-nand-Support-flash-based-BBT.patch +++ /dev/null | |||
@@ -1,64 +0,0 @@ | |||
1 | From b288061f27dca116f164b39a24844932d74c3b88 Mon Sep 17 00:00:00 2001 | ||
2 | From: Timo Ketola <timo@exertus.fi> | ||
3 | Date: Wed, 18 Apr 2012 22:55:31 +0000 | ||
4 | Subject: [PATCH 30/56] imx: nand: Support flash based BBT | ||
5 | |||
6 | Signed-off-by: Timo Ketola <timo@exertus.fi> | ||
7 | Acked-by: Scott Wood <scottwood@freescale.com> | ||
8 | --- | ||
9 | drivers/mtd/nand/mxc_nand.c | 33 +++++++++++++++++++++++++++++++++ | ||
10 | 1 file changed, 33 insertions(+) | ||
11 | |||
12 | diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c | ||
13 | index 35e89a0..936186f 100644 | ||
14 | --- a/drivers/mtd/nand/mxc_nand.c | ||
15 | +++ b/drivers/mtd/nand/mxc_nand.c | ||
16 | @@ -1302,12 +1302,45 @@ static void mxc_setup_config1(void) | ||
17 | #define mxc_setup_config1() | ||
18 | #endif | ||
19 | |||
20 | +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT | ||
21 | + | ||
22 | +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | ||
23 | +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | ||
24 | + | ||
25 | +static struct nand_bbt_descr bbt_main_descr = { | ||
26 | + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | ||
27 | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | ||
28 | + .offs = 0, | ||
29 | + .len = 4, | ||
30 | + .veroffs = 4, | ||
31 | + .maxblocks = 4, | ||
32 | + .pattern = bbt_pattern, | ||
33 | +}; | ||
34 | + | ||
35 | +static struct nand_bbt_descr bbt_mirror_descr = { | ||
36 | + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | ||
37 | + NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | ||
38 | + .offs = 0, | ||
39 | + .len = 4, | ||
40 | + .veroffs = 4, | ||
41 | + .maxblocks = 4, | ||
42 | + .pattern = mirror_pattern, | ||
43 | +}; | ||
44 | + | ||
45 | +#endif | ||
46 | + | ||
47 | int board_nand_init(struct nand_chip *this) | ||
48 | { | ||
49 | struct mtd_info *mtd; | ||
50 | uint16_t tmp; | ||
51 | int err = 0; | ||
52 | |||
53 | +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT | ||
54 | + this->options |= NAND_USE_FLASH_BBT; | ||
55 | + this->bbt_td = &bbt_main_descr; | ||
56 | + this->bbt_md = &bbt_mirror_descr; | ||
57 | +#endif | ||
58 | + | ||
59 | /* structures must be linked */ | ||
60 | mtd = &host->mtd; | ||
61 | mtd->priv = this; | ||
62 | -- | ||
63 | 1.7.10 | ||
64 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0031-i.MX25-usb-Set-PORTSCx-register.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0031-i.MX25-usb-Set-PORTSCx-register.patch deleted file mode 100644 index f1eb111..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0031-i.MX25-usb-Set-PORTSCx-register.patch +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | From 6ac02672f1a34125de09864788b1ecb653b1b3bd Mon Sep 17 00:00:00 2001 | ||
2 | From: Timo Ketola <timo@exertus.fi> | ||
3 | Date: Wed, 18 Apr 2012 22:55:32 +0000 | ||
4 | Subject: [PATCH 31/56] i.MX25: usb: Set PORTSCx register | ||
5 | |||
6 | The USB controller in i.MX25 has a PORTSCx registers which should be | ||
7 | set. In this regard it is similar to the controller in i.MX31. As this | ||
8 | file is compiled only with i.MX25 and -31, #ifdef check can be removed. | ||
9 | |||
10 | Signed-off-by: Timo Ketola <timo@exertus.fi> | ||
11 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
12 | --- | ||
13 | drivers/usb/host/ehci-mxc.c | 2 -- | ||
14 | 1 file changed, 2 deletions(-) | ||
15 | |||
16 | diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c | ||
17 | index 61dbccd..7384580 100644 | ||
18 | --- a/drivers/usb/host/ehci-mxc.c | ||
19 | +++ b/drivers/usb/host/ehci-mxc.c | ||
20 | @@ -125,11 +125,9 @@ int ehci_hcd_init(void) | ||
21 | hcor = (struct ehci_hcor *)((uint32_t) hccr + | ||
22 | HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | ||
23 | setbits_le32(&ehci->usbmode, CM_HOST); | ||
24 | -#ifdef CONFIG_MX31 | ||
25 | setbits_le32(&ehci->control, USB_EN); | ||
26 | |||
27 | __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); | ||
28 | -#endif | ||
29 | mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); | ||
30 | |||
31 | udelay(10000); | ||
32 | -- | ||
33 | 1.7.10 | ||
34 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0032-imx-usb-There-is-no-such-register.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0032-imx-usb-There-is-no-such-register.patch deleted file mode 100644 index 9b99c05..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0032-imx-usb-There-is-no-such-register.patch +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | From 75aeb21482b9487c5f6cfd99a605b01343ef3440 Mon Sep 17 00:00:00 2001 | ||
2 | From: Timo Ketola <timo@exertus.fi> | ||
3 | Date: Wed, 18 Apr 2012 22:55:33 +0000 | ||
4 | Subject: [PATCH 32/56] imx: usb: There is no such register | ||
5 | |||
6 | The reference manual of i.MX25 (nor i.MX31) does not define such | ||
7 | register. This seems to access read only UH2_CAPLENGTH register (if | ||
8 | CONFIG_MXC_USB_PORT is zero). | ||
9 | |||
10 | Signed-off-by: Timo Ketola <timo@exertus.fi> | ||
11 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
12 | --- | ||
13 | drivers/usb/host/ehci-mxc.c | 2 -- | ||
14 | 1 file changed, 2 deletions(-) | ||
15 | |||
16 | diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c | ||
17 | index 7384580..45cbd18 100644 | ||
18 | --- a/drivers/usb/host/ehci-mxc.c | ||
19 | +++ b/drivers/usb/host/ehci-mxc.c | ||
20 | @@ -125,8 +125,6 @@ int ehci_hcd_init(void) | ||
21 | hcor = (struct ehci_hcor *)((uint32_t) hccr + | ||
22 | HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | ||
23 | setbits_le32(&ehci->usbmode, CM_HOST); | ||
24 | - setbits_le32(&ehci->control, USB_EN); | ||
25 | - | ||
26 | __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); | ||
27 | mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); | ||
28 | |||
29 | -- | ||
30 | 1.7.10 | ||
31 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch deleted file mode 100644 index ba62b1a..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | From 8c1283e4c08528b009789303e112694d174cc1d1 Mon Sep 17 00:00:00 2001 | ||
2 | From: Timo Ketola <timo@exertus.fi> | ||
3 | Date: Wed, 18 Apr 2012 22:55:34 +0000 | ||
4 | Subject: [PATCH 33/56] i.MX2: Include asm/types.h in arch-mx25/imx-regs.h | ||
5 | |||
6 | types.h must be included in imx-regs.h if one wants to include | ||
7 | imx-regs.h in a board configuration file. That for one's part is | ||
8 | necessary, if one wants to use addresses defined in imx-regs.h. | ||
9 | |||
10 | For example, fsl_esdhc.c needs CONFIG_SYS_FSL_ESDHC_ADDR defined and | ||
11 | a proper thing is to define it with IMX_MMC_SDHCx_BASE in board | ||
12 | configuration file. This patch fixes the build in that case. | ||
13 | |||
14 | Signed-off-by: Timo Ketola <timo@exertus.fi> | ||
15 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
16 | --- | ||
17 | arch/arm/include/asm/arch-mx25/imx-regs.h | 3 +++ | ||
18 | 1 file changed, 3 insertions(+) | ||
19 | |||
20 | diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h | ||
21 | index 7f9449b..cf925d7 100644 | ||
22 | --- a/arch/arm/include/asm/arch-mx25/imx-regs.h | ||
23 | +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h | ||
24 | @@ -34,6 +34,9 @@ | ||
25 | #define _IMX_REGS_H | ||
26 | |||
27 | #ifndef __ASSEMBLY__ | ||
28 | + | ||
29 | +#include <asm/types.h> | ||
30 | + | ||
31 | #ifdef CONFIG_FEC_MXC | ||
32 | extern void mx25_fec_init_pins(void); | ||
33 | #endif | ||
34 | -- | ||
35 | 1.7.10 | ||
36 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch deleted file mode 100644 index 692d16a..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | From b2f6a61134714190757c7aa81c3ed935cff106fa Mon Sep 17 00:00:00 2001 | ||
2 | From: Timo Ketola <timo@exertus.fi> | ||
3 | Date: Wed, 18 Apr 2012 22:55:35 +0000 | ||
4 | Subject: [PATCH 34/56] imx: Add u-boot.imx as target for ARM9 i.MX SOCs | ||
5 | |||
6 | Signed-off-by: Timo Ketola <timo@exertus.fi> | ||
7 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
8 | --- | ||
9 | arch/arm/cpu/arm926ejs/config.mk | 6 ++++++ | ||
10 | 1 file changed, 6 insertions(+) | ||
11 | |||
12 | diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk | ||
13 | index ffb2e6c..6a3a1bb 100644 | ||
14 | --- a/arch/arm/cpu/arm926ejs/config.mk | ||
15 | +++ b/arch/arm/cpu/arm926ejs/config.mk | ||
16 | @@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te | ||
17 | # ========================================================================= | ||
18 | PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) | ||
19 | PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) | ||
20 | + | ||
21 | +ifneq ($(CONFIG_IMX_CONFIG),) | ||
22 | + | ||
23 | +ALL-y += $(obj)u-boot.imx | ||
24 | + | ||
25 | +endif | ||
26 | -- | ||
27 | 1.7.10 | ||
28 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0035-pmic-dialog-Avoid-name-conflicts.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0035-pmic-dialog-Avoid-name-conflicts.patch deleted file mode 100644 index 6675f87..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0035-pmic-dialog-Avoid-name-conflicts.patch +++ /dev/null | |||
@@ -1,80 +0,0 @@ | |||
1 | From dcb3005b3fec92efb7a874eceb7074d6062b07ab Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 7 May 2012 10:25:58 +0000 | ||
4 | Subject: [PATCH 35/56] pmic: dialog: Avoid name conflicts | ||
5 | |||
6 | As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC, | ||
7 | we need to be able to build both drivers. | ||
8 | |||
9 | Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present. | ||
10 | |||
11 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
12 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
13 | --- | ||
14 | board/freescale/mx53loco/mx53loco.c | 2 +- | ||
15 | drivers/misc/pmic_dialog.c | 4 ++-- | ||
16 | include/dialog_pmic.h | 2 +- | ||
17 | include/pmic.h | 1 + | ||
18 | 4 files changed, 5 insertions(+), 4 deletions(-) | ||
19 | |||
20 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
21 | index 0dcec9b..7ed5c4e 100644 | ||
22 | --- a/board/freescale/mx53loco/mx53loco.c | ||
23 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
24 | @@ -322,7 +322,7 @@ static int power_init(void) | ||
25 | unsigned int val, ret; | ||
26 | struct pmic *p; | ||
27 | |||
28 | - pmic_init(); | ||
29 | + pmic_dialog_init(); | ||
30 | p = get_pmic(); | ||
31 | |||
32 | /* Set VDDA to 1.25V */ | ||
33 | diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c | ||
34 | index 7242073..e97af1d 100644 | ||
35 | --- a/drivers/misc/pmic_dialog.c | ||
36 | +++ b/drivers/misc/pmic_dialog.c | ||
37 | @@ -20,13 +20,13 @@ | ||
38 | #include <pmic.h> | ||
39 | #include <dialog_pmic.h> | ||
40 | |||
41 | -int pmic_init(void) | ||
42 | +int pmic_dialog_init(void) | ||
43 | { | ||
44 | struct pmic *p = get_pmic(); | ||
45 | static const char name[] = "DIALOG_PMIC"; | ||
46 | |||
47 | p->name = name; | ||
48 | - p->number_of_regs = PMIC_NUM_OF_REGS; | ||
49 | + p->number_of_regs = DIALOG_NUM_OF_REGS; | ||
50 | |||
51 | p->interface = PMIC_I2C; | ||
52 | p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR; | ||
53 | diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h | ||
54 | index b0925f5..8d43585 100644 | ||
55 | --- a/include/dialog_pmic.h | ||
56 | +++ b/include/dialog_pmic.h | ||
57 | @@ -164,7 +164,7 @@ enum { | ||
58 | DA9053_GPID7_REG, | ||
59 | DA9053_GPID8_REG, | ||
60 | DA9053_GPID9_REG, | ||
61 | - PMIC_NUM_OF_REGS, | ||
62 | + DIALOG_NUM_OF_REGS, | ||
63 | }; | ||
64 | |||
65 | #define DA_BUCKCORE_VBCORE_1_250V 0x1E | ||
66 | diff --git a/include/pmic.h b/include/pmic.h | ||
67 | index 52a1526..6a05b40 100644 | ||
68 | --- a/include/pmic.h | ||
69 | +++ b/include/pmic.h | ||
70 | @@ -55,6 +55,7 @@ struct pmic { | ||
71 | }; | ||
72 | |||
73 | int pmic_init(void); | ||
74 | +int pmic_dialog_init(void); | ||
75 | int check_reg(u32 reg); | ||
76 | struct pmic *get_pmic(void); | ||
77 | int pmic_probe(struct pmic *p); | ||
78 | -- | ||
79 | 1.7.10 | ||
80 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch deleted file mode 100644 index d6b353b..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch +++ /dev/null | |||
@@ -1,124 +0,0 @@ | |||
1 | From bb46787a684ee948eff96d5d9a7e6ff1632016ea Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 7 May 2012 10:25:59 +0000 | ||
4 | Subject: [PATCH 36/56] mx53loco: Add mc34708 support and set mx53 frequency | ||
5 | at 1GHz | ||
6 | |||
7 | Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz. | ||
8 | |||
9 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
10 | Acked-by: Jason Liu <r64343@freescale.com> | ||
11 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
12 | --- | ||
13 | board/freescale/mx53loco/mx53loco.c | 48 ++++++++++++++++++++++++++--------- | ||
14 | include/configs/mx53loco.h | 2 ++ | ||
15 | include/fsl_pmic.h | 10 ++++++++ | ||
16 | 3 files changed, 48 insertions(+), 12 deletions(-) | ||
17 | |||
18 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
19 | index 7ed5c4e..8f5ded9 100644 | ||
20 | --- a/board/freescale/mx53loco/mx53loco.c | ||
21 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
22 | @@ -38,6 +38,7 @@ | ||
23 | #include <asm/gpio.h> | ||
24 | #include <pmic.h> | ||
25 | #include <dialog_pmic.h> | ||
26 | +#include <fsl_pmic.h> | ||
27 | |||
28 | DECLARE_GLOBAL_DATA_PTR; | ||
29 | |||
30 | @@ -319,23 +320,46 @@ static void setup_iomux_i2c(void) | ||
31 | |||
32 | static int power_init(void) | ||
33 | { | ||
34 | - unsigned int val, ret; | ||
35 | + unsigned int val; | ||
36 | + int ret = -1; | ||
37 | struct pmic *p; | ||
38 | |||
39 | - pmic_dialog_init(); | ||
40 | - p = get_pmic(); | ||
41 | + if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { | ||
42 | + pmic_dialog_init(); | ||
43 | + p = get_pmic(); | ||
44 | |||
45 | - /* Set VDDA to 1.25V */ | ||
46 | - val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; | ||
47 | - ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); | ||
48 | + /* Set VDDA to 1.25V */ | ||
49 | + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; | ||
50 | + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); | ||
51 | |||
52 | - ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); | ||
53 | - val |= DA9052_SUPPLY_VBCOREGO; | ||
54 | - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); | ||
55 | + ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); | ||
56 | + val |= DA9052_SUPPLY_VBCOREGO; | ||
57 | + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); | ||
58 | |||
59 | - /* Set Vcc peripheral to 1.35V */ | ||
60 | - ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); | ||
61 | - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); | ||
62 | + /* Set Vcc peripheral to 1.30V */ | ||
63 | + ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); | ||
64 | + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); | ||
65 | + } | ||
66 | + | ||
67 | + if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { | ||
68 | + pmic_init(); | ||
69 | + p = get_pmic(); | ||
70 | + | ||
71 | + /* Set VDDGP to 1.25V for 1GHz on SW1 */ | ||
72 | + pmic_reg_read(p, REG_SW_0, &val); | ||
73 | + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; | ||
74 | + ret = pmic_reg_write(p, REG_SW_0, val); | ||
75 | + | ||
76 | + /* Set VCC as 1.30V on SW2 */ | ||
77 | + pmic_reg_read(p, REG_SW_1, &val); | ||
78 | + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; | ||
79 | + ret |= pmic_reg_write(p, REG_SW_1, val); | ||
80 | + | ||
81 | + /* Set global reset timer to 4s */ | ||
82 | + pmic_reg_read(p, REG_POWER_CTL2, &val); | ||
83 | + val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; | ||
84 | + ret |= pmic_reg_write(p, REG_POWER_CTL2, val); | ||
85 | + } | ||
86 | |||
87 | return ret; | ||
88 | } | ||
89 | diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h | ||
90 | index 8f43eec..87f6ed1 100644 | ||
91 | --- a/include/configs/mx53loco.h | ||
92 | +++ b/include/configs/mx53loco.h | ||
93 | @@ -97,7 +97,9 @@ | ||
94 | #define CONFIG_PMIC | ||
95 | #define CONFIG_PMIC_I2C | ||
96 | #define CONFIG_DIALOG_PMIC | ||
97 | +#define CONFIG_PMIC_FSL | ||
98 | #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 | ||
99 | +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 | ||
100 | |||
101 | /* allow to overwrite serial and ethaddr */ | ||
102 | #define CONFIG_ENV_OVERWRITE | ||
103 | diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h | ||
104 | index 742f2e1..3b7cd37 100644 | ||
105 | --- a/include/fsl_pmic.h | ||
106 | +++ b/include/fsl_pmic.h | ||
107 | @@ -122,4 +122,14 @@ enum { | ||
108 | /* Interrupt status 1 */ | ||
109 | #define RTCRSTI (1 << 7) | ||
110 | |||
111 | +/* MC34708 Definitions */ | ||
112 | +#define SWx_VOLT_MASK_MC34708 0x3F | ||
113 | +#define SWx_1_250V_MC34708 0x30 | ||
114 | +#define SWx_1_300V_MC34708 0x34 | ||
115 | +#define TIMER_MASK_MC34708 0x300 | ||
116 | +#define TIMER_4S_MC34708 0x100 | ||
117 | +#define VUSBSEL_MC34708 (1 << 2) | ||
118 | +#define VUSBEN_MC34708 (1 << 3) | ||
119 | +#define SWBST_CTRL 31 | ||
120 | + | ||
121 | #endif | ||
122 | -- | ||
123 | 1.7.10 | ||
124 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0037-mx53loco-Turn-on-VUSB-regulator.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0037-mx53loco-Turn-on-VUSB-regulator.patch deleted file mode 100644 index 783c460..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0037-mx53loco-Turn-on-VUSB-regulator.patch +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | From b2297ec8b5d8efeee9adfed046afd8594f020b51 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 7 May 2012 10:26:00 +0000 | ||
4 | Subject: [PATCH 37/56] mx53loco: Turn on VUSB regulator | ||
5 | |||
6 | On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator | ||
7 | so that the mx53 USBH1 PHY receives the 3.3V voltage. | ||
8 | |||
9 | Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the | ||
10 | commands: | ||
11 | |||
12 | usb start | ||
13 | |||
14 | usb info | ||
15 | |||
16 | ,which correctly detected and printed the USB pen drive information. | ||
17 | |||
18 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
19 | Acked-by: Jason Liu <r64343@freescale.com> | ||
20 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
21 | --- | ||
22 | board/freescale/mx53loco/mx53loco.c | 9 +++++++++ | ||
23 | include/fsl_pmic.h | 1 + | ||
24 | 2 files changed, 10 insertions(+) | ||
25 | |||
26 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
27 | index 8f5ded9..a49b00a 100644 | ||
28 | --- a/board/freescale/mx53loco/mx53loco.c | ||
29 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
30 | @@ -359,6 +359,15 @@ static int power_init(void) | ||
31 | pmic_reg_read(p, REG_POWER_CTL2, &val); | ||
32 | val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; | ||
33 | ret |= pmic_reg_write(p, REG_POWER_CTL2, val); | ||
34 | + | ||
35 | + /* Set VUSBSEL and VUSBEN for USB PHY supply*/ | ||
36 | + pmic_reg_read(p, REG_MODE_0, &val); | ||
37 | + val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); | ||
38 | + ret |= pmic_reg_write(p, REG_MODE_0, val); | ||
39 | + | ||
40 | + /* Set SWBST to 5V in auto mode */ | ||
41 | + val = SWBST_AUTO; | ||
42 | + ret |= pmic_reg_write(p, SWBST_CTRL, val); | ||
43 | } | ||
44 | |||
45 | return ret; | ||
46 | diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h | ||
47 | index 3b7cd37..64c1e2e 100644 | ||
48 | --- a/include/fsl_pmic.h | ||
49 | +++ b/include/fsl_pmic.h | ||
50 | @@ -131,5 +131,6 @@ enum { | ||
51 | #define VUSBSEL_MC34708 (1 << 2) | ||
52 | #define VUSBEN_MC34708 (1 << 3) | ||
53 | #define SWBST_CTRL 31 | ||
54 | +#define SWBST_AUTO 0x8 | ||
55 | |||
56 | #endif | ||
57 | -- | ||
58 | 1.7.10 | ||
59 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0038-mx53loco-Add-CONFIG_REVISION_TAG.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0038-mx53loco-Add-CONFIG_REVISION_TAG.patch deleted file mode 100644 index d6ee8e8..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0038-mx53loco-Add-CONFIG_REVISION_TAG.patch +++ /dev/null | |||
@@ -1,73 +0,0 @@ | |||
1 | From c5d52c5258d93702c8963c608a770e5142c76167 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Tue, 8 May 2012 03:40:49 +0000 | ||
4 | Subject: [PATCH 38/56] mx53loco: Add CONFIG_REVISION_TAG | ||
5 | |||
6 | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. | ||
7 | |||
8 | The kernel uses this data to distinguish between Dialog versus mc34708 based boards, | ||
9 | and also to distinguish between revA and revB of the mc34708 based boards. | ||
10 | |||
11 | Suggested-by: Yu Li <yk@magniel.com> | ||
12 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
13 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
14 | --- | ||
15 | arch/arm/include/asm/arch-mx5/imx-regs.h | 5 +++++ | ||
16 | board/freescale/mx53loco/mx53loco.c | 12 ++++++++++++ | ||
17 | include/configs/mx53loco.h | 1 + | ||
18 | 3 files changed, 18 insertions(+) | ||
19 | |||
20 | diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h | ||
21 | index 262517e..21c1bf5 100644 | ||
22 | --- a/arch/arm/include/asm/arch-mx5/imx-regs.h | ||
23 | +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h | ||
24 | @@ -486,6 +486,11 @@ struct iim_regs { | ||
25 | } bank[4]; | ||
26 | }; | ||
27 | |||
28 | +struct fuse_bank0_regs { | ||
29 | + u32 fuse0_23[24]; | ||
30 | + u32 gp[8]; | ||
31 | +}; | ||
32 | + | ||
33 | struct fuse_bank1_regs { | ||
34 | u32 fuse0_8[9]; | ||
35 | u32 mac_addr[6]; | ||
36 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
37 | index a49b00a..fb13895 100644 | ||
38 | --- a/board/freescale/mx53loco/mx53loco.c | ||
39 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
40 | @@ -62,6 +62,18 @@ void dram_init_banksize(void) | ||
41 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | ||
42 | } | ||
43 | |||
44 | +u32 get_board_rev(void) | ||
45 | +{ | ||
46 | + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; | ||
47 | + struct fuse_bank *bank = &iim->bank[0]; | ||
48 | + struct fuse_bank0_regs *fuse = | ||
49 | + (struct fuse_bank0_regs *)bank->fuse_regs; | ||
50 | + | ||
51 | + int rev = readl(&fuse->gp[6]); | ||
52 | + | ||
53 | + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; | ||
54 | +} | ||
55 | + | ||
56 | static void setup_iomux_uart(void) | ||
57 | { | ||
58 | /* UART1 RXD */ | ||
59 | diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h | ||
60 | index 87f6ed1..eab0e27 100644 | ||
61 | --- a/include/configs/mx53loco.h | ||
62 | +++ b/include/configs/mx53loco.h | ||
63 | @@ -43,6 +43,7 @@ | ||
64 | #define CONFIG_BOARD_EARLY_INIT_F | ||
65 | #define CONFIG_BOARD_LATE_INIT | ||
66 | #define CONFIG_MXC_GPIO | ||
67 | +#define CONFIG_REVISION_TAG | ||
68 | |||
69 | #define CONFIG_MXC_UART | ||
70 | #define CONFIG_MXC_UART_BASE UART1_BASE | ||
71 | -- | ||
72 | 1.7.10 | ||
73 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0039-mx53loco-Remove-unneeded-gpio_set_value.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0039-mx53loco-Remove-unneeded-gpio_set_value.patch deleted file mode 100644 index 3c91353..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0039-mx53loco-Remove-unneeded-gpio_set_value.patch +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | From ab4f8321498b5d9605d2e1754fcba5752f1b9d2b Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 7 May 2012 10:42:57 +0000 | ||
4 | Subject: [PATCH 39/56] mx53loco: Remove unneeded gpio_set_value() | ||
5 | |||
6 | There is no need to set the VBUS power enable to 0 first and then to 1. | ||
7 | |||
8 | Set it to 1 in the gpio_direction_output() function. | ||
9 | |||
10 | While at it, use the standard naming convention for the GPIO comment. | ||
11 | |||
12 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
13 | --- | ||
14 | board/freescale/mx53loco/mx53loco.c | 5 ++--- | ||
15 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
16 | |||
17 | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c | ||
18 | index fb13895..dec966d 100644 | ||
19 | --- a/board/freescale/mx53loco/mx53loco.c | ||
20 | +++ b/board/freescale/mx53loco/mx53loco.c | ||
21 | @@ -97,10 +97,9 @@ static void setup_iomux_uart(void) | ||
22 | #ifdef CONFIG_USB_EHCI_MX5 | ||
23 | int board_ehci_hcd_init(int port) | ||
24 | { | ||
25 | - /* request VBUS power enable pin, GPIO[8}, gpio7 */ | ||
26 | + /* request VBUS power enable pin, GPIO7_8 */ | ||
27 | mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1); | ||
28 | - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); | ||
29 | - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); | ||
30 | + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); | ||
31 | return 0; | ||
32 | } | ||
33 | #endif | ||
34 | -- | ||
35 | 1.7.10 | ||
36 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0040-spi-mxs-Introduce-spi_cs_is_valid.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0040-spi-mxs-Introduce-spi_cs_is_valid.patch deleted file mode 100644 index 5af00e8..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0040-spi-mxs-Introduce-spi_cs_is_valid.patch +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | From 99e963384668bdd678cea944c02ce47d223e7f0d Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 08:30:49 +0000 | ||
4 | Subject: [PATCH 40/56] spi: mxs: Introduce spi_cs_is_valid() | ||
5 | |||
6 | Introduce spi_cs_is_valid() for validating spi bus and chip select numbers. | ||
7 | |||
8 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | Acked-by: Marek Vasut <marex@denx.de> | ||
10 | Acked-by: Mike Frysinger <vapier@gentoo.org> | ||
11 | --- | ||
12 | drivers/spi/mxs_spi.c | 13 +++++++++++-- | ||
13 | 1 file changed, 11 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c | ||
16 | index 4e6f14e..e7237e7 100644 | ||
17 | --- a/drivers/spi/mxs_spi.c | ||
18 | +++ b/drivers/spi/mxs_spi.c | ||
19 | @@ -51,14 +51,23 @@ void spi_init(void) | ||
20 | { | ||
21 | } | ||
22 | |||
23 | +int spi_cs_is_valid(unsigned int bus, unsigned int cs) | ||
24 | +{ | ||
25 | + /* MXS SPI: 4 ports and 3 chip selects maximum */ | ||
26 | + if (bus > 3 || cs > 2) | ||
27 | + return 0; | ||
28 | + else | ||
29 | + return 1; | ||
30 | +} | ||
31 | + | ||
32 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, | ||
33 | unsigned int max_hz, unsigned int mode) | ||
34 | { | ||
35 | struct mxs_spi_slave *mxs_slave; | ||
36 | uint32_t addr; | ||
37 | |||
38 | - if (bus > 3) { | ||
39 | - printf("MXS SPI: Max bus number is 3\n"); | ||
40 | + if (!spi_cs_is_valid(bus, cs)) { | ||
41 | + printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); | ||
42 | return NULL; | ||
43 | } | ||
44 | |||
45 | -- | ||
46 | 1.7.10 | ||
47 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0041-spi-mxs-Allow-other-chip-selects-to-work.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0041-spi-mxs-Allow-other-chip-selects-to-work.patch deleted file mode 100644 index 03a4fe9..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0041-spi-mxs-Allow-other-chip-selects-to-work.patch +++ /dev/null | |||
@@ -1,57 +0,0 @@ | |||
1 | From f61ed79b5e9e95a15a7fa1e2180dfe7d64cd2d17 Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Mon, 23 Apr 2012 08:30:50 +0000 | ||
4 | Subject: [PATCH 41/56] spi: mxs: Allow other chip selects to work | ||
5 | |||
6 | MXS SSP controller may have up to three chip selects per port: SS0, SS1 and SS2. | ||
7 | |||
8 | Currently only SS0 is supported in the mxs_spi driver. | ||
9 | |||
10 | Allow all the three chip select to work by selecting the desired one | ||
11 | in bits 20 and 21 of the HW_SSP_CTRL0 register. | ||
12 | |||
13 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
14 | Acked-by: Marek Vasut <marex@denx.de> | ||
15 | --- | ||
16 | drivers/spi/mxs_spi.c | 10 ++++++++++ | ||
17 | 1 file changed, 10 insertions(+) | ||
18 | |||
19 | diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c | ||
20 | index e7237e7..7859536 100644 | ||
21 | --- a/drivers/spi/mxs_spi.c | ||
22 | +++ b/drivers/spi/mxs_spi.c | ||
23 | @@ -34,6 +34,8 @@ | ||
24 | |||
25 | #define MXS_SPI_MAX_TIMEOUT 1000000 | ||
26 | #define MXS_SPI_PORT_OFFSET 0x2000 | ||
27 | +#define MXS_SSP_CHIPSELECT_MASK 0x00300000 | ||
28 | +#define MXS_SSP_CHIPSELECT_SHIFT 20 | ||
29 | |||
30 | struct mxs_spi_slave { | ||
31 | struct spi_slave slave; | ||
32 | @@ -65,6 +67,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, | ||
33 | { | ||
34 | struct mxs_spi_slave *mxs_slave; | ||
35 | uint32_t addr; | ||
36 | + struct mx28_ssp_regs *ssp_regs; | ||
37 | + int reg; | ||
38 | |||
39 | if (!spi_cs_is_valid(bus, cs)) { | ||
40 | printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); | ||
41 | @@ -82,7 +86,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, | ||
42 | mxs_slave->max_khz = max_hz / 1000; | ||
43 | mxs_slave->mode = mode; | ||
44 | mxs_slave->regs = (struct mx28_ssp_regs *)addr; | ||
45 | + ssp_regs = mxs_slave->regs; | ||
46 | |||
47 | + reg = readl(&ssp_regs->hw_ssp_ctrl0); | ||
48 | + reg &= ~(MXS_SSP_CHIPSELECT_MASK); | ||
49 | + reg |= cs << MXS_SSP_CHIPSELECT_SHIFT; | ||
50 | + | ||
51 | + writel(reg, &ssp_regs->hw_ssp_ctrl0); | ||
52 | return &mxs_slave->slave; | ||
53 | } | ||
54 | |||
55 | -- | ||
56 | 1.7.10 | ||
57 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch deleted file mode 100644 index af60aa4..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | From 070bb8e23c0f2eb5106854adbc432c67b3177598 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Fri, 4 May 2012 01:32:50 +0000 | ||
4 | Subject: [PATCH 42/56] i.MX28: Add delay after CPU bypass is cleared | ||
5 | |||
6 | This solves issues when larger amount of DRAM is used, like 256MB. | ||
7 | Behave the same in case of CPU bypass as we do in case of EMI | ||
8 | bypass, but wait 15 ms. We need to wait until the clock domain | ||
9 | stabilizes. | ||
10 | |||
11 | This issue seemed to have been caused by not waiting after frobbing | ||
12 | with the CPU bypass, it was unrelated to memory, but had a direct | ||
13 | impact, causing trouble. This was yet another X-File of the | ||
14 | imx-bootlets, sigh. The conclusion is, trying a semi-random delay | ||
15 | (there is delay after the EMI bypass change), the issue is fixed. | ||
16 | |||
17 | Another possible explanation is that we do not do the "simple memory | ||
18 | test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of | ||
19 | the memory, while also outputing something on the serial port). This | ||
20 | might have caused the similar delay in the imx-bootlets and therefore | ||
21 | they didn't need to add this explicitly. | ||
22 | |||
23 | For now, this seems good fix enough, but to me, whole that memory | ||
24 | init code in imx-bootlets is completely flunked and it'd need deeper | ||
25 | investigation. | ||
26 | |||
27 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
28 | Cc: Wolfgang Denk <wd@denx.de> | ||
29 | Cc: Detlev Zundel <dzu@denx.de> | ||
30 | Cc: Stefano Babic <sbabic@denx.de> | ||
31 | Cc: Fabio Estevam <festevam@gmail.com> | ||
32 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
33 | Acked-by: Detlev Zundel <dzu@denx.de> | ||
34 | --- | ||
35 | arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 2 ++ | ||
36 | 1 file changed, 2 insertions(+) | ||
37 | |||
38 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
39 | index 0f825ed..69c865e 100644 | ||
40 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
41 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
42 | @@ -149,6 +149,8 @@ void mx28_mem_setup_cpu_and_hbus(void) | ||
43 | /* Disable CPU bypass */ | ||
44 | writel(CLKCTRL_CLKSEQ_BYPASS_CPU, | ||
45 | &clkctrl_regs->hw_clkctrl_clkseq_clr); | ||
46 | + | ||
47 | + early_delay(15000); | ||
48 | } | ||
49 | |||
50 | void mx28_mem_setup_vdda(void) | ||
51 | -- | ||
52 | 1.7.10 | ||
53 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch deleted file mode 100644 index d6bf84a..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch +++ /dev/null | |||
@@ -1,45 +0,0 @@ | |||
1 | From 31b19f2736b7d1c5c209ff22a99aec1c3449fedc Mon Sep 17 00:00:00 2001 | ||
2 | From: Stefano Babic <sbabic@denx.de> | ||
3 | Date: Wed, 9 May 2012 12:07:31 +0200 | ||
4 | Subject: [PATCH 43/56] MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH | ||
5 | exchanged | ||
6 | |||
7 | After an update to the MX51 reference manual (Rev. 5), the | ||
8 | values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH | ||
9 | are now clearly wrong: | ||
10 | |||
11 | "Bit 13: | ||
12 | High / Low Output Voltage Range. This bit selects the output voltage mode for | ||
13 | SD2_CMD. 0 High output voltage mode | ||
14 | 1 Low output voltage mode" | ||
15 | |||
16 | The values are currently negated in code - fixed. | ||
17 | |||
18 | Reported-by: David Jander <david.jander@protonic.nl> | ||
19 | Signed-off-by: Stefano Babic <sbabic@denx.de> | ||
20 | CC: Marek Vasut <marek.vasut@gmail.com> | ||
21 | CC: David Jander <david.jander@protonic.nl> | ||
22 | Acked-by: David Jander <david.jander@protonic.nl> | ||
23 | Acked-by: Marek Vasut <marek.vasut@gmail.com> | ||
24 | --- | ||
25 | arch/arm/include/asm/arch-mx5/iomux.h | 4 ++-- | ||
26 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
27 | |||
28 | diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h | ||
29 | index 760371b..e3765a3 100644 | ||
30 | --- a/arch/arm/include/asm/arch-mx5/iomux.h | ||
31 | +++ b/arch/arm/include/asm/arch-mx5/iomux.h | ||
32 | @@ -66,8 +66,8 @@ typedef enum iomux_pad_config { | ||
33 | PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ | ||
34 | PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ | ||
35 | PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ | ||
36 | - PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ | ||
37 | - PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ | ||
38 | + PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */ | ||
39 | + PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */ | ||
40 | } iomux_pad_config_t; | ||
41 | |||
42 | /* various IOMUX input functions */ | ||
43 | -- | ||
44 | 1.7.10 | ||
45 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0044-M28EVK-Implement-support-for-new-board-V2.0.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0044-M28EVK-Implement-support-for-new-board-V2.0.patch deleted file mode 100644 index 7b1e4f7..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0044-M28EVK-Implement-support-for-new-board-V2.0.patch +++ /dev/null | |||
@@ -1,92 +0,0 @@ | |||
1 | From 890ec079f7ada8cd197e7dcc30ec00435b2560d5 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Tue, 1 May 2012 11:09:42 +0000 | ||
4 | Subject: [PATCH 44/56] M28EVK: Implement support for new board V2.0 | ||
5 | |||
6 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
7 | Cc: Detlev Zundel <dzu@denx.de> | ||
8 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | Cc: Stefano Babic <sbabic@denx.de> | ||
10 | Cc: Wolfgang Denk <wd@denx.de> | ||
11 | --- | ||
12 | board/denx/m28evk/m28evk.c | 20 +++++++++++++++++++- | ||
13 | board/denx/m28evk/spl_boot.c | 8 ++++++-- | ||
14 | 2 files changed, 25 insertions(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c | ||
17 | index 53df476..3d28ea8 100644 | ||
18 | --- a/board/denx/m28evk/m28evk.c | ||
19 | +++ b/board/denx/m28evk/m28evk.c | ||
20 | @@ -90,6 +90,8 @@ int board_mmc_init(bd_t *bis) | ||
21 | { | ||
22 | /* Configure WP as input. */ | ||
23 | gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10); | ||
24 | + /* Turn on the power to the card. */ | ||
25 | + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); | ||
26 | |||
27 | return mxsmmc_initialize(bis, 0, m28_mmc_wp); | ||
28 | } | ||
29 | @@ -103,10 +105,18 @@ int board_mmc_init(bd_t *bis) | ||
30 | |||
31 | int fecmxc_mii_postcall(int phy) | ||
32 | { | ||
33 | +#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10) | ||
34 | + /* KZ8031 PHY on old boards. */ | ||
35 | + const uint32_t freq = 0x0080; | ||
36 | +#else | ||
37 | + /* KZ8021 PHY on new boards. */ | ||
38 | + const uint32_t freq = 0x0000; | ||
39 | +#endif | ||
40 | + | ||
41 | miiphy_write("FEC1", phy, MII_BMCR, 0x9000); | ||
42 | miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); | ||
43 | if (phy == 3) | ||
44 | - miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); | ||
45 | + miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq); | ||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | @@ -123,6 +133,14 @@ int board_eth_init(bd_t *bis) | ||
50 | CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, | ||
51 | CLKCTRL_ENET_TIME_SEL_RMII_CLK); | ||
52 | |||
53 | +#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) | ||
54 | + /* Reset the new PHY */ | ||
55 | + gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); | ||
56 | + udelay(10000); | ||
57 | + gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1); | ||
58 | + udelay(10000); | ||
59 | +#endif | ||
60 | + | ||
61 | ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); | ||
62 | if (ret) { | ||
63 | printf("FEC MXS: Unable to init FEC0\n"); | ||
64 | diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c | ||
65 | index a04fe18..7a12592 100644 | ||
66 | --- a/board/denx/m28evk/spl_boot.c | ||
67 | +++ b/board/denx/m28evk/spl_boot.c | ||
68 | @@ -109,8 +109,9 @@ const iomux_cfg_t iomux_setup[] = { | ||
69 | (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), | ||
70 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
71 | (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), | ||
72 | - MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */ | ||
73 | - MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */ | ||
74 | + MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 | | ||
75 | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */ | ||
76 | + MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */ | ||
77 | |||
78 | /* GPMI NAND */ | ||
79 | MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, | ||
80 | @@ -147,6 +148,9 @@ const iomux_cfg_t iomux_setup[] = { | ||
81 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, | ||
82 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, | ||
83 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, | ||
84 | +#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) | ||
85 | + MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */ | ||
86 | +#endif | ||
87 | |||
88 | /* I2C */ | ||
89 | MX28_PAD_I2C0_SCL__I2C0_SCL, | ||
90 | -- | ||
91 | 1.7.10 | ||
92 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0045-M28EVK-Add-SD-update-command.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0045-M28EVK-Add-SD-update-command.patch deleted file mode 100644 index c9a4d19..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0045-M28EVK-Add-SD-update-command.patch +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | From 9877804a0ec14f0582641bba8e5c9eec34e25c0e Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Tue, 1 May 2012 11:09:43 +0000 | ||
4 | Subject: [PATCH 45/56] M28EVK: Add SD update command | ||
5 | |||
6 | Add "update_sd_firmware" command to easily reload the SD card of | ||
7 | m28evk kit. This comes handy when the board boots from SD card. | ||
8 | |||
9 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
10 | Cc: Detlev Zundel <dzu@denx.de> | ||
11 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
12 | Cc: Stefano Babic <sbabic@denx.de> | ||
13 | Cc: Wolfgang Denk <wd@denx.de> | ||
14 | --- | ||
15 | include/configs/m28evk.h | 9 +++++++++ | ||
16 | 1 file changed, 9 insertions(+) | ||
17 | |||
18 | diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h | ||
19 | index 8cd5f31..60f8a6c 100644 | ||
20 | --- a/include/configs/m28evk.h | ||
21 | +++ b/include/configs/m28evk.h | ||
22 | @@ -289,6 +289,7 @@ | ||
23 | #define CONFIG_EXTRA_ENV_SETTINGS \ | ||
24 | "update_nand_full_filename=u-boot.nand\0" \ | ||
25 | "update_nand_firmware_filename=u-boot.sb\0" \ | ||
26 | + "update_sd_firmware_filename=u-boot.sd\0" \ | ||
27 | "update_nand_firmware_maxsz=0x100000\0" \ | ||
28 | "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ | ||
29 | "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ | ||
30 | @@ -315,6 +316,14 @@ | ||
31 | "nand erase ${fcb_sz} ${fw_sz} ; " \ | ||
32 | "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ | ||
33 | "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ | ||
34 | + "fi\0" \ | ||
35 | + "update_sd_firmware=" /* Update the SD firmware partition */ \ | ||
36 | + "if mmc rescan ; then " \ | ||
37 | + "if tftp ${update_sd_firmware_filename} ; then " \ | ||
38 | + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ | ||
39 | + "setexpr fw_sz ${fw_sz} + 1 ; " \ | ||
40 | + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ | ||
41 | + "fi ; " \ | ||
42 | "fi\0" | ||
43 | |||
44 | #endif /* __M28_H__ */ | ||
45 | -- | ||
46 | 1.7.10 | ||
47 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch deleted file mode 100644 index e84bd24..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch +++ /dev/null | |||
@@ -1,148 +0,0 @@ | |||
1 | From b4a826714297d304a42bfbe6622e66bbdebe0f61 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Tue, 1 May 2012 11:09:44 +0000 | ||
4 | Subject: [PATCH 46/56] i.MX28: Improve passing of data from SPL to U-Boot | ||
5 | |||
6 | Pass memory size from SPL via structure located in SRAM instead of SCRATCH | ||
7 | registers. This allows passing more data about boot from SPL to U-Boot, like the | ||
8 | boot mode pads configuration. | ||
9 | |||
10 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
11 | Cc: Detlev Zundel <dzu@denx.de> | ||
12 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
13 | Cc: Stefano Babic <sbabic@denx.de> | ||
14 | Cc: Wolfgang Denk <wd@denx.de> | ||
15 | --- | ||
16 | arch/arm/cpu/arm926ejs/mx28/mx28.c | 16 +++++----------- | ||
17 | arch/arm/cpu/arm926ejs/mx28/mx28_init.h | 1 + | ||
18 | arch/arm/cpu/arm926ejs/mx28/spl_boot.c | 7 +++++++ | ||
19 | arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 10 +++------- | ||
20 | arch/arm/include/asm/arch-mx28/sys_proto.h | 4 ++++ | ||
21 | 5 files changed, 20 insertions(+), 18 deletions(-) | ||
22 | |||
23 | diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
24 | index dc0338d..54a68e1 100644 | ||
25 | --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
26 | +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
27 | @@ -279,22 +279,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) | ||
28 | |||
29 | int mx28_dram_init(void) | ||
30 | { | ||
31 | - struct mx28_digctl_regs *digctl_regs = | ||
32 | - (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; | ||
33 | - uint32_t sz[2]; | ||
34 | + struct mx28_spl_data *data = (struct mx28_spl_data *) | ||
35 | + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); | ||
36 | |||
37 | - sz[0] = readl(&digctl_regs->hw_digctl_scratch0); | ||
38 | - sz[1] = readl(&digctl_regs->hw_digctl_scratch1); | ||
39 | - | ||
40 | - if (sz[0] != sz[1]) { | ||
41 | + if (data->mem_dram_size == 0) { | ||
42 | printf("MX28:\n" | ||
43 | - "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" | ||
44 | - "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" | ||
45 | - "verify these two registers contain valid RAM size!\n"); | ||
46 | + "Error, the RAM size passed up from SPL is 0!\n"); | ||
47 | hang(); | ||
48 | } | ||
49 | |||
50 | - gd->ram_size = sz[0]; | ||
51 | + gd->ram_size = data->mem_dram_size; | ||
52 | return 0; | ||
53 | } | ||
54 | |||
55 | diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h | ||
56 | index 98d3631..8eac958 100644 | ||
57 | --- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h | ||
58 | +++ b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h | ||
59 | @@ -37,5 +37,6 @@ static inline void mx28_power_wait_pswitch(void) { } | ||
60 | #endif | ||
61 | |||
62 | void mx28_mem_init(void); | ||
63 | +uint32_t mx28_mem_get_size(void); | ||
64 | |||
65 | #endif /* __M28_INIT_H__ */ | ||
66 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
67 | index dfb8309..37e1eb7 100644 | ||
68 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
69 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
70 | @@ -28,6 +28,7 @@ | ||
71 | #include <asm/io.h> | ||
72 | #include <asm/arch/iomux-mx28.h> | ||
73 | #include <asm/arch/imx-regs.h> | ||
74 | +#include <asm/arch/sys_proto.h> | ||
75 | |||
76 | #include "mx28_init.h" | ||
77 | |||
78 | @@ -49,9 +50,15 @@ void early_delay(int delay) | ||
79 | void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, | ||
80 | const unsigned int iomux_size) | ||
81 | { | ||
82 | + struct mx28_spl_data *data = (struct mx28_spl_data *) | ||
83 | + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); | ||
84 | + | ||
85 | mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); | ||
86 | mx28_power_init(); | ||
87 | + | ||
88 | mx28_mem_init(); | ||
89 | + data->mem_dram_size = mx28_mem_get_size(); | ||
90 | + | ||
91 | mx28_power_wait_pswitch(); | ||
92 | } | ||
93 | |||
94 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
95 | index 69c865e..9fa5d29 100644 | ||
96 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
97 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ||
98 | @@ -175,10 +175,8 @@ void mx28_mem_setup_vddd(void) | ||
99 | &power_regs->hw_power_vdddctrl); | ||
100 | } | ||
101 | |||
102 | -void mx28_mem_get_size(void) | ||
103 | +uint32_t mx28_mem_get_size(void) | ||
104 | { | ||
105 | - struct mx28_digctl_regs *digctl_regs = | ||
106 | - (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; | ||
107 | uint32_t sz, da; | ||
108 | uint32_t *vt = (uint32_t *)0x20; | ||
109 | /* The following is "subs pc, r14, #4", used as return from DABT. */ | ||
110 | @@ -189,11 +187,11 @@ void mx28_mem_get_size(void) | ||
111 | vt[4] = data_abort_memdetect_handler; | ||
112 | |||
113 | sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); | ||
114 | - writel(sz, &digctl_regs->hw_digctl_scratch0); | ||
115 | - writel(sz, &digctl_regs->hw_digctl_scratch1); | ||
116 | |||
117 | /* Restore the old DABT handler. */ | ||
118 | vt[4] = da; | ||
119 | + | ||
120 | + return sz; | ||
121 | } | ||
122 | |||
123 | void mx28_mem_init(void) | ||
124 | @@ -241,6 +239,4 @@ void mx28_mem_init(void) | ||
125 | early_delay(10000); | ||
126 | |||
127 | mx28_mem_setup_cpu_and_hbus(); | ||
128 | - | ||
129 | - mx28_mem_get_size(); | ||
130 | } | ||
131 | diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h | ||
132 | index 15d8de3..04f2e4d 100644 | ||
133 | --- a/arch/arm/include/asm/arch-mx28/sys_proto.h | ||
134 | +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h | ||
135 | @@ -39,6 +39,10 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, | ||
136 | const unsigned int iomux_size); | ||
137 | #endif | ||
138 | |||
139 | +struct mx28_spl_data { | ||
140 | + uint32_t mem_dram_size; | ||
141 | +}; | ||
142 | + | ||
143 | int mx28_dram_init(void); | ||
144 | |||
145 | #endif /* __MX28_H__ */ | ||
146 | -- | ||
147 | 1.7.10 | ||
148 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch deleted file mode 100644 index e915372..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch +++ /dev/null | |||
@@ -1,181 +0,0 @@ | |||
1 | From a950701d418e2e103cdfcd2f5880816dc1c6e6ec Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Tue, 1 May 2012 11:09:45 +0000 | ||
4 | Subject: [PATCH 47/56] i.MX28: Implement boot pads sampling and reporting | ||
5 | |||
6 | This patch implements code that samples i.MX28 boot pads and reports boot mode | ||
7 | accordingly. | ||
8 | |||
9 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
10 | Cc: Detlev Zundel <dzu@denx.de> | ||
11 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
12 | Cc: Stefano Babic <sbabic@denx.de> | ||
13 | Cc: Wolfgang Denk <wd@denx.de> | ||
14 | --- | ||
15 | arch/arm/cpu/arm926ejs/mx28/mx28.c | 4 +++ | ||
16 | arch/arm/cpu/arm926ejs/mx28/spl_boot.c | 48 ++++++++++++++++++++++++++++ | ||
17 | arch/arm/include/asm/arch-mx28/sys_proto.h | 26 +++++++++++++++ | ||
18 | include/configs/m28evk.h | 1 + | ||
19 | include/configs/mx28evk.h | 1 + | ||
20 | 5 files changed, 80 insertions(+) | ||
21 | |||
22 | diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
23 | index 54a68e1..865dbb3 100644 | ||
24 | --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
25 | +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
26 | @@ -185,8 +185,12 @@ int arch_cpu_init(void) | ||
27 | #if defined(CONFIG_DISPLAY_CPUINFO) | ||
28 | int print_cpuinfo(void) | ||
29 | { | ||
30 | + struct mx28_spl_data *data = (struct mx28_spl_data *) | ||
31 | + ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); | ||
32 | + | ||
33 | printf("Freescale i.MX28 family at %d MHz\n", | ||
34 | mxc_get_clock(MXC_ARM_CLK) / 1000000); | ||
35 | + printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); | ||
36 | return 0; | ||
37 | } | ||
38 | #endif | ||
39 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
40 | index 37e1eb7..c9b4566 100644 | ||
41 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
42 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
43 | @@ -29,6 +29,7 @@ | ||
44 | #include <asm/arch/iomux-mx28.h> | ||
45 | #include <asm/arch/imx-regs.h> | ||
46 | #include <asm/arch/sys_proto.h> | ||
47 | +#include <asm/gpio.h> | ||
48 | |||
49 | #include "mx28_init.h" | ||
50 | |||
51 | @@ -47,11 +48,56 @@ void early_delay(int delay) | ||
52 | ; | ||
53 | } | ||
54 | |||
55 | +#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) | ||
56 | +const iomux_cfg_t iomux_boot[] = { | ||
57 | + MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, | ||
58 | + MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, | ||
59 | + MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, | ||
60 | + MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, | ||
61 | + MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, | ||
62 | + MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, | ||
63 | +}; | ||
64 | + | ||
65 | +uint8_t mx28_get_bootmode_index(void) | ||
66 | +{ | ||
67 | + uint8_t bootmode = 0; | ||
68 | + int i; | ||
69 | + uint8_t masked; | ||
70 | + | ||
71 | + /* Setup IOMUX of bootmode pads to GPIO */ | ||
72 | + mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); | ||
73 | + | ||
74 | + /* Setup bootmode pins as GPIO input */ | ||
75 | + gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); | ||
76 | + gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); | ||
77 | + gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); | ||
78 | + gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); | ||
79 | + gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); | ||
80 | + gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); | ||
81 | + | ||
82 | + /* Read bootmode pads */ | ||
83 | + bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; | ||
84 | + bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; | ||
85 | + bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; | ||
86 | + bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; | ||
87 | + bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; | ||
88 | + bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; | ||
89 | + | ||
90 | + for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) { | ||
91 | + masked = bootmode & mx28_boot_modes[i].boot_mask; | ||
92 | + if (masked == mx28_boot_modes[i].boot_pads) | ||
93 | + break; | ||
94 | + } | ||
95 | + | ||
96 | + return i; | ||
97 | +} | ||
98 | + | ||
99 | void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, | ||
100 | const unsigned int iomux_size) | ||
101 | { | ||
102 | struct mx28_spl_data *data = (struct mx28_spl_data *) | ||
103 | ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf); | ||
104 | + uint8_t bootmode = mx28_get_bootmode_index(); | ||
105 | |||
106 | mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); | ||
107 | mx28_power_init(); | ||
108 | @@ -59,6 +105,8 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, | ||
109 | mx28_mem_init(); | ||
110 | data->mem_dram_size = mx28_mem_get_size(); | ||
111 | |||
112 | + data->boot_mode_idx = bootmode; | ||
113 | + | ||
114 | mx28_power_wait_pswitch(); | ||
115 | } | ||
116 | |||
117 | diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h | ||
118 | index 04f2e4d..e701c64 100644 | ||
119 | --- a/arch/arm/include/asm/arch-mx28/sys_proto.h | ||
120 | +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h | ||
121 | @@ -39,7 +39,33 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, | ||
122 | const unsigned int iomux_size); | ||
123 | #endif | ||
124 | |||
125 | +struct mx28_pair { | ||
126 | + uint8_t boot_pads; | ||
127 | + uint8_t boot_mask; | ||
128 | + const char *mode; | ||
129 | +}; | ||
130 | + | ||
131 | +static const struct mx28_pair mx28_boot_modes[] = { | ||
132 | + { 0x00, 0x0f, "USB #0" }, | ||
133 | + { 0x01, 0x1f, "I2C #0, master, 3V3" }, | ||
134 | + { 0x11, 0x1f, "I2C #0, master, 1V8" }, | ||
135 | + { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, | ||
136 | + { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, | ||
137 | + { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, | ||
138 | + { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, | ||
139 | + { 0x04, 0x1f, "NAND, 3V3" }, | ||
140 | + { 0x14, 0x1f, "NAND, 1V8" }, | ||
141 | + { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, | ||
142 | + { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, | ||
143 | + { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, | ||
144 | + { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, | ||
145 | + { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, | ||
146 | + { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, | ||
147 | + { 0x00, 0x00, "Reserved/Unknown/Wrong" }, | ||
148 | +}; | ||
149 | + | ||
150 | struct mx28_spl_data { | ||
151 | + uint8_t boot_mode_idx; | ||
152 | uint32_t mem_dram_size; | ||
153 | }; | ||
154 | |||
155 | diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h | ||
156 | index 60f8a6c..c62f4d0 100644 | ||
157 | --- a/include/configs/m28evk.h | ||
158 | +++ b/include/configs/m28evk.h | ||
159 | @@ -54,6 +54,7 @@ | ||
160 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" | ||
161 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | ||
162 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | ||
163 | +#define CONFIG_SPL_GPIO_SUPPORT | ||
164 | |||
165 | /* | ||
166 | * U-Boot Commands | ||
167 | diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h | ||
168 | index 5cd9730..0c18e50 100644 | ||
169 | --- a/include/configs/mx28evk.h | ||
170 | +++ b/include/configs/mx28evk.h | ||
171 | @@ -46,6 +46,7 @@ | ||
172 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" | ||
173 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | ||
174 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | ||
175 | +#define CONFIG_SPL_GPIO_SUPPORT | ||
176 | |||
177 | /* | ||
178 | * U-Boot Commands | ||
179 | -- | ||
180 | 1.7.10 | ||
181 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0048-i.MX28-Add-LCDIF-register-definitions.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0048-i.MX28-Add-LCDIF-register-definitions.patch deleted file mode 100644 index f7f8c79..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0048-i.MX28-Add-LCDIF-register-definitions.patch +++ /dev/null | |||
@@ -1,249 +0,0 @@ | |||
1 | From c4132c660f8e5e2f05b4f7e284f0ae516a10bb8a Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marek.vasut@gmail.com> | ||
3 | Date: Tue, 1 May 2012 11:09:46 +0000 | ||
4 | Subject: [PATCH 48/56] i.MX28: Add LCDIF register definitions | ||
5 | |||
6 | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> | ||
7 | Cc: Detlev Zundel <dzu@denx.de> | ||
8 | Cc: Fabio Estevam <festevam@gmail.com> | ||
9 | Cc: Stefano Babic <sbabic@denx.de> | ||
10 | Cc: Wolfgang Denk <wd@denx.de> | ||
11 | --- | ||
12 | arch/arm/include/asm/arch-mx28/imx-regs.h | 1 + | ||
13 | arch/arm/include/asm/arch-mx28/regs-lcdif.h | 212 +++++++++++++++++++++++++++ | ||
14 | 2 files changed, 213 insertions(+) | ||
15 | create mode 100644 arch/arm/include/asm/arch-mx28/regs-lcdif.h | ||
16 | |||
17 | diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h | ||
18 | index f9e6c53..581bf0a 100644 | ||
19 | --- a/arch/arm/include/asm/arch-mx28/imx-regs.h | ||
20 | +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h | ||
21 | @@ -30,6 +30,7 @@ | ||
22 | #include <asm/arch/regs-digctl.h> | ||
23 | #include <asm/arch/regs-gpmi.h> | ||
24 | #include <asm/arch/regs-i2c.h> | ||
25 | +#include <asm/arch/regs-lcdif.h> | ||
26 | #include <asm/arch/regs-ocotp.h> | ||
27 | #include <asm/arch/regs-pinctrl.h> | ||
28 | #include <asm/arch/regs-power.h> | ||
29 | diff --git a/arch/arm/include/asm/arch-mx28/regs-lcdif.h b/arch/arm/include/asm/arch-mx28/regs-lcdif.h | ||
30 | new file mode 100644 | ||
31 | index 0000000..cb47e41 | ||
32 | --- /dev/null | ||
33 | +++ b/arch/arm/include/asm/arch-mx28/regs-lcdif.h | ||
34 | @@ -0,0 +1,212 @@ | ||
35 | +/* | ||
36 | + * Freescale i.MX28 LCDIF Register Definitions | ||
37 | + * | ||
38 | + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | ||
39 | + * on behalf of DENX Software Engineering GmbH | ||
40 | + * | ||
41 | + * Based on code from LTIB: | ||
42 | + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
43 | + * | ||
44 | + * This program is free software; you can redistribute it and/or modify | ||
45 | + * it under the terms of the GNU General Public License as published by | ||
46 | + * the Free Software Foundation; either version 2 of the License, or | ||
47 | + * (at your option) any later version. | ||
48 | + * | ||
49 | + * This program is distributed in the hope that it will be useful, | ||
50 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
51 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
52 | + * GNU General Public License for more details. | ||
53 | + * | ||
54 | + * You should have received a copy of the GNU General Public License | ||
55 | + * along with this program; if not, write to the Free Software | ||
56 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
57 | + * | ||
58 | + */ | ||
59 | + | ||
60 | +#ifndef __MX28_REGS_LCDIF_H__ | ||
61 | +#define __MX28_REGS_LCDIF_H__ | ||
62 | + | ||
63 | +#include <asm/arch/regs-common.h> | ||
64 | + | ||
65 | +#ifndef __ASSEMBLY__ | ||
66 | +struct mx28_lcdif_regs { | ||
67 | + mx28_reg_32(hw_lcdif_ctrl) /* 0x00 */ | ||
68 | + mx28_reg_32(hw_lcdif_ctrl1) /* 0x10 */ | ||
69 | + mx28_reg_32(hw_lcdif_ctrl2) /* 0x20 */ | ||
70 | + mx28_reg_32(hw_lcdif_transfer_count) /* 0x30 */ | ||
71 | + mx28_reg_32(hw_lcdif_cur_buf) /* 0x40 */ | ||
72 | + mx28_reg_32(hw_lcdif_next_buf) /* 0x50 */ | ||
73 | + mx28_reg_32(hw_lcdif_timing) /* 0x60 */ | ||
74 | + mx28_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ | ||
75 | + mx28_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ | ||
76 | + mx28_reg_32(hw_lcdif_vdctrl2) /* 0x90 */ | ||
77 | + mx28_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */ | ||
78 | + mx28_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */ | ||
79 | + mx28_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */ | ||
80 | + mx28_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */ | ||
81 | + mx28_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */ | ||
82 | + mx28_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */ | ||
83 | + mx28_reg_32(hw_lcdif_dvictrl4) /* 0x100 */ | ||
84 | + mx28_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */ | ||
85 | + mx28_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */ | ||
86 | + mx28_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ | ||
87 | + mx28_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ | ||
88 | + mx28_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ | ||
89 | + mx28_reg_32(hw_lcdif_csc_offset) /* 0x160 */ | ||
90 | + mx28_reg_32(hw_lcdif_csc_limit) /* 0x170 */ | ||
91 | + mx28_reg_32(hw_lcdif_data) /* 0x180 */ | ||
92 | + mx28_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */ | ||
93 | + mx28_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ | ||
94 | + mx28_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */ | ||
95 | + mx28_reg_32(hw_lcdif_version) /* 0x1c0 */ | ||
96 | + mx28_reg_32(hw_lcdif_debug0) /* 0x1d0 */ | ||
97 | + mx28_reg_32(hw_lcdif_debug1) /* 0x1e0 */ | ||
98 | + mx28_reg_32(hw_lcdif_debug2) /* 0x1f0 */ | ||
99 | +}; | ||
100 | +#endif | ||
101 | + | ||
102 | +#define LCDIF_CTRL_SFTRST (1 << 31) | ||
103 | +#define LCDIF_CTRL_CLKGATE (1 << 30) | ||
104 | +#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) | ||
105 | +#define LCDIF_CTRL_READ_WRITEB (1 << 28) | ||
106 | +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) | ||
107 | +#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) | ||
108 | +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) | ||
109 | +#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 | ||
110 | +#define LCDIF_CTRL_DVI_MODE (1 << 20) | ||
111 | +#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) | ||
112 | +#define LCDIF_CTRL_VSYNC_MODE (1 << 18) | ||
113 | +#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) | ||
114 | +#define LCDIF_CTRL_DATA_SELECT (1 << 16) | ||
115 | +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) | ||
116 | +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 | ||
117 | +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) | ||
118 | +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 | ||
119 | +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) | ||
120 | +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 | ||
121 | +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) | ||
122 | +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) | ||
123 | +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) | ||
124 | +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) | ||
125 | +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) | ||
126 | +#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 | ||
127 | +#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) | ||
128 | +#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) | ||
129 | +#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) | ||
130 | +#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) | ||
131 | +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) | ||
132 | +#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) | ||
133 | +#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) | ||
134 | +#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) | ||
135 | +#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) | ||
136 | +#define LCDIF_CTRL_RUN (1 << 0) | ||
137 | + | ||
138 | +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) | ||
139 | +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) | ||
140 | +#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) | ||
141 | +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) | ||
142 | +#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) | ||
143 | +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) | ||
144 | +#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) | ||
145 | +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) | ||
146 | +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) | ||
147 | +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 | ||
148 | +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) | ||
149 | +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) | ||
150 | +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) | ||
151 | +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) | ||
152 | +#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) | ||
153 | +#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) | ||
154 | +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) | ||
155 | +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) | ||
156 | +#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) | ||
157 | +#define LCDIF_CTRL1_MODE86 (1 << 1) | ||
158 | +#define LCDIF_CTRL1_RESET (1 << 0) | ||
159 | + | ||
160 | +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) | ||
161 | +#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 | ||
162 | +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) | ||
163 | +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) | ||
164 | +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) | ||
165 | +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) | ||
166 | +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) | ||
167 | +#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) | ||
168 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) | ||
169 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 | ||
170 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) | ||
171 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) | ||
172 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) | ||
173 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) | ||
174 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) | ||
175 | +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) | ||
176 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) | ||
177 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 | ||
178 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) | ||
179 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) | ||
180 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) | ||
181 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) | ||
182 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) | ||
183 | +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) | ||
184 | +#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) | ||
185 | +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) | ||
186 | +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) | ||
187 | +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) | ||
188 | +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 | ||
189 | +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) | ||
190 | +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 | ||
191 | + | ||
192 | +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) | ||
193 | +#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 | ||
194 | +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) | ||
195 | +#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 | ||
196 | + | ||
197 | +#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff | ||
198 | +#define LCDIF_CUR_BUF_ADDR_OFFSET 0 | ||
199 | + | ||
200 | +#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff | ||
201 | +#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 | ||
202 | + | ||
203 | +#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) | ||
204 | +#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 | ||
205 | +#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) | ||
206 | +#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 | ||
207 | +#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) | ||
208 | +#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 | ||
209 | +#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) | ||
210 | +#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 | ||
211 | + | ||
212 | +#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) | ||
213 | +#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) | ||
214 | +#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) | ||
215 | +#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) | ||
216 | +#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) | ||
217 | +#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) | ||
218 | +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) | ||
219 | +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) | ||
220 | +#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) | ||
221 | +#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) | ||
222 | +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff | ||
223 | +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 | ||
224 | + | ||
225 | +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff | ||
226 | +#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 | ||
227 | + | ||
228 | +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) | ||
229 | +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 | ||
230 | +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff | ||
231 | +#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 | ||
232 | + | ||
233 | +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) | ||
234 | +#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) | ||
235 | +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) | ||
236 | +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 | ||
237 | +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) | ||
238 | +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 | ||
239 | + | ||
240 | +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) | ||
241 | +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 | ||
242 | +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) | ||
243 | +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff | ||
244 | +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 | ||
245 | + | ||
246 | +#endif /* __MX28_REGS_LCDIF_H__ */ | ||
247 | -- | ||
248 | 1.7.10 | ||
249 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch deleted file mode 100644 index 724477f..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | From 589511bd8e847c1990216aa89e56dca0fabac4e2 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Tue, 1 May 2012 11:09:47 +0000 | ||
4 | Subject: [PATCH 49/56] i.MX28: Shut down the LCD controller before reset | ||
5 | |||
6 | If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF | ||
7 | data pins interferes with the BootROM's boot mode sampling. So shut the | ||
8 | controller down. | ||
9 | |||
10 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
11 | Cc: Detlev Zundel <dzu@denx.de> | ||
12 | Cc: Fabio Estevam <festevam@gmail.com> | ||
13 | Cc: Stefano Babic <sbabic@denx.de> | ||
14 | Cc: Wolfgang Denk <wd@denx.de> | ||
15 | --- | ||
16 | arch/arm/cpu/arm926ejs/mx28/mx28.c | 9 ++++++++- | ||
17 | 1 file changed, 8 insertions(+), 1 deletion(-) | ||
18 | |||
19 | diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
20 | index 865dbb3..a82ff25 100644 | ||
21 | --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
22 | +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c | ||
23 | @@ -51,9 +51,16 @@ void reset_cpu(ulong ignored) __attribute__((noreturn)); | ||
24 | |||
25 | void reset_cpu(ulong ignored) | ||
26 | { | ||
27 | - | ||
28 | struct mx28_rtc_regs *rtc_regs = | ||
29 | (struct mx28_rtc_regs *)MXS_RTC_BASE; | ||
30 | + struct mx28_lcdif_regs *lcdif_regs = | ||
31 | + (struct mx28_lcdif_regs *)MXS_LCDIF_BASE; | ||
32 | + | ||
33 | + /* | ||
34 | + * Shut down the LCD controller as it interferes with BootROM boot mode | ||
35 | + * pads sampling. | ||
36 | + */ | ||
37 | + writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); | ||
38 | |||
39 | /* Wait 1 uS before doing the actual watchdog reset */ | ||
40 | writel(1, &rtc_regs->hw_rtc_watchdog); | ||
41 | -- | ||
42 | 1.7.10 | ||
43 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch deleted file mode 100644 index 0717e16..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0050-i.MX28-Add-LRADC-register-definitions.patch +++ /dev/null | |||
@@ -1,437 +0,0 @@ | |||
1 | From dfc17c49a75e682b9ef56985bdb5793863019f6b Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marek.vasut@gmail.com> | ||
3 | Date: Tue, 1 May 2012 11:09:48 +0000 | ||
4 | Subject: [PATCH 50/56] i.MX28: Add LRADC register definitions | ||
5 | |||
6 | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> | ||
7 | Cc: Detlev Zundel <dzu@denx.de> | ||
8 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | Cc: Stefano Babic <sbabic@denx.de> | ||
10 | Cc: Wolfgang Denk <wd@denx.de> | ||
11 | --- | ||
12 | arch/arm/include/asm/arch-mx28/imx-regs.h | 1 + | ||
13 | arch/arm/include/asm/arch-mx28/regs-lradc.h | 400 +++++++++++++++++++++++++++ | ||
14 | 2 files changed, 401 insertions(+) | ||
15 | create mode 100644 arch/arm/include/asm/arch-mx28/regs-lradc.h | ||
16 | |||
17 | diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h | ||
18 | index 581bf0a..37d0a93 100644 | ||
19 | --- a/arch/arm/include/asm/arch-mx28/imx-regs.h | ||
20 | +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h | ||
21 | @@ -31,6 +31,7 @@ | ||
22 | #include <asm/arch/regs-gpmi.h> | ||
23 | #include <asm/arch/regs-i2c.h> | ||
24 | #include <asm/arch/regs-lcdif.h> | ||
25 | +#include <asm/arch/regs-lradc.h> | ||
26 | #include <asm/arch/regs-ocotp.h> | ||
27 | #include <asm/arch/regs-pinctrl.h> | ||
28 | #include <asm/arch/regs-power.h> | ||
29 | diff --git a/arch/arm/include/asm/arch-mx28/regs-lradc.h b/arch/arm/include/asm/arch-mx28/regs-lradc.h | ||
30 | new file mode 100644 | ||
31 | index 0000000..16e2bbf | ||
32 | --- /dev/null | ||
33 | +++ b/arch/arm/include/asm/arch-mx28/regs-lradc.h | ||
34 | @@ -0,0 +1,400 @@ | ||
35 | +/* | ||
36 | + * Freescale i.MX28 LRADC Register Definitions | ||
37 | + * | ||
38 | + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | ||
39 | + * on behalf of DENX Software Engineering GmbH | ||
40 | + * | ||
41 | + * Based on code from LTIB: | ||
42 | + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | ||
43 | + * | ||
44 | + * This program is free software; you can redistribute it and/or modify | ||
45 | + * it under the terms of the GNU General Public License as published by | ||
46 | + * the Free Software Foundation; either version 2 of the License, or | ||
47 | + * (at your option) any later version. | ||
48 | + * | ||
49 | + * This program is distributed in the hope that it will be useful, | ||
50 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
51 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
52 | + * GNU General Public License for more details. | ||
53 | + * | ||
54 | + * You should have received a copy of the GNU General Public License | ||
55 | + * along with this program; if not, write to the Free Software | ||
56 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
57 | + * | ||
58 | + */ | ||
59 | + | ||
60 | +#ifndef __MX28_REGS_LRADC_H__ | ||
61 | +#define __MX28_REGS_LRADC_H__ | ||
62 | + | ||
63 | +#include <asm/arch/regs-common.h> | ||
64 | + | ||
65 | +#ifndef __ASSEMBLY__ | ||
66 | +struct mx28_lradc_regs { | ||
67 | + mx28_reg_32(hw_lradc_ctrl0); | ||
68 | + mx28_reg_32(hw_lradc_ctrl1); | ||
69 | + mx28_reg_32(hw_lradc_ctrl2); | ||
70 | + mx28_reg_32(hw_lradc_ctrl3); | ||
71 | + mx28_reg_32(hw_lradc_status); | ||
72 | + mx28_reg_32(hw_lradc_ch0); | ||
73 | + mx28_reg_32(hw_lradc_ch1); | ||
74 | + mx28_reg_32(hw_lradc_ch2); | ||
75 | + mx28_reg_32(hw_lradc_ch3); | ||
76 | + mx28_reg_32(hw_lradc_ch4); | ||
77 | + mx28_reg_32(hw_lradc_ch5); | ||
78 | + mx28_reg_32(hw_lradc_ch6); | ||
79 | + mx28_reg_32(hw_lradc_ch7); | ||
80 | + mx28_reg_32(hw_lradc_delay0); | ||
81 | + mx28_reg_32(hw_lradc_delay1); | ||
82 | + mx28_reg_32(hw_lradc_delay2); | ||
83 | + mx28_reg_32(hw_lradc_delay3); | ||
84 | + mx28_reg_32(hw_lradc_debug0); | ||
85 | + mx28_reg_32(hw_lradc_debug1); | ||
86 | + mx28_reg_32(hw_lradc_conversion); | ||
87 | + mx28_reg_32(hw_lradc_ctrl4); | ||
88 | + mx28_reg_32(hw_lradc_treshold0); | ||
89 | + mx28_reg_32(hw_lradc_treshold1); | ||
90 | + mx28_reg_32(hw_lradc_version); | ||
91 | +}; | ||
92 | +#endif | ||
93 | + | ||
94 | +#define LRADC_CTRL0_SFTRST (1 << 31) | ||
95 | +#define LRADC_CTRL0_CLKGATE (1 << 30) | ||
96 | +#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) | ||
97 | +#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) | ||
98 | +#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) | ||
99 | +#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) | ||
100 | +#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) | ||
101 | +#define LRADC_CTRL0_YNLRSW (1 << 21) | ||
102 | +#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) | ||
103 | +#define LRADC_CTRL0_YPLLSW_OFFSET 19 | ||
104 | +#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) | ||
105 | +#define LRADC_CTRL0_XNURSW_OFFSET 17 | ||
106 | +#define LRADC_CTRL0_XPULSW (1 << 16) | ||
107 | +#define LRADC_CTRL0_SCHEDULE_MASK 0xff | ||
108 | +#define LRADC_CTRL0_SCHEDULE_OFFSET 0 | ||
109 | + | ||
110 | +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) | ||
111 | +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) | ||
112 | +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) | ||
113 | +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) | ||
114 | +#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) | ||
115 | +#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) | ||
116 | +#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) | ||
117 | +#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) | ||
118 | +#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) | ||
119 | +#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) | ||
120 | +#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) | ||
121 | +#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) | ||
122 | +#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) | ||
123 | +#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) | ||
124 | +#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) | ||
125 | +#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) | ||
126 | +#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) | ||
127 | +#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) | ||
128 | +#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) | ||
129 | +#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) | ||
130 | +#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) | ||
131 | +#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) | ||
132 | +#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) | ||
133 | +#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) | ||
134 | +#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) | ||
135 | +#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) | ||
136 | + | ||
137 | +#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) | ||
138 | +#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 | ||
139 | +#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) | ||
140 | +#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) | ||
141 | +#define LRADC_CTRL2_VTHSENSE_OFFSET 13 | ||
142 | +#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) | ||
143 | +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) | ||
144 | +#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) | ||
145 | +#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) | ||
146 | +#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 | ||
147 | +#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) | ||
148 | +#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) | ||
149 | +#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) | ||
150 | +#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) | ||
151 | +#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) | ||
152 | +#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) | ||
153 | +#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) | ||
154 | +#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) | ||
155 | +#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) | ||
156 | +#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) | ||
157 | +#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) | ||
158 | +#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) | ||
159 | +#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) | ||
160 | +#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) | ||
161 | +#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) | ||
162 | +#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) | ||
163 | +#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) | ||
164 | +#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 | ||
165 | +#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) | ||
166 | +#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) | ||
167 | +#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) | ||
168 | +#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) | ||
169 | +#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) | ||
170 | +#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) | ||
171 | +#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) | ||
172 | +#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) | ||
173 | +#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) | ||
174 | +#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) | ||
175 | +#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) | ||
176 | +#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) | ||
177 | +#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) | ||
178 | +#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) | ||
179 | +#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) | ||
180 | +#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) | ||
181 | + | ||
182 | +#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) | ||
183 | +#define LRADC_CTRL3_DISCARD_OFFSET 24 | ||
184 | +#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) | ||
185 | +#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) | ||
186 | +#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) | ||
187 | +#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) | ||
188 | +#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) | ||
189 | +#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) | ||
190 | +#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 | ||
191 | +#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) | ||
192 | +#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) | ||
193 | +#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) | ||
194 | +#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) | ||
195 | +#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) | ||
196 | +#define LRADC_CTRL3_HIGH_TIME_OFFSET 4 | ||
197 | +#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) | ||
198 | +#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) | ||
199 | +#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) | ||
200 | +#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) | ||
201 | +#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) | ||
202 | +#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) | ||
203 | + | ||
204 | +#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) | ||
205 | +#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) | ||
206 | +#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) | ||
207 | +#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) | ||
208 | +#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) | ||
209 | +#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) | ||
210 | +#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) | ||
211 | +#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) | ||
212 | +#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) | ||
213 | +#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) | ||
214 | +#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) | ||
215 | +#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) | ||
216 | +#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) | ||
217 | +#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) | ||
218 | +#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) | ||
219 | +#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) | ||
220 | + | ||
221 | +#define LRADC_CH_TOGGLE (1 << 31) | ||
222 | +#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) | ||
223 | +#define LRADC_CH_ACCUMULATE (1 << 29) | ||
224 | +#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) | ||
225 | +#define LRADC_CH_NUM_SAMPLES_OFFSET 24 | ||
226 | +#define LRADC_CH_VALUE_MASK 0x3ffff | ||
227 | +#define LRADC_CH_VALUE_OFFSET 0 | ||
228 | + | ||
229 | +#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) | ||
230 | +#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 | ||
231 | +#define LRADC_DELAY_KICK (1 << 20) | ||
232 | +#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) | ||
233 | +#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 | ||
234 | +#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) | ||
235 | +#define LRADC_DELAY_LOOP_COUNT_OFFSET 11 | ||
236 | +#define LRADC_DELAY_DELAY_MASK 0x7ff | ||
237 | +#define LRADC_DELAY_DELAY_OFFSET 0 | ||
238 | + | ||
239 | +#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) | ||
240 | +#define LRADC_DEBUG0_READONLY_OFFSET 16 | ||
241 | +#define LRADC_DEBUG0_STATE_MASK (0xfff << 0) | ||
242 | +#define LRADC_DEBUG0_STATE_OFFSET 0 | ||
243 | + | ||
244 | +#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) | ||
245 | +#define LRADC_DEBUG1_REQUEST_OFFSET 16 | ||
246 | +#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) | ||
247 | +#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 | ||
248 | +#define LRADC_DEBUG1_TESTMODE6 (1 << 2) | ||
249 | +#define LRADC_DEBUG1_TESTMODE5 (1 << 1) | ||
250 | +#define LRADC_DEBUG1_TESTMODE (1 << 0) | ||
251 | + | ||
252 | +#define LRADC_CONVERSION_AUTOMATIC (1 << 20) | ||
253 | +#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) | ||
254 | +#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 | ||
255 | +#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) | ||
256 | +#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) | ||
257 | +#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) | ||
258 | +#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) | ||
259 | +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff | ||
260 | +#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 | ||
261 | + | ||
262 | +#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) | ||
263 | +#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 | ||
264 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) | ||
265 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) | ||
266 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) | ||
267 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) | ||
268 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) | ||
269 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) | ||
270 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) | ||
271 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) | ||
272 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) | ||
273 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) | ||
274 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) | ||
275 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) | ||
276 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) | ||
277 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) | ||
278 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) | ||
279 | +#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) | ||
280 | +#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) | ||
281 | +#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 | ||
282 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) | ||
283 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) | ||
284 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) | ||
285 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) | ||
286 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) | ||
287 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) | ||
288 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) | ||
289 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) | ||
290 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) | ||
291 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) | ||
292 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) | ||
293 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) | ||
294 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) | ||
295 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) | ||
296 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) | ||
297 | +#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) | ||
298 | +#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) | ||
299 | +#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 | ||
300 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) | ||
301 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) | ||
302 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) | ||
303 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) | ||
304 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) | ||
305 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) | ||
306 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) | ||
307 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) | ||
308 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) | ||
309 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) | ||
310 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) | ||
311 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) | ||
312 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) | ||
313 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) | ||
314 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) | ||
315 | +#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) | ||
316 | +#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) | ||
317 | +#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 | ||
318 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) | ||
319 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) | ||
320 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) | ||
321 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) | ||
322 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) | ||
323 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) | ||
324 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) | ||
325 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) | ||
326 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) | ||
327 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) | ||
328 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) | ||
329 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) | ||
330 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) | ||
331 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) | ||
332 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) | ||
333 | +#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) | ||
334 | +#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) | ||
335 | +#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 | ||
336 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) | ||
337 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) | ||
338 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) | ||
339 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) | ||
340 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) | ||
341 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) | ||
342 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) | ||
343 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) | ||
344 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) | ||
345 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) | ||
346 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) | ||
347 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) | ||
348 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) | ||
349 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) | ||
350 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) | ||
351 | +#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) | ||
352 | +#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) | ||
353 | +#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 | ||
354 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) | ||
355 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) | ||
356 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) | ||
357 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) | ||
358 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) | ||
359 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) | ||
360 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) | ||
361 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) | ||
362 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) | ||
363 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) | ||
364 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) | ||
365 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) | ||
366 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) | ||
367 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) | ||
368 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) | ||
369 | +#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) | ||
370 | +#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) | ||
371 | +#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 | ||
372 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) | ||
373 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) | ||
374 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) | ||
375 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) | ||
376 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) | ||
377 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) | ||
378 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) | ||
379 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) | ||
380 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) | ||
381 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) | ||
382 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) | ||
383 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) | ||
384 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) | ||
385 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) | ||
386 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) | ||
387 | +#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) | ||
388 | +#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf | ||
389 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) | ||
390 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) | ||
391 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) | ||
392 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) | ||
393 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) | ||
394 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) | ||
395 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) | ||
396 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) | ||
397 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) | ||
398 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) | ||
399 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) | ||
400 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) | ||
401 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) | ||
402 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) | ||
403 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) | ||
404 | +#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) | ||
405 | + | ||
406 | +#define LRADC_THRESHOLD_ENABLE (1 << 24) | ||
407 | +#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) | ||
408 | +#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) | ||
409 | +#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 | ||
410 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) | ||
411 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) | ||
412 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) | ||
413 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) | ||
414 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) | ||
415 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) | ||
416 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) | ||
417 | +#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) | ||
418 | +#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) | ||
419 | +#define LRADC_THRESHOLD_SETTING_OFFSET 18 | ||
420 | +#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) | ||
421 | +#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) | ||
422 | +#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) | ||
423 | +#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) | ||
424 | +#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff | ||
425 | +#define LRADC_THRESHOLD_VALUE_OFFSET 0 | ||
426 | + | ||
427 | +#define LRADC_VERSION_MAJOR_MASK (0xff << 24) | ||
428 | +#define LRADC_VERSION_MAJOR_OFFSET 24 | ||
429 | +#define LRADC_VERSION_MINOR_MASK (0xff << 16) | ||
430 | +#define LRADC_VERSION_MINOR_OFFSET 16 | ||
431 | +#define LRADC_VERSION_STEP_MASK 0xffff | ||
432 | +#define LRADC_VERSION_STEP_OFFSET 0 | ||
433 | + | ||
434 | +#endif /* __MX28_REGS_LRADC_H__ */ | ||
435 | -- | ||
436 | 1.7.10 | ||
437 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch deleted file mode 100644 index 5141781..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch +++ /dev/null | |||
@@ -1,168 +0,0 @@ | |||
1 | From c9d426383e2d672d72e646801cbe19fea9653cba Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marek.vasut@gmail.com> | ||
3 | Date: Tue, 1 May 2012 11:09:49 +0000 | ||
4 | Subject: [PATCH 51/56] i.MX28: Add LRADC init to i.MX28 SPL | ||
5 | |||
6 | This code is part of battery boot support for i.MX28. | ||
7 | |||
8 | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> | ||
9 | Cc: Detlev Zundel <dzu@denx.de> | ||
10 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
11 | Cc: Stefano Babic <sbabic@denx.de> | ||
12 | Cc: Wolfgang Denk <wd@denx.de> | ||
13 | --- | ||
14 | arch/arm/cpu/arm926ejs/mx28/Makefile | 2 +- | ||
15 | arch/arm/cpu/arm926ejs/mx28/mx28_init.h | 3 + | ||
16 | arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c | 86 ++++++++++++++++++++++++++ | ||
17 | arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 10 +++ | ||
18 | 4 files changed, 100 insertions(+), 1 deletion(-) | ||
19 | create mode 100644 arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c | ||
20 | |||
21 | diff --git a/arch/arm/cpu/arm926ejs/mx28/Makefile b/arch/arm/cpu/arm926ejs/mx28/Makefile | ||
22 | index a2e3f77..674a3af 100644 | ||
23 | --- a/arch/arm/cpu/arm926ejs/mx28/Makefile | ||
24 | +++ b/arch/arm/cpu/arm926ejs/mx28/Makefile | ||
25 | @@ -28,7 +28,7 @@ LIB = $(obj)lib$(SOC).o | ||
26 | COBJS = clock.o mx28.o iomux.o timer.o | ||
27 | |||
28 | ifdef CONFIG_SPL_BUILD | ||
29 | -COBJS += spl_boot.o spl_mem_init.o spl_power_init.o | ||
30 | +COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o | ||
31 | endif | ||
32 | |||
33 | SRCS := $(START:.o=.S) $(COBJS:.o=.c) | ||
34 | diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h | ||
35 | index 8eac958..e3a4493 100644 | ||
36 | --- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h | ||
37 | +++ b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h | ||
38 | @@ -39,4 +39,7 @@ static inline void mx28_power_wait_pswitch(void) { } | ||
39 | void mx28_mem_init(void); | ||
40 | uint32_t mx28_mem_get_size(void); | ||
41 | |||
42 | +void mx28_lradc_init(void); | ||
43 | +void mx28_lradc_enable_batt_measurement(void); | ||
44 | + | ||
45 | #endif /* __M28_INIT_H__ */ | ||
46 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c | ||
47 | new file mode 100644 | ||
48 | index 0000000..88a603c | ||
49 | --- /dev/null | ||
50 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c | ||
51 | @@ -0,0 +1,86 @@ | ||
52 | +/* | ||
53 | + * Freescale i.MX28 Battery measurement init | ||
54 | + * | ||
55 | + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | ||
56 | + * on behalf of DENX Software Engineering GmbH | ||
57 | + * | ||
58 | + * See file CREDITS for list of people who contributed to this | ||
59 | + * project. | ||
60 | + * | ||
61 | + * This program is free software; you can redistribute it and/or | ||
62 | + * modify it under the terms of the GNU General Public License as | ||
63 | + * published by the Free Software Foundation; either version 2 of | ||
64 | + * the License, or (at your option) any later version. | ||
65 | + * | ||
66 | + * This program is distributed in the hope that it will be useful, | ||
67 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
68 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
69 | + * GNU General Public License for more details. | ||
70 | + * | ||
71 | + * You should have received a copy of the GNU General Public License | ||
72 | + * along with this program; if not, write to the Free Software | ||
73 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
74 | + * MA 02111-1307 USA | ||
75 | + */ | ||
76 | + | ||
77 | +#include <common.h> | ||
78 | +#include <config.h> | ||
79 | +#include <asm/io.h> | ||
80 | +#include <asm/arch/imx-regs.h> | ||
81 | + | ||
82 | +#include "mx28_init.h" | ||
83 | + | ||
84 | +void mx28_lradc_init(void) | ||
85 | +{ | ||
86 | + struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE; | ||
87 | + | ||
88 | + writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr); | ||
89 | + writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr); | ||
90 | + writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr); | ||
91 | + | ||
92 | + clrsetbits_le32(®s->hw_lradc_ctrl3, | ||
93 | + LRADC_CTRL3_CYCLE_TIME_MASK, | ||
94 | + LRADC_CTRL3_CYCLE_TIME_6MHZ); | ||
95 | + | ||
96 | + clrsetbits_le32(®s->hw_lradc_ctrl4, | ||
97 | + LRADC_CTRL4_LRADC7SELECT_MASK | | ||
98 | + LRADC_CTRL4_LRADC6SELECT_MASK, | ||
99 | + LRADC_CTRL4_LRADC7SELECT_CHANNEL7 | | ||
100 | + LRADC_CTRL4_LRADC6SELECT_CHANNEL10); | ||
101 | +} | ||
102 | + | ||
103 | +void mx28_lradc_enable_batt_measurement(void) | ||
104 | +{ | ||
105 | + struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE; | ||
106 | + | ||
107 | + /* Check if the channel is present at all. */ | ||
108 | + if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) | ||
109 | + return; | ||
110 | + | ||
111 | + writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr); | ||
112 | + writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr); | ||
113 | + | ||
114 | + clrsetbits_le32(®s->hw_lradc_conversion, | ||
115 | + LRADC_CONVERSION_SCALE_FACTOR_MASK, | ||
116 | + LRADC_CONVERSION_SCALE_FACTOR_LI_ION); | ||
117 | + writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set); | ||
118 | + | ||
119 | + /* Configure the channel. */ | ||
120 | + writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, | ||
121 | + ®s->hw_lradc_ctrl2_clr); | ||
122 | + writel(0xffffffff, ®s->hw_lradc_ch7_clr); | ||
123 | + clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK); | ||
124 | + writel(LRADC_CH_ACCUMULATE, ®s->hw_lradc_ch7_clr); | ||
125 | + | ||
126 | + /* Schedule the channel. */ | ||
127 | + writel(1 << 7, ®s->hw_lradc_ctrl0_set); | ||
128 | + | ||
129 | + /* Start the channel sampling. */ | ||
130 | + writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) | | ||
131 | + ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) | | ||
132 | + 100, ®s->hw_lradc_delay3); | ||
133 | + | ||
134 | + writel(0xffffffff, ®s->hw_lradc_ch7_clr); | ||
135 | + | ||
136 | + writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set); | ||
137 | +} | ||
138 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
139 | index aa4117d..dfb62eb 100644 | ||
140 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
141 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
142 | @@ -883,6 +883,13 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) | ||
143 | new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); | ||
144 | } | ||
145 | |||
146 | +void mx28_setup_batt_detect(void) | ||
147 | +{ | ||
148 | + mx28_lradc_init(); | ||
149 | + mx28_lradc_enable_batt_measurement(); | ||
150 | + early_delay(10); | ||
151 | +} | ||
152 | + | ||
153 | void mx28_power_init(void) | ||
154 | { | ||
155 | struct mx28_power_regs *power_regs = | ||
156 | @@ -892,6 +899,9 @@ void mx28_power_init(void) | ||
157 | mx28_power_clear_auto_restart(); | ||
158 | mx28_power_set_linreg(); | ||
159 | mx28_power_setup_5v_detect(); | ||
160 | + | ||
161 | + mx28_setup_batt_detect(); | ||
162 | + | ||
163 | mx28_power_configure_power_source(); | ||
164 | mx28_enable_output_rail_protection(); | ||
165 | |||
166 | -- | ||
167 | 1.7.10 | ||
168 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch deleted file mode 100644 index 6c7d89a..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch +++ /dev/null | |||
@@ -1,162 +0,0 @@ | |||
1 | From cd97dc62732fe84ee4a979e002515c89f37fc477 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marek.vasut@gmail.com> | ||
3 | Date: Tue, 1 May 2012 11:09:50 +0000 | ||
4 | Subject: [PATCH 52/56] i.MX28: Reorder battery status functions in SPL | ||
5 | |||
6 | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> | ||
7 | Cc: Detlev Zundel <dzu@denx.de> | ||
8 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | Cc: Stefano Babic <sbabic@denx.de> | ||
10 | Cc: Wolfgang Denk <wd@denx.de> | ||
11 | --- | ||
12 | arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 120 ++++++++++++-------------- | ||
13 | 1 file changed, 56 insertions(+), 64 deletions(-) | ||
14 | |||
15 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
16 | index dfb62eb..ac942b4 100644 | ||
17 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
18 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
19 | @@ -104,6 +104,62 @@ void mx28_power_set_linreg(void) | ||
20 | POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); | ||
21 | } | ||
22 | |||
23 | +int mx28_get_batt_volt(void) | ||
24 | +{ | ||
25 | + struct mx28_power_regs *power_regs = | ||
26 | + (struct mx28_power_regs *)MXS_POWER_BASE; | ||
27 | + uint32_t volt = readl(&power_regs->hw_power_battmonitor); | ||
28 | + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; | ||
29 | + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; | ||
30 | + volt *= 8; | ||
31 | + return volt; | ||
32 | +} | ||
33 | + | ||
34 | +int mx28_is_batt_ready(void) | ||
35 | +{ | ||
36 | + return (mx28_get_batt_volt() >= 3600); | ||
37 | +} | ||
38 | + | ||
39 | +int mx28_is_batt_good(void) | ||
40 | +{ | ||
41 | + struct mx28_power_regs *power_regs = | ||
42 | + (struct mx28_power_regs *)MXS_POWER_BASE; | ||
43 | + uint32_t volt = mx28_get_batt_volt(); | ||
44 | + | ||
45 | + if ((volt >= 2400) && (volt <= 4300)) | ||
46 | + return 1; | ||
47 | + | ||
48 | + clrsetbits_le32(&power_regs->hw_power_5vctrl, | ||
49 | + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, | ||
50 | + 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); | ||
51 | + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, | ||
52 | + &power_regs->hw_power_5vctrl_clr); | ||
53 | + | ||
54 | + clrsetbits_le32(&power_regs->hw_power_charge, | ||
55 | + POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, | ||
56 | + POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); | ||
57 | + | ||
58 | + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); | ||
59 | + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, | ||
60 | + &power_regs->hw_power_5vctrl_clr); | ||
61 | + | ||
62 | + early_delay(500000); | ||
63 | + | ||
64 | + volt = mx28_get_batt_volt(); | ||
65 | + | ||
66 | + if (volt >= 3500) | ||
67 | + return 0; | ||
68 | + | ||
69 | + if (volt >= 2400) | ||
70 | + return 1; | ||
71 | + | ||
72 | + writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, | ||
73 | + &power_regs->hw_power_charge_clr); | ||
74 | + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); | ||
75 | + | ||
76 | + return 0; | ||
77 | +} | ||
78 | + | ||
79 | void mx28_power_setup_5v_detect(void) | ||
80 | { | ||
81 | struct mx28_power_regs *power_regs = | ||
82 | @@ -486,22 +542,6 @@ void mx28_handle_5v_conflict(void) | ||
83 | } | ||
84 | } | ||
85 | |||
86 | -int mx28_get_batt_volt(void) | ||
87 | -{ | ||
88 | - struct mx28_power_regs *power_regs = | ||
89 | - (struct mx28_power_regs *)MXS_POWER_BASE; | ||
90 | - uint32_t volt = readl(&power_regs->hw_power_battmonitor); | ||
91 | - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; | ||
92 | - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; | ||
93 | - volt *= 8; | ||
94 | - return volt; | ||
95 | -} | ||
96 | - | ||
97 | -int mx28_is_batt_ready(void) | ||
98 | -{ | ||
99 | - return (mx28_get_batt_volt() >= 3600); | ||
100 | -} | ||
101 | - | ||
102 | void mx28_5v_boot(void) | ||
103 | { | ||
104 | struct mx28_power_regs *power_regs = | ||
105 | @@ -553,54 +593,6 @@ void mx28_switch_vddd_to_dcdc_source(void) | ||
106 | POWER_VDDDCTRL_DISABLE_STEPPING); | ||
107 | } | ||
108 | |||
109 | -int mx28_is_batt_good(void) | ||
110 | -{ | ||
111 | - struct mx28_power_regs *power_regs = | ||
112 | - (struct mx28_power_regs *)MXS_POWER_BASE; | ||
113 | - uint32_t volt; | ||
114 | - | ||
115 | - volt = readl(&power_regs->hw_power_battmonitor); | ||
116 | - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; | ||
117 | - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; | ||
118 | - volt *= 8; | ||
119 | - | ||
120 | - if ((volt >= 2400) && (volt <= 4300)) | ||
121 | - return 1; | ||
122 | - | ||
123 | - clrsetbits_le32(&power_regs->hw_power_5vctrl, | ||
124 | - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, | ||
125 | - 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); | ||
126 | - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, | ||
127 | - &power_regs->hw_power_5vctrl_clr); | ||
128 | - | ||
129 | - clrsetbits_le32(&power_regs->hw_power_charge, | ||
130 | - POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, | ||
131 | - POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); | ||
132 | - | ||
133 | - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); | ||
134 | - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, | ||
135 | - &power_regs->hw_power_5vctrl_clr); | ||
136 | - | ||
137 | - early_delay(500000); | ||
138 | - | ||
139 | - volt = readl(&power_regs->hw_power_battmonitor); | ||
140 | - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; | ||
141 | - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; | ||
142 | - volt *= 8; | ||
143 | - | ||
144 | - if (volt >= 3500) | ||
145 | - return 0; | ||
146 | - | ||
147 | - if (volt >= 2400) | ||
148 | - return 1; | ||
149 | - | ||
150 | - writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, | ||
151 | - &power_regs->hw_power_charge_clr); | ||
152 | - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); | ||
153 | - | ||
154 | - return 0; | ||
155 | -} | ||
156 | - | ||
157 | void mx28_power_configure_power_source(void) | ||
158 | { | ||
159 | mx28_src_power_init(); | ||
160 | -- | ||
161 | 1.7.10 | ||
162 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch deleted file mode 100644 index 8da6d97..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0053-i.MX28-Add-battery-boot-components-to-SPL.patch +++ /dev/null | |||
@@ -1,162 +0,0 @@ | |||
1 | From 2e5adad8385127605c3ad3e3a006d65deeccde38 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marek.vasut@gmail.com> | ||
3 | Date: Tue, 1 May 2012 11:09:51 +0000 | ||
4 | Subject: [PATCH 53/56] i.MX28: Add battery boot components to SPL | ||
5 | |||
6 | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> | ||
7 | Cc: Detlev Zundel <dzu@denx.de> | ||
8 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
9 | Cc: Stefano Babic <sbabic@denx.de> | ||
10 | Cc: Wolfgang Denk <wd@denx.de> | ||
11 | --- | ||
12 | arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 100 +++++++++++++++++++++++--- | ||
13 | 1 file changed, 92 insertions(+), 8 deletions(-) | ||
14 | |||
15 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
16 | index ac942b4..4b09b0c 100644 | ||
17 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
18 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | ||
19 | @@ -45,11 +45,11 @@ void mx28_power_clock2pll(void) | ||
20 | struct mx28_clkctrl_regs *clkctrl_regs = | ||
21 | (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; | ||
22 | |||
23 | - writel(CLKCTRL_PLL0CTRL0_POWER, | ||
24 | - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); | ||
25 | + setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, | ||
26 | + CLKCTRL_PLL0CTRL0_POWER); | ||
27 | early_delay(100); | ||
28 | - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, | ||
29 | - &clkctrl_regs->hw_clkctrl_clkseq_clr); | ||
30 | + setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, | ||
31 | + CLKCTRL_CLKSEQ_BYPASS_CPU); | ||
32 | } | ||
33 | |||
34 | void mx28_power_clear_auto_restart(void) | ||
35 | @@ -455,9 +455,14 @@ void mx28_power_enable_4p2(void) | ||
36 | mx28_power_init_4p2_regulator(); | ||
37 | |||
38 | /* Shutdown battery (none present) */ | ||
39 | - clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); | ||
40 | - writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); | ||
41 | - writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); | ||
42 | + if (!mx28_is_batt_ready()) { | ||
43 | + clrbits_le32(&power_regs->hw_power_dcdc4p2, | ||
44 | + POWER_DCDC4P2_BO_MASK); | ||
45 | + writel(POWER_CTRL_DCDC4P2_BO_IRQ, | ||
46 | + &power_regs->hw_power_ctrl_clr); | ||
47 | + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, | ||
48 | + &power_regs->hw_power_ctrl_clr); | ||
49 | + } | ||
50 | |||
51 | mx28_power_init_dcdc_4p2_source(); | ||
52 | |||
53 | @@ -515,6 +520,50 @@ void mx28_powerdown(void) | ||
54 | &power_regs->hw_power_reset); | ||
55 | } | ||
56 | |||
57 | +void mx28_batt_boot(void) | ||
58 | +{ | ||
59 | + struct mx28_power_regs *power_regs = | ||
60 | + (struct mx28_power_regs *)MXS_POWER_BASE; | ||
61 | + | ||
62 | + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); | ||
63 | + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); | ||
64 | + | ||
65 | + clrbits_le32(&power_regs->hw_power_dcdc4p2, | ||
66 | + POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2); | ||
67 | + writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr); | ||
68 | + | ||
69 | + /* 5V to battery handoff. */ | ||
70 | + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); | ||
71 | + early_delay(30); | ||
72 | + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); | ||
73 | + | ||
74 | + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); | ||
75 | + | ||
76 | + clrsetbits_le32(&power_regs->hw_power_minpwr, | ||
77 | + POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); | ||
78 | + | ||
79 | + mx28_power_set_linreg(); | ||
80 | + | ||
81 | + clrbits_le32(&power_regs->hw_power_vdddctrl, | ||
82 | + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG); | ||
83 | + | ||
84 | + clrbits_le32(&power_regs->hw_power_vddactrl, | ||
85 | + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG); | ||
86 | + | ||
87 | + clrbits_le32(&power_regs->hw_power_vddioctrl, | ||
88 | + POWER_VDDIOCTRL_DISABLE_FET); | ||
89 | + | ||
90 | + setbits_le32(&power_regs->hw_power_5vctrl, | ||
91 | + POWER_5VCTRL_PWD_CHARGE_4P2_MASK); | ||
92 | + | ||
93 | + setbits_le32(&power_regs->hw_power_5vctrl, | ||
94 | + POWER_5VCTRL_ENABLE_DCDC); | ||
95 | + | ||
96 | + clrsetbits_le32(&power_regs->hw_power_5vctrl, | ||
97 | + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, | ||
98 | + 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); | ||
99 | +} | ||
100 | + | ||
101 | void mx28_handle_5v_conflict(void) | ||
102 | { | ||
103 | struct mx28_power_regs *power_regs = | ||
104 | @@ -539,6 +588,11 @@ void mx28_handle_5v_conflict(void) | ||
105 | mx28_powerdown(); | ||
106 | break; | ||
107 | } | ||
108 | + | ||
109 | + if (tmp & POWER_STS_PSWITCH_MASK) { | ||
110 | + mx28_batt_boot(); | ||
111 | + break; | ||
112 | + } | ||
113 | } | ||
114 | } | ||
115 | |||
116 | @@ -595,12 +649,42 @@ void mx28_switch_vddd_to_dcdc_source(void) | ||
117 | |||
118 | void mx28_power_configure_power_source(void) | ||
119 | { | ||
120 | + int batt_ready, batt_good; | ||
121 | + struct mx28_power_regs *power_regs = | ||
122 | + (struct mx28_power_regs *)MXS_POWER_BASE; | ||
123 | + struct mx28_lradc_regs *lradc_regs = | ||
124 | + (struct mx28_lradc_regs *)MXS_LRADC_BASE; | ||
125 | + | ||
126 | mx28_src_power_init(); | ||
127 | |||
128 | - mx28_5v_boot(); | ||
129 | + batt_ready = mx28_is_batt_ready(); | ||
130 | + | ||
131 | + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { | ||
132 | + batt_good = mx28_is_batt_good(); | ||
133 | + if (batt_ready) { | ||
134 | + /* 5V source detected, good battery detected. */ | ||
135 | + mx28_batt_boot(); | ||
136 | + } else { | ||
137 | + if (batt_good) { | ||
138 | + /* 5V source detected, low battery detceted. */ | ||
139 | + } else { | ||
140 | + /* 5V source detected, bad battery detected. */ | ||
141 | + writel(LRADC_CONVERSION_AUTOMATIC, | ||
142 | + &lradc_regs->hw_lradc_conversion_clr); | ||
143 | + clrbits_le32(&power_regs->hw_power_battmonitor, | ||
144 | + POWER_BATTMONITOR_BATT_VAL_MASK); | ||
145 | + } | ||
146 | + mx28_5v_boot(); | ||
147 | + } | ||
148 | + } else { | ||
149 | + /* 5V not detected, booting from battery. */ | ||
150 | + mx28_batt_boot(); | ||
151 | + } | ||
152 | + | ||
153 | mx28_power_clock2pll(); | ||
154 | |||
155 | mx28_init_batt_bo(); | ||
156 | + | ||
157 | mx28_switch_vddd_to_dcdc_source(); | ||
158 | } | ||
159 | |||
160 | -- | ||
161 | 1.7.10 | ||
162 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch deleted file mode 100644 index 476ab90..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | From a79af9bfd334db959881ebbe917976ebc7824c35 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Tue, 1 May 2012 11:09:52 +0000 | ||
4 | Subject: [PATCH 54/56] i.MX28: Check if WP detection is implemented at all | ||
5 | |||
6 | If the WP function is NULL, simply assume the card is always RW. | ||
7 | |||
8 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
9 | Cc: Stefano Babic <sbabic@denx.de> | ||
10 | Cc: Wolfgang Denk <wd@denx.de> | ||
11 | Cc: Detlev Zundel <dzu@denx.de> | ||
12 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
13 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
14 | --- | ||
15 | drivers/mmc/mxsmmc.c | 3 ++- | ||
16 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c | ||
19 | index 35c6bda..c7200ee 100644 | ||
20 | --- a/drivers/mmc/mxsmmc.c | ||
21 | +++ b/drivers/mmc/mxsmmc.c | ||
22 | @@ -133,7 +133,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) | ||
23 | /* READ or WRITE */ | ||
24 | if (data->flags & MMC_DATA_READ) { | ||
25 | ctrl0 |= SSP_CTRL0_READ; | ||
26 | - } else if (priv->mmc_is_wp(mmc->block_dev.dev)) { | ||
27 | + } else if (priv->mmc_is_wp && | ||
28 | + priv->mmc_is_wp(mmc->block_dev.dev)) { | ||
29 | printf("MMC%d: Can not write a locked card!\n", | ||
30 | mmc->block_dev.dev); | ||
31 | return UNUSABLE_ERR; | ||
32 | -- | ||
33 | 1.7.10 | ||
34 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0055-i.MX28-Avoid-redefining-serial_put-cs.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0055-i.MX28-Avoid-redefining-serial_put-cs.patch deleted file mode 100644 index ef237e8..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0055-i.MX28-Avoid-redefining-serial_put-cs.patch +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | From b72b9a019acd1646ad8ae2518c8e7901f4ca8a90 Mon Sep 17 00:00:00 2001 | ||
2 | From: Marek Vasut <marex@denx.de> | ||
3 | Date: Tue, 1 May 2012 11:09:53 +0000 | ||
4 | Subject: [PATCH 55/56] i.MX28: Avoid redefining serial_put[cs]() | ||
5 | |||
6 | Do not define serial_putc() and serial_puts() calls if | ||
7 | CONFIG_SPL_SERIAL_SUPPORT is set. | ||
8 | |||
9 | Signed-off-by: Marek Vasut <marex@denx.de> | ||
10 | Cc: Detlev Zundel <dzu@denx.de> | ||
11 | Cc: Fabio Estevam <fabio.estevam@freescale.com> | ||
12 | Cc: Stefano Babic <sbabic@denx.de> | ||
13 | Cc: Wolfgang Denk <wd@denx.de> | ||
14 | Acked-by: Stefano Babic <sbabic@denx.de> | ||
15 | --- | ||
16 | arch/arm/cpu/arm926ejs/mx28/spl_boot.c | 2 ++ | ||
17 | 1 file changed, 2 insertions(+) | ||
18 | |||
19 | diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
20 | index c9b4566..a6dfca3 100644 | ||
21 | --- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
22 | +++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c | ||
23 | @@ -123,8 +123,10 @@ inline void board_init_r(gd_t *id, ulong dest_addr) | ||
24 | ; | ||
25 | } | ||
26 | |||
27 | +#ifndef CONFIG_SPL_SERIAL_SUPPORT | ||
28 | void serial_putc(const char c) {} | ||
29 | void serial_puts(const char *s) {} | ||
30 | +#endif | ||
31 | void hang(void) __attribute__ ((noreturn)); | ||
32 | void hang(void) | ||
33 | { | ||
34 | -- | ||
35 | 1.7.10 | ||
36 | |||
diff --git a/recipes-bsp/u-boot/u-boot-v2012.04.01/0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch b/recipes-bsp/u-boot/u-boot-v2012.04.01/0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch deleted file mode 100644 index b3946a1..0000000 --- a/recipes-bsp/u-boot/u-boot-v2012.04.01/0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | From 694d7164c05e3b785ac3c7055d0bd605bfc6a5ee Mon Sep 17 00:00:00 2001 | ||
2 | From: Fabio Estevam <fabio.estevam@freescale.com> | ||
3 | Date: Sat, 12 May 2012 14:14:13 -0300 | ||
4 | Subject: [PATCH 56/56] mx28evk: Scan only first 128MB of DRAM to avoid memory | ||
5 | wraparound | ||
6 | |||
7 | Scan only first 128MB of DRAM to avoid memory wraparound. | ||
8 | |||
9 | This fixes mx28evk boot and it follows the same idea of commit | ||
10 | 19a2066b57 (M28: Scan only first 512 MB of DRAM to avoid memory wraparound) | ||
11 | |||
12 | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> | ||
13 | --- | ||
14 | include/configs/mx28evk.h | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h | ||
18 | index 0c18e50..41037fc 100644 | ||
19 | --- a/include/configs/mx28evk.h | ||
20 | +++ b/include/configs/mx28evk.h | ||
21 | @@ -75,7 +75,7 @@ | ||
22 | */ | ||
23 | #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ | ||
24 | #define PHYS_SDRAM_1 0x40000000 /* Base address */ | ||
25 | -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ | ||
26 | +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128MB RAM */ | ||
27 | #define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ | ||
28 | #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ | ||
29 | #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ | ||
30 | -- | ||
31 | 1.7.10 | ||
32 | |||
diff --git a/recipes-bsp/u-boot/u-boot_2012.04.01.bb b/recipes-bsp/u-boot/u-boot_2012.04.01.bb index 0439c6e..96d8d26 100644 --- a/recipes-bsp/u-boot/u-boot_2012.04.01.bb +++ b/recipes-bsp/u-boot/u-boot_2012.04.01.bb | |||
@@ -6,68 +6,12 @@ COMPATIBLE_MACHINE = "(imx28evk|mx5|mx6)" | |||
6 | 6 | ||
7 | DEPENDS_mxs += "elftosb-native" | 7 | DEPENDS_mxs += "elftosb-native" |
8 | 8 | ||
9 | SRCREV = "415d386877df49eb051b85ef74fa59a16dc17c7d" | 9 | SRCREV = "694d7164c05e3b785ac3c7055d0bd605bfc6a5ee" |
10 | 10 | ||
11 | PV = "v2012.04.01" | 11 | PV = "v2012.04.01" |
12 | PR = "r1" | ||
12 | 13 | ||
13 | SRC_URI = "git://git.denx.de/u-boot.git;branch=master;protocol=git \ | 14 | SRC_URI = "git://github.com/Freescale/u-boot-imx.git" |
14 | file://0001-MX5-Add-definitions-for-SATA-controller.patch \ | ||
15 | file://0002-SATA-check-for-return-value-from-sata-functions.patch \ | ||
16 | file://0003-MX53-add-function-to-set-SATA-clock-to-internal.patch \ | ||
17 | file://0004-SATA-add-driver-for-MX5-MX6-SOCs.patch \ | ||
18 | file://0005-MX53-Add-support-to-ESG-ima3-board.patch \ | ||
19 | file://0006-MX53-mx53loco-Add-SATA-support.patch \ | ||
20 | file://0007-pmic-Add-support-for-the-Dialog-DA9053-PMIC.patch \ | ||
21 | file://0008-mx6qsabrelite-No-need-to-set-the-direction-for-GPIO3.patch \ | ||
22 | file://0009-mx28evk-Allow-to-booting-a-dt-kernel.patch \ | ||
23 | file://0010-m28evk-Allow-to-booting-a-dt-kernel.patch \ | ||
24 | file://0011-mx28evk-Allow-booting-a-zImage-kernel.patch \ | ||
25 | file://0012-mx6qsabrelite-Allow-booting-a-zImage-kernel.patch \ | ||
26 | file://0013-mx6qarm2-Allow-booting-a-zImage-kernel.patch \ | ||
27 | file://0014-mx31pdk-Allow-booting-a-zImage-kernel.patch \ | ||
28 | file://0015-i.MX6Q-mx6qsabrelite-Add-keypress-support-to-alter-b.patch \ | ||
29 | file://0016-imx-common-Factor-out-get_ahb_clk.patch \ | ||
30 | file://0017-mx5-Add-clock-config-interface.patch \ | ||
31 | file://0018-mx53loco-Allow-to-print-CPU-information-at-a-later-s.patch \ | ||
32 | file://0019-mx53loco-Add-support-for-1GHz-operation-for-DA9053-b.patch \ | ||
33 | file://0020-M28-Enable-FDT-support.patch \ | ||
34 | file://0021-Revert-i.MX28-Enable-additional-DRAM-address-bits.patch \ | ||
35 | file://0022-M28-Scan-only-first-512-MB-of-DRAM-to-avoid-memory-w.patch \ | ||
36 | file://0023-USB-ehci-mx6-Fix-broken-IO-access.patch \ | ||
37 | file://0024-mx28evk-add-NAND-support.patch \ | ||
38 | file://0025-i.MX6-Add-ANATOP-regulator-init.patch \ | ||
39 | file://0026-i.MX6-add-enable_sata_clock.patch \ | ||
40 | file://0027-i.MX6-mx6q_sabrelite-add-SATA-bindings.patch \ | ||
41 | file://0028-i.MX25-esdhc-Add-mxc_get_clock-infrastructure.patch \ | ||
42 | file://0029-i.MX25-This-architecture-has-a-GPIO4-too.patch \ | ||
43 | file://0030-imx-nand-Support-flash-based-BBT.patch \ | ||
44 | file://0031-i.MX25-usb-Set-PORTSCx-register.patch \ | ||
45 | file://0032-imx-usb-There-is-no-such-register.patch \ | ||
46 | file://0033-i.MX2-Include-asm-types.h-in-arch-mx25-imx-regs.h.patch \ | ||
47 | file://0034-imx-Add-u-boot.imx-as-target-for-ARM9-i.MX-SOCs.patch \ | ||
48 | file://0035-pmic-dialog-Avoid-name-conflicts.patch \ | ||
49 | file://0036-mx53loco-Add-mc34708-support-and-set-mx53-frequency-.patch \ | ||
50 | file://0037-mx53loco-Turn-on-VUSB-regulator.patch \ | ||
51 | file://0038-mx53loco-Add-CONFIG_REVISION_TAG.patch \ | ||
52 | file://0039-mx53loco-Remove-unneeded-gpio_set_value.patch \ | ||
53 | file://0040-spi-mxs-Introduce-spi_cs_is_valid.patch \ | ||
54 | file://0041-spi-mxs-Allow-other-chip-selects-to-work.patch \ | ||
55 | file://0042-i.MX28-Add-delay-after-CPU-bypass-is-cleared.patch \ | ||
56 | file://0043-MX5-PAD_CTL_DRV_VOT_LOW-and-PAD_CTL_DRV_VOT_HIGH-exc.patch \ | ||
57 | file://0044-M28EVK-Implement-support-for-new-board-V2.0.patch \ | ||
58 | file://0045-M28EVK-Add-SD-update-command.patch \ | ||
59 | file://0046-i.MX28-Improve-passing-of-data-from-SPL-to-U-Boot.patch \ | ||
60 | file://0047-i.MX28-Implement-boot-pads-sampling-and-reporting.patch \ | ||
61 | file://0048-i.MX28-Add-LCDIF-register-definitions.patch \ | ||
62 | file://0049-i.MX28-Shut-down-the-LCD-controller-before-reset.patch \ | ||
63 | file://0050-i.MX28-Add-LRADC-register-definitions.patch \ | ||
64 | file://0051-i.MX28-Add-LRADC-init-to-i.MX28-SPL.patch \ | ||
65 | file://0052-i.MX28-Reorder-battery-status-functions-in-SPL.patch \ | ||
66 | file://0053-i.MX28-Add-battery-boot-components-to-SPL.patch \ | ||
67 | file://0054-i.MX28-Check-if-WP-detection-is-implemented-at-all.patch \ | ||
68 | file://0055-i.MX28-Avoid-redefining-serial_put-cs.patch \ | ||
69 | file://0056-mx28evk-Scan-only-first-128MB-of-DRAM-to-avoid-memor.patch \ | ||
70 | " | ||
71 | 15 | ||
72 | S = "${WORKDIR}/git" | 16 | S = "${WORKDIR}/git" |
73 | 17 | ||