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-rw-r--r--recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch3932
1 files changed, 3932 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch b/recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch
new file mode 100644
index 0000000..c8dceb2
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-imx/cgtqmx6/0001-Add-uboot-support-for-congatec-qmx6-board.patch
@@ -0,0 +1,3932 @@
1From a58f89ba75334edcb1759fa174a4d56afe1b55ce Mon Sep 17 00:00:00 2001
2From: Leo Sartre <lsartre@adeneo-embedded.com>
3Date: Wed, 29 May 2013 11:03:07 +0200
4Subject: [PATCH] Add support for congatec qmx6 board
5
6Add support for the Congatec Qseven evaluation board, the patch was
7originally written by Congatec Team, some minor changes and cleanup
8were applied to make it work with the new Freescale BSP 4.0.
9---
10 Makefile | 10 +
11 board/freescale/cgt_qmx6/Makefile | 51 +
12 board/freescale/cgt_qmx6/cgt_qmx6.c | 1726 ++++++++++++++++++++++
13 board/freescale/cgt_qmx6/config.mk | 7 +
14 board/freescale/cgt_qmx6/flash_header.S | 202 +++
15 board/freescale/cgt_qmx6/flash_header_pn016101.S | 202 +++
16 board/freescale/cgt_qmx6/flash_header_pn016104.S | 202 +++
17 board/freescale/cgt_qmx6/lowlevel_init.S | 167 +++
18 board/freescale/cgt_qmx6/u-boot.lds | 74 +
19 common/cmd_mii.c | 17 +
20 drivers/mtd/spi/imx_spi_nor_sst.c | 24 +-
21 include/asm-arm/mach-types.h | 13 +
22 include/configs/cgt_qmx6.h | 364 +++++
23 include/configs/cgt_qmx6_android.h | 360 +++++
24 include/configs/cgt_qmx6_mfg.h | 320 ++++
25 localversion-qmx6 | 1 +
26 16 files changed, 3737 insertions(+), 3 deletions(-)
27 create mode 100644 board/freescale/cgt_qmx6/Makefile
28 create mode 100644 board/freescale/cgt_qmx6/cgt_qmx6.c
29 create mode 100644 board/freescale/cgt_qmx6/config.mk
30 create mode 100644 board/freescale/cgt_qmx6/flash_header.S
31 create mode 100644 board/freescale/cgt_qmx6/flash_header_pn016101.S
32 create mode 100644 board/freescale/cgt_qmx6/flash_header_pn016104.S
33 create mode 100644 board/freescale/cgt_qmx6/lowlevel_init.S
34 create mode 100644 board/freescale/cgt_qmx6/u-boot.lds
35 create mode 100644 include/configs/cgt_qmx6.h
36 create mode 100644 include/configs/cgt_qmx6_android.h
37 create mode 100644 include/configs/cgt_qmx6_mfg.h
38 create mode 100644 localversion-qmx6
39
40diff --git a/Makefile b/Makefile
41index 17c21cd..47e6cbe 100644
42--- a/Makefile
43+++ b/Makefile
44@@ -3205,6 +3205,15 @@ apollon_config : unconfig
45 @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
46 @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
47
48+cgt_qmx6_android_config \
49+cgt_qmx6_mfg_config \
50+cgt_qmx6_config : unconfig
51+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 cgt_qmx6 freescale mx6
52+ @if [ ! "$(shell sed -n '/^#define CONFIG_QMX6_PN0161/p' include/configs/$(@:_config=).h)" ] ; then \
53+ echo "ERROR: No CONFIG_QMX6_PN0161xx entry found." ; \
54+ echo "Please enable product specific configuration in configuration file!" ; \
55+ fi
56+
57 mx23_evk_config : unconfig
58 @$(MKCONFIG) $(@:_config=) arm arm926ejs mx23_evk freescale mx23
59
60@@ -3838,6 +3847,7 @@ grsim_leon2_config : unconfig
61 #########################################################################
62
63 clean:
64+ @rm -f $(obj)board/freescale/cgt_qmx6/flash_header.S
65 @rm -f $(obj)examples/standalone/82559_eeprom \
66 $(obj)examples/standalone/eepro100_eeprom \
67 $(obj)examples/standalone/hello_world \
68diff --git a/board/freescale/cgt_qmx6/Makefile b/board/freescale/cgt_qmx6/Makefile
69new file mode 100644
70index 0000000..fa5e709
71--- /dev/null
72+++ b/board/freescale/cgt_qmx6/Makefile
73@@ -0,0 +1,51 @@
74+#
75+# (C) Copyright 2011 Freescale Semiconductor, Inc.
76+#
77+# This program is free software; you can redistribute it and/or
78+# modify it under the terms of the GNU General Public License as
79+# published by the Free Software Foundation; either version 2 of
80+# the License, or (at your option) any later version.
81+#
82+# This program is distributed in the hope that it will be useful,
83+# but WITHOUT ANY WARRANTY; without even the implied warranty of
84+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
85+# GNU General Public License for more details.
86+#
87+# You should have received a copy of the GNU General Public License
88+# along with this program; if not, write to the Free Software
89+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
90+# MA 02111-1307 USA
91+#
92+
93+include $(TOPDIR)/config.mk
94+
95+LIB = $(obj)lib$(BOARD).a
96+
97+COBJS := $(BOARD).o
98+SOBJS := lowlevel_init.o flash_header.o
99+
100+
101+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
102+OBJS := $(addprefix $(obj),$(COBJS))
103+SOBJS := $(addprefix $(obj),$(SOBJS))
104+
105+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
106+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
107+
108+flash_header.S: flash_header_pn$(CONFIG_QMX6_PN).S
109+ cp flash_header_pn$(CONFIG_QMX6_PN).S flash_header.S
110+
111+clean:
112+ rm -f $(SOBJS) $(OBJS) flash_header.S
113+
114+distclean: clean
115+ rm -f $(LIB) core *.bak .depend
116+
117+#########################################################################
118+
119+# defines $(obj).depend target
120+include $(SRCTREE)/rules.mk
121+
122+sinclude $(obj).depend
123+
124+#########################################################################
125diff --git a/board/freescale/cgt_qmx6/cgt_qmx6.c b/board/freescale/cgt_qmx6/cgt_qmx6.c
126new file mode 100644
127index 0000000..2f47e7e
128--- /dev/null
129+++ b/board/freescale/cgt_qmx6/cgt_qmx6.c
130@@ -0,0 +1,1726 @@
131+/*
132+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
133+ *
134+ * See file CREDITS for list of people who contributed to this
135+ * project.
136+ *
137+ * This program is free software; you can redistribute it and/or
138+ * modify it under the terms of the GNU General Public License as
139+ * published by the Free Software Foundation; either version 2 of
140+ * the License, or (at your option) any later version.
141+ *
142+ * This program is distributed in the hope that it will be useful,
143+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
144+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
145+ * GNU General Public License for more details.
146+ *
147+ * You should have received a copy of the GNU General Public License
148+ * along with this program; if not, write to the Free Software
149+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
150+ * MA 02111-1307 USA
151+ */
152+
153+#include <common.h>
154+#include <asm/io.h>
155+#include <asm/arch/mx6.h>
156+#include <asm/arch/mx6_pins.h>
157+
158+#if defined(CONFIG_SECURE_BOOT)
159+#include <asm/arch/mx6_secure.h>
160+#endif
161+#include <asm/arch/mx6dl_pins.h>
162+#include <asm/arch/iomux-v3.h>
163+#include <asm/arch/regs-anadig.h>
164+#include <asm/errno.h>
165+#ifdef CONFIG_MXC_FEC
166+#include <miiphy.h>
167+#endif
168+#if defined(CONFIG_VIDEO_MX5)
169+#include <asm/imx_pwm.h>
170+#include <linux/list.h>
171+#include <linux/fb.h>
172+#include <linux/mxcfb.h>
173+#include <ipu.h>
174+#include <lcd.h>
175+#endif
176+
177+#ifdef CONFIG_IMX_ECSPI
178+#include <imx_spi.h>
179+#endif
180+
181+#if CONFIG_I2C_MXC
182+#include <i2c.h>
183+#endif
184+
185+#ifdef CONFIG_CMD_MMC
186+#include <mmc.h>
187+#include <fsl_esdhc.h>
188+#endif
189+
190+#ifdef CONFIG_ARCH_MMU
191+#include <asm/mmu.h>
192+#include <asm/arch/mmu.h>
193+#endif
194+
195+#ifdef CONFIG_CMD_CLOCK
196+#include <asm/clock.h>
197+#endif
198+
199+#ifdef CONFIG_CMD_IMXOTP
200+#include <imx_otp.h>
201+#endif
202+
203+#ifdef CONFIG_MXC_GPIO
204+#include <asm/gpio.h>
205+#include <asm/arch/gpio.h>
206+#endif
207+#ifdef CONFIG_ANDROID_RECOVERY
208+#include <recovery.h>
209+#endif
210+
211+#ifdef CONFIG_DWC_AHSATA
212+#include <ahci.h>
213+#endif
214+DECLARE_GLOBAL_DATA_PTR;
215+
216+static enum boot_device boot_dev;
217+
218+void set_gpio_output_val(unsigned base, unsigned mask, unsigned val)
219+{
220+ unsigned reg = readl(base + GPIO_DR);
221+ if (val & 1)
222+ reg |= mask; /* set high */
223+ else
224+ reg &= ~mask; /* clear low */
225+ writel(reg, base + GPIO_DR);
226+
227+ reg = readl(base + GPIO_GDIR);
228+ reg |= mask; /* configure GPIO line as output */
229+ writel(reg, base + GPIO_GDIR);
230+}
231+
232+extern int sata_curr_device;
233+
234+#ifdef CONFIG_VIDEO_MX5
235+extern unsigned char fsl_bmp_reversed_600x400[];
236+extern int fsl_bmp_reversed_600x400_size;
237+extern int g_ipu_hw_rev;
238+
239+#if defined(CONFIG_BMP_8BPP)
240+unsigned short colormap[256];
241+#elif defined(CONFIG_BMP_16BPP)
242+unsigned short colormap[65536];
243+#else
244+unsigned short colormap[16777216];
245+#endif
246+
247+static struct pwm_device pwm0 = {
248+ .pwm_id = 3,
249+ .pwmo_invert = 0,
250+};
251+
252+static int di = 1;
253+
254+extern int ipuv3_fb_init(struct fb_videomode *mode, int di,
255+ int interface_pix_fmt,
256+ ipu_di_clk_parent_t di_clk_parent,
257+ int di_clk_val);
258+
259+static struct fb_videomode lvds_xga = {
260+ "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10,
261+ FB_SYNC_EXT,
262+ FB_VMODE_NONINTERLACED,
263+ 0,
264+};
265+
266+vidinfo_t panel_info;
267+#endif
268+
269+static inline void setup_boot_device(void)
270+{
271+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
272+ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
273+ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
274+
275+ switch (bt_mem_ctl) {
276+ case 0x0:
277+ if (bt_mem_type)
278+ boot_dev = ONE_NAND_BOOT;
279+ else
280+ boot_dev = WEIM_NOR_BOOT;
281+ break;
282+ case 0x2:
283+ boot_dev = SATA_BOOT;
284+ break;
285+ case 0x3:
286+ if (bt_mem_type)
287+ boot_dev = I2C_BOOT;
288+ else
289+ boot_dev = SPI_NOR_BOOT;
290+ break;
291+ case 0x4:
292+ case 0x5:
293+ boot_dev = SD_BOOT;
294+ break;
295+ case 0x6:
296+ case 0x7:
297+ boot_dev = MMC_BOOT;
298+ break;
299+ case 0x8 ... 0xf:
300+ boot_dev = NAND_BOOT;
301+ break;
302+ default:
303+ boot_dev = UNKNOWN_BOOT;
304+ break;
305+ }
306+}
307+
308+enum boot_device get_boot_device(void)
309+{
310+ return boot_dev;
311+}
312+
313+u32 get_board_rev(void)
314+{
315+ return fsl_system_rev;
316+}
317+
318+#ifdef CONFIG_ARCH_MMU
319+void board_mmu_init(void)
320+{
321+ unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
322+ unsigned long i;
323+
324+ /*
325+ * Set the TTB register
326+ */
327+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
328+
329+ /*
330+ * Set the Domain Access Control Register
331+ */
332+ i = ARM_ACCESS_DACR_DEFAULT;
333+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
334+
335+ /*
336+ * First clear all TT entries - ie Set them to Faulting
337+ */
338+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
339+ /* Actual Virtual Size Attributes Function */
340+ /* Base Base MB cached? buffered? access permissions */
341+ /* xxx00000 xxx00000 */
342+ X_ARM_MMU_SECTION(0x000, 0x000, 0x001,
343+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
344+ ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
345+ X_ARM_MMU_SECTION(0x001, 0x001, 0x008,
346+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
347+ ARM_ACCESS_PERM_RW_RW); /* 8M */
348+ X_ARM_MMU_SECTION(0x009, 0x009, 0x001,
349+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
350+ ARM_ACCESS_PERM_RW_RW); /* IRAM */
351+ X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
352+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
353+ ARM_ACCESS_PERM_RW_RW); /* 246M */
354+
355+ #ifdef CONFIG_QMX6_PN016104
356+ /* 2 GB memory starting at 0x10000000, only map 1.875 GB */
357+ X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
358+ ARM_CACHEABLE, ARM_BUFFERABLE,
359+ ARM_ACCESS_PERM_RW_RW);
360+ /* uncached alias of the same 1.875 GB memory */
361+ X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
362+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
363+ ARM_ACCESS_PERM_RW_RW);
364+ #endif
365+
366+ #ifdef CONFIG_QMX6_PN016101
367+ /* 1 GB memory starting at 0x10000000, only map 0.875 GB */
368+ X_ARM_MMU_SECTION(0x100, 0x100, 0x380,
369+ ARM_CACHEABLE, ARM_BUFFERABLE,
370+ ARM_ACCESS_PERM_RW_RW);
371+ /* uncached alias of the same 0.875 GB memory */
372+ X_ARM_MMU_SECTION(0x100, 0x880, 0x380,
373+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
374+ ARM_ACCESS_PERM_RW_RW);
375+ #endif
376+
377+ /* Enable MMU */
378+ MMU_ON();
379+}
380+#endif
381+
382+#ifdef CONFIG_DWC_AHSATA
383+
384+#define ANATOP_PLL_LOCK 0x80000000
385+#define ANATOP_PLL_ENABLE_MASK 0x00002000
386+#define ANATOP_PLL_BYPASS_MASK 0x00010000
387+#define ANATOP_PLL_LOCK 0x80000000
388+#define ANATOP_PLL_PWDN_MASK 0x00001000
389+#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800
390+#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000
391+
392+/* Staggered Spin-up */
393+#define HOST_CAP_SSS (1 << 27)
394+/* host version register*/
395+#define HOST_VERSIONR 0xfc
396+#define PORT_SATA_SR 0x128
397+#define PORT_PHY_CTL 0x178
398+#define PORT_PHY_CTL_PDDQ_LOC 0x100000
399+
400+int sata_initialize(void)
401+{
402+ u32 reg = 0;
403+ u32 iterations = 1000000;
404+
405+ if (sata_curr_device == -1) {
406+ /* Make sure that the PDDQ mode is disabled. */
407+ reg = readl(SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
408+ writel(reg & (~PORT_PHY_CTL_PDDQ_LOC),
409+ SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
410+
411+ /* Reset HBA */
412+ writel(HOST_RESET, SATA_ARB_BASE_ADDR + HOST_CTL);
413+
414+ reg = 0;
415+ while (readl(SATA_ARB_BASE_ADDR + HOST_VERSIONR) == 0) {
416+ reg++;
417+ if (reg > 1000000)
418+ break;
419+ }
420+
421+ reg = readl(SATA_ARB_BASE_ADDR + HOST_CAP);
422+ if (!(reg & HOST_CAP_SSS)) {
423+ reg |= HOST_CAP_SSS;
424+ writel(reg, SATA_ARB_BASE_ADDR + HOST_CAP);
425+ }
426+
427+ reg = readl(SATA_ARB_BASE_ADDR + HOST_PORTS_IMPL);
428+ if (!(reg & 0x1))
429+ writel((reg | 0x1),
430+ SATA_ARB_BASE_ADDR + HOST_PORTS_IMPL);
431+
432+ /* Release resources when there is no device on the port */
433+ do {
434+ reg = readl(SATA_ARB_BASE_ADDR + PORT_SATA_SR) & 0xF;
435+ if ((reg & 0xF) == 0)
436+ iterations--;
437+ else
438+ break;
439+
440+ } while (iterations > 0);
441+ }
442+
443+ return __sata_initialize();
444+}
445+
446+int setup_sata(void)
447+{
448+ u32 reg = 0;
449+ s32 timeout = 100000;
450+
451+ /* Enable sata clock */
452+ reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */
453+ reg |= 0x30;
454+ writel(reg, CCM_BASE_ADDR + 0x7c);
455+
456+ /* Enable PLLs */
457+ reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */
458+ reg &= ~ANATOP_PLL_PWDN_MASK;
459+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
460+ reg |= ANATOP_PLL_ENABLE_MASK;
461+ while (timeout--) {
462+ if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK)
463+ break;
464+ }
465+ if (timeout <= 0)
466+ return -1;
467+ reg &= ~ANATOP_PLL_BYPASS_MASK;
468+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
469+ reg |= ANATOP_SATA_CLK_ENABLE_MASK;
470+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
471+
472+ /* Enable sata phy */
473+ reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */
474+
475+ reg &= ~0x07ffffff;
476+ /*
477+ * rx_eq_val_0 = 5 [26:24]
478+ * los_lvl = 0x12 [23:19]
479+ * rx_dpll_mode_0 = 0x3 [18:16]
480+ * mpll_ss_en = 0x0 [14]
481+ * tx_atten_0 = 0x4 [13:11]
482+ * tx_boost_0 = 0x0 [10:7]
483+ * tx_lvl = 0x11 [6:2]
484+ * mpll_ck_off_b = 0x1 [1]
485+ * tx_edgerate_0 = 0x0 [0]
486+ * */
487+ reg |= 0x59124c6;
488+ writel(reg, IOMUXC_BASE_ADDR + 0x34);
489+
490+ if (sata_curr_device == -1) {
491+
492+ reg = readl(SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
493+ writel(reg | PORT_PHY_CTL_PDDQ_LOC,
494+ SATA_ARB_BASE_ADDR + PORT_PHY_CTL);
495+ }
496+
497+ return 0;
498+}
499+#endif
500+
501+int dram_init(void)
502+{
503+ /*
504+ * Switch PL301_FAST2 to DDR Dual-channel mapping
505+ * however this block the boot up, temperory redraw
506+ */
507+ /*
508+ * u32 reg = 1;
509+ * writel(reg, GPV0_BASE_ADDR);
510+ */
511+
512+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
513+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
514+
515+ return 0;
516+}
517+
518+static void setup_uart(void)
519+{
520+ /* UART1 & UART2 */
521+#if defined CONFIG_MX6Q
522+#ifndef CONFIG_QMX6_TRACE
523+ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT10__UART1_TXD);
524+ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT11__UART1_RXD);
525+#endif
526+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
527+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
528+#elif defined CONFIG_MX6DL
529+#ifndef CONFIG_QMX6_TRACE
530+ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT10__UART1_TXD);
531+ mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT11__UART1_RXD);
532+#endif
533+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D26__UART2_TXD);
534+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D27__UART2_RXD);
535+#endif
536+}
537+
538+#ifdef CONFIG_VIDEO_MX5
539+void setup_lvds_poweron(void)
540+{
541+ int reg;
542+ /* enable LVDS VDD */
543+#if defined CONFIG_MX6Q
544+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_7__GPIO_1_7);
545+#elif defined CONFIG_MX6DL
546+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_7__GPIO_1_7);
547+#endif
548+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 7), 1);
549+}
550+#endif
551+
552+#ifdef CONFIG_I2C_MXC
553+#define I2C1_SDA_GPIO3_28_BIT_MASK (1 << 28)
554+#define I2C1_SCL_GPIO3_21_BIT_MASK (1 << 21)
555+#define I2C2_SCL_GPIO4_12_BIT_MASK (1 << 12)
556+#define I2C2_SDA_GPIO4_13_BIT_MASK (1 << 13)
557+#define I2C3_SCL_GPIO1_3_BIT_MASK (1 << 3)
558+#define I2C3_SDA_GPIO1_6_BIT_MASK (1 << 6)
559+
560+
561+static void setup_i2c(unsigned int module_base)
562+{
563+ unsigned int reg;
564+
565+ switch (module_base) {
566+ case I2C1_BASE_ADDR:
567+ /* i2c1 SDA & CLK */
568+#if defined CONFIG_MX6Q
569+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D28__I2C1_SDA);
570+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D21__I2C1_SCL);
571+#elif defined CONFIG_MX6DL
572+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D28__I2C1_SDA);
573+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D21__I2C1_SCL);
574+#endif
575+
576+ /* Enable i2c clock */
577+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
578+ reg |= 0xC0;
579+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
580+ break;
581+
582+ case I2C2_BASE_ADDR:
583+ /* i2c2 SDA & CLK */
584+#if defined CONFIG_MX6Q
585+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA);
586+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL);
587+#elif defined CONFIG_MX6DL
588+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW3__I2C2_SDA);
589+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL3__I2C2_SCL);
590+#endif
591+
592+ /* Enable i2c clock */
593+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
594+ reg |= 0x300;
595+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
596+ break;
597+
598+ case I2C3_BASE_ADDR:
599+ /* i2c3 SDA & CLK */
600+#if defined CONFIG_MX6Q
601+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_3__I2C3_SCL);
602+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_6__I2C3_SDA);
603+#elif defined CONFIG_MX6DL
604+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_3__I2C3_SCL);
605+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_6__I2C3_SDA);
606+#endif
607+
608+ /* Enable i2c clock */
609+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
610+ reg |= 0xC00;
611+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
612+ break;
613+
614+ default:
615+ printf("Invalid I2C base: 0x%x\n", module_base);
616+ break;
617+ }
618+}
619+/* Note: udelay() is not accurate for i2c timing */
620+static void __udelay(int time)
621+{
622+ int i, j;
623+
624+ for (i = 0; i < time; i++) {
625+ for (j = 0; j < 200; j++) {
626+ asm("nop");
627+ asm("nop");
628+ }
629+ }
630+}
631+static void mx6q_i2c_gpio_scl_direction(int bus, int output)
632+{
633+ u32 reg;
634+
635+ switch (bus) {
636+ case 1:
637+#if defined CONFIG_MX6Q
638+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D21__GPIO_3_21);
639+#elif defined CONFIG_MX6DL
640+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D21__GPIO_3_21);
641+#endif
642+ reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
643+ if (output)
644+ reg |= I2C1_SCL_GPIO3_21_BIT_MASK;
645+ else
646+ reg &= ~I2C1_SCL_GPIO3_21_BIT_MASK;
647+ writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
648+ break;
649+
650+ case 2:
651+#if defined CONFIG_MX6Q
652+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__GPIO_4_12);
653+#elif defined CONFIG_MX6DL
654+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL3__GPIO_4_12);
655+#endif
656+ reg = readl(GPIO4_BASE_ADDR + GPIO_GDIR);
657+ if (output)
658+ reg |= I2C2_SCL_GPIO4_12_BIT_MASK;
659+ else
660+ reg &= ~I2C2_SCL_GPIO4_12_BIT_MASK;
661+ writel(reg, GPIO4_BASE_ADDR + GPIO_GDIR);
662+ break;
663+
664+ case 3:
665+#if defined CONFIG_MX6Q
666+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_3__GPIO_1_3);
667+#elif defined CONFIG_MX6DL
668+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_3__GPIO_1_3);
669+#endif
670+ reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR);
671+ if (output)
672+ reg |= I2C3_SCL_GPIO1_3_BIT_MASK;
673+ else
674+ reg &= I2C3_SCL_GPIO1_3_BIT_MASK;
675+ writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR);
676+ break;
677+ }
678+}
679+
680+/* set 1 to output, sent 0 to input */
681+static void mx6q_i2c_gpio_sda_direction(int bus, int output)
682+{
683+ u32 reg;
684+
685+ switch (bus) {
686+ case 1:
687+#if defined CONFIG_MX6Q
688+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D28__GPIO_3_28);
689+#elif defined CONFIG_MX6DL
690+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D28__GPIO_3_28);
691+#endif
692+ reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
693+ if (output)
694+ reg |= I2C1_SDA_GPIO3_28_BIT_MASK;
695+ else
696+ reg &= ~I2C1_SDA_GPIO3_28_BIT_MASK;
697+ writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
698+ break;
699+
700+ case 2:
701+#if defined CONFIG_MX6Q
702+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__GPIO_4_13);
703+#elif defined CONFIG_MX6DL
704+ mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW3__GPIO_4_13);
705+#endif
706+ reg = readl(GPIO4_BASE_ADDR + GPIO_GDIR);
707+ if (output)
708+ reg |= I2C2_SDA_GPIO4_13_BIT_MASK;
709+ else
710+ reg &= ~I2C2_SDA_GPIO4_13_BIT_MASK;
711+ writel(reg, GPIO4_BASE_ADDR + GPIO_GDIR);
712+ break;
713+
714+ case 3:
715+#if defined CONFIG_MX6Q
716+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_6__GPIO_1_6);
717+#elif defined CONFIG_MX6DL
718+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_6__GPIO_1_6);
719+#endif
720+ reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR);
721+ if (output)
722+ reg |= I2C3_SDA_GPIO1_6_BIT_MASK;
723+ else
724+ reg &= ~I2C3_SDA_GPIO1_6_BIT_MASK;
725+ writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR);
726+ break;
727+
728+ default:
729+ break;
730+ }
731+}
732+
733+/* set 1 to high 0 to low */
734+static void mx6q_i2c_gpio_scl_set_level(int bus, int high)
735+{
736+ u32 reg;
737+
738+ switch (bus) {
739+ case 1:
740+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
741+ if (high)
742+ reg |= I2C1_SCL_GPIO3_21_BIT_MASK;
743+ else
744+ reg &= ~I2C1_SCL_GPIO3_21_BIT_MASK;
745+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
746+ break;
747+ case 2:
748+ reg = readl(GPIO4_BASE_ADDR + GPIO_DR);
749+ if (high)
750+ reg |= I2C2_SCL_GPIO4_12_BIT_MASK;
751+ else
752+ reg &= ~I2C2_SCL_GPIO4_12_BIT_MASK;
753+ writel(reg, GPIO4_BASE_ADDR + GPIO_DR);
754+ break;
755+ case 3:
756+ reg = readl(GPIO1_BASE_ADDR + GPIO_DR);
757+ if (high)
758+ reg |= I2C3_SCL_GPIO1_3_BIT_MASK;
759+ else
760+ reg &= ~I2C3_SCL_GPIO1_3_BIT_MASK;
761+ writel(reg, GPIO1_BASE_ADDR + GPIO_DR);
762+ break;
763+ }
764+}
765+
766+/* set 1 to high 0 to low */
767+static void mx6q_i2c_gpio_sda_set_level(int bus, int high)
768+{
769+ u32 reg;
770+
771+ switch (bus) {
772+ case 1:
773+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
774+ if (high)
775+ reg |= I2C1_SDA_GPIO3_28_BIT_MASK;
776+ else
777+ reg &= ~I2C1_SDA_GPIO3_28_BIT_MASK;
778+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
779+ break;
780+ case 2:
781+ reg = readl(GPIO4_BASE_ADDR + GPIO_DR);
782+ if (high)
783+ reg |= I2C2_SDA_GPIO4_13_BIT_MASK;
784+ else
785+ reg &= ~I2C2_SDA_GPIO4_13_BIT_MASK;
786+ writel(reg, GPIO4_BASE_ADDR + GPIO_DR);
787+ break;
788+ case 3:
789+ reg = readl(GPIO1_BASE_ADDR + GPIO_DR);
790+ if (high)
791+ reg |= I2C3_SDA_GPIO1_6_BIT_MASK;
792+ else
793+ reg &= ~I2C3_SDA_GPIO1_6_BIT_MASK;
794+ writel(reg, GPIO1_BASE_ADDR + GPIO_DR);
795+ break;
796+ }
797+}
798+
799+static int mx6q_i2c_gpio_check_sda(int bus)
800+{
801+ u32 reg;
802+ int result = 0;
803+
804+ switch (bus) {
805+ case 1:
806+ reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
807+ result = !!(reg & I2C1_SDA_GPIO3_28_BIT_MASK);
808+ break;
809+ case 2:
810+ reg = readl(GPIO4_BASE_ADDR + GPIO_PSR);
811+ result = !!(reg & I2C2_SDA_GPIO4_13_BIT_MASK);
812+ break;
813+ case 3:
814+ reg = readl(GPIO1_BASE_ADDR + GPIO_PSR);
815+ result = !!(reg & I2C3_SDA_GPIO1_6_BIT_MASK);
816+ break;
817+ }
818+
819+ return result;
820+}
821+
822+ /* Random reboot cause i2c SDA low issue:
823+ * the i2c bus busy because some device pull down the I2C SDA
824+ * line. This happens when Host is reading some byte from slave, and
825+ * then host is reset/reboot. Since in this case, device is
826+ * controlling i2c SDA line, the only thing host can do this give the
827+ * clock on SCL and sending NAK, and STOP to finish this
828+ * transaction.
829+ *
830+ * How to fix this issue:
831+ * detect if the SDA was low on bus send 8 dummy clock, and 1
832+ * clock + NAK, and STOP to finish i2c transaction the pending
833+ * transfer.
834+ */
835+int i2c_bus_recovery(void)
836+{
837+ int i, bus, result = 0;
838+
839+ for (bus = 1; bus <= 3; bus++) {
840+ mx6q_i2c_gpio_sda_direction(bus, 0);
841+
842+ if (mx6q_i2c_gpio_check_sda(bus) == 0) {
843+ printf("i2c: I2C%d SDA is low, start i2c recovery...\n", bus);
844+ mx6q_i2c_gpio_scl_direction(bus, 1);
845+ mx6q_i2c_gpio_scl_set_level(bus, 1);
846+ __udelay(10000);
847+
848+ for (i = 0; i < 9; i++) {
849+ mx6q_i2c_gpio_scl_set_level(bus, 1);
850+ __udelay(5);
851+ mx6q_i2c_gpio_scl_set_level(bus, 0);
852+ __udelay(5);
853+ }
854+
855+ /* 9th clock here, the slave should already
856+ release the SDA, we can set SDA as high to
857+ a NAK.*/
858+ mx6q_i2c_gpio_sda_direction(bus, 1);
859+ mx6q_i2c_gpio_sda_set_level(bus, 1);
860+ __udelay(1); /* Pull up SDA first */
861+ mx6q_i2c_gpio_scl_set_level(bus, 1);
862+ __udelay(5); /* plus pervious 1 us */
863+ mx6q_i2c_gpio_scl_set_level(bus, 0);
864+ __udelay(5);
865+ mx6q_i2c_gpio_sda_set_level(bus, 0);
866+ __udelay(5);
867+ mx6q_i2c_gpio_scl_set_level(bus, 1);
868+ __udelay(5);
869+ /* Here: SCL is high, and SDA from low to high, it's a
870+ * stop condition */
871+ mx6q_i2c_gpio_sda_set_level(bus, 1);
872+ __udelay(5);
873+
874+ mx6q_i2c_gpio_sda_direction(bus, 0);
875+ if (mx6q_i2c_gpio_check_sda(bus) == 1)
876+ printf("I2C%d Recovery success\n", bus);
877+ else {
878+ printf("I2C%d Recovery failed, I2C1 SDA still low!!!\n", bus);
879+ result |= 1 << bus;
880+ }
881+ }
882+
883+ /* configure back to i2c */
884+ switch (bus) {
885+ case 1:
886+ setup_i2c(I2C1_BASE_ADDR);
887+ break;
888+ case 2:
889+ setup_i2c(I2C2_BASE_ADDR);
890+ break;
891+ case 3:
892+ setup_i2c(I2C3_BASE_ADDR);
893+ break;
894+ }
895+ }
896+
897+ return result;
898+}
899+
900+/* check and set PMIC value */
901+static int setup_pmic_reg(uint addr, uchar val)
902+{
903+ uchar rdval;
904+
905+ if (i2c_read(0x8, addr, 1, &rdval, 1)) {
906+ printf("%s:i2c_read:error\n", __func__);
907+ return -1;
908+ }
909+ else
910+ {
911+ if (rdval != val)
912+ {
913+ printf("Warning: adjusted PFUZE value reg: 0x%02x old: 0x%02x new:0x%02x\n",addr,rdval,val);
914+ if (i2c_write(0x8, addr, 1, &val, 1)) {
915+ printf("%s:i2c_write:error\n",__func__);
916+ return -1;
917+ }
918+ }
919+ }
920+ return 0;
921+}
922+
923+static int setup_pmic_voltages(void)
924+{
925+ unsigned char id1 = 0, id2 = 0, value = 0 ;
926+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
927+ if (!i2c_probe(0x8)) {
928+ if (i2c_read(0x8, 0, 1, &id1, 1)) {
929+ printf("%s:i2c_read:error\n", __func__);
930+ return -1;
931+ }
932+ if (i2c_read(0x8, 3, 1, &id2, 1)) {
933+ printf("%s:i2c_read:error\n", __func__);
934+ return -1;
935+ }
936+ #if CONFIG_MX6_INTER_LDO_BYPASS
937+ /*VDDCORE 1.1V@800Mhz: SW1AB*/
938+ value = 0x20;
939+ if (i2c_write(0x8, 0x20, 1, &value, 1)) {
940+ printf("%s:i2c_write:error SW1AB\n",__func__);
941+ return -1;
942+ }
943+ /*VDDSOC 1.2V : SW1C*/
944+ value = 0x24;
945+ if (i2c_write(0x8, 0x2e, 1, &value, 1)) {
946+ printf("%s:i2c_write:error SW1C\n",__func__);
947+ return -1;
948+ }
949+ /* Bypass the VDDSOC from Anatop */
950+ val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
951+ val &= ~BM_ANADIG_REG_CORE_REG2_TRG;
952+ val |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f);
953+ REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
954+
955+ /* Bypass the VDDCORE from Anatop */
956+ val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
957+ val &= ~BM_ANADIG_REG_CORE_REG0_TRG;
958+ val |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f);
959+ REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
960+
961+ /* Bypass the VDDPU from Anatop */
962+ val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);
963+ val &= ~BM_ANADIG_REG_CORE_REG1_TRG;
964+ val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
965+ REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);
966+
967+ /*clear PowerDown Enable bit of WDOG1_WMCR*/
968+ writew(0, WDOG1_BASE_ADDR + 0x08);
969+ printf("hw_anadig_reg_core=%x\n",
970+ REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE));
971+ #endif
972+
973+ switch (id2)
974+ {
975+ case 0x01:
976+ /* GEN1 PMIC (default programming), set correct values for PHY, EMMC, DDR VTT */
977+ printf("PFUZE100 1st Gen detected (0x%x/0x%x)\n", id1, id2);
978+
979+ /* VGEN5, 1.8V phy power supply */
980+ value = 0x10;
981+ if (i2c_write(0x8, 0x70, 1, &value, 1)) {
982+ printf("%s:i2c_write:error VGEN5\n",__func__);
983+ return -1;
984+ }
985+ /* VGEN6, 1.8V emmc vccio power supply */
986+ value = 0x10;
987+ if (i2c_write(0x8, 0x71, 1, &value, 1)) {
988+ printf("%s:i2c_write:error VGEN6\n",__func__);
989+ return -1;
990+ }
991+ /* SW4, 0.75V DDR VTT */
992+ value = 0x0e;
993+ if (i2c_write(0x8, 0x4a, 1, &value, 1)) {
994+ printf("%s:i2c_write:error SW4\n",__func__);
995+ return -1;
996+ }
997+ break;
998+
999+ case 0x10:
1000+ case 0x11:
1001+ /* GEN2 PMIC (OTP programmed) - check correct settings */
1002+ printf("PFUZE100 2nd Gen (OTP) detected (0x%x/0x%x)\n", id1, id2);
1003+
1004+ if (setup_pmic_reg(0x70, 0x10))
1005+ return -1;
1006+ if (setup_pmic_reg(0x71, 0x10))
1007+ return -1;
1008+ if (setup_pmic_reg(0x4a, 0x0e))
1009+ return -1;
1010+ break;
1011+
1012+ default:
1013+ /* unknown PMIC */
1014+ printf("unknown PFUZE100 detected (0x%x/0x%x)\n", id1, id2);
1015+
1016+ if (setup_pmic_reg(0x70, 0x10))
1017+ return -1;
1018+ if (setup_pmic_reg(0x71, 0x10))
1019+ return -1;
1020+ if (setup_pmic_reg(0x4a, 0x0e))
1021+ return -1;
1022+ break;
1023+ }
1024+ }
1025+ return 0;
1026+}
1027+#endif
1028+
1029+#ifdef CONFIG_IMX_ECSPI
1030+s32 spi_get_cfg(struct imx_spi_dev_t *dev)
1031+{
1032+ switch (dev->slave.cs) {
1033+ case 0:
1034+ /* SPI-NOR */
1035+ dev->base = ECSPI1_BASE_ADDR;
1036+ dev->freq = 25000000;
1037+ dev->ss_pol = IMX_SPI_ACTIVE_LOW;
1038+ dev->ss = 0;
1039+ dev->fifo_sz = 64 * 4;
1040+ dev->us_delay = 0;
1041+ break;
1042+ case 1:
1043+ /* SPI-NOR */
1044+ dev->base = ECSPI1_BASE_ADDR;
1045+ dev->freq = 25000000;
1046+ dev->ss_pol = IMX_SPI_ACTIVE_LOW;
1047+ dev->ss = 1;
1048+ dev->fifo_sz = 64 * 4;
1049+ dev->us_delay = 0;
1050+ break;
1051+ default:
1052+ printf("Invalid Bus ID!\n");
1053+ }
1054+
1055+ return 0;
1056+}
1057+
1058+void spi_io_init(struct imx_spi_dev_t *dev)
1059+{
1060+ u32 reg;
1061+
1062+ switch (dev->base) {
1063+ case ECSPI1_BASE_ADDR:
1064+ /* Enable clock */
1065+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR1);
1066+ reg |= 0x3;
1067+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR1);
1068+
1069+ /* SCLK, MISO, MOSI */
1070+#if defined CONFIG_MX6Q
1071+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D16__ECSPI1_SCLK);
1072+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D17__ECSPI1_MISO);
1073+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D18__ECSPI1_MOSI);
1074+ if (dev->ss == 1)
1075+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D19__ECSPI1_SS1);
1076+#elif defined CONFIG_MX6DL
1077+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D16__ECSPI1_SCLK);
1078+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D17__ECSPI1_MISO);
1079+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D18__ECSPI1_MOSI);
1080+ if (dev->ss == 1)
1081+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D19__ECSPI1_SS1);
1082+#endif
1083+ break;
1084+ case ECSPI2_BASE_ADDR:
1085+ case ECSPI3_BASE_ADDR:
1086+ /* ecspi2-3 fall through */
1087+ break;
1088+ default:
1089+ break;
1090+ }
1091+}
1092+#endif
1093+
1094+#ifdef CONFIG_NET_MULTI
1095+int board_eth_init(bd_t *bis)
1096+{
1097+ int rc = -ENODEV;
1098+ return rc;
1099+}
1100+#endif
1101+
1102+#ifdef CONFIG_CMD_MMC
1103+
1104+struct fsl_esdhc_cfg usdhc_cfg[4] = {
1105+ {USDHC2_BASE_ADDR, 1, 1, 1, 0},
1106+ {USDHC3_BASE_ADDR, 1, 1, 1, 0},
1107+ {USDHC4_BASE_ADDR, 1, 1, 1, 0},
1108+};
1109+
1110+#if defined CONFIG_MX6Q
1111+iomux_v3_cfg_t usdhc1_pads[] = {
1112+ MX6Q_PAD_SD1_CLK__USDHC1_CLK,
1113+ MX6Q_PAD_SD1_CMD__USDHC1_CMD,
1114+ MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
1115+ MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
1116+ MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
1117+ MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
1118+};
1119+
1120+iomux_v3_cfg_t usdhc2_pads[] = {
1121+ MX6Q_PAD_SD2_CLK__USDHC2_CLK,
1122+ MX6Q_PAD_SD2_CMD__USDHC2_CMD,
1123+ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
1124+ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
1125+ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
1126+ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
1127+};
1128+
1129+iomux_v3_cfg_t usdhc3_pads[] = {
1130+ MX6Q_PAD_SD3_CLK__USDHC3_CLK,
1131+ MX6Q_PAD_SD3_CMD__USDHC3_CMD,
1132+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
1133+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
1134+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
1135+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
1136+ MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
1137+ MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
1138+ MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
1139+ MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
1140+ MX6Q_PAD_SD3_RST__USDHC3_RST,
1141+};
1142+
1143+iomux_v3_cfg_t usdhc4_pads[] = {
1144+ MX6Q_PAD_SD4_CLK__USDHC4_CLK,
1145+ MX6Q_PAD_SD4_CMD__USDHC4_CMD,
1146+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
1147+ MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
1148+ MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
1149+ MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
1150+ MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
1151+ MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
1152+ MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
1153+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
1154+};
1155+#elif defined CONFIG_MX6DL
1156+iomux_v3_cfg_t usdhc1_pads[] = {
1157+ MX6DL_PAD_SD1_CLK__USDHC1_CLK,
1158+ MX6DL_PAD_SD1_CMD__USDHC1_CMD,
1159+ MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
1160+ MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
1161+ MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
1162+ MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
1163+};
1164+
1165+iomux_v3_cfg_t usdhc2_pads[] = {
1166+ MX6DL_PAD_SD2_CLK__USDHC2_CLK,
1167+ MX6DL_PAD_SD2_CMD__USDHC2_CMD,
1168+ MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
1169+ MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
1170+ MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
1171+ MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
1172+};
1173+
1174+iomux_v3_cfg_t usdhc3_pads[] = {
1175+ MX6DL_PAD_SD3_CLK__USDHC3_CLK,
1176+ MX6DL_PAD_SD3_CMD__USDHC3_CMD,
1177+ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0,
1178+ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1,
1179+ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2,
1180+ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3,
1181+ MX6DL_PAD_SD3_DAT4__USDHC3_DAT4,
1182+ MX6DL_PAD_SD3_DAT5__USDHC3_DAT5,
1183+ MX6DL_PAD_SD3_DAT6__USDHC3_DAT6,
1184+ MX6DL_PAD_SD3_DAT7__USDHC3_DAT7,
1185+ MX6DL_PAD_SD3_RST__USDHC3_RST,
1186+};
1187+
1188+iomux_v3_cfg_t usdhc4_pads[] = {
1189+ MX6DL_PAD_SD4_CLK__USDHC4_CLK,
1190+ MX6DL_PAD_SD4_CMD__USDHC4_CMD,
1191+ MX6DL_PAD_SD4_DAT0__USDHC4_DAT0,
1192+ MX6DL_PAD_SD4_DAT1__USDHC4_DAT1,
1193+ MX6DL_PAD_SD4_DAT2__USDHC4_DAT2,
1194+ MX6DL_PAD_SD4_DAT3__USDHC4_DAT3,
1195+ MX6DL_PAD_SD4_DAT4__USDHC4_DAT4,
1196+ MX6DL_PAD_SD4_DAT5__USDHC4_DAT5,
1197+ MX6DL_PAD_SD4_DAT6__USDHC4_DAT6,
1198+ MX6DL_PAD_SD4_DAT7__USDHC4_DAT7,
1199+};
1200+#endif
1201+
1202+int usdhc_gpio_init(bd_t *bis)
1203+{
1204+ s32 status = 0;
1205+ u32 index = 0;
1206+
1207+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM;
1208+ ++index) {
1209+ switch (index) {
1210+ case 0:
1211+ mxc_iomux_v3_setup_multiple_pads(usdhc3_pads,
1212+ sizeof(usdhc3_pads) /
1213+ sizeof(usdhc3_pads[0]));
1214+ break;
1215+ case 1:
1216+ mxc_iomux_v3_setup_multiple_pads(usdhc4_pads,
1217+ sizeof(usdhc4_pads) /
1218+ sizeof(usdhc4_pads[0]));
1219+ break;
1220+ case 2:
1221+ mxc_iomux_v3_setup_multiple_pads(usdhc2_pads,
1222+ sizeof(usdhc2_pads) /
1223+ sizeof(usdhc2_pads[0]));
1224+ break;
1225+ default:
1226+ printf("Warning: you configured more USDHC controllers"
1227+ "(%d) then supported by the board (%d)\n",
1228+ index+1, CONFIG_SYS_FSL_USDHC_NUM);
1229+ return status;
1230+ }
1231+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
1232+ }
1233+
1234+ return status;
1235+}
1236+
1237+int board_mmc_init(bd_t *bis)
1238+{
1239+ if (!usdhc_gpio_init(bis))
1240+ return 0;
1241+ else
1242+ return -1;
1243+}
1244+
1245+/* For DDR mode operation, provide target delay parameter for each SD port.
1246+ * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
1247+ * is dependent on signal layout for that particular port. If the following
1248+ * CONFIG is not defined, then the default target delay value will be used.
1249+ */
1250+#ifdef CONFIG_GET_DDR_TARGET_DELAY
1251+u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg)
1252+{
1253+ /* No delay required */
1254+ return 0;
1255+}
1256+#endif
1257+
1258+#endif
1259+
1260+#ifdef CONFIG_LCD
1261+void lcd_enable(void)
1262+{
1263+ char *s;
1264+ int ret;
1265+ unsigned int reg;
1266+
1267+ s = getenv("lvds_num");
1268+ di = simple_strtol(s, NULL, 10);
1269+
1270+ /*
1271+ * hw_rev 2: IPUV3DEX
1272+ * hw_rev 3: IPUV3M
1273+ * hw_rev 4: IPUV3H
1274+ */
1275+ g_ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
1276+
1277+ imx_pwm_config(pwm0, 25000, 50000);
1278+ imx_pwm_enable(pwm0);
1279+
1280+ /* GPIO & PWM backlight */
1281+#if defined CONFIG_MX6Q
1282+ mxc_iomux_v3_setup_pad(MX6Q_PAD_SD1_DAT3__PWM1_PWMO);
1283+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9);
1284+#elif defined CONFIG_MX6DL
1285+ mxc_iomux_v3_setup_pad(MX6DL_PAD_SD1_DAT3__PWM1_PWMO);
1286+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_9__GPIO_1_9);
1287+#endif
1288+
1289+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 9), 1);
1290+
1291+#if defined CONFIG_MX6Q
1292+ /*
1293+ * Align IPU1 HSP clock and IPU1 DIx pixel clock
1294+ * with kernel setting to avoid screen flick when
1295+ * booting into kernel. Developer should change
1296+ * the relevant setting if kernel setting changes.
1297+ * IPU1 HSP clock tree:
1298+ * osc_clk(24M)->pll2_528_bus_main_clk(528M)->
1299+ * periph_clk(528M)->mmdc_ch0_axi_clk(528M)->
1300+ * ipu1_clk(264M)
1301+ */
1302+ /* pll2_528_bus_main_clk */
1303+ /* divider */
1304+ writel(0x1, ANATOP_BASE_ADDR + 0x34);
1305+
1306+ /* periph_clk */
1307+ /* source */
1308+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
1309+ reg &= ~(0x3 << 18);
1310+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCMR);
1311+
1312+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
1313+ reg &= ~(0x1 << 25);
1314+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
1315+
1316+ /*
1317+ * Check PERIPH_CLK_SEL_BUSY in
1318+ * MXC_CCM_CDHIPR register.
1319+ */
1320+ do {
1321+ udelay(5);
1322+ reg = readl(CCM_BASE_ADDR + CLKCTL_CDHIPR);
1323+ } while (reg & (0x1 << 5));
1324+
1325+ /* mmdc_ch0_axi_clk */
1326+ /* divider */
1327+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
1328+ reg &= ~(0x7 << 19);
1329+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
1330+
1331+ /*
1332+ * Check MMDC_CH0PODF_BUSY in
1333+ * MXC_CCM_CDHIPR register.
1334+ */
1335+ do {
1336+ udelay(5);
1337+ reg = readl(CCM_BASE_ADDR + CLKCTL_CDHIPR);
1338+ } while (reg & (0x1 << 4));
1339+
1340+ /* ipu1_clk */
1341+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3);
1342+ /* source */
1343+ reg &= ~(0x3 << 9);
1344+ /* divider */
1345+ reg &= ~(0x7 << 11);
1346+ reg |= (0x1 << 11);
1347+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3);
1348+
1349+ /*
1350+ * ipu1_pixel_clk_x clock tree:
1351+ * osc_clk(24M)->pll2_528_bus_main_clk(528M)->
1352+ * pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)->
1353+ * ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M)
1354+ */
1355+ /* pll2_pfd_352M */
1356+ /* disable */
1357+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x104);
1358+ /* divider */
1359+ writel(0x3F, ANATOP_BASE_ADDR + 0x108);
1360+ writel(0x15, ANATOP_BASE_ADDR + 0x104);
1361+
1362+ /* ldb_dix_clk */
1363+ /* source */
1364+ reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
1365+ reg &= ~(0x3F << 9);
1366+ reg |= (0x9 << 9);
1367+ writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
1368+ /* divider */
1369+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
1370+ reg |= (0x3 << 10);
1371+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
1372+
1373+ /* pll2_pfd_352M */
1374+ /* enable after ldb_dix_clk source is set */
1375+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x108);
1376+
1377+ /* ipu1_di_clk_x */
1378+ /* source */
1379+ reg = readl(CCM_BASE_ADDR + CLKCTL_CHSCCDR);
1380+ reg &= ~0xE07;
1381+ reg |= 0x803;
1382+ writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
1383+#elif defined CONFIG_MX6DL /* CONFIG_MX6Q */
1384+ /*
1385+ * IPU1 HSP clock tree:
1386+ * osc_clk(24M)->pll3_usb_otg_main_clk(480M)->
1387+ * pll3_pfd_540M(540M)->ipu1_clk(270M)
1388+ */
1389+ /* pll3_usb_otg_main_clk */
1390+ /* divider */
1391+ writel(0x3, ANATOP_BASE_ADDR + 0x18);
1392+
1393+ /* pll3_pfd_540M */
1394+ /* divider */
1395+ writel(0x3F << 8, ANATOP_BASE_ADDR + 0xF8);
1396+ writel(0x10 << 8, ANATOP_BASE_ADDR + 0xF4);
1397+ /* enable */
1398+ writel(0x1 << 15, ANATOP_BASE_ADDR + 0xF8);
1399+
1400+ /* ipu1_clk */
1401+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3);
1402+ /* source */
1403+ reg |= (0x3 << 9);
1404+ /* divider */
1405+ reg &= ~(0x7 << 11);
1406+ reg |= (0x1 << 11);
1407+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3);
1408+
1409+ /*
1410+ * ipu1_pixel_clk_x clock tree:
1411+ * osc_clk(24M)->pll2_528_bus_main_clk(528M)->
1412+ * pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)->
1413+ * ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M)
1414+ */
1415+ /* pll2_528_bus_main_clk */
1416+ /* divider */
1417+ writel(0x1, ANATOP_BASE_ADDR + 0x34);
1418+
1419+ /* pll2_pfd_352M */
1420+ /* disable */
1421+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x104);
1422+ /* divider */
1423+ writel(0x3F, ANATOP_BASE_ADDR + 0x108);
1424+ writel(0x15, ANATOP_BASE_ADDR + 0x104);
1425+
1426+ /* ldb_dix_clk */
1427+ /* source */
1428+ reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
1429+ reg &= ~(0x3F << 9);
1430+ reg |= (0x9 << 9);
1431+ writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
1432+ /* divider */
1433+ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
1434+ reg |= (0x3 << 10);
1435+ writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
1436+
1437+ /* pll2_pfd_352M */
1438+ /* enable after ldb_dix_clk source is set */
1439+ writel(0x1 << 7, ANATOP_BASE_ADDR + 0x108);
1440+
1441+ /* ipu1_di_clk_x */
1442+ /* source */
1443+ reg = readl(CCM_BASE_ADDR + CLKCTL_CHSCCDR);
1444+ reg &= ~0xE07;
1445+ reg |= 0x803;
1446+ writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
1447+#endif /* CONFIG_MX6DL */
1448+ if (di == 1) {
1449+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
1450+ reg |= 0xC033;
1451+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
1452+ } else {
1453+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
1454+ reg |= 0x300F;
1455+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
1456+ }
1457+
1458+ ret = ipuv3_fb_init(&lvds_xga, di, IPU_PIX_FMT_RGB666,
1459+ DI_PCLK_LDB, 65000000);
1460+ if (ret)
1461+ puts("LCD cannot be configured\n");
1462+
1463+ /*
1464+ * LVDS0 mux to IPU1 DI0.
1465+ * LVDS1 mux to IPU1 DI1.
1466+ */
1467+ reg = readl(IOMUXC_BASE_ADDR + 0xC);
1468+ reg &= ~(0x000003C0);
1469+ reg |= 0x00000100;
1470+ writel(reg, IOMUXC_BASE_ADDR + 0xC);
1471+
1472+ if (di == 1)
1473+ writel(0x40C, IOMUXC_BASE_ADDR + 0x8);
1474+ else
1475+ writel(0x201, IOMUXC_BASE_ADDR + 0x8);
1476+}
1477+#endif
1478+
1479+#ifdef CONFIG_VIDEO_MX5
1480+void panel_info_init(void)
1481+{
1482+ panel_info.vl_bpix = LCD_BPP;
1483+ panel_info.vl_col = lvds_xga.xres;
1484+ panel_info.vl_row = lvds_xga.yres;
1485+ panel_info.cmap = colormap;
1486+}
1487+#endif
1488+
1489+#ifdef CONFIG_SPLASH_SCREEN
1490+void setup_splash_image(void)
1491+{
1492+ char *s;
1493+ ulong addr;
1494+
1495+ s = getenv("splashimage");
1496+
1497+ if (s != NULL) {
1498+ addr = simple_strtoul(s, NULL, 16);
1499+
1500+#if defined(CONFIG_ARCH_MMU)
1501+ addr = ioremap_nocache(iomem_to_phys(addr),
1502+ fsl_bmp_reversed_600x400_size);
1503+#endif
1504+ memcpy((char *)addr, (char *)fsl_bmp_reversed_600x400,
1505+ fsl_bmp_reversed_600x400_size);
1506+ }
1507+}
1508+#endif
1509+
1510+int board_init(void)
1511+{
1512+/* need set Power Supply Glitch to 0x41736166
1513+*and need clear Power supply Glitch Detect bit
1514+* when POR or reboot or power on Otherwise system
1515+*could not be power off anymore*/
1516+ u32 reg;
1517+ writel(0x41736166, SNVS_BASE_ADDR + 0x64);/*set LPPGDR*/
1518+ udelay(10);
1519+ reg = readl(SNVS_BASE_ADDR + 0x4c);
1520+ reg |= (1 << 3);
1521+ writel(reg, SNVS_BASE_ADDR + 0x4c);/*clear LPSR*/
1522+
1523+ mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
1524+ setup_boot_device();
1525+ fsl_set_system_rev();
1526+
1527+ /* board id for linux */
1528+ gd->bd->bi_arch_number = MACH_TYPE_CGT_QMX6;
1529+
1530+ /* address of boot parameters */
1531+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
1532+
1533+ /* turn off backlight */
1534+#if defined CONFIG_MX6Q
1535+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9);
1536+#elif defined CONFIG_MX6DL
1537+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_9__GPIO_1_9);
1538+#endif
1539+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 9), 0);
1540+
1541+ setup_uart();
1542+
1543+#ifdef CONFIG_DWC_AHSATA
1544+ setup_sata();
1545+#endif
1546+
1547+#ifdef CONFIG_VIDEO_MX5
1548+ /* Enable lvds power */
1549+ setup_lvds_poweron();
1550+
1551+ panel_info_init();
1552+
1553+ gd->fb_base = CONFIG_FB_BASE;
1554+#ifdef CONFIG_ARCH_MMU
1555+ gd->fb_base = ioremap_nocache(iomem_to_phys(gd->fb_base), 0);
1556+#endif
1557+#endif
1558+
1559+ return 0;
1560+}
1561+
1562+
1563+#ifdef CONFIG_ANDROID_RECOVERY
1564+
1565+int check_recovery_cmd_file(void)
1566+{
1567+ int button_pressed = 0;
1568+ int recovery_mode = 0;
1569+
1570+ recovery_mode = check_and_clean_recovery_flag();
1571+
1572+ /* Check Recovery Combo Button press or not. */
1573+#if defined CONFIG_MX6Q
1574+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_19__GPIO_4_5);
1575+#elif defined CONFIG_MX6DL
1576+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_19__GPIO_4_5);
1577+#endif
1578+ reg = readl(GPIO4_BASE_ADDR + GPIO_GDIR);
1579+ reg &= ~(1<<5);
1580+ writel(reg, GPIO4_BASE_ADDR + GPIO_GDIR);
1581+ reg = readl(GPIO4_BASE_ADDR + GPIO_PSR);
1582+ if (!(reg & (1 << 5))) { /* VOL_DN key is low assert */
1583+ button_pressed = 1;
1584+ printf("Recovery key pressed\n");
1585+ }
1586+ return recovery_mode || button_pressed;
1587+}
1588+#endif
1589+
1590+int board_late_init(void)
1591+{
1592+ int ret = 0;
1593+ #ifdef CONFIG_I2C_MXC
1594+ setup_i2c(CONFIG_SYS_I2C_PORT);
1595+ i2c_bus_recovery();
1596+ ret = setup_pmic_voltages();
1597+ if (ret)
1598+ return -1;
1599+ #endif
1600+ return 0;
1601+}
1602+
1603+#ifdef CONFIG_MXC_FEC
1604+static int phy_read(char *devname, unsigned char addr, unsigned char reg,
1605+ unsigned short *pdata)
1606+{
1607+ int ret = miiphy_read(devname, addr, reg, pdata);
1608+ if (ret)
1609+ printf("Error reading from %s PHY addr=%02x reg=%02x\n",
1610+ devname, addr, reg);
1611+ return ret;
1612+}
1613+
1614+static int phy_write(char *devname, unsigned char addr, unsigned char reg,
1615+ unsigned short value)
1616+{
1617+ int ret = miiphy_write(devname, addr, reg, value);
1618+ if (ret)
1619+ printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
1620+ addr, reg);
1621+ return ret;
1622+}
1623+
1624+int mx6_rgmii_rework(char *devname, int phy_addr)
1625+{
1626+ /* KSZ9031RN ethernet phy on rev. Y.0+ */
1627+
1628+ phy_write(devname, phy_addr, 0x0d, 2);
1629+ phy_write(devname, phy_addr, 0x0e, 4);
1630+ phy_write(devname, phy_addr, 0x0d, 0xc002);
1631+ phy_write(devname, phy_addr, 0x0e, 0x0000);
1632+
1633+ phy_write(devname, phy_addr, 0x0d, 2);
1634+ phy_write(devname, phy_addr, 0x0e, 5);
1635+ phy_write(devname, phy_addr, 0x0d, 0xc002);
1636+ phy_write(devname, phy_addr, 0x0e, 0x0000);
1637+
1638+ phy_write(devname, phy_addr, 0x0d, 2);
1639+ phy_write(devname, phy_addr, 0x0e, 6);
1640+ phy_write(devname, phy_addr, 0x0d, 0xc002);
1641+ phy_write(devname, phy_addr, 0x0e, 0xFFFF);
1642+
1643+ phy_write(devname, phy_addr, 0x0d, 2);
1644+ phy_write(devname, phy_addr, 0x0e, 8);
1645+ phy_write(devname, phy_addr, 0x0d, 0xc002);
1646+ phy_write(devname, phy_addr, 0x0e, 0x3FFF);
1647+
1648+ phy_write(devname, phy_addr, 0x0d, 0x0);
1649+
1650+ return 0;
1651+}
1652+#if defined CONFIG_MX6Q
1653+iomux_v3_cfg_t enet_pads[] = {
1654+ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
1655+ MX6Q_PAD_ENET_MDC__ENET_MDC,
1656+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
1657+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
1658+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
1659+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
1660+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
1661+ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
1662+ /* pin 35 - 1 (PHY_AD2) on reset */
1663+ MX6Q_PAD_RGMII_RXC__GPIO_6_30,
1664+ /* pin 32 - 1 - (MODE0) all */
1665+ MX6Q_PAD_RGMII_RD0__GPIO_6_25,
1666+ /* pin 31 - 1 - (MODE1) all */
1667+ MX6Q_PAD_RGMII_RD1__GPIO_6_27,
1668+ /* pin 28 - 1 - (MODE2) all */
1669+ MX6Q_PAD_RGMII_RD2__GPIO_6_28,
1670+ /* pin 27 - 1 - (MODE3) all */
1671+ MX6Q_PAD_RGMII_RD3__GPIO_6_29,
1672+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
1673+ MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
1674+ MX6Q_PAD_GPIO_0__CCM_CLKO,
1675+ MX6Q_PAD_GPIO_3__CCM_CLKO2,
1676+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
1677+};
1678+
1679+iomux_v3_cfg_t enet_pads_final[] = {
1680+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
1681+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
1682+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
1683+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
1684+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
1685+ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
1686+};
1687+#elif defined CONFIG_MX6DL
1688+iomux_v3_cfg_t enet_pads[] = {
1689+ MX6DL_PAD_ENET_MDIO__ENET_MDIO,
1690+ MX6DL_PAD_ENET_MDC__ENET_MDC,
1691+ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC,
1692+ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0,
1693+ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1,
1694+ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2,
1695+ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3,
1696+ MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
1697+ /* pin 35 - 1 (PHY_AD2) on reset */
1698+ MX6DL_PAD_RGMII_RXC__GPIO_6_30,
1699+ /* pin 32 - 1 - (MODE0) all */
1700+ MX6DL_PAD_RGMII_RD0__GPIO_6_25,
1701+ /* pin 31 - 1 - (MODE1) all */
1702+ MX6DL_PAD_RGMII_RD1__GPIO_6_27,
1703+ /* pin 28 - 1 - (MODE2) all */
1704+ MX6DL_PAD_RGMII_RD2__GPIO_6_28,
1705+ /* pin 27 - 1 - (MODE3) all */
1706+ MX6DL_PAD_RGMII_RD3__GPIO_6_29,
1707+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
1708+ MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24,
1709+ MX6DL_PAD_GPIO_0__CCM_CLKO,
1710+ MX6DL_PAD_GPIO_3__CCM_CLKO2,
1711+ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK,
1712+};
1713+
1714+iomux_v3_cfg_t enet_pads_final[] = {
1715+ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC,
1716+ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0,
1717+ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1,
1718+ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2,
1719+ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3,
1720+ MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
1721+};
1722+#endif
1723+
1724+void enet_board_init(void)
1725+{
1726+ unsigned int reg;
1727+#if defined CONFIG_MX6Q
1728+ iomux_v3_cfg_t enet_reset =
1729+ (MX6Q_PAD_EIM_D23__GPIO_3_23 &
1730+ ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x48);
1731+#elif defined CONFIG_MX6DL
1732+ iomux_v3_cfg_t enet_reset =
1733+ (MX6DL_PAD_EIM_D23__GPIO_3_23 &
1734+ ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x48);
1735+#endif
1736+
1737+ /* phy reset: gpio3-23 */
1738+ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 0);
1739+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 30),
1740+ (CONFIG_FEC0_PHY_ADDR >> 2));
1741+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 25), 1);
1742+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 27), 1);
1743+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 28), 1);
1744+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 29), 1);
1745+ mxc_iomux_v3_setup_multiple_pads(enet_pads,
1746+ ARRAY_SIZE(enet_pads));
1747+ mxc_iomux_v3_setup_pad(enet_reset);
1748+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 24), 1);
1749+
1750+ udelay(500);
1751+ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 1);
1752+ mxc_iomux_v3_setup_multiple_pads(enet_pads_final,
1753+ ARRAY_SIZE(enet_pads_final));
1754+}
1755+#endif
1756+
1757+int checkboard(void)
1758+{
1759+ printf("Board: %s-QMX6: Board: 0x%x [",
1760+ mx6_chip_name(),
1761+ fsl_system_rev);
1762+
1763+ switch (__REG(SRC_BASE_ADDR + 0x8)) {
1764+ case 0x0001:
1765+ printf("POR");
1766+ break;
1767+ case 0x0009:
1768+ printf("RST");
1769+ break;
1770+ case 0x0010:
1771+ case 0x0011:
1772+ printf("WDOG");
1773+ break;
1774+ default:
1775+ printf("unknown");
1776+ }
1777+ printf(" ]\n");
1778+
1779+ printf("Boot Device: ");
1780+ switch (get_boot_device()) {
1781+ case WEIM_NOR_BOOT:
1782+ printf("NOR\n");
1783+ break;
1784+ case ONE_NAND_BOOT:
1785+ printf("ONE NAND\n");
1786+ break;
1787+ case PATA_BOOT:
1788+ printf("PATA\n");
1789+ break;
1790+ case SATA_BOOT:
1791+ printf("SATA\n");
1792+ break;
1793+ case I2C_BOOT:
1794+ printf("I2C\n");
1795+ break;
1796+ case SPI_NOR_BOOT:
1797+ printf("SPI NOR\n");
1798+ break;
1799+ case SD_BOOT:
1800+ printf("SD\n");
1801+ break;
1802+ case MMC_BOOT:
1803+ printf("MMC\n");
1804+ break;
1805+ case NAND_BOOT:
1806+ printf("NAND\n");
1807+ break;
1808+ case UNKNOWN_BOOT:
1809+ default:
1810+ printf("UNKNOWN\n");
1811+ break;
1812+ }
1813+
1814+#ifdef CONFIG_SECURE_BOOT
1815+ if (check_hab_enable() == 1)
1816+ get_hab_status();
1817+#endif
1818+
1819+ return 0;
1820+}
1821+
1822+
1823+#ifdef CONFIG_IMX_UDC
1824+void udc_pins_setting(void)
1825+{
1826+
1827+#define GPIO_3_22_BIT_MASK (1<<22)
1828+ u32 reg;
1829+#if defined CONFIG_MX6Q
1830+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_1__USBOTG_ID);
1831+#elif defined CONFIG_MX6DL
1832+ mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_1__USBOTG_ID);
1833+#endif
1834+
1835+#ifdef CONFIG_USB_OTG_PWR
1836+ /* USB_OTG_PWR */
1837+#if defined CONFIG_MX6Q
1838+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D22__GPIO_3_22);
1839+#elif defined CONFIG_MX6DL
1840+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D22__GPIO_3_22);
1841+#endif
1842+
1843+ reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
1844+ /* set gpio_3_22 as output */
1845+ reg |= GPIO_3_22_BIT_MASK;
1846+ writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
1847+
1848+ /* set USB_OTG_PWR to 0 */
1849+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
1850+ reg &= ~GPIO_3_22_BIT_MASK;
1851+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
1852+#endif
1853+ /* USB_ID via GPIO_1 */
1854+ mxc_iomux_set_gpr_register(1, 13, 1, 1);
1855+}
1856+#endif
1857diff --git a/board/freescale/cgt_qmx6/config.mk b/board/freescale/cgt_qmx6/config.mk
1858new file mode 100644
1859index 0000000..a0ce2a1
1860--- /dev/null
1861+++ b/board/freescale/cgt_qmx6/config.mk
1862@@ -0,0 +1,7 @@
1863+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
1864+
1865+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
1866+
1867+ifndef TEXT_BASE
1868+ TEXT_BASE = 0x27800000
1869+endif
1870diff --git a/board/freescale/cgt_qmx6/flash_header.S b/board/freescale/cgt_qmx6/flash_header.S
1871new file mode 100644
1872index 0000000..8bbef35
1873--- /dev/null
1874+++ b/board/freescale/cgt_qmx6/flash_header.S
1875@@ -0,0 +1,202 @@
1876+/*
1877+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
1878+ *
1879+ * This program is free software; you can redistribute it and/or
1880+ * modify it under the terms of the GNU General Public License as
1881+ * published by the Free Software Foundation; either version 2 of
1882+ * the License, or (at your option) any later version.
1883+ *
1884+ * This program is distributed in the hope that it will be useful,
1885+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1886+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1887+ * GNU General Public License for more details.
1888+ *
1889+ * You should have received a copy of the GNU General Public License
1890+ * along with this program; if not, write to the Free Software
1891+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1892+ * MA 02111-1307 USA
1893+ */
1894+
1895+#include <config.h>
1896+#include <asm/arch/mx6.h>
1897+
1898+#ifdef CONFIG_FLASH_HEADER
1899+#ifndef CONFIG_FLASH_HEADER_OFFSET
1900+# error "Must define the offset of flash header"
1901+#endif
1902+
1903+#define CPU_2_BE_32(l) \
1904+ ((((l) & 0x000000FF) << 24) | \
1905+ (((l) & 0x0000FF00) << 8) | \
1906+ (((l) & 0x00FF0000) >> 8) | \
1907+ (((l) & 0xFF000000) >> 24))
1908+
1909+#define MXC_DCD_ITEM(i, addr, val) \
1910+dcd_node_##i: \
1911+ .word CPU_2_BE_32(addr) ; \
1912+ .word CPU_2_BE_32(val) ; \
1913+
1914+.section ".text.flasheader", "x"
1915+ b _start
1916+ .org CONFIG_FLASH_HEADER_OFFSET
1917+
1918+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
1919+app_code_jump_v: .word _start
1920+reserv1: .word 0x0
1921+dcd_ptr: .word dcd_hdr
1922+boot_data_ptr: .word boot_data
1923+self_ptr: .word ivt_header
1924+app_code_csf: .word 0x0
1925+reserv2: .word 0x0
1926+
1927+boot_data: .word TEXT_BASE
1928+image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
1929+plugin: .word 0x0
1930+
1931+dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
1932+write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
1933+
1934+/* DCD */
1935+
1936+/* DDR IO TYPE */
1937+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
1938+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
1939+
1940+/* clock */
1941+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
1942+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
1943+
1944+/* address */
1945+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
1946+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
1947+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
1948+
1949+/* control */
1950+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
1951+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
1952+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
1953+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
1954+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
1955+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
1956+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
1957+
1958+/* data strobe */
1959+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
1960+
1961+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
1962+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
1963+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
1964+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
1965+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
1966+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
1967+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
1968+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
1969+
1970+/* data */
1971+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
1972+
1973+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
1974+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
1975+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
1976+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
1977+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
1978+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
1979+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
1980+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
1981+
1982+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
1983+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
1984+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
1985+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
1986+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
1987+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
1988+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
1989+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
1990+
1991+/* calibrations */
1992+/* ZQ */
1993+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
1994+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
1995+
1996+/* write leveling */
1997+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001C001C)
1998+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0024001F)
1999+
2000+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001A0037)
2001+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001A002F)
2002+
2003+/* DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00 */
2004+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x43050315)
2005+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02720272)
2006+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83c, 0x03220325)
2007+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x0312026B)
2008+
2009+/* read calibration */
2010+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x43393A3B)
2011+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x3E433A43)
2012+
2013+/* write calibration */
2014+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x47444C47)
2015+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x4D334F46)
2016+
2017+/* read data bit delay: (3 is the recommended default value, although out of reset value is 0) */
2018+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
2019+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
2020+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
2021+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
2022+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
2023+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
2024+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
2025+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
2026+
2027+/* complete calibration by forced measurment */
2028+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
2029+MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
2030+
2031+/* MMDC init */
2032+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
2033+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
2034+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
2035+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
2036+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8C63)
2037+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
2038+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00091740)
2039+
2040+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
2041+
2042+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
2043+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
2044+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
2045+
2046+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
2047+
2048+/* Initialize 2GB DDR3 - Micron MT41J128M */
2049+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
2050+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
2051+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
2052+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
2053+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
2054+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
2055+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
2056+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
2057+
2058+/* DDR device ZQ calibration */
2059+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
2060+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
2061+
2062+/* final DDR setup, before operation start */
2063+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
2064+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
2065+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
2066+
2067+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
2068+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
2069+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
2070+
2071+/* enable AXI cache for VDOA/VPU/IPU */
2072+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
2073+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
2074+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
2075+MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
2076+
2077+#endif
2078diff --git a/board/freescale/cgt_qmx6/flash_header_pn016101.S b/board/freescale/cgt_qmx6/flash_header_pn016101.S
2079new file mode 100644
2080index 0000000..1528d67
2081--- /dev/null
2082+++ b/board/freescale/cgt_qmx6/flash_header_pn016101.S
2083@@ -0,0 +1,202 @@
2084+/*
2085+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
2086+ *
2087+ * This program is free software; you can redistribute it and/or
2088+ * modify it under the terms of the GNU General Public License as
2089+ * published by the Free Software Foundation; either version 2 of
2090+ * the License, or (at your option) any later version.
2091+ *
2092+ * This program is distributed in the hope that it will be useful,
2093+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2094+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2095+ * GNU General Public License for more details.
2096+ *
2097+ * You should have received a copy of the GNU General Public License
2098+ * along with this program; if not, write to the Free Software
2099+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2100+ * MA 02111-1307 USA
2101+ */
2102+
2103+#include <config.h>
2104+#include <asm/arch/mx6.h>
2105+
2106+#ifdef CONFIG_FLASH_HEADER
2107+#ifndef CONFIG_FLASH_HEADER_OFFSET
2108+# error "Must define the offset of flash header"
2109+#endif
2110+
2111+#define CPU_2_BE_32(l) \
2112+ ((((l) & 0x000000FF) << 24) | \
2113+ (((l) & 0x0000FF00) << 8) | \
2114+ (((l) & 0x00FF0000) >> 8) | \
2115+ (((l) & 0xFF000000) >> 24))
2116+
2117+#define MXC_DCD_ITEM(i, addr, val) \
2118+dcd_node_##i: \
2119+ .word CPU_2_BE_32(addr) ; \
2120+ .word CPU_2_BE_32(val) ; \
2121+
2122+.section ".text.flasheader", "x"
2123+ b _start
2124+ .org CONFIG_FLASH_HEADER_OFFSET
2125+
2126+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
2127+app_code_jump_v: .word _start
2128+reserv1: .word 0x0
2129+dcd_ptr: .word dcd_hdr
2130+boot_data_ptr: .word boot_data
2131+self_ptr: .word ivt_header
2132+app_code_csf: .word 0x0
2133+reserv2: .word 0x0
2134+
2135+boot_data: .word TEXT_BASE
2136+image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
2137+plugin: .word 0x0
2138+
2139+dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
2140+write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
2141+
2142+/* DCD */
2143+
2144+/* DDR IO TYPE */
2145+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
2146+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
2147+
2148+/* clock */
2149+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
2150+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
2151+
2152+/* address */
2153+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
2154+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
2155+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
2156+
2157+/* control */
2158+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
2159+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
2160+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
2161+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
2162+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
2163+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
2164+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
2165+
2166+/* data strobe */
2167+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
2168+
2169+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
2170+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
2171+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
2172+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
2173+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
2174+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
2175+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
2176+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
2177+
2178+/* data */
2179+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
2180+
2181+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
2182+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
2183+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
2184+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
2185+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
2186+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
2187+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
2188+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
2189+
2190+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
2191+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
2192+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
2193+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
2194+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
2195+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
2196+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
2197+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
2198+
2199+/* calibrations */
2200+/* ZQ */
2201+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
2202+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
2203+
2204+/* write leveling */
2205+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x002C0030)
2206+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001C0022)
2207+
2208+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x002E0031)
2209+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x003A004A)
2210+
2211+/* DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00 */
2212+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x420A0207)
2213+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x01710177)
2214+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83c, 0x42160222)
2215+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x02010213)
2216+
2217+/* read calibration */
2218+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x484B4A48)
2219+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x4B4F4C49)
2220+
2221+/* write calibration */
2222+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x412A262B)
2223+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x2E2F2F2C)
2224+
2225+/* read data bit delay: (3 is the recommended default value, although out of reset value is 0) */
2226+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
2227+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
2228+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
2229+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
2230+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
2231+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
2232+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
2233+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
2234+
2235+/* complete calibration by forced measurment */
2236+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
2237+MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
2238+
2239+/* MMDC init */
2240+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
2241+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
2242+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
2243+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
2244+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8C63)
2245+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
2246+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
2247+
2248+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
2249+
2250+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
2251+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
2252+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
2253+
2254+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
2255+
2256+/* Initialize 1GB DDR3 - Micron MT41J128M */
2257+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
2258+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
2259+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
2260+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
2261+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
2262+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
2263+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x09208030)
2264+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x09208038)
2265+
2266+/* DDR device ZQ calibration */
2267+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
2268+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
2269+
2270+/* final DDR setup, before operation start */
2271+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
2272+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
2273+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
2274+
2275+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
2276+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
2277+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
2278+
2279+/* enable AXI cache for VDOA/VPU/IPU */
2280+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
2281+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
2282+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
2283+MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
2284+
2285+#endif
2286diff --git a/board/freescale/cgt_qmx6/flash_header_pn016104.S b/board/freescale/cgt_qmx6/flash_header_pn016104.S
2287new file mode 100644
2288index 0000000..8bbef35
2289--- /dev/null
2290+++ b/board/freescale/cgt_qmx6/flash_header_pn016104.S
2291@@ -0,0 +1,202 @@
2292+/*
2293+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
2294+ *
2295+ * This program is free software; you can redistribute it and/or
2296+ * modify it under the terms of the GNU General Public License as
2297+ * published by the Free Software Foundation; either version 2 of
2298+ * the License, or (at your option) any later version.
2299+ *
2300+ * This program is distributed in the hope that it will be useful,
2301+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2302+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2303+ * GNU General Public License for more details.
2304+ *
2305+ * You should have received a copy of the GNU General Public License
2306+ * along with this program; if not, write to the Free Software
2307+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2308+ * MA 02111-1307 USA
2309+ */
2310+
2311+#include <config.h>
2312+#include <asm/arch/mx6.h>
2313+
2314+#ifdef CONFIG_FLASH_HEADER
2315+#ifndef CONFIG_FLASH_HEADER_OFFSET
2316+# error "Must define the offset of flash header"
2317+#endif
2318+
2319+#define CPU_2_BE_32(l) \
2320+ ((((l) & 0x000000FF) << 24) | \
2321+ (((l) & 0x0000FF00) << 8) | \
2322+ (((l) & 0x00FF0000) >> 8) | \
2323+ (((l) & 0xFF000000) >> 24))
2324+
2325+#define MXC_DCD_ITEM(i, addr, val) \
2326+dcd_node_##i: \
2327+ .word CPU_2_BE_32(addr) ; \
2328+ .word CPU_2_BE_32(val) ; \
2329+
2330+.section ".text.flasheader", "x"
2331+ b _start
2332+ .org CONFIG_FLASH_HEADER_OFFSET
2333+
2334+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
2335+app_code_jump_v: .word _start
2336+reserv1: .word 0x0
2337+dcd_ptr: .word dcd_hdr
2338+boot_data_ptr: .word boot_data
2339+self_ptr: .word ivt_header
2340+app_code_csf: .word 0x0
2341+reserv2: .word 0x0
2342+
2343+boot_data: .word TEXT_BASE
2344+image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
2345+plugin: .word 0x0
2346+
2347+dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
2348+write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
2349+
2350+/* DCD */
2351+
2352+/* DDR IO TYPE */
2353+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
2354+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
2355+
2356+/* clock */
2357+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
2358+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
2359+
2360+/* address */
2361+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
2362+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
2363+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
2364+
2365+/* control */
2366+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
2367+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
2368+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
2369+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
2370+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
2371+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
2372+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
2373+
2374+/* data strobe */
2375+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
2376+
2377+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
2378+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
2379+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
2380+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
2381+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
2382+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
2383+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
2384+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
2385+
2386+/* data */
2387+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
2388+
2389+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
2390+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
2391+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
2392+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
2393+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
2394+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
2395+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
2396+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
2397+
2398+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
2399+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
2400+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
2401+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
2402+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
2403+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
2404+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
2405+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
2406+
2407+/* calibrations */
2408+/* ZQ */
2409+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
2410+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
2411+
2412+/* write leveling */
2413+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001C001C)
2414+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0024001F)
2415+
2416+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x001A0037)
2417+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x001A002F)
2418+
2419+/* DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00 */
2420+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x43050315)
2421+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x02720272)
2422+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83c, 0x03220325)
2423+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x0312026B)
2424+
2425+/* read calibration */
2426+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x43393A3B)
2427+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x3E433A43)
2428+
2429+/* write calibration */
2430+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x47444C47)
2431+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x4D334F46)
2432+
2433+/* read data bit delay: (3 is the recommended default value, although out of reset value is 0) */
2434+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
2435+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
2436+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
2437+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
2438+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
2439+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
2440+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
2441+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
2442+
2443+/* complete calibration by forced measurment */
2444+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
2445+MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
2446+
2447+/* MMDC init */
2448+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
2449+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
2450+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
2451+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323)
2452+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8C63)
2453+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
2454+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00091740)
2455+
2456+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
2457+
2458+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
2459+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
2460+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
2461+
2462+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
2463+
2464+/* Initialize 2GB DDR3 - Micron MT41J128M */
2465+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
2466+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a)
2467+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
2468+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
2469+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
2470+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
2471+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
2472+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038)
2473+
2474+/* DDR device ZQ calibration */
2475+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
2476+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
2477+
2478+/* final DDR setup, before operation start */
2479+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
2480+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
2481+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
2482+
2483+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
2484+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
2485+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
2486+
2487+/* enable AXI cache for VDOA/VPU/IPU */
2488+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
2489+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
2490+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
2491+MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
2492+
2493+#endif
2494diff --git a/board/freescale/cgt_qmx6/lowlevel_init.S b/board/freescale/cgt_qmx6/lowlevel_init.S
2495new file mode 100644
2496index 0000000..4a31cb0
2497--- /dev/null
2498+++ b/board/freescale/cgt_qmx6/lowlevel_init.S
2499@@ -0,0 +1,167 @@
2500+/*
2501+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
2502+ *
2503+ * This program is free software; you can redistribute it and/or
2504+ * modify it under the terms of the GNU General Public License as
2505+ * published by the Free Software Foundation; either version 2 of
2506+ * the License, or (at your option) any later version.
2507+ *
2508+ * This program is distributed in the hope that it will be useful,
2509+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2510+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2511+ * GNU General Public License for more details.
2512+ *
2513+ * You should have received a copy of the GNU General Public License
2514+ * along with this program; if not, write to the Free Software
2515+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2516+ * MA 02111-1307 USA
2517+ */
2518+
2519+#include <config.h>
2520+#include <asm/arch/mx6.h>
2521+
2522+/*
2523+ Disable L2Cache because ROM turn it on when uboot use plug-in.
2524+ If L2Cache is on default, there are cache coherence problem if kernel have
2525+ not config L2Cache.
2526+*/
2527+.macro init_l2cc
2528+ ldr r1, =0xa02000
2529+ ldr r0, =0x0
2530+ str r0, [r1, #0x100]
2531+.endm /* init_l2cc */
2532+
2533+/* invalidate the D-CACHE */
2534+.macro inv_dcache
2535+ mov r0,#0
2536+ mcr p15,2,r0,c0,c0,0 /* cache size selection register, select dcache */
2537+ mrc p15,1,r0,c0,c0,0 /* cache size ID register */
2538+ mov r0,r0,ASR #13
2539+ ldr r3,=0xfff
2540+ and r0,r0,r3
2541+ cmp r0,#0x7f
2542+ moveq r6,#0x1000
2543+ beq size_done
2544+ cmp r0,#0xff
2545+ moveq r6,#0x2000
2546+ movne r6,#0x4000
2547+
2548+size_done:
2549+ mov r2,#0
2550+ mov r3,#0x40000000
2551+ mov r4,#0x80000000
2552+ mov r5,#0xc0000000
2553+
2554+d_inv_loop:
2555+ mcr p15,0,r2,c7,c6,2 /* invalidate dcache by set / way */
2556+ mcr p15,0,r3,c7,c6,2 /* invalidate dcache by set / way */
2557+ mcr p15,0,r4,c7,c6,2 /* invalidate dcache by set / way */
2558+ mcr p15,0,r5,c7,c6,2 /* invalidate dcache by set / way */
2559+ add r2,r2,#0x20
2560+ add r3,r3,#0x20
2561+ add r4,r4,#0x20
2562+ add r5,r5,#0x20
2563+
2564+ cmp r2,r6
2565+ bne d_inv_loop
2566+.endm
2567+
2568+/* AIPS setup - Only setup MPROTx registers.
2569+ * The PACR default values are good.*/
2570+.macro init_aips
2571+ /*
2572+ * Set all MPROTx to be non-bufferable, trusted for R/W,
2573+ * not forced to user-mode.
2574+ */
2575+ ldr r0, =AIPS1_ON_BASE_ADDR
2576+ ldr r1, =0x77777777
2577+ str r1, [r0, #0x0]
2578+ str r1, [r0, #0x4]
2579+ ldr r1, =0x0
2580+ str r1, [r0, #0x40]
2581+ str r1, [r0, #0x44]
2582+ str r1, [r0, #0x48]
2583+ str r1, [r0, #0x4C]
2584+ str r1, [r0, #0x50]
2585+
2586+ ldr r0, =AIPS2_ON_BASE_ADDR
2587+ ldr r1, =0x77777777
2588+ str r1, [r0, #0x0]
2589+ str r1, [r0, #0x4]
2590+ ldr r1, =0x0
2591+ str r1, [r0, #0x40]
2592+ str r1, [r0, #0x44]
2593+ str r1, [r0, #0x48]
2594+ str r1, [r0, #0x4C]
2595+ str r1, [r0, #0x50]
2596+.endm /* init_aips */
2597+
2598+.macro setup_pll pll, freq
2599+.endm
2600+
2601+.macro init_clock
2602+
2603+/* PLL1, PLL2, and PLL3 are enabled by ROM */
2604+#ifdef CONFIG_PLL3
2605+ /* enable PLL3 for UART */
2606+ ldr r0, ANATOP_BASE_ADDR_W
2607+
2608+ /* power up PLL */
2609+ ldr r1, [r0, #ANATOP_USB1]
2610+ orr r1, r1, #0x1000
2611+ str r1, [r0, #ANATOP_USB1]
2612+
2613+ /* enable PLL */
2614+ ldr r1, [r0, #ANATOP_USB1]
2615+ orr r1, r1, #0x2000
2616+ str r1, [r0, #ANATOP_USB1]
2617+
2618+ /* wait PLL lock */
2619+100:
2620+ ldr r1, [r0, #ANATOP_USB1]
2621+ mov r1, r1, lsr #31
2622+ cmp r1, #0x1
2623+ bne 100b
2624+
2625+ /* clear bypass bit */
2626+ ldr r1, [r0, #ANATOP_USB1]
2627+ and r1, r1, #0xfffeffff
2628+ str r1, [r0, #ANATOP_USB1]
2629+#endif
2630+
2631+ /* Restore the default values in the Gate registers */
2632+ ldr r0, CCM_BASE_ADDR_W
2633+ ldr r1, =0xC0003F
2634+ str r1, [r0, #CLKCTL_CCGR0]
2635+ ldr r1, =0x30FC00
2636+ str r1, [r0, #CLKCTL_CCGR1]
2637+ ldr r1, =0xFFFC000
2638+ str r1, [r0, #CLKCTL_CCGR2]
2639+ ldr r1, =0x3FF00000
2640+ str r1, [r0, #CLKCTL_CCGR3]
2641+ ldr r1, =0xFFF300
2642+ str r1, [r0, #CLKCTL_CCGR4]
2643+ ldr r1, =0xF0000C3
2644+ str r1, [r0, #CLKCTL_CCGR5]
2645+ ldr r1, =0x03FF
2646+ str r1, [r0, #CLKCTL_CCGR6]
2647+.endm
2648+
2649+.section ".text.init", "x"
2650+
2651+.globl lowlevel_init
2652+lowlevel_init:
2653+
2654+ inv_dcache
2655+
2656+ init_l2cc
2657+
2658+ init_aips
2659+
2660+ init_clock
2661+
2662+ mov pc, lr
2663+
2664+/* Board level setting value */
2665+ANATOP_BASE_ADDR_W: .word ANATOP_BASE_ADDR
2666+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
2667diff --git a/board/freescale/cgt_qmx6/u-boot.lds b/board/freescale/cgt_qmx6/u-boot.lds
2668new file mode 100644
2669index 0000000..28ee8e0
2670--- /dev/null
2671+++ b/board/freescale/cgt_qmx6/u-boot.lds
2672@@ -0,0 +1,74 @@
2673+/*
2674+ * January 2004 - Changed to support H4 device
2675+ * Copyright (c) 2004 Texas Instruments
2676+ *
2677+ * (C) Copyright 2002
2678+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
2679+ *
2680+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
2681+ *
2682+ * See file CREDITS for list of people who contributed to this
2683+ * project.
2684+ *
2685+ * This program is free software; you can redistribute it and/or
2686+ * modify it under the terms of the GNU General Public License as
2687+ * published by the Free Software Foundation; either version 2 of
2688+ * the License, or (at your option) any later version.
2689+ *
2690+ * This program is distributed in the hope that it will be useful,
2691+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2692+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2693+ * GNU General Public License for more details.
2694+ *
2695+ * You should have received a copy of the GNU General Public License
2696+ * along with this program; if not, write to the Free Software
2697+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2698+ * MA 02111-1307 USA
2699+ */
2700+
2701+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
2702+OUTPUT_ARCH(arm)
2703+ENTRY(_start)
2704+SECTIONS
2705+{
2706+ . = 0x00000000;
2707+
2708+ . = ALIGN(4);
2709+ .text :
2710+ {
2711+ /* WARNING - the following is hand-optimized to fit within */
2712+ /* the sector layout of our flash chips! XXX FIXME XXX */
2713+ board/freescale/cgt_qmx6/flash_header.o (.text.flasheader)
2714+ cpu/arm_cortexa8/start.o
2715+ board/freescale/cgt_qmx6/libcgt_qmx6.a (.text)
2716+ lib_arm/libarm.a (.text)
2717+ net/libnet.a (.text)
2718+ drivers/mtd/libmtd.a (.text)
2719+ drivers/mmc/libmmc.a (.text)
2720+
2721+ . = DEFINED(env_offset) ? env_offset : .;
2722+ common/env_embedded.o(.text)
2723+
2724+ *(.text)
2725+ }
2726+
2727+ . = ALIGN(4);
2728+ .rodata : { *(.rodata) }
2729+
2730+ . = ALIGN(4);
2731+ .data : { *(.data) }
2732+
2733+ . = ALIGN(4);
2734+ .got : { *(.got) }
2735+
2736+ . = .;
2737+ __u_boot_cmd_start = .;
2738+ .u_boot_cmd : { *(.u_boot_cmd) }
2739+ __u_boot_cmd_end = .;
2740+
2741+ . = ALIGN(4);
2742+ _end_of_copy = .; /* end_of ROM copy code here */
2743+ __bss_start = .;
2744+ .bss : { *(.bss) }
2745+ _end = .;
2746+}
2747diff --git a/common/cmd_mii.c b/common/cmd_mii.c
2748index 65e13c3..dfa45fe 100644
2749--- a/common/cmd_mii.c
2750+++ b/common/cmd_mii.c
2751@@ -300,12 +300,29 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
2752 unsigned short data;
2753 int rcode = 0;
2754 char *devname;
2755+ struct eth_device *current;
2756
2757 if (argc < 2) {
2758 cmd_usage(cmdtp);
2759 return 1;
2760 }
2761
2762+ current = eth_get_dev();
2763+ if (!current) {
2764+ puts ("No ethernet found.\n");
2765+ return -1;
2766+ }
2767+
2768+ if (current->state != ETH_STATE_ACTIVE)
2769+ {
2770+ eth_halt();
2771+ eth_set_current();
2772+ if (eth_init(NULL) < 0) {
2773+ eth_halt();
2774+ return(-1);
2775+ }
2776+ }
2777+
2778 #if defined(CONFIG_MII_INIT)
2779 mii_init ();
2780 #endif
2781diff --git a/drivers/mtd/spi/imx_spi_nor_sst.c b/drivers/mtd/spi/imx_spi_nor_sst.c
2782index d484a51..19ba1bf 100644
2783--- a/drivers/mtd/spi/imx_spi_nor_sst.c
2784+++ b/drivers/mtd/spi/imx_spi_nor_sst.c
2785@@ -61,9 +61,9 @@ static const struct imx_spi_flash_params imx_spi_flash_table[] = {
2786 {
2787 .idcode1 = 0x25,
2788 .block_size = SZ_64K,
2789- .block_count = 32,
2790- .device_size = SZ_64K * 32,
2791- .name = "SST25VF016B - 2MB",
2792+ .block_count = 64,
2793+ .device_size = SZ_64K * 64,
2794+ .name = "SST25VF032B - 4MB",
2795 },
2796 };
2797
2798@@ -184,6 +184,15 @@ static int spi_nor_erase_block(struct spi_flash *flash,
2799 block_addr);
2800 return -1;
2801 }
2802+
2803+ #ifndef CONFIG_MFGAREA_UNPROTECT
2804+ /* protect 16KB at the end of flash for manufacturing purpose */
2805+ if ((addr + block_size) > (flash->size - 16*1024))
2806+ {
2807+ printf("Error - tried to erase reserved area\n");
2808+ return -1;
2809+ }
2810+ #endif
2811
2812 if (ENABLE_WRITE_STATUS(flash) != 0 ||
2813 spi_nor_write_status(flash, 0) != 0) {
2814@@ -328,6 +337,15 @@ static int spi_nor_flash_write(struct spi_flash *flash, u32 offset,
2815 debug("%s(flash addr=0x%08x, ram=%p, len=0x%x)\n",
2816 __func__, offset, buf, len);
2817
2818+ #ifndef CONFIG_MFGAREA_UNPROTECT
2819+ /* protect 16KB at the end of flash for manufacturing purpose */
2820+ if ((d_addr + len) > (flash->size - 16*1024))
2821+ {
2822+ printf("Error - tried to write to reserved area\n");
2823+ return -1;
2824+ }
2825+ #endif
2826+
2827 if (ENABLE_WRITE_STATUS(flash) != 0 ||
2828 spi_nor_write_status(flash, 0) != 0) {
2829 printf("Error: %s: %d\n", __func__, __LINE__);
2830diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
2831index a1fee0e..06ec506 100644
2832--- a/include/asm-arm/mach-types.h
2833+++ b/include/asm-arm/mach-types.h
2834@@ -3259,6 +3259,7 @@ extern unsigned int __machine_arch_type;
2835 #define MACH_TYPE_MX6Q_ARM2 3837
2836 #define MACH_TYPE_MX6Q_SABRESD 3980
2837 #define MACH_TYPE_MX6SL_ARM2 4091
2838+#define MACH_TYPE_CGT_QMX6 4122
2839 #define MACH_TYPE_MX6Q_HDMIDONGLE 4284
2840 #define MACH_TYPE_MX6SL_EVK 4307
2841
2842@@ -42214,6 +42215,18 @@ extern unsigned int __machine_arch_type;
2843 # define machine_is_mx6sl_evk() (0)
2844 #endif
2845
2846+#ifdef CONFIG_MACH_CGT_QMX6
2847+# ifdef machine_arch_type
2848+# undef machine_arch_type
2849+# define machine_arch_type __machine_arch_type
2850+# else
2851+# define machine_arch_type MACH_TYPE_CGT_QMX6
2852+# endif
2853+# define machine_is_cgt_qmx6() (machine_arch_type == MACH_TYPE_CGT_QMX6)
2854+#else
2855+# define machine_is_cgt_qmx6() (0)
2856+#endif
2857+
2858 /*
2859 * These have not yet been registered
2860 */
2861diff --git a/include/configs/cgt_qmx6.h b/include/configs/cgt_qmx6.h
2862new file mode 100644
2863index 0000000..fdfe5c1
2864--- /dev/null
2865+++ b/include/configs/cgt_qmx6.h
2866@@ -0,0 +1,364 @@
2867+/*
2868+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
2869+ *
2870+ * Configuration settings for the congatec QMX6 i.MX6 cpu module.
2871+ *
2872+ * This program is free software; you can redistribute it and/or
2873+ * modify it under the terms of the GNU General Public License as
2874+ * published by the Free Software Foundation; either version 2 of
2875+ * the License, or (at your option) any later version.
2876+ *
2877+ * This program is distributed in the hope that it will be useful,
2878+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2879+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2880+ * GNU General Public License for more details.
2881+ *
2882+ * You should have received a copy of the GNU General Public License
2883+ * along with this program; if not, write to the Free Software
2884+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
2885+ * MA 02111-1307 USA
2886+ */
2887+
2888+#ifndef __CONFIG_H
2889+#define __CONFIG_H
2890+
2891+#include <asm/arch/mx6.h>
2892+
2893+/* congatec product selection */
2894+/* uncomment one of the configuration switches below in order to build a bootloader for conga-QMX6 */
2895+/* enabling CONFIG_QMX6_PN016104 builds a bootloader for conga-QMX6 module, part number 016104, equipped i.MX6 1GHz QuadCore, 2GByte onboard DDR3 memory */
2896+/* enabling CONFIG_QMX6_PN016101 builds a bootloader for conga-QMX6 module, part number 016101, equipped i.MX6 1GHz DualCore Lite, 1GByte onboard DDR3 memory */
2897+#define CONFIG_QMX6_PN016104
2898+//#define CONFIG_QMX6_PN016101
2899+
2900+/* uncomment in order to build special trace version of bootloader */
2901+// #define CONFIG_QMX6_TRACE
2902+
2903+ /* High Level Configuration Options */
2904+#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
2905+#define CONFIG_MXC
2906+
2907+#ifdef CONFIG_QMX6_PN016101
2908+#define CONFIG_QMX6_PN 016101
2909+#define CONFIG_MX6DL
2910+#endif
2911+
2912+#ifdef CONFIG_QMX6_PN016104
2913+#define CONFIG_QMX6_PN 016104
2914+#define CONFIG_MX6Q
2915+#endif
2916+
2917+#define CONFIG_FLASH_HEADER
2918+#define CONFIG_FLASH_HEADER_OFFSET 0x400
2919+#define CONFIG_MX6_CLK32 32768
2920+
2921+#define CONFIG_SKIP_RELOCATE_UBOOT
2922+
2923+#define CONFIG_ARCH_CPU_INIT
2924+#undef CONFIG_ARCH_MMU /* disable MMU first */
2925+#define CONFIG_L2_OFF /* disable L2 cache first*/
2926+
2927+#define CONFIG_MX6_HCLK_FREQ 24000000
2928+
2929+#define CONFIG_DISPLAY_CPUINFO
2930+#define CONFIG_DISPLAY_BOARDINFO
2931+
2932+#define CONFIG_SYS_64BIT_VSPRINTF
2933+
2934+#define BOARD_LATE_INIT
2935+
2936+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
2937+#define CONFIG_REVISION_TAG
2938+#define CONFIG_SETUP_MEMORY_TAGS
2939+#define CONFIG_INITRD_TAG
2940+
2941+/*
2942+ * Size of malloc() pool
2943+ */
2944+#ifdef CONFIG_QMX6_PN016104
2945+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
2946+#endif
2947+#ifdef CONFIG_QMX6_PN016101
2948+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
2949+#endif
2950+/* size in bytes reserved for initial data */
2951+#define CONFIG_SYS_GBL_DATA_SIZE 128
2952+
2953+/*
2954+ * Hardware drivers
2955+ */
2956+#define CONFIG_MXC_UART
2957+#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
2958+
2959+/* allow to overwrite serial and ethaddr */
2960+#define CONFIG_ENV_OVERWRITE
2961+#define CONFIG_CONS_INDEX 1
2962+#define CONFIG_BAUDRATE 115200
2963+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
2964+
2965+/***********************************************************
2966+ * Command definition
2967+ ***********************************************************/
2968+
2969+#include <config_cmd_default.h>
2970+
2971+#define CONFIG_CMD_PING
2972+#define CONFIG_CMD_DHCP
2973+#define CONFIG_CMD_MII
2974+#define CONFIG_CMD_NET
2975+#define CONFIG_NET_RETRY_COUNT 100
2976+#define CONFIG_NET_MULTI 1
2977+#define CONFIG_BOOTP_SUBNETMASK
2978+#define CONFIG_BOOTP_GATEWAY
2979+#define CONFIG_BOOTP_DNS
2980+
2981+#define CONFIG_CMD_SPI
2982+#define CONFIG_CMD_I2C
2983+
2984+/* Enable below configure when supporting nand */
2985+
2986+#define CONFIG_CMD_MMC
2987+#define CONFIG_MMC_8BIT_PORTS 0x00000002
2988+#define CONFIG_CMD_SF
2989+#define CONFIG_CMD_ENV
2990+#define CONFIG_CMD_REGUL
2991+
2992+#define CONFIG_CMD_CLOCK
2993+#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
2994+
2995+#ifdef CONFIG_QMX6_PN016104
2996+#define CONFIG_CMD_SATA
2997+#endif
2998+#undef CONFIG_CMD_IMLS
2999+
3000+#define CONFIG_CMD_IMX_DOWNLOAD_MODE
3001+
3002+#define CONFIG_BOOTDELAY 3
3003+
3004+#define CONFIG_PRIME "FEC0"
3005+
3006+#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
3007+#define CONFIG_RD_LOADADDR 0x11000000
3008+
3009+#define CONFIG_EXTRA_ENV_SETTINGS \
3010+ "netdev=eth0\0" \
3011+ "ethprime=FEC0\0" \
3012+ "ethaddr=00:00:00:00:00:00\0" \
3013+ "uboot=u-boot.bin\0" \
3014+ "kernel=uImage\0" \
3015+ "vid_dev0=hdmi,1920x1080M@60,if=RGB24\0" \
3016+ "vid_dev1=ldb,LDB-XGA,if=RGB666\0" \
3017+ "bootargs=console=ttymxc1,115200\0" \
3018+ "bootargs_base=setenv bootargs ${bootargs} " \
3019+ "video=mxcfb0:dev=${vid_dev0} " \
3020+ "video=mxcfb2:dev=${vid_dev1}\0" \
3021+ "bootargs_mmc=setenv bootargs ${bootargs} rootwait enable_wait_mode=on\0" \
3022+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
3023+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
3024+ "enable_wait_mode=off\0" \
3025+ "bootcmd_net=dhcp; run bootargs_base bootargs_nfs;bootm\0" \
3026+ "bootcmd_mmc=run bootargs_base bootargs_mmc;" \
3027+ "for disk in 0 1 2; do mmc dev ${disk};" \
3028+ "for fs in fat ext2 ; do " \
3029+ "${fs}load mmc ${disk}:1 10008000 " \
3030+ "/6q_bootscript && " \
3031+ "source 10008000 ; " \
3032+ "done ; " \
3033+ "done\0" \
3034+ "bootcmd=run bootcmd_mmc\0" \
3035+ "clearenv=sf probe 1 && sf erase 0xc0000 0x2000 && " \
3036+ "echo restored environment to factory default\0" \
3037+ "upgradeu=for disk in 0 1 2; do mmc dev ${disk} ;" \
3038+ "for fs in fat ext2 ; do " \
3039+ "${fs}load mmc ${disk}:1 10008000 " \
3040+ "/6q_upgrade && " \
3041+ "source 10008000 ; " \
3042+ "done ; " \
3043+ "done\0" \
3044+ "bootfile=_BOOT_FILE_PATH_IN_TFTP_\0" \
3045+ "nfsroot=_ROOTFS_PATH_IN_NFS_\0"
3046+
3047+
3048+#define CONFIG_ARP_TIMEOUT 200UL
3049+
3050+/*
3051+ * Miscellaneous configurable options
3052+ */
3053+#define CONFIG_SYS_LONGHELP /* undef to save memory */
3054+#define CONFIG_SYS_PROMPT "conga-QMX6 U-Boot > "
3055+#define CONFIG_AUTO_COMPLETE
3056+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
3057+/* Print Buffer Size */
3058+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
3059+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
3060+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
3061+
3062+#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
3063+#define CONFIG_SYS_MEMTEST_END 0x10010000
3064+
3065+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
3066+
3067+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
3068+
3069+#define CONFIG_SYS_HZ 1000
3070+
3071+#define CONFIG_CMDLINE_EDITING
3072+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
3073+#ifdef CONFIG_SYS_HUSH_PARSER
3074+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
3075+#endif
3076+
3077+#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
3078+#define CONFIG_FEC0_PINMUX -1
3079+#define CONFIG_FEC0_MIIBASE -1
3080+#define CONFIG_GET_FEC_MAC_ADDR_FROM_ENV
3081+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
3082+#define CONFIG_MXC_FEC
3083+#define CONFIG_FEC0_PHY_ADDR 6
3084+#define CONFIG_ETH_PRIME
3085+#define CONFIG_RMII
3086+#define CONFIG_PHY_MICREL_KSZ9021
3087+#define CONFIG_CMD_MII
3088+#define CONFIG_CMD_DHCP
3089+#define CONFIG_CMD_PING
3090+#define CONFIG_IPADDR 192.168.1.103
3091+
3092+/*The IP ADDRESS of SERVERIP*/
3093+#define CONFIG_SERVERIP _SERVER_IP_ADDR_
3094+
3095+#define CONFIG_NETMASK 255.255.255.0
3096+
3097+/*
3098+ * OCOTP Configs
3099+ */
3100+#ifdef CONFIG_CMD_IMXOTP
3101+ #define CONFIG_IMX_OTP
3102+ #define IMX_OTP_BASE OCOTP_BASE_ADDR
3103+ #define IMX_OTP_ADDR_MAX 0x7F
3104+ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
3105+#endif
3106+
3107+/*
3108+ * I2C Configs
3109+ */
3110+#ifdef CONFIG_CMD_I2C
3111+ #define CONFIG_HARD_I2C 1
3112+ #define CONFIG_I2C_MXC 1
3113+ #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
3114+ #define CONFIG_SYS_I2C_SPEED 100000
3115+ #define CONFIG_SYS_I2C_SLAVE 0x08
3116+#endif
3117+
3118+/*
3119+ * SPI Configs
3120+ */
3121+#ifdef CONFIG_CMD_SF
3122+ #define CONFIG_FSL_SF 1
3123+ #define CONFIG_SPI_FLASH_IMX_SST 1
3124+ #define CONFIG_SPI_FLASH_CS 1
3125+ #define CONFIG_IMX_ECSPI
3126+ #define IMX_CSPI_VER_2_3 1
3127+ #define MAX_SPI_BYTES (64 * 4)
3128+#endif
3129+
3130+/* Regulator Configs */
3131+#ifdef CONFIG_CMD_REGUL
3132+ #define CONFIG_ANATOP_REGULATOR
3133+ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
3134+ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
3135+#endif
3136+
3137+/*
3138+ * MMC Configs
3139+ */
3140+#ifdef CONFIG_CMD_MMC
3141+ #define CONFIG_MMC
3142+ #define CONFIG_GENERIC_MMC
3143+ #define CONFIG_IMX_MMC
3144+ #define CONFIG_SYS_FSL_USDHC_NUM 3
3145+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
3146+ #define CONFIG_SYS_MMC_ENV_DEV 2
3147+ #define CONFIG_DOS_PARTITION 1
3148+ #define CONFIG_CMD_FAT 1
3149+ #define CONFIG_CMD_EXT2 1
3150+
3151+ /* detect whether SD1, 2, 3, or 4 is boot device */
3152+ #define CONFIG_DYNAMIC_MMC_DEVNO
3153+
3154+ /* Setup target delay in DDR mode for each SD port */
3155+ #define CONFIG_GET_DDR_TARGET_DELAY
3156+#endif
3157+
3158+/*
3159+ * SATA Configs
3160+ */
3161+#ifdef CONFIG_CMD_SATA
3162+ #define CONFIG_DWC_AHSATA
3163+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
3164+ #define CONFIG_DWC_AHSATA_PORT_ID 0
3165+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
3166+ #define CONFIG_LBA48
3167+ #define CONFIG_LIBATA
3168+
3169+ #define CONFIG_DOS_PARTITION 1
3170+ #define CONFIG_CMD_FAT 1
3171+ #define CONFIG_CMD_EXT2 1
3172+#endif
3173+
3174+/*
3175+ * USB OTG
3176+ */
3177+#define CONFIG_IMX_UDC 1
3178+
3179+/*-----------------------------------------------------------------------
3180+ * Stack sizes
3181+ *
3182+ * The stack sizes are set up in start.S using the settings below
3183+ */
3184+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
3185+
3186+/*-----------------------------------------------------------------------
3187+ * Physical Memory Map
3188+ */
3189+#define CONFIG_NR_DRAM_BANKS 1
3190+#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
3191+#ifdef CONFIG_QMX6_PN016104
3192+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
3193+#endif
3194+#ifdef CONFIG_QMX6_PN016101
3195+#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
3196+#endif
3197+#define iomem_valid_addr(addr, size) \
3198+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
3199+
3200+/*-----------------------------------------------------------------------
3201+ * FLASH and environment organization
3202+ */
3203+#define CONFIG_SYS_NO_FLASH
3204+
3205+/* Monitor at beginning of flash */
3206+/* #define CONFIG_FSL_ENV_IN_MMC */
3207+/* #define CONFIG_FSL_ENV_IN_SATA */
3208+#define CONFIG_FSL_ENV_IN_SF
3209+
3210+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
3211+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
3212+
3213+#if defined(CONFIG_FSL_ENV_IN_NAND)
3214+ #define CONFIG_ENV_IS_IN_NAND 1
3215+ #define CONFIG_ENV_OFFSET 0x100000
3216+#elif defined(CONFIG_FSL_ENV_IN_MMC)
3217+ #define CONFIG_ENV_IS_IN_MMC 1
3218+ #define CONFIG_ENV_OFFSET (768 * 1024)
3219+#elif defined(CONFIG_FSL_ENV_IN_SATA)
3220+ #define CONFIG_ENV_IS_IN_SATA 1
3221+ #define CONFIG_SATA_ENV_DEV 0
3222+ #define CONFIG_ENV_OFFSET (768 * 1024)
3223+#elif defined(CONFIG_FSL_ENV_IN_SF)
3224+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
3225+ #define CONFIG_ENV_SPI_CS 1
3226+ #define CONFIG_ENV_OFFSET (768 * 1024)
3227+#else
3228+ #define CONFIG_ENV_IS_NOWHERE 1
3229+#endif
3230+#endif /* __CONFIG_H */
3231diff --git a/include/configs/cgt_qmx6_android.h b/include/configs/cgt_qmx6_android.h
3232new file mode 100644
3233index 0000000..9c3a80d
3234--- /dev/null
3235+++ b/include/configs/cgt_qmx6_android.h
3236@@ -0,0 +1,360 @@
3237+/*
3238+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
3239+ *
3240+ * Configuration settings for the MX6Q SABRE-Lite Freescale board.
3241+ *
3242+ * This program is free software; you can redistribute it and/or
3243+ * modify it under the terms of the GNU General Public License as
3244+ * published by the Free Software Foundation; either version 2 of
3245+ * the License, or (at your option) any later version.
3246+ *
3247+ * This program is distributed in the hope that it will be useful,
3248+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3249+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3250+ * GNU General Public License for more details.
3251+ *
3252+ * You should have received a copy of the GNU General Public License
3253+ * along with this program; if not, write to the Free Software
3254+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3255+ * MA 02111-1307 USA
3256+ */
3257+
3258+#ifndef __CONFIG_H
3259+#define __CONFIG_H
3260+
3261+#include <asm/arch/mx6.h>
3262+
3263+/* congatec product selection */
3264+/* uncomment one of the configuration switches below in order to build a bootloader for conga-QMX6 */
3265+/* enabling CONFIG_QMX6_PN016104 builds a bootloader for conga-QMX6 module, part number 016104, equipped i.MX6 1GHz QuadCore, 2GByte onboard DDR3 memory */
3266+/* enabling CONFIG_QMX6_PN016101 builds a bootloader for conga-QMX6 module, part number 016101, equipped i.MX6 1GHz DualCore Lite, 1GByte onboard DDR3 memory */
3267+//#define CONFIG_QMX6_PN016104
3268+//#define CONFIG_QMX6_PN016101
3269+
3270+/* uncomment in order to build special trace version of bootloader */
3271+// #define CONFIG_QMX6_TRACE
3272+
3273+ /* High Level Configuration Options */
3274+#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
3275+#define CONFIG_MXC
3276+
3277+#ifdef CONFIG_QMX6_PN016101
3278+#define CONFIG_QMX6_PN 016101
3279+#define CONFIG_MX6DL
3280+#endif
3281+
3282+#ifdef CONFIG_QMX6_PN016104
3283+#define CONFIG_QMX6_PN 016104
3284+#define CONFIG_MX6Q
3285+#endif
3286+
3287+#define CONFIG_FLASH_HEADER
3288+#define CONFIG_FLASH_HEADER_OFFSET 0x400
3289+#define CONFIG_MX6_CLK32 32768
3290+
3291+#define CONFIG_SKIP_RELOCATE_UBOOT
3292+
3293+#define CONFIG_ARCH_CPU_INIT
3294+#undef CONFIG_ARCH_MMU /* disable MMU first */
3295+#define CONFIG_L2_OFF /* disable L2 cache first*/
3296+
3297+#define CONFIG_MX6_HCLK_FREQ 24000000
3298+
3299+#define CONFIG_DISPLAY_CPUINFO
3300+#define CONFIG_DISPLAY_BOARDINFO
3301+
3302+#define CONFIG_SYS_64BIT_VSPRINTF
3303+
3304+#define BOARD_LATE_INIT
3305+
3306+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
3307+#define CONFIG_REVISION_TAG
3308+#define CONFIG_SETUP_MEMORY_TAGS
3309+#define CONFIG_INITRD_TAG
3310+
3311+/*
3312+ * Size of malloc() pool
3313+ */
3314+#ifdef CONFIG_QMX6_PN016104
3315+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
3316+#endif
3317+#ifdef CONFIG_QMX6_PN016101
3318+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
3319+#endif
3320+/* size in bytes reserved for initial data */
3321+#define CONFIG_SYS_GBL_DATA_SIZE 128
3322+
3323+/*
3324+ * Hardware drivers
3325+ */
3326+#define CONFIG_MXC_UART
3327+#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
3328+
3329+/* allow to overwrite serial and ethaddr */
3330+#define CONFIG_ENV_OVERWRITE
3331+#define CONFIG_CONS_INDEX 1
3332+#define CONFIG_BAUDRATE 115200
3333+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
3334+
3335+/* Android related config */
3336+#define CONFIG_USB_DEVICE
3337+#define CONFIG_IMX_UDC 1
3338+#define CONFIG_FASTBOOT 1
3339+#define CONFIG_FASTBOOT_STORAGE_EMMC_SATA
3340+#define CONFIG_FASTBOOT_VENDOR_ID 0xbb4
3341+#define CONFIG_FASTBOOT_PRODUCT_ID 0xc01
3342+#define CONFIG_FASTBOOT_BCD_DEVICE 0x311
3343+#define CONFIG_FASTBOOT_MANUFACTURER_STR "Freescale"
3344+#define CONFIG_FASTBOOT_PRODUCT_NAME_STR "i.mx6q qmx6"
3345+#define CONFIG_FASTBOOT_INTERFACE_STR "Android fastboot"
3346+#define CONFIG_FASTBOOT_CONFIGURATION_STR "Android fastboot"
3347+#define CONFIG_FASTBOOT_SERIAL_NUM "12345"
3348+#define CONFIG_FASTBOOT_SATA_NO 0
3349+#define CONFIG_FASTBOOT_TRANSFER_BUF 0x30000000
3350+#define CONFIG_FASTBOOT_TRANSFER_BUF_SIZE 0x10000000 /* 256M byte */
3351+
3352+#define CONFIG_CMD_BOOTI
3353+#define CONFIG_ANDROID_RECOVERY
3354+#define CONFIG_ANDROID_BOOT_PARTITION_MMC 1
3355+#define CONFIG_ANDROID_SYSTEM_PARTITION_MMC 5
3356+#define CONFIG_ANDROID_RECOVERY_PARTITION_MMC 2
3357+#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
3358+
3359+#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC NULL
3360+#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \
3361+ "booti mmc1 recovery"
3362+#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command"
3363+
3364+/***********************************************************
3365+ * Command definition
3366+ ***********************************************************/
3367+
3368+#include <config_cmd_default.h>
3369+
3370+#define CONFIG_CMD_PING
3371+#define CONFIG_CMD_DHCP
3372+#define CONFIG_CMD_MII
3373+#define CONFIG_CMD_NET
3374+#define CONFIG_NET_RETRY_COUNT 100
3375+#define CONFIG_NET_MULTI 1
3376+#define CONFIG_BOOTP_SUBNETMASK
3377+#define CONFIG_BOOTP_GATEWAY
3378+#define CONFIG_BOOTP_DNS
3379+
3380+#define CONFIG_CMD_SPI
3381+#define CONFIG_CMD_I2C
3382+
3383+/* Enable below configure when supporting nand */
3384+
3385+#define CONFIG_CMD_MMC
3386+#define CONFIG_MMC_8BIT_PORTS 0x00000002
3387+#define CONFIG_CMD_SF
3388+#define CONFIG_CMD_ENV
3389+#define CONFIG_CMD_REGUL
3390+
3391+#define CONFIG_CMD_CLOCK
3392+#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
3393+
3394+#ifdef CONFIG_QMX6_PN016104
3395+#define CONFIG_CMD_SATA
3396+#endif
3397+#undef CONFIG_CMD_IMLS
3398+
3399+#define CONFIG_CMD_IMX_DOWNLOAD_MODE
3400+
3401+#define CONFIG_BOOTDELAY 3
3402+
3403+#define CONFIG_PRIME "FEC0"
3404+
3405+#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
3406+#define CONFIG_RD_LOADADDR 0x11000000
3407+
3408+#define CONFIG_INITRD_TAG
3409+
3410+#define CONFIG_EXTRA_ENV_SETTINGS \
3411+ "netdev=eth0\0" \
3412+ "ethprime=FEC0\0" \
3413+ "bootcmd=booti mmc1\0"
3414+#define CONFIG_ARP_TIMEOUT 200UL
3415+
3416+/*
3417+ * Miscellaneous configurable options
3418+ */
3419+#define CONFIG_SYS_LONGHELP /* undef to save memory */
3420+#define CONFIG_SYS_PROMPT "conga-QMX6 U-Boot > "
3421+#define CONFIG_AUTO_COMPLETE
3422+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
3423+/* Print Buffer Size */
3424+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
3425+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
3426+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
3427+
3428+#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
3429+#define CONFIG_SYS_MEMTEST_END 0x10010000
3430+
3431+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
3432+
3433+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
3434+
3435+#define CONFIG_SYS_HZ 1000
3436+
3437+#define CONFIG_CMDLINE_EDITING
3438+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
3439+#ifdef CONFIG_SYS_HUSH_PARSER
3440+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
3441+#endif
3442+
3443+#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
3444+#define CONFIG_FEC0_PINMUX -1
3445+#define CONFIG_FEC0_MIIBASE -1
3446+#define CONFIG_GET_FEC_MAC_ADDR_FROM_ENV
3447+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
3448+#define CONFIG_MXC_FEC
3449+#define CONFIG_FEC0_PHY_ADDR 6
3450+#define CONFIG_ETH_PRIME
3451+#define CONFIG_RMII
3452+#define CONFIG_PHY_MICREL_KSZ9021
3453+#define CONFIG_CMD_MII
3454+#define CONFIG_CMD_DHCP
3455+#define CONFIG_CMD_PING
3456+#define CONFIG_IPADDR 192.168.1.103
3457+
3458+/*The IP ADDRESS of SERVERIP*/
3459+#define CONFIG_SERVERIP _SERVER_IP_ADDR_
3460+
3461+#define CONFIG_NETMASK 255.255.255.0
3462+
3463+/*
3464+ * OCOTP Configs
3465+ */
3466+#ifdef CONFIG_CMD_IMXOTP
3467+ #define CONFIG_IMX_OTP
3468+ #define IMX_OTP_BASE OCOTP_BASE_ADDR
3469+ #define IMX_OTP_ADDR_MAX 0x7F
3470+ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
3471+#endif
3472+
3473+/*
3474+ * I2C Configs
3475+ */
3476+#ifdef CONFIG_CMD_I2C
3477+ #define CONFIG_HARD_I2C 1
3478+ #define CONFIG_I2C_MXC 1
3479+ #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
3480+ #define CONFIG_SYS_I2C_SPEED 100000
3481+ #define CONFIG_SYS_I2C_SLAVE 0x08
3482+#endif
3483+
3484+/*
3485+ * SPI Configs
3486+ */
3487+#ifdef CONFIG_CMD_SF
3488+ #define CONFIG_FSL_SF 1
3489+ #define CONFIG_SPI_FLASH_IMX_SST 1
3490+ #define CONFIG_SPI_FLASH_CS 1
3491+ #define CONFIG_IMX_ECSPI
3492+ #define IMX_CSPI_VER_2_3 1
3493+ #define MAX_SPI_BYTES (64 * 4)
3494+#endif
3495+
3496+/* Regulator Configs */
3497+#ifdef CONFIG_CMD_REGUL
3498+ #define CONFIG_ANATOP_REGULATOR
3499+ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
3500+ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
3501+#endif
3502+
3503+/*
3504+ * MMC Configs
3505+ */
3506+#ifdef CONFIG_CMD_MMC
3507+ #define CONFIG_MMC
3508+ #define CONFIG_GENERIC_MMC
3509+ #define CONFIG_IMX_MMC
3510+ #define CONFIG_SYS_FSL_USDHC_NUM 3
3511+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
3512+ #define CONFIG_SYS_MMC_ENV_DEV 2
3513+ #define CONFIG_DOS_PARTITION 1
3514+ #define CONFIG_CMD_FAT 1
3515+ #define CONFIG_CMD_EXT2 1
3516+
3517+ /* detect whether SD1, 2, 3, or 4 is boot device */
3518+ #define CONFIG_DYNAMIC_MMC_DEVNO
3519+
3520+ /* Setup target delay in DDR mode for each SD port */
3521+ #define CONFIG_GET_DDR_TARGET_DELAY
3522+#endif
3523+
3524+/*
3525+ * SATA Configs
3526+ */
3527+#ifdef CONFIG_CMD_SATA
3528+ #define CONFIG_DWC_AHSATA
3529+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
3530+ #define CONFIG_DWC_AHSATA_PORT_ID 0
3531+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
3532+ #define CONFIG_LBA48
3533+ #define CONFIG_LIBATA
3534+
3535+ #define CONFIG_DOS_PARTITION 1
3536+ #define CONFIG_CMD_FAT 1
3537+ #define CONFIG_CMD_EXT2 1
3538+#endif
3539+
3540+/*
3541+ * USB OTG
3542+ */
3543+#define CONFIG_IMX_UDC 1
3544+
3545+/*-----------------------------------------------------------------------
3546+ * Stack sizes
3547+ *
3548+ * The stack sizes are set up in start.S using the settings below
3549+ */
3550+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
3551+
3552+/*-----------------------------------------------------------------------
3553+ * Physical Memory Map
3554+ */
3555+#define CONFIG_NR_DRAM_BANKS 1
3556+#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
3557+#ifdef CONFIG_QMX6_PN016104
3558+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
3559+#endif
3560+#ifdef CONFIG_QMX6_PN016101
3561+#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
3562+#endif
3563+#define iomem_valid_addr(addr, size) \
3564+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
3565+
3566+/*-----------------------------------------------------------------------
3567+ * FLASH and environment organization
3568+ */
3569+#define CONFIG_SYS_NO_FLASH
3570+
3571+/* Monitor at beginning of flash */
3572+/* #define CONFIG_FSL_ENV_IN_MMC */
3573+/* #define CONFIG_FSL_ENV_IN_SATA */
3574+#define CONFIG_FSL_ENV_IN_SF
3575+
3576+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
3577+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
3578+
3579+#if defined(CONFIG_FSL_ENV_IN_NAND)
3580+ #define CONFIG_ENV_IS_IN_NAND 1
3581+ #define CONFIG_ENV_OFFSET 0x100000
3582+#elif defined(CONFIG_FSL_ENV_IN_MMC)
3583+ #define CONFIG_ENV_IS_IN_MMC 1
3584+ #define CONFIG_ENV_OFFSET (768 * 1024)
3585+#elif defined(CONFIG_FSL_ENV_IN_SATA)
3586+ #define CONFIG_ENV_IS_IN_SATA 1
3587+ #define CONFIG_SATA_ENV_DEV 0
3588+ #define CONFIG_ENV_OFFSET (768 * 1024)
3589+#elif defined(CONFIG_FSL_ENV_IN_SF)
3590+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
3591+ #define CONFIG_ENV_SPI_CS 1
3592+ #define CONFIG_ENV_OFFSET (768 * 1024)
3593+#else
3594+ #define CONFIG_ENV_IS_NOWHERE 1
3595+#endif
3596+#endif /* __CONFIG_H */
3597diff --git a/include/configs/cgt_qmx6_mfg.h b/include/configs/cgt_qmx6_mfg.h
3598new file mode 100644
3599index 0000000..8a8ba20
3600--- /dev/null
3601+++ b/include/configs/cgt_qmx6_mfg.h
3602@@ -0,0 +1,320 @@
3603+/*
3604+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
3605+ *
3606+ * Configuration settings for the MX6Q SABRE-Lite Freescale board.
3607+ *
3608+ * This program is free software; you can redistribute it and/or
3609+ * modify it under the terms of the GNU General Public License as
3610+ * published by the Free Software Foundation; either version 2 of
3611+ * the License, or (at your option) any later version.
3612+ *
3613+ * This program is distributed in the hope that it will be useful,
3614+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3615+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3616+ * GNU General Public License for more details.
3617+ *
3618+ * You should have received a copy of the GNU General Public License
3619+ * along with this program; if not, write to the Free Software
3620+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
3621+ * MA 02111-1307 USA
3622+ */
3623+
3624+#ifndef __CONFIG_H
3625+#define __CONFIG_H
3626+
3627+#include <asm/arch/mx6.h>
3628+
3629+/* congatec product selection */
3630+/* uncomment one of the configuration switches below in order to build a bootloader for conga-QMX6 */
3631+/* enabling CONFIG_QMX6_PN016104 builds a bootloader for conga-QMX6 module, part number 016104, equipped i.MX6 1GHz QuadCore, 2GByte onboard DDR3 memory */
3632+/* enabling CONFIG_QMX6_PN016101 builds a bootloader for conga-QMX6 module, part number 016101, equipped i.MX6 1GHz DualCore Lite, 1GByte onboard DDR3 memory */
3633+//#define CONFIG_QMX6_PN016104
3634+//#define CONFIG_QMX6_PN016101
3635+
3636+/* uncomment in order to build special trace version of bootloader */
3637+// #define CONFIG_QMX6_TRACE
3638+
3639+ /* High Level Configuration Options */
3640+#define CONFIG_MFG
3641+#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
3642+#define CONFIG_MXC
3643+
3644+#ifdef CONFIG_QMX6_PN016101
3645+#define CONFIG_QMX6_PN 016101
3646+#define CONFIG_MX6DL
3647+#endif
3648+
3649+#ifdef CONFIG_QMX6_PN016104
3650+#define CONFIG_QMX6_PN 016104
3651+#define CONFIG_MX6Q
3652+#endif
3653+
3654+#define CONFIG_FLASH_HEADER
3655+#define CONFIG_FLASH_HEADER_OFFSET 0x400
3656+#define CONFIG_MX6_CLK32 32768
3657+
3658+#define CONFIG_SKIP_RELOCATE_UBOOT
3659+
3660+#define CONFIG_ARCH_CPU_INIT
3661+#undef CONFIG_ARCH_MMU /* disable MMU first */
3662+#define CONFIG_L2_OFF /* disable L2 cache first*/
3663+
3664+#define CONFIG_MX6_HCLK_FREQ 24000000
3665+
3666+#define CONFIG_DISPLAY_CPUINFO
3667+#define CONFIG_DISPLAY_BOARDINFO
3668+
3669+#define CONFIG_SYS_64BIT_VSPRINTF
3670+
3671+#define BOARD_LATE_INIT
3672+
3673+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
3674+#define CONFIG_REVISION_TAG
3675+#define CONFIG_SETUP_MEMORY_TAGS
3676+#define CONFIG_INITRD_TAG
3677+
3678+/*
3679+ * Size of malloc() pool
3680+ */
3681+#ifdef CONFIG_QMX6_PN016104
3682+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
3683+#endif
3684+#ifdef CONFIG_QMX6_PN016101
3685+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
3686+#endif
3687+/* size in bytes reserved for initial data */
3688+#define CONFIG_SYS_GBL_DATA_SIZE 128
3689+
3690+/*
3691+ * Hardware drivers
3692+ */
3693+#define CONFIG_MXC_UART
3694+#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
3695+
3696+/* allow to overwrite serial and ethaddr */
3697+#define CONFIG_ENV_OVERWRITE
3698+#define CONFIG_CONS_INDEX 1
3699+#define CONFIG_BAUDRATE 115200
3700+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
3701+
3702+/***********************************************************
3703+ * Command definition
3704+ ***********************************************************/
3705+
3706+#include <config_cmd_default.h>
3707+
3708+#define CONFIG_CMD_PING
3709+#define CONFIG_CMD_DHCP
3710+#define CONFIG_CMD_MII
3711+#define CONFIG_CMD_NET
3712+#define CONFIG_NET_RETRY_COUNT 100
3713+#define CONFIG_NET_MULTI 1
3714+#define CONFIG_BOOTP_SUBNETMASK
3715+#define CONFIG_BOOTP_GATEWAY
3716+#define CONFIG_BOOTP_DNS
3717+
3718+#define CONFIG_CMD_SPI
3719+#define CONFIG_CMD_I2C
3720+#define CONFIG_CMD_IMXOTP
3721+
3722+/* Enable below configure when supporting nand */
3723+
3724+#define CONFIG_CMD_MMC
3725+#define CONFIG_MMC_8BIT_PORTS 0x00000002
3726+#define CONFIG_CMD_SF
3727+#define CONFIG_CMD_ENV
3728+#define CONFIG_CMD_REGUL
3729+
3730+#define CONFIG_CMD_CLOCK
3731+#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
3732+
3733+#ifdef CONFIG_QMX6_PN016104
3734+#define CONFIG_CMD_SATA
3735+#endif
3736+#undef CONFIG_CMD_IMLS
3737+
3738+#define CONFIG_BOOTDELAY 3
3739+
3740+#define CONFIG_PRIME "FEC0"
3741+
3742+#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
3743+#define CONFIG_RD_LOADADDR 0x11000000
3744+
3745+#define CONFIG_BOOTARGS "console=ttymxc1,115200 rdinit=/linuxrc rootwait root=/dev/ram0"
3746+#define CONFIG_BOOTCOMMAND "bootm 0x10800000 0x11000000"
3747+
3748+#define CONFIG_EXTRA_ENV_SETTINGS \
3749+ "netdev=eth0\0" \
3750+ "ethprime=FEC0\0" \
3751+ "uboot=u-boot.bin\0" \
3752+ "kernel=uImage\0" \
3753+
3754+
3755+#define CONFIG_ARP_TIMEOUT 200UL
3756+
3757+/*
3758+ * Miscellaneous configurable options
3759+ */
3760+#define CONFIG_SYS_LONGHELP /* undef to save memory */
3761+#define CONFIG_SYS_PROMPT "conga-QMX6-MFG U-Boot > "
3762+#define CONFIG_AUTO_COMPLETE
3763+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
3764+/* Print Buffer Size */
3765+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
3766+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
3767+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
3768+
3769+#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
3770+#define CONFIG_SYS_MEMTEST_END 0x10010000
3771+
3772+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
3773+
3774+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
3775+
3776+#define CONFIG_SYS_HZ 1000
3777+
3778+#define CONFIG_CMDLINE_EDITING
3779+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
3780+#ifdef CONFIG_SYS_HUSH_PARSER
3781+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
3782+#endif
3783+
3784+#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
3785+#define CONFIG_FEC0_PINMUX -1
3786+#define CONFIG_FEC0_MIIBASE -1
3787+#define CONFIG_GET_FEC_MAC_ADDR_FROM_ENV
3788+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
3789+#define CONFIG_MXC_FEC
3790+#define CONFIG_FEC0_PHY_ADDR 6
3791+#define CONFIG_ETH_PRIME
3792+#define CONFIG_RMII
3793+#define CONFIG_PHY_MICREL_KSZ9021
3794+#define CONFIG_CMD_MII
3795+#define CONFIG_CMD_DHCP
3796+#define CONFIG_CMD_PING
3797+#define CONFIG_IPADDR 192.168.1.103
3798+
3799+/*The IP ADDRESS of SERVERIP*/
3800+#define CONFIG_SERVERIP _SERVER_IP_ADDR_
3801+
3802+#define CONFIG_NETMASK 255.255.255.0
3803+
3804+/*
3805+ * OCOTP Configs
3806+ */
3807+#ifdef CONFIG_CMD_IMXOTP
3808+ #define CONFIG_IMX_OTP
3809+ #define IMX_OTP_BASE OCOTP_BASE_ADDR
3810+ #define IMX_OTP_ADDR_MAX 0x7F
3811+ #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
3812+#endif
3813+
3814+/*
3815+ * I2C Configs
3816+ */
3817+#ifdef CONFIG_CMD_I2C
3818+ #define CONFIG_HARD_I2C 1
3819+ #define CONFIG_I2C_MXC 1
3820+ #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
3821+ #define CONFIG_SYS_I2C_SPEED 100000
3822+ #define CONFIG_SYS_I2C_SLAVE 0x08
3823+#endif
3824+
3825+/*
3826+ * SPI Configs
3827+ */
3828+#ifdef CONFIG_CMD_SF
3829+ #define CONFIG_FSL_SF 1
3830+ #define CONFIG_SPI_FLASH_IMX_SST 1
3831+ #define CONFIG_SPI_FLASH_CS 1
3832+/* #define CONFIG_MFGAREA_UNPROTECT */
3833+ #define CONFIG_IMX_ECSPI
3834+ #define IMX_CSPI_VER_2_3 1
3835+ #define MAX_SPI_BYTES (64 * 4)
3836+#endif
3837+
3838+/* Regulator Configs */
3839+#ifdef CONFIG_CMD_REGUL
3840+ #define CONFIG_ANATOP_REGULATOR
3841+ #define CONFIG_CORE_REGULATOR_NAME "vdd1p1"
3842+ #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1"
3843+#endif
3844+
3845+/*
3846+ * MMC Configs
3847+ */
3848+#ifdef CONFIG_CMD_MMC
3849+ #define CONFIG_MMC
3850+ #define CONFIG_GENERIC_MMC
3851+ #define CONFIG_IMX_MMC
3852+ #define CONFIG_SYS_FSL_USDHC_NUM 3
3853+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
3854+ #define CONFIG_SYS_MMC_ENV_DEV 2
3855+ #define CONFIG_DOS_PARTITION 1
3856+ #define CONFIG_CMD_FAT 1
3857+ #define CONFIG_CMD_EXT2 1
3858+
3859+ /* detect whether SD1, 2, 3, or 4 is boot device */
3860+ #define CONFIG_DYNAMIC_MMC_DEVNO
3861+
3862+ /* Setup target delay in DDR mode for each SD port */
3863+ #define CONFIG_GET_DDR_TARGET_DELAY
3864+#endif
3865+
3866+/*
3867+ * SATA Configs
3868+ */
3869+#ifdef CONFIG_CMD_SATA
3870+ #define CONFIG_DWC_AHSATA
3871+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
3872+ #define CONFIG_DWC_AHSATA_PORT_ID 0
3873+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
3874+ #define CONFIG_LBA48
3875+ #define CONFIG_LIBATA
3876+
3877+ #define CONFIG_DOS_PARTITION 1
3878+ #define CONFIG_CMD_FAT 1
3879+ #define CONFIG_CMD_EXT2 1
3880+#endif
3881+
3882+/*
3883+ * USB OTG
3884+ */
3885+#define CONFIG_IMX_UDC 1
3886+
3887+/*-----------------------------------------------------------------------
3888+ * Stack sizes
3889+ *
3890+ * The stack sizes are set up in start.S using the settings below
3891+ */
3892+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
3893+
3894+/*-----------------------------------------------------------------------
3895+ * Physical Memory Map
3896+ */
3897+#define CONFIG_NR_DRAM_BANKS 1
3898+#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
3899+#ifdef CONFIG_QMX6_PN016104
3900+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
3901+#endif
3902+#ifdef CONFIG_QMX6_PN016101
3903+#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
3904+#endif
3905+#define iomem_valid_addr(addr, size) \
3906+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
3907+
3908+/*-----------------------------------------------------------------------
3909+ * FLASH and environment organization
3910+ */
3911+#define CONFIG_SYS_NO_FLASH
3912+
3913+/* Monitor at beginning of flash */
3914+/* #define CONFIG_FSL_ENV_IN_MMC */
3915+/* #define CONFIG_FSL_ENV_IN_SATA */
3916+/* #define CONFIG_FSL_ENV_IN_SF */
3917+
3918+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
3919+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
3920+#define CONFIG_ENV_IS_NOWHERE 1
3921+
3922+#endif /* __CONFIG_H */
3923diff --git a/localversion-qmx6 b/localversion-qmx6
3924new file mode 100644
3925index 0000000..5293f29
3926--- /dev/null
3927+++ b/localversion-qmx6
3928@@ -0,0 +1 @@
3929+ QMX6R003
3930--
39311.7.10.4
3932
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-01 09:48:45 +0000