diff options
Diffstat (limited to 'recipes-kernel/linux/linux-3.0.6/acp3448v2/0002-Patch-to-head_44x.S-to-support-lsi-acp3448v2.patch')
-rw-r--r-- | recipes-kernel/linux/linux-3.0.6/acp3448v2/0002-Patch-to-head_44x.S-to-support-lsi-acp3448v2.patch | 246 |
1 files changed, 246 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-3.0.6/acp3448v2/0002-Patch-to-head_44x.S-to-support-lsi-acp3448v2.patch b/recipes-kernel/linux/linux-3.0.6/acp3448v2/0002-Patch-to-head_44x.S-to-support-lsi-acp3448v2.patch new file mode 100644 index 0000000..2a9127c --- /dev/null +++ b/recipes-kernel/linux/linux-3.0.6/acp3448v2/0002-Patch-to-head_44x.S-to-support-lsi-acp3448v2.patch | |||
@@ -0,0 +1,246 @@ | |||
1 | From 159aad211bf918f2b582f8a12622bf02fb7dd64f Mon Sep 17 00:00:00 2001 | ||
2 | From: Jerry Pei <jerry.pei@enea.com> | ||
3 | Date: Mon, 23 Apr 2012 14:20:03 +0800 | ||
4 | Subject: [PATCH 2/7] Patch to head_44x.S to support lsi acp3448v2 | ||
5 | |||
6 | Signed-off-by: Jerry Pei <jerry.pei@enea.com> | ||
7 | --- | ||
8 | arch/powerpc/kernel/head_44x.S | 130 ++++++++++++++++++++++++++++++++++++--- | ||
9 | 1 files changed, 120 insertions(+), 10 deletions(-) | ||
10 | |||
11 | diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S | ||
12 | index 5e12b74..ac8d20e 100644 | ||
13 | --- a/arch/powerpc/kernel/head_44x.S | ||
14 | +++ b/arch/powerpc/kernel/head_44x.S | ||
15 | @@ -26,6 +26,8 @@ | ||
16 | * under the terms of the GNU General Public License as published by the | ||
17 | * Free Software Foundation; either version 2 of the License, or (at your | ||
18 | * option) any later version. | ||
19 | + * | ||
20 | + * These patches add ACP3400 support signed-off-by: john.jacques@lsi.com | ||
21 | */ | ||
22 | |||
23 | #include <linux/init.h> | ||
24 | @@ -41,6 +43,8 @@ | ||
25 | #include <asm/synch.h> | ||
26 | #include "head_booke.h" | ||
27 | |||
28 | +#undef TLBERRORCOUNTER | ||
29 | +/*#define TLBERRORCOUNTER*/ | ||
30 | |||
31 | /* As with the other PowerPC ports, it is expected that when code | ||
32 | * execution begins here, the following registers contain valid, yet | ||
33 | @@ -93,6 +97,30 @@ _ENTRY(_start); | ||
34 | |||
35 | bl early_init | ||
36 | |||
37 | +#ifdef CONFIG_RELOCATABLE | ||
38 | + /* | ||
39 | + * r25 will contain RPN/ERPN for the start address of memory | ||
40 | + * | ||
41 | + * Add the difference between KERNELBASE and PAGE_OFFSET to the | ||
42 | + * start of physical memory to get kernstart_addr. | ||
43 | + */ | ||
44 | + lis r3,kernstart_addr@ha | ||
45 | + la r3,kernstart_addr@l(r3) | ||
46 | + | ||
47 | + lis r4,KERNELBASE@h | ||
48 | + ori r4,r4,KERNELBASE@l | ||
49 | + lis r5,PAGE_OFFSET@h | ||
50 | + ori r5,r5,PAGE_OFFSET@l | ||
51 | + subf r4,r5,r4 | ||
52 | + | ||
53 | + rlwinm r6,r25,0,28,31 /* ERPN */ | ||
54 | + rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */ | ||
55 | + add r7,r7,r4 | ||
56 | + | ||
57 | + stw r6,0(r3) | ||
58 | + stw r7,4(r3) | ||
59 | +#endif | ||
60 | + | ||
61 | /* | ||
62 | * Decide what sort of machine this is and initialize the MMU. | ||
63 | */ | ||
64 | @@ -449,6 +477,15 @@ finish_tlb_load_44x: | ||
65 | mtspr SPRN_SPRG_WSCRATCH1,r11 | ||
66 | mtspr SPRN_SPRG_WSCRATCH2,r12 | ||
67 | mtspr SPRN_SPRG_WSCRATCH3,r13 | ||
68 | + /* ZZZ */ | ||
69 | +#ifdef TLBERRORCOUNTER | ||
70 | + lis r10,dtlb_misses@h | ||
71 | + ori r10,r10,dtlb_misses@l | ||
72 | + lwzu r11,0(r10) | ||
73 | + addi r11,r11,1 | ||
74 | + stwu r11,0(r10) | ||
75 | +#endif | ||
76 | + /* ZZZ */ | ||
77 | mfcr r11 | ||
78 | mtspr SPRN_SPRG_WSCRATCH4,r11 | ||
79 | mfspr r10,SPRN_DEAR /* Get faulting address */ | ||
80 | @@ -546,6 +583,15 @@ finish_tlb_load_44x: | ||
81 | mtspr SPRN_SPRG_WSCRATCH1,r11 | ||
82 | mtspr SPRN_SPRG_WSCRATCH2,r12 | ||
83 | mtspr SPRN_SPRG_WSCRATCH3,r13 | ||
84 | + /* ZZZ */ | ||
85 | +#ifdef TLBERRORCOUNTER | ||
86 | + lis r10,itlb_misses@h | ||
87 | + ori r10,r10,itlb_misses@l | ||
88 | + lwzu r11,0(r10) | ||
89 | + addi r11,r11,1 | ||
90 | + stwu r11,0(r10) | ||
91 | +#endif | ||
92 | + /* ZZZ */ | ||
93 | mfcr r11 | ||
94 | mtspr SPRN_SPRG_WSCRATCH4,r11 | ||
95 | mfspr r10,SPRN_SRR0 /* Get faulting address */ | ||
96 | @@ -704,6 +750,7 @@ _GLOBAL(set_context) | ||
97 | stw r4, 0x4(r5) | ||
98 | #endif | ||
99 | mtspr SPRN_PID,r3 | ||
100 | + PPC476_ERR_MTPID() | ||
101 | isync /* Force context change */ | ||
102 | blr | ||
103 | |||
104 | @@ -718,9 +765,12 @@ _GLOBAL(init_cpu_state) | ||
105 | /* We use the PVR to differenciate 44x cores from 476 */ | ||
106 | mfspr r3,SPRN_PVR | ||
107 | srwi r3,r3,16 | ||
108 | - cmplwi cr0,r3,PVR_476@h | ||
109 | + cmplwi cr0,r3,PVR_476X2@h /* some x2 had a non-standard PVR */ | ||
110 | beq head_start_47x | ||
111 | - cmplwi cr0,r3,PVR_476_ISS@h | ||
112 | + | ||
113 | + /* All other 476 cores have a 0x5 as the 4th nibble */ | ||
114 | + rlwinm r3,r3,0,28,31 | ||
115 | + cmplwi cr0,r3,PVR_476@h | ||
116 | beq head_start_47x | ||
117 | #endif /* CONFIG_PPC_47x */ | ||
118 | |||
119 | @@ -1001,9 +1051,6 @@ clear_utlb_entry: | ||
120 | lis r3,PAGE_OFFSET@h | ||
121 | ori r3,r3,PAGE_OFFSET@l | ||
122 | |||
123 | - /* Kernel is at the base of RAM */ | ||
124 | - li r4, 0 /* Load the kernel physical address */ | ||
125 | - | ||
126 | /* Load the kernel PID = 0 */ | ||
127 | li r0,0 | ||
128 | mtspr SPRN_PID,r0 | ||
129 | @@ -1013,9 +1060,8 @@ clear_utlb_entry: | ||
130 | clrrwi r3,r3,12 /* Mask off the effective page number */ | ||
131 | ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M | ||
132 | |||
133 | - /* Word 1 */ | ||
134 | - clrrwi r4,r4,12 /* Mask off the real page number */ | ||
135 | - /* ERPN is 0 for first 4GB page */ | ||
136 | + /* Word 1 - use r25. RPN is the same as the original entry */ | ||
137 | + | ||
138 | /* Word 2 */ | ||
139 | li r5,0 | ||
140 | ori r5,r5,PPC47x_TLB2_S_RWX | ||
141 | @@ -1026,7 +1072,7 @@ clear_utlb_entry: | ||
142 | /* We write to way 0 and bolted 0 */ | ||
143 | lis r0,0x8800 | ||
144 | tlbwe r3,r0,0 | ||
145 | - tlbwe r4,r0,1 | ||
146 | + tlbwe r25,r0,1 | ||
147 | tlbwe r5,r0,2 | ||
148 | |||
149 | /* | ||
150 | @@ -1057,6 +1103,7 @@ clear_utlb_entry: | ||
151 | tlbwe r24,r23,2 | ||
152 | isync /* Clear out the shadow TLB entries */ | ||
153 | |||
154 | +#ifndef CONFIG_ACP | ||
155 | #ifdef CONFIG_PPC_EARLY_DEBUG_44x | ||
156 | /* Add UART mapping for early debug. */ | ||
157 | |||
158 | @@ -1083,6 +1130,54 @@ clear_utlb_entry: | ||
159 | /* Force context change */ | ||
160 | isync | ||
161 | #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ | ||
162 | +#endif /* CONFIG_ACP */ | ||
163 | + | ||
164 | +#ifdef CONFIG_ACP | ||
165 | + /* Add bolted entries for I/O. */ | ||
166 | + | ||
167 | + /* Word 0 */ | ||
168 | + lis r3,(0xf0000000)@h | ||
169 | + ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_1M | ||
170 | + | ||
171 | + /* Word 1 */ | ||
172 | + lis r4,(0x00400000)@h | ||
173 | + ori r4,r4,0x20 | ||
174 | + | ||
175 | + /* Word 2 */ | ||
176 | + li r5,(PPC47x_TLB2_SW | PPC47x_TLB2_SR | PPC47x_TLB2_I | PPC47x_TLB2_G) | ||
177 | + | ||
178 | + /* Bolted in way 0, bolt slot 4, we -hope- we don't hit the same | ||
179 | + * congruence class as the kernel, we need to make sure of it at | ||
180 | + * some point | ||
181 | + */ | ||
182 | + lis r0,0x8d00 | ||
183 | + tlbwe r3,r0,0 | ||
184 | + tlbwe r4,r0,1 | ||
185 | + tlbwe r5,r0,2 | ||
186 | + | ||
187 | + /* Word 0 */ | ||
188 | + lis r3,(0xf0100000)@h | ||
189 | + ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_1M | ||
190 | + | ||
191 | + /* Word 1 */ | ||
192 | + lis r4,(0x00500000)@h | ||
193 | + ori r4,r4,0x20 | ||
194 | + | ||
195 | + /* Word 2 */ | ||
196 | + li r5,(PPC47x_TLB2_SW | PPC47x_TLB2_SR | PPC47x_TLB2_I | PPC47x_TLB2_G) | ||
197 | + | ||
198 | + /* Bolted in way 0, bolt slot 4, we -hope- we don't hit the same | ||
199 | + * congruence class as the kernel, we need to make sure of it at | ||
200 | + * some point | ||
201 | + */ | ||
202 | + lis r0,0x8c00 | ||
203 | + tlbwe r3,r0,0 | ||
204 | + tlbwe r4,r0,1 | ||
205 | + tlbwe r5,r0,2 | ||
206 | + | ||
207 | + /* Force context change */ | ||
208 | + isync | ||
209 | +#endif /* CONFIG_ACP */ | ||
210 | |||
211 | /* Establish the interrupt vector offsets */ | ||
212 | SET_IVOR(0, CriticalInput); | ||
213 | @@ -1111,6 +1206,15 @@ clear_utlb_entry: | ||
214 | mtspr SPRN_CCR0,r3 | ||
215 | isync | ||
216 | |||
217 | + /* XXX DD1.1 workaround, trap on dcbz & dcbf. We pre-configure | ||
218 | + * IOCR1 and 2 but we don't enable them in IOCCR, this will | ||
219 | + * be done on kernel entry/exit | ||
220 | + */ | ||
221 | + LOAD_REG_IMMEDIATE(r3, (31 << 26) | ( 86 << 1)) /* dcbf */ | ||
222 | + LOAD_REG_IMMEDIATE(r4, (31 << 26) | (1014 << 1)) /* dcbz */ | ||
223 | + mtspr SPRN_IOCR1, r3 | ||
224 | + mtspr SPRN_IOCR2, r4 | ||
225 | + | ||
226 | #endif /* CONFIG_PPC_47x */ | ||
227 | |||
228 | /* | ||
229 | @@ -1124,7 +1228,13 @@ head_start_common: | ||
230 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | ||
231 | mtspr SPRN_IVPR,r4 | ||
232 | |||
233 | - addis r22,r22,KERNELBASE@h | ||
234 | + /* | ||
235 | + * If the kernel was loaded at a non-zero 256 MB page, we need to | ||
236 | + * mask off the most significant 4 bits to get the relative address | ||
237 | + * from the start of physical memory | ||
238 | + */ | ||
239 | + rlwinm r22,r22,0,4,31 | ||
240 | + addis r22,r22,PAGE_OFFSET@h | ||
241 | mtlr r22 | ||
242 | isync | ||
243 | blr | ||
244 | -- | ||
245 | 1.7.0.4 | ||
246 | |||