1 files changed, 19 insertions, 0 deletions

diff --git a/recipes-kernel/linux/files/powerpc-fsl-booke64-Set-vmemmap_psize-to-4K.patch b/recipes-kernel/linux/files/powerpc-fsl-booke64-Set-vmemmap_psize-to-4K.patch
new file mode 100644
index 0000000..5acf97a
--- /dev/null
+++ b/recipes-kernel/linux/files/powerpc-fsl-booke64-Set-vmemmap_psize-to-4K.patch
@@ -0,0 +1,19 @@
+diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
+index ae3d5b7..92cb18d 100644
+--- a/arch/powerpc/mm/tlb_nohash.c
++++ b/arch/powerpc/mm/tlb_nohash.c
+@@ -596,8 +596,13 @@ static void __early_init_mmu(int boot_cpu)
+        /* XXX This should be decided at runtime based on supported
+         * page sizes in the TLB, but for now let's assume 16M is
+         * always there and a good fit (which it probably is)
++        *
++        * Freescale booke only supports 4K pages in TLB0, so use that.
+         */
+-       mmu_vmemmap_psize = MMU_PAGE_16M;
++       if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
++               mmu_vmemmap_psize = MMU_PAGE_4K;
++       else
++               mmu_vmemmap_psize = MMU_PAGE_16M;
+
+        /* XXX This code only checks for TLB 0 capabilities and doesn't
+         *     check what page size combos are supported by the HW. It