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-rw-r--r--recipes-kernel/linux/files/powerpc-fsl-booke64-Set-vmemmap_psize-to-4K.patch19
1 files changed, 0 insertions, 19 deletions
diff --git a/recipes-kernel/linux/files/powerpc-fsl-booke64-Set-vmemmap_psize-to-4K.patch b/recipes-kernel/linux/files/powerpc-fsl-booke64-Set-vmemmap_psize-to-4K.patch
deleted file mode 100644
index 5acf97a..0000000
--- a/recipes-kernel/linux/files/powerpc-fsl-booke64-Set-vmemmap_psize-to-4K.patch
+++ /dev/null
@@ -1,19 +0,0 @@
1diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
2index ae3d5b7..92cb18d 100644
3--- a/arch/powerpc/mm/tlb_nohash.c
4+++ b/arch/powerpc/mm/tlb_nohash.c
5@@ -596,8 +596,13 @@ static void __early_init_mmu(int boot_cpu)
6 /* XXX This should be decided at runtime based on supported
7 * page sizes in the TLB, but for now let's assume 16M is
8 * always there and a good fit (which it probably is)
9+ *
10+ * Freescale booke only supports 4K pages in TLB0, so use that.
11 */
12- mmu_vmemmap_psize = MMU_PAGE_16M;
13+ if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
14+ mmu_vmemmap_psize = MMU_PAGE_4K;
15+ else
16+ mmu_vmemmap_psize = MMU_PAGE_16M;
17
18 /* XXX This code only checks for TLB 0 capabilities and doesn't
19 * check what page size combos are supported by the HW. It