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-rw-r--r--recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch434
1 files changed, 0 insertions, 434 deletions
diff --git a/recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch b/recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch
deleted file mode 100644
index ecc37cc..0000000
--- a/recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch
+++ /dev/null
@@ -1,434 +0,0 @@
1From 448329ea097447aee73d050045295c5a0ae8519e Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Mon, 2 Mar 2015 01:51:05 +0000
4Subject: [PATCH 12/13] Add XLP instructions support
5
6From 26adb06ce515aadfec08ce13109b4b98287f677b Mon Sep 17 00:00:00 2001
7From: Nebu Philips <nphilips@netlogicmicro.com>
8Date: Fri, 30 Jul 2010 15:10:03 -0700
9Subject: [PATCH] Add support for Netlogic XLP
10
11Using the mipsisa64r2nlm target, add support for XLP from
12Netlogic. Also, update vendor name to NLM wherever applicable.
13---
14 bfd/aoutx.h | 1 +
15 bfd/archures.c | 1 +
16 bfd/bfd-in2.h | 1 +
17 bfd/config.bfd | 5 +++++
18 bfd/cpu-mips.c | 6 ++++--
19 bfd/elfxx-mips.c | 8 ++++++++
20 binutils/readelf.c | 1 +
21 gas/config/tc-mips.c | 4 +++-
22 gas/configure | 3 +++
23 gas/configure.tgt | 2 +-
24 include/elf/mips.h | 1 +
25 include/opcode/mips.h | 10 ++++++++--
26 ld/configure.tgt | 2 ++
27 opcodes/mips-dis.c | 12 +++++-------
28 opcodes/mips-opc.c | 33 +++++++++++++++++++++------------
29 15 files changed, 65 insertions(+), 25 deletions(-)
30
31Upstream-Status: Pending
32
33Signed-off-by: Khem Raj <raj.khem@gmail.com>
34
35Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been assigned
36to INSN_OCTEON3
37
38Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com>
39Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
40---
41 bfd/aoutx.h | 1 +
42 bfd/archures.c | 1 +
43 bfd/bfd-in2.h | 1 +
44 bfd/config.bfd | 5 +++++
45 bfd/cpu-mips.c | 6 ++++--
46 bfd/elfxx-mips.c | 8 ++++++++
47 binutils/readelf.c | 1 +
48 gas/config/tc-mips.c | 4 +++-
49 gas/configure | 3 +++
50 gas/configure.tgt | 2 +-
51 include/elf/mips.h | 1 +
52 include/opcode/mips.h | 10 ++++++++--
53 ld/configure.tgt | 2 ++
54 opcodes/mips-dis.c | 12 +++++-------
55 opcodes/mips-opc.c | 33 +++++++++++++++++++++------------
56 15 files changed, 65 insertions(+), 25 deletions(-)
57
58diff --git a/bfd/aoutx.h b/bfd/aoutx.h
59index 9385a98..a88df99 100644
60--- a/bfd/aoutx.h
61+++ b/bfd/aoutx.h
62@@ -802,6 +802,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
63 case bfd_mach_mipsisa64r6:
64 case bfd_mach_mips_sb1:
65 case bfd_mach_mips_xlr:
66+ case bfd_mach_mips_xlp:
67 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
68 arch_flags = M_MIPS2;
69 break;
70diff --git a/bfd/archures.c b/bfd/archures.c
71index c9fd6c8..547bd09 100644
72--- a/bfd/archures.c
73+++ b/bfd/archures.c
74@@ -180,6 +180,7 @@ DESCRIPTION
75 .#define bfd_mach_mips_octeonp 6601
76 .#define bfd_mach_mips_octeon2 6502
77 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
78+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
79 .#define bfd_mach_mipsisa32 32
80 .#define bfd_mach_mipsisa32r2 33
81 .#define bfd_mach_mipsisa32r3 34
82diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
83index c7a2bb5..413b773 100644
84--- a/bfd/bfd-in2.h
85+++ b/bfd/bfd-in2.h
86@@ -1967,6 +1967,7 @@ enum bfd_architecture
87 #define bfd_mach_mips_octeonp 6601
88 #define bfd_mach_mips_octeon2 6502
89 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
90+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
91 #define bfd_mach_mipsisa32 32
92 #define bfd_mach_mipsisa32r2 33
93 #define bfd_mach_mipsisa32r3 34
94diff --git a/bfd/config.bfd b/bfd/config.bfd
95index 03d2c6f..27086db 100644
96--- a/bfd/config.bfd
97+++ b/bfd/config.bfd
98@@ -1041,6 +1041,11 @@ case "${targ}" in
99 targ_defvec=mips_elf32_le_vec
100 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
101 ;;
102+ mipsisa64*-*-elf*)
103+ targ_defvec=mips_elf32_trad_be_vec
104+ targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
105+ want64=true
106+ ;;
107 mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss)
108 targ_defvec=mips_elf32_be_vec
109 targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
110diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
111index b617aaa..19a99d1 100644
112--- a/bfd/cpu-mips.c
113+++ b/bfd/cpu-mips.c
114@@ -103,7 +103,8 @@ enum
115 I_mipsocteonp,
116 I_mipsocteon2,
117 I_xlr,
118- I_micromips
119+ I_micromips,
120+ I_xlp
121 };
122
123 #define NN(index) (&arch_info_struct[(index) + 1])
124@@ -153,7 +154,8 @@ static const bfd_arch_info_type arch_info_struct[] =
125 N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
126 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
127 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
128- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
129+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
130+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
131 };
132
133 /* The default architecture is mips:3000, but with a machine number of
134diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
135index 0df7abf..d268e86 100644
136--- a/bfd/elfxx-mips.c
137+++ b/bfd/elfxx-mips.c
138@@ -6608,6 +6608,9 @@ _bfd_elf_mips_mach (flagword flags)
139 case E_MIPS_MACH_XLR:
140 return bfd_mach_mips_xlr;
141
142+ case E_MIPS_MACH_XLP:
143+ return bfd_mach_mips_xlp;
144+
145 default:
146 switch (flags & EF_MIPS_ARCH)
147 {
148@@ -11878,6 +11881,10 @@ mips_set_isa_flags (bfd *abfd)
149 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
150 break;
151
152+ case bfd_mach_mips_xlp:
153+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
154+ break;
155+
156 case bfd_mach_mipsisa32:
157 val = E_MIPS_ARCH_32;
158 break;
159@@ -14765,6 +14772,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
160 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
161 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
162 { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
163+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
164
165 /* MIPS64 extensions. */
166 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
167diff --git a/binutils/readelf.c b/binutils/readelf.c
168index 0c00b2f..6e9d5e4 100644
169--- a/binutils/readelf.c
170+++ b/binutils/readelf.c
171@@ -2898,6 +2898,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
172 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
173 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
174 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
175+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
176 case 0:
177 /* We simply ignore the field in this case to avoid confusion:
178 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
179diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
180index c3e3e2a..8d64344 100644
181--- a/gas/config/tc-mips.c
182+++ b/gas/config/tc-mips.c
183@@ -551,6 +551,7 @@ static int mips_32bitmode = 0;
184 || mips_opts.arch == CPU_RM7000 \
185 || mips_opts.arch == CPU_VR5500 \
186 || mips_opts.micromips \
187+ || mips_opts.arch == CPU_XLP \
188 )
189
190 /* Whether the processor uses hardware interlocks to protect reads
191@@ -580,6 +581,7 @@ static int mips_32bitmode = 0;
192 && mips_opts.isa != ISA_MIPS3) \
193 || mips_opts.arch == CPU_R4300 \
194 || mips_opts.micromips \
195+ || mips_opts.arch == CPU_XLP \
196 )
197
198 /* Whether the processor uses hardware interlocks to protect reads
199@@ -18682,7 +18684,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
200 /* Broadcom XLP.
201 XLP is mostly like XLR, with the prominent exception that it is
202 MIPS64R2 rather than MIPS64. */
203- { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
204+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
205
206 /* End marker */
207 { NULL, 0, 0, 0, 0 }
208diff --git a/gas/configure b/gas/configure
209index 074886f..8091f2f 100755
210--- a/gas/configure
211+++ b/gas/configure
212@@ -12808,6 +12808,9 @@ _ACEOF
213 mipsisa64r6 | mipsisa64r6el)
214 mips_cpu=mips64r6
215 ;;
216+ mipsisa64r2nlm | mipsisa64r2nlmel)
217+ mips_cpu=xlp
218+ ;;
219 mipstx39 | mipstx39el)
220 mips_cpu=r3900
221 ;;
222diff --git a/gas/configure.tgt b/gas/configure.tgt
223index 1d92f55..06e8b4f 100644
224--- a/gas/configure.tgt
225+++ b/gas/configure.tgt
226@@ -332,7 +332,7 @@ case ${generic_target} in
227 mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;;
228 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
229 fmt=elf em=tmips ;;
230- mips-*-elf* | mips-*-rtems*) fmt=elf ;;
231+ mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;;
232 mips-*-netbsd*) fmt=elf em=tmips ;;
233 mips-*-openbsd*) fmt=elf em=tmips ;;
234
235diff --git a/include/elf/mips.h b/include/elf/mips.h
236index 2ed6acd..e541f50 100644
237--- a/include/elf/mips.h
238+++ b/include/elf/mips.h
239@@ -285,6 +285,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
240 #define E_MIPS_MACH_SB1 0x008a0000
241 #define E_MIPS_MACH_OCTEON 0x008b0000
242 #define E_MIPS_MACH_XLR 0x008c0000
243+#define E_MIPS_MACH_XLP 0x008f0000
244 #define E_MIPS_MACH_OCTEON2 0x008d0000
245 #define E_MIPS_MACH_OCTEON3 0x008e0000
246 #define E_MIPS_MACH_5400 0x00910000
247diff --git a/include/opcode/mips.h b/include/opcode/mips.h
248index ef26167..ef53ec6 100644
249--- a/include/opcode/mips.h
250+++ b/include/opcode/mips.h
251@@ -1227,8 +1227,10 @@ static const unsigned int mips_isa_table[] = {
252 #define INSN_LOONGSON_2F 0x80000000
253 /* Loongson 3A. */
254 #define INSN_LOONGSON_3A 0x00000400
255-/* RMI Xlr instruction */
256-#define INSN_XLR 0x00000020
257+/* Netlogic Xlr instruction */
258+#define INSN_XLR 0x00000020
259+/* Netlogic XlP instruction */
260+#define INSN_XLP 0x00000080
261
262 /* DSP ASE */
263 #define ASE_DSP 0x00000001
264@@ -1324,6 +1326,7 @@ static const unsigned int mips_isa_table[] = {
265 #define CPU_OCTEONP 6601
266 #define CPU_OCTEON2 6502
267 #define CPU_XLR 887682 /* decimal 'XLR' */
268+#define CPU_XLP 887680 /* decimal 'XLP' */
269
270 /* Return true if the given CPU is included in INSN_* mask MASK. */
271
272@@ -1398,6 +1401,9 @@ cpu_is_member (int cpu, unsigned int mask)
273 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
274 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
275
276+ case CPU_XLP:
277+ return (mask & INSN_XLP) != 0;
278+
279 default:
280 return FALSE;
281 }
282diff --git a/ld/configure.tgt b/ld/configure.tgt
283index 740b2ea..4df13a7 100644
284--- a/ld/configure.tgt
285+++ b/ld/configure.tgt
286@@ -462,6 +462,8 @@ mips*el-sde-elf*) targ_emul=elf32ltsmip
287 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
288 targ_emul=elf32btsmip
289 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
290+mipsisa64*-*-elf*) targ_emul=elf32btsmip
291+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;;
292 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
293 targ_extra_emuls="elf32lr5900"
294 targ_extra_libpath=$targ_extra_emuls ;;
295diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
296index 1eb1d45..d6881af 100644
297--- a/opcodes/mips-dis.c
298+++ b/opcodes/mips-dis.c
299@@ -655,13 +655,11 @@ const struct mips_arch_choice mips_arch_choices[] =
300 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
301 mips_cp1_names_mips3264, mips_hwr_names_numeric },
302
303- /* XLP is mostly like XLR, with the prominent exception it is being
304- MIPS64R2. */
305- { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
306- ISA_MIPS64R2 | INSN_XLR, 0,
307- mips_cp0_names_xlr,
308- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
309- mips_cp1_names_mips3264, mips_hwr_names_numeric },
310+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
311+ ISA_MIPS64R2 | INSN_XLP, 0,
312+ mips_cp0_names_mips3264r2,
313+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
314+ mips_hwr_names_mips3264r2 },
315
316 /* This entry, mips16, is here only for ISA/processor selection; do
317 not print its name. */
318diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
319index 2c3bbad..9785a7e 100644
320--- a/opcodes/mips-opc.c
321+++ b/opcodes/mips-opc.c
322@@ -319,7 +319,8 @@ decode_mips_operand (const char *p)
323 #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
324 #define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
325 #define IOCT2 INSN_OCTEON2
326-#define XLR INSN_XLR
327+#define XLR INSN_XLR
328+#define XLP INSN_XLP
329 #define IVIRT ASE_VIRT
330 #define IVIRT64 ASE_VIRT64
331
332@@ -956,6 +957,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
333 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
334 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
335 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
336+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
337 /* ctc0 is at the bottom of the table. */
338 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
339 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
340@@ -988,12 +990,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
341 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
342 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
343 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
344-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
345+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
346 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
347 {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
348 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
349 {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
350 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
351+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
352 /* dctr and dctw are used on the r5000. */
353 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
354 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
355@@ -1065,6 +1068,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
356 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
357 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
358 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
359+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
360 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
361 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
362 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
363@@ -1080,6 +1084,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
364 /* dmfc3 is at the bottom of the table. */
365 /* dmtc3 is at the bottom of the table. */
366 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
367+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
368+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
369 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
370 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
371 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
372@@ -1229,9 +1235,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
373 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
374 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
375 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
376-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
377-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
378-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
379+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
380+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
381+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
382 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
383 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
384 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
385@@ -1396,7 +1402,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
386 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
387 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
388 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
389-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
390+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
391 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
392 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
393 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
394@@ -1441,10 +1447,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
395 /* move is at the top of the table. */
396 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
397 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
398+{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
399 {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 },
400 {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 },
401-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 },
402-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 },
403+{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
404+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
405+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
406+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
407 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
408 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
409 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
410@@ -1494,7 +1503,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
411 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
412 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
413 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
414-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
415+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
416 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
417 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
418 {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
419@@ -1924,9 +1933,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
420 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
421 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
422 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
423-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
424-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
425-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
426+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
427+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
428+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
429 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
430 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
431 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
432--
4332.1.4
434
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-03 19:42:59 +0000