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From e2d575410329f42542972b7276fbb1c2c7f48334 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Sixten=20Sj=C3=B6str=C3=B6m=20Thames?=
<Sixten.Sjoestroem.Thames@enea.com>
Date: Mon, 12 May 2014 21:18:47 +0200
Subject: [PATCH] arm_arch_timer: Keystone 2 architected timer frequency fix
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The arch timer frequency register returns incorrect values on early
versions of the Keystone 2 evm silicon. The frequency register always
returns 1000 MHz on bad silicon. This temporary fix solves that.
Signed-off-by: Sixten Sjöström Thames <Sixten.Sjoestroem.Thames@enea.com>
---
drivers/clocksource/arm_arch_timer.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index a2b2541..321aba1 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -23,6 +23,8 @@
#include <clocksource/arm_arch_timer.h>
+#define K2_PG1_AT_FREQ 133120000UL
+
static u32 arch_timer_rate;
enum ppi_nr {
@@ -165,6 +167,20 @@ static int arch_timer_available(void)
if (arch_timer_rate == 0) {
freq = arch_timer_get_cntfrq();
+ /* The Keystone 2 EVM PG1.0 silicon has a malfunctional
+ * Architected timer. The timer frequency register allways
+ * incorrectly returns 1000 MHz. This is a temorary fix for
+ * internal Enea Linux testing so that the same kernel can
+ * be used on targets with both PG1.0 and PG1.1 silicon.
+ * Another solution is to have different DTBs with hard
+ * coded frequencies.*/
+ if (freq == 1000000000) {
+ pr_warn("Keystone 2 EVM specific arch timer fix\n");
+ pr_warn("Set architected timer frequency to %u\n",
+ K2_PG1_AT_FREQ);
+ freq = K2_PG1_AT_FREQ;
+ }
+
/* Check the timer frequency. */
if (freq == 0) {
pr_warn("Architected timer frequency not available\n");
--
1.7.10.4
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