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Diffstat (limited to 'recipes-kernel/linux/linux-proliant-m400/proliant-m400.dts')
-rw-r--r--recipes-kernel/linux/linux-proliant-m400/proliant-m400.dts775
1 files changed, 0 insertions, 775 deletions
diff --git a/recipes-kernel/linux/linux-proliant-m400/proliant-m400.dts b/recipes-kernel/linux/linux-proliant-m400/proliant-m400.dts
deleted file mode 100644
index efc8157..0000000
--- a/recipes-kernel/linux/linux-proliant-m400/proliant-m400.dts
+++ /dev/null
@@ -1,775 +0,0 @@
1/dts-v1/;
2
3/ {
4 #size-cells = <0x2>;
5 #address-cells = <0x2>;
6 interrupt-parent = <0x1>;
7 compatible = "apm,mustang", "apm,xgene-storm";
8 model = "HP ProLiant m400 Server Cartridge";
9 copyright = "Hewlett-Packard Development Company, L.P.";
10 serial-number = "CN7416V02J";
11
12 memory {
13 reg = <0x40 0x0 0x8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
14 device_type = "memory";
15 };
16
17 chosen {
18 bootargs = "console=ttyS0,115200n8 ro";
19 linux,initrd-start = <0x47 0xeef28000>;
20 linux,initrd-end = <0x47 0xeffffaf6>;
21 };
22
23 soc {
24 ranges;
25 #size-cells = <0x2>;
26 #address-cells = <0x2>;
27 compatible = "simple-bus";
28
29 crypto@1f250000 {
30 interrupts = <0x0 0x85 0x4>;
31 slave_info = <0x1 0x0 0x2 0x20 0x8>;
32 slave_name = "SEC";
33 clocks = <0x10 0x0>;
34 #clock-cells = <0x1>;
35 reg = <0x0 0x1f250000 0x0 0x10000>;
36 compatible = "apm,xgene-crypto";
37 device_type = "crypto";
38 };
39
40 gpio_keys_polled {
41 autorepeat;
42 poll-interval = <0x64>;
43 #size-cells = <0x0>;
44 #address-cells = <0x1>;
45 compatible = "gpio-keys-polled";
46
47 button@1 {
48 gpios = <0x18 0x17 0x1>;
49 linux,input-type = <0x1>;
50 linux,code = <0x74>;
51 label = "Power button";
52 };
53 };
54
55 gpio_poweroff {
56 gpios = <0x18 0x18 0x0>;
57 compatible = "gpio-poweroff";
58 };
59
60 dwgpio@1c024000 {
61 reg-io-width = <0x4>;
62 #size-cells = <0x0>;
63 #address-cells = <0x1>;
64 reg = <0x0 0x1c024000 0x0 0x1000>;
65 compatible = "snps,dw-apb-gpio";
66
67 gpio-controller@0 {
68 phandle = <0x18>;
69 linux,phandle = <0x18>;
70 reg = <0x0>;
71 snps,nr-gpios = <0x20>;
72 #gpio-cells = <0x2>;
73 gpio-controller;
74 compatible = "snps,dw-apb-gpio-port";
75 };
76 };
77
78 ethernet@17020000 {
79 phy-mode = "rgmii";
80 phyid = <0x3>;
81 max-frame-size = <0x233a>;
82 local-mac-address = <0x0 0x11 0x3a 0x8a 0x5a 0x78>;
83 clocks = <0x17 0x0>;
84 #clock-cells = <0x1>;
85 interrupts = <0x0 0x38 0x4 0x0 0x39 0x4 0x0 0x3a 0x4>;
86 slave-name = "RGMII";
87 reg = <0x0 0x17020000 0x0 0x30 0x0 0x17020000 0x0 0x10000 0x0 0x17020000 0x0 0x20>;
88 status = "na";
89 compatible = "apm,xgene-enet";
90 };
91
92 qmtm@17030000 {
93 clocks = <0x16 0x0>;
94 #clock-cells = <0x1>;
95 status = "ok";
96 interrupts = <0x0 0x40 0x4 0x0 0x3c 0x4>;
97 slave-name = "CPU_QMTM3";
98 reg = <0x0 0x17030000 0x0 0x10000 0x0 0x10000000 0x0 0x400000>;
99 compatible = "apm,xgene-qmtm-lite";
100 };
101
102 sata@1a800000 {
103 phy-names = "sata-phy";
104 phys = <0x15 0x0>;
105 clocks = <0x14 0x0>;
106 status = "ok";
107 interrupts = <0x0 0x88 0x4>;
108 reg = <0x0 0x1a800000 0x0 0x1000 0x0 0x1f230000 0x0 0x1000 0x0 0x1f23d000 0x0 0x1000 0x0 0x1f23e000 0x0 0x1000 0x0 0x1c000200 0x0 0x100>;
109 compatible = "apm,xgene-ahci";
110 };
111
112 sata@1a400000 {
113 phy-names = "sata-phy";
114 phys = <0x13 0x0>;
115 clocks = <0x12 0x0>;
116 status = "disabled";
117 interrupts = <0x0 0x87 0x4>;
118 reg = <0x0 0x1a400000 0x0 0x1000 0x0 0x1f220000 0x0 0x1000 0x0 0x1f22d000 0x0 0x1000 0x0 0x1f22e000 0x0 0x1000 0x0 0x1c000200 0x0 0x100 0x0 0x1f227000 0x0 0x1000>;
119 compatible = "apm,xgene-ahci";
120 };
121
122 sata@1a000000 {
123 phy-names = "sata-phy";
124 phys = <0x11 0x0>;
125 clocks = <0x10 0x0>;
126 status = "disabled";
127 interrupts = <0x0 0x86 0x4>;
128 reg = <0x0 0x1a000000 0x0 0x1000 0x0 0x1f210000 0x0 0x1000 0x0 0x1f21d000 0x0 0x1000 0x0 0x1f21e000 0x0 0x1000 0x0 0x1f217000 0x0 0x1000>;
129 compatible = "apm,xgene-ahci";
130 };
131
132 phy@1f23a000 {
133 phandle = <0x15>;
134 linux,phandle = <0x15>;
135 apm,tx-amplitude-A3 = <0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0>;
136 apm,tx-post-cursor-A3 = <0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0>;
137 apm,tx-pre-cursor2-A3 = <0x0 0x0 0x0 0x0 0x0 0x0>;
138 apm,tx-pre-cursor1-A3 = <0x8e30 0x8e30 0x8e30 0x8e30 0x8e30 0x8e30>;
139 apm,tx-equalizer-A3 = <0x1 0x1 0x1 0x1 0x1 0x1>;
140 apm,tx-eye-tuning-A3 = <0x1 0xa 0xa 0x2 0xa 0xa>;
141 apm,tx-boost-gain-A3 = <0x1e 0x1e 0x1e 0x1e 0x1e 0x1e>;
142 apm,tx-boost-gain-ssd-A3 = <0x2 0x2 0x2 0x2 0x2 0x2>;
143 status = "ok";
144 clocks = <0xf 0x0>;
145 #phy-cells = <0x1>;
146 reg = <0x0 0x1f23a000 0x0 0x100>;
147 compatible = "apm,xgene-phy";
148 };
149
150 phy@1f22a000 {
151 phandle = <0x13>;
152 linux,phandle = <0x13>;
153 apm,tx-amplitude-A3 = <0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0>;
154 apm,tx-post-cursor-A3 = <0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0>;
155 apm,tx-pre-cursor2-A3 = <0x0 0x0 0x0 0x0 0x0 0x0>;
156 apm,tx-pre-cursor1-A3 = <0x8e30 0x8e30 0x8e30 0x8e30 0x8e30 0x8e30>;
157 apm,tx-equalizer-A3 = <0x1 0x1 0x1 0x1 0x1 0x1>;
158 apm,tx-eye-tuning-A3 = <0x1 0xa 0xa 0x2 0xa 0xa>;
159 apm,tx-boost-gain-A3 = <0x1e 0x1e 0x1e 0x1e 0x1e 0x1e>;
160 apm,tx-boost-gain-ssd-A3 = <0x2 0x2 0x2 0x2 0x2 0x2>;
161 status = "disabled";
162 clocks = <0xe 0x0>;
163 #phy-cells = <0x1>;
164 reg = <0x0 0x1f22a000 0x0 0x100>;
165 compatible = "apm,xgene-phy";
166 };
167
168 phy@1f21a000 {
169 phandle = <0x11>;
170 linux,phandle = <0x11>;
171 apm,tx-amplitude-A3 = <0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0 0x19fa0>;
172 apm,tx-post-cursor-A3 = <0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0 0x2c6f0>;
173 apm,tx-pre-cursor2-A3 = <0x0 0x0 0x0 0x0 0x0 0x0>;
174 apm,tx-pre-cursor1-A3 = <0x8e30 0x8e30 0x8e30 0x8e30 0x8e30 0x8e30>;
175 apm,tx-equalizer-A3 = <0x1 0x1 0x1 0x1 0x1 0x1>;
176 apm,tx-eye-tuning-A3 = <0xa 0xa 0xa 0xa 0xa 0xa>;
177 apm,tx-boost-gain-A3 = <0x1e 0x1e 0x1e 0x1e 0x1e 0x1e>;
178 apm,tx-boost-gain-ssd-A3 = <0x2 0x2 0x2 0x2 0x2 0x2>;
179 status = "disabled";
180 clocks = <0xd 0x0>;
181 #phy-cells = <0x1>;
182 reg = <0x0 0x1f21a000 0x0 0x100>;
183 compatible = "apm,xgene-phy";
184 };
185
186 reboot@17000014 {
187 mask = <0x1>;
188 offset = <0x14>;
189 regmap = <0xc>;
190 compatible = "syscon-reboot";
191 };
192
193 slimpro@10540000 {
194 interrupts = <0x0 0x0 0x4 0x0 0x1 0x4 0x0 0x2 0x4 0x0 0x3 0x4 0x0 0x4 0x4 0x0 0x5 0x4 0x0 0x6 0x4 0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4>;
195 reg = <0x0 0x10540000 0x0 0xa000>;
196 compatible = "apm,xgene-slimpro-mbox";
197 };
198
199 serial@1c021000 {
200 status = "ok";
201 interrupts = <0x0 0x4d 0x4>;
202 interrupt-parent = <0x1>;
203 clock-frequency = <0x2faf080>;
204 reg-shift = <0x2>;
205 reg = <0x0 0x1c021000 0x0 0x1000>;
206 hw-flow-control;
207 auto-flow-control;
208 fifo-size = <0x10>;
209 compatible = "snps,dw-apb-uart", "ns16550a";
210 device_type = "serial";
211 };
212
213 serial@1c020000 {
214 status = "disabled";
215 interrupts = <0x0 0x4c 0x4>;
216 interrupt-parent = <0x1>;
217 clock-frequency = <0x2faf080>;
218 reg-shift = <0x2>;
219 reg = <0x0 0x1c020000 0x0 0x1000>;
220 auto-flow-control;
221 fifo-size = <0x10>;
222 compatible = "snps,dw-apb-uart", "ns16550a";
223 device_type = "serial";
224 };
225
226 rtc@10510000 {
227 clocks = <0xb 0x0>;
228 #clock-cells = <0x1>;
229 interrupts = <0x0 0x46 0x4>;
230 reg = <0x0 0x10510000 0x0 0x400>;
231 compatible = "apm,xgene-rtc";
232 device_type = "rtc";
233 };
234
235 pcie@1f510000 {
236 clocks = <0xa 0x0>;
237 interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xda 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xdb 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xdc 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xdd 0x1>;
238 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
239 interrupts = <0x0 0x10 0x4>;
240 ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
241 ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
242 dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
243 ranges = <0x1000000 0x0 0x0 0xc0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xc0 0x10000000 0x0 0x80000000>;
244 reg-names = "csr", "cfg";
245 reg = <0x0 0x1f510000 0x0 0x10000 0xc0 0xd0000000 0x0 0x200000>;
246 serdes-diff-clk = <0x0>;
247 link_speed = <0x2>;
248 link_width = <0x4>;
249 port = <0x4>;
250 #address-cells = <0x3>;
251 #size-cells = <0x2>;
252 #interrupt-cells = <0x1>;
253 compatible = "apm,xgene-pcie";
254 device_type = "pci";
255 status = "na";
256 };
257
258 pcie@1f500000 {
259 clocks = <0x9 0x0>;
260 interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xd4 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xd5 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xd6 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xd7 0x1>;
261 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
262 interrupts = <0x0 0x10 0x4>;
263 ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
264 ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
265 dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
266 ranges = <0x1000000 0x0 0x0 0xa0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xa0 0x10000000 0x0 0x80000000>;
267 reg-names = "csr", "cfg";
268 reg = <0x0 0x1f500000 0x0 0x10000 0xa0 0xd0000000 0x0 0x200000>;
269 serdes-diff-clk = <0x0>;
270 link_speed = <0x2>;
271 link_width = <0x8>;
272 port = <0x3>;
273 #address-cells = <0x3>;
274 #size-cells = <0x2>;
275 #interrupt-cells = <0x1>;
276 compatible = "apm,xgene-pcie";
277 device_type = "pci";
278 status = "ok";
279 reset_gpio = <0xffffffff>;
280 };
281
282 pcie@1f2d0000 {
283 clocks = <0x8 0x0>;
284 interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xce 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xcf 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xd0 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xd1 0x1>;
285 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
286 interrupts = <0x0 0x10 0x4>;
287 ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
288 ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
289 dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
290 ranges = <0x1000000 0x0 0x0 0x90 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0x90 0x10000000 0x0 0x80000000>;
291 reg-names = "csr", "cfg";
292 reg = <0x0 0x1f2d0000 0x0 0x10000 0x90 0xd0000000 0x0 0x200000>;
293 serdes-diff-clk = <0x0>;
294 link_speed = <0x2>;
295 link_width = <0x1>;
296 port = <0x2>;
297 #address-cells = <0x3>;
298 #size-cells = <0x2>;
299 #interrupt-cells = <0x1>;
300 compatible = "apm,xgene-pcie";
301 device_type = "pci";
302 status = "na";
303 };
304
305 pcie@1f2c0000 {
306 clocks = <0x7 0x0>;
307 interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xc8 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xc9 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xca 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xcb 0x1>;
308 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
309 interrupts = <0x0 0x10 0x4>;
310 ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
311 ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
312 dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
313 ranges = <0x1000000 0x0 0x0 0xd0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xd0 0x10000000 0x0 0x80000000>;
314 reg-names = "csr", "cfg";
315 reg = <0x0 0x1f2c0000 0x0 0x10000 0xd0 0xd0000000 0x0 0x200000>;
316 serdes-diff-clk = <0x0>;
317 link_speed = <0x3>;
318 link_width = <0x4>;
319 port = <0x1>;
320 #address-cells = <0x3>;
321 #size-cells = <0x2>;
322 #interrupt-cells = <0x1>;
323 compatible = "apm,xgene-pcie";
324 device_type = "pci";
325 status = "na";
326 };
327
328 pcie@1f2b0000 {
329 clocks = <0x6 0x0>;
330 interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0xc2 0x1 0x0 0x0 0x0 0x2 0x1 0x0 0xc3 0x1 0x0 0x0 0x0 0x3 0x1 0x0 0xc4 0x1 0x0 0x0 0x0 0x4 0x1 0x0 0xc5 0x1>;
331 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
332 interrupts = <0x0 0x10 0x4>;
333 ib-ranges-ep = <0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x0 0x0 0x0 0x0 0x400000 0x2000000 0x0 0x79000000 0x0 0x79000000 0x0 0x100000>;
334 ib-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
335 dma-ranges = <0x42000000 0x40 0x0 0x40 0x0 0x40 0x0 0x0 0x0 0x79000000 0x0 0x79000000 0x0 0x800000>;
336 ranges = <0x1000000 0x0 0x0 0xe0 0x0 0x0 0x10000 0x2000000 0x0 0x10000000 0xe0 0x10000000 0x0 0x80000000>;
337 reg-names = "csr", "cfg";
338 reg = <0x0 0x1f2b0000 0x0 0x10000 0xe0 0xd0000000 0x0 0x200000>;
339 serdes-diff-clk = <0x0>;
340 link_speed = <0x3>;
341 link_width = <0x4>;
342 reset_gpio = <0x19>;
343 port = <0x0>;
344 #address-cells = <0x3>;
345 #size-cells = <0x2>;
346 #interrupt-cells = <0x1>;
347 compatible = "apm,xgene-pcie";
348 device_type = "pci";
349 status = "na";
350 };
351
352 msi@79000000 {
353 interrupts = <0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x12 0x4 0x0 0x13 0x4 0x0 0x14 0x4 0x0 0x15 0x4 0x0 0x16 0x4 0x0 0x17 0x4 0x0 0x18 0x4 0x0 0x19 0x4 0x0 0x1a 0x4 0x0 0x1b 0x4 0x0 0x1c 0x4 0x0 0x1d 0x4 0x0 0x1e 0x4 0x0 0x1f 0x4>;
354 msi-available-ranges = <0x0 0x1000>;
355 reg = <0x0 0x79000000 0x0 0x900000>;
356 compatible = "xgene,gic-msi";
357 };
358
359 clocks {
360 ranges;
361 #size-cells = <0x2>;
362 #address-cells = <0x2>;
363
364 gpioclk@1f2ac000 {
365 phandle = <0x27>;
366 linux,phandle = <0x27>;
367 clock-output-names = "gpioclk";
368 enable-mask = <0x4>;
369 enable-offset = <0x8>;
370 csr-mask = <0x4>;
371 csr-offset = <0x0>;
372 reg-names = "csr-reg";
373 reg = <0x0 0x1f2ac000 0x0 0x1000>;
374 clock-names = "ahbclk";
375 clocks = <0x6 0x0>;
376 #clock-cells = <0x1>;
377 compatible = "apm,xgene-device-clock";
378 };
379
380 pcie4clk@1f51c000 {
381 phandle = <0xa>;
382 linux,phandle = <0xa>;
383 clock-output-names = "pcie4clk";
384 reg-names = "csr-reg";
385 reg = <0x0 0x1f51c000 0x0 0x1000>;
386 clocks = <0x4 0x0>;
387 #clock-cells = <0x1>;
388 compatible = "apm,xgene-device-clock";
389 status = "disabled";
390 };
391
392 pcie3clk@1f50c000 {
393 phandle = <0x9>;
394 linux,phandle = <0x9>;
395 clock-output-names = "pcie3clk";
396 reg-names = "csr-reg";
397 reg = <0x0 0x1f50c000 0x0 0x1000>;
398 clocks = <0x4 0x0>;
399 #clock-cells = <0x1>;
400 compatible = "apm,xgene-device-clock";
401 status = "ok";
402 };
403
404 pcie2clk@1f2dc000 {
405 phandle = <0x8>;
406 linux,phandle = <0x8>;
407 clock-output-names = "pcie2clk";
408 reg-names = "csr-reg";
409 reg = <0x0 0x1f2dc000 0x0 0x1000>;
410 clocks = <0x4 0x0>;
411 #clock-cells = <0x1>;
412 compatible = "apm,xgene-device-clock";
413 status = "disabled";
414 };
415
416 pcie1clk@1f2cc000 {
417 phandle = <0x7>;
418 linux,phandle = <0x7>;
419 clock-output-names = "pcie1clk";
420 reg-names = "csr-reg";
421 reg = <0x0 0x1f2cc000 0x0 0x1000>;
422 clocks = <0x4 0x0>;
423 #clock-cells = <0x1>;
424 compatible = "apm,xgene-device-clock";
425 status = "ok";
426 };
427
428 pcie0clk@1f2bc000 {
429 phandle = <0x6>;
430 linux,phandle = <0x6>;
431 clock-output-names = "pcie0clk";
432 reg-names = "csr-reg";
433 reg = <0x0 0x1f2bc000 0x0 0x1000>;
434 clocks = <0x4 0x0>;
435 #clock-cells = <0x1>;
436 compatible = "apm,xgene-device-clock";
437 status = "ok";
438 };
439
440 rtcclk@17000000 {
441 phandle = <0xb>;
442 linux,phandle = <0xb>;
443 clock-output-names = "rtcclk";
444 enable-mask = <0x2>;
445 enable-offset = <0x10>;
446 csr-mask = <0x2>;
447 csr-offset = <0xc>;
448 reg-names = "csr-reg";
449 reg = <0x0 0x17000000 0x0 0x2000>;
450 clock-names = "socplldiv2";
451 clocks = <0x4 0x0>;
452 #clock-cells = <0x1>;
453 compatible = "apm,xgene-device-clock";
454 };
455
456 sata45clk@1f23c000 {
457 phandle = <0x14>;
458 linux,phandle = <0x14>;
459 enable-mask = <0x39>;
460 enable-offset = <0x0>;
461 csr-mask = <0x5>;
462 csr-offset = <0x4>;
463 clock-output-names = "sata45clk";
464 reg-names = "csr-reg";
465 reg = <0x0 0x1f23c000 0x0 0x1000>;
466 clocks = <0x4 0x0>;
467 #clock-cells = <0x1>;
468 compatible = "apm,xgene-device-clock";
469 };
470
471 sata23clk@1f22c000 {
472 phandle = <0x12>;
473 linux,phandle = <0x12>;
474 enable-mask = <0x39>;
475 enable-offset = <0x0>;
476 csr-mask = <0x5>;
477 csr-offset = <0x4>;
478 clock-output-names = "sata23clk";
479 reg-names = "csr-reg";
480 reg = <0x0 0x1f22c000 0x0 0x1000>;
481 clocks = <0x4 0x0>;
482 #clock-cells = <0x1>;
483 compatible = "apm,xgene-device-clock";
484 };
485
486 sata01clk@1f21c000 {
487 phandle = <0x10>;
488 linux,phandle = <0x10>;
489 enable-mask = <0x39>;
490 enable-offset = <0x0>;
491 csr-mask = <0x5>;
492 csr-offset = <0x4>;
493 clock-output-names = "sata01clk";
494 reg-names = "csr-reg";
495 reg = <0x0 0x1f21c000 0x0 0x1000>;
496 clocks = <0x4 0x0>;
497 #clock-cells = <0x1>;
498 compatible = "apm,xgene-device-clock";
499 };
500
501 sataphy1clk@1f23c000 {
502 phandle = <0xf>;
503 linux,phandle = <0xf>;
504 enable-mask = <0x6>;
505 enable-offset = <0x0>;
506 csr-mask = <0x3a>;
507 csr-offset = <0x4>;
508 status = "ok";
509 clock-output-names = "sataphy3clk";
510 reg-names = "csr-reg";
511 reg = <0x0 0x1f23c000 0x0 0x1000>;
512 clocks = <0x4 0x0>;
513 #clock-cells = <0x1>;
514 compatible = "apm,xgene-device-clock";
515 };
516
517 sataphy1clk@1f22c000 {
518 phandle = <0xe>;
519 linux,phandle = <0xe>;
520 enable-mask = <0x6>;
521 enable-offset = <0x0>;
522 csr-mask = <0x3a>;
523 csr-offset = <0x4>;
524 status = "ok";
525 clock-output-names = "sataphy2clk";
526 reg-names = "csr-reg";
527 reg = <0x0 0x1f22c000 0x0 0x1000>;
528 clocks = <0x4 0x0>;
529 #clock-cells = <0x1>;
530 compatible = "apm,xgene-device-clock";
531 };
532
533 sataphy1clk@1f21c000 {
534 phandle = <0xd>;
535 linux,phandle = <0xd>;
536 enable-mask = <0x6>;
537 enable-offset = <0x0>;
538 csr-mask = <0x0>;
539 csr-offset = <0x4>;
540 status = "disabled";
541 clock-output-names = "sataphy1clk";
542 reg-names = "csr-reg";
543 reg = <0x0 0x1f21c000 0x0 0x1000>;
544 clocks = <0x4 0x0>;
545 #clock-cells = <0x1>;
546 compatible = "apm,xgene-device-clock";
547 };
548
549 eth8clk {
550 phandle = <0x17>;
551 linux,phandle = <0x17>;
552 clock-output-names = "eth8clk";
553 reg-names = "csr-reg";
554 reg = <0x0 0x1702c000 0x0 0x1000>;
555 clock-names = "eth8clk";
556 clocks = <0x5 0x0>;
557 #clock-cells = <0x1>;
558 compatible = "apm,xgene-device-clock";
559 };
560
561 ethclk {
562 phandle = <0x5>;
563 linux,phandle = <0x5>;
564 clock-output-names = "ethclk";
565 divider-shift = <0x0>;
566 divider-width = <0x9>;
567 divider-offset = <0x238>;
568 reg-names = "div-reg";
569 reg = <0x0 0x17000000 0x0 0x1000>;
570 clock-names = "ethclk";
571 clocks = <0x4 0x0>;
572 #clock-cells = <0x1>;
573 compatible = "apm,xgene-device-clock";
574 };
575
576 qmlclk {
577 phandle = <0x16>;
578 linux,phandle = <0x16>;
579 enable-mask = <0x3>;
580 enable-offset = <0x8>;
581 csr-mask = <0x3>;
582 csr-offset = <0x0>;
583 status = "ok";
584 clock-output-names = "qmlclk";
585 reg-names = "csr-reg";
586 reg = <0x0 0x1703c000 0x0 0x1000>;
587 clock-names = "socplldiv2";
588 clocks = <0x4 0x0>;
589 #clock-cells = <0x1>;
590 compatible = "apm,xgene-device-clock";
591 };
592
593 socplldiv2 {
594 phandle = <0x4>;
595 linux,phandle = <0x4>;
596 clock-output-names = "socpll";
597 clock-div = <0x2>;
598 clock-mult = <0x1>;
599 clock-names = "socplldiv2";
600 clocks = <0x3 0x0>;
601 #clock-cells = <0x1>;
602 compatible = "fixed-factor-clock";
603 };
604
605 socpll@17000120 {
606 phandle = <0x3>;
607 linux,phandle = <0x3>;
608 type = <0x1>;
609 clock-output-names = "socpll";
610 reg = <0x0 0x17000120 0x0 0x1000>;
611 clock-names = "refclk";
612 clocks = <0x2 0x0>;
613 #clock-cells = <0x1>;
614 compatible = "apm,xgene-socpll-clock";
615 };
616
617 pcppll@17000100 {
618 type = <0x0>;
619 clock-output-names = "pcppll";
620 reg = <0x0 0x17000100 0x0 0x1000>;
621 clock-names = "refclk";
622 clocks = <0x2 0x0>;
623 #clock-cells = <0x1>;
624 compatible = "apm,xgene-pcppll-clock";
625 };
626
627 refclk {
628 phandle = <0x2>;
629 linux,phandle = <0x2>;
630 clock-output-names = "refclk";
631 clock-frequency = <0x5f5e100>;
632 #clock-cells = <0x1>;
633 compatible = "fixed-clock";
634 };
635 };
636
637 system-clk-controller@17000000 {
638 phandle = <0xc>;
639 linux,phandle = <0xc>;
640 reg = <0x0 0x17000000 0x0 0x400>;
641 compatible = "apm,xgene-scu", "syscon";
642 };
643 };
644
645 timer {
646 clock-frequency = <0x2faf080>;
647 interrupts = <0x1 0x0 0xff04 0x1 0xd 0xff04 0x1 0xe 0xff04 0x1 0xf 0xff04>;
648 compatible = "arm,armv8-timer";
649 };
650
651 pmu {
652 interrupts = <0x1 0xc 0xff04>;
653 compatible = "arm,armv8-pmuv3";
654 };
655
656 interrupt-controller@78010000 {
657 phandle = <0x1>;
658 linux,phandle = <0x1>;
659 interrupts = <0x1 0x9 0xf04>;
660 reg = <0x0 0x78010000 0x0 0x1000 0x0 0x78020000 0x0 0x1000 0x0 0x78040000 0x0 0x2000 0x0 0x78060000 0x0 0x2000>;
661 interrupt-controller;
662 #interrupt-cells = <0x3>;
663 compatible = "arm,cortex-a15-gic";
664 };
665
666 cpus {
667 #size-cells = <0x0>;
668 #address-cells = <0x2>;
669
670 cpu@301 {
671 cpu-release-addr = <0x40 0xfff8>;
672 enable-method = "spin-table";
673 reg = <0x0 0x301>;
674 compatible = "apm,potenza", "arm,armv8";
675 device_type = "cpu";
676 };
677
678 cpu@300 {
679 cpu-release-addr = <0x40 0xfff8>;
680 enable-method = "spin-table";
681 reg = <0x0 0x300>;
682 compatible = "apm,potenza", "arm,armv8";
683 device_type = "cpu";
684 };
685
686 cpu@201 {
687 cpu-release-addr = <0x40 0xfff8>;
688 enable-method = "spin-table";
689 reg = <0x0 0x201>;
690 compatible = "apm,potenza", "arm,armv8";
691 device_type = "cpu";
692 };
693
694 cpu@200 {
695 cpu-release-addr = <0x40 0xfff8>;
696 enable-method = "spin-table";
697 reg = <0x0 0x200>;
698 compatible = "apm,potenza", "arm,armv8";
699 device_type = "cpu";
700 };
701
702 cpu@101 {
703 cpu-release-addr = <0x40 0xfff8>;
704 enable-method = "spin-table";
705 reg = <0x0 0x101>;
706 compatible = "apm,potenza", "arm,armv8";
707 device_type = "cpu";
708 };
709
710 cpu@100 {
711 cpu-release-addr = <0x40 0xfff8>;
712 enable-method = "spin-table";
713 reg = <0x0 0x100>;
714 compatible = "apm,potenza", "arm,armv8";
715 device_type = "cpu";
716 };
717
718 cpu@001 {
719 cpu-release-addr = <0x40 0xfff8>;
720 enable-method = "spin-table";
721 reg = <0x0 0x1>;
722 compatible = "apm,potenza", "arm,armv8";
723 device_type = "cpu";
724 };
725
726 cpu@000 {
727 cpu-release-addr = <0x40 0xfff8>;
728 enable-method = "spin-table";
729 reg = <0x0 0x0>;
730 compatible = "apm,potenza", "arm,armv8";
731 device_type = "cpu";
732 };
733 };
734
735 rom {
736
737 boot-rom {
738 BootROM-version = "U02";
739 };
740 };
741
742 sl1500 {
743 compatible = "hp,moonshot";
744
745 node {
746 device_type = "hp,sl1500-node";
747 id = [31 00];
748 serial-number = "CN7416V02J";
749 uuid = "C69C5311-CB25-594A-9D73-56064A71BF4C";
750 boot-time = "2014-11-13T06:03:45";
751 boot-adjust = "47";
752 };
753
754 cartridge {
755 device_type = "hp,sl1500-cartridge";
756 id = "37";
757 serial-number = "CN7416V02J";
758 product-name = "ProLiant m400 Server Cartridge";
759 product-id = "721717-B21";
760 asset-tag = [00];
761 cpld = "04";
762 rom-sysid = "U02";
763 rom-date = "07/14/2014";
764 };
765
766 chassis {
767 device_type = "hp,sl1500-chassis";
768 serial-number = "MX241200GX";
769 asset-tag = [00];
770 timezone-gmtoff = [30 00];
771 timezone = "Europe/London";
772 timezone-data = "GMT-0:00BST-01:00:00,M3.5.0/01:00:00,M10.5.0/01:00:00";
773 };
774 };
775};
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-02 23:09:23 +0000