1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
|
From 19de4c98078a98a0663e945d419fa2147a70fe9c Mon Sep 17 00:00:00 2001
From: Simon Cook <simon.cook@embecosm.com>
Date: Wed, 31 Jul 2019 09:12:00 +0000
Subject: [PATCH] [RISCV] Add support for floating point registers in inlineasm
This adds support for parsing/emitting in IR the floating-point RISC-V
registers in inline assembly clobber lists.
Differential Revision: https://reviews.llvm.org/D64737
llvm-svn: 367399
---
clang/lib/Basic/Targets/RISCV.cpp | 33 ++++++++++++++++++++++---------
clang/test/Sema/riscv-asm.c | 28 ++++++++++++++++++++++++++
2 files changed, 52 insertions(+), 9 deletions(-)
create mode 100644 clang/test/Sema/riscv-asm.c
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 930b825e94d..d1166d90df4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -19,23 +19,38 @@ using namespace clang::targets;
ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
static const char *const GCCRegNames[] = {
+ // Integer registers
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
- "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"};
+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
+
+ // Floating point registers
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
return llvm::makeArrayRef(GCCRegNames);
}
ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
- {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
- {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
- {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
- {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
- {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
- {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
- {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
- {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"}};
+ {{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
+ {{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
+ {{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
+ {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
+ {{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
+ {{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
+ {{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
+ {{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"},
+ {{"ft0"}, "f0"}, {{"ft1"}, "f1"}, {{"ft2"}, "f2"}, {{"ft3"}, "f3"},
+ {{"ft4"}, "f4"}, {{"ft5"}, "f5"}, {{"ft6"}, "f6"}, {{"ft7"}, "f7"},
+ {{"fs0"}, "f8"}, {{"fs1"}, "f9"}, {{"fa0"}, "f10"}, {{"fa1"}, "f11"},
+ {{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"}, {{"fa5"}, "f15"},
+ {{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"}, "f18"}, {{"fs3"}, "f19"},
+ {{"fs4"}, "f20"}, {{"fs5"}, "f21"}, {{"fs6"}, "f22"}, {{"fs7"}, "f23"},
+ {{"fs8"}, "f24"}, {{"fs9"}, "f25"}, {{"fs10"}, "f26"}, {{"fs11"}, "f27"},
+ {{"ft8"}, "f28"}, {{"ft9"}, "f29"}, {{"ft10"}, "f30"}, {{"ft11"}, "f31"}};
return llvm::makeArrayRef(GCCRegAliases);
}
diff --git a/clang/test/Sema/riscv-asm.c b/clang/test/Sema/riscv-asm.c
new file mode 100644
index 00000000000..82664c01317
--- /dev/null
+++ b/clang/test/Sema/riscv-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 %s -triple riscv32 -verify -fsyntax-only
+// RUN: %clang_cc1 %s -triple riscv64 -verify -fsyntax-only
+
+// expected-no-diagnostics
+
+void i (void) {
+ asm volatile ("" ::: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7");
+ asm volatile ("" ::: "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15");
+ asm volatile ("" ::: "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23");
+ asm volatile ("" ::: "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31");
+
+ asm volatile ("" ::: "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2");
+ asm volatile ("" ::: "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5");
+ asm volatile ("" ::: "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7");
+ asm volatile ("" ::: "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6");
+}
+
+void f (void) {
+ asm volatile ("" ::: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7");
+ asm volatile ("" ::: "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
+ asm volatile ("" ::: "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23");
+ asm volatile ("" ::: "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
+
+ asm volatile ("" ::: "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7");
+ asm volatile ("" ::: "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5");
+ asm volatile ("" ::: "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7");
+ asm volatile ("" ::: "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11");
+}
|
