diff options
| author | Dalon Westergreen <dwesterg@gmail.com> | 2019-08-12 12:52:35 -0700 |
|---|---|---|
| committer | Khem Raj <raj.khem@gmail.com> | 2019-08-13 22:13:28 -0700 |
| commit | cdabbbd867c08f1a5b81b6d875c637007a2a46cb (patch) | |
| tree | 7d0c39e4206aedf062affe23c6ab2c6d7e7fd341 /recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch | |
| parent | bcce227df6c047292b79724458d102ed335ee4fd (diff) | |
| download | meta-altera-cdabbbd867c08f1a5b81b6d875c637007a2a46cb.tar.gz | |
u-boot: cleanup 2019.07 stratix10 patches
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Diffstat (limited to 'recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch')
| -rw-r--r-- | recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch index 7d30706..55a9805 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | From a859bc214aa913be022a7aa8f03723079a325b07 Mon Sep 17 00:00:00 2001 | 1 | From d6ac4f9f2756a14021f9cdc3c3305f950643d45f Mon Sep 17 00:00:00 2001 |
| 2 | From: Chee Hong Ang <chee.hong.ang@intel.com> | 2 | From: Chee Hong Ang <chee.hong.ang@intel.com> |
| 3 | Date: Fri, 20 Apr 2018 18:28:07 +0800 | 3 | Date: Fri, 20 Apr 2018 18:28:07 +0800 |
| 4 | Subject: [PATCH 04/12] ARM: socfpga: stratix10: Enable SMC/PSCI calls from | 4 | Subject: [PATCH 04/14] ARM: socfpga: stratix10: Enable SMC/PSCI calls from |
| 5 | slave CPUs | 5 | slave CPUs |
| 6 | 6 | ||
| 7 | Before this patch, only master CPU (CPU0) is able to | 7 | Before this patch, only master CPU (CPU0) is able to |