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| author | Dalon Westergreen <dwesterg@gmail.com> | 2018-02-27 08:49:23 -0800 |
|---|---|---|
| committer | Khem Raj <raj.khem@gmail.com> | 2018-02-27 09:08:35 -0800 |
| commit | 84f3884e005e7ba97498d82859d9ec578aebd95b (patch) | |
| tree | 379b2ff25e4555b89e72e6980538ab60c1358f29 /classes | |
| parent | e3b57a3200ff397391a934f64a6e521f5486d0fd (diff) | |
| download | meta-altera-84f3884e005e7ba97498d82859d9ec578aebd95b.tar.gz | |
Generate U-Boot SPL hex image
For Stratix10, U-Boot SPL is placed in the FPGA
image. To do this, it must be in an ihex format.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Diffstat (limited to 'classes')
0 files changed, 0 insertions, 0 deletions