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Diffstat (limited to 'patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch')
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diff --git a/patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch b/patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch new file mode 100644 index 0000000..31c3de6 --- /dev/null +++ b/patches/cve/CVE-2018-15572-x86-speculation-Protect-against-userspace-userspace-.patch | |||
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1 | Date: Thu, 11 Oct 2018 05:34:10 +0200 | ||
2 | Subject: [PATCH] x86/speculation: Protect against userspace-userspace | ||
3 | spectreRSB | ||
4 | |||
5 | The article "Spectre Returns! Speculation Attacks using the Return Stack | ||
6 | Buffer" [1] describes two new (sub-)variants of spectrev2-like attacks, | ||
7 | making use solely of the RSB contents even on CPUs that don't fallback to | ||
8 | BTB on RSB underflow (Skylake+). | ||
9 | |||
10 | Mitigate userspace-userspace attacks by always unconditionally filling RSB on | ||
11 | context switch when the generic spectrev2 mitigation has been enabled. | ||
12 | |||
13 | [1] https://arxiv.org/pdf/1807.07940.pdf | ||
14 | |||
15 | CVE: CVE-2018-15572 | ||
16 | Upstream-Status: Backport | ||
17 | |||
18 | Signed-off-by: Jiri Kosina <jkosina@suse.cz> | ||
19 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | ||
20 | Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com> | ||
21 | Acked-by: Tim Chen <tim.c.chen@linux.intel.com> | ||
22 | Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | ||
23 | Cc: Borislav Petkov <bp@suse.de> | ||
24 | Cc: David Woodhouse <dwmw@amazon.co.uk> | ||
25 | Cc: Peter Zijlstra <peterz@infradead.org> | ||
26 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | ||
27 | Cc: stable@vger.kernel.org | ||
28 | Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1807261308190.997@cbobk.fhfr.pm | ||
29 | Signed-off-by: Andreas Wellving <andreas.wellving@enea.com> | ||
30 | --- | ||
31 | arch/x86/kernel/cpu/bugs.c | 40 ++++++++-------------------------------- | ||
32 | 1 file changed, 8 insertions(+), 32 deletions(-) | ||
33 | |||
34 | diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c | ||
35 | index 86af9b1..a416723 100644 | ||
36 | --- a/arch/x86/kernel/cpu/bugs.c | ||
37 | +++ b/arch/x86/kernel/cpu/bugs.c | ||
38 | @@ -310,23 +310,6 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) | ||
39 | return cmd; | ||
40 | } | ||
41 | |||
42 | -/* Check for Skylake-like CPUs (for RSB handling) */ | ||
43 | -static bool __init is_skylake_era(void) | ||
44 | -{ | ||
45 | - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | ||
46 | - boot_cpu_data.x86 == 6) { | ||
47 | - switch (boot_cpu_data.x86_model) { | ||
48 | - case INTEL_FAM6_SKYLAKE_MOBILE: | ||
49 | - case INTEL_FAM6_SKYLAKE_DESKTOP: | ||
50 | - case INTEL_FAM6_SKYLAKE_X: | ||
51 | - case INTEL_FAM6_KABYLAKE_MOBILE: | ||
52 | - case INTEL_FAM6_KABYLAKE_DESKTOP: | ||
53 | - return true; | ||
54 | - } | ||
55 | - } | ||
56 | - return false; | ||
57 | -} | ||
58 | - | ||
59 | static void __init spectre_v2_select_mitigation(void) | ||
60 | { | ||
61 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | ||
62 | @@ -387,22 +370,15 @@ static void __init spectre_v2_select_mitigation(void) | ||
63 | pr_info("%s\n", spectre_v2_strings[mode]); | ||
64 | |||
65 | /* | ||
66 | - * If neither SMEP nor PTI are available, there is a risk of | ||
67 | - * hitting userspace addresses in the RSB after a context switch | ||
68 | - * from a shallow call stack to a deeper one. To prevent this fill | ||
69 | - * the entire RSB, even when using IBRS. | ||
70 | - * | ||
71 | - * Skylake era CPUs have a separate issue with *underflow* of the | ||
72 | - * RSB, when they will predict 'ret' targets from the generic BTB. | ||
73 | - * The proper mitigation for this is IBRS. If IBRS is not supported | ||
74 | - * or deactivated in favour of retpolines the RSB fill on context | ||
75 | - * switch is required. | ||
76 | + * If spectre v2 protection has been enabled, unconditionally fill | ||
77 | + * RSB during a context switch; this protects against two independent | ||
78 | + * issues: | ||
79 | + * | ||
80 | + * - RSB underflow (and switch to BTB) on Skylake+ | ||
81 | + * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | ||
82 | */ | ||
83 | - if ((!boot_cpu_has(X86_FEATURE_KAISER) && | ||
84 | - !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | ||
85 | - setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | ||
86 | - pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); | ||
87 | - } | ||
88 | + setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | ||
89 | + pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | ||
90 | |||
91 | /* Initialize Indirect Branch Prediction Barrier if supported */ | ||
92 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | ||
93 | -- | ||
94 | |||
95 | |||