diff options
Diffstat (limited to 'patches/boot_time_opt/0108-intel_idle-tweak-cpuidle-cstates.patch')
-rw-r--r-- | patches/boot_time_opt/0108-intel_idle-tweak-cpuidle-cstates.patch | 227 |
1 files changed, 227 insertions, 0 deletions
diff --git a/patches/boot_time_opt/0108-intel_idle-tweak-cpuidle-cstates.patch b/patches/boot_time_opt/0108-intel_idle-tweak-cpuidle-cstates.patch new file mode 100644 index 0000000..da5396c --- /dev/null +++ b/patches/boot_time_opt/0108-intel_idle-tweak-cpuidle-cstates.patch | |||
@@ -0,0 +1,227 @@ | |||
1 | From bf7e0cebaafe790f62cbc5815648d556847b7d27 Mon Sep 17 00:00:00 2001 | ||
2 | From: Arjan van de Ven <arjan@linux.intel.com> | ||
3 | Date: Sat, 19 Mar 2016 21:32:19 -0400 | ||
4 | Subject: [PATCH 108/124] intel_idle: tweak cpuidle cstates | ||
5 | |||
6 | Increase target_residency in cpuidle cstate | ||
7 | |||
8 | Tune intel_idle to be a bit less agressive; | ||
9 | Clear linux is cleaner in hygiene (wakupes) than the average linux, | ||
10 | so we can afford changing these in a way that increases | ||
11 | performance while keeping power efficiency | ||
12 | --- | ||
13 | drivers/idle/intel_idle.c | 74 +++++++++++------------------------------------ | ||
14 | 1 file changed, 17 insertions(+), 57 deletions(-) | ||
15 | |||
16 | diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c | ||
17 | index 4466a2f969d7..cbab050b83f0 100644 | ||
18 | --- a/drivers/idle/intel_idle.c | ||
19 | +++ b/drivers/idle/intel_idle.c | ||
20 | @@ -475,7 +475,7 @@ static struct cpuidle_state hsw_cstates[] = { | ||
21 | .desc = "MWAIT 0x10", | ||
22 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
23 | .exit_latency = 33, | ||
24 | - .target_residency = 100, | ||
25 | + .target_residency = 1000, | ||
26 | .enter = &intel_idle, | ||
27 | .enter_freeze = intel_idle_freeze, }, | ||
28 | { | ||
29 | @@ -483,7 +483,7 @@ static struct cpuidle_state hsw_cstates[] = { | ||
30 | .desc = "MWAIT 0x20", | ||
31 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
32 | .exit_latency = 133, | ||
33 | - .target_residency = 400, | ||
34 | + .target_residency = 4000, | ||
35 | .enter = &intel_idle, | ||
36 | .enter_freeze = intel_idle_freeze, }, | ||
37 | { | ||
38 | @@ -491,7 +491,7 @@ static struct cpuidle_state hsw_cstates[] = { | ||
39 | .desc = "MWAIT 0x32", | ||
40 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
41 | .exit_latency = 166, | ||
42 | - .target_residency = 500, | ||
43 | + .target_residency = 5000, | ||
44 | .enter = &intel_idle, | ||
45 | .enter_freeze = intel_idle_freeze, }, | ||
46 | { | ||
47 | @@ -499,7 +499,7 @@ static struct cpuidle_state hsw_cstates[] = { | ||
48 | .desc = "MWAIT 0x40", | ||
49 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
50 | .exit_latency = 300, | ||
51 | - .target_residency = 900, | ||
52 | + .target_residency = 9000, | ||
53 | .enter = &intel_idle, | ||
54 | .enter_freeze = intel_idle_freeze, }, | ||
55 | { | ||
56 | @@ -507,7 +507,7 @@ static struct cpuidle_state hsw_cstates[] = { | ||
57 | .desc = "MWAIT 0x50", | ||
58 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
59 | .exit_latency = 600, | ||
60 | - .target_residency = 1800, | ||
61 | + .target_residency = 18000, | ||
62 | .enter = &intel_idle, | ||
63 | .enter_freeze = intel_idle_freeze, }, | ||
64 | { | ||
65 | @@ -515,7 +515,7 @@ static struct cpuidle_state hsw_cstates[] = { | ||
66 | .desc = "MWAIT 0x60", | ||
67 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
68 | .exit_latency = 2600, | ||
69 | - .target_residency = 7700, | ||
70 | + .target_residency = 77000, | ||
71 | .enter = &intel_idle, | ||
72 | .enter_freeze = intel_idle_freeze, }, | ||
73 | { | ||
74 | @@ -531,27 +531,11 @@ static struct cpuidle_state bdw_cstates[] = { | ||
75 | .enter = &intel_idle, | ||
76 | .enter_freeze = intel_idle_freeze, }, | ||
77 | { | ||
78 | - .name = "C1E-BDW", | ||
79 | - .desc = "MWAIT 0x01", | ||
80 | - .flags = MWAIT2flg(0x01), | ||
81 | - .exit_latency = 10, | ||
82 | - .target_residency = 20, | ||
83 | - .enter = &intel_idle, | ||
84 | - .enter_freeze = intel_idle_freeze, }, | ||
85 | - { | ||
86 | - .name = "C3-BDW", | ||
87 | - .desc = "MWAIT 0x10", | ||
88 | - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
89 | - .exit_latency = 40, | ||
90 | - .target_residency = 100, | ||
91 | - .enter = &intel_idle, | ||
92 | - .enter_freeze = intel_idle_freeze, }, | ||
93 | - { | ||
94 | .name = "C6-BDW", | ||
95 | .desc = "MWAIT 0x20", | ||
96 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
97 | .exit_latency = 133, | ||
98 | - .target_residency = 400, | ||
99 | + .target_residency = 4000, | ||
100 | .enter = &intel_idle, | ||
101 | .enter_freeze = intel_idle_freeze, }, | ||
102 | { | ||
103 | @@ -559,7 +543,7 @@ static struct cpuidle_state bdw_cstates[] = { | ||
104 | .desc = "MWAIT 0x32", | ||
105 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
106 | .exit_latency = 166, | ||
107 | - .target_residency = 500, | ||
108 | + .target_residency = 5000, | ||
109 | .enter = &intel_idle, | ||
110 | .enter_freeze = intel_idle_freeze, }, | ||
111 | { | ||
112 | @@ -567,7 +551,7 @@ static struct cpuidle_state bdw_cstates[] = { | ||
113 | .desc = "MWAIT 0x40", | ||
114 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
115 | .exit_latency = 300, | ||
116 | - .target_residency = 900, | ||
117 | + .target_residency = 9000, | ||
118 | .enter = &intel_idle, | ||
119 | .enter_freeze = intel_idle_freeze, }, | ||
120 | { | ||
121 | @@ -575,7 +559,7 @@ static struct cpuidle_state bdw_cstates[] = { | ||
122 | .desc = "MWAIT 0x50", | ||
123 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
124 | .exit_latency = 600, | ||
125 | - .target_residency = 1800, | ||
126 | + .target_residency = 18000, | ||
127 | .enter = &intel_idle, | ||
128 | .enter_freeze = intel_idle_freeze, }, | ||
129 | { | ||
130 | @@ -583,7 +567,7 @@ static struct cpuidle_state bdw_cstates[] = { | ||
131 | .desc = "MWAIT 0x60", | ||
132 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
133 | .exit_latency = 2600, | ||
134 | - .target_residency = 7700, | ||
135 | + .target_residency = 77000, | ||
136 | .enter = &intel_idle, | ||
137 | .enter_freeze = intel_idle_freeze, }, | ||
138 | { | ||
139 | @@ -600,27 +584,11 @@ static struct cpuidle_state skl_cstates[] = { | ||
140 | .enter = &intel_idle, | ||
141 | .enter_freeze = intel_idle_freeze, }, | ||
142 | { | ||
143 | - .name = "C1E-SKL", | ||
144 | - .desc = "MWAIT 0x01", | ||
145 | - .flags = MWAIT2flg(0x01), | ||
146 | - .exit_latency = 10, | ||
147 | - .target_residency = 20, | ||
148 | - .enter = &intel_idle, | ||
149 | - .enter_freeze = intel_idle_freeze, }, | ||
150 | - { | ||
151 | - .name = "C3-SKL", | ||
152 | - .desc = "MWAIT 0x10", | ||
153 | - .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
154 | - .exit_latency = 70, | ||
155 | - .target_residency = 100, | ||
156 | - .enter = &intel_idle, | ||
157 | - .enter_freeze = intel_idle_freeze, }, | ||
158 | - { | ||
159 | .name = "C6-SKL", | ||
160 | .desc = "MWAIT 0x20", | ||
161 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
162 | .exit_latency = 85, | ||
163 | - .target_residency = 200, | ||
164 | + .target_residency = 2000, | ||
165 | .enter = &intel_idle, | ||
166 | .enter_freeze = intel_idle_freeze, }, | ||
167 | { | ||
168 | @@ -628,7 +596,7 @@ static struct cpuidle_state skl_cstates[] = { | ||
169 | .desc = "MWAIT 0x33", | ||
170 | .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
171 | .exit_latency = 124, | ||
172 | - .target_residency = 800, | ||
173 | + .target_residency = 8000, | ||
174 | .enter = &intel_idle, | ||
175 | .enter_freeze = intel_idle_freeze, }, | ||
176 | { | ||
177 | @@ -636,7 +604,7 @@ static struct cpuidle_state skl_cstates[] = { | ||
178 | .desc = "MWAIT 0x40", | ||
179 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
180 | .exit_latency = 200, | ||
181 | - .target_residency = 800, | ||
182 | + .target_residency = 8000, | ||
183 | .enter = &intel_idle, | ||
184 | .enter_freeze = intel_idle_freeze, }, | ||
185 | { | ||
186 | @@ -644,7 +612,7 @@ static struct cpuidle_state skl_cstates[] = { | ||
187 | .desc = "MWAIT 0x50", | ||
188 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
189 | .exit_latency = 480, | ||
190 | - .target_residency = 5000, | ||
191 | + .target_residency = 50000, | ||
192 | .enter = &intel_idle, | ||
193 | .enter_freeze = intel_idle_freeze, }, | ||
194 | { | ||
195 | @@ -652,7 +620,7 @@ static struct cpuidle_state skl_cstates[] = { | ||
196 | .desc = "MWAIT 0x60", | ||
197 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
198 | .exit_latency = 890, | ||
199 | - .target_residency = 5000, | ||
200 | + .target_residency = 50000, | ||
201 | .enter = &intel_idle, | ||
202 | .enter_freeze = intel_idle_freeze, }, | ||
203 | { | ||
204 | @@ -669,19 +637,11 @@ static struct cpuidle_state skx_cstates[] = { | ||
205 | .enter = &intel_idle, | ||
206 | .enter_freeze = intel_idle_freeze, }, | ||
207 | { | ||
208 | - .name = "C1E-SKX", | ||
209 | - .desc = "MWAIT 0x01", | ||
210 | - .flags = MWAIT2flg(0x01), | ||
211 | - .exit_latency = 10, | ||
212 | - .target_residency = 20, | ||
213 | - .enter = &intel_idle, | ||
214 | - .enter_freeze = intel_idle_freeze, }, | ||
215 | - { | ||
216 | .name = "C6-SKX", | ||
217 | .desc = "MWAIT 0x20", | ||
218 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
219 | .exit_latency = 133, | ||
220 | - .target_residency = 600, | ||
221 | + .target_residency = 1600, | ||
222 | .enter = &intel_idle, | ||
223 | .enter_freeze = intel_idle_freeze, }, | ||
224 | { | ||
225 | -- | ||
226 | 2.11.1 | ||
227 | |||