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-rw-r--r--patches/boot_time_opt/0107-intel_idle-tweak-cpuidle-cstates.patch229
1 files changed, 229 insertions, 0 deletions
diff --git a/patches/boot_time_opt/0107-intel_idle-tweak-cpuidle-cstates.patch b/patches/boot_time_opt/0107-intel_idle-tweak-cpuidle-cstates.patch
new file mode 100644
index 0000000..43c40cd
--- /dev/null
+++ b/patches/boot_time_opt/0107-intel_idle-tweak-cpuidle-cstates.patch
@@ -0,0 +1,229 @@
1From 790db86f51a23533d457b361bb61e2845b6de6b8 Mon Sep 17 00:00:00 2001
2From: Arjan van de Ven <arjan@linux.intel.com>
3Date: Sat, 19 Mar 2016 21:32:19 -0400
4Subject: [PATCH 107/126] intel_idle: tweak cpuidle cstates
5
6Increase target_residency in cpuidle cstate
7
8Tune intel_idle to be a bit less agressive;
9Clear linux is cleaner in hygiene (wakupes) than the average linux,
10so we can afford changing these in a way that increases
11performance while keeping power efficiency
12---
13 drivers/idle/intel_idle.c | 46 +++++++++++++++++++++++-----------------------
14 1 file changed, 23 insertions(+), 23 deletions(-)
15
16diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
17index f0b06b14e782..24609fbb1010 100644
18--- a/drivers/idle/intel_idle.c
19+++ b/drivers/idle/intel_idle.c
20@@ -466,7 +466,7 @@ static struct cpuidle_state hsw_cstates[] = {
21 .desc = "MWAIT 0x01",
22 .flags = MWAIT2flg(0x01),
23 .exit_latency = 10,
24- .target_residency = 20,
25+ .target_residency = 120,
26 .enter = &intel_idle,
27 .enter_s2idle = intel_idle_s2idle, },
28 {
29@@ -474,7 +474,7 @@ static struct cpuidle_state hsw_cstates[] = {
30 .desc = "MWAIT 0x10",
31 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
32 .exit_latency = 33,
33- .target_residency = 100,
34+ .target_residency = 1000,
35 .enter = &intel_idle,
36 .enter_s2idle = intel_idle_s2idle, },
37 {
38@@ -482,7 +482,7 @@ static struct cpuidle_state hsw_cstates[] = {
39 .desc = "MWAIT 0x20",
40 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
41 .exit_latency = 133,
42- .target_residency = 400,
43+ .target_residency = 4000,
44 .enter = &intel_idle,
45 .enter_s2idle = intel_idle_s2idle, },
46 {
47@@ -490,7 +490,7 @@ static struct cpuidle_state hsw_cstates[] = {
48 .desc = "MWAIT 0x32",
49 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
50 .exit_latency = 166,
51- .target_residency = 500,
52+ .target_residency = 5000,
53 .enter = &intel_idle,
54 .enter_s2idle = intel_idle_s2idle, },
55 {
56@@ -498,7 +498,7 @@ static struct cpuidle_state hsw_cstates[] = {
57 .desc = "MWAIT 0x40",
58 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
59 .exit_latency = 300,
60- .target_residency = 900,
61+ .target_residency = 9000,
62 .enter = &intel_idle,
63 .enter_s2idle = intel_idle_s2idle, },
64 {
65@@ -506,7 +506,7 @@ static struct cpuidle_state hsw_cstates[] = {
66 .desc = "MWAIT 0x50",
67 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
68 .exit_latency = 600,
69- .target_residency = 1800,
70+ .target_residency = 18000,
71 .enter = &intel_idle,
72 .enter_s2idle = intel_idle_s2idle, },
73 {
74@@ -514,7 +514,7 @@ static struct cpuidle_state hsw_cstates[] = {
75 .desc = "MWAIT 0x60",
76 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
77 .exit_latency = 2600,
78- .target_residency = 7700,
79+ .target_residency = 77000,
80 .enter = &intel_idle,
81 .enter_s2idle = intel_idle_s2idle, },
82 {
83@@ -534,7 +534,7 @@ static struct cpuidle_state bdw_cstates[] = {
84 .desc = "MWAIT 0x01",
85 .flags = MWAIT2flg(0x01),
86 .exit_latency = 10,
87- .target_residency = 20,
88+ .target_residency = 120,
89 .enter = &intel_idle,
90 .enter_s2idle = intel_idle_s2idle, },
91 {
92@@ -542,7 +542,7 @@ static struct cpuidle_state bdw_cstates[] = {
93 .desc = "MWAIT 0x10",
94 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
95 .exit_latency = 40,
96- .target_residency = 100,
97+ .target_residency = 1000,
98 .enter = &intel_idle,
99 .enter_s2idle = intel_idle_s2idle, },
100 {
101@@ -550,7 +550,7 @@ static struct cpuidle_state bdw_cstates[] = {
102 .desc = "MWAIT 0x20",
103 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
104 .exit_latency = 133,
105- .target_residency = 400,
106+ .target_residency = 4000,
107 .enter = &intel_idle,
108 .enter_s2idle = intel_idle_s2idle, },
109 {
110@@ -558,7 +558,7 @@ static struct cpuidle_state bdw_cstates[] = {
111 .desc = "MWAIT 0x32",
112 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
113 .exit_latency = 166,
114- .target_residency = 500,
115+ .target_residency = 5000,
116 .enter = &intel_idle,
117 .enter_s2idle = intel_idle_s2idle, },
118 {
119@@ -566,7 +566,7 @@ static struct cpuidle_state bdw_cstates[] = {
120 .desc = "MWAIT 0x40",
121 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
122 .exit_latency = 300,
123- .target_residency = 900,
124+ .target_residency = 9000,
125 .enter = &intel_idle,
126 .enter_s2idle = intel_idle_s2idle, },
127 {
128@@ -574,7 +574,7 @@ static struct cpuidle_state bdw_cstates[] = {
129 .desc = "MWAIT 0x50",
130 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
131 .exit_latency = 600,
132- .target_residency = 1800,
133+ .target_residency = 18000,
134 .enter = &intel_idle,
135 .enter_s2idle = intel_idle_s2idle, },
136 {
137@@ -582,7 +582,7 @@ static struct cpuidle_state bdw_cstates[] = {
138 .desc = "MWAIT 0x60",
139 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
140 .exit_latency = 2600,
141- .target_residency = 7700,
142+ .target_residency = 77000,
143 .enter = &intel_idle,
144 .enter_s2idle = intel_idle_s2idle, },
145 {
146@@ -603,7 +603,7 @@ static struct cpuidle_state skl_cstates[] = {
147 .desc = "MWAIT 0x01",
148 .flags = MWAIT2flg(0x01),
149 .exit_latency = 10,
150- .target_residency = 20,
151+ .target_residency = 120,
152 .enter = &intel_idle,
153 .enter_s2idle = intel_idle_s2idle, },
154 {
155@@ -611,7 +611,7 @@ static struct cpuidle_state skl_cstates[] = {
156 .desc = "MWAIT 0x10",
157 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
158 .exit_latency = 70,
159- .target_residency = 100,
160+ .target_residency = 1000,
161 .enter = &intel_idle,
162 .enter_s2idle = intel_idle_s2idle, },
163 {
164@@ -619,7 +619,7 @@ static struct cpuidle_state skl_cstates[] = {
165 .desc = "MWAIT 0x20",
166 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
167 .exit_latency = 85,
168- .target_residency = 200,
169+ .target_residency = 2000,
170 .enter = &intel_idle,
171 .enter_s2idle = intel_idle_s2idle, },
172 {
173@@ -627,7 +627,7 @@ static struct cpuidle_state skl_cstates[] = {
174 .desc = "MWAIT 0x33",
175 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
176 .exit_latency = 124,
177- .target_residency = 800,
178+ .target_residency = 8000,
179 .enter = &intel_idle,
180 .enter_s2idle = intel_idle_s2idle, },
181 {
182@@ -635,7 +635,7 @@ static struct cpuidle_state skl_cstates[] = {
183 .desc = "MWAIT 0x40",
184 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
185 .exit_latency = 200,
186- .target_residency = 800,
187+ .target_residency = 8000,
188 .enter = &intel_idle,
189 .enter_s2idle = intel_idle_s2idle, },
190 {
191@@ -643,7 +643,7 @@ static struct cpuidle_state skl_cstates[] = {
192 .desc = "MWAIT 0x50",
193 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
194 .exit_latency = 480,
195- .target_residency = 5000,
196+ .target_residency = 50000,
197 .enter = &intel_idle,
198 .enter_s2idle = intel_idle_s2idle, },
199 {
200@@ -651,7 +651,7 @@ static struct cpuidle_state skl_cstates[] = {
201 .desc = "MWAIT 0x60",
202 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
203 .exit_latency = 890,
204- .target_residency = 5000,
205+ .target_residency = 50000,
206 .enter = &intel_idle,
207 .enter_s2idle = intel_idle_s2idle, },
208 {
209@@ -672,7 +672,7 @@ static struct cpuidle_state skx_cstates[] = {
210 .desc = "MWAIT 0x01",
211 .flags = MWAIT2flg(0x01),
212 .exit_latency = 10,
213- .target_residency = 20,
214+ .target_residency = 1000,
215 .enter = &intel_idle,
216 .enter_s2idle = intel_idle_s2idle, },
217 {
218@@ -680,7 +680,7 @@ static struct cpuidle_state skx_cstates[] = {
219 .desc = "MWAIT 0x20",
220 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
221 .exit_latency = 133,
222- .target_residency = 600,
223+ .target_residency = 20000,
224 .enter = &intel_idle,
225 .enter_s2idle = intel_idle_s2idle, },
226 {
227--
2282.15.0
229
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-11 12:59:34 +0000