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diff --git a/recipes-jailhouse/jailhouse/files/plamics-bpi-root.c b/recipes-jailhouse/jailhouse/files/plamics-bpi-root.c
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1/*
2 * Jailhouse, a Linux-based partitioning hypervisor
3 *
4 * Test configuration for Banana Pi board (A20 dual-core Cortex-A7, 1G RAM)
5 *
6 * Copyright (c) Siemens AG, 2014
7 *
8 * Authors:
9 * Jan Kiszka <jan.kiszka@siemens.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
13 */
14
15#include <jailhouse/types.h>
16#include <jailhouse/cell-config.h>
17
18#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
19
20struct {
21 struct jailhouse_system header;
22 __u64 cpus[1];
23 struct jailhouse_memory mem_regions[18];
24 struct jailhouse_irqchip irqchips[1];
25 struct jailhouse_pci_device pci_devices[1];
26} __attribute__((packed)) config = {
27 .header = {
28 .signature = JAILHOUSE_SYSTEM_SIGNATURE,
29 .revision = JAILHOUSE_CONFIG_REVISION,
30 .hypervisor_memory = {
31 .phys_start = 0x7c000000,
32 .size = 0x4000000,
33 },
34 .debug_console = {
35 .address = 0x01c28000,
36 .size = 0x1000,
37 /* .clock_reg = 0x01c2006c, */
38 /* .gate_nr = 16 */
39 /* .divider = 0x0d, */
40 .flags = JAILHOUSE_CON_TYPE_8250 |
41 JAILHOUSE_CON_FLAG_MMIO,
42 },
43 .platform_info = {
44 .pci_mmconfig_base = 0x2000000,
45 .pci_mmconfig_end_bus = 0,
46 .pci_is_virtual = 1,
47 .arm = {
48 .gicd_base = 0x01c81000,
49 .gicc_base = 0x01c82000,
50 .gich_base = 0x01c84000,
51 .gicv_base = 0x01c86000,
52 .maintenance_irq = 25,
53 },
54 },
55 .root_cell = {
56 .name = "Banana-Pi",
57
58 .cpu_set_size = sizeof(config.cpus),
59 .num_memory_regions = ARRAY_SIZE(config.mem_regions),
60 .num_irqchips = ARRAY_SIZE(config.irqchips),
61 .num_pci_devices = ARRAY_SIZE(config.pci_devices),
62
63 .vpci_irq_base = 108,
64 },
65 },
66
67 .cpus = {
68 0x3,
69 },
70
71 .mem_regions = {
72 /* SPI */ {
73 .phys_start = 0x01c05000,
74 .virt_start = 0x01c05000,
75 .size = 0x00001000,
76 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
77 JAILHOUSE_MEM_IO,
78 },
79 /* MMC */ {
80 .phys_start = 0x01c0f000,
81 .virt_start = 0x01c0f000,
82 .size = 0x00001000,
83 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
84 JAILHOUSE_MEM_IO,
85 },
86 /* USB + PMU1 */ {
87 .phys_start = 0x01c14000,
88 .virt_start = 0x01c14000,
89 .size = 0x00001000,
90 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
91 JAILHOUSE_MEM_IO,
92 },
93 /* SATA */ {
94 .phys_start = 0x01c18000,
95 .virt_start = 0x01c18000,
96 .size = 0x00001000,
97 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
98 JAILHOUSE_MEM_IO,
99 },
100 /* USB + PMU2 */ {
101 .phys_start = 0x01c1c000,
102 .virt_start = 0x01c1c000,
103 .size = 0x00001000,
104 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
105 JAILHOUSE_MEM_IO,
106 },
107 /* CCU */ {
108 .phys_start = 0x01c20000,
109 .virt_start = 0x01c20000,
110 .size = 0x400,
111 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
112 JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
113 },
114 /* Ints */ {
115 .phys_start = 0x01c20400,
116 .virt_start = 0x01c20400,
117 .size = 0x400,
118 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
119 JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
120 },
121 /* GPIO: ports A-G */ {
122 .phys_start = 0x01c20800,
123 .virt_start = 0x01c20800,
124 .size = 0xfc,
125 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
126 JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
127 },
128 /* GPIO: port H */ {
129 .phys_start = 0x01c208fc,
130 .virt_start = 0x01c208fc,
131 .size = 0x24,
132 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
133 JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
134 },
135 /* GPIO: port I */ {
136 .phys_start = 0x01c20920,
137 .virt_start = 0x01c20920,
138 .size = 0x24,
139 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
140 JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
141 },
142 /* GPIO: intr config */ {
143 .phys_start = 0x01c20a00,
144 .virt_start = 0x01c20a00,
145 .size = 0x1c,
146 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
147 JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
148 },
149 /* Timer */ {
150 .phys_start = 0x01c20c00,
151 .virt_start = 0x01c20c00,
152 .size = 0x400,
153 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
154 JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
155 },
156 /* UART0-3 */ {
157 .phys_start = 0x01c28000,
158 .virt_start = 0x01c28000,
159 .size = 0x1000,
160 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
161 JAILHOUSE_MEM_IO,
162 },
163 /* GMAC */ {
164 .phys_start = 0x01c50000,
165 .virt_start = 0x01c50000,
166 .size = 0x00010000,
167 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
168 JAILHOUSE_MEM_IO,
169 },
170 /* HSTIMER */ {
171 .phys_start = 0x01c60000,
172 .virt_start = 0x01c60000,
173 .size = 0x00001000,
174 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
175 JAILHOUSE_MEM_IO,
176 },
177 /* RAM */ {
178 .phys_start = 0x40000000,
179 .virt_start = 0x40000000,
180 .size = 0x3bf00000,
181 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
182 JAILHOUSE_MEM_EXECUTE,
183 },
184 /* IVSHMEM shared memory region */ {
185 .phys_start = 0x7bf00000,
186 .virt_start = 0x7bf00000,
187 .size = 0x100000,
188 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
189 },
190 /* Framebuffer */ {
191 .phys_start = 0x7f700000,
192 .virt_start = 0x7f700000,
193 .size = 9<<20,
194 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
195 JAILHOUSE_MEM_IO,
196 },
197 },
198
199 .irqchips = {
200 /* GIC */ {
201 .address = 0x01c81000,
202 .pin_base = 32,
203 .pin_bitmap = {
204 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
205 },
206 },
207 },
208
209 .pci_devices = {
210 {
211 .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
212 .bdf = 0x00,
213 .bar_mask = {
214 0xffffff00, 0xffffffff, 0x00000000,
215 0x00000000, 0x00000000, 0x00000000,
216 },
217 .shmem_region = 16,
218 .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
219 },
220 },
221};
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-05 05:05:39 +0000