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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4.0.2-e300c2c3.patch319
1 files changed, 319 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4.0.2-e300c2c3.patch b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4.0.2-e300c2c3.patch
new file mode 100644
index 0000000000..d1df8b2716
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4.0.2-e300c2c3.patch
@@ -0,0 +1,319 @@
1Adds support for Freescale Power architecture e300c2 and e300c3 cores.
2http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm
3
4Leon Woestenberg <leonw@mailcan.com>
5
6---
7 gcc/config.gcc | 2
8 gcc/config/rs6000/e300c2c3.md | 189 ++++++++++++++++++++++++++++++++++++++++++
9 gcc/config/rs6000/rs6000.c | 24 +++++
10 gcc/config/rs6000/rs6000.h | 4
11 gcc/config/rs6000/rs6000.md | 3
12 5 files changed, 220 insertions(+), 2 deletions(-)
13
14Index: gcc-4.3.1/gcc/config/rs6000/e300c2c3.md
15===================================================================
16--- /dev/null 1970-01-01 00:00:00.000000000 +0000
17+++ gcc-4.3.1/gcc/config/rs6000/e300c2c3.md 2008-08-23 16:51:33.000000000 -0700
18@@ -0,0 +1,189 @@
19+;; Pipeline description for Motorola PowerPC e300c3 core.
20+;; Copyright (C) 2003 Free Software Foundation, Inc.
21+;;
22+;; This file is part of GCC.
23+
24+;; GCC is free software; you can redistribute it and/or modify it
25+;; under the terms of the GNU General Public License as published
26+;; by the Free Software Foundation; either version 2, or (at your
27+;; option) any later version.
28+
29+;; GCC is distributed in the hope that it will be useful, but WITHOUT
30+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
31+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
32+;; License for more details.
33+
34+;; You should have received a copy of the GNU General Public License
35+;; along with GCC; see the file COPYING. If not, write to the
36+;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
37+;; MA 02111-1307, USA.
38+
39+(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
40+(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
41+
42+;; We don't simulate general issue queue (GIC). If we have SU insn
43+;; and then SU1 insn, they can not be issued on the same cycle
44+;; (although SU1 insn and then SU insn can be issued) because the SU
45+;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
46+;; multipass insn scheduling will find the situation and issue the SU1
47+;; insn and then the SU insn.
48+(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
49+
50+;; We could describe completion buffers slots in combination with the
51+;; retirement units and the order of completion but the result
52+;; automaton would behave in the same way because we can not describe
53+;; real latency time with taking in order completion into account.
54+;; Actually we could define the real latency time by querying reserved
55+;; automaton units but the current scheduler uses latency time before
56+;; issuing insns and making any reservations.
57+;;
58+;; So our description is aimed to achieve a insn schedule in which the
59+;; insns would not wait in the completion buffer.
60+(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
61+
62+;; Branch unit:
63+(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
64+
65+;; IU:
66+(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
67+
68+;; IU: This used to describe non-pipelined division.
69+(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
70+
71+;; SRU:
72+(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
73+
74+;; Here we simplified LSU unit description not describing the stages.
75+(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
76+
77+;; FPU:
78+(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
79+
80+;; The following units are used to make automata deterministic
81+(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
82+(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
83+(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
84+(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
85+
86+;; The following sets to make automata deterministic when option ndfa is used.
87+(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
88+(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
89+(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
90+(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
91+
92+;; Some useful abbreviations.
93+(define_reservation "ppce300c3_decode"
94+ "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
95+(define_reservation "ppce300c3_issue"
96+ "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
97+(define_reservation "ppce300c3_retire"
98+ "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
99+(define_reservation "ppce300c3_iu_stage0"
100+ "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
101+
102+;; Compares can be executed either one of the IU or SRU
103+(define_insn_reservation "ppce300c3_cmp" 1
104+ (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
105+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
106+ "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
107+ +ppce300c3_retire")
108+
109+;; Other one cycle IU insns
110+(define_insn_reservation "ppce300c3_iu" 1
111+ (and (eq_attr "type" "integer,insert_word")
112+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
113+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
114+
115+;; Branch. Actually this latency time is not used by the scheduler.
116+(define_insn_reservation "ppce300c3_branch" 1
117+ (and (eq_attr "type" "jmpreg,branch")
118+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
119+ "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
120+
121+;; Multiply is non-pipelined but can be executed in any IU
122+(define_insn_reservation "ppce300c3_multiply" 2
123+ (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
124+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
125+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
126+ ppce300c3_iu_stage0+ppce300c3_retire")
127+
128+;; Divide. We use the average latency time here. We omit reserving a
129+;; retire unit because of the result automata will be huge.
130+(define_insn_reservation "ppce300c3_divide" 20
131+ (and (eq_attr "type" "idiv")
132+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
133+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
134+ ppce300c3_mu_div*19")
135+
136+;; CR logical
137+(define_insn_reservation "ppce300c3_cr_logical" 1
138+ (and (eq_attr "type" "cr_logical,delayed_cr")
139+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
140+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
141+
142+;; Mfcr
143+(define_insn_reservation "ppce300c3_mfcr" 1
144+ (and (eq_attr "type" "mfcr")
145+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
146+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
147+
148+;; Mtcrf
149+(define_insn_reservation "ppce300c3_mtcrf" 1
150+ (and (eq_attr "type" "mtcr")
151+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
152+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
153+
154+;; Mtjmpr
155+(define_insn_reservation "ppce300c3_mtjmpr" 1
156+ (and (eq_attr "type" "mtjmpr,mfjmpr")
157+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
158+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
159+
160+;; Float point instructions
161+(define_insn_reservation "ppce300c3_fpcompare" 3
162+ (and (eq_attr "type" "fpcompare")
163+ (eq_attr "cpu" "ppce300c3"))
164+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
165+
166+(define_insn_reservation "ppce300c3_fp" 3
167+ (and (eq_attr "type" "fp")
168+ (eq_attr "cpu" "ppce300c3"))
169+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
170+
171+(define_insn_reservation "ppce300c3_dmul" 4
172+ (and (eq_attr "type" "dmul")
173+ (eq_attr "cpu" "ppce300c3"))
174+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
175+
176+; Divides are not pipelined
177+(define_insn_reservation "ppce300c3_sdiv" 18
178+ (and (eq_attr "type" "sdiv")
179+ (eq_attr "cpu" "ppce300c3"))
180+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
181+
182+(define_insn_reservation "ppce300c3_ddiv" 33
183+ (and (eq_attr "type" "ddiv")
184+ (eq_attr "cpu" "ppce300c3"))
185+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
186+
187+;; Loads
188+(define_insn_reservation "ppce300c3_load" 2
189+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
190+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
191+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
192+
193+(define_insn_reservation "ppce300c3_fpload" 2
194+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
195+ (eq_attr "cpu" "ppce300c3"))
196+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
197+
198+;; Stores.
199+(define_insn_reservation "ppce300c3_store" 2
200+ (and (eq_attr "type" "store,store_ux,store_u")
201+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
202+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
203+
204+(define_insn_reservation "ppce300c3_fpstore" 2
205+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
206+ (eq_attr "cpu" "ppce300c3"))
207+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
208Index: gcc-4.3.1/gcc/config/rs6000/rs6000.c
209===================================================================
210--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.c 2008-08-23 16:49:39.000000000 -0700
211+++ gcc-4.3.1/gcc/config/rs6000/rs6000.c 2008-08-23 16:54:25.000000000 -0700
212@@ -669,6 +669,21 @@ struct processor_costs ppc8540_cost = {
213 1, /* prefetch streams /*/
214 };
215
216+/* Instruction costs on E300C2 and E300C3 cores. */
217+static const
218+struct processor_costs ppce300c2c3_cost = {
219+ COSTS_N_INSNS (4), /* mulsi */
220+ COSTS_N_INSNS (4), /* mulsi_const */
221+ COSTS_N_INSNS (4), /* mulsi_const9 */
222+ COSTS_N_INSNS (4), /* muldi */
223+ COSTS_N_INSNS (19), /* divsi */
224+ COSTS_N_INSNS (19), /* divdi */
225+ COSTS_N_INSNS (3), /* fp */
226+ COSTS_N_INSNS (4), /* dmul */
227+ COSTS_N_INSNS (18), /* sdiv */
228+ COSTS_N_INSNS (33), /* ddiv */
229+};
230+
231 /* Instruction costs on POWER4 and POWER5 processors. */
232 static const
233 struct processor_costs power4_cost = {
234@@ -1420,6 +1435,8 @@ rs6000_override_options (const char *def
235 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
236 /* 8548 has a dummy entry for now. */
237 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
238+ {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
239+ {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
240 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
241 {"970", PROCESSOR_POWER4,
242 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
243@@ -1845,6 +1862,11 @@ rs6000_override_options (const char *def
244 rs6000_cost = &ppc8540_cost;
245 break;
246
247+ case PROCESSOR_PPCE300C2:
248+ case PROCESSOR_PPCE300C3:
249+ rs6000_cost = &ppce300c2c3_cost;
250+ break;
251+
252 case PROCESSOR_POWER4:
253 case PROCESSOR_POWER5:
254 rs6000_cost = &power4_cost;
255@@ -18606,6 +18628,8 @@ rs6000_issue_rate (void)
256 case CPU_PPC7400:
257 case CPU_PPC8540:
258 case CPU_CELL:
259+ case CPU_PPCE300C2:
260+ case CPU_PPCE300C3:
261 return 2;
262 case CPU_RIOS2:
263 case CPU_PPC604:
264Index: gcc-4.3.1/gcc/config/rs6000/rs6000.h
265===================================================================
266--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.h 2008-01-26 09:18:35.000000000 -0800
267+++ gcc-4.3.1/gcc/config/rs6000/rs6000.h 2008-08-23 16:55:30.000000000 -0700
268@@ -117,6 +117,8 @@
269 %{mcpu=G5: -mpower4 -maltivec} \
270 %{mcpu=8540: -me500} \
271 %{mcpu=8548: -me500} \
272+%{mcpu=e300c2: -mppc} \
273+%{mcpu=e300c3: -mppc -mpmr} \
274 %{maltivec: -maltivec} \
275 -many"
276
277@@ -262,6 +264,8 @@ enum processor_type
278 PROCESSOR_PPC7400,
279 PROCESSOR_PPC7450,
280 PROCESSOR_PPC8540,
281+ PROCESSOR_PPCE300C2,
282+ PROCESSOR_PPCE300C3,
283 PROCESSOR_POWER4,
284 PROCESSOR_POWER5,
285 PROCESSOR_POWER6,
286Index: gcc-4.3.1/gcc/config/rs6000/rs6000.md
287===================================================================
288--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.md 2008-02-13 16:14:45.000000000 -0800
289+++ gcc-4.3.1/gcc/config/rs6000/rs6000.md 2008-08-23 16:57:29.000000000 -0700
290@@ -133,7 +133,7 @@
291 ;; Processor type -- this attribute must exactly match the processor_type
292 ;; enumeration in rs6000.h.
293
294-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
295+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell,ppce300c2,ppce300c3"
296 (const (symbol_ref "rs6000_cpu_attr")))
297
298
299@@ -166,6 +166,7 @@
300 (include "7xx.md")
301 (include "7450.md")
302 (include "8540.md")
303+(include "e300c2c3.md")
304 (include "power4.md")
305 (include "power5.md")
306 (include "power6.md")
307Index: gcc-4.3.1/gcc/config.gcc
308===================================================================
309--- gcc-4.3.1.orig/gcc/config.gcc 2008-08-23 16:49:43.000000000 -0700
310+++ gcc-4.3.1/gcc/config.gcc 2008-08-23 17:03:55.000000000 -0700
311@@ -3144,7 +3144,7 @@ case "${target}" in
312 | rios | rios1 | rios2 | rsc | rsc1 | rs64a \
313 | 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
314 | 601 | 602 | 603 | 603e | ec603e | 604 \
315- | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
316+ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
317 | 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
318 # OK
319 ;;
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