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-rw-r--r--meta/recipes-devtools/gdb/gdb-11.1.inc1
-rw-r--r--meta/recipes-devtools/gdb/gdb/0011-AArch64-Make-gdbserver-register-set-selection-dynamic.patch317
2 files changed, 318 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gdb/gdb-11.1.inc b/meta/recipes-devtools/gdb/gdb-11.1.inc
index 686627926d..a480997220 100644
--- a/meta/recipes-devtools/gdb/gdb-11.1.inc
+++ b/meta/recipes-devtools/gdb/gdb-11.1.inc
@@ -15,5 +15,6 @@ SRC_URI = "${GNU_MIRROR}/gdb/gdb-${PV}.tar.xz \
15 file://0008-resolve-restrict-keyword-conflict.patch \ 15 file://0008-resolve-restrict-keyword-conflict.patch \
16 file://0009-Fix-invalid-sigprocmask-call.patch \ 16 file://0009-Fix-invalid-sigprocmask-call.patch \
17 file://0010-gdbserver-ctrl-c-handling.patch \ 17 file://0010-gdbserver-ctrl-c-handling.patch \
18 file://0011-AArch64-Make-gdbserver-register-set-selection-dynamic.patch \
18 " 19 "
19SRC_URI[sha256sum] = "cccfcc407b20d343fb320d4a9a2110776dd3165118ffd41f4b1b162340333f94" 20SRC_URI[sha256sum] = "cccfcc407b20d343fb320d4a9a2110776dd3165118ffd41f4b1b162340333f94"
diff --git a/meta/recipes-devtools/gdb/gdb/0011-AArch64-Make-gdbserver-register-set-selection-dynamic.patch b/meta/recipes-devtools/gdb/gdb/0011-AArch64-Make-gdbserver-register-set-selection-dynamic.patch
new file mode 100644
index 0000000000..6fc1859391
--- /dev/null
+++ b/meta/recipes-devtools/gdb/gdb/0011-AArch64-Make-gdbserver-register-set-selection-dynamic.patch
@@ -0,0 +1,317 @@
1From eb79b2318066cafb75ffdce310e3bbd44f7c79e3 Mon Sep 17 00:00:00 2001
2From: Luis Machado <luis.machado@linaro.org>
3Date: Fri, 29 Oct 2021 14:54:36 -0300
4Subject: [PATCH] [AArch64] Make gdbserver register set selection dynamic
5
6The current register set selection mechanism for AArch64 is static, based
7on a pre-populated array of register sets.
8
9This means that we might potentially probe register sets that are not
10available. This is OK if the kernel errors out during ptrace, but probing the
11tag_ctl register, for example, does not result in a ptrace error if the kernel
12supports the tagged address ABI but not MTE (PR 28355).
13
14Making the register set selection dynamic, based on feature checks, solves
15this and simplifies the code a bit. It allows us to list all of the register
16sets only once, and pick and choose based on HWCAP/HWCAP2 or other properties.
17
18gdb/ChangeLog:
19
202021-11-03 Luis Machado <luis.machado@linaro.org>
21
22 PR gdb/28355
23
24 * arch/aarch64.h (struct aarch64_features): New struct.
25
26gdbserver/ChangeLog:
27
282021-11-03 Luis Machado <luis.machado@linaro.org>
29
30 PR gdb/28355
31
32 * linux-aarch64-low.cc (is_sve_tdesc): Remove.
33 (aarch64_target::low_arch_setup): Rework to adjust the register sets.
34 (aarch64_regsets): Update to list all register sets.
35 (aarch64_regsets_info, regs_info_aarch64): Replace NULL with nullptr.
36 (aarch64_sve_regsets, aarch64_sve_regsets_info)
37 (regs_info_aarch64_sve): Remove.
38 (aarch64_adjust_register_sets): New.
39 (aarch64_target::get_regs_info): Remove references to removed structs.
40 (initialize_low_arch): Likewise.
41
42[ChangeLog entry stripped so that patch applies cleanly]
43Upstream-Status: Accepted
44---
45
46diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h
47index 0eb702c5b5e..95edb664b55 100644
48--- a/gdb/arch/aarch64.h
49+++ b/gdb/arch/aarch64.h
50@@ -22,6 +22,15 @@
51
52 #include "gdbsupport/tdesc.h"
53
54+/* Holds information on what architectural features are available. This is
55+ used to select register sets. */
56+struct aarch64_features
57+{
58+ bool sve = false;
59+ bool pauth = false;
60+ bool mte = false;
61+};
62+
63 /* Create the aarch64 target description. A non zero VQ value indicates both
64 the presence of SVE and the Vector Quotient - the number of 128bit chunks in
65 an SVE Z register. HAS_PAUTH_P indicates the presence of the PAUTH
66diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc
67index daccfef746e..9a8cb4169a7 100644
68--- a/gdbserver/linux-aarch64-low.cc
69+++ b/gdbserver/linux-aarch64-low.cc
70@@ -196,16 +196,6 @@ is_64bit_tdesc (void)
71 return register_size (regcache->tdesc, 0) == 8;
72 }
73
74-/* Return true if the regcache contains the number of SVE registers. */
75-
76-static bool
77-is_sve_tdesc (void)
78-{
79- struct regcache *regcache = get_thread_regcache (current_thread, 0);
80-
81- return tdesc_contains_feature (regcache->tdesc, "org.gnu.gdb.aarch64.sve");
82-}
83-
84 static void
85 aarch64_fill_gregset (struct regcache *regcache, void *buf)
86 {
87@@ -680,40 +670,6 @@ aarch64_target::low_new_fork (process_info *parent,
88 *child->priv->arch_private = *parent->priv->arch_private;
89 }
90
91-/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
92-#define AARCH64_HWCAP_PACA (1 << 30)
93-
94-/* Implementation of linux target ops method "low_arch_setup". */
95-
96-void
97-aarch64_target::low_arch_setup ()
98-{
99- unsigned int machine;
100- int is_elf64;
101- int tid;
102-
103- tid = lwpid_of (current_thread);
104-
105- is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
106-
107- if (is_elf64)
108- {
109- uint64_t vq = aarch64_sve_get_vq (tid);
110- unsigned long hwcap = linux_get_hwcap (8);
111- unsigned long hwcap2 = linux_get_hwcap2 (8);
112- bool pauth_p = hwcap & AARCH64_HWCAP_PACA;
113- /* MTE is AArch64-only. */
114- bool mte_p = hwcap2 & HWCAP2_MTE;
115-
116- current_process ()->tdesc
117- = aarch64_linux_read_description (vq, pauth_p, mte_p);
118- }
119- else
120- current_process ()->tdesc = aarch32_linux_read_description ();
121-
122- aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
123-}
124-
125 /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
126
127 static void
128@@ -730,21 +686,36 @@ aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf)
129 return aarch64_sve_regs_copy_from_reg_buf (regcache, buf);
130 }
131
132+/* Array containing all the possible register sets for AArch64/Linux. During
133+ architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
134+ validity and enabled/disabled accordingly.
135+
136+ Their sizes are set to 0 here, but they will be adjusted later depending
137+ on whether each register set is available or not. */
138 static struct regset_info aarch64_regsets[] =
139 {
140+ /* GPR registers. */
141 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
142- sizeof (struct user_pt_regs), GENERAL_REGS,
143+ 0, GENERAL_REGS,
144 aarch64_fill_gregset, aarch64_store_gregset },
145+ /* Floating Point (FPU) registers. */
146 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
147- sizeof (struct user_fpsimd_state), FP_REGS,
148+ 0, FP_REGS,
149 aarch64_fill_fpregset, aarch64_store_fpregset
150 },
151+ /* Scalable Vector Extension (SVE) registers. */
152+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
153+ 0, EXTENDED_REGS,
154+ aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
155+ },
156+ /* PAC registers. */
157 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
158- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
159- NULL, aarch64_store_pauthregset },
160+ 0, OPTIONAL_REGS,
161+ nullptr, aarch64_store_pauthregset },
162+ /* Tagged address control / MTE registers. */
163 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
164- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
165- aarch64_store_mteregset },
166+ 0, OPTIONAL_REGS,
167+ aarch64_fill_mteregset, aarch64_store_mteregset },
168 NULL_REGSET
169 };
170
171@@ -752,47 +723,95 @@ static struct regsets_info aarch64_regsets_info =
172 {
173 aarch64_regsets, /* regsets */
174 0, /* num_regsets */
175- NULL, /* disabled_regsets */
176+ nullptr, /* disabled_regsets */
177 };
178
179 static struct regs_info regs_info_aarch64 =
180 {
181- NULL, /* regset_bitmap */
182- NULL, /* usrregs */
183+ nullptr, /* regset_bitmap */
184+ nullptr, /* usrregs */
185 &aarch64_regsets_info,
186 };
187
188-static struct regset_info aarch64_sve_regsets[] =
189+/* Given FEATURES, adjust the available register sets by setting their
190+ sizes. A size of 0 means the register set is disabled and won't be
191+ used. */
192+
193+static void
194+aarch64_adjust_register_sets (const struct aarch64_features &features)
195 {
196- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
197- sizeof (struct user_pt_regs), GENERAL_REGS,
198- aarch64_fill_gregset, aarch64_store_gregset },
199- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
200- SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE), EXTENDED_REGS,
201- aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
202- },
203- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
204- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
205- NULL, aarch64_store_pauthregset },
206- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
207- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
208- aarch64_store_mteregset },
209- NULL_REGSET
210-};
211+ struct regset_info *regset;
212
213-static struct regsets_info aarch64_sve_regsets_info =
214- {
215- aarch64_sve_regsets, /* regsets. */
216- 0, /* num_regsets. */
217- NULL, /* disabled_regsets. */
218- };
219+ for (regset = aarch64_regsets; regset->size >= 0; regset++)
220+ {
221+ switch (regset->nt_type)
222+ {
223+ case NT_PRSTATUS:
224+ /* General purpose registers are always present. */
225+ regset->size = sizeof (struct user_pt_regs);
226+ break;
227+ case NT_FPREGSET:
228+ /* This is unavailable when SVE is present. */
229+ if (!features.sve)
230+ regset->size = sizeof (struct user_fpsimd_state);
231+ break;
232+ case NT_ARM_SVE:
233+ if (features.sve)
234+ regset->size = SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE);
235+ break;
236+ case NT_ARM_PAC_MASK:
237+ if (features.pauth)
238+ regset->size = AARCH64_PAUTH_REGS_SIZE;
239+ break;
240+ case NT_ARM_TAGGED_ADDR_CTRL:
241+ if (features.mte)
242+ regset->size = AARCH64_LINUX_SIZEOF_MTE;
243+ break;
244+ default:
245+ gdb_assert_not_reached ("Unknown register set found.");
246+ }
247+ }
248+}
249
250-static struct regs_info regs_info_aarch64_sve =
251- {
252- NULL, /* regset_bitmap. */
253- NULL, /* usrregs. */
254- &aarch64_sve_regsets_info,
255- };
256+/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
257+#define AARCH64_HWCAP_PACA (1 << 30)
258+
259+/* Implementation of linux target ops method "low_arch_setup". */
260+
261+void
262+aarch64_target::low_arch_setup ()
263+{
264+ unsigned int machine;
265+ int is_elf64;
266+ int tid;
267+
268+ tid = lwpid_of (current_thread);
269+
270+ is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
271+
272+ if (is_elf64)
273+ {
274+ struct aarch64_features features;
275+
276+ uint64_t vq = aarch64_sve_get_vq (tid);
277+ features.sve = (vq > 0);
278+ /* A-profile PAC is 64-bit only. */
279+ features.pauth = linux_get_hwcap (8) & AARCH64_HWCAP_PACA;
280+ /* A-profile MTE is 64-bit only. */
281+ features.mte = linux_get_hwcap2 (8) & HWCAP2_MTE;
282+
283+ current_process ()->tdesc
284+ = aarch64_linux_read_description (vq, features.pauth, features.mte);
285+
286+ /* Adjust the register sets we should use for this particular set of
287+ features. */
288+ aarch64_adjust_register_sets (features);
289+ }
290+ else
291+ current_process ()->tdesc = aarch32_linux_read_description ();
292+
293+ aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
294+}
295
296 /* Implementation of linux target ops method "get_regs_info". */
297
298@@ -802,9 +821,7 @@ aarch64_target::get_regs_info ()
299 if (!is_64bit_tdesc ())
300 return &regs_info_aarch32;
301
302- if (is_sve_tdesc ())
303- return &regs_info_aarch64_sve;
304-
305+ /* AArch64 64-bit registers. */
306 return &regs_info_aarch64;
307 }
308
309@@ -3294,5 +3311,4 @@ initialize_low_arch (void)
310 initialize_low_arch_aarch32 ();
311
312 initialize_regsets_info (&aarch64_regsets_info);
313- initialize_regsets_info (&aarch64_sve_regsets_info);
314 }
315--
3162.27.0
317
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-12-09 09:08:21 +0000