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-rw-r--r--meta/packages/linux/linux-cmx270-2.6.16/CL_FlashDrvbin0 -> 173090 bytes
-rw-r--r--meta/packages/linux/linux-cmx270-2.6.16/diff-2.6.16-cm-x2709154
-rw-r--r--meta/packages/linux/linux-cmx270-rp_2.6.17.bb2
-rw-r--r--meta/packages/linux/linux-cmx270_2.6.16.bb34
-rw-r--r--meta/packages/linux/linux-cmx270_2.6.17.bb2
5 files changed, 9192 insertions, 0 deletions
diff --git a/meta/packages/linux/linux-cmx270-2.6.16/CL_FlashDrv b/meta/packages/linux/linux-cmx270-2.6.16/CL_FlashDrv
new file mode 100644
index 0000000000..4c35c9e71d
--- /dev/null
+++ b/meta/packages/linux/linux-cmx270-2.6.16/CL_FlashDrv
Binary files differ
diff --git a/meta/packages/linux/linux-cmx270-2.6.16/diff-2.6.16-cm-x270 b/meta/packages/linux/linux-cmx270-2.6.16/diff-2.6.16-cm-x270
new file mode 100644
index 0000000000..5610a3e6a5
--- /dev/null
+++ b/meta/packages/linux/linux-cmx270-2.6.16/diff-2.6.16-cm-x270
@@ -0,0 +1,9154 @@
1diff --git a/Makefile b/Makefile
2index cb57905..dd02f27 100644
3--- a/Makefile
4+++ b/Makefile
5@@ -172,8 +172,11 @@ # Alternatively CROSS_COMPILE can be set
6 # Default value for CROSS_COMPILE is not to prefix executables
7 # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
8
9-ARCH ?= $(SUBARCH)
10-CROSS_COMPILE ?=
11+#ARCH ?= $(SUBARCH)
12+#CROSS_COMPILE ?=
13+
14+ARCH = arm
15+CROSS_COMPILE = arm-linux-
16
17 # Architecture as present in compile.h
18 UTS_MACHINE := $(ARCH)
19diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
20index 32ba00b..2de9ceb 100644
21--- a/arch/arm/Kconfig
22+++ b/arch/arm/Kconfig
23@@ -331,7 +331,7 @@ config ISA_DMA_API
24 bool
25
26 config PCI
27- bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB
28+ bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || MACH_ARMCORE
29 help
30 Find out whether you have a PCI motherboard. PCI is the name of a
31 bus system, i.e. the way the CPU talks to the other stuff inside
32@@ -349,6 +349,12 @@ config PCI_HOST_VIA82C505
33 depends on PCI && ARCH_SHARK
34 default y
35
36+config PCI_HOST_ITE8152
37+ bool
38+ depends on PCI && MACH_ARMCORE
39+ default y
40+ select DMABOUNCE
41+
42 source "drivers/pci/Kconfig"
43
44 source "drivers/pcmcia/Kconfig"
45@@ -484,7 +490,7 @@ config LEDS
46 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
47 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
48 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
49- ARCH_AT91RM9200
50+ ARCH_AT91RM9200 || MACH_ARMCORE
51 help
52 If you say Y here, the LEDs on your machine will be used
53 to provide useful information about your current system status.
54diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
55index ad6c89a..dc2bbd0 100644
56--- a/arch/arm/common/dmabounce.c
57+++ b/arch/arm/common/dmabounce.c
58@@ -235,7 +235,7 @@ map_single(struct device *dev, void *ptr
59 /*
60 * Figure out if we need to bounce from the DMA mask.
61 */
62- needs_bounce = (dma_addr | (dma_addr + size - 1)) & ~mask;
63+ needs_bounce = ((dma_addr | (dma_addr + size - 1)) - PHYS_OFFSET) & ~mask;
64 }
65
66 if (device_info && (needs_bounce || dma_needs_bounce(dev, dma_addr, size))) {
67@@ -275,6 +275,7 @@ unmap_single(struct device *dev, dma_add
68 {
69 struct dmabounce_device_info *device_info = find_dmabounce_dev(dev);
70 struct safe_buffer *buf = NULL;
71+ unsigned long flags;
72
73 /*
74 * Trying to unmap an invalid mapping
75@@ -284,6 +285,8 @@ unmap_single(struct device *dev, dma_add
76 return;
77 }
78
79+ local_irq_save(flags);
80+
81 if (device_info)
82 buf = find_safe_buffer(device_info, dma_addr);
83
84@@ -316,8 +319,11 @@ unmap_single(struct device *dev, dma_add
85 ptr = (unsigned long)buf->ptr;
86 dmac_clean_range(ptr, ptr + size);
87 }
88+ local_irq_restore(flags);
89 free_safe_buffer(device_info, buf);
90 }
91+ else
92+ local_irq_restore(flags);
93 }
94
95 static inline void
96@@ -424,18 +430,12 @@ void
97 dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
98 enum dma_data_direction dir)
99 {
100- unsigned long flags;
101-
102 dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
103 __func__, (void *) dma_addr, size, dir);
104
105 BUG_ON(dir == DMA_NONE);
106
107- local_irq_save(flags);
108-
109 unmap_single(dev, dma_addr, size, dir);
110-
111- local_irq_restore(flags);
112 }
113
114 int
115@@ -471,7 +471,6 @@ void
116 dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
117 enum dma_data_direction dir)
118 {
119- unsigned long flags;
120 int i;
121
122 dev_dbg(dev, "%s(sg=%p,nents=%d,dir=%x)\n",
123@@ -479,16 +478,12 @@ dma_unmap_sg(struct device *dev, struct
124
125 BUG_ON(dir == DMA_NONE);
126
127- local_irq_save(flags);
128-
129 for (i = 0; i < nents; i++, sg++) {
130 dma_addr_t dma_addr = sg->dma_address;
131 unsigned int length = sg->length;
132
133 unmap_single(dev, dma_addr, length, dir);
134 }
135-
136- local_irq_restore(flags);
137 }
138
139 void
140@@ -632,7 +627,7 @@ #endif
141 list_add(&device_info->node, &dmabounce_devs);
142
143 printk(KERN_INFO "dmabounce: registered device %s on %s bus\n",
144- dev->bus_id, dev->bus->name);
145+ dev->bus_id, dev->bus ? dev->bus->name : "no");
146
147 return 0;
148
149@@ -677,7 +672,7 @@ #endif
150 kfree(device_info);
151
152 printk(KERN_INFO "dmabounce: device %s on %s bus unregistered\n",
153- dev->bus_id, dev->bus->name);
154+ dev->bus_id, dev->bus ? dev->bus->name : "no");
155 }
156
157
158diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/cm_x270_defconfig
159new file mode 100644
160index 0000000..7f6d1f7
161--- /dev/null
162+++ b/arch/arm/configs/cm_x270_defconfig
163@@ -0,0 +1,1311 @@
164+#
165+# Automatically generated make config: don't edit
166+# Linux kernel version: 2.6.16
167+# Wed Jun 14 17:50:29 2006
168+#
169+CONFIG_ARM=y
170+CONFIG_MMU=y
171+CONFIG_RWSEM_GENERIC_SPINLOCK=y
172+CONFIG_GENERIC_CALIBRATE_DELAY=y
173+CONFIG_ARCH_MTD_XIP=y
174+
175+#
176+# Code maturity level options
177+#
178+CONFIG_EXPERIMENTAL=y
179+CONFIG_BROKEN_ON_SMP=y
180+CONFIG_INIT_ENV_ARG_LIMIT=32
181+
182+#
183+# General setup
184+#
185+CONFIG_LOCALVERSION="-cm-x270"
186+# CONFIG_LOCALVERSION_AUTO is not set
187+CONFIG_SWAP=y
188+CONFIG_SYSVIPC=y
189+# CONFIG_POSIX_MQUEUE is not set
190+# CONFIG_BSD_PROCESS_ACCT is not set
191+CONFIG_SYSCTL=y
192+# CONFIG_AUDIT is not set
193+CONFIG_IKCONFIG=y
194+CONFIG_IKCONFIG_PROC=y
195+CONFIG_INITRAMFS_SOURCE=""
196+CONFIG_UID16=y
197+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
198+CONFIG_EMBEDDED=y
199+CONFIG_KALLSYMS=y
200+# CONFIG_KALLSYMS_ALL is not set
201+# CONFIG_KALLSYMS_EXTRA_PASS is not set
202+CONFIG_HOTPLUG=y
203+CONFIG_PRINTK=y
204+CONFIG_BUG=y
205+CONFIG_ELF_CORE=y
206+CONFIG_BASE_FULL=y
207+CONFIG_FUTEX=y
208+CONFIG_EPOLL=y
209+CONFIG_SHMEM=y
210+CONFIG_CC_ALIGN_FUNCTIONS=0
211+CONFIG_CC_ALIGN_LABELS=0
212+CONFIG_CC_ALIGN_LOOPS=0
213+CONFIG_CC_ALIGN_JUMPS=0
214+CONFIG_SLAB=y
215+# CONFIG_TINY_SHMEM is not set
216+CONFIG_BASE_SMALL=0
217+# CONFIG_SLOB is not set
218+
219+#
220+# Loadable module support
221+#
222+CONFIG_MODULES=y
223+CONFIG_MODULE_UNLOAD=y
224+CONFIG_MODULE_FORCE_UNLOAD=y
225+CONFIG_OBSOLETE_MODPARM=y
226+# CONFIG_MODVERSIONS is not set
227+# CONFIG_MODULE_SRCVERSION_ALL is not set
228+CONFIG_KMOD=y
229+
230+#
231+# Block layer
232+#
233+
234+#
235+# IO Schedulers
236+#
237+CONFIG_IOSCHED_NOOP=y
238+CONFIG_IOSCHED_AS=y
239+CONFIG_IOSCHED_DEADLINE=y
240+CONFIG_IOSCHED_CFQ=y
241+CONFIG_DEFAULT_AS=y
242+# CONFIG_DEFAULT_DEADLINE is not set
243+# CONFIG_DEFAULT_CFQ is not set
244+# CONFIG_DEFAULT_NOOP is not set
245+CONFIG_DEFAULT_IOSCHED="anticipatory"
246+
247+#
248+# System Type
249+#
250+# CONFIG_ARCH_CLPS7500 is not set
251+# CONFIG_ARCH_CLPS711X is not set
252+# CONFIG_ARCH_CO285 is not set
253+# CONFIG_ARCH_EBSA110 is not set
254+# CONFIG_ARCH_FOOTBRIDGE is not set
255+# CONFIG_ARCH_INTEGRATOR is not set
256+# CONFIG_ARCH_IOP3XX is not set
257+# CONFIG_ARCH_IXP4XX is not set
258+# CONFIG_ARCH_IXP2000 is not set
259+# CONFIG_ARCH_L7200 is not set
260+CONFIG_ARCH_PXA=y
261+# CONFIG_ARCH_RPC is not set
262+# CONFIG_ARCH_SA1100 is not set
263+# CONFIG_ARCH_S3C2410 is not set
264+# CONFIG_ARCH_SHARK is not set
265+# CONFIG_ARCH_LH7A40X is not set
266+# CONFIG_ARCH_OMAP is not set
267+# CONFIG_ARCH_VERSATILE is not set
268+# CONFIG_ARCH_REALVIEW is not set
269+# CONFIG_ARCH_IMX is not set
270+# CONFIG_ARCH_H720X is not set
271+# CONFIG_ARCH_AAEC2000 is not set
272+# CONFIG_ARCH_AT91RM9200 is not set
273+
274+#
275+# Intel PXA2xx Implementations
276+#
277+# CONFIG_ARCH_LUBBOCK is not set
278+# CONFIG_MACH_MAINSTONE is not set
279+CONFIG_MACH_ARMCORE=y
280+# CONFIG_ARCH_PXA_IDP is not set
281+# CONFIG_PXA_SHARPSL is not set
282+CONFIG_ARMCORE_ATXBASE=y
283+# CONFIG_ARMCORE_SB270 is not set
284+CONFIG_ARMCORE_REV12=y
285+# CONFIG_ARMCORE_REV11 is not set
286+CONFIG_PXA27x=y
287+CONFIG_IWMMXT=y
288+
289+#
290+# Processor Type
291+#
292+CONFIG_CPU_32=y
293+CONFIG_CPU_XSCALE=y
294+CONFIG_CPU_32v5=y
295+CONFIG_CPU_ABRT_EV5T=y
296+CONFIG_CPU_CACHE_VIVT=y
297+CONFIG_CPU_TLB_V4WBI=y
298+
299+#
300+# Processor Features
301+#
302+CONFIG_ARM_THUMB=y
303+CONFIG_XSCALE_PMU=y
304+CONFIG_DMABOUNCE=y
305+
306+#
307+# Bus support
308+#
309+CONFIG_PCI=y
310+CONFIG_PCI_HOST_ITE8152=y
311+# CONFIG_PCI_LEGACY_PROC is not set
312+# CONFIG_PCI_DEBUG is not set
313+
314+#
315+# PCCARD (PCMCIA/CardBus) support
316+#
317+CONFIG_PCCARD=y
318+# CONFIG_PCMCIA_DEBUG is not set
319+CONFIG_PCMCIA=y
320+# CONFIG_PCMCIA_LOAD_CIS is not set
321+CONFIG_PCMCIA_IOCTL=y
322+CONFIG_CARDBUS=y
323+
324+#
325+# PC-card bridges
326+#
327+CONFIG_YENTA=m
328+CONFIG_YENTA_O2=y
329+CONFIG_YENTA_RICOH=y
330+CONFIG_YENTA_TI=y
331+CONFIG_YENTA_ENE_TUNE=y
332+CONFIG_YENTA_TOSHIBA=y
333+# CONFIG_PD6729 is not set
334+# CONFIG_I82092 is not set
335+CONFIG_PCMCIA_PXA2XX=m
336+CONFIG_PCCARD_NONSTATIC=m
337+
338+#
339+# Kernel Features
340+#
341+# CONFIG_PREEMPT is not set
342+# CONFIG_NO_IDLE_HZ is not set
343+# CONFIG_AEABI is not set
344+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
345+CONFIG_SELECT_MEMORY_MODEL=y
346+CONFIG_FLATMEM_MANUAL=y
347+# CONFIG_DISCONTIGMEM_MANUAL is not set
348+# CONFIG_SPARSEMEM_MANUAL is not set
349+CONFIG_FLATMEM=y
350+CONFIG_FLAT_NODE_MEM_MAP=y
351+# CONFIG_SPARSEMEM_STATIC is not set
352+CONFIG_SPLIT_PTLOCK_CPUS=4096
353+CONFIG_LEDS=y
354+CONFIG_LEDS_TIMER=y
355+CONFIG_LEDS_CPU=y
356+CONFIG_ALIGNMENT_TRAP=y
357+
358+#
359+# Boot options
360+#
361+CONFIG_ZBOOT_ROM_TEXT=0x0
362+CONFIG_ZBOOT_ROM_BSS=0x0
363+CONFIG_CMDLINE=""
364+# CONFIG_XIP_KERNEL is not set
365+
366+#
367+# Floating point emulation
368+#
369+
370+#
371+# At least one emulation must be selected
372+#
373+CONFIG_FPE_NWFPE=y
374+# CONFIG_FPE_NWFPE_XP is not set
375+# CONFIG_FPE_FASTFPE is not set
376+
377+#
378+# Userspace binary formats
379+#
380+CONFIG_BINFMT_ELF=y
381+# CONFIG_BINFMT_AOUT is not set
382+# CONFIG_BINFMT_MISC is not set
383+# CONFIG_ARTHUR is not set
384+
385+#
386+# Power management options
387+#
388+CONFIG_PM=y
389+CONFIG_PM_LEGACY=y
390+# CONFIG_PM_DEBUG is not set
391+# CONFIG_APM is not set
392+
393+#
394+# Networking
395+#
396+CONFIG_NET=y
397+
398+#
399+# Networking options
400+#
401+# CONFIG_NETDEBUG is not set
402+CONFIG_PACKET=y
403+# CONFIG_PACKET_MMAP is not set
404+CONFIG_UNIX=y
405+# CONFIG_NET_KEY is not set
406+CONFIG_INET=y
407+# CONFIG_IP_MULTICAST is not set
408+# CONFIG_IP_ADVANCED_ROUTER is not set
409+CONFIG_IP_FIB_HASH=y
410+CONFIG_IP_PNP=y
411+CONFIG_IP_PNP_DHCP=y
412+CONFIG_IP_PNP_BOOTP=y
413+# CONFIG_IP_PNP_RARP is not set
414+# CONFIG_NET_IPIP is not set
415+# CONFIG_NET_IPGRE is not set
416+# CONFIG_ARPD is not set
417+# CONFIG_SYN_COOKIES is not set
418+# CONFIG_INET_AH is not set
419+# CONFIG_INET_ESP is not set
420+# CONFIG_INET_IPCOMP is not set
421+# CONFIG_INET_TUNNEL is not set
422+CONFIG_INET_DIAG=y
423+CONFIG_INET_TCP_DIAG=y
424+# CONFIG_TCP_CONG_ADVANCED is not set
425+CONFIG_TCP_CONG_BIC=y
426+# CONFIG_IPV6 is not set
427+# CONFIG_NETFILTER is not set
428+
429+#
430+# DCCP Configuration (EXPERIMENTAL)
431+#
432+# CONFIG_IP_DCCP is not set
433+
434+#
435+# SCTP Configuration (EXPERIMENTAL)
436+#
437+# CONFIG_IP_SCTP is not set
438+
439+#
440+# TIPC Configuration (EXPERIMENTAL)
441+#
442+# CONFIG_TIPC is not set
443+# CONFIG_ATM is not set
444+# CONFIG_BRIDGE is not set
445+# CONFIG_VLAN_8021Q is not set
446+# CONFIG_DECNET is not set
447+# CONFIG_LLC2 is not set
448+# CONFIG_IPX is not set
449+# CONFIG_ATALK is not set
450+# CONFIG_X25 is not set
451+# CONFIG_LAPB is not set
452+# CONFIG_NET_DIVERT is not set
453+# CONFIG_ECONET is not set
454+# CONFIG_WAN_ROUTER is not set
455+
456+#
457+# QoS and/or fair queueing
458+#
459+# CONFIG_NET_SCHED is not set
460+
461+#
462+# Network testing
463+#
464+# CONFIG_NET_PKTGEN is not set
465+# CONFIG_HAMRADIO is not set
466+# CONFIG_IRDA is not set
467+# CONFIG_BT is not set
468+CONFIG_IEEE80211=m
469+# CONFIG_IEEE80211_DEBUG is not set
470+CONFIG_IEEE80211_CRYPT_WEP=m
471+CONFIG_IEEE80211_CRYPT_CCMP=m
472+# CONFIG_IEEE80211_CRYPT_TKIP is not set
473+
474+#
475+# Device Drivers
476+#
477+
478+#
479+# Generic Driver Options
480+#
481+CONFIG_STANDALONE=y
482+CONFIG_PREVENT_FIRMWARE_BUILD=y
483+CONFIG_FW_LOADER=y
484+# CONFIG_DEBUG_DRIVER is not set
485+
486+#
487+# Connector - unified userspace <-> kernelspace linker
488+#
489+# CONFIG_CONNECTOR is not set
490+
491+#
492+# Memory Technology Devices (MTD)
493+#
494+# CONFIG_MTD is not set
495+
496+#
497+# Parallel port support
498+#
499+# CONFIG_PARPORT is not set
500+
501+#
502+# Plug and Play support
503+#
504+
505+#
506+# Block devices
507+#
508+# CONFIG_BLK_CPQ_DA is not set
509+# CONFIG_BLK_CPQ_CISS_DA is not set
510+# CONFIG_BLK_DEV_DAC960 is not set
511+# CONFIG_BLK_DEV_UMEM is not set
512+# CONFIG_BLK_DEV_COW_COMMON is not set
513+CONFIG_BLK_DEV_LOOP=y
514+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
515+# CONFIG_BLK_DEV_NBD is not set
516+# CONFIG_BLK_DEV_SX8 is not set
517+# CONFIG_BLK_DEV_UB is not set
518+CONFIG_BLK_DEV_RAM=y
519+CONFIG_BLK_DEV_RAM_COUNT=16
520+CONFIG_BLK_DEV_RAM_SIZE=12000
521+CONFIG_BLK_DEV_INITRD=y
522+# CONFIG_CDROM_PKTCDVD is not set
523+# CONFIG_ATA_OVER_ETH is not set
524+CONFIG_ARMCORE_FLASH=y
525+# CONFIG_ARMCORE_NOR is not set
526+CONFIG_ARMCORE_NAND=y
527+
528+#
529+# ATA/ATAPI/MFM/RLL support
530+#
531+CONFIG_IDE=y
532+CONFIG_BLK_DEV_IDE=y
533+
534+#
535+# Please see Documentation/ide.txt for help/info on IDE drives
536+#
537+# CONFIG_BLK_DEV_IDE_SATA is not set
538+CONFIG_BLK_DEV_IDEDISK=y
539+# CONFIG_IDEDISK_MULTI_MODE is not set
540+CONFIG_BLK_DEV_IDECS=y
541+CONFIG_BLK_DEV_IDECD=y
542+# CONFIG_BLK_DEV_IDETAPE is not set
543+# CONFIG_BLK_DEV_IDEFLOPPY is not set
544+CONFIG_BLK_DEV_IDESCSI=y
545+# CONFIG_IDE_TASK_IOCTL is not set
546+
547+#
548+# IDE chipset support/bugfixes
549+#
550+CONFIG_IDE_GENERIC=y
551+# CONFIG_BLK_DEV_IDEPCI is not set
552+# CONFIG_IDE_ARM is not set
553+CONFIG_BLK_DEV_IDE_CM_X270=m
554+# CONFIG_BLK_DEV_IDEDMA is not set
555+# CONFIG_IDEDMA_AUTO is not set
556+# CONFIG_BLK_DEV_HD is not set
557+
558+#
559+# SCSI device support
560+#
561+# CONFIG_RAID_ATTRS is not set
562+CONFIG_SCSI=y
563+# CONFIG_SCSI_PROC_FS is not set
564+
565+#
566+# SCSI support type (disk, tape, CD-ROM)
567+#
568+CONFIG_BLK_DEV_SD=y
569+# CONFIG_CHR_DEV_ST is not set
570+# CONFIG_CHR_DEV_OSST is not set
571+# CONFIG_BLK_DEV_SR is not set
572+# CONFIG_CHR_DEV_SG is not set
573+# CONFIG_CHR_DEV_SCH is not set
574+
575+#
576+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
577+#
578+# CONFIG_SCSI_MULTI_LUN is not set
579+# CONFIG_SCSI_CONSTANTS is not set
580+# CONFIG_SCSI_LOGGING is not set
581+
582+#
583+# SCSI Transport Attributes
584+#
585+# CONFIG_SCSI_SPI_ATTRS is not set
586+# CONFIG_SCSI_FC_ATTRS is not set
587+# CONFIG_SCSI_ISCSI_ATTRS is not set
588+# CONFIG_SCSI_SAS_ATTRS is not set
589+
590+#
591+# SCSI low-level drivers
592+#
593+# CONFIG_ISCSI_TCP is not set
594+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
595+# CONFIG_SCSI_3W_9XXX is not set
596+# CONFIG_SCSI_ACARD is not set
597+# CONFIG_SCSI_AACRAID is not set
598+# CONFIG_SCSI_AIC7XXX is not set
599+# CONFIG_SCSI_AIC7XXX_OLD is not set
600+# CONFIG_SCSI_AIC79XX is not set
601+# CONFIG_SCSI_DPT_I2O is not set
602+# CONFIG_MEGARAID_NEWGEN is not set
603+# CONFIG_MEGARAID_LEGACY is not set
604+# CONFIG_MEGARAID_SAS is not set
605+# CONFIG_SCSI_SATA is not set
606+# CONFIG_SCSI_DMX3191D is not set
607+# CONFIG_SCSI_FUTURE_DOMAIN is not set
608+# CONFIG_SCSI_IPS is not set
609+# CONFIG_SCSI_INITIO is not set
610+# CONFIG_SCSI_INIA100 is not set
611+# CONFIG_SCSI_SYM53C8XX_2 is not set
612+# CONFIG_SCSI_IPR is not set
613+# CONFIG_SCSI_QLOGIC_FC is not set
614+# CONFIG_SCSI_QLOGIC_1280 is not set
615+# CONFIG_SCSI_QLA_FC is not set
616+# CONFIG_SCSI_LPFC is not set
617+# CONFIG_SCSI_DC395x is not set
618+# CONFIG_SCSI_DC390T is not set
619+# CONFIG_SCSI_NSP32 is not set
620+# CONFIG_SCSI_DEBUG is not set
621+
622+#
623+# PCMCIA SCSI adapter support
624+#
625+# CONFIG_PCMCIA_AHA152X is not set
626+# CONFIG_PCMCIA_FDOMAIN is not set
627+# CONFIG_PCMCIA_NINJA_SCSI is not set
628+# CONFIG_PCMCIA_QLOGIC is not set
629+# CONFIG_PCMCIA_SYM53C500 is not set
630+
631+#
632+# Multi-device support (RAID and LVM)
633+#
634+# CONFIG_MD is not set
635+
636+#
637+# Fusion MPT device support
638+#
639+# CONFIG_FUSION is not set
640+# CONFIG_FUSION_SPI is not set
641+# CONFIG_FUSION_FC is not set
642+# CONFIG_FUSION_SAS is not set
643+
644+#
645+# IEEE 1394 (FireWire) support
646+#
647+# CONFIG_IEEE1394 is not set
648+
649+#
650+# I2O device support
651+#
652+# CONFIG_I2O is not set
653+
654+#
655+# Network device support
656+#
657+CONFIG_NETDEVICES=y
658+# CONFIG_DUMMY is not set
659+# CONFIG_BONDING is not set
660+# CONFIG_EQUALIZER is not set
661+# CONFIG_TUN is not set
662+
663+#
664+# ARCnet devices
665+#
666+# CONFIG_ARCNET is not set
667+
668+#
669+# PHY device support
670+#
671+# CONFIG_PHYLIB is not set
672+
673+#
674+# Ethernet (10 or 100Mbit)
675+#
676+CONFIG_NET_ETHERNET=y
677+CONFIG_MII=y
678+# CONFIG_HAPPYMEAL is not set
679+# CONFIG_SUNGEM is not set
680+# CONFIG_CASSINI is not set
681+# CONFIG_NET_VENDOR_3COM is not set
682+# CONFIG_SMC91X is not set
683+CONFIG_DM9000=y
684+CONFIG_DM9000_NOEPROM=y
685+
686+#
687+# Tulip family network device support
688+#
689+# CONFIG_NET_TULIP is not set
690+# CONFIG_HP100 is not set
691+CONFIG_NET_PCI=y
692+# CONFIG_PCNET32 is not set
693+# CONFIG_AMD8111_ETH is not set
694+# CONFIG_ADAPTEC_STARFIRE is not set
695+# CONFIG_B44 is not set
696+# CONFIG_FORCEDETH is not set
697+# CONFIG_DGRS is not set
698+# CONFIG_EEPRO100 is not set
699+# CONFIG_E100 is not set
700+# CONFIG_FEALNX is not set
701+# CONFIG_NATSEMI is not set
702+# CONFIG_NE2K_PCI is not set
703+# CONFIG_8139CP is not set
704+CONFIG_8139TOO=m
705+# CONFIG_8139TOO_PIO is not set
706+# CONFIG_8139TOO_TUNE_TWISTER is not set
707+# CONFIG_8139TOO_8129 is not set
708+# CONFIG_8139_OLD_RX_RESET is not set
709+# CONFIG_SIS900 is not set
710+# CONFIG_EPIC100 is not set
711+# CONFIG_SUNDANCE is not set
712+# CONFIG_TLAN is not set
713+# CONFIG_VIA_RHINE is not set
714+
715+#
716+# Ethernet (1000 Mbit)
717+#
718+# CONFIG_ACENIC is not set
719+# CONFIG_DL2K is not set
720+# CONFIG_E1000 is not set
721+# CONFIG_NS83820 is not set
722+# CONFIG_HAMACHI is not set
723+# CONFIG_YELLOWFIN is not set
724+# CONFIG_R8169 is not set
725+# CONFIG_SIS190 is not set
726+# CONFIG_SKGE is not set
727+# CONFIG_SKY2 is not set
728+# CONFIG_SK98LIN is not set
729+# CONFIG_VIA_VELOCITY is not set
730+# CONFIG_TIGON3 is not set
731+# CONFIG_BNX2 is not set
732+
733+#
734+# Ethernet (10000 Mbit)
735+#
736+# CONFIG_CHELSIO_T1 is not set
737+# CONFIG_IXGB is not set
738+# CONFIG_S2IO is not set
739+
740+#
741+# Token Ring devices
742+#
743+# CONFIG_TR is not set
744+
745+#
746+# Wireless LAN (non-hamradio)
747+#
748+CONFIG_NET_RADIO=y
749+
750+#
751+# Obsolete Wireless cards support (pre-802.11)
752+#
753+# CONFIG_STRIP is not set
754+# CONFIG_PCMCIA_WAVELAN is not set
755+# CONFIG_PCMCIA_NETWAVE is not set
756+
757+#
758+# Wireless 802.11 Frequency Hopping cards support
759+#
760+# CONFIG_PCMCIA_RAYCS is not set
761+
762+#
763+# Wireless 802.11b ISA/PCI cards support
764+#
765+# CONFIG_IPW2100 is not set
766+# CONFIG_IPW2200 is not set
767+# CONFIG_HERMES is not set
768+# CONFIG_ATMEL is not set
769+
770+#
771+# Wireless 802.11b Pcmcia/Cardbus cards support
772+#
773+# CONFIG_AIRO_CS is not set
774+# CONFIG_PCMCIA_WL3501 is not set
775+
776+#
777+# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
778+#
779+# CONFIG_PRISM54 is not set
780+# CONFIG_HOSTAP is not set
781+CONFIG_NET_WIRELESS=y
782+
783+#
784+# PCMCIA network device support
785+#
786+CONFIG_NET_PCMCIA=y
787+# CONFIG_PCMCIA_3C589 is not set
788+# CONFIG_PCMCIA_3C574 is not set
789+# CONFIG_PCMCIA_FMVJ18X is not set
790+CONFIG_PCMCIA_PCNET=y
791+# CONFIG_PCMCIA_NMCLAN is not set
792+# CONFIG_PCMCIA_SMC91C92 is not set
793+# CONFIG_PCMCIA_XIRC2PS is not set
794+# CONFIG_PCMCIA_AXNET is not set
795+
796+#
797+# Wan interfaces
798+#
799+# CONFIG_WAN is not set
800+# CONFIG_FDDI is not set
801+# CONFIG_HIPPI is not set
802+# CONFIG_PPP is not set
803+# CONFIG_SLIP is not set
804+# CONFIG_NET_FC is not set
805+# CONFIG_SHAPER is not set
806+# CONFIG_NETCONSOLE is not set
807+# CONFIG_NETPOLL is not set
808+# CONFIG_NET_POLL_CONTROLLER is not set
809+
810+#
811+# ISDN subsystem
812+#
813+# CONFIG_ISDN is not set
814+
815+#
816+# Input device support
817+#
818+CONFIG_INPUT=y
819+
820+#
821+# Userland interfaces
822+#
823+CONFIG_INPUT_MOUSEDEV=y
824+CONFIG_INPUT_MOUSEDEV_PSAUX=y
825+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
826+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
827+# CONFIG_INPUT_JOYDEV is not set
828+# CONFIG_INPUT_TSDEV is not set
829+CONFIG_INPUT_EVDEV=y
830+# CONFIG_INPUT_EVBUG is not set
831+
832+#
833+# Input Device Drivers
834+#
835+# CONFIG_INPUT_KEYBOARD is not set
836+# CONFIG_INPUT_MOUSE is not set
837+# CONFIG_INPUT_JOYSTICK is not set
838+# CONFIG_INPUT_TOUCHSCREEN is not set
839+# CONFIG_INPUT_MISC is not set
840+
841+#
842+# Hardware I/O ports
843+#
844+CONFIG_SERIO=y
845+# CONFIG_SERIO_SERPORT is not set
846+# CONFIG_SERIO_PCIPS2 is not set
847+CONFIG_SERIO_LIBPS2=y
848+# CONFIG_SERIO_RAW is not set
849+# CONFIG_GAMEPORT is not set
850+
851+#
852+# Character devices
853+#
854+CONFIG_VT=y
855+CONFIG_VT_CONSOLE=y
856+CONFIG_HW_CONSOLE=y
857+# CONFIG_SERIAL_NONSTANDARD is not set
858+
859+#
860+# Serial drivers
861+#
862+CONFIG_SERIAL_8250=y
863+# CONFIG_SERIAL_8250_CONSOLE is not set
864+# CONFIG_SERIAL_8250_CS is not set
865+CONFIG_SERIAL_8250_NR_UARTS=4
866+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
867+# CONFIG_SERIAL_8250_EXTENDED is not set
868+
869+#
870+# Non-8250 serial port support
871+#
872+CONFIG_SERIAL_PXA=y
873+CONFIG_SERIAL_PXA_CONSOLE=y
874+CONFIG_SERIAL_CORE=y
875+CONFIG_SERIAL_CORE_CONSOLE=y
876+# CONFIG_SERIAL_JSM is not set
877+CONFIG_UNIX98_PTYS=y
878+CONFIG_LEGACY_PTYS=y
879+CONFIG_LEGACY_PTY_COUNT=256
880+
881+#
882+# IPMI
883+#
884+# CONFIG_IPMI_HANDLER is not set
885+
886+#
887+# Watchdog Cards
888+#
889+# CONFIG_WATCHDOG is not set
890+# CONFIG_NVRAM is not set
891+# CONFIG_RTC is not set
892+# CONFIG_DTLK is not set
893+# CONFIG_R3964 is not set
894+# CONFIG_APPLICOM is not set
895+
896+#
897+# Ftape, the floppy tape device driver
898+#
899+# CONFIG_DRM is not set
900+
901+#
902+# PCMCIA character devices
903+#
904+# CONFIG_SYNCLINK_CS is not set
905+# CONFIG_CARDMAN_4000 is not set
906+# CONFIG_CARDMAN_4040 is not set
907+# CONFIG_RAW_DRIVER is not set
908+
909+#
910+# TPM devices
911+#
912+# CONFIG_TCG_TPM is not set
913+# CONFIG_TELCLOCK is not set
914+CONFIG_EMV3020_RTC=y
915+
916+#
917+# I2C support
918+#
919+# CONFIG_I2C is not set
920+
921+#
922+# SPI support
923+#
924+# CONFIG_SPI is not set
925+# CONFIG_SPI_MASTER is not set
926+
927+#
928+# Dallas's 1-wire bus
929+#
930+# CONFIG_W1 is not set
931+
932+#
933+# Hardware Monitoring support
934+#
935+# CONFIG_HWMON is not set
936+# CONFIG_HWMON_VID is not set
937+
938+#
939+# Misc devices
940+#
941+
942+#
943+# Multimedia Capabilities Port drivers
944+#
945+CONFIG_UCB1400=m
946+CONFIG_UCB1400_TS=m
947+
948+#
949+# Multimedia devices
950+#
951+# CONFIG_VIDEO_DEV is not set
952+
953+#
954+# Digital Video Broadcasting Devices
955+#
956+# CONFIG_DVB is not set
957+
958+#
959+# Graphics support
960+#
961+CONFIG_FB=y
962+CONFIG_FB_CFB_FILLRECT=y
963+CONFIG_FB_CFB_COPYAREA=y
964+CONFIG_FB_CFB_IMAGEBLIT=y
965+# CONFIG_FB_MACMODES is not set
966+# CONFIG_FB_MODE_HELPERS is not set
967+# CONFIG_FB_TILEBLITTING is not set
968+# CONFIG_FB_CIRRUS is not set
969+# CONFIG_FB_PM2 is not set
970+# CONFIG_FB_CYBER2000 is not set
971+# CONFIG_FB_ASILIANT is not set
972+# CONFIG_FB_IMSTT is not set
973+# CONFIG_FB_S1D13XXX is not set
974+# CONFIG_FB_NVIDIA is not set
975+# CONFIG_FB_RIVA is not set
976+# CONFIG_FB_MATROX is not set
977+# CONFIG_FB_RADEON_OLD is not set
978+# CONFIG_FB_RADEON is not set
979+# CONFIG_FB_ATY128 is not set
980+# CONFIG_FB_ATY is not set
981+# CONFIG_FB_SAVAGE is not set
982+# CONFIG_FB_SIS is not set
983+# CONFIG_FB_NEOMAGIC is not set
984+# CONFIG_FB_KYRO is not set
985+# CONFIG_FB_3DFX is not set
986+# CONFIG_FB_VOODOO1 is not set
987+# CONFIG_FB_TRIDENT is not set
988+CONFIG_FB_PXA=y
989+# CONFIG_FB_PXA_PARAMETERS is not set
990+CONFIG_FB_MBX=m
991+# CONFIG_FB_VIRTUAL is not set
992+
993+#
994+# Console display driver support
995+#
996+# CONFIG_VGA_CONSOLE is not set
997+CONFIG_DUMMY_CONSOLE=y
998+CONFIG_FRAMEBUFFER_CONSOLE=y
999+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1000+# CONFIG_FONTS is not set
1001+CONFIG_FONT_8x8=y
1002+CONFIG_FONT_8x16=y
1003+
1004+#
1005+# Logo configuration
1006+#
1007+CONFIG_LOGO=y
1008+CONFIG_LOGO_LINUX_MONO=y
1009+CONFIG_LOGO_LINUX_VGA16=y
1010+CONFIG_LOGO_LINUX_CLUT224=y
1011+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1012+
1013+#
1014+# Sound
1015+#
1016+CONFIG_SOUND=y
1017+
1018+#
1019+# Advanced Linux Sound Architecture
1020+#
1021+CONFIG_SND=y
1022+CONFIG_SND_TIMER=y
1023+CONFIG_SND_PCM=y
1024+# CONFIG_SND_SEQUENCER is not set
1025+CONFIG_SND_OSSEMUL=y
1026+CONFIG_SND_MIXER_OSS=y
1027+CONFIG_SND_PCM_OSS=y
1028+# CONFIG_SND_DYNAMIC_MINORS is not set
1029+CONFIG_SND_SUPPORT_OLD_API=y
1030+# CONFIG_SND_VERBOSE_PRINTK is not set
1031+# CONFIG_SND_DEBUG is not set
1032+
1033+#
1034+# Generic devices
1035+#
1036+CONFIG_SND_AC97_CODEC=y
1037+CONFIG_SND_AC97_BUS=y
1038+# CONFIG_SND_DUMMY is not set
1039+# CONFIG_SND_MTPAV is not set
1040+# CONFIG_SND_SERIAL_U16550 is not set
1041+# CONFIG_SND_MPU401 is not set
1042+
1043+#
1044+# PCI devices
1045+#
1046+# CONFIG_SND_AD1889 is not set
1047+# CONFIG_SND_ALI5451 is not set
1048+# CONFIG_SND_ATIIXP is not set
1049+# CONFIG_SND_ATIIXP_MODEM is not set
1050+# CONFIG_SND_AU8810 is not set
1051+# CONFIG_SND_AU8820 is not set
1052+# CONFIG_SND_AU8830 is not set
1053+# CONFIG_SND_AZT3328 is not set
1054+# CONFIG_SND_BT87X is not set
1055+# CONFIG_SND_CA0106 is not set
1056+# CONFIG_SND_CMIPCI is not set
1057+# CONFIG_SND_CS4281 is not set
1058+# CONFIG_SND_CS46XX is not set
1059+# CONFIG_SND_EMU10K1 is not set
1060+# CONFIG_SND_EMU10K1X is not set
1061+# CONFIG_SND_ENS1370 is not set
1062+# CONFIG_SND_ENS1371 is not set
1063+# CONFIG_SND_ES1938 is not set
1064+# CONFIG_SND_ES1968 is not set
1065+# CONFIG_SND_FM801 is not set
1066+# CONFIG_SND_HDA_INTEL is not set
1067+# CONFIG_SND_HDSP is not set
1068+# CONFIG_SND_HDSPM is not set
1069+# CONFIG_SND_ICE1712 is not set
1070+# CONFIG_SND_ICE1724 is not set
1071+# CONFIG_SND_INTEL8X0 is not set
1072+# CONFIG_SND_INTEL8X0M is not set
1073+# CONFIG_SND_KORG1212 is not set
1074+# CONFIG_SND_MAESTRO3 is not set
1075+# CONFIG_SND_MIXART is not set
1076+# CONFIG_SND_NM256 is not set
1077+# CONFIG_SND_PCXHR is not set
1078+# CONFIG_SND_RME32 is not set
1079+# CONFIG_SND_RME96 is not set
1080+# CONFIG_SND_RME9652 is not set
1081+# CONFIG_SND_SONICVIBES is not set
1082+# CONFIG_SND_TRIDENT is not set
1083+# CONFIG_SND_VIA82XX is not set
1084+# CONFIG_SND_VIA82XX_MODEM is not set
1085+# CONFIG_SND_VX222 is not set
1086+# CONFIG_SND_YMFPCI is not set
1087+
1088+#
1089+# ALSA ARM devices
1090+#
1091+CONFIG_SND_PXA2XX_PCM=y
1092+CONFIG_SND_PXA2XX_AC97=y
1093+
1094+#
1095+# USB devices
1096+#
1097+# CONFIG_SND_USB_AUDIO is not set
1098+
1099+#
1100+# PCMCIA devices
1101+#
1102+
1103+#
1104+# Open Sound System
1105+#
1106+# CONFIG_SOUND_PRIME is not set
1107+
1108+#
1109+# USB support
1110+#
1111+CONFIG_USB_ARCH_HAS_HCD=y
1112+CONFIG_USB_ARCH_HAS_OHCI=y
1113+CONFIG_USB=y
1114+# CONFIG_USB_DEBUG is not set
1115+
1116+#
1117+# Miscellaneous USB options
1118+#
1119+CONFIG_USB_DEVICEFS=y
1120+# CONFIG_USB_BANDWIDTH is not set
1121+# CONFIG_USB_DYNAMIC_MINORS is not set
1122+# CONFIG_USB_SUSPEND is not set
1123+# CONFIG_USB_OTG is not set
1124+
1125+#
1126+# USB Host Controller Drivers
1127+#
1128+# CONFIG_USB_EHCI_HCD is not set
1129+# CONFIG_USB_ISP116X_HCD is not set
1130+CONFIG_USB_OHCI_HCD=y
1131+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
1132+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1133+# CONFIG_USB_UHCI_HCD is not set
1134+# CONFIG_USB_SL811_HCD is not set
1135+
1136+#
1137+# USB Device Class drivers
1138+#
1139+# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
1140+# CONFIG_USB_ACM is not set
1141+# CONFIG_USB_PRINTER is not set
1142+
1143+#
1144+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1145+#
1146+
1147+#
1148+# may also be needed; see USB_STORAGE Help for more information
1149+#
1150+CONFIG_USB_STORAGE=y
1151+# CONFIG_USB_STORAGE_DEBUG is not set
1152+# CONFIG_USB_STORAGE_DATAFAB is not set
1153+# CONFIG_USB_STORAGE_FREECOM is not set
1154+# CONFIG_USB_STORAGE_ISD200 is not set
1155+# CONFIG_USB_STORAGE_DPCM is not set
1156+# CONFIG_USB_STORAGE_USBAT is not set
1157+# CONFIG_USB_STORAGE_SDDR09 is not set
1158+# CONFIG_USB_STORAGE_SDDR55 is not set
1159+# CONFIG_USB_STORAGE_JUMPSHOT is not set
1160+# CONFIG_USB_STORAGE_ALAUDA is not set
1161+# CONFIG_USB_LIBUSUAL is not set
1162+
1163+#
1164+# USB Input Devices
1165+#
1166+CONFIG_USB_HID=y
1167+CONFIG_USB_HIDINPUT=y
1168+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1169+# CONFIG_HID_FF is not set
1170+# CONFIG_USB_HIDDEV is not set
1171+# CONFIG_USB_AIPTEK is not set
1172+# CONFIG_USB_WACOM is not set
1173+# CONFIG_USB_ACECAD is not set
1174+# CONFIG_USB_KBTAB is not set
1175+# CONFIG_USB_POWERMATE is not set
1176+# CONFIG_USB_MTOUCH is not set
1177+# CONFIG_USB_ITMTOUCH is not set
1178+# CONFIG_USB_EGALAX is not set
1179+# CONFIG_USB_YEALINK is not set
1180+# CONFIG_USB_XPAD is not set
1181+# CONFIG_USB_ATI_REMOTE is not set
1182+# CONFIG_USB_ATI_REMOTE2 is not set
1183+# CONFIG_USB_KEYSPAN_REMOTE is not set
1184+# CONFIG_USB_APPLETOUCH is not set
1185+
1186+#
1187+# USB Imaging devices
1188+#
1189+# CONFIG_USB_MDC800 is not set
1190+# CONFIG_USB_MICROTEK is not set
1191+
1192+#
1193+# USB Multimedia devices
1194+#
1195+# CONFIG_USB_DABUSB is not set
1196+
1197+#
1198+# Video4Linux support is needed for USB Multimedia device support
1199+#
1200+
1201+#
1202+# USB Network Adapters
1203+#
1204+# CONFIG_USB_CATC is not set
1205+# CONFIG_USB_KAWETH is not set
1206+# CONFIG_USB_PEGASUS is not set
1207+# CONFIG_USB_RTL8150 is not set
1208+# CONFIG_USB_USBNET is not set
1209+# CONFIG_USB_ZD1201 is not set
1210+CONFIG_USB_MON=y
1211+
1212+#
1213+# USB port drivers
1214+#
1215+
1216+#
1217+# USB Serial Converter support
1218+#
1219+# CONFIG_USB_SERIAL is not set
1220+
1221+#
1222+# USB Miscellaneous drivers
1223+#
1224+# CONFIG_USB_EMI62 is not set
1225+# CONFIG_USB_EMI26 is not set
1226+# CONFIG_USB_AUERSWALD is not set
1227+# CONFIG_USB_RIO500 is not set
1228+# CONFIG_USB_LEGOTOWER is not set
1229+# CONFIG_USB_LCD is not set
1230+# CONFIG_USB_LED is not set
1231+# CONFIG_USB_CYTHERM is not set
1232+# CONFIG_USB_PHIDGETKIT is not set
1233+# CONFIG_USB_PHIDGETSERVO is not set
1234+# CONFIG_USB_IDMOUSE is not set
1235+# CONFIG_USB_LD is not set
1236+# CONFIG_USB_TEST is not set
1237+
1238+#
1239+# USB DSL modem support
1240+#
1241+
1242+#
1243+# USB Gadget Support
1244+#
1245+# CONFIG_USB_GADGET is not set
1246+
1247+#
1248+# MMC/SD Card support
1249+#
1250+# CONFIG_MMC is not set
1251+
1252+#
1253+# File systems
1254+#
1255+CONFIG_EXT2_FS=y
1256+# CONFIG_EXT2_FS_XATTR is not set
1257+# CONFIG_EXT2_FS_XIP is not set
1258+CONFIG_EXT3_FS=y
1259+CONFIG_EXT3_FS_XATTR=y
1260+# CONFIG_EXT3_FS_POSIX_ACL is not set
1261+# CONFIG_EXT3_FS_SECURITY is not set
1262+CONFIG_JBD=y
1263+# CONFIG_JBD_DEBUG is not set
1264+CONFIG_FS_MBCACHE=y
1265+# CONFIG_REISERFS_FS is not set
1266+# CONFIG_JFS_FS is not set
1267+# CONFIG_FS_POSIX_ACL is not set
1268+# CONFIG_XFS_FS is not set
1269+# CONFIG_OCFS2_FS is not set
1270+# CONFIG_MINIX_FS is not set
1271+# CONFIG_ROMFS_FS is not set
1272+CONFIG_INOTIFY=y
1273+# CONFIG_QUOTA is not set
1274+CONFIG_DNOTIFY=y
1275+# CONFIG_AUTOFS_FS is not set
1276+# CONFIG_AUTOFS4_FS is not set
1277+# CONFIG_FUSE_FS is not set
1278+
1279+#
1280+# CD-ROM/DVD Filesystems
1281+#
1282+# CONFIG_ISO9660_FS is not set
1283+# CONFIG_UDF_FS is not set
1284+
1285+#
1286+# DOS/FAT/NT Filesystems
1287+#
1288+CONFIG_FAT_FS=y
1289+CONFIG_MSDOS_FS=y
1290+CONFIG_VFAT_FS=y
1291+CONFIG_FAT_DEFAULT_CODEPAGE=437
1292+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1293+# CONFIG_NTFS_FS is not set
1294+
1295+#
1296+# Pseudo filesystems
1297+#
1298+CONFIG_PROC_FS=y
1299+CONFIG_SYSFS=y
1300+CONFIG_TMPFS=y
1301+# CONFIG_HUGETLB_PAGE is not set
1302+CONFIG_RAMFS=y
1303+# CONFIG_RELAYFS_FS is not set
1304+# CONFIG_CONFIGFS_FS is not set
1305+
1306+#
1307+# Miscellaneous filesystems
1308+#
1309+# CONFIG_ADFS_FS is not set
1310+# CONFIG_AFFS_FS is not set
1311+# CONFIG_HFS_FS is not set
1312+# CONFIG_HFSPLUS_FS is not set
1313+# CONFIG_BEFS_FS is not set
1314+# CONFIG_BFS_FS is not set
1315+# CONFIG_EFS_FS is not set
1316+# CONFIG_CRAMFS is not set
1317+# CONFIG_VXFS_FS is not set
1318+# CONFIG_HPFS_FS is not set
1319+# CONFIG_QNX4FS_FS is not set
1320+# CONFIG_SYSV_FS is not set
1321+# CONFIG_UFS_FS is not set
1322+
1323+#
1324+# Network File Systems
1325+#
1326+CONFIG_NFS_FS=y
1327+CONFIG_NFS_V3=y
1328+# CONFIG_NFS_V3_ACL is not set
1329+# CONFIG_NFS_V4 is not set
1330+# CONFIG_NFS_DIRECTIO is not set
1331+# CONFIG_NFSD is not set
1332+CONFIG_ROOT_NFS=y
1333+CONFIG_LOCKD=y
1334+CONFIG_LOCKD_V4=y
1335+CONFIG_NFS_COMMON=y
1336+CONFIG_SUNRPC=y
1337+# CONFIG_RPCSEC_GSS_KRB5 is not set
1338+# CONFIG_RPCSEC_GSS_SPKM3 is not set
1339+CONFIG_SMB_FS=y
1340+# CONFIG_SMB_NLS_DEFAULT is not set
1341+# CONFIG_CIFS is not set
1342+# CONFIG_NCP_FS is not set
1343+# CONFIG_CODA_FS is not set
1344+# CONFIG_AFS_FS is not set
1345+# CONFIG_9P_FS is not set
1346+
1347+#
1348+# Partition Types
1349+#
1350+# CONFIG_PARTITION_ADVANCED is not set
1351+CONFIG_MSDOS_PARTITION=y
1352+
1353+#
1354+# Native Language Support
1355+#
1356+CONFIG_NLS=y
1357+CONFIG_NLS_DEFAULT="iso8859-1"
1358+CONFIG_NLS_CODEPAGE_437=y
1359+# CONFIG_NLS_CODEPAGE_737 is not set
1360+# CONFIG_NLS_CODEPAGE_775 is not set
1361+# CONFIG_NLS_CODEPAGE_850 is not set
1362+# CONFIG_NLS_CODEPAGE_852 is not set
1363+# CONFIG_NLS_CODEPAGE_855 is not set
1364+# CONFIG_NLS_CODEPAGE_857 is not set
1365+# CONFIG_NLS_CODEPAGE_860 is not set
1366+# CONFIG_NLS_CODEPAGE_861 is not set
1367+# CONFIG_NLS_CODEPAGE_862 is not set
1368+# CONFIG_NLS_CODEPAGE_863 is not set
1369+# CONFIG_NLS_CODEPAGE_864 is not set
1370+# CONFIG_NLS_CODEPAGE_865 is not set
1371+# CONFIG_NLS_CODEPAGE_866 is not set
1372+# CONFIG_NLS_CODEPAGE_869 is not set
1373+# CONFIG_NLS_CODEPAGE_936 is not set
1374+# CONFIG_NLS_CODEPAGE_950 is not set
1375+# CONFIG_NLS_CODEPAGE_932 is not set
1376+# CONFIG_NLS_CODEPAGE_949 is not set
1377+# CONFIG_NLS_CODEPAGE_874 is not set
1378+# CONFIG_NLS_ISO8859_8 is not set
1379+# CONFIG_NLS_CODEPAGE_1250 is not set
1380+# CONFIG_NLS_CODEPAGE_1251 is not set
1381+# CONFIG_NLS_ASCII is not set
1382+CONFIG_NLS_ISO8859_1=y
1383+# CONFIG_NLS_ISO8859_2 is not set
1384+# CONFIG_NLS_ISO8859_3 is not set
1385+# CONFIG_NLS_ISO8859_4 is not set
1386+# CONFIG_NLS_ISO8859_5 is not set
1387+# CONFIG_NLS_ISO8859_6 is not set
1388+# CONFIG_NLS_ISO8859_7 is not set
1389+# CONFIG_NLS_ISO8859_9 is not set
1390+# CONFIG_NLS_ISO8859_13 is not set
1391+# CONFIG_NLS_ISO8859_14 is not set
1392+# CONFIG_NLS_ISO8859_15 is not set
1393+# CONFIG_NLS_KOI8_R is not set
1394+# CONFIG_NLS_KOI8_U is not set
1395+# CONFIG_NLS_UTF8 is not set
1396+
1397+#
1398+# Profiling support
1399+#
1400+# CONFIG_PROFILING is not set
1401+
1402+#
1403+# Kernel hacking
1404+#
1405+# CONFIG_PRINTK_TIME is not set
1406+CONFIG_MAGIC_SYSRQ=y
1407+CONFIG_DEBUG_KERNEL=y
1408+CONFIG_LOG_BUF_SHIFT=17
1409+# CONFIG_DETECT_SOFTLOCKUP is not set
1410+# CONFIG_SCHEDSTATS is not set
1411+# CONFIG_DEBUG_SLAB is not set
1412+# CONFIG_DEBUG_MUTEXES is not set
1413+# CONFIG_DEBUG_SPINLOCK is not set
1414+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1415+# CONFIG_DEBUG_KOBJECT is not set
1416+# CONFIG_DEBUG_BUGVERBOSE is not set
1417+CONFIG_DEBUG_INFO=y
1418+# CONFIG_DEBUG_FS is not set
1419+# CONFIG_DEBUG_VM is not set
1420+CONFIG_FRAME_POINTER=y
1421+CONFIG_FORCED_INLINING=y
1422+# CONFIG_RCU_TORTURE_TEST is not set
1423+CONFIG_DEBUG_USER=y
1424+# CONFIG_DEBUG_WAITQ is not set
1425+CONFIG_DEBUG_ERRORS=y
1426+CONFIG_DEBUG_LL=y
1427+# CONFIG_DEBUG_ICEDCC is not set
1428+
1429+#
1430+# Security options
1431+#
1432+# CONFIG_KEYS is not set
1433+# CONFIG_SECURITY is not set
1434+
1435+#
1436+# Cryptographic options
1437+#
1438+CONFIG_CRYPTO=y
1439+# CONFIG_CRYPTO_HMAC is not set
1440+# CONFIG_CRYPTO_NULL is not set
1441+# CONFIG_CRYPTO_MD4 is not set
1442+# CONFIG_CRYPTO_MD5 is not set
1443+# CONFIG_CRYPTO_SHA1 is not set
1444+# CONFIG_CRYPTO_SHA256 is not set
1445+# CONFIG_CRYPTO_SHA512 is not set
1446+# CONFIG_CRYPTO_WP512 is not set
1447+# CONFIG_CRYPTO_TGR192 is not set
1448+# CONFIG_CRYPTO_DES is not set
1449+# CONFIG_CRYPTO_BLOWFISH is not set
1450+# CONFIG_CRYPTO_TWOFISH is not set
1451+# CONFIG_CRYPTO_SERPENT is not set
1452+CONFIG_CRYPTO_AES=m
1453+# CONFIG_CRYPTO_CAST5 is not set
1454+# CONFIG_CRYPTO_CAST6 is not set
1455+# CONFIG_CRYPTO_TEA is not set
1456+CONFIG_CRYPTO_ARC4=m
1457+# CONFIG_CRYPTO_KHAZAD is not set
1458+# CONFIG_CRYPTO_ANUBIS is not set
1459+# CONFIG_CRYPTO_DEFLATE is not set
1460+# CONFIG_CRYPTO_MICHAEL_MIC is not set
1461+# CONFIG_CRYPTO_CRC32C is not set
1462+# CONFIG_CRYPTO_TEST is not set
1463+
1464+#
1465+# Hardware crypto devices
1466+#
1467+
1468+#
1469+# Library routines
1470+#
1471+# CONFIG_CRC_CCITT is not set
1472+# CONFIG_CRC16 is not set
1473+CONFIG_CRC32=y
1474+# CONFIG_LIBCRC32C is not set
1475diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
1476index c4923fa..4ff2a62 100644
1477--- a/arch/arm/kernel/bios32.c
1478+++ b/arch/arm/kernel/bios32.c
1479@@ -280,6 +280,34 @@ static void __devinit pci_fixup_cy82c693
1480 }
1481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
1482
1483+static void __init pci_fixup_it8152(struct pci_dev *dev)
1484+{
1485+ int i;
1486+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
1487+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1488+ dev->resource[i].start = 0;
1489+ dev->resource[i].end = 0;
1490+ dev->resource[i].flags = 0;
1491+ }
1492+ }
1493+ if (dev->class == 0x68000) {
1494+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1495+ dev->resource[i].start = 0;
1496+ dev->resource[i].end = 0;
1497+ dev->resource[i].flags = 0;
1498+ }
1499+ }
1500+ if (dev->class == 0x80103) {
1501+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1502+ dev->resource[i].start = 0;
1503+ dev->resource[i].end = 0;
1504+ dev->resource[i].flags = 0;
1505+ }
1506+ }
1507+}
1508+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8152, pci_fixup_it8152);
1509+
1510+
1511 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
1512 {
1513 if (debug_pci)
1514@@ -293,9 +321,11 @@ void __devinit pcibios_update_irq(struct
1515 */
1516 static inline int pdev_bad_for_parity(struct pci_dev *dev)
1517 {
1518- return (dev->vendor == PCI_VENDOR_ID_INTERG &&
1519- (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
1520- dev->device == PCI_DEVICE_ID_INTERG_2010));
1521+ return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
1522+ (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
1523+ dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
1524+ (dev->vendor == PCI_VENDOR_ID_ITE &&
1525+ dev->device == PCI_DEVICE_ID_ITE_IT8152));
1526 }
1527
1528 /*
1529diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
1530index 2b254e8..310ccf5 100644
1531--- a/arch/arm/kernel/vmlinux.lds.S
1532+++ b/arch/arm/kernel/vmlinux.lds.S
1533@@ -175,5 +175,5 @@ #endif
1534 * If you have to comment these two assert statements out, your
1535 * binutils is too old (for other reasons as well)
1536 */
1537-ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
1538-ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
1539+/* ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support") */
1540+/* ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined") */
1541diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
1542index c1d77f5..c240211 100644
1543--- a/arch/arm/mach-pxa/Kconfig
1544+++ b/arch/arm/mach-pxa/Kconfig
1545@@ -15,6 +15,11 @@ config MACH_MAINSTONE
1546 select PXA27x
1547 select IWMMXT
1548
1549+config MACH_ARMCORE
1550+ bool "CompuLab CM-X270 modules"
1551+ select PXA27x
1552+ select IWMMXT
1553+
1554 config ARCH_PXA_IDP
1555 bool "Accelent Xscale IDP"
1556 select PXA25x
1557@@ -50,6 +55,25 @@ endchoice
1558
1559 endif
1560
1561+if MACH_ARMCORE
1562+choice
1563+ prompt "Select CM-X270 base board"
1564+ config ARMCORE_ATXBASE
1565+ bool "ATX-X270 base board"
1566+ config ARMCORE_SB270
1567+ bool "SB-270 base board"
1568+endchoice
1569+
1570+choice
1571+ prompt "Select CM-X270 revision"
1572+ config ARMCORE_REV12
1573+ bool "CM-X270 revision 1.2"
1574+ config ARMCORE_REV11
1575+ bool "CM-X270 revision 1.1"
1576+endchoice
1577+
1578+endif
1579+
1580 endmenu
1581
1582 config MACH_POODLE
1583diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
1584index 32526a0..d78d061 100644
1585--- a/arch/arm/mach-pxa/Makefile
1586+++ b/arch/arm/mach-pxa/Makefile
1587@@ -16,12 +16,14 @@ obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o
1588 obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
1589 obj-$(CONFIG_MACH_POODLE) += poodle.o
1590 obj-$(CONFIG_MACH_TOSA) += tosa.o
1591+obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
1592
1593 # Support for blinky lights
1594 led-y := leds.o
1595 led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
1596 led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
1597 led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
1598+led-$(CONFIG_MACH_ARMCORE) += leds-cm-x270.o
1599
1600 obj-$(CONFIG_LEDS) += $(led-y)
1601
1602@@ -32,3 +34,10 @@ obj-$(CONFIG_PXA_SSP) += ssp.o
1603 ifeq ($(CONFIG_PXA27x),y)
1604 obj-$(CONFIG_PM) += standby.o
1605 endif
1606+
1607+# PCI support on CM-X270
1608+obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
1609+
1610+ifeq ($(CONFIG_PCI),y)
1611+obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
1612+endif
1613diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
1614new file mode 100644
1615index 0000000..73243d3
1616--- /dev/null
1617+++ b/arch/arm/mach-pxa/cm-x270-pci.c
1618@@ -0,0 +1,152 @@
1619+/*
1620+ * arch/arm/kernel/cm-x270-pci.c
1621+ *
1622+ * PCI bios-type initialisation for PCI machines
1623+ *
1624+ * Bits taken from various places.
1625+ *
1626+ * Copyright (C) 2006 Compulab, Ltd.
1627+ *
1628+ * This program is free software; you can redistribute it and/or modify
1629+ * it under the terms of the GNU General Public License version 2 as
1630+ * published by the Free Software Foundation.
1631+ */
1632+
1633+#include <linux/kernel.h>
1634+#include <linux/pci.h>
1635+#include <linux/init.h>
1636+#include <linux/device.h>
1637+#include <linux/platform_device.h>
1638+
1639+#include <asm/irq.h>
1640+#include <asm/mach/pci.h>
1641+#include <asm/arch/cm-x270.h>
1642+#include <asm/mach-types.h>
1643+
1644+#include <asm/hardware/it8152.h>
1645+
1646+unsigned long armcore_pcibios_min_mem = 0x10000000;
1647+unsigned long armcore_pcibios_min_io = CMX270_IT8152_VIRT + 0x03e00000 + 0x120000;
1648+unsigned long it8152_base_address = CMX270_IT8152_VIRT;
1649+
1650+/* these symbols needed for CardBus driver (yenta_socket) */
1651+EXPORT_SYMBOL(armcore_pcibios_min_io);
1652+EXPORT_SYMBOL(armcore_pcibios_min_mem);
1653+
1654+static u8 __init cmx270_pci_swizzle(struct pci_dev *dev, u8 *pin)
1655+{
1656+ return PCI_SLOT(dev->devfn);
1657+}
1658+
1659+/* Platform specific IRQ mapping */
1660+static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
1661+{
1662+ if((dev->vendor==0x1283) && (dev->device==0x8152) &&
1663+ ((dev->class >> 8)==0x801)) return(CDMA_INT);
1664+ if((dev->vendor==0x1283) && (dev->device==0x0801) &&
1665+ ((dev->class >> 8)==0x401)) return(AUDIO_INT);
1666+ if((dev->vendor==0x1283) && (dev->device==0x8152) &&
1667+ ((dev->class >> 8)==0xc03)) return(USB_INT);
1668+
1669+ /* ATXBASE PCI slot */
1670+ if ( slot == 7 )
1671+ return(PCI_INTA);
1672+
1673+ /* ATXBASE/SB-X270 CardBus */
1674+ if ( (slot == 8) || (slot == 0) )
1675+ return(PCI_INTB);
1676+
1677+ /* ATXBASE ETH */
1678+ if ( slot == 9 )
1679+ return(PCI_INTA);
1680+
1681+ /* ARMCore onboard ETH */
1682+ if ( slot == 15 )
1683+ return(PCI_INTC);
1684+
1685+ /* ARMBase ETH */
1686+ if ( slot == 16 )
1687+ return(PCI_INTA);
1688+
1689+ /* PC104+ interrupt routing */
1690+ if ( (slot == 17) || (slot == 19) )
1691+ return(PCI_INTA);
1692+ if ( (slot == 18) || (slot == 20) )
1693+ return(PCI_INTB);
1694+
1695+ return(0);
1696+}
1697+
1698+extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
1699+extern struct pci_bus * it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
1700+
1701+static struct pci_bus* __init cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
1702+{
1703+ IT8152_PCI_CFG_ADDR = 0x800;
1704+ if(IT8152_PCI_CFG_DATA == 0x81521283) {
1705+ printk("PCI Bridge found.\n");
1706+
1707+ IT8152_GPIO_GPLR=0x20;
1708+
1709+/*********** CardBus Controller on ATXBASE configuration ********/
1710+ IT8152_PCI_CFG_ADDR = 0x4000;
1711+ if(IT8152_PCI_CFG_DATA == 0xAC51104C) {
1712+ unsigned int temp;
1713+ printk("CardBus Bridge found.\n");
1714+
1715+ // Configure socket 0
1716+ IT8152_PCI_CFG_ADDR = 0x408C;
1717+ IT8152_PCI_CFG_DATA = 0x1022;
1718+
1719+ IT8152_PCI_CFG_ADDR = 0x4080;
1720+ IT8152_PCI_CFG_DATA = 0x3844d060;
1721+
1722+ IT8152_PCI_CFG_ADDR = 0x4090;
1723+ temp = IT8152_PCI_CFG_DATA;
1724+ temp = temp & 0xFFFF;
1725+ temp = temp | (0x60440000);
1726+ IT8152_PCI_CFG_ADDR = 0x4090;
1727+ IT8152_PCI_CFG_DATA = temp;
1728+
1729+ IT8152_PCI_CFG_ADDR = 0x4018;
1730+ IT8152_PCI_CFG_DATA = 0xb0000000;
1731+
1732+ // Configure socket 1
1733+ IT8152_PCI_CFG_ADDR = 0x418C;
1734+ IT8152_PCI_CFG_DATA = 0x1022;
1735+
1736+ IT8152_PCI_CFG_ADDR = 0x4180;
1737+ IT8152_PCI_CFG_DATA = 0x3844d060;
1738+
1739+ IT8152_PCI_CFG_ADDR = 0x4190;
1740+ temp = IT8152_PCI_CFG_DATA;
1741+ temp = temp & 0xFFFF;
1742+ temp = temp | (0x60440000);
1743+ IT8152_PCI_CFG_ADDR = 0x4190;
1744+ IT8152_PCI_CFG_DATA = temp;
1745+
1746+ IT8152_PCI_CFG_ADDR = 0x4118;
1747+ IT8152_PCI_CFG_DATA = 0xb0000000;
1748+ }
1749+/*********** End of CardBus controller configuration **************/
1750+ }
1751+ return it8152_pci_scan_bus(nr, sys);
1752+}
1753+
1754+static struct hw_pci cmx270_pci __initdata = {
1755+ .swizzle = cmx270_pci_swizzle,
1756+ .map_irq = cmx270_pci_map_irq,
1757+ .nr_controllers = 1,
1758+ .setup = it8152_pci_setup,
1759+ .scan = cmx270_pci_scan_bus,
1760+};
1761+
1762+static int __init cmx270_init_pci(void)
1763+{
1764+ if (machine_is_armcore()) {
1765+ pci_common_init(&cmx270_pci);
1766+ }
1767+ return 0;
1768+}
1769+
1770+subsys_initcall(cmx270_init_pci);
1771diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
1772new file mode 100644
1773index 0000000..6157135
1774--- /dev/null
1775+++ b/arch/arm/mach-pxa/cm-x270.c
1776@@ -0,0 +1,887 @@
1777+/*
1778+ * linux/arch/arm/mach-pxa/cm-x270.c
1779+ *
1780+ * Copyright (C) 2006 CompuLab, Ltd.
1781+ *
1782+ * This program is free software; you can redistribute it and/or modify
1783+ * it under the terms of the GNU General Public License version 2 as
1784+ * published by the Free Software Foundation.
1785+ */
1786+
1787+#include <linux/pm.h>
1788+#include <linux/fb.h>
1789+#include <linux/platform_device.h>
1790+#include <linux/sysdev.h>
1791+#include <linux/dm9000.h>
1792+#include <linux/serial_8250.h>
1793+
1794+#include <asm/types.h>
1795+#include <asm/setup.h>
1796+#include <asm/memory.h>
1797+#include <asm/mach-types.h>
1798+#include <asm/hardware.h>
1799+#include <asm/irq.h>
1800+#include <asm/io.h>
1801+#include <asm/delay.h>
1802+
1803+#include <asm/mach/arch.h>
1804+#include <asm/mach/map.h>
1805+#include <asm/mach/irq.h>
1806+
1807+#include <asm/arch/pxa-regs.h>
1808+#include <asm/arch/irq.h>
1809+#include <asm/arch/pxafb.h>
1810+#include <asm/arch/marathonfb.h>
1811+#include <asm/arch/ohci.h>
1812+#include <asm/arch/pxafbsetup.h>
1813+#include <asm/arch/bitfield.h>
1814+#include <asm/arch/cm-x270.h>
1815+
1816+#include <asm/hardware/it8152.h>
1817+
1818+#include "generic.h"
1819+
1820+#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22))
1821+#define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
1822+
1823+static struct resource cmx270_dm9k_resource[] = {
1824+ [0] = {
1825+ .start = DM9000_PHYS_BASE,
1826+ .end = DM9000_PHYS_BASE + 4,
1827+ .flags = IORESOURCE_MEM,
1828+ },
1829+ [1] = {
1830+ .start = DM9000_PHYS_BASE + 8,
1831+ .end = DM9000_PHYS_BASE + 8 + 500,
1832+ .flags = IORESOURCE_MEM,
1833+ },
1834+ [2] = {
1835+ .start = CMX270_ETHIRQ,
1836+ .end = CMX270_ETHIRQ,
1837+ .flags = IORESOURCE_IRQ,
1838+ }
1839+};
1840+
1841+/* for the moment we limit ourselves to 32bit IO until some
1842+ * better IO routines can be written and tested
1843+ */
1844+static struct dm9000_plat_data cmx270_dm9k_platdata = {
1845+ .flags = DM9000_PLATF_32BITONLY,
1846+};
1847+
1848+/* Ethernet device */
1849+static struct platform_device cmx270_device_dm9k = {
1850+ .name = "dm9000",
1851+ .id = 0,
1852+ .num_resources = ARRAY_SIZE(cmx270_dm9k_resource),
1853+ .resource = cmx270_dm9k_resource,
1854+ .dev = {
1855+ .platform_data = &cmx270_dm9k_platdata,
1856+ }
1857+};
1858+
1859+/* audio device */
1860+static struct platform_device cmx270_audio_device = {
1861+ .name = "pxa2xx-ac97",
1862+ .id = -1,
1863+};
1864+
1865+/* touchscreen controller */
1866+static struct platform_device cmx270_ts_device = {
1867+ .name = "ucb1x00",
1868+ .id = -1,
1869+};
1870+
1871+/* RTC */
1872+static struct resource cmx270_v3020_resource[] = {
1873+ [0] = {
1874+ .start = RTC_PHYS_BASE,
1875+ .end = RTC_PHYS_BASE + 4,
1876+ .flags = IORESOURCE_MEM,
1877+ },
1878+};
1879+
1880+static struct platform_device cmx270_rtc_device = {
1881+ .name = "emv3020-rtc",
1882+ .num_resources = ARRAY_SIZE(cmx270_v3020_resource),
1883+ .resource = cmx270_v3020_resource,
1884+ .id = -1,
1885+};
1886+
1887+/* UART on the ITE8152 chip */
1888+#ifdef CONFIG_PCI
1889+static struct plat_serial8250_port ite_uart_port[] = {
1890+ {
1891+ .irq = IRQ_ITESER, /* interrupt number */
1892+ .uartclk = 115200 * 16, /* UART clock rate */
1893+ .iotype = UPIO_MEM, /* UPIO_* */
1894+ .flags = UPF_BOOT_AUTOCONF,
1895+ },
1896+ {}
1897+};
1898+
1899+static struct platform_device iteuart_device = {
1900+ .name = "serial8250",
1901+ .id = PLAT8250_DEV_PLATFORM,
1902+ .dev = {
1903+ .platform_data = ite_uart_port,
1904+ },
1905+};
1906+#endif
1907+
1908+/* 2700G graphics */
1909+static u64 fb_dma_mask = ~(u64)0;
1910+
1911+static struct resource cmx270_2700G_resource[] = {
1912+ /* frame buffer memory including ODFB and External SDRAM */
1913+ [0] = {
1914+ .start = MARATHON_PHYS,
1915+ .end = MARATHON_PHYS + 0x02000000,
1916+ .flags = IORESOURCE_MEM,
1917+ },
1918+ /* Marathon registers */
1919+ [1] = {
1920+ .start = MARATHON_PHYS + 0x03fe0000,
1921+ .end = MARATHON_PHYS + 0x03ffffff,
1922+ .flags = IORESOURCE_MEM,
1923+ },
1924+};
1925+
1926+static unsigned long save_lcd_regs[10];
1927+
1928+#define LB_TROTTLE_OFF (PXA_CS1_PHYS | (1 << 25))
1929+#define LB_TROTTLE_MAX (PXA_CS1_PHYS | (1 << 25) | (1 << 22))
1930+static int cmx270_marathon_probe(struct fb_info *fb)
1931+{
1932+ volatile unsigned long *cpld;
1933+
1934+ cpld = (volatile unsigned long*)ioremap(LB_TROTTLE_OFF, 4);
1935+
1936+ if ( !cpld ) {
1937+ return -ENODEV;
1938+ }
1939+ *cpld = 0;
1940+ iounmap((void*)cpld);
1941+
1942+
1943+ /* save PXA-270 pin settings before enabling 2700G */
1944+ save_lcd_regs[0] = GPDR1;
1945+ save_lcd_regs[1] = GPDR2;
1946+ save_lcd_regs[2] = GAFR1_U;
1947+ save_lcd_regs[3] = GAFR2_L;
1948+ save_lcd_regs[4] = GAFR2_U;
1949+
1950+ /* Disable PXA-270 on-chip controller driving pins */
1951+ GPDR1 &= ~(0xfc000000);
1952+ GPDR2 &= ~(0x00c03fff);
1953+ GAFR1_U &= ~(0xfff00000);
1954+ GAFR2_L &= ~(0x0fffffff);
1955+ GAFR2_U &= ~(0x0000f000);
1956+ return 0;
1957+}
1958+
1959+static int cmx270_marathon_remove(struct fb_info *fb)
1960+{
1961+ volatile unsigned long *cpld;
1962+
1963+ cpld = (volatile unsigned long*)ioremap(LB_TROTTLE_MAX, 4);
1964+
1965+ if ( !cpld ) {
1966+ return -ENODEV;
1967+ }
1968+ *cpld = 0;
1969+ iounmap((void*)cpld);
1970+
1971+ GPDR1 = save_lcd_regs[0];
1972+ GPDR2 = save_lcd_regs[1];
1973+ GAFR1_U = save_lcd_regs[2];
1974+ GAFR2_L = save_lcd_regs[3];
1975+ GAFR2_U = save_lcd_regs[4];
1976+ return 0;
1977+}
1978+
1979+static struct mbxfb_platform_data cmx270_2700G_data = {
1980+ .xres = {
1981+ .min = 240,
1982+ .max = 1200,
1983+ .defval = 640,
1984+ },
1985+ .yres = {
1986+ .min = 240,
1987+ .max = 1200,
1988+ .defval = 480,
1989+ },
1990+ .bpp = {
1991+ .min = 16,
1992+ .max = 32,
1993+ .defval = 16,
1994+ },
1995+ .memsize = 8*1024*1024,
1996+ .probe = cmx270_marathon_probe,
1997+ .remove = cmx270_marathon_remove,
1998+};
1999+
2000+static struct platform_device cmx270_2700G = {
2001+ .name = "mbx-fb",
2002+ .dev = {
2003+ .platform_data = &cmx270_2700G_data,
2004+ .dma_mask = &fb_dma_mask,
2005+ .coherent_dma_mask = 0xffffffff,
2006+ },
2007+ .num_resources = ARRAY_SIZE(cmx270_2700G_resource),
2008+ .resource = cmx270_2700G_resource,
2009+ .id = -1,
2010+};
2011+
2012+/* platform devices */
2013+static struct platform_device *platform_devices[] __initdata = {
2014+ &cmx270_device_dm9k,
2015+ &cmx270_audio_device,
2016+ &cmx270_ts_device,
2017+ &cmx270_rtc_device,
2018+ &cmx270_2700G,
2019+#ifdef CONFIG_PCI
2020+ &iteuart_device,
2021+#endif
2022+};
2023+
2024+#ifdef CONFIG_PCI
2025+/*
2026+ * Install handler for IT8152 IRQ. Yes, yes... we are way down the IRQ
2027+ * cascade which is not good for IRQ latency, but the hardware has been
2028+ * designed that way...
2029+ */
2030+static inline void cmx270_irq(int irq, struct pt_regs *regs)
2031+{
2032+ struct irqdesc *desc;
2033+ desc = irq_desc + irq;
2034+ desc->handle(irq, desc, regs);
2035+}
2036+
2037+static void cmx270_irq_demux(unsigned int irq, struct irqdesc *desc,
2038+ struct pt_regs *regs)
2039+{
2040+ unsigned long pdcnimr, ldcnimr;
2041+ int pdcnirr, ldcnir;
2042+
2043+ /* clear our parent irq */
2044+ GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
2045+
2046+ /* read pending IRQs in the chip registers and clear them */
2047+ pdcnirr = IT8152_INTC_PDCNIRR;
2048+ ldcnir = IT8152_INTC_LDCNIRR;
2049+ IT8152_INTC_PDCNIRR = ~pdcnirr;
2050+ IT8152_INTC_LDCNIRR = ~ldcnir;
2051+
2052+ /* mask ITE irqs */
2053+ pdcnimr = IT8152_INTC_PDCNIMR;
2054+ ldcnimr = IT8152_INTC_LDCNIMR;
2055+ IT8152_INTC_PDCNIMR = 0xffff;
2056+ IT8152_INTC_LDCNIMR = 0xffff;
2057+
2058+ pdcnirr &= (PCISERR_BIT | H2PTADR_BIT | H2PMAR_BIT |
2059+ PCI_INTD_BIT | PCI_INTC_BIT | PCI_INTB_BIT | PCI_INTA_BIT |
2060+ USB_INT_BIT | CDMA_INT_BIT);
2061+
2062+ ldcnir &= ITESER_BIT;
2063+
2064+ IT8152_INTC_PDCNIRR = ~pdcnirr;
2065+ IT8152_INTC_LDCNIRR = ~ldcnir;
2066+
2067+ /* are there interrupts pending ? */
2068+ if( (pdcnirr | ldcnir) ) {
2069+ if (pdcnirr) {
2070+ if( pdcnirr & PCISERR_BIT )
2071+ cmx270_irq(PCISERR, regs);
2072+ if( pdcnirr & H2PTADR_BIT )
2073+ cmx270_irq(H2PTADR, regs);
2074+ if( pdcnirr & H2PMAR_BIT )
2075+ cmx270_irq(H2PMAR, regs);
2076+ if( pdcnirr & PCI_INTA_BIT )
2077+ cmx270_irq(PCI_INTA, regs);
2078+ if( pdcnirr & PCI_INTB_BIT )
2079+ cmx270_irq(PCI_INTB, regs);
2080+ if( pdcnirr & PCI_INTC_BIT )
2081+ cmx270_irq(PCI_INTC, regs);
2082+ if( pdcnirr & PCI_INTD_BIT )
2083+ cmx270_irq(PCI_INTD, regs);
2084+ if( pdcnirr & USB_INT_BIT )
2085+ cmx270_irq(USB_INT, regs);
2086+ if( pdcnirr & CDMA_INT_BIT )
2087+ cmx270_irq(CDMA_INT, regs);
2088+ }
2089+ if(ldcnir) {
2090+ if( ldcnir & ITESER_BIT )
2091+ cmx270_irq(IRQ_ITESER, regs);
2092+ }
2093+ }
2094+
2095+ /* re-enable ITE interrupts */
2096+ IT8152_INTC_PDCNIMR = pdcnimr;
2097+ IT8152_INTC_LDCNIMR = ldcnimr;
2098+}
2099+#else
2100+unsigned long it8152_base_address = CMX270_IT8152_VIRT;
2101+#endif
2102+
2103+/* Map PCI companion and IDE/General Purpose CS statically */
2104+static struct map_desc cmx270_io_desc[] __initdata = {
2105+ {
2106+ .virtual = CMX270_IDE104_VIRT,
2107+ .pfn = __phys_to_pfn(CMX270_IDE104_PHYS),
2108+ .length = PXA_CS_SIZE,
2109+ .type = MT_DEVICE
2110+ },
2111+ {
2112+ .virtual = CMX270_IT8152_VIRT,
2113+ .pfn = __phys_to_pfn(CMX270_IT8152_PHYS),
2114+ .length = PXA_CS_SIZE,
2115+ .type = MT_DEVICE
2116+ },
2117+};
2118+
2119+/*********************** Display definitions ****************************/
2120+static int mtype=MTYPE_CRT640x480;
2121+static int mbpp=-1;
2122+
2123+struct cmx270_display_info {
2124+ struct pxafb_mach_info fb_info;
2125+ char *display_name;
2126+};
2127+
2128+static struct __initdata cmx270_display_info cmx270_displays[] = {
2129+ [ MTYPE_STN320x240 ] = {
2130+ .fb_info = {
2131+ .pixclock = 76923,
2132+ .bpp = 8,
2133+ .xres = 320,
2134+ .yres = 240,
2135+ .hsync_len = 3,
2136+ .vsync_len = 2,
2137+ .left_margin = 3,
2138+ .upper_margin = 0,
2139+ .right_margin = 3,
2140+ .lower_margin = 0,
2141+ .sync = (FB_SYNC_HOR_HIGH_ACT |
2142+ FB_SYNC_VERT_HIGH_ACT),
2143+ .lccr0 = 0,
2144+ .lccr3 = (LCCR3_PixClkDiv(0x03) |
2145+ LCCR3_Acb(0xff) |
2146+ LCCR3_PCP),
2147+ .cmap_greyscale = 0,
2148+ .cmap_inverse = 0,
2149+ .cmap_static = 0,
2150+ },
2151+ .display_name = "STN 320x240",
2152+ },
2153+ [ MTYPE_TFT640x480 ] = {
2154+ .fb_info = {
2155+ .pixclock = 38461,
2156+ .bpp = 8,
2157+ .xres = 640,
2158+ .yres = 480,
2159+ .hsync_len = 60,
2160+ .vsync_len = 2,
2161+ .left_margin = 70,
2162+ .upper_margin = 10,
2163+ .right_margin = 70,
2164+ .lower_margin = 5,
2165+ .sync = 0,
2166+ .lccr0 = (LCCR0_PAS),
2167+ .lccr3 = (LCCR3_PixClkDiv(0x01) |
2168+ LCCR3_Acb(0xff) |
2169+ LCCR3_PCP),
2170+ .cmap_greyscale = 0,
2171+ .cmap_inverse = 0,
2172+ .cmap_static = 0,
2173+ },
2174+ .display_name = "TFT 640x480",
2175+ },
2176+ [ MTYPE_CRT640x480 ] = {
2177+ .fb_info = {
2178+ .pixclock = 38461,
2179+ .bpp = 8,
2180+ .xres = 640,
2181+ .yres = 480,
2182+ .hsync_len = 63,
2183+ .vsync_len = 2,
2184+ .left_margin = 81,
2185+ .upper_margin = 33,
2186+ .right_margin = 16,
2187+ .lower_margin = 10,
2188+ .sync = (FB_SYNC_HOR_HIGH_ACT |
2189+ FB_SYNC_VERT_HIGH_ACT),
2190+ .lccr0 = (LCCR0_PAS),
2191+ .lccr3 = (LCCR3_PixClkDiv(0x01) |
2192+ LCCR3_Acb(0xff)),
2193+ .cmap_greyscale = 0,
2194+ .cmap_inverse = 0,
2195+ .cmap_static = 0,
2196+ },
2197+ .display_name = "CRT 640x480",
2198+ },
2199+ [ MTYPE_CRT800x600 ] = {
2200+ .fb_info = {
2201+ .pixclock = 28846,
2202+ .bpp = 8,
2203+ .xres = 800,
2204+ .yres = 600,
2205+ .hsync_len = 63,
2206+ .vsync_len = 2,
2207+ .left_margin = 26,
2208+ .upper_margin = 21,
2209+ .right_margin = 26,
2210+ .lower_margin = 11,
2211+ .sync = (FB_SYNC_HOR_HIGH_ACT |
2212+ FB_SYNC_VERT_HIGH_ACT),
2213+ .lccr0 = (LCCR0_PAS),
2214+ .lccr3 = (LCCR3_PixClkDiv(0x02) |
2215+ LCCR3_Acb(0xff)),
2216+ .cmap_greyscale = 0,
2217+ .cmap_inverse = 0,
2218+ .cmap_static = 0,
2219+ },
2220+ .display_name = "CRT 800x600",
2221+ },
2222+ [ MTYPE_CRT1024x768 ] = {
2223+ .fb_info = {
2224+ .pixclock = 0,
2225+ .xres = 0,
2226+ .yres = 0,
2227+ },
2228+ .display_name = "CRT 1024x768",
2229+ },
2230+ [ MTYPE_USER_DEFINED ] = {
2231+ .fb_info = {
2232+ .pixclock = LCD_PIXCLOCK,
2233+ .bpp = LCD_BPP,
2234+ .xres = LCD_XRES,
2235+ .yres = LCD_YRES,
2236+ .hsync_len = LCD_HORIZONTAL_SYNC_PULSE_WIDTH,
2237+ .vsync_len = LCD_VERTICAL_SYNC_PULSE_WIDTH,
2238+ .left_margin = LCD_BEGIN_OF_LINE_WAIT_COUNT,
2239+ .upper_margin = LCD_BEGIN_FRAME_WAIT_COUNT,
2240+ .right_margin = LCD_END_OF_LINE_WAIT_COUNT,
2241+ .lower_margin = LCD_END_OF_FRAME_WAIT_COUNT,
2242+ .sync = LCD_SYNC,
2243+ .lccr0 = LCD_LCCR0,
2244+ .lccr3 = LCD_LCCR3,
2245+ .cmap_greyscale = CMAP_GREYSCALE,
2246+ .cmap_inverse = CMAP_INVERSE,
2247+ .cmap_static = CMAP_STATIC,
2248+ },
2249+ .display_name = LCD_NAME,
2250+ },
2251+ [ MTYPE_TFT320x240 ] = {
2252+ .fb_info = {
2253+ .pixclock = 134615,
2254+ .bpp = 16,
2255+ .xres = 320,
2256+ .yres = 240,
2257+ .hsync_len = 63,
2258+ .vsync_len = 7,
2259+ .left_margin = 75,
2260+ .upper_margin = 0,
2261+ .right_margin = 15,
2262+ .lower_margin = 15,
2263+ .sync = 0,
2264+ .lccr0 = (LCCR0_PAS),
2265+ .lccr3 = (LCCR3_PixClkDiv(0x06) |
2266+ LCCR3_Acb(0xff) |
2267+ LCCR3_PCP),
2268+ .cmap_greyscale = 0,
2269+ .cmap_inverse = 0,
2270+ .cmap_static = 0,
2271+ },
2272+ .display_name = "TFT 320x240",
2273+ },
2274+ [ MTYPE_STN640x480 ] = {
2275+ .fb_info = {
2276+ .pixclock = 57692,
2277+ .bpp = 8,
2278+ .xres = 640,
2279+ .yres = 480,
2280+ .hsync_len = 4,
2281+ .vsync_len = 2,
2282+ .left_margin = 10,
2283+ .upper_margin = 5,
2284+ .right_margin = 10,
2285+ .lower_margin = 5,
2286+ .sync = (FB_SYNC_HOR_HIGH_ACT |
2287+ FB_SYNC_VERT_HIGH_ACT),
2288+ .lccr0 = 0,
2289+ .lccr3 = (LCCR3_PixClkDiv(0x02) |
2290+ LCCR3_Acb(0xff)),
2291+ .cmap_greyscale = 0,
2292+ .cmap_inverse = 0,
2293+ .cmap_static = 0,
2294+ },
2295+ .display_name = "STN 640x480",
2296+ },
2297+};
2298+
2299+static int __init monitor_params(char *str)
2300+{
2301+ mtype = simple_strtol(str, NULL, 0);
2302+ return 1;
2303+}
2304+
2305+__setup("monitor=", monitor_params);
2306+
2307+static int __init fb_bpp(char *str)
2308+{
2309+ mbpp = simple_strtol(str, NULL, 0);
2310+ return 1;
2311+}
2312+
2313+__setup("bpp=", fb_bpp);
2314+
2315+/* PXA27x OHCI controller setup */
2316+static int cmx270_ohci_init(struct device *dev)
2317+{
2318+ /* Set the Power Control Polarity Low */
2319+ UHCHR = (UHCHR | UHCHR_PCPL) &
2320+ ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
2321+
2322+ return 0;
2323+}
2324+
2325+static struct pxaohci_platform_data cmx270_ohci_platform_data = {
2326+ .port_mode = PMM_PERPORT_MODE,
2327+ .init = cmx270_ohci_init,
2328+};
2329+
2330+#ifdef CONFIG_PM
2331+/* timeout for RTC wakeup */
2332+unsigned int cmx270_suspend_timeout;
2333+
2334+static ssize_t timeout_show(struct subsystem * subsys, char * buf)
2335+{
2336+ char * s = buf;
2337+
2338+ s += sprintf(s,"%d seconds\n", cmx270_suspend_timeout);
2339+ return (s - buf);
2340+}
2341+
2342+static ssize_t timeout_store(struct subsystem * subsys, const char * buf, size_t n)
2343+{
2344+ char *endp = 0;
2345+ int timeout;
2346+
2347+ timeout = simple_strtoul(buf, &endp, 10);
2348+ if ( *endp && *endp != '\n')
2349+ return -EINVAL;
2350+
2351+ cmx270_suspend_timeout = timeout;
2352+ return n;
2353+}
2354+
2355+static struct subsys_attribute timeout_attr = {
2356+ .attr = {
2357+ .name = __stringify(timeout),
2358+ .mode = 0644,
2359+ },
2360+ .show = timeout_show,
2361+ .store = timeout_store,
2362+};
2363+
2364+static struct attribute * g[] = {
2365+ &timeout_attr.attr,
2366+ NULL,
2367+};
2368+
2369+static struct attribute_group attr_group = {
2370+ .attrs = g,
2371+};
2372+
2373+extern struct subsystem power_subsys;
2374+static unsigned long sleep_save_ite[10];
2375+static unsigned long sleep_save_msc[10];
2376+
2377+static int cmx270_suspend(struct sys_device *dev, pm_message_t state)
2378+{
2379+#ifdef CONFIG_PCI
2380+ /* save ITE state */
2381+ sleep_save_ite[0] = IT8152_INTC_PDCNIMR;
2382+ sleep_save_ite[1] = IT8152_INTC_LPCNIMR;
2383+ sleep_save_ite[2] = IT8152_INTC_LPNIAR;
2384+
2385+ /* Clear ITE IRQ's */
2386+ IT8152_INTC_PDCNIRR = 0;
2387+ IT8152_INTC_LPCNIRR = 0;
2388+#endif
2389+
2390+ /* save MSC registers */
2391+ sleep_save_msc[0] = MSC0;
2392+ sleep_save_msc[1] = MSC1;
2393+ sleep_save_msc[2] = MSC2;
2394+
2395+ /* setup power saving mode registers */
2396+ PCFR = 0x0;
2397+ PSLR = 0xff400000;
2398+ PMCR = 0x00000005;
2399+ PWER = 0x80000000;
2400+ PFER = 0x00000000;
2401+ PRER = 0x00000000;
2402+ PGSR0 = 0xC0018800;
2403+ PGSR1 = 0x004F0002;
2404+ PGSR2 = 0x6021C000;
2405+ PGSR3 = 0x00020000;
2406+
2407+ if ( cmx270_suspend_timeout ) {
2408+ RTAR = RCNR + cmx270_suspend_timeout;
2409+ cmx270_suspend_timeout = 0;
2410+ }
2411+
2412+ return 0;
2413+}
2414+
2415+static int cmx270_resume(struct sys_device *dev)
2416+{
2417+#ifdef CONFIG_PCI
2418+ /* restore IT8152 state */
2419+ IT8152_INTC_PDCNIMR = sleep_save_ite[0];
2420+ IT8152_INTC_LPCNIMR = sleep_save_ite[1];
2421+ IT8152_INTC_LPNIAR = sleep_save_ite[2];
2422+#endif
2423+
2424+ /* restore MSC registers */
2425+ MSC0 = sleep_save_msc[0];
2426+ MSC1 = sleep_save_msc[1];
2427+ MSC2 = sleep_save_msc[2];
2428+
2429+ return 0;
2430+}
2431+
2432+static struct sysdev_class cmx270_pm_sysclass = {
2433+ set_kset_name("pm"),
2434+ .resume = cmx270_resume,
2435+ .suspend = cmx270_suspend,
2436+};
2437+
2438+static struct sys_device cmx270_pm_device = {
2439+ .cls = &cmx270_pm_sysclass,
2440+};
2441+
2442+static int __init cmx270_pm_init(void)
2443+{
2444+ int error;
2445+ error = sysdev_class_register(&cmx270_pm_sysclass);
2446+ if (error == 0)
2447+ error = sysdev_register(&cmx270_pm_device);
2448+
2449+ error = sysfs_create_group(&power_subsys.kset.kobj,&attr_group);
2450+ return error;
2451+}
2452+#else
2453+static int __init cmx270_pm_init(void) { return 0; }
2454+#endif
2455+
2456+/* SA1111 compatibiliy 8 bit read register needed for proper function
2457+ of ITE8152 UART */
2458+#define MEMC_SA1111 __REG(0x48000064)
2459+
2460+static void __init cmx270_init(void)
2461+{
2462+ /* set display timings for VGA 640x480 by default */
2463+ struct cmx270_display_info *tfbi = &cmx270_displays[2];
2464+
2465+ MEMC_SA1111 = 0x3c;
2466+
2467+ cmx270_pm_init();
2468+
2469+ if ( mtype >= 0 && mtype < ARRAY_SIZE(cmx270_displays) )
2470+ tfbi = &cmx270_displays[mtype];
2471+
2472+ /* use default instead of unsupported displays */
2473+ if ( tfbi->fb_info.pixclock == 0 &&
2474+ tfbi->fb_info.xres == 0 &&
2475+ tfbi->fb_info.yres == 0 ) {
2476+ printk(KERN_WARNING "CM-X270 does not support %s display\n", cmx270_displays[mtype].display_name);
2477+ tfbi = &cmx270_displays[2];
2478+ }
2479+
2480+ /* setup color depth */
2481+ if( mtype == MTYPE_USER_DEFINED ) {
2482+ mbpp = tfbi->fb_info.bpp;
2483+ }
2484+ if( mbpp > 0 ) {
2485+ if( (mbpp!=1) && (mbpp!=2) && (mbpp!=4) &&
2486+ (mbpp!=8) && (mbpp!=16)) {
2487+ printk(KERN_WARNING "Illegal BPP value "
2488+ "supplied, leaving default\n");
2489+ mbpp = 8;
2490+ }
2491+ }
2492+ else mbpp = 8;
2493+ tfbi->fb_info.bpp = mbpp;
2494+
2495+ printk(KERN_INFO "Running a %s display with %d bits per pixel\n",
2496+ tfbi->display_name, tfbi->fb_info.bpp);
2497+ set_pxa_fb_info(&tfbi->fb_info);
2498+
2499+#ifdef CONFIG_PCI
2500+ /* setup ITE8152 UART base addresses */
2501+ ite_uart_port[0].membase = (void *)&IT8152_UART_BASE;
2502+ ite_uart_port[0].mapbase = IT8152_UART_BASE;
2503+#endif
2504+
2505+ /* register CM-X270 platform devices */
2506+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
2507+
2508+ pxa_set_ohci_info(&cmx270_ohci_platform_data);
2509+
2510+ /* This enables the STUART */
2511+ pxa_gpio_mode(GPIO46_STRXD_MD);
2512+ pxa_gpio_mode(GPIO47_STTXD_MD);
2513+
2514+ /* This enables the BTUART */
2515+ pxa_gpio_mode(GPIO42_BTRXD_MD);
2516+ pxa_gpio_mode(GPIO43_BTTXD_MD);
2517+ pxa_gpio_mode(GPIO44_BTCTS_MD);
2518+ pxa_gpio_mode(GPIO45_BTRTS_MD);
2519+}
2520+
2521+#ifdef CONFIG_PCI
2522+static void cmx270_mask_irq(unsigned int irq)
2523+{
2524+ switch(irq) {
2525+ case IT8152_IRQ(0):
2526+ IT8152_INTC_PDCNIMR |= PCISERR_BIT;
2527+ break;
2528+ case IT8152_IRQ(1):
2529+ IT8152_INTC_PDCNIMR |= H2PTADR_BIT;
2530+ break;
2531+ case IT8152_IRQ(2):
2532+ IT8152_INTC_PDCNIMR |= H2PMAR_BIT;
2533+ break;
2534+ case IT8152_IRQ(3):
2535+ IT8152_INTC_PDCNIMR |= PCI_INTA_BIT;
2536+ break;
2537+ case IT8152_IRQ(4):
2538+ IT8152_INTC_PDCNIMR |= PCI_INTB_BIT;
2539+ break;
2540+ case IT8152_IRQ(5):
2541+ IT8152_INTC_PDCNIMR |= PCI_INTC_BIT;
2542+ break;
2543+ case IT8152_IRQ(6):
2544+ IT8152_INTC_PDCNIMR |= PCI_INTD_BIT;
2545+ break;
2546+ case IT8152_IRQ(7):
2547+ IT8152_INTC_PDCNIMR |= USB_INT_BIT;
2548+ break;
2549+ case IT8152_IRQ(9):
2550+ IT8152_INTC_PDCNIMR |= CDMA_INT_BIT;
2551+ break;
2552+ case IT8152_IRQ(10):
2553+ IT8152_INTC_LDCNIMR |= ITESER_BIT;
2554+ break;
2555+ }
2556+}
2557+
2558+static void cmx270_unmask_irq(unsigned int irq)
2559+{
2560+ switch(irq) {
2561+ case IT8152_IRQ(0):
2562+ IT8152_INTC_PDCNIMR &= (~PCISERR_BIT);
2563+ break;
2564+ case IT8152_IRQ(1):
2565+ IT8152_INTC_PDCNIMR &= (~H2PTADR_BIT);
2566+ break;
2567+ case IT8152_IRQ(2):
2568+ IT8152_INTC_PDCNIMR &= (~H2PMAR_BIT);
2569+ break;
2570+ case IT8152_IRQ(3):
2571+ IT8152_INTC_PDCNIMR &= (~PCI_INTA_BIT);
2572+ break;
2573+ case IT8152_IRQ(4):
2574+ IT8152_INTC_PDCNIMR &= (~PCI_INTB_BIT);
2575+ break;
2576+ case IT8152_IRQ(5):
2577+ IT8152_INTC_PDCNIMR &= (~PCI_INTC_BIT);
2578+ break;
2579+ case IT8152_IRQ(6):
2580+ IT8152_INTC_PDCNIMR &= (~PCI_INTD_BIT);
2581+ break;
2582+ case IT8152_IRQ(7):
2583+ IT8152_INTC_PDCNIMR &= (~USB_INT_BIT);
2584+ break;
2585+ case IT8152_IRQ(9):
2586+ IT8152_INTC_PDCNIMR &= (~CDMA_INT_BIT);
2587+ break;
2588+ case IT8152_IRQ(10):
2589+ IT8152_INTC_LDCNIMR &= (~ITESER_BIT);
2590+ break;
2591+ }
2592+}
2593+
2594+static struct irqchip cmx270_irq_chip = {
2595+ .ack = cmx270_mask_irq,
2596+ .mask = cmx270_mask_irq,
2597+ .unmask = cmx270_unmask_irq,
2598+};
2599+#endif
2600+
2601+static void __init cmx270_init_irq(void)
2602+{
2603+ int irq;
2604+
2605+ pxa_init_irq();
2606+
2607+ /* LED and NAND GPIOs should not be probed for IRQ */
2608+ irq_desc[IRQ_GPIO(11)].probe_ok = 0;
2609+ irq_desc[IRQ_GPIO(89)].probe_ok = 0;
2610+ irq_desc[IRQ_GPIO(93)].probe_ok = 0;
2611+ irq_desc[IRQ_GPIO(94)].probe_ok = 0;
2612+
2613+ IT8152_INTC_PDCNIMR = 0xffff;
2614+
2615+#ifdef CONFIG_PCI
2616+ /* Disable and clear IRQ's for ITE8152 */
2617+ IT8152_INTC_PDCNIMR = 0xffff;
2618+ IT8152_INTC_PDCNIRR = 0;
2619+ IT8152_INTC_LPCNIMR = 0xffff;
2620+ IT8152_INTC_LPCNIRR = 0;
2621+ IT8152_INTC_LDCNIMR = 0xffff;
2622+ IT8152_INTC_LDCNIRR = 0;
2623+
2624+ /* Set IT8152 serial port IRQ as active high*/
2625+ IT8152_INTC_LDNIAR |= ITESER_BIT;
2626+
2627+ for(irq = IT8152_IRQ(0); irq <= IT8152_IRQ_MAX; irq++) {
2628+ set_irq_chip(irq, &cmx270_irq_chip);
2629+ set_irq_handler(irq, do_level_IRQ);
2630+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
2631+ }
2632+
2633+ /* INTC signal from IT8152 is connected to GPIO0 */
2634+ pxa_gpio_mode(IRQ_GPIO_IT8152_IRQ);
2635+ set_irq_chained_handler(IRQ_GPIO_IT8152_IRQ, cmx270_irq_demux);
2636+ set_irq_type(IRQ_GPIO_IT8152_IRQ, IRQT_RISING);
2637+#endif
2638+
2639+ /* Setup interrupt for dm9000 */
2640+ pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ));
2641+ set_irq_type(CMX270_ETHIRQ, IRQT_RISING);
2642+
2643+ /* Setup interrupt for 2700G */
2644+ pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ));
2645+ set_irq_type(CMX270_GFXIRQ, IRQT_FALLING);
2646+}
2647+
2648+static void __init cmx270_map_io(void)
2649+{
2650+ pxa_map_io();
2651+ iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
2652+}
2653+
2654+
2655+MACHINE_START(ARMCORE, "Compulab CM-x270")
2656+ .boot_params = 0xa0000100,
2657+ .phys_io = 0x40000000,
2658+ .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
2659+ .map_io = cmx270_map_io,
2660+ .init_irq = cmx270_init_irq,
2661+ .timer = &pxa_timer,
2662+ .init_machine = cmx270_init,
2663+MACHINE_END
2664diff --git a/arch/arm/mach-pxa/it8152.c b/arch/arm/mach-pxa/it8152.c
2665new file mode 100644
2666index 0000000..91bb49c
2667--- /dev/null
2668+++ b/arch/arm/mach-pxa/it8152.c
2669@@ -0,0 +1,248 @@
2670+/*
2671+ * arch/arm/common/it8152.c: PCI functions for IT8152
2672+ *
2673+ * Compulab Ltd, 2002-2006
2674+ *
2675+ * The DMA bouncing is taken from arch/arm/mach-ixp4xx/common-pci.c
2676+ * (see this file for respective copyrights)
2677+ *
2678+ * This program is free software; you can redistribute it and/or modify
2679+ * it under the terms of the GNU General Public License version 2 as
2680+ * published by the Free Software Foundation.
2681+ */
2682+
2683+#include <linux/sched.h>
2684+#include <linux/kernel.h>
2685+#include <linux/pci.h>
2686+#include <linux/ptrace.h>
2687+#include <linux/interrupt.h>
2688+#include <linux/mm.h>
2689+#include <linux/slab.h>
2690+#include <linux/init.h>
2691+#include <linux/ioport.h>
2692+#include <asm/mach/map.h>
2693+
2694+
2695+#include <asm/io.h>
2696+#include <asm/irq.h>
2697+#include <asm/system.h>
2698+#include <asm/mach/pci.h>
2699+#include <asm/hardware/it8152.h>
2700+
2701+#define MAX_SLOTS 21
2702+
2703+static unsigned long
2704+it8152_pci_dev_base_address(struct pci_bus *bus, unsigned int devfn)
2705+{
2706+ unsigned long addr = 0;
2707+
2708+ if (bus->number == 0) {
2709+ if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
2710+ addr = (devfn << 8);
2711+ } else
2712+ addr = (bus->number << 16) | (devfn << 8);
2713+
2714+ return addr;
2715+}
2716+
2717+static int
2718+it8152_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
2719+ int size, u32 *value)
2720+{
2721+ unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
2722+ u32 v;
2723+ int shift;
2724+
2725+#ifdef CONFIG_MACH_ARMCORE
2726+ if(devfn!=0) IT8152_GPIO_GPLR=0x00;
2727+#endif
2728+ shift = (where & 3);
2729+
2730+ IT8152_PCI_CFG_ADDR = (addr + where);
2731+ v = (IT8152_PCI_CFG_DATA >> (8 * (shift)));
2732+
2733+ *value = v;
2734+
2735+#ifdef CONFIG_MACH_ARMCORE
2736+ if(devfn!=0) IT8152_GPIO_GPLR=0x20;
2737+#endif
2738+
2739+ return PCIBIOS_SUCCESSFUL;
2740+}
2741+
2742+
2743+static int
2744+it8152_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
2745+ int size, u32 value)
2746+{
2747+ unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
2748+ u32 v, vtemp, mask=0;
2749+ int shift;
2750+
2751+#ifdef CONFIG_MACH_ARMCORE
2752+ if(devfn!=0) IT8152_GPIO_GPLR=0x00;
2753+#endif
2754+
2755+ if(size==1) mask=0xff;
2756+ if(size==2) mask=0xffff;
2757+
2758+ shift = (where & 3);
2759+
2760+ IT8152_PCI_CFG_ADDR = addr + where;
2761+ vtemp = IT8152_PCI_CFG_DATA;
2762+
2763+ if(mask) vtemp &= ~(mask << (8 * shift));
2764+ else vtemp = 0;
2765+
2766+ v = (value << (8 * shift));
2767+ IT8152_PCI_CFG_ADDR = addr + where;
2768+ IT8152_PCI_CFG_DATA = (v | vtemp);
2769+
2770+#ifdef CONFIG_MACH_ARMCORE
2771+ if(devfn!=0) IT8152_GPIO_GPLR=0x20;
2772+#endif
2773+
2774+ return PCIBIOS_SUCCESSFUL;
2775+}
2776+
2777+static struct pci_ops it8152_ops = {
2778+ .read = it8152_pci_read_config,
2779+ .write = it8152_pci_write_config,
2780+};
2781+
2782+static struct resource it8152_io = {
2783+ .name = "IT8152 PCI I/O region",
2784+ .flags = IORESOURCE_IO,
2785+};
2786+
2787+static struct resource it8152_mem1 = {
2788+ .name = "First IT8152 PCI memory region",
2789+ .start = 0x10000000,
2790+ .end = 0x13e00000,
2791+ .flags = IORESOURCE_MEM,
2792+};
2793+
2794+/*
2795+ * The following functions are needed for DMA bouncing.
2796+ * ITE8152 chip can addrees up to 64MByte, so all the devices
2797+ * connected to ITE8152 (PCI and USB) should have limited DMA window
2798+ */
2799+
2800+/*
2801+ * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
2802+ * other devices.
2803+ */
2804+static int it8152_pci_platform_notify(struct device *dev)
2805+{
2806+ if ( dev->bus == &pci_bus_type ) {
2807+ if ( dev->dma_mask )
2808+ *dev->dma_mask = SZ_64M - 1;
2809+ dev->coherent_dma_mask = SZ_64M - 1;
2810+ dmabounce_register_dev(dev, 2048, 4096);
2811+ }
2812+ return 0;
2813+}
2814+
2815+static int it8152_pci_platform_notify_remove(struct device *dev)
2816+{
2817+ if ( dev->bus == &pci_bus_type ) {
2818+ dmabounce_unregister_dev(dev);
2819+ }
2820+ return 0;
2821+}
2822+
2823+int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
2824+{
2825+ dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
2826+ __FUNCTION__, dma_addr, size);
2827+ return (dev->bus == &pci_bus_type ) &&
2828+ ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
2829+}
2830+
2831+/*
2832+ * Only first 64MB of memory can be accessed via PCI.
2833+ * We use GFP_DMA to allocate safe buffers to do map/unmap.
2834+ * This is really ugly and we need a better way of specifying
2835+ * DMA-capable regions of memory.
2836+ */
2837+void __init it8152_adjust_zones(int node, unsigned long *zone_size,
2838+ unsigned long *zhole_size)
2839+{
2840+ unsigned int sz = SZ_64M >> PAGE_SHIFT;
2841+
2842+ /*
2843+ * Only adjust if > 64M on current system
2844+ */
2845+ if (node || (zone_size[0] <= sz))
2846+ return;
2847+
2848+ zone_size[1] = zone_size[0] - sz;
2849+ zone_size[0] = sz;
2850+ zhole_size[1] = zhole_size[0];
2851+ zhole_size[0] = 0;
2852+}
2853+
2854+/*
2855+ * We override these so we properly do dmabounce otherwise drivers
2856+ * are able to set the dma_mask to 0xffffffff and we can no longer
2857+ * trap bounces. :(
2858+ *
2859+ * We just return true on everyhing except for < 64MB in which case
2860+ * we will fail miseralby and die since we can't handle that case.
2861+ */
2862+int
2863+pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2864+{
2865+ if (mask >= SZ_64M - 1 )
2866+ return 0;
2867+
2868+ return -EIO;
2869+}
2870+
2871+int
2872+pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2873+{
2874+ if (mask >= SZ_64M - 1 )
2875+ return 0;
2876+
2877+ return -EIO;
2878+}
2879+
2880+EXPORT_SYMBOL(pci_set_dma_mask);
2881+EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2882+
2883+
2884+int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
2885+{
2886+ it8152_io.start = IT8152_IO_BASE + 0x12000;
2887+ it8152_io.end = IT8152_IO_BASE + 0x100000;
2888+
2889+ if (request_resource(&ioport_resource, &it8152_io)) {
2890+ printk(KERN_ERR "PCI: unable to allocate IO region\n");
2891+ return -EBUSY;
2892+ }
2893+ if (request_resource(&iomem_resource, &it8152_mem1)) {
2894+ printk(KERN_ERR "PCI: unable to allocate memory region\n");
2895+ return -EBUSY;
2896+ }
2897+
2898+ sys->resource[0] = &it8152_io;
2899+ sys->resource[1] = &it8152_mem1;
2900+
2901+ if (platform_notify || platform_notify_remove) {
2902+ printk(KERN_ERR "PCI: Can't use platform_notify\n");
2903+ return -EBUSY;
2904+ }
2905+
2906+ platform_notify = it8152_pci_platform_notify;
2907+ platform_notify_remove = it8152_pci_platform_notify_remove;
2908+
2909+ return 1;
2910+}
2911+
2912+
2913+struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
2914+{
2915+ return pci_scan_bus(nr, &it8152_ops, sys);
2916+}
2917+
2918diff --git a/arch/arm/mach-pxa/leds-cm-x270.c b/arch/arm/mach-pxa/leds-cm-x270.c
2919new file mode 100644
2920index 0000000..5402b69
2921--- /dev/null
2922+++ b/arch/arm/mach-pxa/leds-cm-x270.c
2923@@ -0,0 +1,134 @@
2924+/*
2925+ * linux/arch/arm/mach-pxa/leds-cm-x270.c
2926+ *
2927+ * Compulab Ltd., 2003
2928+ *
2929+ * Original (leds-footbridge.c) by Russell King
2930+ *
2931+ * Macros for actual LED manipulation should be in machine specific
2932+ * files in this 'mach' directory.
2933+ */
2934+
2935+
2936+#include <linux/config.h>
2937+#include <linux/types.h>
2938+#include <linux/init.h>
2939+
2940+#include <asm/hardware.h>
2941+#include <asm/leds.h>
2942+#include <asm/system.h>
2943+
2944+#include <asm/arch/pxa-regs.h>
2945+#include <asm/arch/cm-x270.h>
2946+
2947+#include "leds.h"
2948+
2949+#define LED_STATE_ENABLED 1
2950+#define LED_STATE_CLAIMED 2
2951+
2952+#define RED_LED_ON 1
2953+#define GREEN_LED_ON 2
2954+
2955+static unsigned int led_state;
2956+static unsigned int hw_led_state;
2957+
2958+void armcore_leds_event(led_event_t evt)
2959+{
2960+ unsigned long flags;
2961+
2962+ local_irq_save(flags);
2963+
2964+ switch (evt) {
2965+ case led_start:
2966+ hw_led_state = GREEN_LED_ON | RED_LED_ON;
2967+ led_state = LED_STATE_ENABLED;
2968+ break;
2969+
2970+ case led_stop:
2971+ led_state &= ~LED_STATE_ENABLED;
2972+ break;
2973+
2974+ case led_claim:
2975+ led_state |= LED_STATE_CLAIMED;
2976+ hw_led_state = GREEN_LED_ON | RED_LED_ON;
2977+ break;
2978+
2979+ case led_release:
2980+ led_state &= ~LED_STATE_CLAIMED;
2981+ hw_led_state = GREEN_LED_ON | RED_LED_ON;
2982+ break;
2983+
2984+#ifdef CONFIG_LEDS_TIMER
2985+ case led_timer:
2986+ if (!(led_state & LED_STATE_CLAIMED))
2987+ hw_led_state ^= GREEN_LED_ON;
2988+ break;
2989+#endif
2990+
2991+#ifdef CONFIG_LEDS_CPU
2992+ case led_idle_start:
2993+ if (!(led_state & LED_STATE_CLAIMED))
2994+ hw_led_state &= ~RED_LED_ON;
2995+ break;
2996+
2997+ case led_idle_end:
2998+ if (!(led_state & LED_STATE_CLAIMED))
2999+ hw_led_state |= RED_LED_ON;
3000+ break;
3001+#endif
3002+
3003+ case led_halted:
3004+ break;
3005+
3006+ case led_green_on:
3007+ if (led_state & LED_STATE_CLAIMED)
3008+ hw_led_state &= ~GREEN_LED_ON;
3009+ break;
3010+
3011+ case led_green_off:
3012+ if (led_state & LED_STATE_CLAIMED)
3013+ hw_led_state |= GREEN_LED_ON;
3014+ break;
3015+
3016+ case led_amber_on:
3017+ break;
3018+
3019+ case led_amber_off:
3020+ break;
3021+
3022+ case led_red_on:
3023+ if (led_state & LED_STATE_CLAIMED)
3024+ hw_led_state &= ~RED_LED_ON;
3025+ break;
3026+
3027+ case led_red_off:
3028+ if (led_state & LED_STATE_CLAIMED)
3029+ hw_led_state |= RED_LED_ON;
3030+ break;
3031+
3032+ default:
3033+ break;
3034+ }
3035+
3036+ if (led_state & LED_STATE_ENABLED)
3037+ {
3038+ if(hw_led_state & RED_LED_ON) {
3039+ CMX270_RED_ON();
3040+// printk("Red on\n");
3041+ }
3042+ else {
3043+// printk("Red off\n");
3044+ CMX270_RED_OFF();
3045+ }
3046+ if(hw_led_state & GREEN_LED_ON) {
3047+// printk("Green on\n");
3048+ CMX270_GREEN_ON();
3049+ }
3050+ else {
3051+// printk("Green off\n");
3052+ CMX270_GREEN_OFF();
3053+ }
3054+ }
3055+
3056+ local_irq_restore(flags);
3057+}
3058diff --git a/arch/arm/mach-pxa/leds.c b/arch/arm/mach-pxa/leds.c
3059index bbe4d5f..a27d027 100644
3060--- a/arch/arm/mach-pxa/leds.c
3061+++ b/arch/arm/mach-pxa/leds.c
3062@@ -24,6 +24,8 @@ pxa_leds_init(void)
3063 leds_event = mainstone_leds_event;
3064 if (machine_is_pxa_idp())
3065 leds_event = idp_leds_event;
3066+ if (machine_is_armcore())
3067+ leds_event = armcore_leds_event;
3068
3069 leds_event(led_start);
3070 return 0;
3071diff --git a/arch/arm/mach-pxa/leds.h b/arch/arm/mach-pxa/leds.h
3072index d98f6e9..0dcc346 100644
3073--- a/arch/arm/mach-pxa/leds.h
3074+++ b/arch/arm/mach-pxa/leds.h
3075@@ -10,3 +10,4 @@
3076 extern void idp_leds_event(led_event_t evt);
3077 extern void lubbock_leds_event(led_event_t evt);
3078 extern void mainstone_leds_event(led_event_t evt);
3079+extern void armcore_leds_event(led_event_t evt);
3080diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
3081index 3baa708..823c32d 100644
3082--- a/arch/arm/mach-pxa/pxa27x.c
3083+++ b/arch/arm/mach-pxa/pxa27x.c
3084@@ -140,10 +140,12 @@ void pxa_cpu_pm_enter(suspend_state_t st
3085 extern void pxa_cpu_suspend(unsigned int);
3086 extern void pxa_cpu_resume(void);
3087
3088+#ifndef CONFIG_MACH_ARMCORE
3089 if (state == PM_SUSPEND_STANDBY)
3090 CKEN = CKEN22_MEMC | CKEN9_OSTIMER | CKEN16_LCD |CKEN0_PWM0;
3091 else
3092 CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
3093+#endif
3094
3095 /* ensure voltage-change sequencer not initiated, which hangs */
3096 PCFR &= ~PCFR_FVC;
3097@@ -158,7 +160,11 @@ void pxa_cpu_pm_enter(suspend_state_t st
3098 case PM_SUSPEND_MEM:
3099 /* set resume return address */
3100 PSPR = virt_to_phys(pxa_cpu_resume);
3101+#ifdef CONFIG_MACH_ARMCORE
3102+ pxa_cpu_suspend(PWRMODE_DEEPSLEEP);
3103+#else
3104 pxa_cpu_suspend(PWRMODE_SLEEP);
3105+#endif
3106 break;
3107 }
3108 }
3109diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
3110index 8b13316..8ffaad0 100644
3111--- a/drivers/block/Kconfig
3112+++ b/drivers/block/Kconfig
3113@@ -453,4 +453,9 @@ config ATA_OVER_ETH
3114 This driver provides Support for ATA over Ethernet block
3115 devices like the Coraid EtherDrive (R) Storage Blade.
3116
3117+config ARMCORE_FLASH
3118+ tristate "ARMCORE flash drivers"
3119+ depends on MACH_ARMCORE
3120+ source "drivers/block/cl_flash/Kconfig"
3121+
3122 endmenu
3123diff --git a/drivers/block/Makefile b/drivers/block/Makefile
3124index 3ec1f8d..ebeb4c6 100644
3125--- a/drivers/block/Makefile
3126+++ b/drivers/block/Makefile
3127@@ -31,3 +31,4 @@ obj-$(CONFIG_VIODASD) += viodasd.o
3128 obj-$(CONFIG_BLK_DEV_SX8) += sx8.o
3129 obj-$(CONFIG_BLK_DEV_UB) += ub.o
3130
3131+obj-$(CONFIG_ARMCORE_FLASH) += cl_flash/
3132diff --git a/drivers/block/cl_flash/CL_Logic.h b/drivers/block/cl_flash/CL_Logic.h
3133new file mode 100644
3134index 0000000..fe3e8d7
3135--- /dev/null
3136+++ b/drivers/block/cl_flash/CL_Logic.h
3137@@ -0,0 +1,245 @@
3138+/* Module: CL_Logic.h
3139+ Author: Vova Lifliand
3140+ Description: Controls Nand flash management logic
3141+ Notes:
3142+*/
3143+
3144+#ifndef __CL_LOGIC__
3145+#define __CL_LOGIC__
3146+/*#define CL_NAND_BIG_DELAYS*/
3147+#if defined(FLASH_PLATFORM_LINUX) || defined(FLASH_PLATFORM_ARMonitor)
3148+/* Structure packaging */
3149+ #define PACKAGE __attribute__ ((packed,aligned(1)))
3150+ #define CL_ST static
3151+#else
3152+ #define PACKAGE
3153+ #define CL_ST
3154+#endif
3155+ #define FAR
3156+ #define far
3157+/* NOR Flash management constants */
3158+#define CL_NOR_FLASH_PAGE_SIZE 512 /* bytes */
3159+
3160+#ifdef FLASH_PLATFORM_DOS
3161+ #define cl_error_log(x,...){}
3162+#endif /* MS-DOS */
3163+/* Nand Flash management constants */
3164+
3165+/* Page size must not be changed because this value is also used for
3166+ page size of Nand flash */
3167+/*#define CL_FLASH_PAGE_SIZE 512 // bytes */
3168+#define CL_FLASH_MAXIMUM_PAGE_SIZE 2048/* bytes */
3169+#define CL_FLASH_MINIMAL_SECTOR_SIZE 512 /* Sectors can't be less than 512 bytes */
3170+/*#define CL_FLASH_SPARE_AREA_SIZE 16 // bytes */
3171+/*#define CL_FLASH_MAXIMUM_SPARE_AREA_SIZE 128 bytes - twice the needed for biggest
3172+ flash today 2004/05 */
3173+#define CL_FLASH_MAXIMUM_SPARE_AREA_SIZE 128 /*Stingy with space...*/
3174+
3175+/* Maximum blocks number in flash - adjust according to maximum flash size */
3176+#define CL_MAX_BLKS_NUMBER 8192 /* good for 128MB flash */
3177+ /* Good up to 512 MB flash, if 64kb is the smallest block */
3178+/* Number of pages in Nand flash block */
3179+/* #define CL_FLASH_PAGES_PER_NAND_BLK 32 */
3180+/* Maximum Number of pages in Nand flash block */
3181+#define CL_FLASH_MAXIMUM_PAGES_PER_NAND_BLK 128 /* 32 */ /* Can't be more than 255
3182+ to fit in unsigned char arrays*/
3183+/* Number of pages to make free */
3184+#define CL_FLASH_FREE_PAGE_PER_BLK 1
3185+/* Usable pages per 16 KB Nand flash block */
3186+/*#define CL_FLASH_USE_PAGE_PER_BLK (CL_FLASH_PAGES_PER_NAND_BLK - CL_FLASH_FREE_PAGE_PER_BLK)*/
3187+#define CL_FLASH_USE_PAGE_PER_BLK (flogic->nand->pages_per_block - CL_FLASH_FREE_PAGE_PER_BLK)
3188+/* Number of logical to physical page translation tables stored in memory
3189+ Each table size is ~40 bytes */
3190+#define CL_LTF_PAGE_TBLS 30
3191+/* Always leave a number of blocks unused - just for sure */
3192+#define CL_EXTRA_SPARE_BLKS 10
3193+/* Define maximum number of different blocks with cached pages */
3194+#define CL_MAX_CACHED_BLKS 4
3195+/* Number of erases per one launching of anti wearing procedure */
3196+#define CL_ERASE_PER_ANTI_WEARING 1000
3197+
3198+
3199+#define CLBYTEPTR unsigned char far*
3200+
3201+
3202+/* Flash mapping and accessing interface */
3203+typedef struct PACKAGE cl_nand_map_if_t
3204+{
3205+ /* Destroy function must free all allocated resources (such as virtual memory) */
3206+ void (*init) (void);
3207+ void (*destroy) (void);
3208+ /* Chip select operation. When on = 1: chip select, on = 0: disable chip select */
3209+ /* need_auto_operation - Whe the ON is false, the pin is expected to pulse in accordance
3210+ with bus transactions. This function exists on x86, but not on ARM */
3211+ void (*chip_select) (int on, int need_auto_operation);
3212+ /* Reading from flash (HW read access, not actual data reading) */
3213+ unsigned char (*readb) (unsigned char offset);
3214+ /* Writing to flash (HW write access, not actual data writing) */
3215+ void (*writeb) (unsigned char offset, unsigned char data);
3216+ /* Reads block from flash: reads data from address 0 while incrementing data pointer */
3217+ void (*blockread) (CLBYTEPTR data, int count);
3218+ /* Writes block to flash: writes data to address 0 while incrementing data pointer */
3219+ void (*blockwrite) ( CLBYTEPTR data, int count);
3220+ /* Turns on/off activity indication leds */
3221+ void (*activity_leds) (short operation, short reclaim);
3222+ /* Performs specified delay (parameter in microsecond units) */
3223+ int (*sleep) (unsigned long microseconds);
3224+ /* Wait for completion using R/B line */
3225+ /* Use microseconds, if R/B line not implemented */
3226+ int (*rbwait) (unsigned long microseconds);
3227+} cl_nand_map_if;
3228+
3229+
3230+/* Internal flash logic structure */
3231+typedef struct cl_logic_t far*cl_logic;
3232+
3233+
3234+/* Parameter retrive enum */
3235+typedef enum
3236+{
3237+ CL_FLASH_TOTAL_SIZE, /* Total size of the flash in bytes */
3238+ CL_FLASH_HEADS_NUM, /* Number of heads */
3239+ CL_FLASH_SECTOR_SIZE = 512, /* Sector size (in bytes) =512 - is legacy for ARMonitor only*/
3240+ CL_FLASH_SECTORS_NUM, /* Number of sectors per tracks */
3241+ CL_FLASH_CYLINDERS_NUM, /* Number of cylinders */
3242+ CL_FLASH_PAGE_SIZE, /* Size of the page without spare area */
3243+ CL_FLASH_READ_PAGE_CNT, /* Read page operations count */
3244+ CL_FLASH_WRITE_PAGE_CNT, /* Write page operations count */
3245+ CL_FLASH_RECLAIM_CNT, /* Reclaim block count */
3246+ CL_FLASH_BURSTS_NUM, /* Bursts of length 'var' numbers */
3247+ CL_FLASH_ERASE_CNT, /* Erase cnt of block specified by 'var' */
3248+ CL_FLASH_BAD_BLOCK_CNT,
3249+} PACKAGE cl_logic_param;
3250+
3251+/* Direct access type enum */
3252+typedef enum
3253+{
3254+ CL_FLASH_READ_PAGE,
3255+ CL_FLASH_READ_SPARE_AREA,
3256+ CL_FLASH_READ_BLK_SPARES, /* All spare areas of specified block */
3257+ CL_FLASH_WRITE_PAGE,
3258+ CL_FLASH_WRITE_SPARE_AREA,
3259+ CL_FLASH_ERASE_BLOCK /* Data ignored */
3260+} PACKAGE cl_nand_direct_access_type;
3261+
3262+/* memory access type enum */
3263+typedef enum //Memory areas usage is dscribed in separate document.
3264+{
3265+ CL_FLOGIC = 0,
3266+ CL_NAND,
3267+ CL_CACHE,
3268+ CL_CACHE_ORDERED_ARRAY,
3269+ CL_SP_AREA,
3270+ CL_SP_AREA_2,
3271+ CL_SP_AREA_3,
3272+ CL_PAGE,
3273+ CL_CACHE_REF
3274+} PACKAGE cl_memory_region_name;
3275+
3276+#define NUMBER_OF_MEMORY_REGIONS 9
3277+
3278+
3279+typedef enum
3280+{
3281+ CL_FIRST_ALLOCATION_STAGE,
3282+ CL_SECOND_ALLOCATION_STAGE
3283+}PACKAGE cl_memory_allocation_stages;
3284+
3285+typedef struct cl_memory_pointer_type
3286+{
3287+ void far* pMemory;
3288+ char IN_USE;
3289+} PACKAGE cl_memory_pointer;
3290+
3291+void far* cl_memory_request (cl_memory_region_name mem_name);
3292+
3293+void cl_memory_return (cl_memory_region_name mem_name);
3294+
3295+/* Creates flash logic object and attaches it to specified HW nand flash.
3296+ cache_size is max. number of pages, the cache can hold.
3297+ The flash is formatted prior initialization if format != 0.
3298+ When formatting reseved blocks and bad are not erased. */
3299+cl_logic cl_logic_create (cl_nand_map_if* nand_if, long cache_size, int format, unsigned short sector_size);
3300+
3301+/* Removes flash logic object and frees all allocated resources. */
3302+void cl_logic_free (cl_logic flogic);
3303+
3304+/* Parameters retrival function. */
3305+long cl_logic_get_param (cl_logic flogic, cl_logic_param prm, long var);
3306+
3307+/* Read page command. */
3308+int cl_logic_read_page (cl_logic flogic, long fs_sectn,
3309+ CLBYTEPTR sector_data);
3310+
3311+/* Write page command. */
3312+int cl_logic_write_page (cl_logic flogic, long fs_pagen,
3313+ CLBYTEPTR page_data);
3314+
3315+/* Flushes too old cache. If force_one_flush is TRUE, at least one
3316+ cached block is flushed. */
3317+void cl_logic_on_idle (cl_logic flogic, int force_one_flush);
3318+
3319+/* Flushes all cached data to disk. */
3320+void cl_logic_sync (cl_logic flogic);
3321+
3322+/* Direct accessing commands */
3323+int cl_logic_direct_access (cl_logic flogic, cl_nand_direct_access_type type,
3324+ unsigned short block, unsigned char page, CLBYTEPTR data);
3325+
3326+
3327+/* NOR Flash Disk Driver */
3328+
3329+/* The header describes block information */
3330+typedef struct
3331+{
3332+ unsigned short Signature; /* 0x1998 for initialized blocks */
3333+ unsigned short State;
3334+ unsigned short EraseCounter;
3335+ unsigned short PageIndex[128];
3336+ unsigned short Unused[10];
3337+ unsigned short BlockReserved; /* 0xFFFF - usable block, 0 - reserved block */
3338+} PACKAGE cl_nor_block_header;
3339+
3340+/* Abstract class for flash access */
3341+typedef struct
3342+{
3343+ /* Constructor */
3344+ void (*Constructor)(void);
3345+ /* Destructor */
3346+ void (*Destructor)(void);
3347+ /* Define flash access functions */
3348+ /* Returns usable size */
3349+ unsigned long (*GetSize)(void);
3350+ /* Remaps or unmaps MMS windows, allocated by flash */
3351+ void (*EnableFlashMap)(int EnableFlag);
3352+ /* Returns number of usable pages, 512 bytes each. */
3353+ /* Doesn't include first page that is used for header - signature, state . . . */
3354+ int (*GetPagesPerBlock)(void);
3355+ /* Header */
3356+ int (*ReadHeader)(unsigned short BlockN, cl_nor_block_header* Header);
3357+ /* The PageNum == 0 is first data page and not the header. Max. value of PageNum */
3358+ /* is GetBlockSize() / BytesPerPage - 1 (min. is 0) */
3359+ int (*ReadPage)(unsigned short BlockN, unsigned char PageNum, CLBYTEPTR DestBuff);
3360+ int (*SetBlockState) (unsigned short BlockN, unsigned short Signature,
3361+ unsigned short State, unsigned short Reserved);
3362+ /* Sets logical page index to zero - invalidates page. PageN is like in WritePage */
3363+ int (*InvalidatePage)(unsigned short BlockN, unsigned char PageN);
3364+ /* BlockN and PageN - destination location, where PageN doesn't include header */
3365+ /* information (PageN = 0 means first logical page and it's seconds physical page). */
3366+ /* PageIndex is physical page number for further identification (by ReadHeader) */
3367+ int (*WritePage)(unsigned short BlockN, unsigned char PageN,
3368+ const CLBYTEPTR PageData, unsigned short PageIndex);
3369+ int (*EraseBlock)(unsigned short BlockN);
3370+} PACKAGE cl_nor_flash_access;
3371+
3372+/* Define flash access functions */
3373+int cl_nor_init_flash (void);
3374+int cl_nor_free_mem (void);
3375+int cl_nor_format_flash (int (*ProgressCallback)(int Percentage));
3376+int cl_nor_write_page (int PageIndex, CLBYTEPTR Data);
3377+int cl_nor_read_page (int PageIndex, CLBYTEPTR Data);
3378+int cl_nor_get_disk_param (unsigned long* TotalPage, unsigned long* BytesPerPage,
3379+ unsigned long* Cylinders, unsigned long* PagesPerTrk,
3380+ unsigned long* Heads);
3381+#endif /* __CL_LOGIC__ */
3382+
3383diff --git a/drivers/block/cl_flash/Kconfig b/drivers/block/cl_flash/Kconfig
3384new file mode 100644
3385index 0000000..60aa80d
3386--- /dev/null
3387+++ b/drivers/block/cl_flash/Kconfig
3388@@ -0,0 +1,11 @@
3389+#
3390+# Block device driver configuration
3391+#
3392+
3393+config ARMCORE_NOR
3394+ bool "CompuLab NOR flash driver"
3395+ depends on ARMCORE_FLASH
3396+config ARMCORE_NAND
3397+ bool "CompuLab NAND flash driver"
3398+ depends on ARMCORE_FLASH
3399+
3400diff --git a/drivers/block/cl_flash/Makefile b/drivers/block/cl_flash/Makefile
3401new file mode 100644
3402index 0000000..538cb2c
3403--- /dev/null
3404+++ b/drivers/block/cl_flash/Makefile
3405@@ -0,0 +1,12 @@
3406+#
3407+# Makefile for Compulab flash disk driver
3408+#
3409+
3410+EXTRA_CFLAGS += -DTARGET_ARM_CORE -DFLASH_PLATFORM_LINUX
3411+
3412+obj-$(CONFIG_ARMCORE_FLASH) += fdrv.o
3413+
3414+fdrv-y += cl_nordev.o cl_blkdev.o CL_FlashDrv
3415+
3416+
3417+fdrv-$(CONFIG_MACH_ARMCORE) += cl_nanddev_x270.o
3418diff --git a/drivers/block/cl_flash/cl_blkdev.c b/drivers/block/cl_flash/cl_blkdev.c
3419new file mode 100644
3420index 0000000..adb030d
3421--- /dev/null
3422+++ b/drivers/block/cl_flash/cl_blkdev.c
3423@@ -0,0 +1,731 @@
3424+/*
3425+ * Flash Disk Driver for Linux.
3426+ * Generic block device and genric disk implementation
3427+ *
3428+ * Copyright Compulab 2003-2006 (c).
3429+ */
3430+
3431+#include <linux/timer.h>
3432+#include <linux/hdreg.h>
3433+#include <linux/devfs_fs_kernel.h>
3434+#include <linux/blkdev.h>
3435+#include <linux/blkpg.h>
3436+#include <linux/ioctl.h>
3437+
3438+#include "CL_Logic.h"
3439+#include "cl_blkdev.h"
3440+
3441+/* I/O Controls */
3442+#define CL_FLASH_IOC_MAGIC 'f'
3443+#define CL_FLASH_IO_GET_PARAM _IOWR (CL_FLASH_IOC_MAGIC, 1, char[12])
3444+#define CL_FLASH_IO_DIRECT_ACCESS _IOWR (CL_FLASH_IOC_MAGIC, 2, char[524])
3445+
3446+#define FLUSH_INTERVAL 100
3447+
3448+struct cl_blkdev;
3449+
3450+struct flash_blkdev_ops {
3451+ /* timer for periodic flushes of NAND flash */
3452+ void (*flush_proc)(void* dev);
3453+
3454+ /* HW specific ioctl */
3455+ int (*flash_hw_ioctl)(struct cl_blkdev *dev, struct inode *inode,
3456+ struct file *file, unsigned int cmd,
3457+ unsigned long arg);
3458+
3459+ /* HW specific request handling */
3460+ int (*do_flash_hw_request)(struct cl_blkdev *dev, struct request *q);
3461+ /* HW specific cleanups */
3462+ int (*flash_hw_release)(struct cl_blkdev *dev, struct inode *inode,
3463+ struct file *file);
3464+};
3465+
3466+struct cl_blkdev_priv {
3467+ /* thread is dead indication */
3468+ struct completion thread_dead;
3469+ /* flag to notify the thread that we are done */
3470+ int exiting;
3471+ /* thread wait queue head for requests */
3472+ wait_queue_head_t thread_wq;
3473+ /* block device request queue */
3474+ struct request_queue *rq;
3475+ /* request queue lock */
3476+ spinlock_t queue_lock;
3477+};
3478+
3479+struct cl_blkdev {
3480+ struct cl_blkdev_priv *blkdev_priv;
3481+ struct gendisk *flash_disk;
3482+ struct flash_blkdev_ops *ops;
3483+ struct semaphore sem;
3484+ char name[32];
3485+
3486+ int major;
3487+ void *hw_private; /* Low level hook */
3488+
3489+#ifdef CONFIG_PROC_FS
3490+ /* proc entry */
3491+ struct proc_dir_entry *pde;
3492+#endif
3493+};
3494+
3495+#define FLASH_SECTOR 512
3496+
3497+/* declarations of cl_mem_set etc */
3498+#include "cl_common.c"
3499+
3500+
3501+/***************************************************************/
3502+/* Flash software write protect setup */
3503+/***************************************************************/
3504+unsigned long wpstart=0, wpend=0;
3505+
3506+static int __init wpstart_det(char *str) /*30-May-04, interrupts */
3507+{
3508+ wpstart = simple_strtol(str, NULL, 0);
3509+ return 1;
3510+}
3511+
3512+static int __init wpend_det(char *str) /*30-May-04, interrupts */
3513+{
3514+ wpend = simple_strtol(str, NULL, 0);
3515+ return 1;
3516+}
3517+
3518+__setup("wpstart=", wpstart_det);
3519+__setup("wpend=", wpend_det);
3520+
3521+
3522+/***************************************************************/
3523+/* generic block device interface */
3524+/***************************************************************/
3525+/* cl_blkdev_open: open a device */
3526+static int cl_blkdev_open(struct inode *inode, struct file *file)
3527+{
3528+ return 0;
3529+}
3530+
3531+static int cl_blkdev_check_media_change(struct gendisk* dev)
3532+{
3533+ return 0; /* Disk not changed */
3534+}
3535+
3536+static int cl_blkdev_revalidate(struct gendisk* dev)
3537+{
3538+ return 0;
3539+}
3540+
3541+/* cl_blkdev_release: release the device */
3542+static int cl_blkdev_release(struct inode *inode, struct file *file)
3543+{
3544+ struct cl_blkdev *dev;
3545+ dev = inode->i_bdev->bd_disk->private_data;
3546+
3547+ down (&dev->sem);
3548+ dev->ops->flash_hw_release(dev, inode, file);
3549+ up (&dev->sem);
3550+
3551+ return 0;
3552+}
3553+
3554+/*
3555+ cl_blkdev_ioctl: handle device ioctl's
3556+ common ioctls (if any) for NAND and NOR flash are handled here
3557+ then HW specific ioctl handler is invoked
3558+ */
3559+static int cl_blkdev_ioctl(struct inode *inode,
3560+ struct file *file, u_int cmd, u_long arg)
3561+{
3562+ struct cl_blkdev *dev;
3563+
3564+ if ((!inode) || !(inode->i_rdev))
3565+ return -EINVAL;
3566+
3567+ dev = inode->i_bdev->bd_disk->private_data;
3568+ return dev->ops->flash_hw_ioctl(dev, inode, file, cmd, arg);
3569+}
3570+
3571+static struct block_device_operations flash_fops =
3572+{
3573+ .owner = THIS_MODULE,
3574+ .open = cl_blkdev_open,
3575+ .release = cl_blkdev_release,
3576+ .ioctl = cl_blkdev_ioctl,
3577+ .media_changed = cl_blkdev_check_media_change,
3578+ .revalidate_disk = cl_blkdev_revalidate
3579+};
3580+
3581+static int cl_nand_request (struct cl_blkdev *_dev, struct request * req);
3582+
3583+/* wake up the flashdiskd thread to handle the request */
3584+static void do_cl_blkdev_request(struct request_queue *rq)
3585+{
3586+ struct cl_blkdev *dev = rq->queuedata;
3587+ wake_up(&dev->blkdev_priv->thread_wq);
3588+}
3589+
3590+void cl_blkdev_suspend(struct cl_blkdev* dev)
3591+{
3592+ dev->ops->flush_proc(dev);
3593+}
3594+
3595+/***************************************************************/
3596+/* flashdiskd thread is handling all transfer requests */
3597+/***************************************************************/
3598+static int cl_flashdisk_thread(void *arg)
3599+{
3600+ struct cl_blkdev *dev = (struct cl_blkdev*)arg;
3601+ struct request_queue *rq = dev->blkdev_priv->rq;
3602+ unsigned long flush_period = msecs_to_jiffies(FLUSH_INTERVAL);
3603+ unsigned long last_flush_jiffies = jiffies;
3604+
3605+ current->flags |= PF_MEMALLOC/* | PF_NOFREEZE */;
3606+ daemonize("%sd", "flashdisk");
3607+
3608+ while (!dev->blkdev_priv->exiting) {
3609+ struct request *req;
3610+ int res = 0;
3611+ DECLARE_WAITQUEUE(wait, current);
3612+
3613+ try_to_freeze();
3614+
3615+ spin_lock_irq(rq->queue_lock);
3616+ req = elv_next_request(rq);
3617+
3618+ if (!req) {
3619+ add_wait_queue(&dev->blkdev_priv->thread_wq, &wait);
3620+ set_current_state(TASK_INTERRUPTIBLE);
3621+
3622+ spin_unlock_irq(rq->queue_lock);
3623+
3624+ schedule();
3625+ remove_wait_queue(&dev->blkdev_priv->thread_wq, &wait);
3626+
3627+ continue;
3628+ }
3629+
3630+ dev = req->rq_disk->private_data;
3631+ spin_unlock_irq(rq->queue_lock);
3632+
3633+ down(&dev->sem);
3634+ res = dev->ops->do_flash_hw_request(dev, req);
3635+
3636+ if ( jiffies - last_flush_jiffies > flush_period ) {
3637+ if ( dev->ops->flush_proc )
3638+ dev->ops->flush_proc(dev);
3639+ last_flush_jiffies = jiffies;
3640+ }
3641+ up(&dev->sem);
3642+
3643+ spin_lock_irq(rq->queue_lock);
3644+ end_request(req, res);
3645+ spin_unlock_irq(rq->queue_lock);
3646+ }
3647+ complete_and_exit(&dev->blkdev_priv->thread_dead, 0);
3648+}
3649+
3650+/***************************************************************/
3651+/* block device initialization routines */
3652+/***************************************************************/
3653+
3654+/*
3655+ cl_blkdev_init:
3656+ - initialize and register generic block device,
3657+ - initialize timers for peroidic flushes
3658+ - initialize thread syncronization data
3659+ - start request processing thread
3660+
3661+ dev - preallocated device that should be initialized
3662+ ops - HW specific implementation of block device ioctl, do_request etc
3663+ name - device name
3664+*/
3665+int cl_blkdev_init(struct cl_blkdev *dev,
3666+ struct flash_blkdev_ops *ops, const char *name)
3667+{
3668+ int ret;
3669+
3670+ /* allocate the thread synchronization structure */
3671+ dev->blkdev_priv = kmalloc(sizeof(*dev->blkdev_priv), GFP_KERNEL);
3672+ if (!dev->blkdev_priv)
3673+ return -ENOMEM;
3674+ memset(dev->blkdev_priv, 0, sizeof(*dev->blkdev_priv));
3675+
3676+ dev->ops = ops;
3677+ dev->major = 0;
3678+ strcpy(dev->name, name);
3679+
3680+ /* register block device */
3681+ if ((dev->major = register_blkdev(dev->major, dev->name)) <= 0) {
3682+ printk("flash: Unable to get major number.\n");
3683+ return -ENODEV;
3684+ }
3685+ else
3686+ printk("Major number received: %d\n", dev->major);
3687+
3688+ /* initialize data for 'flashdiskd' thread */
3689+ spin_lock_init(&dev->blkdev_priv->queue_lock);
3690+ init_completion(&dev->blkdev_priv->thread_dead);
3691+ init_waitqueue_head(&dev->blkdev_priv->thread_wq);
3692+ init_MUTEX(&dev->sem);
3693+
3694+ /* initialize block device request queue */
3695+ dev->blkdev_priv->rq = blk_init_queue(do_cl_blkdev_request,
3696+ &dev->blkdev_priv->queue_lock);
3697+ if(!dev->blkdev_priv->rq) {
3698+ printk ("Could not initialize queue.\n");
3699+ unregister_blkdev(dev->major, dev->name);
3700+ kfree(dev->blkdev_priv);
3701+ return -ENOMEM;
3702+ }
3703+ dev->blkdev_priv->rq->queuedata = dev;
3704+ blk_queue_hardsect_size(dev->blkdev_priv->rq, FLASH_SECTOR);
3705+
3706+ /* start thread */
3707+ ret = kernel_thread(cl_flashdisk_thread, dev, CLONE_KERNEL);
3708+ if (ret < 0) {
3709+ blk_cleanup_queue(dev->blkdev_priv->rq);
3710+ unregister_blkdev(dev->major, dev->name);
3711+ kfree(dev->blkdev_priv);
3712+ printk(KERN_ERR "%s: kernel_thread returned %d\n", __FUNCTION__, ret);
3713+ return ret;
3714+ }
3715+
3716+ return 0;
3717+}
3718+
3719+/*
3720+ cl_blkdev_register_disk:
3721+ - allocate generic dik object
3722+ - setup the disk (major, minors, name, ops)
3723+ - register the disk
3724+
3725+ dev - block device enclosing the disk
3726+ name - disk name
3727+ size - size of the disk in sectors
3728+*/
3729+int cl_blkdev_register_disk(struct cl_blkdev *dev,
3730+ const char* name, sector_t size)
3731+{
3732+ /* allocate disk data structure */
3733+ dev->flash_disk = alloc_disk(16);
3734+ if (! dev->flash_disk)
3735+ return -ENOMEM;
3736+
3737+ /* initialize disk parameters */
3738+ dev->flash_disk->major = dev->major;
3739+ dev->flash_disk->first_minor = 0;
3740+ dev->flash_disk->fops = &flash_fops;
3741+ dev->flash_disk->private_data = dev;
3742+ dev->flash_disk->queue = dev->blkdev_priv->rq;
3743+
3744+ /* set /dev node names */
3745+ strcpy(dev->flash_disk->disk_name, name);
3746+ strcpy(dev->flash_disk->devfs_name, name);
3747+ set_capacity(dev->flash_disk, size);
3748+
3749+ /* Insert this disk into linked list of disks */
3750+ add_disk(dev->flash_disk);
3751+
3752+ return 0;
3753+}
3754+
3755+/*
3756+ cl_blkdev_unregister: unregister flash disk and associated block device
3757+*/
3758+void cl_blkdev_unregister(struct cl_blkdev *dev)
3759+{
3760+ dev->blkdev_priv->exiting = 1;
3761+ wake_up(&dev->blkdev_priv->thread_wq);
3762+ wait_for_completion(&dev->blkdev_priv->thread_dead);
3763+
3764+ del_gendisk(dev->flash_disk);
3765+ put_disk(dev->flash_disk);
3766+ blk_cleanup_queue(dev->blkdev_priv->rq);
3767+
3768+ unregister_blkdev(dev->major, dev->name);
3769+}
3770+
3771+/***************************************************************/
3772+/* NAND flash specific */
3773+/***************************************************************/
3774+int format = 0;
3775+MODULE_PARM(format, "i");
3776+
3777+#define CACHE_SIZE 128
3778+
3779+/* This buffer is used for cach allocation, when cash size is bigger
3780+ than 128kb. 300 KB is the approximate amount needed for cache of 128
3781+ pages, 2kb each. */
3782+#define BUFFER_SIZE (300 * 1024)
3783+#define MAXIMUM_ALLOCATABLE_MEMORY (128 * 1024)
3784+char tmp_buff[BUFFER_SIZE];
3785+
3786+/*
3787+ cl_nand_mem_alloc: allocates memory for driver cache
3788+*/
3789+void* cl_nand_mem_alloc (unsigned long size)
3790+{
3791+ static int buf_not_used = 1;
3792+ if ((size > MAXIMUM_ALLOCATABLE_MEMORY) &&
3793+ (size < BUFFER_SIZE) && buf_not_used) {
3794+ buf_not_used = 0;
3795+ return (void*)tmp_buff;
3796+ }
3797+ return kmalloc (size, GFP_KERNEL);
3798+}
3799+
3800+/*
3801+ cl_nand_mem_free: frees memory allocated for driver cache
3802+*/
3803+void cl_nand_mem_free (void* ptr)
3804+{
3805+ kfree (ptr);
3806+}
3807+
3808+/*
3809+ cl_nand_flush_proc: flushes driver caches to the device
3810+*/
3811+static void cl_nand_flush_proc (void* _dev)
3812+{
3813+ struct cl_blkdev *blkdev = (struct cl_blkdev*)_dev;
3814+ struct cl_nand_dev *dev = (struct cl_nand_dev*)blkdev->hw_private;
3815+
3816+ dev->logic_sync(dev->logic);
3817+ cl_trace_log ("Data synced\n");
3818+ dev->last_end_write_cmd = 0;
3819+}
3820+
3821+/*
3822+ cl_nand_request: handles an incoming IO request
3823+*/
3824+static int cl_nand_request (struct cl_blkdev *_dev, struct request * req)
3825+{
3826+ struct cl_blkdev *blkdev = (struct cl_blkdev*)_dev;
3827+ struct cl_nand_dev *dev = (struct cl_nand_dev*)blkdev->hw_private;
3828+
3829+ u_int block, count;
3830+ int code=1, i;
3831+
3832+ block = req->sector;
3833+ count = req->current_nr_sectors;
3834+
3835+ switch (rq_data_dir(req)) {
3836+ case 0: /* READ */
3837+ for (i = 0, code = 1; i < count; i++)
3838+ if (!dev->logic_read_page(
3839+ dev->logic, block + i,
3840+ (char*)req->buffer + i * 512)) {
3841+ cl_trace_log ("Reading failed.\n");
3842+ code = 0; /* failure */
3843+ break;
3844+ }
3845+ break;
3846+ case 1: /* WRITE */
3847+ for (i = 0, code = 1; i < count; i++) {
3848+ if(wpend) {
3849+ if (((block + i) >= wpstart) ||
3850+ ((block + i) <= wpend)) {
3851+ code=0;
3852+ break;
3853+ }
3854+ }
3855+ if (!dev->logic_write_page(
3856+ dev->logic, block + i,
3857+ (char*)req->buffer + i * 512)) {
3858+ cl_trace_log ("Writing failed.\n");
3859+ code = 0; /* failure */
3860+ break;
3861+ }
3862+ }
3863+ dev->last_end_write_cmd = jiffies;
3864+ break;
3865+ default:
3866+ printk("do_flash_request: unknown request\n");
3867+ break;
3868+ }
3869+
3870+ return code;
3871+}
3872+
3873+/*
3874+ cl_nand_ioctl: handles device ioctl's
3875+*/
3876+static int cl_nand_ioctl(struct cl_blkdev *_dev, struct inode *inode,
3877+ struct file *file,unsigned int cmd,unsigned long arg)
3878+{
3879+ struct cl_nand_dev *dev = (struct cl_nand_dev*)_dev->hw_private;
3880+
3881+ cl_trace_log ("flash_ioctl called.\n");
3882+ printk("fdrv.o ioctl\n");
3883+ if ((!inode) || !(inode->i_rdev))
3884+ return -EINVAL;
3885+
3886+ switch (cmd) {
3887+ case HDIO_GETGEO:
3888+ {
3889+ struct hd_geometry *geometry = (struct hd_geometry*)arg;
3890+ if (!geometry)
3891+ return -EINVAL; /* Bad arguments to ioctl */
3892+ put_user(dev->logic_get_param(dev->logic,
3893+ CL_FLASH_CYLINDERS_NUM,
3894+ 0),
3895+ &geometry->cylinders);
3896+ put_user(dev->logic_get_param(dev->logic,
3897+ CL_FLASH_HEADS_NUM, 0),
3898+ &geometry->heads);
3899+ put_user(dev->logic_get_param(dev->logic,
3900+ CL_FLASH_SECTORS_NUM, 0),
3901+ &geometry->sectors);
3902+ put_user(0, &geometry->start);
3903+ return 0;
3904+ }
3905+ case BLKGETSIZE:
3906+ if (!arg)
3907+ return -EINVAL;
3908+ return put_user(dev->logic_get_param(
3909+ dev->logic,
3910+ CL_FLASH_TOTAL_SIZE, 0) / 512,
3911+ (long *) arg);
3912+ case HDIO_SET_DMA:
3913+ /* We don't use DMA for flash.
3914+ This has no meaning */
3915+ if (!capable (CAP_SYS_ADMIN))
3916+ return -EACCES;
3917+ return 0;
3918+ case HDIO_GET_DMA:
3919+ return put_user( 0, (long *) arg); /* No DMA */
3920+ case HDIO_GET_MULTCOUNT:
3921+ /* We don't have a limitation of number of
3922+ sectors in op. */
3923+ return put_user (128, (long *) arg);
3924+ case BLKRRPART:
3925+ case BLKFLSBUF:
3926+ case BLKROSET:
3927+ case BLKROGET:
3928+ case BLKRASET:
3929+ case BLKRAGET:
3930+ case BLKPG:
3931+ case CL_FLASH_IO_GET_PARAM:
3932+ {
3933+ int err;
3934+ long* prm = (long*)arg;
3935+ err = access_ok(VERIFY_READ, prm,
3936+ sizeof(long) * 2) ? 0 : -EFAULT;
3937+ if (err)
3938+ return err;
3939+ err = access_ok(VERIFY_WRITE, prm,
3940+ sizeof (long)) ? 0 : -EFAULT;
3941+ if (err)
3942+ return err;
3943+ prm[0] = dev->logic_get_param(dev->logic,
3944+ prm[0], prm[1]);
3945+ return 0;
3946+ }
3947+
3948+ case CL_FLASH_IO_DIRECT_ACCESS:
3949+ {
3950+ int err;
3951+ printk("====> CL_FLASH_IO_DIRECT_ACCESS\n");
3952+ long* prm = (long*)arg;
3953+ err = access_ok(VERIFY_READ, prm,
3954+ sizeof(long) * 3) ? 0 : -EFAULT;
3955+ if(err) return err;
3956+ err = access_ok(VERIFY_WRITE, prm,
3957+ CL_FLASH_SECTOR_SIZE) ? 0 : -EFAULT;
3958+ if(err) return err;
3959+ return dev->logic_direct_access(
3960+ dev->logic,
3961+ (cl_nand_direct_access_type)prm[0],
3962+ (unsigned short)prm[1],
3963+ (unsigned short)prm[2],
3964+ (unsigned char*)(prm + 3));
3965+ }
3966+
3967+ default:
3968+ return -EINVAL;
3969+ }
3970+}
3971+
3972+/*
3973+ cl_nand_release: releases the device
3974+*/
3975+static int cl_nand_release (struct cl_blkdev *_dev,
3976+ struct inode *inode, struct file *file)
3977+{
3978+ struct cl_nand_dev *dev = (struct cl_nand_dev*)_dev->hw_private;
3979+
3980+ dev->logic_sync(dev->logic);
3981+ cl_trace_log ("Data synced after RELEASE command\n");
3982+ dev->last_end_write_cmd = 0;
3983+
3984+ return 0;
3985+}
3986+
3987+static struct flash_blkdev_ops nand_blkdev_ops = {
3988+ .flush_proc = cl_nand_flush_proc,
3989+ .flash_hw_ioctl = cl_nand_ioctl,
3990+ .do_flash_hw_request = cl_nand_request,
3991+ .flash_hw_release = cl_nand_release
3992+};
3993+
3994+#ifdef CONFIG_PROC_FS
3995+/***************************************************************/
3996+/* proc entry /proc/flashdisk implementation */
3997+/***************************************************************/
3998+#include <linux/proc_fs.h>
3999+#include <linux/seq_file.h>
4000+
4001+static void cl_nand_proc_show(struct seq_file *s, struct cl_blkdev *_dev)
4002+{
4003+ struct cl_nand_dev *dev = _dev->hw_private;
4004+
4005+ unsigned long heads, sects, tot_size, cylinders;
4006+ unsigned short sector_size, page_size;
4007+ long read_page_cnt, write_page_cnt, reclaim_cnt;
4008+
4009+ tot_size = dev->logic_get_param(dev->logic, CL_FLASH_TOTAL_SIZE, 0);
4010+ heads = dev->logic_get_param(dev->logic, CL_FLASH_HEADS_NUM, 0);
4011+ sects = dev->logic_get_param(dev->logic, CL_FLASH_SECTOR_SIZE, 0);
4012+ cylinders = dev->logic_get_param(dev->logic, CL_FLASH_CYLINDERS_NUM, 0);
4013+ sector_size = dev->logic_get_param(dev->logic, CL_FLASH_SECTOR_SIZE, 0);
4014+ page_size = dev->logic_get_param(dev->logic, CL_FLASH_PAGE_SIZE, 0);
4015+ read_page_cnt = dev->logic_get_param(dev->logic,
4016+ CL_FLASH_READ_PAGE_CNT, 0);
4017+ write_page_cnt = dev->logic_get_param(dev->logic,
4018+ CL_FLASH_WRITE_PAGE_CNT, 0);
4019+ reclaim_cnt = dev->logic_get_param(dev->logic, CL_FLASH_RECLAIM_CNT, 0);
4020+
4021+
4022+ seq_printf(s, "NAND flash disk:\n");
4023+ seq_printf(s, "\ttotal size: %lu Mbytes (%lu bytes)\n",
4024+ (tot_size >> 20), tot_size);
4025+ seq_printf(s, "\theads: %lu \tcylinders: %lu\tsectors: %lu\n", heads,
4026+ cylinders, sects);
4027+ seq_printf(s, "\tsector: %d\tpage: %d\n", sector_size, page_size);
4028+ seq_printf(s, "Stats:\n");
4029+ seq_printf(s, "\tread: %ld\twritten: %ld\treclaimed: %ld\n",
4030+ read_page_cnt, write_page_cnt, reclaim_cnt);
4031+}
4032+
4033+static int cl_blkdev_proc_show(struct seq_file *s, void *unused)
4034+{
4035+ struct cl_blkdev *dev = s->private;
4036+
4037+ seq_printf(s, "CompuLab flash disks:\n");
4038+ cl_nand_proc_show(s, dev);
4039+
4040+ return 0;
4041+}
4042+
4043+static int cl_blkdev_proc_open(struct inode *inode, struct file *file)
4044+{
4045+ return single_open(file, cl_blkdev_proc_show, PDE(inode)->data);
4046+}
4047+
4048+static struct file_operations proc_ops = {
4049+ .open = cl_blkdev_proc_open,
4050+ .read = seq_read,
4051+ .llseek = seq_lseek,
4052+ .release = single_release,
4053+};
4054+
4055+static const char proc_filename[] = "flashdisk";
4056+
4057+static void cl_blkdev_proc_create_file(struct cl_blkdev *dev)
4058+{
4059+ struct proc_dir_entry *pde;
4060+ pde = create_proc_entry(proc_filename, 0666, NULL);
4061+ if (pde == NULL)
4062+ return;
4063+
4064+ pde->proc_fops = &proc_ops;
4065+ pde->data = dev;
4066+ dev->pde = pde;
4067+}
4068+
4069+static void cl_blkdev_remove_proc_file(struct cl_blkdev *dev)
4070+{
4071+ if (dev->pde)
4072+ remove_proc_entry(proc_filename, NULL);
4073+}
4074+
4075+#else
4076+
4077+#define cl_blkdev_create_proc_file(x) do {} while(0)
4078+#define cl_blkdev_remove_proc_file(x) do {} while(0)
4079+
4080+#endif
4081+
4082+/*******************************************************************/
4083+/* NAND device initialization and cleanup */
4084+/*******************************************************************/
4085+/*
4086+ cl_nand_flash_init:
4087+ - initialize the CL_Logic
4088+ - register the block device and gendisk
4089+
4090+ dev - preallocated cl_nand_dev object
4091+ cl_nand_linux - HW interface
4092+*/
4093+int cl_nand_flash_init(struct cl_nand_dev *dev, cl_nand_map_if *cl_nand_linux)
4094+{
4095+ const char *name = "nand";
4096+ int ret = 0;
4097+ printk ("Nand Flash disk driver, CompuLab");
4098+
4099+ if( wpend )
4100+ printk("NAND Write Protection activated from %ld to %ld.\n",
4101+ wpstart, wpend);
4102+
4103+ if (format)
4104+ printk ("Formatting Nand flash . . .\n");
4105+ dev->logic = dev->logic_create(cl_nand_linux, CACHE_SIZE, format, FLASH_SECTOR);
4106+ if (!dev->logic) {
4107+ printk ("Flash logic couldn't be created.\n");
4108+ return -1;
4109+ }
4110+
4111+ dev->blkdev = kmalloc(sizeof(*dev->blkdev), GFP_KERNEL);
4112+ if ( !dev->blkdev ) {
4113+ return -ENOMEM;
4114+ }
4115+
4116+ dev->blkdev->hw_private = dev;
4117+ if ( (ret = cl_blkdev_init(dev->blkdev, &nand_blkdev_ops, name)) ) {
4118+ printk(KERN_ERR "%s: cl_blkdev initialization failed: %d\n",
4119+ __FUNCTION__, ret);
4120+ dev->logic_free(dev->logic);
4121+ return ret;
4122+ }
4123+
4124+ ret = cl_blkdev_register_disk(dev->blkdev, name,
4125+ dev->logic_get_param(dev->logic,
4126+ CL_FLASH_TOTAL_SIZE,
4127+ 0) / 512);
4128+ if ( ret ) {
4129+ printk(KERN_ERR "%s: NAND disk registration failed: %d\n",
4130+ __FUNCTION__, ret);
4131+ cl_blkdev_unregister(dev->blkdev);
4132+ dev->logic_free(dev->logic);
4133+ return ret;
4134+ }
4135+
4136+ cl_blkdev_proc_create_file(dev->blkdev);
4137+
4138+ return 0;
4139+}
4140+
4141+/*
4142+ cl_nand_flash_cleanup: performs cleanup when driver is no longer used
4143+*/
4144+void cl_nand_flash_cleanup(struct cl_nand_dev * dev)
4145+{
4146+ cl_blkdev_unregister(dev->blkdev);
4147+ if ( dev->logic )
4148+ dev->logic_free(dev->logic);
4149+
4150+ cl_blkdev_remove_proc_file(dev->blkdev);
4151+
4152+ if ( dev->blkdev )
4153+ kfree(dev->blkdev);
4154+}
4155diff --git a/drivers/block/cl_flash/cl_blkdev.h b/drivers/block/cl_flash/cl_blkdev.h
4156new file mode 100644
4157index 0000000..bca1944
4158--- /dev/null
4159+++ b/drivers/block/cl_flash/cl_blkdev.h
4160@@ -0,0 +1,43 @@
4161+#ifndef __CL_BLKDEV_H__
4162+#define __CL_BLKDEV_H__
4163+
4164+struct cl_blkdev;
4165+
4166+struct cl_nand_dev {
4167+ struct cl_blkdev *blkdev;
4168+ cl_logic logic;
4169+ unsigned long last_end_write_cmd;
4170+
4171+ /* CL logic access layer */
4172+ cl_logic (*logic_create)(cl_nand_map_if*, long,
4173+ int, unsigned short);
4174+ void (*logic_free)(cl_logic);
4175+ long (*logic_get_param)(cl_logic, cl_logic_param, long);
4176+ int (*logic_read_page)(cl_logic, long, CLBYTEPTR);
4177+ int (*logic_write_page)(cl_logic, long, CLBYTEPTR);
4178+ void (*logic_on_idle)(cl_logic, int);
4179+ void (*logic_sync)(cl_logic);
4180+ int (*logic_direct_access)(cl_logic,cl_nand_direct_access_type,
4181+ unsigned short, unsigned char, CLBYTEPTR);
4182+};
4183+
4184+extern int cl_nand_flash_init(struct cl_nand_dev *dev, cl_nand_map_if *cl_nand_linux);
4185+extern void cl_nand_flash_cleanup(struct cl_nand_dev * dev);
4186+
4187+#define INIT_NAND_DEV(dev) \
4188+ do { \
4189+ dev->logic = 0; \
4190+ dev->blkdev = 0; \
4191+ dev->last_end_write_cmd = 0; \
4192+ dev->logic_create = cl_logic_create; \
4193+ dev->logic_free = cl_logic_free; \
4194+ dev->logic_get_param = cl_logic_get_param; \
4195+ dev->logic_read_page = cl_logic_read_page; \
4196+ dev->logic_write_page = cl_logic_write_page; \
4197+ dev->logic_on_idle = cl_logic_on_idle; \
4198+ dev->logic_sync = cl_logic_sync; \
4199+ dev->logic_direct_access = cl_logic_direct_access; \
4200+ } while(0)
4201+
4202+
4203+#endif /* __CL_BLKDEV_H__ */
4204diff --git a/drivers/block/cl_flash/cl_common.c b/drivers/block/cl_flash/cl_common.c
4205new file mode 100644
4206index 0000000..a0d2a9c
4207--- /dev/null
4208+++ b/drivers/block/cl_flash/cl_common.c
4209@@ -0,0 +1,52 @@
4210+void cl_zero_mem (void* ptr, long size)
4211+{
4212+ memset (ptr, 0, size);
4213+}
4214+
4215+void cl_ff_mem (void* ptr, long size)
4216+{
4217+ memset (ptr, 0xff, size);
4218+}
4219+void cl_mem_copy (void* dest, void* src, long size)
4220+{
4221+ memcpy (dest, src, size);
4222+}
4223+
4224+int cl_mem_compare (void* mem1, void* mem2, long size)
4225+{
4226+ return memcmp (mem1, mem2, size);
4227+}
4228+
4229+unsigned long cl_get_jiffies (void)
4230+{
4231+ return jiffies;
4232+}
4233+
4234+unsigned long cl_nand_get_max_cache_time (void)
4235+{
4236+ return HZ * 30; /* 30 seconds in cache maximum */
4237+}
4238+
4239+void cl_trace_log ( char* format, ...)
4240+{
4241+#ifdef DO_CL_TRACE_LOG
4242+ char full_msg[300];
4243+ va_list marker;
4244+
4245+ va_start(marker, format);
4246+ vsprintf(full_msg, format, marker);
4247+ printk(full_msg);
4248+ va_end(marker);
4249+#endif
4250+}
4251+
4252+void cl_error_log ( char* format, ...)
4253+{
4254+ char full_msg[300];
4255+ va_list marker;
4256+
4257+ va_start(marker, format);
4258+ vsprintf(full_msg, format, marker);
4259+ printk(full_msg);
4260+ va_end(marker);
4261+}
4262diff --git a/drivers/block/cl_flash/cl_nanddev_x270.c b/drivers/block/cl_flash/cl_nanddev_x270.c
4263new file mode 100644
4264index 0000000..71f05f8
4265--- /dev/null
4266+++ b/drivers/block/cl_flash/cl_nanddev_x270.c
4267@@ -0,0 +1,233 @@
4268+/*
4269+ * drivers/block/cl_flash/cl_nandded_x270.c
4270+ *
4271+ * Flash Disk Driver for CM-X270 platform.
4272+ * Low level device interface implementation
4273+ *
4274+ * Copyright Compulab 2003-2006 (c).
4275+ */
4276+
4277+#include <linux/sched.h>
4278+#include <linux/delay.h>
4279+#include <linux/platform_device.h>
4280+
4281+#include <asm/io.h>
4282+#include <asm/arch/hardware.h>
4283+#include <asm/arch/pxa-regs.h>
4284+#include <asm/arch/cm-x270.h>
4285+
4286+#include "CL_Logic.h"
4287+#include "cl_blkdev.h"
4288+
4289+/* The following macro enables flash activity indication by LEDs */
4290+#undef USE_LEDS
4291+
4292+#define NAND_RB (GPLR2 & (1<<25))
4293+
4294+#define NandCLE (1<<0)
4295+#define NandALE (1<<1)
4296+
4297+/*
4298+ * Values specific to the ARMCore
4299+ */
4300+volatile unsigned long * FLASH_DATA;
4301+volatile unsigned long * FLASH_DATA_ALE;
4302+volatile unsigned long * FLASH_DATA_CLE;
4303+
4304+/* asm-arm/arch-pxa/hardware.h defines UNCACHED_ADDR */
4305+volatile unsigned char * UNC = (volatile unsigned char *)UNCACHED_ADDR;
4306+
4307+/*******************************************************************/
4308+/* CM-X270 NAND HW access layer */
4309+/*******************************************************************/
4310+static inline void nand_cs_on(void)
4311+{
4312+ GPCR0 = 1<<11;
4313+ while( (GPLR0 & (1<<11)) );
4314+}
4315+
4316+static inline void nand_cs_off(void)
4317+{
4318+ unsigned char dummy;
4319+ asm volatile ("mcr p15, 0, r0, c7, c10, 4":::"r0");
4320+ dummy=*UNC;
4321+
4322+ GPSR0 = 1<<11;
4323+ while( !(GPLR0 & (1<<11)) );
4324+}
4325+
4326+static void FlashInitial(void)
4327+{
4328+}
4329+
4330+static void FlashChipSelect (int on, int need_auto_operation)
4331+{
4332+ static int cs_state = -1;
4333+
4334+ if (need_auto_operation)
4335+ on = 1;
4336+
4337+ if (cs_state == on)
4338+ return;
4339+
4340+ cs_state = on;
4341+
4342+ if (on) {
4343+ nand_cs_on();
4344+ }
4345+ else {
4346+ nand_cs_off();
4347+ }
4348+}
4349+
4350+static unsigned char FlashReadByte (unsigned char offset)
4351+{
4352+ return (unsigned char)(*FLASH_DATA >> 16);
4353+}
4354+
4355+static void FlashWriteByte (unsigned char offset, unsigned char data)
4356+{
4357+ if(offset & NandALE) *FLASH_DATA_ALE = (data << 16);
4358+ else if(offset & NandCLE) *FLASH_DATA_CLE = (data << 16);
4359+ else *FLASH_DATA = (data << 16);
4360+}
4361+
4362+static void FlashBlockRead (unsigned char* data, int count)
4363+{
4364+ while (count--)
4365+ *data++ = (unsigned char)(*FLASH_DATA >> 16);
4366+}
4367+
4368+static void FlashBlockWrite ( unsigned char* data, int count)
4369+{
4370+ while (count--)
4371+ *FLASH_DATA = (*data++ << 16);
4372+}
4373+
4374+/* Orange LED used by Linux kernel activity */
4375+static void FlashCoreLeds (short operation, short reclaim)
4376+{
4377+#ifdef USE_LEDS
4378+
4379+#endif
4380+}
4381+
4382+static void do_nothing (void)
4383+{
4384+}
4385+
4386+int nand_delay(unsigned long microseconds)
4387+{
4388+ if ( microseconds < 1000 ) {
4389+ udelay(microseconds);
4390+ return 0;
4391+ }
4392+ udelay(1000);
4393+ udelay(1000);
4394+ udelay(1000);
4395+ return 0;
4396+}
4397+
4398+/* Wait on Ready/Busy signal */
4399+static int RBWait(unsigned long microseconds)
4400+{
4401+ unsigned char dummy;
4402+ int i=0;
4403+
4404+ /* ensure there's no outstanding bus transaction */
4405+ asm volatile ("mcr p15, 0, r0, c7, c10, 4":::"r0");
4406+ dummy=*UNC;
4407+
4408+ /* protect from big delays in R/B GPIO falling edge (or no R/B
4409+ falling edge activity) */
4410+ while((NAND_RB == 1) && (i < 3000)){
4411+ udelay(1);
4412+ i++;
4413+ };
4414+
4415+ if ( i > 0 )
4416+ printk(KERN_DEBUG "%s: No immediate R/B activity\n", __FILE__);
4417+
4418+ if (i == 3000){
4419+ printk(KERN_DEBUG "%s: No R/B activity for 3 ms\n", __FILE__);
4420+ return (0);
4421+ }
4422+
4423+ i=0;
4424+
4425+ /* protect from big delays in R/B GPIO rising edge */
4426+ while((NAND_RB == 0) && (i < 3000)){
4427+ udelay(1);
4428+ i++;
4429+ };
4430+
4431+ if (i == 3000){
4432+ printk(KERN_DEBUG "%s: R/B timed out\n", __FILE__);
4433+ return (0);
4434+ }
4435+
4436+ /* ensure there's no outstanding bus transaction */
4437+ asm volatile ("mcr p15, 0, r0, c7, c10, 4":::"r0");
4438+ dummy=*UNC;
4439+
4440+ return(1);
4441+}
4442+
4443+static cl_nand_map_if cl_nand_linux = {
4444+ .init = FlashInitial,
4445+ .destroy = do_nothing,
4446+ .chip_select = FlashChipSelect,
4447+ .readb = FlashReadByte,
4448+ .writeb = FlashWriteByte,
4449+ .blockread = FlashBlockRead,
4450+ .blockwrite = FlashBlockWrite,
4451+ .activity_leds = FlashCoreLeds,
4452+ .sleep = nand_delay,
4453+ .rbwait = RBWait
4454+};
4455+
4456+static struct cl_nand_dev nand_dev;
4457+
4458+/*
4459+ nand_flash_init:
4460+ - perform board specific initialization
4461+ - initialize NAND device data structure
4462+ - initialize block device layer
4463+*/
4464+static int nand_flash_init (void)
4465+{
4466+ struct cl_nand_dev *dev = &nand_dev;
4467+
4468+ FLASH_DATA = (volatile unsigned long*)ioremap(PXA_CS1_PHYS, 12);
4469+ if (FLASH_DATA == NULL) {
4470+ printk("Bad NAND flash window at %X (already in use)\n", 0x04000000);
4471+ return -1;
4472+ }
4473+ FLASH_DATA_CLE = FLASH_DATA + 1;
4474+ FLASH_DATA_ALE = FLASH_DATA + 2;
4475+
4476+ INIT_NAND_DEV(dev);
4477+ return cl_nand_flash_init(dev, &cl_nand_linux);
4478+}
4479+
4480+#ifdef CONFIG_ARMCORE_NAND
4481+int cl_nand_init_module(void)
4482+{
4483+ return nand_flash_init();
4484+}
4485+
4486+void cl_nand_cleanup_module(void)
4487+{
4488+ struct cl_nand_dev *dev = &nand_dev;
4489+ cl_nand_flash_cleanup(dev);
4490+}
4491+#else
4492+int cl_nand_init_module(void)
4493+{
4494+ return 0;
4495+}
4496+
4497+void cl_nand_cleanup_module(void)
4498+{
4499+}
4500+#endif
4501diff --git a/drivers/block/cl_flash/cl_nordev.c b/drivers/block/cl_flash/cl_nordev.c
4502new file mode 100644
4503index 0000000..c141735
4504--- /dev/null
4505+++ b/drivers/block/cl_flash/cl_nordev.c
4506@@ -0,0 +1,594 @@
4507+/*
4508+ Flash Disk Driver Interface for Linux 2.4.x
4509+ Written by Vova Lifliand
4510+*/
4511+
4512+/* Includes */
4513+#include <linux/module.h>
4514+#include <linux/errno.h>
4515+#include <linux/sched.h>
4516+#include <linux/mm.h>
4517+#include <linux/fs.h>
4518+#include <linux/kernel.h>
4519+#include <linux/timer.h>
4520+#include <linux/genhd.h>
4521+#include <linux/hdreg.h>
4522+#include <linux/ioport.h>
4523+#include <linux/init.h>
4524+#include <linux/devfs_fs_kernel.h>
4525+#include <linux/delay.h>
4526+
4527+#include <asm/system.h>
4528+#include <asm/io.h>
4529+#include <asm/uaccess.h>
4530+
4531+/* Macros for correct linux/blk.h inclusion */
4532+
4533+#define DEVICE_NAME "nor"
4534+
4535+static int major = 0;
4536+
4537+#define FLASH_SECTOR 512
4538+
4539+#include <linux/blkdev.h>
4540+#include <linux/blkpg.h>
4541+
4542+extern void cl_error_log ( char* format, ...);
4543+extern void cl_trace_log ( char* format, ...);
4544+extern void cl_mem_copy (void* dest, void* src, long size);
4545+
4546+
4547+/* Undefine for custom LEDs usage */
4548+#undef USE_LEDS
4549+
4550+/* CrFlash driver interface */
4551+#ifndef FLASH_PLATFORM_LINUX
4552+#define FLASH_PLATFORM_LINUX
4553+#endif
4554+#include "CL_Logic.h"
4555+
4556+typedef unsigned long ULONG;
4557+
4558+/* Forward functions declaration */
4559+static int flash_open (struct inode *inode,struct file *file);
4560+static void do_flash_request (request_queue_t * q);
4561+static int flash_ioctl (struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg);
4562+static int flash_release (struct inode *inode, struct file *file);
4563+
4564+static DECLARE_MUTEX (nor_flash_sem);
4565+static int nor_flash_sem_catched = 0;
4566+
4567+
4568+volatile unsigned short * NorFlashMem;
4569+
4570+static int flash_check_media_change (struct gendisk* dev)
4571+{
4572+/* printk ("flash_check_media_change called.\r\n");*/
4573+ return 0; /* Disk not changed */
4574+}
4575+
4576+static int flash_revalidate (struct gendisk* dev)
4577+{
4578+/* printk ("flash_revalidate called.\r\n");*/
4579+ return 0;
4580+}
4581+
4582+static struct block_device_operations flash_fops =
4583+{
4584+ .owner = THIS_MODULE,
4585+ .open = flash_open,
4586+ .release = flash_release,
4587+ .ioctl = flash_ioctl,
4588+ .media_changed = flash_check_media_change,
4589+ .revalidate_disk = flash_revalidate
4590+};
4591+
4592+static struct gendisk *flash_gendisk;
4593+static spinlock_t flash_lock;
4594+static struct request_queue *flash_queue;
4595+
4596+
4597+#ifdef CONFIG_ARMCORE_NOR
4598+/* nor_flash_init: register the block device number and set up pointer tables */
4599+int __init nor_flash_init (void)
4600+{
4601+ ULONG trash1, trash2, trash3, trash4, TotalSect;
4602+
4603+ /* Request memory for NOR Flash */
4604+ NorFlashMem = (volatile unsigned short*)ioremap (0x00000000, 0x800000);
4605+ if (NorFlashMem == NULL) {
4606+ printk("Bad NOR flash window at %X (already in use)\n", 0x00000000);
4607+ return -1;
4608+ }
4609+
4610+ /* Do flash initialization */
4611+ if (!cl_nor_init_flash()) {
4612+ printk("NOR: Flash initialization failed\n");
4613+ iounmap((void __iomem *)NorFlashMem);
4614+ return -1;
4615+ }
4616+
4617+ spin_lock_init(&flash_lock);
4618+ flash_queue = blk_init_queue(do_flash_request, &flash_lock);
4619+ if(flash_queue == NULL)
4620+ {
4621+ printk ("Could not initialize queue.\r\n");
4622+ iounmap((void __iomem *)NorFlashMem);
4623+ return -1;
4624+ }
4625+ blk_queue_hardsect_size(flash_queue, FLASH_SECTOR);
4626+
4627+ if ((major=register_blkdev (0, DEVICE_NAME)) <= 0)
4628+ {
4629+ printk("flash: Unable to get major number \n");
4630+ iounmap((void __iomem *)NorFlashMem);
4631+ return -1;
4632+ } else printk("Major number received: %d\n", major);
4633+
4634+ /* Insert this disk into linked list of disks */
4635+
4636+ flash_gendisk = alloc_disk(16);
4637+ if (! flash_gendisk) return -ENOMEM;
4638+ flash_gendisk->major = major;
4639+ flash_gendisk->first_minor = 0;
4640+ flash_gendisk->fops = &flash_fops;
4641+ flash_gendisk->private_data=NULL;
4642+ flash_gendisk->queue = flash_queue;
4643+ strcpy(flash_gendisk->disk_name, "nor");
4644+ cl_nor_get_disk_param( &TotalSect, &trash1, &trash2, &trash3, &trash4);
4645+ set_capacity(flash_gendisk, TotalSect);
4646+ add_disk(flash_gendisk);
4647+
4648+ /* Starting flush timer: the cl_timer_proc will be executed on each timer interrupt */
4649+
4650+ return 0;
4651+}
4652+#else
4653+int __init nor_flash_init (void)
4654+{
4655+ return 0;
4656+}
4657+#endif
4658+
4659+/* flash_open: open a device */
4660+static int flash_open (struct inode *inode, struct file *file)
4661+{
4662+
4663+ return 0;
4664+
4665+}
4666+
4667+/* do_flash_request: handle an incoming request */
4668+static void do_flash_request (request_queue_t * q)
4669+{
4670+ u_int block, count;
4671+ int code=1, i;
4672+ struct request* req=NULL;
4673+
4674+ while ((code == 1) && ((req = elv_next_request(q)) != NULL))
4675+ {
4676+ block = req->sector;
4677+ // printk ("req->nr_sectors = %d.\r\n", req->nr_sectors);
4678+ // printk ("req->current_nr_sectors = %d.\r\n", req->current_nr_sectors);
4679+ count = req->current_nr_sectors;
4680+
4681+ nor_flash_sem_catched++;
4682+ down (&nor_flash_sem);
4683+
4684+ switch (rq_data_dir(req)) {
4685+ case 0: // READ
4686+ for (i = 0, code = 1; i < count; i++)
4687+ // printk ("Reading sector %d (of %d).\r\n", block + i, count);
4688+ if (!cl_nor_read_page ( block + i,
4689+ (void *)((char*)req->buffer + i * 512))) {
4690+ // printk ("Reading failed.\r\n");
4691+ code = 0; /* failure */
4692+ break;
4693+ }
4694+ // printk ("Reading completed successfully.\r\n");
4695+ break;
4696+ case 1: // WRITE
4697+ for (i = 0, code = 1; i < count; i++) {
4698+ // printk ("Writing sector %d.\r\n", block + i);
4699+ if (!cl_nor_write_page ( block + i,
4700+ (void *)((char*)req->buffer + i * 512))) {
4701+ // printk ("Writing failed.\r\n");
4702+ code = 0; /* failure */
4703+ break;
4704+ }
4705+ // printk ("Writing completed successfully.\r\n");
4706+ }
4707+ break;
4708+ default:
4709+ printk("do_flash_request: unknown request\n");
4710+ break;
4711+ }
4712+ up (&nor_flash_sem);
4713+ nor_flash_sem_catched--;
4714+ end_request (req, code); /* wrap up, 0 = fail, 1 = success */
4715+ }
4716+}
4717+
4718+/* flash_ioctl: handle device ioctl's */
4719+static int flash_ioctl (struct inode *inode, struct file *file, u_int cmd, u_long arg)
4720+{
4721+ ULONG trash1, trash2, trash3, trash4, TotalSect;
4722+
4723+ // printk ("flash_ioctl called.\r\n");
4724+
4725+ if ((!inode) || !(inode->i_rdev))
4726+ return -EINVAL;
4727+
4728+ cl_nor_get_disk_param( &TotalSect, &trash1, &trash2, &trash3, &trash4);
4729+ // printk ("flash_ioctl in switch.\r\n");
4730+ switch (cmd)
4731+ {
4732+ case HDIO_GETGEO:
4733+ {
4734+ struct hd_geometry *geometry = (struct hd_geometry*)arg;
4735+ if (!geometry)
4736+ return -EINVAL; /* Bad arguments to ioctl */
4737+ put_user(TotalSect / 32 , &geometry->cylinders);
4738+ put_user(1, &geometry->heads);
4739+ put_user(32, &geometry->sectors);
4740+ put_user(2, &geometry->start);
4741+ }
4742+ case BLKGETSIZE:
4743+ if (!arg)
4744+ return -EINVAL;
4745+ return put_user (TotalSect, (long *) arg);
4746+ case HDIO_SET_DMA: /* We don't use DMA for flash. This has no meaning */
4747+ if (!capable (CAP_SYS_ADMIN))
4748+ return -EACCES;
4749+ return 0;
4750+ case HDIO_GET_DMA:
4751+ return put_user( 0, (long *) arg); /* No DMA */
4752+ case HDIO_GET_MULTCOUNT: /* We don't have a limitation of number of sectors in op. */
4753+ return put_user (128, (long *) arg);
4754+ case BLKFLSBUF:
4755+ case BLKROSET:
4756+ case BLKROGET:
4757+ case BLKRASET:
4758+ case BLKRAGET:
4759+ case BLKPG:
4760+
4761+ default:
4762+ return -EINVAL;
4763+ }
4764+}
4765+
4766+/* flash_release: release the device */
4767+static int flash_release (struct inode *inode, struct file *file)
4768+{
4769+
4770+ return 0;
4771+}
4772+
4773+#ifdef CONFIG_ARMCORE_NOR
4774+static void flash_done (void)
4775+{
4776+ del_gendisk(flash_gendisk);
4777+ put_disk(flash_gendisk);
4778+ blk_cleanup_queue(flash_queue);
4779+
4780+ /* Free memory allocated by flash module */
4781+ cl_nor_free_mem ();
4782+
4783+ unregister_blkdev (major, DEVICE_NAME);
4784+}
4785+#else
4786+static void flash_done (void)
4787+{
4788+}
4789+#endif
4790+
4791+extern int cl_nand_init_module(void);
4792+extern void cl_nand_cleanup_module(void);
4793+
4794+int flash_init_module(void)
4795+{
4796+ int error;
4797+
4798+ error = cl_nand_init_module();
4799+ if (error) return error;
4800+
4801+ error = nor_flash_init();
4802+ if (error) return error;
4803+
4804+ return 0;
4805+}
4806+
4807+void flash_cleanup_module(void)
4808+{
4809+ flash_done();
4810+ cl_nand_cleanup_module();
4811+}
4812+
4813+module_init (flash_init_module);
4814+module_exit (flash_cleanup_module);
4815+
4816+//-------------------- CMNLIN.C ---------
4817+
4818+#define TRUE 1
4819+#define FALSE 0
4820+
4821+#define FL_CLKS_PER_SEC 182
4822+
4823+#define NAND_HEAP_SIZE 64000 /* bytes */
4824+#define NOR_HEAP_SIZE 50000 /* bytes */
4825+
4826+/* NOR Flash constants */
4827+#define NorFlashBlockSize 0x10000L /* 64 KB */
4828+#define NorFlashDiskPagesPerBlock 127
4829+
4830+#define NOR_DRIVE_STARTING_BLOCK 27
4831+
4832+/* NOR Flash Functions Support */
4833+
4834+/* Constructor / destructor */
4835+static void Nor_Create(void);
4836+/* Basic operations */
4837+static void Nor_EnableFlashMap(int EnableFlag);
4838+static unsigned long Nor_GetSize(void);
4839+static int Nor_GetPagesPerBlock(void);
4840+static int Nor_ReadHeader (unsigned short BlockN, cl_nor_block_header* Header);
4841+static int Nor_ReadPage (unsigned short BlockN, unsigned char PageNum, CLBYTEPTR DestBuff);
4842+static int Nor_SetBlockState(unsigned short BlockN, unsigned short Signature,
4843+ unsigned short State, unsigned short Reserved);
4844+static int Nor_InvalidatePage(unsigned short BlockN, unsigned char PageN);
4845+static int Nor_WritePage(unsigned short BlockN, unsigned char PageN,
4846+ CLBYTEPTR PageData, unsigned short PageIndex);
4847+static int Nor_EraseBlock(unsigned short BlockN);
4848+
4849+extern volatile unsigned short * NorFlashMem;
4850+unsigned char Nor_IntelFlash;
4851+
4852+void Nor_EmptyFunc(void){};
4853+
4854+cl_nor_flash_access NorFlashAccess =
4855+ {
4856+ Nor_Create,
4857+ Nor_EmptyFunc, /*NULL,*/ /* Destructor not needed */
4858+ Nor_GetSize,
4859+ Nor_EnableFlashMap,
4860+ Nor_GetPagesPerBlock,
4861+ Nor_ReadHeader,
4862+ Nor_ReadPage,
4863+ Nor_SetBlockState,
4864+ Nor_InvalidatePage,
4865+ Nor_WritePage,
4866+ Nor_EraseBlock,
4867+ };
4868+
4869+/* Driver see NOR Flash Blocks as linear, while there are BIOS holes */
4870+static int Nor_GetPhysBlockIndex (int BlockN)
4871+{
4872+ return (BlockN + NOR_DRIVE_STARTING_BLOCK);
4873+}
4874+
4875+static void NorWrWord(unsigned long index, unsigned short data)
4876+{
4877+ *(NorFlashMem+index)=data;
4878+}
4879+extern void NorWrWord(unsigned long index, unsigned short data);
4880+
4881+static unsigned short NorRdWord(unsigned long index)
4882+{
4883+ return *(NorFlashMem+index);
4884+}
4885+
4886+static unsigned char Nor_OutAMDCommand(unsigned short command)
4887+{
4888+ NorWrWord(0x555, 0xAAAA);
4889+ NorWrWord(0x2AA, 0x5555);
4890+ NorWrWord(0x555, command);
4891+ return TRUE;
4892+}
4893+
4894+
4895+static void Nor_Create(void)
4896+{
4897+ /* Nothing should be done here - all services are provided by BIOS */
4898+}
4899+
4900+static unsigned long Nor_GetSize(void)
4901+{
4902+ unsigned long NorFlashSize = 0x100000;
4903+ unsigned short n;
4904+/* unsigned long i; */
4905+
4906+ /* Determine flash type */
4907+ NorWrWord(0, 0xFFFF);
4908+ NorWrWord(0, 0x9090);
4909+ if(NorRdWord(0) == 0x89)
4910+ Nor_IntelFlash = TRUE;
4911+ else Nor_IntelFlash = FALSE;
4912+ NorWrWord(0, 0xFFFF);
4913+
4914+ /* Query flash size */
4915+ /* 1. Do reset command */
4916+ NorWrWord(0, 0xF0F0); /* was 0f0f */
4917+ NorWrWord(0, 0xFFFF); /* Will also reset intel flash */
4918+ /* 2. Enter CFI mode */
4919+ NorWrWord(0x55, 0x9898);
4920+ /* 3. Read flash size */
4921+/* READ WHOLE CFI for (i=10; i<0x3D; i++){
4922+ n = NorRdWord(i);
4923+ printk("CFI n=%x\n", n);} */
4924+ n = NorRdWord(0x27);
4925+ /* 4. Do reset again - exit CFI mode */
4926+ NorWrWord(0, 0xF0F0); /* was 0f0f */
4927+ NorWrWord(0, 0xFFFF); /* Will also reset intel flash */
4928+ /* Exclude BIOS area */
4929+ if((n>0x17) | (n<0x14)) n=0x14; // if detection is unsuccessfull (no CFI) default to 1MB
4930+ NorFlashSize = (1 << n); /* 2 ^ n */
4931+
4932+ cl_error_log("NOR Flash (%s) size: %d MB total\n",(Nor_IntelFlash ? "Intel" : "AMD"),NorFlashSize / (1024 * 1024));
4933+
4934+ if(NorFlashSize == (1024 * 1024)) {
4935+ cl_error_log("1Mb flash not supported!\n");
4936+ return 0;
4937+ }
4938+
4939+ return NorFlashSize -= NOR_DRIVE_STARTING_BLOCK * 64L * 1024L; /*exclude BIOS and jump areas, spareblocks etc.*/
4940+}
4941+
4942+/* Remaps or unmaps MMS windows, allocated by flash */
4943+static void Nor_EnableFlashMap (int EnableFlag)
4944+{
4945+ /* Just to prevent warning */
4946+ int x = EnableFlag;
4947+ EnableFlag = x;
4948+ /* Nothing should be done here - all services are provided by BIOS */
4949+}
4950+
4951+static int Nor_GetPagesPerBlock(void)
4952+{
4953+ return NorFlashDiskPagesPerBlock;
4954+}
4955+
4956+static int Nor_ReadHeader (unsigned short BlockN, cl_nor_block_header* Header)
4957+{
4958+
4959+ cl_mem_copy (Header,
4960+ (char*)(NorFlashMem + (0x8000 * Nor_GetPhysBlockIndex(BlockN))),
4961+ (sizeof (cl_nor_block_header) + 1) & 0xFFFE);
4962+ return 1;
4963+}
4964+
4965+static int Nor_ReadPage (unsigned short BlockN, unsigned char PageNum, CLBYTEPTR DestBuff)
4966+{
4967+ cl_mem_copy (DestBuff,
4968+ (char*)(NorFlashMem + (0x8000 * Nor_GetPhysBlockIndex(BlockN)) +
4969+ ((PageNum + 1) * (CL_NOR_FLASH_PAGE_SIZE / 2))),
4970+ CL_NOR_FLASH_PAGE_SIZE);
4971+ return 1;
4972+}
4973+
4974+static int Nor_EraseBlock(unsigned short BlockN)
4975+{
4976+ unsigned long addr;
4977+ unsigned short dummy;
4978+
4979+ addr=(Nor_GetPhysBlockIndex(BlockN)*NorFlashBlockSize)/2;
4980+ if(Nor_IntelFlash)
4981+ { /* Erase block sequence from Intel flash */
4982+ NorWrWord(addr, 0xFFFF);
4983+ NorWrWord(addr, 0x7070);
4984+ NorWrWord(addr, 0x2020);
4985+ NorWrWord(addr, 0xD0D0);
4986+ NorWrWord(addr, 0xD0D0);
4987+ while(!(NorRdWord(addr) & 128))
4988+ ;
4989+ NorWrWord(0, 0xFFFF);
4990+ return TRUE;
4991+ }
4992+ else
4993+ {
4994+ /* Do "erase block" commands sequence */
4995+ if(!Nor_OutAMDCommand(0xF0F0)) return FALSE;
4996+ dummy = NorRdWord(addr); /* read and discard */
4997+ if(!Nor_OutAMDCommand(0x8080)) return FALSE;
4998+ NorWrWord(0x555, 0xAAAA);
4999+ NorWrWord(0x2AA, 0x5555);
5000+ NorWrWord(addr, 0x3030);
5001+
5002+ /* Waiting block is erased - no timeout here */
5003+ while(TRUE)
5004+ {
5005+ /* Stall processor execution for about 20 microseconds <--- it is much less */
5006+ for(dummy = 0; dummy < 20; dummy++)
5007+ ;
5008+ /* Check if ready */
5009+ if(NorRdWord(addr) == 0xFFFF)
5010+ return TRUE;
5011+ }
5012+ }
5013+}
5014+
5015+static int Nor_SetWord (unsigned long ofs, unsigned short word)
5016+{
5017+ unsigned short timeout = 0xFFF;
5018+ unsigned long addr;
5019+ addr = ((Nor_GetPhysBlockIndex (ofs >> 15))<<15)+(ofs&0x7FFF);// 15 because address is given for word argument
5020+ /* The address should be word aligned since accessing by word and not by byte */
5021+
5022+ if(Nor_IntelFlash)
5023+ { /* Write sequence from Intel flash */
5024+ NorWrWord(addr, 0x4040);
5025+ NorWrWord(addr, word);
5026+ while(timeout--)
5027+ udelay(1);
5028+ if(NorRdWord(addr) & 128)
5029+ {
5030+ unsigned char res = !(NorRdWord(addr) & 16);
5031+ NorWrWord(addr, 0x5050);
5032+ NorWrWord(addr, 0xFFFF);
5033+ return res;
5034+ }
5035+ NorWrWord(0, 0x5050);
5036+ }
5037+ else
5038+ { /* Write sequence from AMD flash */
5039+ /* Output command is a necessary sequence to write word */
5040+ if(!Nor_OutAMDCommand(0xA0A0))
5041+ return FALSE;
5042+
5043+ /* Write data */
5044+ NorWrWord(addr, word);
5045+ /* Wait data written */
5046+ while(timeout--) {
5047+ udelay(1);
5048+ if(NorRdWord(addr) == word)
5049+ return TRUE;
5050+ }
5051+ }
5052+ /* Failure */
5053+ cl_error_log("ERROR: SetWord timeout.");
5054+
5055+ return FALSE;
5056+}
5057+
5058+static int Nor_SetBlockState(unsigned short BlockN, unsigned short Signature,
5059+ unsigned short State, unsigned short Reserved)
5060+{
5061+ return Nor_SetWord ((BlockN * NorFlashBlockSize + 0)/2, Signature) &&
5062+ Nor_SetWord ((BlockN * NorFlashBlockSize + 2)/2, State) &&
5063+ Nor_SetWord ((BlockN * NorFlashBlockSize + 26 + 127 * 2)/2, Reserved);
5064+}
5065+
5066+static int Nor_InvalidatePage (unsigned short BlockN, unsigned char PageN)
5067+{
5068+ return Nor_SetWord ((BlockN * NorFlashBlockSize + 6 + 2 * PageN)/2, 0);
5069+}
5070+
5071+static int Nor_WritePage (unsigned short BlockN, unsigned char PageN,
5072+ CLBYTEPTR PageData, unsigned short PageIndex)
5073+{
5074+ int words_left, dest_addr;
5075+ unsigned short* ptr;
5076+
5077+ /* Write index to first page - header information */
5078+ if(!Nor_SetWord((BlockN * NorFlashBlockSize + 6 + 2 * PageN)/2, PageIndex))
5079+ {
5080+ cl_error_log("A");
5081+ return FALSE; /* Couldn't write page index */
5082+ }
5083+
5084+ /* Write page data */
5085+ words_left = (512 >> 1); /* Write by word */
5086+ dest_addr = BlockN * NorFlashBlockSize + (PageN + 1) * 512;
5087+ ptr = (unsigned short*)PageData;
5088+ while(words_left--)
5089+ {
5090+ if(!Nor_SetWord(dest_addr/2, *ptr++))
5091+ {
5092+ cl_error_log("B");
5093+ return FALSE; /* Page data writing failure */
5094+ }
5095+ dest_addr += 2; /* Write by word (2 bytes each write command) */
5096+ }
5097+
5098+ return TRUE;
5099+}
5100+
5101diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
5102index 05ba410..a820db0 100644
5103--- a/drivers/char/Kconfig
5104+++ b/drivers/char/Kconfig
5105@@ -1020,5 +1020,11 @@ config TELCLOCK
5106 sysfs directory, /sys/devices/platform/telco_clock, with a number of
5107 files for controlling the behavior of this hardware.
5108
5109+
5110+config EMV3020_RTC
5111+ tristate "EM-V3020 RTC"
5112+ ---help---
5113+ Support for EM Microelectronics V3020 RTC
5114+
5115 endmenu
5116
5117diff --git a/drivers/char/Makefile b/drivers/char/Makefile
5118index 503dd90..625bfd9 100644
5119--- a/drivers/char/Makefile
5120+++ b/drivers/char/Makefile
5121@@ -49,6 +49,7 @@ obj-$(CONFIG_VIOCONS) += viocons.o
5122 obj-$(CONFIG_VIOTAPE) += viotape.o
5123 obj-$(CONFIG_HVCS) += hvcs.o
5124 obj-$(CONFIG_SGI_MBCS) += mbcs.o
5125+obj-$(CONFIG_EMV3020_RTC) += emv3020.o
5126
5127 obj-$(CONFIG_PRINTER) += lp.o
5128 obj-$(CONFIG_TIPAR) += tipar.o
5129diff --git a/drivers/char/emv3020.c b/drivers/char/emv3020.c
5130new file mode 100644
5131index 0000000..df7f1a4
5132--- /dev/null
5133+++ b/drivers/char/emv3020.c
5134@@ -0,0 +1,365 @@
5135+/*
5136+ * emv3020.c
5137+ *
5138+ * Driver for EMV3020 RTC
5139+ *
5140+ * Copyright (C) 2006 Compulab Ltd.
5141+ *
5142+ *
5143+ * This program is free software; you can redistribute it and/or modify
5144+ * it under the terms of the GNU General Public License version 2 as
5145+ * published by the Free Software Foundation.
5146+ *
5147+ *
5148+ */
5149+
5150+#include <linux/module.h>
5151+#include <linux/fs.h>
5152+#include <linux/string.h>
5153+#include <linux/init.h>
5154+#include <linux/platform_device.h>
5155+#include <linux/interrupt.h>
5156+#include <linux/rtc.h>
5157+#include <linux/bcd.h>
5158+#include <linux/clk.h>
5159+
5160+#include <asm/hardware.h>
5161+#include <asm/uaccess.h>
5162+#include <asm/io.h>
5163+#include <asm/irq.h>
5164+#include <asm/rtc.h>
5165+
5166+#include <asm/hardware.h>
5167+#include <asm/delay.h>
5168+
5169+#define EMV3020_VA_RTC emv3020_rtc_base
5170+
5171+static struct resource *emv3020_rtc_mem;
5172+static void __iomem *emv3020_rtc_base;
5173+
5174+#define DEBUG 0
5175+#if DEBUG
5176+static unsigned int rtc_debug = DEBUG;
5177+#else
5178+#define rtc_debug 0 /* gcc will remove all the debug code for us */
5179+#endif
5180+
5181+static void emv3020_set_reg(unsigned char address, unsigned char data)
5182+{
5183+ int i;
5184+
5185+ for ( i = 0; i < 4; i++ )
5186+ writel((address << (16-i)), EMV3020_VA_RTC);
5187+
5188+ if ( address < 0xe)
5189+ for ( i = 0; i < 8; i++)
5190+ writel((data << (16-i)), EMV3020_VA_RTC);
5191+}
5192+
5193+static unsigned char emv3020_get_reg(unsigned char address)
5194+{
5195+ unsigned int data=0;
5196+ int i, tmp;
5197+
5198+ for ( i = 0; i < 4; i++ )
5199+ writel((address << (16-i)), EMV3020_VA_RTC);
5200+
5201+ for ( i = 0; i < 8; i++ ) {
5202+ tmp = readl(EMV3020_VA_RTC);
5203+ data |= ((tmp & 0x10000) >> (16 - i));
5204+ }
5205+
5206+ return data;
5207+}
5208+
5209+static int emv3020_detect(struct device *dev)
5210+{
5211+ int i;
5212+ int temp;
5213+
5214+ for ( i=0; i<8; i++)
5215+ temp = readl(EMV3020_VA_RTC);
5216+
5217+ emv3020_set_reg(0x2, 0x33);
5218+
5219+ if ( emv3020_get_reg(0x2) == 0x33 ) {
5220+ emv3020_set_reg(0x0, 0x0);
5221+ return 0;
5222+ }
5223+
5224+ return -ENODEV;
5225+}
5226+
5227+static int emv3020_rtc_gettime(struct rtc_time *dt)
5228+{
5229+ int ret=0;
5230+
5231+ emv3020_set_reg(0x0F, 0);
5232+
5233+ dt->tm_sec = emv3020_get_reg(0x02);
5234+ dt->tm_min = emv3020_get_reg(0x03);
5235+ dt->tm_hour = emv3020_get_reg(0x04);
5236+ dt->tm_mday = emv3020_get_reg(0x05);
5237+ dt->tm_mon = emv3020_get_reg(0x06);
5238+ dt->tm_wday = emv3020_get_reg(0x08);
5239+ dt->tm_year = emv3020_get_reg(0x07);
5240+
5241+ BCD_TO_BIN(dt->tm_sec);
5242+ BCD_TO_BIN(dt->tm_min);
5243+ BCD_TO_BIN(dt->tm_hour);
5244+ BCD_TO_BIN(dt->tm_mday);
5245+ BCD_TO_BIN(dt->tm_mon);
5246+ BCD_TO_BIN(dt->tm_wday);
5247+ BCD_TO_BIN(dt->tm_year);
5248+ dt->tm_year += 100;
5249+
5250+ if(rtc_debug)printk("\n%s : Read RTC values\n",__FUNCTION__);
5251+ if(rtc_debug)printk("tm_hour: %i\n",dt->tm_hour);
5252+ if(rtc_debug)printk("tm_min : %i\n",dt->tm_min);
5253+ if(rtc_debug)printk("tm_sec : %i\n",dt->tm_sec);
5254+ if(rtc_debug)printk("tm_year: %i\n",dt->tm_year);
5255+ if(rtc_debug)printk("tm_mon : %i\n",dt->tm_mon);
5256+ if(rtc_debug)printk("tm_mday: %i\n",dt->tm_mday);
5257+ if(rtc_debug)printk("tm_wday: %i\n",dt->tm_wday);
5258+
5259+ return ret;
5260+}
5261+
5262+static int emv3020_rtc_settime(struct rtc_time *dt)
5263+{
5264+ if(rtc_debug)printk("\n%s : Setting RTC values\n",__FUNCTION__);
5265+ if(rtc_debug)printk("tm_sec : %i\n",dt->tm_sec);
5266+ if(rtc_debug)printk("tm_min : %i\n",dt->tm_min);
5267+ if(rtc_debug)printk("tm_hour: %i\n",dt->tm_hour);
5268+ if(rtc_debug)printk("tm_mday: %i\n",dt->tm_mday);
5269+ if(rtc_debug)printk("tm_wday: %i\n",dt->tm_wday);
5270+ if(rtc_debug)printk("tm_year: %i\n",dt->tm_year);
5271+
5272+ dt->tm_year %= 100;
5273+ BIN_TO_BCD(dt->tm_sec);
5274+ BIN_TO_BCD(dt->tm_min);
5275+ BIN_TO_BCD(dt->tm_hour);
5276+ BIN_TO_BCD(dt->tm_mday);
5277+ BIN_TO_BCD(dt->tm_mon);
5278+ BIN_TO_BCD(dt->tm_wday);
5279+ BIN_TO_BCD(dt->tm_year);
5280+
5281+ emv3020_set_reg(0x02, dt->tm_sec);
5282+ emv3020_set_reg(0x03, dt->tm_min);
5283+ emv3020_set_reg(0x04, dt->tm_hour);
5284+ emv3020_set_reg(0x05, dt->tm_mday);
5285+ emv3020_set_reg(0x06, dt->tm_mon);
5286+ emv3020_set_reg(0x08, dt->tm_wday);
5287+ emv3020_set_reg(0x07, dt->tm_year);
5288+
5289+ emv3020_set_reg(0x0E, 0);
5290+
5291+ return 0;
5292+}
5293+
5294+static int emv3020_rtc_open(void)
5295+{
5296+ return 0;
5297+}
5298+
5299+static void emv3020_rtc_release(void)
5300+{
5301+}
5302+
5303+static int emv3020_rtc_ioctl(unsigned int cmd, unsigned long arg)
5304+{
5305+ struct rtc_time wtime;
5306+ int status = 0;
5307+
5308+ switch (cmd) {
5309+ default:
5310+ case RTC_UIE_ON:
5311+ case RTC_UIE_OFF:
5312+ case RTC_PIE_ON:
5313+ case RTC_PIE_OFF:
5314+ case RTC_AIE_ON:
5315+ case RTC_AIE_OFF:
5316+ case RTC_ALM_SET:
5317+ case RTC_ALM_READ:
5318+ case RTC_IRQP_READ:
5319+ case RTC_IRQP_SET:
5320+ case RTC_EPOCH_READ:
5321+ case RTC_EPOCH_SET:
5322+ case RTC_WKALM_SET:
5323+ case RTC_WKALM_RD:
5324+ status = -EINVAL;
5325+ break;
5326+
5327+ case RTC_RD_TIME:
5328+ emv3020_rtc_gettime(&wtime);
5329+ if( copy_to_user((void *)arg, &wtime,
5330+ sizeof (struct rtc_time)))
5331+ status = -EFAULT;
5332+ break;
5333+
5334+ case RTC_SET_TIME:
5335+ if (!capable(CAP_SYS_TIME)) {
5336+ status = -EACCES;
5337+ break;
5338+ }
5339+
5340+ if (copy_from_user(&wtime, (struct rtc_time *)arg,
5341+ sizeof(struct rtc_time)) ) {
5342+ status = -EFAULT;
5343+ break;
5344+ }
5345+
5346+ emv3020_rtc_settime(&wtime);
5347+ break;
5348+ }
5349+
5350+ return status;
5351+}
5352+
5353+static char *emv3020_mon2str(unsigned int mon)
5354+{
5355+ char *mon2str[12] = {
5356+ "Jan", "Feb", "Mar", "Apr", "May", "Jun",
5357+ "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
5358+ };
5359+ if( mon > 11) return "error";
5360+ else return mon2str[ mon];
5361+}
5362+
5363+static int emv3020_rtc_proc( char *buf)
5364+{
5365+ char *p = buf;
5366+ struct rtc_time dt;
5367+
5368+ emv3020_rtc_gettime(&dt);
5369+
5370+ p += sprintf(p, "\nEMV3020 (Real Time Clock)\n");
5371+ p += sprintf(p, "Date/Time : %02d-%s-%04d %02d:%02d:%02d\n",
5372+ dt.tm_mday,
5373+ emv3020_mon2str(dt.tm_mon),
5374+ dt.tm_year+1900,
5375+ dt.tm_hour,
5376+ dt.tm_min,
5377+ dt.tm_sec);
5378+ return p - buf;
5379+}
5380+
5381+static struct rtc_ops emv3020_rtcops = {
5382+ .owner = THIS_MODULE,
5383+ .open = emv3020_rtc_open,
5384+ .release = emv3020_rtc_release,
5385+ .ioctl = emv3020_rtc_ioctl,
5386+ .read_time = emv3020_rtc_gettime,
5387+ .set_time = emv3020_rtc_settime,
5388+ .read_alarm = 0,
5389+ .set_alarm = 0,
5390+ .proc = emv3020_rtc_proc,
5391+};
5392+
5393+static int emv3020_rtc_remove(struct device *dev)
5394+{
5395+ unregister_rtc(&emv3020_rtcops);
5396+
5397+ if (emv3020_rtc_mem != NULL) {
5398+ pr_debug("emv3020_rtc: releasing emv3020_rtc_mem\n");
5399+ iounmap(emv3020_rtc_base);
5400+ release_resource(emv3020_rtc_mem);
5401+ }
5402+
5403+ return 0;
5404+}
5405+
5406+static int emv3020_rtc_probe(struct device *dev)
5407+{
5408+ struct platform_device *pdev = to_platform_device(dev);
5409+ struct resource *res;
5410+ int ret;
5411+
5412+ pr_debug("%s: probe=%p, device=%p\n", __FUNCTION__, pdev, dev);
5413+
5414+ /* get the memory region */
5415+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5416+ if (res == NULL) {
5417+ dev_err(dev, "failed to get memory region resource\n");
5418+ return -ENOENT;
5419+ }
5420+
5421+ emv3020_rtc_mem = request_mem_region(res->start,
5422+ res->end - res->start + 1,
5423+ pdev->name);
5424+
5425+ if (emv3020_rtc_mem == NULL) {
5426+ dev_err(dev, "failed to reserve memory region\n");
5427+ ret = -ENOENT;
5428+ goto exit_err;
5429+ }
5430+
5431+ emv3020_rtc_base = ioremap(res->start, res->end - res->start + 1);
5432+ if (emv3020_rtc_base == NULL) {
5433+ dev_err(dev, "failed ioremap()\n");
5434+ ret = -EINVAL;
5435+ goto exit_err;
5436+ }
5437+
5438+ emv3020_rtc_mem = res;
5439+ pr_debug("emv3020_rtc_base=%p\n", emv3020_rtc_base);
5440+
5441+ /* check to see if everything is setup correctly */
5442+ if ( (ret = emv3020_detect(dev)) != 0 ) {
5443+ iounmap(emv3020_rtc_base);
5444+ release_resource(emv3020_rtc_mem);
5445+ goto exit_err;
5446+ }
5447+
5448+ /* register RTC and exit */
5449+ register_rtc(&emv3020_rtcops);
5450+
5451+ return 0;
5452+
5453+ exit_err:
5454+ dev_err(dev, "error %d during initialisation\n", ret);
5455+
5456+ return ret;
5457+}
5458+
5459+#ifdef CONFIG_PM
5460+/* EMV3020 RTC Power management control */
5461+static int emv3020_rtc_suspend(struct device *dev, pm_message_t state)
5462+{
5463+ return 0;
5464+}
5465+
5466+static int emv3020_rtc_resume(struct device *dev)
5467+{
5468+ return 0;
5469+}
5470+#else
5471+#define emv3020_rtc_suspend NULL
5472+#define emv3020_rtc_resume NULL
5473+#endif
5474+
5475+static struct device_driver emv3020_rtcdrv = {
5476+ .name = "emv3020-rtc",
5477+ .bus = &platform_bus_type,
5478+ .probe = emv3020_rtc_probe,
5479+ .remove = emv3020_rtc_remove,
5480+ .suspend = emv3020_rtc_suspend,
5481+ .resume = emv3020_rtc_resume,
5482+};
5483+
5484+static __init int emv3020_init(void)
5485+{
5486+ return driver_register(&emv3020_rtcdrv);
5487+}
5488+
5489+static __exit void emv3020_exit(void)
5490+{
5491+ driver_unregister(&emv3020_rtcdrv);
5492+}
5493+
5494+module_init(emv3020_init);
5495+module_exit(emv3020_exit);
5496+
5497+
5498+MODULE_AUTHOR ("Compulab Ltd.");
5499+MODULE_LICENSE ("GPL");
5500diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
5501index d633081..5e7f6ee 100644
5502--- a/drivers/ide/Kconfig
5503+++ b/drivers/ide/Kconfig
5504@@ -850,6 +850,13 @@ config BLK_DEV_IDE_BAST
5505 Say Y here if you want to support the onboard IDE channels on the
5506 Simtec BAST or the Thorcom VR1000
5507
5508+config BLK_DEV_IDE_CM_X270
5509+ tristate "CompuLab CM-X270 IDE support"
5510+ depends on ARM && (MACH_ARMCORE)
5511+ help
5512+ Say Y here if you want to support the onboard IDE channels on the
5513+ CompuLab CM-X270 module
5514+
5515 config BLK_DEV_GAYLE
5516 bool "Amiga Gayle IDE interface support"
5517 depends on AMIGA
5518diff --git a/drivers/ide/arm/Makefile b/drivers/ide/arm/Makefile
5519index 6a78f07..e5cadb7 100644
5520--- a/drivers/ide/arm/Makefile
5521+++ b/drivers/ide/arm/Makefile
5522@@ -2,5 +2,6 @@
5523 obj-$(CONFIG_BLK_DEV_IDE_ICSIDE) += icside.o
5524 obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapide.o
5525 obj-$(CONFIG_BLK_DEV_IDE_BAST) += bast-ide.o
5526+obj-$(CONFIG_BLK_DEV_IDE_CM_X270) += cm-x270-ide.o
5527
5528 EXTRA_CFLAGS := -Idrivers/ide
5529diff --git a/drivers/ide/arm/cm-x270-ide.c b/drivers/ide/arm/cm-x270-ide.c
5530new file mode 100644
5531index 0000000..ba0904c
5532--- /dev/null
5533+++ b/drivers/ide/arm/cm-x270-ide.c
5534@@ -0,0 +1,113 @@
5535+/* linux/drivers/ide/arm/bast-ide.c
5536+ *
5537+ * Copyright (c) 2003-2004 Simtec Electronics
5538+ * Ben Dooks <ben@simtec.co.uk>
5539+ *
5540+ * This program is free software; you can redistribute it and/or modify
5541+ * it under the terms of the GNU General Public License version 2 as
5542+ * published by the Free Software Foundation.
5543+ *
5544+*/
5545+
5546+#include <linux/module.h>
5547+#include <linux/errno.h>
5548+#include <linux/ide.h>
5549+#include <linux/init.h>
5550+
5551+#include <asm/mach-types.h>
5552+
5553+#include <asm/io.h>
5554+#include <asm/irq.h>
5555+#include <asm/arch/pxa-regs.h>
5556+#include <asm/arch/cm-x270.h>
5557+
5558+/* list of registered interfaces */
5559+static ide_hwif_t *ifs[1];
5560+
5561+static int __init
5562+cmx270_register(unsigned int base, unsigned int aux, int irq,
5563+ ide_hwif_t **hwif)
5564+{
5565+ hw_regs_t hw;
5566+
5567+ memset(&hw, 0, sizeof(hw));
5568+
5569+ if(!base || !aux) return -EINVAL;
5570+
5571+ printk(KERN_DEBUG "%s: base = %08x, aux = %08x\n", __FUNCTION__,
5572+ base, aux);
5573+
5574+ // Different mappings for local bus IDE and PCMCIA IDE
5575+ if(base == CMX270_IDECS0_VIRT) {
5576+#ifdef CONFIG_ARMCORE_SB270
5577+ hw.io_ports[IDE_DATA_OFFSET] = base + 0;
5578+ hw.io_ports[IDE_ERROR_OFFSET] = base + (0x1<<3);
5579+ hw.io_ports[IDE_NSECTOR_OFFSET]= base + (0x2<<3);
5580+ hw.io_ports[IDE_SECTOR_OFFSET]= base + (0x3<<3);
5581+ hw.io_ports[IDE_LCYL_OFFSET]= base + (0x4<<3);
5582+ hw.io_ports[IDE_HCYL_OFFSET]= base + (0x5<<3);
5583+ hw.io_ports[IDE_SELECT_OFFSET]= base + (0x6<<3);
5584+ hw.io_ports[IDE_STATUS_OFFSET]= base + (0x7<<3);
5585+
5586+ hw.io_ports[IDE_CONTROL_OFFSET] = aux+(0x6<<3);
5587+#else
5588+ hw.io_ports[IDE_DATA_OFFSET] = base + 0;
5589+ hw.io_ports[IDE_ERROR_OFFSET] = base + 8;
5590+ hw.io_ports[IDE_NSECTOR_OFFSET]= base + 2;
5591+ hw.io_ports[IDE_SECTOR_OFFSET]= base + 10;
5592+ hw.io_ports[IDE_LCYL_OFFSET]= base + 4;
5593+ hw.io_ports[IDE_HCYL_OFFSET]= base + 12;
5594+ hw.io_ports[IDE_SELECT_OFFSET]= base + 6; //6;
5595+ hw.io_ports[IDE_STATUS_OFFSET]= base + 14;
5596+
5597+ hw.io_ports[IDE_CONTROL_OFFSET] = (aux+0x6);
5598+#endif
5599+ } else {
5600+ printk(KERN_DEBUG "%s: registering wrong IDE i/f\n", __FUNCTION__);
5601+ hw.io_ports[IDE_DATA_OFFSET] = base + 8;
5602+ hw.io_ports[IDE_ERROR_OFFSET] = base + 13;
5603+ hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
5604+ hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
5605+ hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
5606+ hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
5607+ hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
5608+ hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
5609+
5610+ hw.io_ports[IDE_CONTROL_OFFSET] = aux;
5611+ }
5612+
5613+ hw.irq = irq;
5614+
5615+ ide_register_hw(&hw, hwif);
5616+
5617+ return 0;
5618+}
5619+
5620+static int __init cmx270_init(void)
5621+{
5622+ if (!(machine_is_armcore()))
5623+ return 0;
5624+
5625+ printk("CM-X270: IDE driver, (c) 2003-2006 CompuLab Ltd\n");
5626+
5627+ MSC1 = 0x7ffc7ff4;
5628+
5629+ /* Interrupts on rising edge: lines are inverted before they get to
5630+ the PXA */
5631+ pxa_gpio_mode(IRQ_TO_GPIO(CMX270_IDE_IRQ));
5632+
5633+#ifdef CONFIG_ARMCORE_SB270
5634+ set_irq_type(CMX270_IDE_IRQ, IRQT_RISING);
5635+#else
5636+ set_irq_type(CMX270_IDE_IRQ, IRQT_FALLING);
5637+#endif
5638+
5639+ return cmx270_register(CMX270_IDECS0_VIRT, CMX270_IDECS1_VIRT, CMX270_IDE_IRQ, &ifs[0]);
5640+ return 0;
5641+}
5642+
5643+module_init(cmx270_init);
5644+
5645+MODULE_AUTHOR("CompuLab");
5646+MODULE_LICENSE("GPL");
5647+MODULE_DESCRIPTION("CompuLab CM-X270 IDE driver");
5648diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
5649index 550f297..ed5bb70 100644
5650--- a/drivers/mfd/Kconfig
5651+++ b/drivers/mfd/Kconfig
5652@@ -23,3 +23,13 @@ config MCP_UCB1200_TS
5653 depends on MCP_UCB1200 && INPUT
5654
5655 endmenu
5656+
5657+config UCB1400
5658+ tristate
5659+
5660+config UCB1400_TS
5661+ tristate "UCB1400 Touchscreen support"
5662+ depends on ARCH_LUBBOCK || MACH_MAINSTONE || MACH_ARMCORE
5663+ select UCB1400
5664+ select SND_AC97_BUS
5665+
5666diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
5667index adb29b5..24429d1 100644
5668--- a/drivers/mfd/Makefile
5669+++ b/drivers/mfd/Makefile
5670@@ -10,3 +10,10 @@ obj-$(CONFIG_MCP_UCB1200_TS) += ucb1x00-
5671 ifeq ($(CONFIG_SA1100_ASSABET),y)
5672 obj-$(CONFIG_MCP_UCB1200) += ucb1x00-assabet.o
5673 endif
5674+
5675+ucb1400-core-y := ucb1x00-core.o mcp-ac97.o
5676+obj-$(CONFIG_UCB1400_TS) += ucb1400-core.o ucb1x00-ts.o
5677+
5678+ucb1400-core-$(CONFIG_UCB1400) := ucb1x00-core.o mcp-ac97.o
5679+obj-$(CONFIG_UCB1400_TS) += ucb1400-core.o ucb1x00-ts.o
5680+
5681diff --git a/drivers/mfd/mcp-ac97.c b/drivers/mfd/mcp-ac97.c
5682new file mode 100644
5683index 0000000..223f8c2
5684--- /dev/null
5685+++ b/drivers/mfd/mcp-ac97.c
5686@@ -0,0 +1,151 @@
5687+/*
5688+ * linux/drivers/misc/mcp-ac97.c
5689+ *
5690+ * Author: Nicolas Pitre
5691+ * Created: Jan 14, 2005
5692+ * Copyright: (C) MontaVista Software Inc.
5693+ *
5694+ * This program is free software; you can redistribute it and/or
5695+ * modify it under the terms of the GNU General Public License
5696+ * version 2 as published by the Free Software Foundation.
5697+ *
5698+ * This module provides the minimum replacement for mcp-core.c allowing for
5699+ * the UCB1400 chip to be driven by the ucb1x00 driver over an AC97 link.
5700+ */
5701+
5702+#include <linux/module.h>
5703+#include <linux/init.h>
5704+#include <linux/errno.h>
5705+#include <linux/device.h>
5706+
5707+#include <sound/driver.h>
5708+#include <sound/core.h>
5709+#include <sound/ac97_codec.h>
5710+
5711+#include "mcp.h"
5712+
5713+/* ucb1x00 SIB register to ucb1400 AC-link register mapping */
5714+
5715+static const unsigned char regmap[] = {
5716+ 0x5a, /* UCB_IO_DATA */
5717+ 0X5C, /* UCB_IO_DIR */
5718+ 0X5E, /* UCB_IE_RIS */
5719+ 0x60, /* UCB_IE_FAL */
5720+ 0x62, /* UCB_IE_STATUS */
5721+ 0, /* UCB_TC_A */
5722+ 0, /* UCB_TC_B */
5723+ 0, /* UCB_AC_A */
5724+ 0, /* UCB_AC_B */
5725+ 0x64, /* UCB_TS_CR */
5726+ 0x66, /* UCB_ADC_CR */
5727+ 0x68, /* UCB_ADC_DATA */
5728+ 0x7e, /* UCB_ID */
5729+ 0, /* UCB_MODE */
5730+};
5731+
5732+unsigned int mcp_reg_read(struct mcp *mcp, unsigned int reg)
5733+{
5734+ ac97_t *ac97 = to_ac97_t(mcp->dev);
5735+ if (reg < ARRAY_SIZE(regmap)) {
5736+ reg = regmap[reg];
5737+ if (reg)
5738+ return ac97->bus->ops->read(ac97, reg);
5739+ }
5740+ return -1;
5741+}
5742+EXPORT_SYMBOL(mcp_reg_read);
5743+
5744+void mcp_reg_write(struct mcp *mcp, unsigned int reg, unsigned int val)
5745+{
5746+ ac97_t *ac97 = to_ac97_t(mcp->dev);
5747+ if (reg < ARRAY_SIZE(regmap)) {
5748+ reg = regmap[reg];
5749+ if (reg)
5750+ ac97->bus->ops->write(ac97, reg, val);
5751+ }
5752+}
5753+EXPORT_SYMBOL(mcp_reg_write);
5754+
5755+void mcp_enable(struct mcp *mcp)
5756+{
5757+}
5758+EXPORT_SYMBOL(mcp_enable);
5759+
5760+void mcp_disable(struct mcp *mcp)
5761+{
5762+}
5763+EXPORT_SYMBOL(mcp_disable);
5764+
5765+#define to_mcp_driver(d) container_of(d, struct mcp_driver, drv)
5766+
5767+static int mcp_probe(struct device *dev)
5768+{
5769+ struct mcp_driver *drv = to_mcp_driver(dev->driver);
5770+ struct mcp *mcp;
5771+ int ret;
5772+
5773+ ret = -ENOMEM;
5774+ mcp = kmalloc(sizeof(*mcp), GFP_KERNEL);
5775+ if (mcp) {
5776+ memset(mcp, 0, sizeof(*mcp));
5777+ mcp->owner = THIS_MODULE;
5778+ mcp->dev = dev;
5779+ ret = drv->probe(mcp);
5780+ if (ret)
5781+ kfree(mcp);
5782+ }
5783+ if (!ret)
5784+ dev_set_drvdata(dev, mcp);
5785+ return ret;
5786+}
5787+
5788+static int mcp_remove(struct device *dev)
5789+{
5790+ struct mcp_driver *drv = to_mcp_driver(dev->driver);
5791+ struct mcp *mcp = dev_get_drvdata(dev);
5792+
5793+ drv->remove(mcp);
5794+ dev_set_drvdata(dev, NULL);
5795+ kfree(mcp);
5796+ return 0;
5797+}
5798+
5799+static int mcp_suspend(struct device *dev, pm_message_t state)
5800+{
5801+ struct mcp_driver *drv = to_mcp_driver(dev->driver);
5802+ struct mcp *mcp = dev_get_drvdata(dev);
5803+ int ret = 0;
5804+
5805+ if (drv->suspend)
5806+ ret = drv->suspend(mcp, state);
5807+ return ret;
5808+}
5809+
5810+static int mcp_resume(struct device *dev)
5811+{
5812+ struct mcp_driver *drv = to_mcp_driver(dev->driver);
5813+ struct mcp *mcp = dev_get_drvdata(dev);
5814+ int ret = 0;
5815+
5816+ if (drv->resume)
5817+ ret = drv->resume(mcp);
5818+ return ret;
5819+}
5820+
5821+int mcp_driver_register(struct mcp_driver *mcpdrv)
5822+{
5823+ mcpdrv->drv.owner = THIS_MODULE;
5824+ mcpdrv->drv.bus = &ac97_bus_type;
5825+ mcpdrv->drv.probe = mcp_probe;
5826+ mcpdrv->drv.remove = mcp_remove;
5827+ mcpdrv->drv.suspend = mcp_suspend;
5828+ mcpdrv->drv.resume = mcp_resume;
5829+ return driver_register(&mcpdrv->drv);
5830+}
5831+
5832+void mcp_driver_unregister(struct mcp_driver *mcpdrv)
5833+{
5834+ driver_unregister(&mcpdrv->drv);
5835+}
5836+
5837+MODULE_LICENSE("GPL");
5838diff --git a/drivers/mfd/mcp-core.c b/drivers/mfd/mcp-core.c
5839index 75f401d..2a7c176 100644
5840--- a/drivers/mfd/mcp-core.c
5841+++ b/drivers/mfd/mcp-core.c
5842@@ -208,6 +208,7 @@ struct mcp *mcp_host_alloc(struct device
5843 mcp->attached_device.bus = &mcp_bus_type;
5844 mcp->attached_device.dma_mask = parent->dma_mask;
5845 mcp->attached_device.release = mcp_release;
5846+ mcp->dev = &mcp->attached_device;
5847 }
5848 return mcp;
5849 }
5850diff --git a/drivers/mfd/mcp.h b/drivers/mfd/mcp.h
5851index c093a93..2897d8c 100644
5852--- a/drivers/mfd/mcp.h
5853+++ b/drivers/mfd/mcp.h
5854@@ -19,11 +19,12 @@ struct mcp {
5855 int use_count;
5856 unsigned int sclk_rate;
5857 unsigned int rw_timeout;
5858- dma_device_t dma_audio_rd;
5859- dma_device_t dma_audio_wr;
5860- dma_device_t dma_telco_rd;
5861- dma_device_t dma_telco_wr;
5862+/* dma_device_t dma_audio_rd; */
5863+/* dma_device_t dma_audio_wr; */
5864+/* dma_device_t dma_telco_rd; */
5865+/* dma_device_t dma_telco_wr; */
5866 struct device attached_device;
5867+ struct device *dev;
5868 };
5869
5870 struct mcp_ops {
5871diff --git a/drivers/mfd/ucb1x00-core.c b/drivers/mfd/ucb1x00-core.c
5872index aff83f9..f9a532b 100644
5873--- a/drivers/mfd/ucb1x00-core.c
5874+++ b/drivers/mfd/ucb1x00-core.c
5875@@ -23,6 +23,7 @@ #include <linux/slab.h>
5876 #include <linux/init.h>
5877 #include <linux/errno.h>
5878 #include <linux/interrupt.h>
5879+#include <linux/kthread.h>
5880 #include <linux/device.h>
5881 #include <linux/mutex.h>
5882
5883@@ -31,6 +32,12 @@ #include <asm/hardware.h>
5884
5885 #include "ucb1x00.h"
5886
5887+#if defined(CONFIG_UCB1400) || defined(CONFIG_UCB1400_MODULE)
5888+#define UCB_IS_1400(id) ((id) == UCB_ID_1400)
5889+#else
5890+#define UCB_IS_1400(id) (0)
5891+#endif
5892+
5893 static DEFINE_MUTEX(ucb1x00_mutex);
5894 static LIST_HEAD(ucb1x00_drivers);
5895 static LIST_HEAD(ucb1x00_devices);
5896@@ -58,9 +65,9 @@ void ucb1x00_io_set_dir(struct ucb1x00 *
5897 spin_lock_irqsave(&ucb->io_lock, flags);
5898 ucb->io_dir |= out;
5899 ucb->io_dir &= ~in;
5900+ spin_unlock_irqrestore(&ucb->io_lock, flags);
5901
5902 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
5903- spin_unlock_irqrestore(&ucb->io_lock, flags);
5904 }
5905
5906 /**
5907@@ -86,9 +93,9 @@ void ucb1x00_io_write(struct ucb1x00 *uc
5908 spin_lock_irqsave(&ucb->io_lock, flags);
5909 ucb->io_out |= set;
5910 ucb->io_out &= ~clear;
5911+ spin_unlock_irqrestore(&ucb->io_lock, flags);
5912
5913 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
5914- spin_unlock_irqrestore(&ucb->io_lock, flags);
5915 }
5916
5917 /**
5918@@ -178,7 +185,7 @@ unsigned int ucb1x00_adc_read(struct ucb
5919 schedule_timeout(1);
5920 }
5921
5922- return UCB_ADC_DAT(val);
5923+ return UCB_IS_1400(ucb->id) ? (val & 0x3ff) : ((val & 0x7fe0) >> 5);
5924 }
5925
5926 /**
5927@@ -223,6 +230,47 @@ static irqreturn_t ucb1x00_irq(int irqnr
5928 return IRQ_HANDLED;
5929 }
5930
5931+/*
5932+ * A restriction with interrupts exists when using the ucb1400, as
5933+ * the codec read/write routines may sleep while waiting for codec
5934+ * access completion and uses semaphores for access control to the
5935+ * AC97 bus. A complete codec read cycle could take anywhere from
5936+ * 60 to 100uSec so we *definitely* don't want to spin inside the
5937+ * interrupt handler waiting for codec access. So, we handle the
5938+ * interrupt by scheduling a RT kernel thread to run in process
5939+ * context instead of interrupt context.
5940+ */
5941+static int ucb1x00_thread(void *_ucb)
5942+{
5943+ struct task_struct *tsk = current;
5944+ struct ucb1x00 *ucb = _ucb;
5945+
5946+ tsk->policy = SCHED_FIFO;
5947+ tsk->rt_priority = 1;
5948+
5949+ while (!kthread_should_stop()) {
5950+ wait_for_completion_interruptible(&ucb->irq_wait);
5951+ if (try_to_freeze())
5952+ continue;
5953+ ucb1x00_irq(ucb->irq, ucb, NULL);
5954+ enable_irq(ucb->irq);
5955+ }
5956+
5957+ ucb->irq_task = NULL;
5958+ return 0;
5959+}
5960+
5961+static irqreturn_t ucb1x00_threaded_irq(int irqnr, void *devid, struct pt_regs *regs)
5962+{
5963+ struct ucb1x00 *ucb = devid;
5964+ if (irqnr == ucb->irq) {
5965+ disable_irq(ucb->irq);
5966+ complete(&ucb->irq_wait);
5967+ return IRQ_HANDLED;
5968+ }
5969+ return IRQ_NONE;
5970+}
5971+
5972 /**
5973 * ucb1x00_hook_irq - hook a UCB1x00 interrupt
5974 * @ucb: UCB1x00 structure describing chip
5975@@ -276,18 +324,22 @@ void ucb1x00_enable_irq(struct ucb1x00 *
5976
5977 if (idx < 16) {
5978 spin_lock_irqsave(&ucb->lock, flags);
5979-
5980- ucb1x00_enable(ucb);
5981- if (edges & UCB_RISING) {
5982+ if (edges & UCB_RISING)
5983 ucb->irq_ris_enbl |= 1 << idx;
5984- ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
5985- }
5986- if (edges & UCB_FALLING) {
5987+ if (edges & UCB_FALLING)
5988 ucb->irq_fal_enbl |= 1 << idx;
5989- ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
5990- }
5991- ucb1x00_disable(ucb);
5992 spin_unlock_irqrestore(&ucb->lock, flags);
5993+
5994+ ucb1x00_enable(ucb);
5995+
5996+ /* This prevents spurious interrupts on the UCB1400 */
5997+ ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 1 << idx);
5998+ ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
5999+
6000+ ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
6001+ ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
6002+
6003+ ucb1x00_disable(ucb);
6004 }
6005 }
6006
6007@@ -305,18 +357,16 @@ void ucb1x00_disable_irq(struct ucb1x00
6008
6009 if (idx < 16) {
6010 spin_lock_irqsave(&ucb->lock, flags);
6011-
6012- ucb1x00_enable(ucb);
6013- if (edges & UCB_RISING) {
6014+ if (edges & UCB_RISING)
6015 ucb->irq_ris_enbl &= ~(1 << idx);
6016- ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
6017- }
6018- if (edges & UCB_FALLING) {
6019+ if (edges & UCB_FALLING)
6020 ucb->irq_fal_enbl &= ~(1 << idx);
6021- ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
6022- }
6023- ucb1x00_disable(ucb);
6024 spin_unlock_irqrestore(&ucb->lock, flags);
6025+
6026+ ucb1x00_enable(ucb);
6027+ ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
6028+ ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
6029+ ucb1x00_disable(ucb);
6030 }
6031 }
6032
6033@@ -349,16 +399,17 @@ int ucb1x00_free_irq(struct ucb1x00 *ucb
6034 ucb->irq_ris_enbl &= ~(1 << idx);
6035 ucb->irq_fal_enbl &= ~(1 << idx);
6036
6037- ucb1x00_enable(ucb);
6038- ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
6039- ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
6040- ucb1x00_disable(ucb);
6041-
6042 irq->fn = NULL;
6043 irq->devid = NULL;
6044 ret = 0;
6045 }
6046 spin_unlock_irq(&ucb->lock);
6047+
6048+ ucb1x00_enable(ucb);
6049+ ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
6050+ ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
6051+ ucb1x00_disable(ucb);
6052+
6053 return ret;
6054
6055 bad:
6056@@ -478,7 +529,7 @@ static int ucb1x00_probe(struct mcp *mcp
6057 mcp_enable(mcp);
6058 id = mcp_reg_read(mcp, UCB_ID);
6059
6060- if (id != UCB_ID_1200 && id != UCB_ID_1300) {
6061+ if (id != UCB_ID_1200 && id != UCB_ID_1300 && !UCB_IS_1400(id)) {
6062 printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
6063 goto err_disable;
6064 }
6065@@ -491,12 +542,13 @@ static int ucb1x00_probe(struct mcp *mcp
6066 memset(ucb, 0, sizeof(struct ucb1x00));
6067
6068 ucb->cdev.class = &ucb1x00_class;
6069- ucb->cdev.dev = &mcp->attached_device;
6070+ ucb->cdev.dev = mcp->dev;
6071 strlcpy(ucb->cdev.class_id, "ucb1x00", sizeof(ucb->cdev.class_id));
6072
6073 spin_lock_init(&ucb->lock);
6074 spin_lock_init(&ucb->io_lock);
6075 sema_init(&ucb->adc_sem, 1);
6076+ init_completion(&ucb->irq_wait);
6077
6078 ucb->id = id;
6079 ucb->mcp = mcp;
6080@@ -507,13 +559,22 @@ static int ucb1x00_probe(struct mcp *mcp
6081 goto err_free;
6082 }
6083
6084- ret = request_irq(ucb->irq, ucb1x00_irq, SA_TRIGGER_RISING,
6085- "UCB1x00", ucb);
6086+ ret = request_irq(ucb->irq,
6087+ UCB_IS_1400(id) ? ucb1x00_threaded_irq : ucb1x00_irq,
6088+ SA_TRIGGER_RISING, "UCB1x00", ucb);
6089 if (ret) {
6090 printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n",
6091 ucb->irq, ret);
6092 goto err_free;
6093 }
6094+ if (UCB_IS_1400(id)) {
6095+ ucb->irq_task = kthread_run(ucb1x00_thread, ucb, "kUCB1x00d");
6096+ if (IS_ERR(ucb->irq_task)) {
6097+ ret = PTR_ERR(ucb->irq_task);
6098+ ucb->irq_task = NULL;
6099+ goto err_irq;
6100+ }
6101+ }
6102
6103 mcp_set_drvdata(mcp, ucb);
6104
6105@@ -531,6 +592,8 @@ static int ucb1x00_probe(struct mcp *mcp
6106 goto out;
6107
6108 err_irq:
6109+ if (UCB_IS_1400(id) && ucb->irq_task)
6110+ kthread_stop(ucb->irq_task);
6111 free_irq(ucb->irq, ucb);
6112 err_free:
6113 kfree(ucb);
6114@@ -553,6 +616,10 @@ static void ucb1x00_remove(struct mcp *m
6115 }
6116 mutex_unlock(&ucb1x00_mutex);
6117
6118+ if (UCB_IS_1400(ucb->id) && ucb->irq_task) {
6119+ complete(&ucb->irq_wait);
6120+ kthread_stop(ucb->irq_task);
6121+ }
6122 free_irq(ucb->irq, ucb);
6123 class_device_unregister(&ucb->cdev);
6124 }
6125diff --git a/drivers/mfd/ucb1x00-ts.c b/drivers/mfd/ucb1x00-ts.c
6126index 79fd062..e68132d 100644
6127--- a/drivers/mfd/ucb1x00-ts.c
6128+++ b/drivers/mfd/ucb1x00-ts.c
6129@@ -35,7 +35,15 @@ #include <linux/kthread.h>
6130
6131 #include <asm/dma.h>
6132 #include <asm/semaphore.h>
6133+
6134+/* FIXME: proper machine detection should be implemented */
6135+#ifdef CONFIG_SA1100_COLLIE
6136 #include <asm/arch/collie.h>
6137+#else
6138+#define machine_is_collie() (0)
6139+#define COLLIE_TC35143_GPIO_TBL_CHK (0)
6140+#endif
6141+
6142 #include <asm/mach-types.h>
6143
6144 #include "ucb1x00.h"
6145@@ -45,7 +53,7 @@ struct ucb1x00_ts {
6146 struct input_dev *idev;
6147 struct ucb1x00 *ucb;
6148
6149- wait_queue_head_t irq_wait;
6150+ struct completion irq_wait;
6151 struct task_struct *rtask;
6152 u16 x_res;
6153 u16 y_res;
6154@@ -98,7 +106,8 @@ static inline unsigned int ucb1x00_ts_re
6155 udelay(55);
6156
6157 return ucb1x00_adc_read(ts->ucb, UCB_ADC_INP_AD2, ts->adcsync);
6158- } else {
6159+ }
6160+ else {
6161 ucb1x00_reg_write(ts->ucb, UCB_TS_CR,
6162 UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
6163 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
6164@@ -205,7 +214,6 @@ static int ucb1x00_thread(void *_ts)
6165 {
6166 struct ucb1x00_ts *ts = _ts;
6167 struct task_struct *tsk = current;
6168- DECLARE_WAITQUEUE(wait, tsk);
6169 int valid;
6170
6171 /*
6172@@ -217,10 +225,8 @@ static int ucb1x00_thread(void *_ts)
6173
6174 valid = 0;
6175
6176- add_wait_queue(&ts->irq_wait, &wait);
6177 while (!kthread_should_stop()) {
6178 unsigned int x, y, p;
6179- signed long timeout;
6180
6181 ts->restart = 0;
6182
6183@@ -242,8 +248,6 @@ static int ucb1x00_thread(void *_ts)
6184
6185
6186 if (ucb1x00_ts_pen_down(ts)) {
6187- set_task_state(tsk, TASK_INTERRUPTIBLE);
6188-
6189 ucb1x00_enable_irq(ts->ucb, UCB_IRQ_TSPX, machine_is_collie() ? UCB_RISING : UCB_FALLING);
6190 ucb1x00_disable(ts->ucb);
6191
6192@@ -256,7 +260,15 @@ static int ucb1x00_thread(void *_ts)
6193 valid = 0;
6194 }
6195
6196- timeout = MAX_SCHEDULE_TIMEOUT;
6197+ /*
6198+ * Since ucb1x00_enable_irq() might sleep due
6199+ * to the way the UCB1400 regs are accessed, we
6200+ * can't use set_task_state() before that call,
6201+ * and not changing state before enabling the
6202+ * interrupt is racy. A completion handler avoids
6203+ * the issue.
6204+ */
6205+ wait_for_completion_interruptible(&ts->irq_wait);
6206 } else {
6207 ucb1x00_disable(ts->ucb);
6208
6209@@ -271,16 +283,12 @@ static int ucb1x00_thread(void *_ts)
6210 }
6211
6212 set_task_state(tsk, TASK_INTERRUPTIBLE);
6213- timeout = HZ / 100;
6214+ schedule_timeout(HZ/100);
6215 }
6216
6217 try_to_freeze();
6218-
6219- schedule_timeout(timeout);
6220 }
6221
6222- remove_wait_queue(&ts->irq_wait, &wait);
6223-
6224 ts->rtask = NULL;
6225 return 0;
6226 }
6227@@ -293,7 +301,7 @@ static void ucb1x00_ts_irq(int idx, void
6228 {
6229 struct ucb1x00_ts *ts = id;
6230 ucb1x00_disable_irq(ts->ucb, UCB_IRQ_TSPX, UCB_FALLING);
6231- wake_up(&ts->irq_wait);
6232+ complete(&ts->irq_wait);
6233 }
6234
6235 static int ucb1x00_ts_open(struct input_dev *idev)
6236@@ -303,7 +311,7 @@ static int ucb1x00_ts_open(struct input_
6237
6238 BUG_ON(ts->rtask);
6239
6240- init_waitqueue_head(&ts->irq_wait);
6241+ init_completion(&ts->irq_wait);
6242 ret = ucb1x00_hook_irq(ts->ucb, UCB_IRQ_TSPX, ucb1x00_ts_irq, ts);
6243 if (ret < 0)
6244 goto out;
6245@@ -337,8 +345,10 @@ static void ucb1x00_ts_close(struct inpu
6246 {
6247 struct ucb1x00_ts *ts = idev->private;
6248
6249- if (ts->rtask)
6250+ if (ts->rtask) {
6251+ complete(&ts->irq_wait);
6252 kthread_stop(ts->rtask);
6253+ }
6254
6255 ucb1x00_enable(ts->ucb);
6256 ucb1x00_free_irq(ts->ucb, UCB_IRQ_TSPX, ts);
6257@@ -358,7 +368,7 @@ static int ucb1x00_ts_resume(struct ucb1
6258 * after sleep.
6259 */
6260 ts->restart = 1;
6261- wake_up(&ts->irq_wait);
6262+ complete(&ts->irq_wait);
6263 }
6264 return 0;
6265 }
6266diff --git a/drivers/mfd/ucb1x00.h b/drivers/mfd/ucb1x00.h
6267index 9c9a647..ff04dc9 100644
6268--- a/drivers/mfd/ucb1x00.h
6269+++ b/drivers/mfd/ucb1x00.h
6270@@ -94,6 +94,7 @@ #define UCB_ADC_DAT(x) (((x) & 0x7fe0)
6271 #define UCB_ID 0x0c
6272 #define UCB_ID_1200 0x1004
6273 #define UCB_ID_1300 0x1005
6274+#define UCB_ID_1400 0x4304
6275
6276 #define UCB_MODE 0x0d
6277 #define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
6278@@ -110,6 +111,8 @@ struct ucb1x00 {
6279 spinlock_t lock;
6280 struct mcp *mcp;
6281 unsigned int irq;
6282+ struct task_struct *irq_task;
6283+ struct completion irq_wait;
6284 struct semaphore adc_sem;
6285 spinlock_t io_lock;
6286 u16 id;
6287@@ -122,6 +125,7 @@ struct ucb1x00 {
6288 struct class_device cdev;
6289 struct list_head node;
6290 struct list_head devs;
6291+
6292 };
6293
6294 struct ucb1x00_driver;
6295diff --git a/drivers/mtd/nand/cmx270-nand.c b/drivers/mtd/nand/cmx270-nand.c
6296new file mode 100644
6297index 0000000..fb37d6d
6298--- /dev/null
6299+++ b/drivers/mtd/nand/cmx270-nand.c
6300@@ -0,0 +1,291 @@
6301+/*
6302+ * drivers/mtd/nand/cmx270-nand.c
6303+ *
6304+ * Copyright (C) 2005 Compulab, Ltd. (mike@compulab.co.il)
6305+ *
6306+ * Derived from drivers/mtd/nand/h1910.c
6307+ * Copyright (C) 2002 Marius Gröger (mag@sysgo.de)
6308+ * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
6309+ *
6310+ *
6311+ * This program is free software; you can redistribute it and/or modify
6312+ * it under the terms of the GNU General Public License version 2 as
6313+ * published by the Free Software Foundation.
6314+ *
6315+ * Overview:
6316+ * This is a device driver for the NAND flash device found on the
6317+ * CM-X270 board.
6318+ */
6319+
6320+#include <linux/config.h>
6321+#include <linux/slab.h>
6322+#include <linux/init.h>
6323+#include <linux/module.h>
6324+#include <linux/mtd/mtd.h>
6325+#include <linux/mtd/nand.h>
6326+#include <linux/mtd/partitions.h>
6327+
6328+#include <asm/io.h>
6329+#include <asm/irq.h>
6330+#include <asm/arch/armcore.h>
6331+
6332+#define NAND_CS_ON (GPCR0 = (1<<11))
6333+#define NAND_CS_OFF (GPSR0 = (1<<11))
6334+#define NAND_RB (GPLR2 & (1<<25))
6335+
6336+/*
6337+ * MTD structure for CM-X270 board
6338+ */
6339+static struct mtd_info *cmx270_nand_mtd = NULL;
6340+
6341+/*
6342+ * Module stuff
6343+ */
6344+
6345+#ifdef CONFIG_MTD_PARTITIONS
6346+/*
6347+ * Define static partitions for flash device
6348+ */
6349+static struct mtd_partition partition_info[] = {
6350+/* { */
6351+/* name: "cmx270-0", */
6352+/* offset: 0, */
6353+/* size: 2*1024*1024 */
6354+/* }, */
6355+ {
6356+ name: "cmx270-0",
6357+ offset: 0,
6358+ size: MTDPART_SIZ_FULL
6359+ }
6360+};
6361+#define NUM_PARTITIONS 1
6362+
6363+#endif
6364+
6365+
6366+static u_char cmx270_read_byte(struct mtd_info *mtd)
6367+{
6368+ struct nand_chip *this = mtd->priv;
6369+ volatile u_long* addr = (volatile u_long*)this->IO_ADDR_R;
6370+ u_long word = *addr;
6371+
6372+/* printk(KERN_DEBUG "%s: addr = %p, byte = %x, byte_shift = %x\n", */
6373+/* __FUNCTION__, addr, word, (word >> 16)); */
6374+
6375+ return (unsigned char)(word >> 16);
6376+/* return (unsigned char)(*addr >> 16); */
6377+}
6378+
6379+static void cmx270_write_byte(struct mtd_info *mtd, u_char byte)
6380+{
6381+ struct nand_chip *this = mtd->priv;
6382+ volatile u_long* addr = (volatile u_long*)this->IO_ADDR_R;
6383+
6384+/* printk(KERN_DEBUG "%s: addr = %p, byte = %x, byte_shift = %x\n", */
6385+/* __FUNCTION__, addr, byte, (byte << 16)); */
6386+
6387+ *addr = (byte << 16);
6388+}
6389+
6390+static void cmx270_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
6391+{
6392+ int i;
6393+ struct nand_chip *this = mtd->priv;
6394+ volatile u_long* addr = (volatile u_long*)this->IO_ADDR_R;
6395+ u_long value;
6396+
6397+ for (i=0; i<len; i++) {
6398+ *addr = (*buf++ << 16);
6399+ }
6400+/* value = (buf[i] << 24) | (buf[i] << 16) | (buf[i] << 8) |buf[i]; */
6401+/* *addr = value; */
6402+/* } */
6403+}
6404+
6405+static void cmx270_read_buf(struct mtd_info *mtd, u_char *buf, int len)
6406+{
6407+ int i;
6408+ struct nand_chip *this = mtd->priv;
6409+ volatile u_long* addr = (volatile u_long*)this->IO_ADDR_R;
6410+/* u_long value; */
6411+
6412+ for (i=0; i<len; i++) {
6413+ *buf++ = (unsigned char)(*addr >> 16);
6414+/* value = *addr; */
6415+/* buf[i] = (u_char)((value & 0x000000ff)); */
6416+ }
6417+}
6418+
6419+static int cmx270_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
6420+{
6421+ int i;
6422+ struct nand_chip *this = mtd->priv;
6423+ volatile u_long* addr = (volatile u_long*)this->IO_ADDR_R;
6424+ u_long value;
6425+
6426+/* for (i=0; i<len; i++) { */
6427+/* value = *addr; */
6428+/* if ( buf[i] != (u_char)((value & 0x000000ff)) ) */
6429+/* return -EFAULT; */
6430+/* } */
6431+
6432+ return 0;
6433+}
6434+
6435+/*
6436+ * hardware specific access to control-lines
6437+ */
6438+static void cmx270_hwcontrol(struct mtd_info *mtd, int cmd)
6439+{
6440+ struct nand_chip* this = (struct nand_chip *) (mtd->priv);
6441+ unsigned int nandaddr = (unsigned int)this->IO_ADDR_R;
6442+
6443+ switch(cmd) {
6444+
6445+ case NAND_CTL_SETCLE:
6446+ nandaddr |= (1 << 2);
6447+ this->IO_ADDR_R = (void __iomem*)nandaddr;
6448+ this->IO_ADDR_W = (void __iomem*)nandaddr;
6449+ break;
6450+ case NAND_CTL_CLRCLE:
6451+ nandaddr &= ~(1 << 2);
6452+ this->IO_ADDR_R = (void __iomem*)nandaddr;
6453+ this->IO_ADDR_W = (void __iomem*)nandaddr;
6454+ break;
6455+
6456+ case NAND_CTL_SETALE:
6457+ nandaddr |= (1 << 3);
6458+ this->IO_ADDR_R = (void __iomem*)nandaddr;
6459+ this->IO_ADDR_W = (void __iomem*)nandaddr;
6460+ break;
6461+ case NAND_CTL_CLRALE:
6462+ nandaddr &= ~(1 << 3);
6463+ this->IO_ADDR_R = (void __iomem*)nandaddr;
6464+ this->IO_ADDR_W = (void __iomem*)nandaddr;
6465+ break;
6466+
6467+ case NAND_CTL_SETNCE:
6468+ NAND_CS_ON;
6469+ break;
6470+ case NAND_CTL_CLRNCE:
6471+ NAND_CS_OFF;
6472+ break;
6473+ }
6474+}
6475+
6476+/*
6477+ * read device ready pin
6478+ */
6479+static int cmx270_device_ready(struct mtd_info *mtd)
6480+{
6481+/* volatile cpm2_map_t *immap = (volatile cpm2_map_t *)CPM_MAP_ADDR; */
6482+/* return ((immap->im_ioport.iop_pdatd & NAND_RDY) != 0); */
6483+
6484+ return ( NAND_RB != 0 );
6485+}
6486+
6487+/*
6488+ * Main initialization routine
6489+ */
6490+static int __init cmx270_init (void)
6491+{
6492+ struct nand_chip *this;
6493+ const char *part_type = 0;
6494+ int mtd_parts_nb = 0;
6495+ struct mtd_partition *mtd_parts = 0;
6496+ static unsigned int nandaddr = 0;
6497+
6498+
6499+ /* Allocate memory for MTD device structure and private data */
6500+ cmx270_nand_mtd = kmalloc(sizeof(struct mtd_info) +
6501+ sizeof(struct nand_chip),
6502+ GFP_KERNEL);
6503+ if (!cmx270_nand_mtd) {
6504+ printk("Unable to allocate CM-X270 NAND MTD device structure.\n");
6505+ return -ENOMEM;
6506+ }
6507+
6508+ nandaddr = (volatile unsigned long*)ARMCORE_CS1_VIRT;
6509+
6510+ /* Get pointer to private data */
6511+ this = (struct nand_chip *) (&cmx270_nand_mtd[1]);
6512+
6513+ /* Initialize structures */
6514+ memset((char *) cmx270_nand_mtd, 0, sizeof(struct mtd_info));
6515+ memset((char *) this, 0, sizeof(struct nand_chip));
6516+
6517+/* pxa_gpio_mode(89 | GPIO_IN ); */
6518+ printk(KERN_WARNING "%s: PSSR = %x\n", __FUNCTION__, PSSR);
6519+ printk(KERN_WARNING "%s: GPDR2 = %x\n", __FUNCTION__, GPDR2);
6520+ printk(KERN_WARNING "%s: GRER2 = %x\n", __FUNCTION__, GRER2);
6521+ printk(KERN_WARNING "%s: GAFR2_U = %x\n", __FUNCTION__, GAFR2_U);
6522+ printk(KERN_WARNING "%s: GPLR2 = %x\n", __FUNCTION__, GPLR2);
6523+ printk(KERN_WARNING "%s: GEDR2 = %x\n", __FUNCTION__, GEDR2);
6524+
6525+ /* Link the private data with the MTD structure */
6526+ cmx270_nand_mtd->priv = this;
6527+
6528+ /* insert callbacks */
6529+ this->IO_ADDR_R = (void __iomem *)nandaddr;
6530+ this->IO_ADDR_W = (void __iomem *)nandaddr;
6531+ this->hwcontrol = cmx270_hwcontrol;
6532+/* this->dev_ready = cmx270_device_ready; /\* unknown whether that was correct or not so we will just do it like this *\/ */
6533+
6534+ /* 15 us command delay time */
6535+ this->chip_delay = 50;
6536+ this->eccmode = NAND_ECC_SOFT;
6537+
6538+ /* read/write functions */
6539+ this->read_byte = cmx270_read_byte;
6540+ this->write_byte = cmx270_write_byte;
6541+ this->read_buf = cmx270_read_buf;
6542+ this->write_buf = cmx270_write_buf;
6543+ this->verify_buf = cmx270_verify_buf;
6544+
6545+ /* Scan to find existence of the device */
6546+ if (nand_scan (cmx270_nand_mtd, 1)) {
6547+ printk(KERN_NOTICE "No NAND device - returning -ENXIO\n");
6548+ kfree (cmx270_nand_mtd);
6549+ return -ENXIO;
6550+ }
6551+
6552+#ifdef CONFIG_MTD_CMDLINE_PARTS
6553+ mtd_parts_nb = parse_cmdline_partitions(cmx270_nand_mtd, &mtd_parts,
6554+ "cmx270");
6555+ if (mtd_parts_nb > 0)
6556+ part_type = "command line";
6557+ else
6558+ mtd_parts_nb = 0;
6559+#endif
6560+ if (mtd_parts_nb == 0)
6561+ {
6562+ mtd_parts = partition_info;
6563+ mtd_parts_nb = NUM_PARTITIONS;
6564+ part_type = "static";
6565+ }
6566+
6567+ /* Register the partitions */
6568+ printk(KERN_NOTICE "Using %s partition definition\n", part_type);
6569+ add_mtd_partitions(cmx270_nand_mtd, mtd_parts, mtd_parts_nb);
6570+
6571+ /* Return happy */
6572+ return 0;
6573+}
6574+module_init(cmx270_init);
6575+
6576+/*
6577+ * Clean up routine
6578+ */
6579+static void __exit cmx270_cleanup (void)
6580+{
6581+ /* Release resources, unregister device */
6582+ nand_release (cmx270_nand_mtd);
6583+
6584+ /* Free the MTD device structure */
6585+ kfree (cmx270_nand_mtd);
6586+}
6587+module_exit(cmx270_cleanup);
6588+
6589+MODULE_LICENSE("GPL");
6590+MODULE_AUTHOR("Mike Rapoport <mike at compulab dot co dot il>");
6591+MODULE_DESCRIPTION("NAND flash driver for Compulab CM-X270 Core");
6592diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
6593index aa633fa..505f92b 100644
6594--- a/drivers/net/Kconfig
6595+++ b/drivers/net/Kconfig
6596@@ -865,6 +865,14 @@ config DM9000
6597 <file:Documentation/networking/net-modules.txt>. The module will be
6598 called dm9000.
6599
6600+config DM9000_NOEPROM
6601+ bool "DM9000 without EEPROM attached"
6602+ depends on DM9000
6603+ ---help---
6604+ Select this option if you have DM9000 chipset without EEPROM
6605+ containing the MAC address. In this case MAC address should
6606+ be set either by the bootloader or using ifconfig
6607+
6608 config NET_VENDOR_RACAL
6609 bool "Racal-Interlan (Micom) NI cards"
6610 depends on NET_ETHERNET && ISA
6611diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
6612index 24996da..7e45756 100644
6613--- a/drivers/net/dm9000.c
6614+++ b/drivers/net/dm9000.c
6615@@ -561,8 +561,14 @@ #endif
6616 ((u16 *) db->srom)[i] = read_srom_word(db, i);
6617
6618 /* Set Node Address */
6619+#ifndef CONFIG_DM9000_NOEPROM
6620 for (i = 0; i < 6; i++)
6621 ndev->dev_addr[i] = db->srom[i];
6622+#else
6623+ /* The Node Address was set by bootloader */
6624+ for (i=0; i<6; i++)
6625+ ndev->dev_addr[i] = ior(db, 0x10+i);
6626+#endif
6627
6628 if (!is_valid_ether_addr(ndev->dev_addr))
6629 printk("%s: Invalid ethernet MAC address. Please "
6630@@ -1098,6 +1104,10 @@ dm9000_phy_read(struct net_device *dev,
6631 /* The read data keeps on REG_0D & REG_0E */
6632 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
6633
6634+/* if ( reg == MII_BMSR ) { */
6635+/* printk(KERN_WARNING "===> %s: ret = %x\n", __FUNCTION__, ret); */
6636+/* } */
6637+
6638 /* restore the previous address */
6639 writeb(reg_save, db->io_addr);
6640
6641@@ -1163,7 +1173,6 @@ dm9000_drv_resume(struct platform_device
6642 if (netif_running(ndev)) {
6643 dm9000_reset(db);
6644 dm9000_init_dm9000(ndev);
6645-
6646 netif_device_attach(ndev);
6647 }
6648 }
6649diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
6650index bcecf51..b6a4173 100644
6651--- a/drivers/pcmcia/Makefile
6652+++ b/drivers/pcmcia/Makefile
6653@@ -68,4 +68,4 @@ sa1100_cs-$(CONFIG_SA1100_SIMPAD) += sa
6654 pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock.o sa1111_generic.o
6655 pxa2xx_cs-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o
6656 pxa2xx_cs-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o
6657-
6658+pxa2xx_cs-$(CONFIG_MACH_ARMCORE) += pxa2xx_cm_x270.o
6659diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
6660new file mode 100644
6661index 0000000..eb4df11
6662--- /dev/null
6663+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
6664@@ -0,0 +1,198 @@
6665+/*
6666+ * linux/drivers/pcmcia/pxa/pxa_armcore.c
6667+ *
6668+ * This program is free software; you can redistribute it and/or modify
6669+ * it under the terms of the GNU General Public License version 2 as
6670+ * published by the Free Software Foundation.
6671+ *
6672+ * Compulab Ltd., 2003
6673+ *
6674+ */
6675+
6676+#include <linux/kernel.h>
6677+#include <linux/sched.h>
6678+#include <linux/platform_device.h>
6679+
6680+#include <pcmcia/ss.h>
6681+#include <asm/delay.h>
6682+#include <asm/hardware.h>
6683+#include <asm/irq.h>
6684+
6685+#include <asm/arch/pxa-regs.h>
6686+#include <asm/arch/cm-x270.h>
6687+
6688+#include "soc_common.h"
6689+
6690+
6691+static struct pcmcia_irqs irqs[] = {
6692+ { 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" },
6693+ { 1, PCMCIA_S1_CD_VALID, "PCMCIA1 CD" },
6694+};
6695+
6696+
6697+static int
6698+cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
6699+{
6700+ int return_val=0;
6701+
6702+ GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
6703+ GPIO_bit(GPIO49_nPWE) |
6704+ GPIO_bit(GPIO50_nPIOR) |
6705+ GPIO_bit(GPIO51_nPIOW) |
6706+ GPIO_bit(GPIO85_nPCE_1) |
6707+ GPIO_bit(GPIO54_nPCE_2);
6708+
6709+ pxa_gpio_mode(GPIO48_nPOE_MD);
6710+ pxa_gpio_mode(GPIO49_nPWE_MD);
6711+ pxa_gpio_mode(GPIO50_nPIOR_MD);
6712+ pxa_gpio_mode(GPIO51_nPIOW_MD);
6713+ pxa_gpio_mode(GPIO85_nPCE_1_MD);
6714+ pxa_gpio_mode(GPIO54_nPCE_2_MD);
6715+ //pxa_gpio_mode(GPIO79_pSKTSEL_MD); /* REVISIT: s/b dependent on num sockets (on ATX base not routed)*/
6716+ pxa_gpio_mode(GPIO55_nPREG_MD);
6717+ pxa_gpio_mode(GPIO56_nPWAIT_MD);
6718+ pxa_gpio_mode(GPIO57_nIOIS16_MD);
6719+
6720+ // Reset signal
6721+ GPDR(GPIO53_nPCE_2) |= GPIO_bit(GPIO53_nPCE_2);
6722+ GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
6723+
6724+ GPDR(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID));
6725+ GPDR(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID));
6726+
6727+ set_irq_type(PCMCIA_S0_CD_VALID, IRQT_BOTHEDGE);
6728+ set_irq_type(PCMCIA_S1_CD_VALID, IRQT_BOTHEDGE);
6729+
6730+ //irq's for slots:
6731+ GPDR(IRQ_TO_GPIO(PCMCIA_S0_RDYINT)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S0_RDYINT));
6732+ GPDR(IRQ_TO_GPIO(PCMCIA_S1_RDYINT)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S1_RDYINT));
6733+
6734+ set_irq_type(PCMCIA_S0_RDYINT, IRQT_FALLING);
6735+ set_irq_type(PCMCIA_S1_RDYINT, IRQT_FALLING);
6736+
6737+ skt->irq = (skt->nr == 0) ? PCMCIA_S0_RDYINT : PCMCIA_S1_RDYINT;
6738+ return_val = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
6739+
6740+ return return_val;
6741+}
6742+
6743+
6744+static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
6745+{
6746+ soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
6747+
6748+ set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID), IRQT_NOEDGE);
6749+ set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID), IRQT_NOEDGE);
6750+
6751+ set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_RDYINT), IRQT_NOEDGE);
6752+ set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_RDYINT), IRQT_NOEDGE);
6753+}
6754+
6755+
6756+static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
6757+ struct pcmcia_state *state)
6758+{
6759+
6760+ state->detect = (PCC_DETECT(skt->nr) == 0) ? 1 : 0;
6761+ state->ready = (PCC_READY(skt->nr) == 0) ? 0 : 1;
6762+ state->bvd1 = 1;
6763+ state->bvd2 = 1;
6764+ state->vs_3v = 0;
6765+ state->vs_Xv = 0;
6766+ state->wrprot = 0; /* not available */
6767+
6768+}
6769+
6770+
6771+static int
6772+cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
6773+ const socket_state_t *state)
6774+{
6775+
6776+ GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
6777+ pxa_gpio_mode(GPIO49_nPWE | GPIO_OUT);
6778+ //pxa_gpio_mode(GPIO79_pSKTSEL_MD | GPIO_OUT); /* For 2-socket mode */
6779+
6780+ switch(skt->nr){
6781+ case 0:
6782+ if(state->flags & SS_RESET) {
6783+ //GPCR(GPIO79_pSKTSEL) = GPIO_bit(GPIO79_pSKTSEL); /* For 2-socket mode */
6784+ //udelay(1);
6785+ GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
6786+ GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
6787+ udelay(10);
6788+ GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
6789+ GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
6790+ }
6791+ break;
6792+ case 1:
6793+ if(state->flags & SS_RESET) {
6794+ //GPCR(GPIO79_pSKTSEL) = GPIO_bit(GPIO79_pSKTSEL); /* For 2-socket mode */
6795+ //udelay(1);
6796+ GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
6797+ GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
6798+ udelay(10);
6799+ GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
6800+ GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
6801+ }
6802+ break;
6803+ }
6804+
6805+ pxa_gpio_mode(GPIO49_nPWE_MD);
6806+ //pxa_gpio_mode(GPIO79_pSKTSEL_MD); /* For 2-socket mode */
6807+
6808+
6809+ return 0;
6810+}
6811+
6812+static void cmx270_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
6813+{
6814+}
6815+
6816+static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
6817+{
6818+}
6819+
6820+
6821+static struct pcmcia_low_level cmx270_pcmcia_ops = {
6822+ .owner = THIS_MODULE,
6823+ .hw_init = cmx270_pcmcia_hw_init,
6824+ .hw_shutdown = cmx270_pcmcia_shutdown,
6825+ .socket_state = cmx270_pcmcia_socket_state,
6826+ .configure_socket = cmx270_pcmcia_configure_socket,
6827+ .socket_init = cmx270_pcmcia_socket_init,
6828+ .socket_suspend = cmx270_pcmcia_socket_suspend,
6829+ .nr = 2,
6830+};
6831+
6832+static struct platform_device *cmx270_pcmcia_device;
6833+
6834+static int __init cmx270_pcmcia_init(void)
6835+{
6836+ int ret;
6837+
6838+ cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
6839+
6840+ if (!cmx270_pcmcia_device)
6841+ return -ENOMEM;
6842+
6843+ cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops;
6844+
6845+ printk ("Registering cm-x270 PCMCIA interface.\n");
6846+ ret = platform_device_add(cmx270_pcmcia_device);
6847+
6848+ if (ret)
6849+ platform_device_put(cmx270_pcmcia_device);
6850+
6851+ return ret;
6852+}
6853+
6854+static void __exit cmx270_pcmcia_exit(void)
6855+{
6856+ platform_device_unregister(cmx270_pcmcia_device);
6857+}
6858+
6859+module_init(cmx270_pcmcia_init);
6860+module_exit(cmx270_pcmcia_exit);
6861+
6862+MODULE_LICENSE("GPL");
6863diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
6864index 10535f0..e04624f 100644
6865--- a/drivers/serial/pxa.c
6866+++ b/drivers/serial/pxa.c
6867@@ -49,6 +49,8 @@ #include <asm/hardware.h>
6868 #include <asm/irq.h>
6869 #include <asm/arch/pxa-regs.h>
6870
6871+#define SERIAL_SA1100_MAJOR 204
6872+#define MINOR_START 5
6873
6874 struct uart_pxa_port {
6875 struct uart_port port;
6876@@ -683,7 +685,7 @@ serial_pxa_console_setup(struct console
6877 }
6878
6879 static struct console serial_pxa_console = {
6880- .name = "ttyS",
6881+ .name = "ttySA",
6882 .write = serial_pxa_console_write,
6883 .device = uart_console_device,
6884 .setup = serial_pxa_console_setup,
6885@@ -788,11 +790,16 @@ static struct uart_pxa_port serial_pxa_p
6886
6887 static struct uart_driver serial_pxa_reg = {
6888 .owner = THIS_MODULE,
6889- .driver_name = "PXA serial",
6890- .devfs_name = "tts/",
6891- .dev_name = "ttyS",
6892- .major = TTY_MAJOR,
6893- .minor = 64,
6894+/* .driver_name = "PXA serial", */
6895+/* .devfs_name = "tts/", */
6896+/* .dev_name = "ttyS", */
6897+/* .major = TTY_MAJOR, */
6898+/* .minor = 64, */
6899+ .driver_name = "ttySA",
6900+ .dev_name = "ttySA",
6901+ .devfs_name = "ttySA",
6902+ .major = SERIAL_SA1100_MAJOR,
6903+ .minor = MINOR_START,
6904 .nr = ARRAY_SIZE(serial_pxa_ports),
6905 .cons = PXA_CONSOLE,
6906 };
6907diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
6908index f5079c7..e49580a 100644
6909--- a/drivers/video/Kconfig
6910+++ b/drivers/video/Kconfig
6911@@ -1387,6 +1387,16 @@ config FB_PXA_PARAMETERS
6912
6913 <file:Documentation/fb/pxafb.txt> describes the available parameters.
6914
6915+config FB_MBX
6916+ tristate "2700G LCD framebuffer support"
6917+ depends on FB && ARCH_PXA
6918+ select FB_CFB_FILLRECT
6919+ select FB_CFB_COPYAREA
6920+ select FB_CFB_IMAGEBLIT
6921+ ---help---
6922+
6923+ If unsure, say N.
6924+
6925 config FB_W100
6926 tristate "W100 frame buffer support"
6927 depends on FB && PXA_SHARPSL
6928diff --git a/drivers/video/Makefile b/drivers/video/Makefile
6929index aa434e7..c6fe5e4 100644
6930--- a/drivers/video/Makefile
6931+++ b/drivers/video/Makefile
6932@@ -94,6 +94,7 @@ obj-$(CONFIG_FB_TX3912) += tx3912fb.o
6933 obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
6934 obj-$(CONFIG_FB_IMX) += imxfb.o
6935 obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
6936+obj-$(CONFIG_FB_MBX) += mbx/
6937
6938 # Platform or fallback drivers go here
6939 obj-$(CONFIG_FB_VESA) += vesafb.o
6940diff --git a/drivers/video/mbx/Makefile b/drivers/video/mbx/Makefile
6941new file mode 100644
6942index 0000000..ef6b729
6943--- /dev/null
6944+++ b/drivers/video/mbx/Makefile
6945@@ -0,0 +1,7 @@
6946+# Makefile for the Linux video drivers.
6947+# 5 Aug 1999, James Simmons, <mailto:jsimmons@users.sf.net>
6948+# Rewritten to use lists instead of if-statements.
6949+
6950+# Each configuration option enables a list of files.
6951+
6952+obj-$(CONFIG_FB_MBX) += mbxfb.o
6953diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
6954new file mode 100644
6955index 0000000..93dcfa5
6956--- /dev/null
6957+++ b/drivers/video/mbx/mbxfb.c
6958@@ -0,0 +1,659 @@
6959+/*
6960+ * linux/drivers/video/mbx/mbxfb.c
6961+ *
6962+ * Copyright (C) 2006 Compulab, Ltd.
6963+ *
6964+ * Based on pxafb.c
6965+ *
6966+ * This file is subject to the terms and conditions of the GNU General Public
6967+ * License. See the file COPYING in the main directory of this archive for
6968+ * more details.
6969+ *
6970+ * Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
6971+ *
6972+ */
6973+
6974+#include <linux/config.h>
6975+#include <linux/module.h>
6976+#include <linux/moduleparam.h>
6977+#include <linux/kernel.h>
6978+#include <linux/sched.h>
6979+#include <linux/errno.h>
6980+#include <linux/string.h>
6981+#include <linux/interrupt.h>
6982+#include <linux/slab.h>
6983+#include <linux/fb.h>
6984+#include <linux/delay.h>
6985+#include <linux/init.h>
6986+#include <linux/ioport.h>
6987+#include <linux/cpufreq.h>
6988+#include <linux/platform_device.h>
6989+#include <linux/dma-mapping.h>
6990+
6991+#include <asm/hardware.h>
6992+#include <asm/io.h>
6993+#include <asm/irq.h>
6994+#include <asm/uaccess.h>
6995+#include <asm/div64.h>
6996+#include <asm/arch/pxa-regs.h>
6997+#include <asm/arch/bitfield.h>
6998+#include <asm/arch/marathonfb.h>
6999+
7000+static unsigned long virt_base_2700;
7001+#include "regs.h"
7002+#include "reg_bits.h"
7003+
7004+#define MIN_XRES 16
7005+#define MIN_YRES 16
7006+#define MAX_XRES 2048
7007+#define MAX_YRES 2048
7008+
7009+/* FIXME: take care of different chip reivsions with different sizes
7010+ of ODFB */
7011+#define MEMORY_OFFSET 0x60000
7012+
7013+struct mbxfb_info {
7014+ struct device *dev;
7015+
7016+ struct resource *fb_res;
7017+ struct resource *fb_req;
7018+
7019+ struct resource *reg_res;
7020+ struct resource *reg_req;
7021+
7022+ void __iomem *fb_virt_addr;
7023+ unsigned long fb_phys_addr;
7024+
7025+ void __iomem *reg_virt_addr;
7026+ unsigned long reg_phys_addr;
7027+
7028+ int (*platform_probe)(struct fb_info *fb);
7029+ int (*platform_remove)(struct fb_info *fb);
7030+};
7031+
7032+static struct fb_var_screeninfo mbxfb_default __initdata = {
7033+ .xres = 640,
7034+ .yres = 480,
7035+ .xres_virtual = 640,
7036+ .yres_virtual = 480,
7037+ .bits_per_pixel = 16,
7038+ .red = { 11, 5, 0 },
7039+ .green = { 5, 6, 0 },
7040+ .blue = { 0, 5, 0 },
7041+ .activate = FB_ACTIVATE_TEST,
7042+ .height = -1,
7043+ .width = -1,
7044+ .pixclock = 40000,
7045+ .left_margin = 48,
7046+ .right_margin = 16,
7047+ .upper_margin = 33,
7048+ .lower_margin = 10,
7049+ .hsync_len = 96,
7050+ .vsync_len = 2,
7051+ .vmode = FB_VMODE_NONINTERLACED,
7052+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
7053+};
7054+
7055+static struct fb_fix_screeninfo mbxfb_fix __initdata = {
7056+ .id = "MBX",
7057+ .type = FB_TYPE_PACKED_PIXELS,
7058+ .visual = FB_VISUAL_TRUECOLOR,
7059+ .xpanstep = 0,
7060+ .ypanstep = 0,
7061+ .ywrapstep = 0,
7062+ .accel = FB_ACCEL_NONE,
7063+};
7064+
7065+struct pixclock_div {
7066+ u8 m;
7067+ u8 n;
7068+ u8 p;
7069+};
7070+
7071+static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps, struct pixclock_div *div)
7072+{
7073+ u8 m, n, p;
7074+ unsigned int err = 0;
7075+ unsigned int min_err = ~0x0;
7076+ unsigned int clk;
7077+ unsigned int best_clk = 0;
7078+ unsigned int ref_clk = 13000; /* FIXME: take from platform data */
7079+ unsigned int pixclock;
7080+
7081+ /* convert pixclock to KHz */
7082+ pixclock = PICOS2KHZ(pixclock_ps);
7083+
7084+ for ( m = 1; m < 64; m++ ) {
7085+ for ( n = 1; n < 8; n++ ) {
7086+ for ( p = 0; p < 8; p++ ) {
7087+ clk = (ref_clk * m) / (n * (1 << p));
7088+ err = (clk > pixclock) ? (clk - pixclock) :
7089+ (pixclock - clk);
7090+ if ( err < min_err ) {
7091+ min_err = err;
7092+ best_clk = clk;
7093+ div->m = m;
7094+ div->n = n;
7095+ div->p = p;
7096+ }
7097+ }
7098+ }
7099+ }
7100+ return KHZ2PICOS(best_clk);
7101+}
7102+
7103+static int
7104+mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
7105+ u_int trans, struct fb_info *info)
7106+{
7107+ uint val, ret = 1;
7108+
7109+ if ( regno < 255 ) {
7110+ val = (red & 0xff) << 16;
7111+ val |= (green & 0xff) << 8;
7112+ val |= (blue & 0xff) << 0;
7113+ GPLUT = Gplut_Lutadr(regno) | Gplut_Lutdata(val);
7114+ udelay(1000);
7115+ ret = 0;
7116+ }
7117+ return ret;
7118+}
7119+
7120+static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
7121+{
7122+ struct pixclock_div div;
7123+
7124+ var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
7125+
7126+ if (var->xres < MIN_XRES)
7127+ var->xres = MIN_XRES;
7128+ if (var->yres < MIN_YRES)
7129+ var->yres = MIN_YRES;
7130+ if (var->xres > MAX_XRES)
7131+ var->xres = MAX_XRES;
7132+ if (var->yres > MAX_YRES)
7133+ var->yres = MAX_YRES;
7134+ var->xres_virtual =
7135+ max(var->xres_virtual, var->xres);
7136+ var->yres_virtual =
7137+ max(var->yres_virtual, var->yres);
7138+
7139+ switch (var->bits_per_pixel) {
7140+ /* FIXME: implement 8 bits-per-pixel */
7141+ case 8:
7142+ var->bits_per_pixel = 16;
7143+ case 16:
7144+ var->green.length = (var->green.length == 5) ? 5 : 6;
7145+ var->red.length = 5;
7146+ var->blue.length = 5;
7147+ var->transp.length = 6 - var->green.length;
7148+ var->blue.offset = 0;
7149+ var->green.offset = 5;
7150+ var->red.offset = 5 + var->green.length;
7151+ var->transp.offset = (5 + var->red.offset) & 15;
7152+ break;
7153+ case 24: /* RGB 888 */
7154+ case 32: /* RGBA 8888 */
7155+ var->red.offset = 16;
7156+ var->red.length = 8;
7157+ var->green.offset = 8;
7158+ var->green.length = 8;
7159+ var->blue.offset = 0;
7160+ var->blue.length = 8;
7161+ var->transp.length = var->bits_per_pixel - 24;
7162+ var->transp.offset = (var->transp.length) ? 24 : 0;
7163+ break;
7164+ }
7165+ var->red.msb_right = 0;
7166+ var->green.msb_right = 0;
7167+ var->blue.msb_right = 0;
7168+ var->transp.msb_right = 0;
7169+
7170+ return 0;
7171+}
7172+
7173+static int mbxfb_set_par(struct fb_info *info)
7174+{
7175+ struct fb_var_screeninfo *var = &info->var;
7176+ struct pixclock_div div;
7177+ ushort hbps, ht, hfps, has;
7178+ ushort vbps, vt, vfps, vas;
7179+
7180+ info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
7181+
7182+ /* setup color mode */
7183+ GSCTRL &= ~(FMsk(GSCTRL_GPIXFMT));
7184+ /* FIXME: add *WORKING* support for 8-bits per color */
7185+ if ( info->var.bits_per_pixel == 8 ) {
7186+ GSCTRL |= GSCTRL_GPIXFMT_INDEXED;
7187+ GSCTRL |= GSCTRL_LUT_EN;
7188+ GSCTRL &= ~GSCTRL_GAMMA_EN;
7189+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
7190+ fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
7191+ }
7192+ else {
7193+ fb_dealloc_cmap(&info->cmap);
7194+ GSCTRL &= ~GSCTRL_LUT_EN;
7195+ info->fix.visual = FB_VISUAL_TRUECOLOR;
7196+ switch ( info->var.bits_per_pixel ) {
7197+ case 16:
7198+ if ( info->var.green.length == 5 )
7199+ GSCTRL |= GSCTRL_GPIXFMT_ARGB1555;
7200+ else
7201+ GSCTRL |= GSCTRL_GPIXFMT_RGB565;
7202+ break;
7203+ case 24:
7204+ GSCTRL |= GSCTRL_GPIXFMT_RGB888;
7205+ break;
7206+ case 32:
7207+ GSCTRL |= GSCTRL_GPIXFMT_ARGB8888;
7208+ break;
7209+ }
7210+ }
7211+
7212+ /* setup resolution */
7213+ GSCTRL &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
7214+ GSCTRL |= Gsctrl_Width(info->var.xres - 1) |
7215+ Gsctrl_Height(info->var.yres - 1);
7216+
7217+ GSADR &= ~(FMsk(GSADR_SRCSTRIDE)); udelay(1000);
7218+ GSADR |= Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel / (8 * 16) - 1); udelay(1000);
7219+
7220+ /* setup timings */
7221+ var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
7222+
7223+ DISPPLL = Disp_Pll_M(div.m) | Disp_Pll_N(div.n) | Disp_Pll_P(div.p) | DISP_PLL_EN;
7224+
7225+ hbps = var->hsync_len;
7226+ has = hbps + var->left_margin;
7227+ hfps = has + var->xres;
7228+ ht = hfps + var->right_margin;
7229+
7230+ vbps = var->vsync_len;
7231+ vas = vbps + var->upper_margin;
7232+ vfps = vas + var->yres;
7233+ vt = vfps + var->lower_margin;
7234+
7235+ DHT01 = Dht01_Hbps(hbps) | Dht01_Ht(ht);
7236+ DHT02 = Dht02_Hlbs(has) | Dht02_Has(has);
7237+ DHT03 = Dht03_Hfps(hfps) | Dht03_Hrbs(hfps);
7238+ DHDET = Dhdet_Hdes(has) | Dhdet_Hdef(hfps);
7239+
7240+ DVT01 = Dvt01_Vbps(vbps) | Dvt01_Vt(vt);
7241+ DVT02 = Dvt02_Vtbs(vas) | Dvt02_Vas(vas);
7242+ DVT03 = Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps);
7243+ DVDET = Dvdet_Vdes(vas) | Dvdet_Vdef(vfps);
7244+ DVECTRL = Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps);
7245+ DSCTRL |= DSCTRL_SYNCGEN_EN;
7246+
7247+ return 0;
7248+}
7249+
7250+static char *blank_mode[] = {
7251+ "FB_BLANK_UNBLANK",
7252+ "FB_BLANK_NORMAL",
7253+ "FB_BLANK_VSYNC_SUSPEND",
7254+ "FB_BLANK_HSYNC_SUSPEND",
7255+ "FB_BLANK_POWERDOWN",
7256+};
7257+
7258+static int mbxfb_blank(int blank, struct fb_info *info)
7259+{
7260+ switch (blank) {
7261+ case FB_BLANK_POWERDOWN:
7262+ case FB_BLANK_VSYNC_SUSPEND:
7263+ case FB_BLANK_HSYNC_SUSPEND:
7264+ case FB_BLANK_NORMAL:
7265+ DSCTRL &= ~DSCTRL_SYNCGEN_EN; udelay(1000);
7266+ PIXCLK &= ~PIXCLK_EN; udelay(1000);
7267+ VOVRCLK &= ~VOVRCLK_EN; udelay(1000);
7268+ break;
7269+ case FB_BLANK_UNBLANK:
7270+ DSCTRL |= DSCTRL_SYNCGEN_EN; udelay(1000);
7271+ PIXCLK |= PIXCLK_EN; udelay(1000);
7272+ break;
7273+ }
7274+ return 0;
7275+}
7276+
7277+static struct fb_ops mbxfb_ops = {
7278+ .owner = THIS_MODULE,
7279+ .fb_check_var = mbxfb_check_var,
7280+ .fb_set_par = mbxfb_set_par,
7281+ .fb_setcolreg = mbxfb_setcolreg,
7282+ .fb_fillrect = cfb_fillrect,
7283+ .fb_copyarea = cfb_copyarea,
7284+ .fb_imageblit = cfb_imageblit,
7285+ .fb_blank = mbxfb_blank,
7286+};
7287+
7288+/*
7289+ Enable external SDRAM controller. Assume that all clocks are active
7290+ by now.
7291+*/
7292+static void setup_memc(struct fb_info *fbi)
7293+{
7294+ unsigned long tmp;
7295+
7296+ /* FIXME: use platfrom specific parameters */
7297+ /* setup SDRAM controller */
7298+ LMCFG = LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS | LMCFG_LMA_TS;
7299+ udelay(1000);
7300+ LMPWR = LMPWR_MC_PWR_ACT;
7301+ udelay(1000);
7302+ /* setup SDRAM timings */
7303+ LMTIM = Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) | Lmtim_Trc(9) |
7304+ Lmtim_Tdpl(2);
7305+ udelay(1000);
7306+ /* setup SDRAM refresh rate */
7307+ LMREFRESH = 0xc2b;
7308+ udelay(1000);
7309+ /* setup SDRAM type parameters */
7310+ LMTYPE = LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
7311+ LMTYPE_COLSZ_8;
7312+ udelay(1000);
7313+ /* enable memory controller */
7314+ LMPWR = LMPWR_MC_PWR_ACT;
7315+ udelay(1000);
7316+
7317+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7318+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7319+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7320+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7321+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7322+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7323+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7324+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7325+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7326+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7327+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
7328+}
7329+
7330+static void enable_clocks(struct fb_info* fbi)
7331+{
7332+ /* enable clocks */
7333+ SYSCLKSRC = SYSCLKSRC_PLL_2; udelay(1000);
7334+ PIXCLKSRC = PIXCLKSRC_PLL_1; udelay(1000);
7335+ CLKSLEEP = 0x00000000; udelay(1000);
7336+ COREPLL = Core_Pll_M(0x17) | Core_Pll_N(0x3) | Core_Pll_P(0x0) | CORE_PLL_EN; udelay(1000);
7337+ DISPPLL = Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) | DISP_PLL_EN;
7338+
7339+ VOVRCLK = 0x00000000; udelay(1000);
7340+ PIXCLK = PIXCLK_EN; udelay(1000);
7341+ MEMCLK = MEMCLK_EN; udelay(1000);
7342+ M24CLK = 0x00000006; udelay(1000);
7343+ MBXCLK = 0x00000006; udelay(1000);
7344+ SDCLK = SDCLK_EN; udelay(1000);
7345+ PIXCLKDIV = 0x00000001; udelay(1000);
7346+}
7347+
7348+static void setup_graphics(struct fb_info* fbi)
7349+{
7350+ unsigned long gsctrl;
7351+
7352+ gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres-1) |
7353+ Gsctrl_Height(fbi->var.yres-1);
7354+ switch ( fbi->var.bits_per_pixel ) {
7355+ case 16:
7356+ if ( fbi->var.green.length == 5 )
7357+ gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
7358+ else
7359+ gsctrl |= GSCTRL_GPIXFMT_RGB565;
7360+ break;
7361+ case 24: gsctrl |= GSCTRL_GPIXFMT_RGB888; break;
7362+ case 32: gsctrl |= GSCTRL_GPIXFMT_ARGB8888; break;
7363+ }
7364+
7365+ GSCTRL = gsctrl; udelay(1000);
7366+ GBBASE = 0x00000000; udelay(1000);
7367+ GDRCTRL = 0x00ffffff; udelay(1000);
7368+ GSCADR = GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000); udelay(1000);
7369+ GPLUT = 0x00000000; udelay(1000);
7370+}
7371+
7372+static void setup_display(struct fb_info* fbi)
7373+{
7374+ unsigned long dsctrl = 0;
7375+
7376+ dsctrl = DSCTRL_BLNK_POL;
7377+ if ( fbi->var.sync & FB_SYNC_HOR_HIGH_ACT )
7378+ dsctrl |= DSCTRL_HS_POL;
7379+ if ( fbi->var.sync & FB_SYNC_VERT_HIGH_ACT )
7380+ dsctrl |= DSCTRL_VS_POL;
7381+ DSCTRL = dsctrl; udelay(1000);
7382+ DMCTRL = 0xd0303010; udelay(1000);
7383+ DSCTRL |= DSCTRL_SYNCGEN_EN;
7384+}
7385+
7386+static void enable_controller(struct fb_info* fbi)
7387+{
7388+ SYSRST = SYSRST_RST;
7389+ udelay(1000);
7390+
7391+ enable_clocks(fbi);
7392+ setup_memc(fbi);
7393+ setup_graphics(fbi);
7394+ setup_display(fbi);
7395+}
7396+
7397+
7398+#ifdef CONFIG_PM
7399+/*
7400+ * Power management hooks. Note that we won't be called from IRQ context,
7401+ * unlike the blank functions above, so we may sleep.
7402+ */
7403+static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
7404+{
7405+ /* make frame buffer memory enter self-refresh mode */
7406+ LMPWR = LMPWR_MC_PWR_SRM;
7407+ while ( LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM );
7408+
7409+ /* reset the device, since it's initial state is 'mostly sleeping' */
7410+ SYSRST = SYSRST_RST;
7411+ return 0;
7412+}
7413+
7414+static int mbxfb_resume(struct platform_device *dev)
7415+{
7416+ struct fb_info *fbi = (struct fb_info*)platform_get_drvdata(dev);
7417+
7418+ enable_clocks(fbi);
7419+/* setup_graphics(fbi); */
7420+/* setup_display(fbi); */
7421+
7422+ DSCTRL |= DSCTRL_SYNCGEN_EN;
7423+ return 0;
7424+}
7425+#else
7426+#define mbxfb_suspend NULL
7427+#define mbxfb_resume NULL
7428+#endif
7429+
7430+#include "mbxsysfs.c"
7431+
7432+#define res_size(_r) (((_r)->end - (_r)->start) + 1)
7433+
7434+static int mbxfb_probe(struct platform_device *dev)
7435+{
7436+ int ret;
7437+ struct fb_info *fbi;
7438+ struct mbxfb_info *mfbi;
7439+ struct mbxfb_platform_data *pdata;
7440+
7441+ dev_dbg(dev, "mbxfb_probe\n");
7442+
7443+ fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
7444+ if ( fbi == NULL ) {
7445+ dev_err(&dev->dev, "framebuffer_alloc failed\n");
7446+ return -ENOMEM;
7447+ }
7448+
7449+ mfbi = fbi->par;
7450+ pdata = dev->dev.platform_data;
7451+ if ( pdata->probe )
7452+ mfbi->platform_probe = pdata->probe;
7453+ if ( pdata->remove )
7454+ mfbi->platform_remove = pdata->remove;
7455+
7456+ mfbi->fb_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
7457+ mfbi->reg_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
7458+
7459+ if ( !mfbi->fb_res || !mfbi->reg_res ) {
7460+ dev_err(&dev->dev, "no resources found\n");
7461+ ret = -ENODEV;
7462+ goto err1;
7463+ }
7464+
7465+ mfbi->fb_req = request_mem_region(mfbi->fb_res->start,
7466+ res_size(mfbi->fb_res),
7467+ dev->name);
7468+ if ( mfbi->fb_req == NULL ) {
7469+ dev_err(&dev->dev, "failed to claim framebuffer memory\n");
7470+ ret = -EINVAL;
7471+ goto err1;
7472+ }
7473+ mfbi->fb_phys_addr = mfbi->fb_res->start;
7474+
7475+ mfbi->reg_req = request_mem_region(mfbi->reg_res->start,
7476+ res_size(mfbi->reg_res),
7477+ dev->name);
7478+ if ( mfbi->reg_req == NULL ) {
7479+ dev_err(&dev->dev, "failed to claim Marathon registers\n");
7480+ ret = -EINVAL;
7481+ goto err2;
7482+ }
7483+ mfbi->reg_phys_addr = mfbi->reg_res->start;
7484+
7485+ mfbi->reg_virt_addr = ioremap_nocache(mfbi->reg_phys_addr,
7486+ res_size(mfbi->reg_req));
7487+ if ( !mfbi->reg_virt_addr ) {
7488+ dev_err(&dev->dev, "failed to ioremap Marathon registers\n");
7489+ ret = -EINVAL;
7490+ goto err3;
7491+ }
7492+ virt_base_2700 = mfbi->reg_virt_addr;
7493+
7494+ mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr,
7495+ res_size(mfbi->fb_req));
7496+ if ( !mfbi->reg_virt_addr ) {
7497+ dev_err(&dev->dev, "failed to ioremap frame buffer\n");
7498+ ret = -EINVAL;
7499+ goto err4;
7500+ }
7501+
7502+ fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000); /* FIXME: */
7503+ fbi->screen_size = 8*1024*1024; /* 8 Megs */ /* FIXME: get from platform */
7504+ fbi->fbops = &mbxfb_ops;
7505+
7506+ fbi->var = mbxfb_default;
7507+ fbi->fix = mbxfb_fix;
7508+ fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
7509+ fbi->fix.smem_len = 8*1024*1024;
7510+ fbi->fix.line_length = 640*2;
7511+
7512+ ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
7513+ if (ret < 0) {
7514+ dev_err(&dev->dev, "fb_alloc_cmap failed\n");
7515+ ret = -EINVAL;
7516+ goto err5;
7517+ }
7518+
7519+ ret = register_framebuffer(fbi);
7520+ if (ret < 0) {
7521+ dev_err(&dev->dev, "register_framebuffer failed\n");
7522+ ret = -EINVAL;
7523+ goto err6;
7524+ }
7525+
7526+ platform_set_drvdata(dev, fbi);
7527+
7528+ printk(KERN_INFO "fb%d: mbx frame buffer device\n", fbi->node);
7529+
7530+ if ( mfbi->platform_probe )
7531+ mfbi->platform_probe(fbi);
7532+
7533+ enable_controller(fbi);
7534+
7535+ mbxfb_sysfs_register(fbi);
7536+
7537+ return 0;
7538+
7539+ err6:
7540+ fb_dealloc_cmap(&fbi->cmap);
7541+ err5:
7542+ iounmap(mfbi->fb_virt_addr);
7543+ err4:
7544+ iounmap(mfbi->reg_virt_addr);
7545+ err3:
7546+ release_mem_region(mfbi->reg_res->start,
7547+ res_size(mfbi->reg_res));
7548+ err2:
7549+ release_mem_region(mfbi->fb_res->start,
7550+ res_size(mfbi->fb_res));
7551+ err1:
7552+ framebuffer_release(fbi);
7553+
7554+ return ret;
7555+}
7556+
7557+static int mbxfb_remove(struct platform_device *dev)
7558+{
7559+ struct fb_info *fbi = (struct fb_info*)platform_get_drvdata(dev);
7560+
7561+ SYSRST = SYSRST_RST;
7562+ udelay(1000);
7563+
7564+ if (fbi) {
7565+ struct mbxfb_info *mfbi = fbi->par;
7566+
7567+ unregister_framebuffer(fbi);
7568+ if ( mfbi ) {
7569+ if ( mfbi->platform_remove )
7570+ mfbi->platform_remove(fbi);
7571+
7572+ if ( mfbi->fb_virt_addr )
7573+ iounmap(mfbi->fb_virt_addr);
7574+ if ( mfbi->reg_virt_addr )
7575+ iounmap(mfbi->reg_virt_addr);
7576+ if ( mfbi->reg_req )
7577+ release_mem_region(mfbi->reg_req->start,
7578+ res_size(mfbi->reg_req));
7579+ if ( mfbi->fb_req )
7580+ release_mem_region(mfbi->fb_req->start,
7581+ res_size(mfbi->fb_req));
7582+ }
7583+ framebuffer_release(fbi);
7584+ }
7585+
7586+ return 0;
7587+}
7588+
7589+static struct platform_driver mbxfb_driver = {
7590+ .probe = mbxfb_probe,
7591+ .remove = mbxfb_remove,
7592+
7593+#ifdef CONFIG_PM
7594+ .suspend = mbxfb_suspend,
7595+ .resume = mbxfb_resume,
7596+#endif
7597+ .driver = {
7598+ .name = "mbx-fb",
7599+ },
7600+};
7601+
7602+int __devinit mbxfb_init(void)
7603+{
7604+ return platform_driver_register(&mbxfb_driver);
7605+}
7606+
7607+static void __exit mbxfb_exit(void)
7608+{
7609+ platform_driver_unregister(&mbxfb_driver);
7610+}
7611+
7612+module_init(mbxfb_init);
7613+module_exit(mbxfb_exit);
7614+
7615+MODULE_DESCRIPTION("loadable framebuffer driver for Marathon device");
7616+MODULE_AUTHOR("Mike Rapoport, Compulab");
7617+MODULE_LICENSE("GPL");
7618diff --git a/drivers/video/mbx/mbxsysfs.c b/drivers/video/mbx/mbxsysfs.c
7619new file mode 100644
7620index 0000000..4b9571a
7621--- /dev/null
7622+++ b/drivers/video/mbx/mbxsysfs.c
7623@@ -0,0 +1,129 @@
7624+static ssize_t sysconf_show(struct class_device * subsys, char * buf)
7625+{
7626+ char * s = buf;
7627+
7628+ s += sprintf(s, "SYSCFG = %08lx\n", SYSCFG);
7629+ s += sprintf(s, "PFBASE = %08lx\n", PFBASE);
7630+ s += sprintf(s, "PFCEIL = %08lx\n", PFCEIL);
7631+ s += sprintf(s, "POLLFLAG = %08lx\n", POLLFLAG);
7632+ s += sprintf(s, "SYSRST = %08lx\n", SYSRST);
7633+ return (s - buf);
7634+}
7635+
7636+static ssize_t sysconf_store(struct class_device * subsys, const char * buf, size_t n)
7637+{
7638+ return n;
7639+}
7640+
7641+static ssize_t gsctl_show(struct class_device * subsys, char * buf)
7642+{
7643+ char * s = buf;
7644+
7645+ s += sprintf(s, "GSCTRL = %08lx\n", GSCTRL);
7646+ s += sprintf(s, "VSCTRL = %08lx\n", VSCTRL);
7647+ s += sprintf(s, "GBBASE = %08lx\n", GBBASE);
7648+ s += sprintf(s, "VBBASE = %08lx\n", VBBASE);
7649+ s += sprintf(s, "GDRCTRL = %08lx\n", GDRCTRL);
7650+ s += sprintf(s, "VCMSK = %08lx\n", VCMSK);
7651+ s += sprintf(s, "GSCADR = %08lx\n", GSCADR);
7652+ s += sprintf(s, "VSCADR = %08lx\n", VSCADR);
7653+ s += sprintf(s, "VUBASE = %08lx\n", VUBASE);
7654+ s += sprintf(s, "VVBASE = %08lx\n", VVBASE);
7655+ s += sprintf(s, "GSADR = %08lx\n", GSADR);
7656+ s += sprintf(s, "VSADR = %08lx\n", VSADR);
7657+ s += sprintf(s, "HCCTRL = %08lx\n", HCCTRL);
7658+ s += sprintf(s, "HCSIZE = %08lx\n", HCSIZE);
7659+ s += sprintf(s, "HCPOS = %08lx\n", HCPOS);
7660+ s += sprintf(s, "HCBADR = %08lx\n", HCBADR);
7661+ s += sprintf(s, "HCCKMSK = %08lx\n", HCCKMSK);
7662+ s += sprintf(s, "GPLUT = %08lx\n", GPLUT);
7663+ return (s - buf);
7664+}
7665+
7666+static ssize_t gsctl_store(struct class_device * subsys, const char * buf, size_t n)
7667+{
7668+ return n;
7669+}
7670+
7671+static ssize_t display_show(struct class_device * subsys, char * buf)
7672+{
7673+ char * s = buf;
7674+
7675+ s += sprintf(s, "DSCTRL = %08lx\n", DSCTRL);
7676+ s += sprintf(s, "DHT01 = %08lx\n", DHT01);
7677+ s += sprintf(s, "DHT02 = %08lx\n", DHT02);
7678+ s += sprintf(s, "DHT03 = %08lx\n", DHT03);
7679+ s += sprintf(s, "DVT01 = %08lx\n", DVT01);
7680+ s += sprintf(s, "DVT02 = %08lx\n", DVT02);
7681+ s += sprintf(s, "DVT03 = %08lx\n", DVT03);
7682+ s += sprintf(s, "DBCOL = %08lx\n", DBCOL);
7683+ s += sprintf(s, "BGCOLOR = %08lx\n", BGCOLOR);
7684+ s += sprintf(s, "DINTRS = %08lx\n", DINTRS);
7685+ s += sprintf(s, "DINTRE = %08lx\n", DINTRE);
7686+ s += sprintf(s, "DINTRCNT = %08lx\n", DINTRCNT);
7687+ s += sprintf(s, "DSIG = %08lx\n", DSIG);
7688+ s += sprintf(s, "DMCTRL = %08lx\n", DMCTRL);
7689+ s += sprintf(s, "CLIPCTRL = %08lx\n", CLIPCTRL);
7690+ s += sprintf(s, "SPOCTRL = %08lx\n", SPOCTRL);
7691+ s += sprintf(s, "SVCTRL = %08lx\n", SVCTRL);
7692+ s += sprintf(s, "DLSTS = %08lx\n", DLSTS);
7693+ s += sprintf(s, "DLLCTRL = %08lx\n", DLLCTRL);
7694+ s += sprintf(s, "DVLNUM = %08lx\n", DVLNUM);
7695+ s += sprintf(s, "DUCTRL = %08lx\n", DUCTRL);
7696+ s += sprintf(s, "DVECTRL = %08lx\n", DVECTRL);
7697+ s += sprintf(s, "DHDET = %08lx\n", DHDET);
7698+ s += sprintf(s, "DVDET = %08lx\n", DVDET);
7699+ s += sprintf(s, "DODMSK = %08lx\n", DODMSK);
7700+ s += sprintf(s, "CSC01 = %08lx\n", CSC01);
7701+ s += sprintf(s, "CSC02 = %08lx\n", CSC02);
7702+ s += sprintf(s, "CSC03 = %08lx\n", CSC03);
7703+ s += sprintf(s, "CSC04 = %08lx\n", CSC04);
7704+ s += sprintf(s, "CSC05 = %08lx\n", CSC05);
7705+ return (s - buf);
7706+}
7707+
7708+static ssize_t display_store(struct class_device * subsys, const char * buf, size_t n)
7709+{
7710+ return n;
7711+}
7712+
7713+static ssize_t clock_show(struct class_device * subsys, char * buf)
7714+{
7715+ char * s = buf;
7716+
7717+ s += sprintf(s, "SYSCLKSRC = %08lx\n", SYSCLKSRC);
7718+ s += sprintf(s, "PIXCLKSRC = %08lx\n", PIXCLKSRC);
7719+ s += sprintf(s, "CLKSLEEP = %08lx\n", CLKSLEEP);
7720+ s += sprintf(s, "COREPLL = %08lx\n", COREPLL);
7721+ s += sprintf(s, "DISPPLL = %08lx\n", DISPPLL);
7722+ s += sprintf(s, "PLLSTAT = %08lx\n", PLLSTAT);
7723+ s += sprintf(s, "VOVRCLK = %08lx\n", VOVRCLK);
7724+ s += sprintf(s, "PIXCLK = %08lx\n", PIXCLK);
7725+ s += sprintf(s, "MEMCLK = %08lx\n", MEMCLK);
7726+ s += sprintf(s, "M24CLK = %08lx\n", M24CLK);
7727+ s += sprintf(s, "MBXCLK = %08lx\n", MBXCLK);
7728+ s += sprintf(s, "SDCLK = %08lx\n", SDCLK);
7729+ s += sprintf(s, "PIXCLKDIV = %08lx\n", PIXCLKDIV);
7730+ return (s - buf);
7731+}
7732+
7733+static ssize_t clock_store(struct class_device * subsys, const char * buf, size_t n)
7734+{
7735+ return n;
7736+}
7737+
7738+static struct class_device_attribute mbx_class_attrs[] = {
7739+ __ATTR(sysconf,0644,sysconf_show,sysconf_store),
7740+ __ATTR(gsctl,0644,gsctl_show,gsctl_store),
7741+ __ATTR(display,0644,display_show,display_store),
7742+ __ATTR(clock,0644,clock_show,clock_store),
7743+};
7744+
7745+
7746+static void mbxfb_sysfs_register(struct fb_info *fbi)
7747+{
7748+ int i;
7749+ for (i = 0; i < ARRAY_SIZE(mbx_class_attrs); i++)
7750+ class_device_create_file(fbi->class_device,
7751+ &mbx_class_attrs[i]);
7752+}
7753diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h
7754new file mode 100644
7755index 0000000..be152f6
7756--- /dev/null
7757+++ b/drivers/video/mbx/reg_bits.h
7758@@ -0,0 +1,489 @@
7759+#ifndef __REG_BITS_2700G_
7760+#define __REG_BITS_2700G_
7761+
7762+/* /\* System Configuration Registers (0x03FE_0000 0x03FE_0010) *\/ */
7763+/* #define SYSCFG __REG_2700G(0x03FE0000) */
7764+/* #define PFBASE __REG_2700G(0x03FE0004) */
7765+/* #define PFCEIL __REG_2700G(0x03FE0008) */
7766+/* #define POLLFLAG __REG_2700G(0x03FE000C) */
7767+
7768+#define SYSRST_RST (1 << 0)
7769+
7770+/* /\* Interrupt Control Registers (0x03FE_0014 0x03FE_002F) *\/ */
7771+/* #define NINTPW __REG_2700G(0x03FE0014) */
7772+/* #define MINTENABLE __REG_2700G(0x03FE0018) */
7773+/* #define MINTSTAT __REG_2700G(0x03FE001C) */
7774+/* #define SINTENABLE __REG_2700G(0x03FE0020) */
7775+/* #define SINTSTAT __REG_2700G(0x03FE0024) */
7776+/* #define SINTCLR __REG_2700G(0x03FE0028) */
7777+
7778+/* SYSCLKSRC - SYSCLK Source Control Register */
7779+#define SYSCLKSRC_SEL Fld(2,0)
7780+#define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
7781+#define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
7782+#define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
7783+
7784+/* PIXCLKSRC - PIXCLK Source Control Register */
7785+#define PIXCLKSRC_SEL Fld(2,0)
7786+#define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
7787+#define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
7788+#define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
7789+
7790+/* Clock Disable Register */
7791+#define CLKSLEEP_SLP (1 << 0)
7792+
7793+/* Core PLL Control Register */
7794+#define CORE_PLL_M Fld(6,7)
7795+#define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
7796+#define CORE_PLL_N Fld(3,4)
7797+#define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
7798+#define CORE_PLL_P Fld(3,1)
7799+#define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
7800+#define CORE_PLL_EN (1 << 0)
7801+
7802+/* Display PLL Control Register */
7803+#define DISP_PLL_M Fld(6,7)
7804+#define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
7805+#define DISP_PLL_N Fld(3,4)
7806+#define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
7807+#define DISP_PLL_P Fld(3,1)
7808+#define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
7809+#define DISP_PLL_EN (1 << 0)
7810+
7811+/* PLL status register */
7812+#define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
7813+#define PLLSTAT_CORE_PLL_LSTS (1 << 2)
7814+#define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
7815+#define PLLSTAT_DISP_PLL_LSTS (1 << 0)
7816+
7817+/* Video and scale clock control register */
7818+#define VOVRCLK_EN (1 << 0)
7819+
7820+/* Pixel clock control register */
7821+#define PIXCLK_EN (1 << 0)
7822+
7823+/* Memory clock control register */
7824+#define MEMCLK_EN (1 << 0)
7825+
7826+/* MBX clock control register */
7827+#define MBXCLK_DIV Fld(2,2)
7828+#define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
7829+#define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
7830+#define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
7831+#define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
7832+#define MBXCLK_EN Fld(2,0)
7833+#define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
7834+#define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
7835+#define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
7836+
7837+/* M24 clock control register */
7838+#define M24CLK_DIV Fld(2,1)
7839+#define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
7840+#define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
7841+#define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
7842+#define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
7843+#define M24CLK_EN (1 << 0)
7844+
7845+/* SDRAM clock control register */
7846+#define SDCLK_EN (1 << 0)
7847+
7848+/* PixClk Divisor Register */
7849+#define PIXCLKDIV_PD Fld(9,0)
7850+#define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
7851+
7852+/* LCD Config control register */
7853+#define LCDCFG_IN_FMT Fld(3,28)
7854+#define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
7855+#define LCDCFG_LCD1DEN_POL (1 << 27)
7856+#define LCDCFG_LCD1FCLK_POL (1 << 26)
7857+#define LCDCFG_LCD1LCLK_POL (1 << 25)
7858+#define LCDCFG_LCD1D_POL (1 << 24)
7859+#define LCDCFG_LCD2DEN_POL (1 << 23)
7860+#define LCDCFG_LCD2FCLK_POL (1 << 22)
7861+#define LCDCFG_LCD2LCLK_POL (1 << 21)
7862+#define LCDCFG_LCD2D_POL (1 << 20)
7863+#define LCDCFG_LCD1_TS (1 << 19)
7864+#define LCDCFG_LCD1D_DS (1 << 18)
7865+#define LCDCFG_LCD1C_DS (1 << 17)
7866+#define LCDCFG_LCD1_IS_IN (1 << 16)
7867+#define LCDCFG_LCD2_TS (1 << 3)
7868+#define LCDCFG_LCD2D_DS (1 << 2)
7869+#define LCDCFG_LCD2C_DS (1 << 1)
7870+#define LCDCFG_LCD2_IS_IN (1 << 0)
7871+
7872+/* On-Die Frame Buffer Power Control Register */
7873+#define ODFBPWR_SLOW (1 << 2)
7874+#define ODFBPWR_MODE Fld(2,0)
7875+#define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
7876+#define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
7877+#define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
7878+#define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
7879+
7880+/* On-Die Frame Buffer Power State Status Register */
7881+#define ODFBSTAT_ACT (1 << 2)
7882+#define ODFBSTAT_SLP (1 << 1)
7883+#define ODFBSTAT_SDN (1 << 0)
7884+
7885+/* /\* GPIO Registers (0x03FE_006C 0x03FE_007F) *\/ */
7886+/* #define GPIOCGF __REG_2700G(0x03FE006C) */
7887+/* #define GPIOHI __REG_2700G(0x03FE0070) */
7888+/* #define GPIOLO __REG_2700G(0x03FE0074) */
7889+/* #define GPIOSTAT __REG_2700G(0x03FE0078) */
7890+
7891+/* /\* Pulse Width Modulator (PWM) Registers (0x03FE_0200 0x03FE_02FF) *\/ */
7892+/* #define PWMRST __REG_2700G(0x03FE0200) */
7893+/* #define PWMCFG __REG_2700G(0x03FE0204) */
7894+/* #define PWM0DIV __REG_2700G(0x03FE0210) */
7895+/* #define PWM0DUTY __REG_2700G(0x03FE0214) */
7896+/* #define PWM0PER __REG_2700G(0x03FE0218) */
7897+/* #define PWM1DIV __REG_2700G(0x03FE0220) */
7898+/* #define PWM1DUTY __REG_2700G(0x03FE0224) */
7899+/* #define PWM1PER __REG_2700G(0x03FE0228) */
7900+
7901+
7902+/* LMRST - Local Memory (SDRAM) Reset */
7903+#define LMRST_MC_RST (1 << 0)
7904+
7905+/* LMCFG - Local Memory (SDRAM) Configuration Register */
7906+#define LMCFG_LMC_DS (1 << 5)
7907+#define LMCFG_LMD_DS (1 << 4)
7908+#define LMCFG_LMA_DS (1 << 3)
7909+#define LMCFG_LMC_TS (1 << 2)
7910+#define LMCFG_LMD_TS (1 << 1)
7911+#define LMCFG_LMA_TS (1 << 0)
7912+
7913+/* LMPWR - Local Memory (SDRAM) Power Control Register */
7914+#define LMPWR_MC_PWR_CNT Fld(2,0)
7915+#define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
7916+#define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
7917+#define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
7918+
7919+/* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
7920+#define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
7921+#define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
7922+#define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
7923+#define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
7924+
7925+/* LMTYPE - Local Memory (SDRAM) Type Register */
7926+#define LMTYPE_CASLAT Fld(3,10)
7927+#define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
7928+#define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
7929+#define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
7930+#define LMTYPE_BKSZ Fld(2,8)
7931+#define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
7932+#define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
7933+#define LMTYPE_ROWSZ Fld(4,4)
7934+#define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
7935+#define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
7936+#define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
7937+#define LMTYPE_COLSZ Fld(4,0)
7938+#define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
7939+#define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
7940+#define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
7941+#define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
7942+#define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
7943+#define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
7944+
7945+/* LMTIM - Local Memory (SDRAM) Timing Register */
7946+#define LMTIM_TRAS Fld(4,16)
7947+#define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
7948+#define LMTIM_TRP Fld(4,12)
7949+#define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
7950+#define LMTIM_TRCD Fld(4,8)
7951+#define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
7952+#define LMTIM_TRC Fld(4,4)
7953+#define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
7954+#define LMTIM_TDPL Fld(4,0)
7955+#define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
7956+
7957+/* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
7958+#define LMREFRESH_TREF Fld(2,0)
7959+#define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
7960+
7961+/* #define LMCEMR __REG_2700G(0x03FE1010) */
7962+/* #define LMPROTMIN __REG_2700G(0x03FE1020) */
7963+/* #define LMPROTMAX __REG_2700G(0x03FE1024) */
7964+/* #define LMPROTCFG __REG_2700G(0x03FE1028) */
7965+/* #define LMPROTERR __REG_2700G(0x03FE102C) */
7966+
7967+/* GSCTRL - Graphics surface control register */
7968+#define GSCTRL_LUT_EN (1 << 31)
7969+#define GSCTRL_GPIXFMT Fld(4,27)
7970+#define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
7971+#define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
7972+#define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
7973+#define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
7974+#define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
7975+#define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
7976+#define GSCTRL_GAMMA_EN (1 << 26)
7977+
7978+#define GSCTRL_GSWIDTH Fld(11,11)
7979+#define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
7980+ (((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
7981+
7982+#define GSCTRL_GSHEIGHT Fld(11,0)
7983+#define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
7984+ (((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
7985+
7986+/* GBBASE fileds */
7987+#define GBBASE_GLALPHA Fld(8,24)
7988+#define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
7989+
7990+#define GBBASE_COLKEY Fld(24,0)
7991+#define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
7992+
7993+/* GDRCTRL fields */
7994+#define GDRCTRL_PIXDBL (1 << 31)
7995+#define GDRCTRL_PIXHLV (1 << 30)
7996+#define GDRCTRL_LNDBL (1 << 29)
7997+#define GDRCTRL_LNHLV (1 << 28)
7998+#define GDRCTRL_COLKEYM Fld(24,0)
7999+#define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
8000+
8001+/* GSCADR graphics stream control address register fields */
8002+#define GSCADR_STR_EN (1 << 31)
8003+#define GSCADR_COLKEY_EN (1 << 30)
8004+#define GSCADR_COLKEYSCR (1 << 29)
8005+#define GSCADR_BLEND_M Fld(2,27)
8006+#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
8007+#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
8008+#define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
8009+#define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
8010+#define GSCADR_BLEND_POS Fld(2,24)
8011+#define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
8012+#define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
8013+#define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
8014+#define GSCADR_GBASE_ADR Fld(23,0)
8015+#define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
8016+
8017+/* GSADR graphics stride address register fields */
8018+#define GSADR_SRCSTRIDE Fld(10,22)
8019+#define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
8020+#define GSADR_XSTART Fld(11,11)
8021+#define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
8022+#define GSADR_YSTART Fld(11,0)
8023+#define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
8024+
8025+/* GPLUT graphics palette register fields */
8026+#define GPLUT_LUTADR Fld(8,24)
8027+#define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
8028+#define GPLUT_LUTDATA Fld(24,0)
8029+#define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
8030+
8031+/* #define VSCTRL __REG_2700G(0x03FE2004) */
8032+/* #define VBBASE __REG_2700G(0x03FE2024) */
8033+/* #define VCMSK __REG_2700G(0x03FE2044) */
8034+/* #define VSCADR __REG_2700G(0x03FE2064) */
8035+/* #define VUBASE __REG_2700G(0x03FE2084) */
8036+/* #define VVBASE __REG_2700G(0x03FE20A4) */
8037+/* #define VSADR __REG_2700G(0x03FE20C4) */
8038+
8039+
8040+/* HCCTRL - Hardware Cursor Register fields */
8041+#define HCCTRL_CUR_EN (1 << 31)
8042+#define HCCTRL_COLKEY_EN (1 << 29)
8043+#define HCCTRL_COLKEYSRC (1 << 28)
8044+#define HCCTRL_BLEND_M Fld(2,26)
8045+#define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
8046+#define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
8047+#define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
8048+#define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
8049+#define HCCTRL_CPIXFMT Fld(3,23)
8050+#define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
8051+#define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
8052+#define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
8053+#define HCCTRL_CBASE_ADR Fld(23,0)
8054+#define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
8055+
8056+/* HCSIZE Hardware Cursor Size Register fields */
8057+#define HCSIZE_BLEND_POS Fld(2,29)
8058+#define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
8059+#define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
8060+#define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
8061+#define HCSIZE_CWIDTH Fld(3,16)
8062+#define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
8063+#define HCSIZE_CHEIGHT Fld(3,0)
8064+#define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
8065+
8066+/* HCPOS Hardware Cursor Position Register fields */
8067+#define HCPOS_SWITCHSRC (1 << 30)
8068+#define HCPOS_CURBLINK Fld(6,24)
8069+#define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
8070+#define HCPOS_XSTART Fld(12,12)
8071+#define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
8072+#define HCPOS_YSTART Fld(12,0)
8073+#define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
8074+
8075+/* HCBADR Hardware Cursor Blend Address Register */
8076+#define HCBADR_GLALPHA Fld(8,24)
8077+#define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
8078+#define HCBADR_COLKEY Fld(24,0)
8079+#define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
8080+
8081+/* HCCKMSK - Hardware Cursor Color Key Mask Register */
8082+#define HCCKMSK_COLKEY_M Fld(24,0)
8083+#define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
8084+
8085+/* DSCTRL - Display sync control register */
8086+#define DSCTRL_SYNCGEN_EN (1 << 31)
8087+#define DSCTRL_DPL_RST (1 << 29)
8088+#define DSCTRL_PWRDN_M (1 << 28)
8089+#define DSCTRL_UPDSYNCCNT (1 << 26)
8090+#define DSCTRL_UPDINTCNT (1 << 25)
8091+#define DSCTRL_UPDCNT (1 << 24)
8092+#define DSCTRL_UPDWAIT Fld(4,16)
8093+#define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
8094+#define DSCTRL_CLKPOL (1 << 11)
8095+#define DSCTRL_CSYNC_EN (1 << 10)
8096+#define DSCTRL_VS_SLAVE (1 << 7)
8097+#define DSCTRL_HS_SLAVE (1 << 6)
8098+#define DSCTRL_BLNK_POL (1 << 5)
8099+#define DSCTRL_BLNK_DIS (1 << 4)
8100+#define DSCTRL_VS_POL (1 << 3)
8101+#define DSCTRL_VS_DIS (1 << 2)
8102+#define DSCTRL_HS_POL (1 << 1)
8103+#define DSCTRL_HS_DIS (1 << 0)
8104+
8105+/* DHT01 - Display horizontal timing register 01 */
8106+#define DHT01_HBPS Fld(12,16)
8107+#define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
8108+#define DHT01_HT Fld(12,0)
8109+#define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
8110+
8111+/* DHT02 - Display horizontal timing register 02 */
8112+#define DHT02_HAS Fld(12,16)
8113+#define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
8114+#define DHT02_HLBS Fld(12,0)
8115+#define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
8116+
8117+/* DHT03 - Display horizontal timing register 03 */
8118+#define DHT03_HFPS Fld(12,16)
8119+#define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
8120+#define DHT03_HRBS Fld(12,0)
8121+#define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
8122+
8123+/* DVT01 - Display vertical timing register 01 */
8124+#define DVT01_VBPS Fld(12,16)
8125+#define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
8126+#define DVT01_VT Fld(12,0)
8127+#define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
8128+
8129+/* DVT02 - Display vertical timing register 02 */
8130+#define DVT02_VAS Fld(12,16)
8131+#define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
8132+#define DVT02_VTBS Fld(12,0)
8133+#define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
8134+
8135+/* DVT03 - Display vertical timing register 03 */
8136+#define DVT03_VFPS Fld(12,16)
8137+#define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
8138+#define DVT03_VBBS Fld(12,0)
8139+#define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
8140+
8141+/* DVECTRL - display vertical event control register */
8142+#define DVECTRL_VEVENT Fld(12,16)
8143+#define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
8144+#define DVECTRL_VFETCH Fld(12,0)
8145+#define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
8146+
8147+/* DHDET - display horizontal DE timing register */
8148+#define DHDET_HDES Fld(12,16)
8149+#define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
8150+#define DHDET_HDEF Fld(12,0)
8151+#define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
8152+
8153+/* DVDET - display vertical DE timing register */
8154+#define DVDET_VDES Fld(12,16)
8155+#define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
8156+#define DVDET_VDEF Fld(12,0)
8157+#define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
8158+
8159+/* DODMSK - display output data mask register */
8160+#define DODMSK_MASK_LVL (1 << 31)
8161+#define DODMSK_BLNK_LVL (1 << 30)
8162+#define DODMSK_MASK_B Fld(8,16)
8163+#define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
8164+#define DODMSK_MASK_G Fld(8,8)
8165+#define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
8166+#define DODMSK_MASK_R Fld(8,0)
8167+#define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
8168+
8169+/* DBCOL - display border color control register */
8170+#define DBCOL_BORDCOL Fld(24,0)
8171+#define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
8172+
8173+/* DVLNUM - display vertical line number register */
8174+#define DVLNUM_VLINE Fld(12,0)
8175+#define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
8176+
8177+/* DMCTRL - Display Memory Control Register */
8178+#define DMCTRL_MEM_REF Fld(2,30)
8179+#define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
8180+#define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
8181+#define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
8182+#define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
8183+#define DMCTRL_UV_THRHLD Fld(6,24)
8184+#define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
8185+#define DMCTRL_V_THRHLD Fld(7,16)
8186+#define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
8187+#define DMCTRL_D_THRHLD Fld(7,8)
8188+#define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
8189+#define DMCTRL_BURSTLEN Fld(6,0)
8190+#define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
8191+
8192+
8193+/* DLSTS - display load status register */
8194+#define DLSTS_RLD_ADONE (1 << 23)
8195+/* #define DLSTS_RLD_ADOUT Fld(23,0) */
8196+
8197+/* DLLCTRL - display list load control register */
8198+#define DLLCTRL_RLD_ADRLN Fld(8,24)
8199+#define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
8200+
8201+/* #define DSIG __REG_2700G(0x03FE2184) */
8202+/* #define DINTRS __REG_2700G(0x03FE2178) */
8203+/* #define DINTRE __REG_2700G(0x03FE217C) */
8204+/* #define DINTRCNT __REG_2700G(0x03FE2180) */
8205+/* #define DUCTRL __REG_2700G(0x03FE230C) */
8206+
8207+/* BGCOLOR - background color control register */
8208+/* #define BGCOLOR __REG_2700G(0x03FE2174) */
8209+
8210+/* #define CLIPCTRL __REG_2700G(0x03FE218C) */
8211+/* SPOCTRL - Scale Pitch/Order Control Register */
8212+#define SPOCTRL_H_SC_BP (1 << 31)
8213+#define SPOCTRL_V_SC_BP (1 << 30)
8214+#define SPOCTRL_HV_SC_OR (1 << 29)
8215+#define SPOCTRL_VS_UR_C (1 << 27)
8216+#define SPOCTRL_VORDER Fld(2,16)
8217+#define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
8218+#define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
8219+#define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
8220+#define SPOCTRL_VPITCH Fld(16,0)
8221+#define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
8222+
8223+/* #define SVCTRL __REG_2700G(0x03FE2194) */
8224+
8225+/* /\* 0x03FE_2198 *\/ */
8226+/* /\* 0x03FE_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 *\/ */
8227+
8228+/* #define SHCTRL __REG_2700G(0x03FE21B0) */
8229+
8230+/* /\* 0x03FE_21B4 *\/ */
8231+/* /\* 0x03FE_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 *\/ */
8232+
8233+/* #define SSSIZE __REG_2700G(0x03FE21D8) */
8234+
8235+/* /\* 0x03FE_2200 *\/ */
8236+/* /\* 0x03FE_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 *\/ */
8237+
8238+/* /\* 0x03FE_2250 *\/ */
8239+/* /\* 0x03FE_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 *\/ */
8240+
8241+/* #define CSC01 __REG_2700G(0x03FE2330) */
8242+/* #define CSC02 __REG_2700G(0x03FE2334) */
8243+/* #define CSC03 __REG_2700G(0x03FE2338) */
8244+/* #define CSC04 __REG_2700G(0x03FE233C) */
8245+/* #define CSC05 __REG_2700G(0x03FE2340) */
8246+
8247+#endif /* __REG_BITS_2700G_ */
8248diff --git a/drivers/video/mbx/regs.h b/drivers/video/mbx/regs.h
8249new file mode 100644
8250index 0000000..edf0f14
8251--- /dev/null
8252+++ b/drivers/video/mbx/regs.h
8253@@ -0,0 +1,192 @@
8254+#ifndef __REGS_2700G_
8255+#define __REGS_2700G_
8256+
8257+/* extern unsigned long virt_base_2700; */
8258+#define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700))
8259+
8260+/* System Configuration Registers (0x0000_0000 0x0000_0010) */
8261+#define SYSCFG __REG_2700G(0x00000000)
8262+#define PFBASE __REG_2700G(0x00000004)
8263+#define PFCEIL __REG_2700G(0x00000008)
8264+#define POLLFLAG __REG_2700G(0x0000000c)
8265+#define SYSRST __REG_2700G(0x00000010)
8266+
8267+/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
8268+#define NINTPW __REG_2700G(0x00000014)
8269+#define MINTENABLE __REG_2700G(0x00000018)
8270+#define MINTSTAT __REG_2700G(0x0000001c)
8271+#define SINTENABLE __REG_2700G(0x00000020)
8272+#define SINTSTAT __REG_2700G(0x00000024)
8273+#define SINTCLR __REG_2700G(0x00000028)
8274+
8275+/* Clock Control Registers (0x0000_002C 0x0000_005F) */
8276+#define SYSCLKSRC __REG_2700G(0x0000002c)
8277+#define PIXCLKSRC __REG_2700G(0x00000030)
8278+#define CLKSLEEP __REG_2700G(0x00000034)
8279+#define COREPLL __REG_2700G(0x00000038)
8280+#define DISPPLL __REG_2700G(0x0000003c)
8281+#define PLLSTAT __REG_2700G(0x00000040)
8282+#define VOVRCLK __REG_2700G(0x00000044)
8283+#define PIXCLK __REG_2700G(0x00000048)
8284+#define MEMCLK __REG_2700G(0x0000004c)
8285+#define M24CLK __REG_2700G(0x00000054)
8286+#define MBXCLK __REG_2700G(0x00000054)
8287+#define SDCLK __REG_2700G(0x00000058)
8288+#define PIXCLKDIV __REG_2700G(0x0000005c)
8289+
8290+/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
8291+#define LCD_CONFIG __REG_2700G(0x00000060)
8292+
8293+/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
8294+#define ODFBPWR __REG_2700G(0x00000064)
8295+#define ODFBSTAT __REG_2700G(0x00000068)
8296+
8297+/* GPIO Registers (0x0000_006C 0x0000_007F) */
8298+#define GPIOCGF __REG_2700G(0x0000006c)
8299+#define GPIOHI __REG_2700G(0x00000070)
8300+#define GPIOLO __REG_2700G(0x00000074)
8301+#define GPIOSTAT __REG_2700G(0x00000078)
8302+
8303+/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
8304+#define PWMRST __REG_2700G(0x00000200)
8305+#define PWMCFG __REG_2700G(0x00000204)
8306+#define PWM0DIV __REG_2700G(0x00000210)
8307+#define PWM0DUTY __REG_2700G(0x00000214)
8308+#define PWM0PER __REG_2700G(0x00000218)
8309+#define PWM1DIV __REG_2700G(0x00000220)
8310+#define PWM1DUTY __REG_2700G(0x00000224)
8311+#define PWM1PER __REG_2700G(0x00000228)
8312+
8313+/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
8314+#define ID __REG_2700G(0x00000FF0)
8315+
8316+/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
8317+#define LMRST __REG_2700G(0x00001000)
8318+#define LMCFG __REG_2700G(0x00001004)
8319+#define LMPWR __REG_2700G(0x00001008)
8320+#define LMPWRSTAT __REG_2700G(0x0000100c)
8321+#define LMCEMR __REG_2700G(0x00001010)
8322+#define LMTYPE __REG_2700G(0x00001014)
8323+#define LMTIM __REG_2700G(0x00001018)
8324+#define LMREFRESH __REG_2700G(0x0000101c)
8325+#define LMPROTMIN __REG_2700G(0x00001020)
8326+#define LMPROTMAX __REG_2700G(0x00001024)
8327+#define LMPROTCFG __REG_2700G(0x00001028)
8328+#define LMPROTERR __REG_2700G(0x0000102c)
8329+
8330+/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
8331+#define GSCTRL __REG_2700G(0x00002000)
8332+#define VSCTRL __REG_2700G(0x00002004)
8333+#define GBBASE __REG_2700G(0x00002020)
8334+#define VBBASE __REG_2700G(0x00002024)
8335+#define GDRCTRL __REG_2700G(0x00002040)
8336+#define VCMSK __REG_2700G(0x00002044)
8337+#define GSCADR __REG_2700G(0x00002060)
8338+#define VSCADR __REG_2700G(0x00002064)
8339+#define VUBASE __REG_2700G(0x00002084)
8340+#define VVBASE __REG_2700G(0x000020a4)
8341+#define GSADR __REG_2700G(0x000020c0)
8342+#define VSADR __REG_2700G(0x000020c4)
8343+#define HCCTRL __REG_2700G(0x00002100)
8344+#define HCSIZE __REG_2700G(0x00002110)
8345+#define HCPOS __REG_2700G(0x00002120)
8346+#define HCBADR __REG_2700G(0x00002130)
8347+#define HCCKMSK __REG_2700G(0x00002140)
8348+#define GPLUT __REG_2700G(0x00002150)
8349+#define DSCTRL __REG_2700G(0x00002154)
8350+#define DHT01 __REG_2700G(0x00002158)
8351+#define DHT02 __REG_2700G(0x0000215c)
8352+#define DHT03 __REG_2700G(0x00002160)
8353+#define DVT01 __REG_2700G(0x00002164)
8354+#define DVT02 __REG_2700G(0x00002168)
8355+#define DVT03 __REG_2700G(0x0000216c)
8356+#define DBCOL __REG_2700G(0x00002170)
8357+#define BGCOLOR __REG_2700G(0x00002174)
8358+#define DINTRS __REG_2700G(0x00002178)
8359+#define DINTRE __REG_2700G(0x0000217c)
8360+#define DINTRCNT __REG_2700G(0x00002180)
8361+#define DSIG __REG_2700G(0x00002184)
8362+#define DMCTRL __REG_2700G(0x00002188)
8363+#define CLIPCTRL __REG_2700G(0x0000218c)
8364+#define SPOCTRL __REG_2700G(0x00002190)
8365+#define SVCTRL __REG_2700G(0x00002194)
8366+
8367+/* 0x0000_2198 */
8368+/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
8369+#define VSCOEFF0 __REG_2700G(0x00002198)
8370+#define VSCOEFF1 __REG_2700G(0x0000219c)
8371+#define VSCOEFF2 __REG_2700G(0x000021a0)
8372+#define VSCOEFF3 __REG_2700G(0x000021a4)
8373+#define VSCOEFF4 __REG_2700G(0x000021a8)
8374+
8375+#define SHCTRL __REG_2700G(0x000021b0)
8376+
8377+/* 0x0000_21B4 */
8378+/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
8379+#define HSCOEFF0 __REG_2700G(0x000021b4)
8380+#define HSCOEFF1 __REG_2700G(0x000021b8)
8381+#define HSCOEFF2 __REG_2700G(0x000021bc)
8382+#define HSCOEFF3 __REG_2700G(0x000021b0)
8383+#define HSCOEFF4 __REG_2700G(0x000021c4)
8384+#define HSCOEFF5 __REG_2700G(0x000021c8)
8385+#define HSCOEFF6 __REG_2700G(0x000021cc)
8386+#define HSCOEFF7 __REG_2700G(0x000021d0)
8387+#define HSCOEFF8 __REG_2700G(0x000021d4)
8388+
8389+#define SSSIZE __REG_2700G(0x000021D8)
8390+
8391+/* 0x0000_2200 */
8392+/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
8393+#define VIDGAM0 __REG_2700G(0x00002200)
8394+#define VIDGAM1 __REG_2700G(0x00002204)
8395+#define VIDGAM2 __REG_2700G(0x00002208)
8396+#define VIDGAM3 __REG_2700G(0x0000220c)
8397+#define VIDGAM4 __REG_2700G(0x00002210)
8398+#define VIDGAM5 __REG_2700G(0x00002214)
8399+#define VIDGAM6 __REG_2700G(0x00002218)
8400+#define VIDGAM7 __REG_2700G(0x0000221c)
8401+#define VIDGAM8 __REG_2700G(0x00002220)
8402+#define VIDGAM9 __REG_2700G(0x00002224)
8403+#define VIDGAM10 __REG_2700G(0x00002228)
8404+#define VIDGAM11 __REG_2700G(0x0000222c)
8405+#define VIDGAM12 __REG_2700G(0x00002230)
8406+#define VIDGAM13 __REG_2700G(0x00002234)
8407+#define VIDGAM14 __REG_2700G(0x00002238)
8408+#define VIDGAM15 __REG_2700G(0x0000223c)
8409+#define VIDGAM16 __REG_2700G(0x00002240)
8410+
8411+/* 0x0000_2250 */
8412+/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
8413+#define GFXGAM0 __REG_2700G(0x00002250)
8414+#define GFXGAM1 __REG_2700G(0x00002254)
8415+#define GFXGAM2 __REG_2700G(0x00002258)
8416+#define GFXGAM3 __REG_2700G(0x0000225c)
8417+#define GFXGAM4 __REG_2700G(0x00002260)
8418+#define GFXGAM5 __REG_2700G(0x00002264)
8419+#define GFXGAM6 __REG_2700G(0x00002268)
8420+#define GFXGAM7 __REG_2700G(0x0000226c)
8421+#define GFXGAM8 __REG_2700G(0x00002270)
8422+#define GFXGAM9 __REG_2700G(0x00002274)
8423+#define GFXGAM10 __REG_2700G(0x00002278)
8424+#define GFXGAM11 __REG_2700G(0x0000227c)
8425+#define GFXGAM12 __REG_2700G(0x00002280)
8426+#define GFXGAM13 __REG_2700G(0x00002284)
8427+#define GFXGAM14 __REG_2700G(0x00002288)
8428+#define GFXGAM15 __REG_2700G(0x0000228c)
8429+#define GFXGAM16 __REG_2700G(0x00002290)
8430+
8431+#define DLSTS __REG_2700G(0x00002300)
8432+#define DLLCTRL __REG_2700G(0x00002304)
8433+#define DVLNUM __REG_2700G(0x00002308)
8434+#define DUCTRL __REG_2700G(0x0000230c)
8435+#define DVECTRL __REG_2700G(0x00002310)
8436+#define DHDET __REG_2700G(0x00002314)
8437+#define DVDET __REG_2700G(0x00002318)
8438+#define DODMSK __REG_2700G(0x0000231c)
8439+#define CSC01 __REG_2700G(0x00002330)
8440+#define CSC02 __REG_2700G(0x00002334)
8441+#define CSC03 __REG_2700G(0x00002338)
8442+#define CSC04 __REG_2700G(0x0000233c)
8443+#define CSC05 __REG_2700G(0x00002340)
8444+
8445+#endif /* __REGS_2700G_ */
8446diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
8447index 53ad61f..76675f6 100644
8448--- a/drivers/video/pxafb.c
8449+++ b/drivers/video/pxafb.c
8450@@ -48,6 +48,11 @@ #include <asm/arch/pxa-regs.h>
8451 #include <asm/arch/bitfield.h>
8452 #include <asm/arch/pxafb.h>
8453
8454+#ifdef CONFIG_PXA27x
8455+#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 3 */
8456+#endif
8457+
8458+
8459 /*
8460 * Complain if VAR is out of range.
8461 */
8462@@ -113,9 +118,15 @@ pxafb_setpalettereg(u_int regno, u_int r
8463 if (fbi->fb.var.grayscale) {
8464 val = ((blue >> 8) & 0x00ff);
8465 } else {
8466+#ifdef CONFIG_ARMCORE_REV11
8467+ val = (((red & 0xff) << 16) & 0xfc0000);
8468+ val |= (((green & 0xff) << 8) & 0xfc00);
8469+ val |= (((blue & 0xff) << 0) & 0x00fc);
8470+#else
8471 val = ((red >> 0) & 0xf800);
8472 val |= ((green >> 5) & 0x07e0);
8473 val |= ((blue >> 11) & 0x001f);
8474+#endif
8475 }
8476 fbi->palette_cpu[regno] = val;
8477 ret = 0;
8478@@ -426,6 +437,8 @@ static struct fb_ops pxafb_ops = {
8479 * We take account of the PPCR clock setting.
8480 * From PXA Developer's Manual:
8481 *
8482+ * If PCDDIV = 0 then:
8483+ *
8484 * PixelClock = LCLK
8485 * -------------
8486 * 2 ( PCD + 1 )
8487@@ -434,6 +447,17 @@ static struct fb_ops pxafb_ops = {
8488 * ------------- - 1
8489 * 2(PixelClock)
8490 *
8491+ *
8492+ * If PCDDIV = 1 then:
8493+ *
8494+ * PixelClock = LCLK
8495+ * -------------
8496+ * ( PCD + 1 )
8497+ *
8498+ * PCD = LCLK
8499+ * ------------- - 1
8500+ * PixelClock
8501+ *
8502 * Where:
8503 * LCLK = LCD/Memory Clock
8504 * PCD = LCCR3[7:0]
8505@@ -448,22 +472,64 @@ static struct fb_ops pxafb_ops = {
8506 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
8507 * -------------------------------------- - 1
8508 * 2
8509+ * or
8510+ * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) - 1
8511 *
8512 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
8513 */
8514-static inline unsigned int get_pcd(unsigned int pixclock)
8515+static inline unsigned int get_pcd(unsigned int pixclock, unsigned int *lccr4)
8516 {
8517- unsigned long long pcd;
8518+ /* pcd1 is for PCDDIV=0 and pcd2 for PCDDIV=1 */
8519+ unsigned long long pcd1, pcd2;
8520+ unsigned long long clk1, clk2;
8521+ unsigned long long dif1, dif2;
8522+
8523+ *lccr4 = LCCR4;
8524
8525 /* FIXME: Need to take into account Double Pixel Clock mode
8526 * (DPC) bit? or perhaps set it based on the various clock
8527 * speeds */
8528
8529- pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
8530- do_div(pcd, 100000000 * 2);
8531+ pcd1 = pcd2 = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
8532+ do_div(pcd1, 100000000 * 2); /* pcd1 /= 100000000 * 2; */
8533+ do_div(pcd2, 100000000); /* pcd2 /= 100000000; */
8534+
8535+/* clk1 = 100000000*(2 * (pcd1 + 1))/get_lcdclk_frequency_10khz(); */
8536+/* clk2 = 100000000*(pcd2 + 1)/get_lcdclk_frequency_10khz(); */
8537+
8538+ clk1 = 100000000*(2 * (pcd1 + 1));
8539+ clk2 = 100000000*(pcd2 + 1);
8540+ do_div(clk1, get_lcdclk_frequency_10khz());
8541+ do_div(clk2, get_lcdclk_frequency_10khz());
8542+
8543+ pr_debug("get_pcd: pcd1 = %lld, dotclock = %lld\n", pcd1, clk1);
8544+ pr_debug("get_pcd: pcd2 = %lld, dotclock = %lld\n", pcd2, clk2);
8545+
8546+ dif1 = pixclock - clk1;
8547+ if ( clk1 > pixclock )
8548+ dif1 *= -1;
8549+
8550+ dif2 = pixclock - clk2;
8551+ if ( clk2 > pixclock )
8552+ dif2 *= -1;
8553+
8554+ if ( dif1 > dif2 ) {
8555+ *lccr4 |= (1 << 31);
8556+ pr_debug(KERN_INFO "get_pcd: setting pixclock to high rate\n");
8557+ return (unsigned int)pcd2;
8558+ }
8559+ else {
8560+ *lccr4 &= ~(1 << 31);
8561+ pr_debug(KERN_INFO "get_pcd: setting pixclock to low rate\n");
8562+ return (unsigned int)pcd1;
8563+ }
8564+
8565 /* no need for this, since we should subtract 1 anyway. they cancel */
8566 /* pcd += 1; */ /* make up for integer math truncations */
8567- return (unsigned int)pcd;
8568+/* return (unsigned int)pcd2; */
8569+
8570+ /* never get here */
8571+ return (unsigned int)0;
8572 }
8573
8574 /*
8575@@ -505,7 +571,9 @@ static int pxafb_activate_var(struct fb_
8576 {
8577 struct pxafb_lcd_reg new_regs;
8578 u_long flags;
8579- u_int lines_per_panel, pcd = get_pcd(var->pixclock);
8580+ u_int lines_per_panel;
8581+ u_int lccr4;
8582+ u_int pcd = get_pcd(var->pixclock, &lccr4);
8583
8584 pr_debug("pxafb: Configuring PXA LCD\n");
8585
8586@@ -735,10 +803,18 @@ static void pxafb_setup_gpio(struct pxaf
8587 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
8588 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
8589 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
8590+
8591+#ifdef CONFIG_ARMCORE_REV11
8592+ pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
8593+ pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
8594+#endif
8595 }
8596
8597 static void pxafb_enable_controller(struct pxafb_info *fbi)
8598 {
8599+ unsigned int lccr4;
8600+ unsigned int pcd = get_pcd(fbi->fb.var.pixclock, &lccr4);
8601+
8602 pr_debug("pxafb: Enabling LCD controller\n");
8603 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
8604 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
8605@@ -751,7 +827,20 @@ static void pxafb_enable_controller(stru
8606 pxa_set_cken(CKEN16_LCD, 1);
8607
8608 /* Sequence from 11.7.10 */
8609- LCCR3 = fbi->reg_lccr3;
8610+#ifdef CONFIG_ARMCORE_REV12
8611+ LCCR4 = lccr4;
8612+#else
8613+ LCCR4 = 0 | (2 << 15) | lccr4;
8614+#endif
8615+
8616+ fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
8617+
8618+#ifdef CONFIG_ARMCORE_REV12
8619+ LCCR3 = (fbi->reg_lccr3);//& (~(7 << 24))) | (3 << 24);
8620+#else
8621+ LCCR3 = (fbi->reg_lccr3 | (3 << 30)) ;//& (~(7 << 24))) | (3 << 24);
8622+#endif
8623+
8624 LCCR2 = fbi->reg_lccr2;
8625 LCCR1 = fbi->reg_lccr1;
8626 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
8627@@ -1083,6 +1172,7 @@ static struct pxafb_info * __init pxafb_
8628 addr = addr + sizeof(struct pxafb_info);
8629 fbi->fb.pseudo_palette = addr;
8630
8631+ fbi->fb.var.pixclock = inf->pixclock;
8632 fbi->max_xres = inf->xres;
8633 fbi->fb.var.xres = inf->xres;
8634 fbi->fb.var.xres_virtual = inf->xres;
8635diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
8636new file mode 100644
8637index 0000000..f2d3675
8638--- /dev/null
8639+++ b/include/asm-arm/arch-pxa/cm-x270.h
8640@@ -0,0 +1,169 @@
8641+/*
8642+ * linux/include/asm/arch-pxa/armcore.h
8643+ *
8644+ * Compulab Ltd., 2003
8645+ *
8646+ * ARMCore registers
8647+ */
8648+
8649+#include <linux/config.h>
8650+
8651+#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
8652+#define MARATHON_PHYS (PXA_CS2_PHYS)
8653+#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
8654+#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
8655+
8656+#define PXA_CS_SIZE (64*1024*1024)
8657+
8658+/* Virtual map */
8659+
8660+#define CMX270_VIRT_BASE (0xe8000000)
8661+/* #define MARATHON_VIRT (CMX270_VIRT_BASE) */
8662+
8663+#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
8664+
8665+#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + PXA_CS_SIZE)
8666+#ifdef CONFIG_CMX270_SB270
8667+#define CMX270_IDECS0_VIRT (CMX270_IDE104_VIRT + (1<<24) + (1<<25))
8668+#define CMX270_IDECS1_VIRT (CMX270_IDE104_VIRT + (1<<25))
8669+#else
8670+#define CMX270_IDECS0_VIRT (CMX270_IDE104_VIRT + (1<<25))
8671+#define CMX270_IDECS1_VIRT (CMX270_IDE104_VIRT + (1<<25) + (1<<22))
8672+#endif
8673+
8674+/* #define CMX270_RTC_VIRT (CMX270_CS1_VIRT + (5<<22)) */
8675+
8676+
8677+/* GPIO related definitions */
8678+#define GPIO_IT8152_IRQ (22)
8679+#define GPIO_RED_LED (93)
8680+#define GPIO_GREEN_LED (94)
8681+
8682+
8683+#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
8684+#define PME_IRQ IRQ_GPIO(0)
8685+#define CMX270_IDE_IRQ IRQ_GPIO(100)
8686+#define CMX270_GPIRQ1 IRQ_GPIO(101)
8687+#define CMX270_TOUCHIRQ IRQ_GPIO(96)
8688+#define CMX270_ETHIRQ IRQ_GPIO(10)
8689+#define CMX270_GFXIRQ IRQ_GPIO(95)
8690+#define CMX270_NANDIRQ IRQ_GPIO(89)
8691+#define ARMCORE_MMC_IRQ IRQ_GPIO(83)
8692+
8693+/* LED macros */
8694+#define CMX270_RED_ON() GPCR(GPIO_RED_LED) = GPIO_bit(GPIO_RED_LED)
8695+#define CMX270_RED_OFF() GPSR(GPIO_RED_LED) = GPIO_bit(GPIO_RED_LED)
8696+#define CMX270_GREEN_ON() GPCR(GPIO_GREEN_LED) = GPIO_bit(GPIO_GREEN_LED)
8697+#define CMX270_GREEN_OFF() GPSR(GPIO_GREEN_LED) = GPIO_bit(GPIO_GREEN_LED)
8698+
8699+/* PCMCIA related definitions */
8700+#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
8701+#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(81 - (x)))
8702+
8703+#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
8704+#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
8705+
8706+#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
8707+#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
8708+
8709+#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
8710+#define PCMCIA_S1_RDYINT IRQ_GPIO(81)
8711+
8712+#define PCMCIA_RESET_GPIO 53
8713+
8714+
8715+/* #define IT8152_IO_BASE (CMX270_IT8152_VIRT + 0x03e00000) */
8716+/* #define IT8152_CFGREG_BASE (CMX270_IT8152_VIRT + 0x03f00000) */
8717+/* #define CMX270_CS1_VIRT (CMX270_IT8152_VIRT + PXA_CS_SIZE) */
8718+/* #define IT8152_SHORT_IO(x) (*((volatile unsigned short *)(IT8152_CFGREG_BASE+(x)))) */
8719+/* #define IT8152_LONG_IO(x) (*((volatile unsigned long *)(IT8152_CFGREG_BASE+(x)))) */
8720+
8721+
8722+/* /\* PCI related definitions *\/ */
8723+
8724+/* /\* #define PCIBIOS_MIN_IO (IT8152_IO_BASE + 0x12000) *\/ */
8725+/* /\* #define PCIBIOS_MIN_MEM (0x10000000) *\/ */
8726+
8727+
8728+/* #define IT8152_PCI_IACK (*((volatile unsigned long *)(CMX270_IT8152_VIRT + 0x3f00808))) */
8729+/* #define IT8152_PCI_CFG_ADDR (*((volatile unsigned long *)(CMX270_IT8152_VIRT + 0x3f00800))) */
8730+/* #define IT8152_PCI_CFG_DATA (*((volatile unsigned long *)(CMX270_IT8152_VIRT + 0x3f00804))) */
8731+/* #define IT8152_PCI_MEMBASE (*((volatile unsigned long *)(CMX270_IT8152_VIRT))) */
8732+/* #define IT8152_PCI_IOBASE (*((volatile unsigned long *)(CMX270_IT8152_VIRT + 0x3e00000))) */
8733+
8734+/* #define IT_BUSNUM_SHF 16 */
8735+/* #define IT_DEVNUM_SHF 11 */
8736+/* #define IT_FUNCNUM_SHF 8 */
8737+/* #define IT_REGNUM_SHF 2 */
8738+
8739+
8740+/* /\* Power management & PLL registers *\/ */
8741+/* #define IT8152_PMPLL_DSR IT8152_LONG_IO(0x00) */
8742+/* #define IT8152_PMPLL_DSSR IT8152_LONG_IO(0x04) */
8743+/* #define IT8152_PMPLL_PLLCR IT8152_LONG_IO(0x20) */
8744+/* #define IT8152_PMPLL_MFSR IT8152_LONG_IO(0x24) */
8745+
8746+
8747+/* /\* Memory controller *\/ */
8748+/* #define IT8152_MC_REG_OFFSET 0x100 */
8749+
8750+/* #define IT8152_MC_SDCR IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x00) */
8751+/* #define IT8152_MC_PCICR IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x04) */
8752+
8753+/* /\* Interrupt related definitions *\/ */
8754+/* #define IT8152_INTC_REG_OFFSET 0x300 */
8755+
8756+/* #define IT8152_INTC_LDCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x00) */
8757+/* #define IT8152_INTC_LDPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x04) */
8758+/* #define IT8152_INTC_LDCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x08) */
8759+/* #define IT8152_INTC_LDPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x0C) */
8760+/* #define IT8152_INTC_LDNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x10) */
8761+/* #define IT8152_INTC_LDNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x14) */
8762+/* #define IT8152_INTC_LPCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x20) */
8763+/* #define IT8152_INTC_LPPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x24) */
8764+/* #define IT8152_INTC_LPCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x28) */
8765+/* #define IT8152_INTC_LPPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x2C) */
8766+/* #define IT8152_INTC_LPNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x30) */
8767+/* #define IT8152_INTC_LPNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x34) */
8768+/* #define IT8152_INTC_PDCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x40) */
8769+/* #define IT8152_INTC_PDPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x44) */
8770+/* #define IT8152_INTC_PDCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x48) */
8771+/* #define IT8152_INTC_PDPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x4C) */
8772+/* #define IT8152_INTC_PDNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x50) */
8773+/* #define IT8152_INTC_PDNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x54) */
8774+/* #define IT8152_INTC_INTC_TYPER IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0xFC) */
8775+
8776+/* #define IT8152_UART_BASE IT8152_LONG_IO(0x200) */
8777+
8778+/* #define IT8152_GPIO_REG_OFFSET 0x500 */
8779+
8780+/* #define IT8152_GPIO_GPLR IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET) */
8781+/* #define IT8152_GPIO_GPCR12 IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x04) */
8782+/* #define IT8152_GPIO_GPCR34 IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x08) */
8783+
8784+
8785+/* /\* Interrupt bit definitions *\/ */
8786+/* #define PCISERR_BIT (1<<14) */
8787+/* #define H2PTADR_BIT (1<<13) */
8788+/* #define H2PMAR_BIT (1<<12) */
8789+/* #define PCI_INTD_BIT (1<<11) */
8790+/* #define PCI_INTC_BIT (1<<10) */
8791+/* #define PCI_INTB_BIT (1<<9) */
8792+/* #define PCI_INTA_BIT (1<<8) */
8793+/* #define CDMA_INT_BIT (1<<2) */
8794+/* #define USB_INT_BIT (1<<1) */
8795+/* #define AUDIO_INT_BIT (1<<0) */
8796+
8797+/* // IT8152 UART */
8798+/* #define ITESER_BIT (1<<5) */
8799+
8800+
8801+
8802+
8803+
8804+
8805+
8806+
8807+
8808+
8809+
8810diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
8811index 3e70bd9..cb4fb2f 100644
8812--- a/include/asm-arm/arch-pxa/hardware.h
8813+++ b/include/asm-arm/arch-pxa/hardware.h
8814@@ -80,4 +80,15 @@ extern unsigned int get_lcdclk_frequency
8815
8816 #endif
8817
8818+#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
8819+#define HAVE_ARCH_PCI_SET_DMA_MASK
8820+#ifndef __ASSEMBLY__
8821+extern unsigned long armcore_pcibios_min_io;
8822+extern unsigned long armcore_pcibios_min_mem;
8823+#endif
8824+#define PCIBIOS_MIN_IO (armcore_pcibios_min_io)
8825+#define PCIBIOS_MIN_MEM (armcore_pcibios_min_mem)
8826+#define pcibios_assign_all_busses() 1
8827+#endif
8828+
8829 #endif /* _ASM_ARCH_HARDWARE_H */
8830diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
8831index 05c4b70..f0259cd 100644
8832--- a/include/asm-arm/arch-pxa/irqs.h
8833+++ b/include/asm-arm/arch-pxa/irqs.h
8834@@ -176,7 +176,8 @@ #define NR_IRQS (IRQ_S1_BVD1_STSCHG +
8835 #elif defined(CONFIG_SHARP_LOCOMO)
8836 #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
8837 #elif defined(CONFIG_ARCH_LUBBOCK) || \
8838- defined(CONFIG_MACH_MAINSTONE)
8839+ defined(CONFIG_MACH_MAINSTONE) || \
8840+ defined(CONFIG_MACH_ARMCORE)
8841 #define NR_IRQS (IRQ_BOARD_END)
8842 #else
8843 #define NR_IRQS (IRQ_BOARD_START)
8844@@ -217,3 +218,24 @@ #define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_S
8845 #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
8846 #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
8847 #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
8848+
8849+/* ITE8152 irqs on CM-x2xx */
8850+#ifdef CONFIG_MACH_ARMCORE
8851+#define IT8152_IRQ(x) (IRQ_BOARD_START + (x))
8852+#define PCISERR IT8152_IRQ(0)
8853+#define H2PTADR IT8152_IRQ(1)
8854+#define H2PMAR IT8152_IRQ(2)
8855+#define PCI_INTA IT8152_IRQ(3)
8856+#define PCI_INTB IT8152_IRQ(4)
8857+#define PCI_INTC IT8152_IRQ(5)
8858+#define PCI_INTD IT8152_IRQ(6)
8859+#define USB_INT IT8152_IRQ(7)
8860+#define AUDIO_INT IT8152_IRQ(8)
8861+#define CDMA_INT IT8152_IRQ(9)
8862+#define IRQ_ITESER IT8152_IRQ(10)
8863+#define IT8152_IRQ_MAX IT8152_IRQ(10)
8864+
8865+
8866+#undef NR_IRQS
8867+#define NR_IRQS IT8152_IRQ_MAX+1
8868+#endif
8869diff --git a/include/asm-arm/arch-pxa/marathonfb.h b/include/asm-arm/arch-pxa/marathonfb.h
8870new file mode 100644
8871index 0000000..97b69ef
8872--- /dev/null
8873+++ b/include/asm-arm/arch-pxa/marathonfb.h
8874@@ -0,0 +1,28 @@
8875+#ifndef __MARATHON_FB_H
8876+#define __MARATHON_FB_H
8877+
8878+struct mbxfb_val {
8879+ unsigned int defval;
8880+ unsigned int min;
8881+ unsigned int max;
8882+};
8883+
8884+struct fb_info;
8885+
8886+struct mbxfb_platform_data {
8887+ /* Screen info */
8888+ struct mbxfb_val xres;
8889+ struct mbxfb_val yres;
8890+ struct mbxfb_val bpp;
8891+
8892+ /* Memory info */
8893+ unsigned long memsize; /* if 0 use ODFB? */
8894+ unsigned long timings1;
8895+ unsigned long timings2;
8896+ unsigned long timings3;
8897+
8898+ int (*probe)(struct fb_info *fb);
8899+ int (*remove)(struct fb_info *fb);
8900+};
8901+
8902+#endif /* __MARATHON_FB_H */
8903diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
8904index eaf6d43..98807e7 100644
8905--- a/include/asm-arm/arch-pxa/memory.h
8906+++ b/include/asm-arm/arch-pxa/memory.h
8907@@ -17,6 +17,19 @@ #define __ASM_ARCH_MEMORY_H
8908 */
8909 #define PHYS_OFFSET UL(0xa0000000)
8910
8911+
8912+#ifdef CONFIG_PCI_HOST_ITE8152
8913+#ifndef __ASSEMBLY__
8914+void it8152_adjust_zones(int node, unsigned long *size, unsigned long *holes);
8915+
8916+#define arch_adjust_zones(node, size, holes) \
8917+ it8152_adjust_zones(node, size, holes)
8918+
8919+#define ISA_DMA_THRESHOLD (SZ_64M - 1)
8920+#endif
8921+#endif
8922+
8923+
8924 /*
8925 * Virtual view <-> DMA view memory address translations
8926 * virt_to_bus: Used to translate the virtual address to an
8927diff --git a/include/asm-arm/arch-pxa/pxafbsetup.h b/include/asm-arm/arch-pxa/pxafbsetup.h
8928new file mode 100644
8929index 0000000..8a7c8de
8930--- /dev/null
8931+++ b/include/asm-arm/arch-pxa/pxafbsetup.h
8932@@ -0,0 +1,39 @@
8933+/*
8934+ Panel specific LCD controller setup
8935+ */
8936+
8937+#ifndef _PXAFBSETUP_H
8938+#define _PXAFBSETUP_H
8939+
8940+#define MTYPE_STN320x240 0
8941+#define MTYPE_TFT640x480 1
8942+#define MTYPE_CRT640x480 2
8943+#define MTYPE_CRT800x600 3
8944+#define MTYPE_CRT1024x768 4
8945+#define MTYPE_USER_DEFINED 5
8946+#define MTYPE_TFT320x240 6
8947+#define MTYPE_STN640x480 7
8948+
8949+#define CMAP_GREYSCALE 0
8950+#define CMAP_INVERSE 0
8951+#define CMAP_STATIC 0
8952+
8953+
8954+// Example for user defined display
8955+// Hitach SX19V-009
8956+#define LCD_PIXCLOCK 38461
8957+#define LCD_BPP 8
8958+#define LCD_XRES 640
8959+#define LCD_YRES 480
8960+#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH 4
8961+#define LCD_VERTICAL_SYNC_PULSE_WIDTH 2
8962+#define LCD_BEGIN_OF_LINE_WAIT_COUNT 10
8963+#define LCD_BEGIN_FRAME_WAIT_COUNT 5
8964+#define LCD_END_OF_LINE_WAIT_COUNT 10
8965+#define LCD_END_OF_FRAME_WAIT_COUNT 5
8966+#define LCD_SYNC (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT)
8967+#define LCD_LCCR0 (LCCR0_LDM | LCCR0_IUM | LCCR0_QDM | LCCR0_BM | LCCR0_OUM )
8968+#define LCD_LCCR3 (LCCR3_PixClkDiv(0x02) | LCCR3_Acb(0xff))
8969+#define LCD_NAME "Hitachi SX19V-009-ZZA-1"
8970+
8971+#endif
8972diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h
8973new file mode 100644
8974index 0000000..d28210d
8975--- /dev/null
8976+++ b/include/asm-arm/hardware/it8152.h
8977@@ -0,0 +1,104 @@
8978+/*
8979+ * arch/arm/mach-pxa/it8152.h
8980+ *
8981+ * Compulab Ltd., 2006
8982+ *
8983+ * ITE 8152 companion chip definitions
8984+ */
8985+
8986+
8987+/* #define CMX270_IT8152_VIRT (CMX270_VIRT_BASE) */
8988+
8989+
8990+extern unsigned long it8152_base_address;
8991+
8992+#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
8993+#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
8994+
8995+/* #define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ) */
8996+
8997+#define IT8152_SHORT_IO(x) (*((volatile unsigned short *)(IT8152_CFGREG_BASE+(x))))
8998+#define IT8152_LONG_IO(x) (*((volatile unsigned long *)(IT8152_CFGREG_BASE+(x))))
8999+
9000+
9001+#define IT8152_PCI_MEMBASE (*((volatile unsigned long *)(it8152_base_address)))
9002+/* #define IT8152_PCI_IOBASE (*((volatile unsigned long *)(it8152_base_address + 0x3e00000))) */
9003+
9004+#define IT8152_PCI_IACK (*((volatile unsigned long *)(it8152_base_address + 0x3f00808)))
9005+#define IT8152_PCI_CFG_ADDR (*((volatile unsigned long *)(it8152_base_address + 0x3f00800)))
9006+#define IT8152_PCI_CFG_DATA (*((volatile unsigned long *)(it8152_base_address + 0x3f00804)))
9007+
9008+#define IT_BUSNUM_SHF 16
9009+#define IT_DEVNUM_SHF 11
9010+#define IT_FUNCNUM_SHF 8
9011+#define IT_REGNUM_SHF 2
9012+
9013+/* Power management & PLL registers */
9014+#define IT8152_PMPLL_DSR IT8152_LONG_IO(0x00)
9015+#define IT8152_PMPLL_DSSR IT8152_LONG_IO(0x04)
9016+#define IT8152_PMPLL_PLLCR IT8152_LONG_IO(0x20)
9017+#define IT8152_PMPLL_MFSR IT8152_LONG_IO(0x24)
9018+
9019+/* Memory controller */
9020+#define IT8152_MC_REG_OFFSET 0x100
9021+
9022+#define IT8152_MC_SDCR IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x00)
9023+#define IT8152_MC_PCICR IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x04)
9024+
9025+/* Interrupt related definitions */
9026+#define IT8152_INTC_REG_OFFSET 0x300
9027+
9028+#define IT8152_INTC_LDCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x00)
9029+#define IT8152_INTC_LDPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x04)
9030+#define IT8152_INTC_LDCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x08)
9031+#define IT8152_INTC_LDPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x0C)
9032+#define IT8152_INTC_LDNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x10)
9033+#define IT8152_INTC_LDNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x14)
9034+#define IT8152_INTC_LPCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x20)
9035+#define IT8152_INTC_LPPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x24)
9036+#define IT8152_INTC_LPCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x28)
9037+#define IT8152_INTC_LPPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x2C)
9038+#define IT8152_INTC_LPNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x30)
9039+#define IT8152_INTC_LPNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x34)
9040+#define IT8152_INTC_PDCNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x40)
9041+#define IT8152_INTC_PDPNIRR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x44)
9042+#define IT8152_INTC_PDCNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x48)
9043+#define IT8152_INTC_PDPNIMR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x4C)
9044+#define IT8152_INTC_PDNITR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x50)
9045+#define IT8152_INTC_PDNIAR IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x54)
9046+#define IT8152_INTC_INTC_TYPER IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0xFC)
9047+
9048+#define IT8152_UART_BASE IT8152_LONG_IO(0x200)
9049+
9050+#define IT8152_GPIO_REG_OFFSET 0x500
9051+
9052+#define IT8152_GPIO_GPLR IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET)
9053+#define IT8152_GPIO_GPCR12 IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x04)
9054+#define IT8152_GPIO_GPCR34 IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x08)
9055+
9056+
9057+/* Interrupt bit definitions */
9058+#define PCISERR_BIT (1<<14)
9059+#define H2PTADR_BIT (1<<13)
9060+#define H2PMAR_BIT (1<<12)
9061+#define PCI_INTD_BIT (1<<11)
9062+#define PCI_INTC_BIT (1<<10)
9063+#define PCI_INTB_BIT (1<<9)
9064+#define PCI_INTA_BIT (1<<8)
9065+#define CDMA_INT_BIT (1<<2)
9066+#define USB_INT_BIT (1<<1)
9067+#define AUDIO_INT_BIT (1<<0)
9068+
9069+/* IT8152 UART */
9070+#define ITESER_BIT (1<<5)
9071+
9072+
9073+
9074+
9075+
9076+
9077+
9078+
9079+
9080+
9081+
9082diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
9083index 751eea5..bc45d11 100644
9084--- a/include/linux/pci_ids.h
9085+++ b/include/linux/pci_ids.h
9086@@ -1568,6 +1568,7 @@ #define PCI_DEVICE_ID_EFFICEON 0x0060
9087 #define PCI_VENDOR_ID_ROCKWELL 0x127A
9088
9089 #define PCI_VENDOR_ID_ITE 0x1283
9090+#define PCI_DEVICE_ID_ITE_IT8152 0x8152
9091 #define PCI_DEVICE_ID_ITE_IT8172G 0x8172
9092 #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
9093 #define PCI_DEVICE_ID_ITE_8211 0x8211
9094diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c
9095index 3020ca2..ba1dc8a 100644
9096--- a/sound/pci/ac97/ac97_codec.c
9097+++ b/sound/pci/ac97/ac97_codec.c
9098@@ -150,7 +150,7 @@ static const struct ac97_codec_id snd_ac
9099 { 0x4e534300, 0xffffffff, "LM4540,43,45,46,48", NULL, NULL }, // only guess --jk
9100 { 0x4e534331, 0xffffffff, "LM4549", NULL, NULL },
9101 { 0x4e534350, 0xffffffff, "LM4550", NULL, NULL },
9102-{ 0x50534304, 0xffffffff, "UCB1400", NULL, NULL },
9103+{ 0x50534304, 0xffffffff, "UCB1400", patch_ucb1400, NULL },
9104 { 0x53494c20, 0xffffffe0, "Si3036,8", mpatch_si3036, mpatch_si3036, AC97_MODEM_PATCH },
9105 { 0x54524102, 0xffffffff, "TR28022", NULL, NULL },
9106 { 0x54524106, 0xffffffff, "TR28026", NULL, NULL },
9107diff --git a/sound/pci/ac97/ac97_patch.c b/sound/pci/ac97/ac97_patch.c
9108index a444a78..0bb1d71 100644
9109--- a/sound/pci/ac97/ac97_patch.c
9110+++ b/sound/pci/ac97/ac97_patch.c
9111@@ -2823,3 +2823,33 @@ int mpatch_si3036(struct snd_ac97 * ac97
9112 snd_ac97_write_cache(ac97, 0x68, 0);
9113 return 0;
9114 }
9115+
9116+/*
9117+ * UCB1400 codec
9118+ */
9119+static const struct snd_kcontrol_new snd_ac97_controls_ucb1400[] = {
9120+AC97_SINGLE("Headphone driver", 0x6a, 6, 1, 0),
9121+AC97_SINGLE("DC filter", 0x6a, 4, 1, 0),
9122+AC97_SINGLE("Smart power mode", 0x6c, 4, 3, 0),
9123+};
9124+
9125+static int patch_ucb1400_specific(struct snd_ac97 * ac97)
9126+{
9127+ int idx, err;
9128+ for (idx = 0; idx < ARRAY_SIZE(snd_ac97_controls_ucb1400); idx++)
9129+ if ((err = snd_ctl_add(ac97->bus->card, snd_ctl_new1(&snd_ac97_controls_ucb1400[idx], ac97))) < 0)
9130+ return err;
9131+ return 0;
9132+}
9133+
9134+static struct snd_ac97_build_ops patch_ucb1400_ops = {
9135+ .build_specific = patch_ucb1400_specific,
9136+};
9137+
9138+int patch_ucb1400(struct snd_ac97 * ac97)
9139+{
9140+ ac97->build_ops = &patch_ucb1400_ops;
9141+ snd_ac97_write(ac97, 0x6a, 0x0050);
9142+ snd_ac97_write(ac97, 0x6c, 0x0030);
9143+ return 0;
9144+}
9145diff --git a/sound/pci/ac97/ac97_patch.h b/sound/pci/ac97/ac97_patch.h
9146index 5060cb6..068b674 100644
9147--- a/sound/pci/ac97/ac97_patch.h
9148+++ b/sound/pci/ac97/ac97_patch.h
9149@@ -58,4 +58,5 @@ int patch_cm9780(struct snd_ac97 * ac97)
9150 int patch_vt1616(struct snd_ac97 * ac97);
9151 int patch_vt1617a(struct snd_ac97 * ac97);
9152 int patch_it2646(struct snd_ac97 * ac97);
9153+int patch_ucb1400(struct snd_ac97 * ac97);
9154 int mpatch_si3036(struct snd_ac97 * ac97);
diff --git a/meta/packages/linux/linux-cmx270-rp_2.6.17.bb b/meta/packages/linux/linux-cmx270-rp_2.6.17.bb
index 846095e401..a67dd4efcb 100644
--- a/meta/packages/linux/linux-cmx270-rp_2.6.17.bb
+++ b/meta/packages/linux/linux-cmx270-rp_2.6.17.bb
@@ -3,6 +3,8 @@ DESCRIPTION = "Linux kernel for Compulab cmx270"
3LICENSE = "GPL" 3LICENSE = "GPL"
4PR = "r1" 4PR = "r1"
5 5
6DEFAULT_PREFERENCE = "-1"
7
6SRC_URI = "http://www.kernel.org/pub/linux/kernel/v2.6/linux-2.6.17.tar.bz2 \ 8SRC_URI = "http://www.kernel.org/pub/linux/kernel/v2.6/linux-2.6.17.tar.bz2 \
7 http://www.rpsys.net/openzaurus/patches/archive/cmx270/cm_x2xx_ide-r1.patch;patch=1 \ 9 http://www.rpsys.net/openzaurus/patches/archive/cmx270/cm_x2xx_ide-r1.patch;patch=1 \
8 http://www.rpsys.net/openzaurus/patches/archive/cmx270/cm_x2xx_mtd-r2.patch;patch=1 \ 10 http://www.rpsys.net/openzaurus/patches/archive/cmx270/cm_x2xx_mtd-r2.patch;patch=1 \
diff --git a/meta/packages/linux/linux-cmx270_2.6.16.bb b/meta/packages/linux/linux-cmx270_2.6.16.bb
new file mode 100644
index 0000000000..1101c06e87
--- /dev/null
+++ b/meta/packages/linux/linux-cmx270_2.6.16.bb
@@ -0,0 +1,34 @@
1SECTION = "kernel"
2DESCRIPTION = "Linux kernel CM-X270"
3LICENSE = "GPL"
4PR = "r1"
5
6SRC_URI = "http://www.kernel.org/pub/linux/kernel/v2.6/linux-2.6.16.tar.bz2 \
7 file://diff-2.6.16-cm-x270;patch=1 \
8 file://CL_FlashDrv"
9
10S = "${WORKDIR}//linux-2.6.16"
11
12KERNEL_OUTPUT = "arch/${ARCH}/boot/compressed/${KERNEL_IMAGETYPE}"
13
14inherit kernel
15
16COMPATIBLE_HOST = "arm.*-linux"
17COMPATIBLE_MACHINE = "cmx270"
18
19do_configure_prepend() {
20 install -m 0644 ${S}/arch/arm/configs/cm_x270_defconfig ${S}/.config
21 install -m 0644 ${WORKDIR}/CL_FlashDrv ${S}/drivers/block/cl_flash
22 oe_runmake oldconfig
23}
24
25do_deploy() {
26 install -d ${DEPLOY_DIR}/images
27 install -m 0644 arch/${ARCH}/boot/${KERNEL_IMAGETYPE} ${DEPLOY_DIR}/images/${KERNEL_IMAGETYPE}-${PV}-${MACHINE}-${DATETIME}.bin
28}
29
30do_deploy[dirs] = "${S}"
31
32addtask deploy before do_build after do_compile
33
34KERNEL_RELEASE = "2.6.16" \ No newline at end of file
diff --git a/meta/packages/linux/linux-cmx270_2.6.17.bb b/meta/packages/linux/linux-cmx270_2.6.17.bb
index d9cdd7e9e2..61ea78f0bd 100644
--- a/meta/packages/linux/linux-cmx270_2.6.17.bb
+++ b/meta/packages/linux/linux-cmx270_2.6.17.bb
@@ -3,6 +3,8 @@ DESCRIPTION = "Linux kernel CM-X270"
3LICENSE = "GPL" 3LICENSE = "GPL"
4PR = "r7" 4PR = "r7"
5 5
6DEFAULT_PREFERENCE = "-1"
7
6SRC_URI = "http://www.kernel.org/pub/linux/kernel/v2.6/linux-2.6.17.tar.bz2 \ 8SRC_URI = "http://www.kernel.org/pub/linux/kernel/v2.6/linux-2.6.17.tar.bz2 \
7 http://raph.people.8d.com/kernels/8d-cmx2xx-2.6.17.1-june21.diff;patch=1 \ 9 http://raph.people.8d.com/kernels/8d-cmx2xx-2.6.17.1-june21.diff;patch=1 \
8 http://raph.people.8d.com/kernels/hardcode-archID.diff;patch=1 \ 10 http://raph.people.8d.com/kernels/hardcode-archID.diff;patch=1 \
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-12-10 16:10:23 +0000