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-rw-r--r--meta/recipes-devtools/qemu/qemu.inc21
-rw-r--r--meta/recipes-devtools/qemu/qemu/0001-softfloat-Extend-float_exception_flags-to-16-bits.patch75
-rw-r--r--meta/recipes-devtools/qemu/qemu/0002-softfloat-Add-flag-specific-to-Inf-Inf.patch59
-rw-r--r--meta/recipes-devtools/qemu/qemu/0003-softfloat-Add-flag-specific-to-Inf-0.patch126
-rw-r--r--meta/recipes-devtools/qemu/qemu/0004-softfloat-Add-flags-specific-to-Inf-Inf-and-0-0.patch73
-rw-r--r--meta/recipes-devtools/qemu/qemu/0005-softfloat-Add-flag-specific-to-signaling-nans.patch121
-rw-r--r--meta/recipes-devtools/qemu/qemu/0006-target-ppc-Update-float_invalid_op_addsub-for-new-fl.patch114
-rw-r--r--meta/recipes-devtools/qemu/qemu/0007-target-ppc-Update-float_invalid_op_mul-for-new-flags.patch86
-rw-r--r--meta/recipes-devtools/qemu/qemu/0008-target-ppc-Update-float_invalid_op_div-for-new-flags.patch99
-rw-r--r--meta/recipes-devtools/qemu/qemu/0009-target-ppc-Update-fmadd-for-new-flags.patch102
-rw-r--r--meta/recipes-devtools/qemu/qemu/0010-target-ppc-Split-out-do_fmadd.patch71
-rw-r--r--meta/recipes-devtools/qemu/qemu/0011-target-ppc-Fix-xs-max-min-cj-dp-to-use-VSX-registers.patch93
-rw-r--r--meta/recipes-devtools/qemu/qemu/0012-target-ppc-Move-xs-max-min-cj-dp-to-decodetree.patch121
-rw-r--r--meta/recipes-devtools/qemu/qemu/0013-target-ppc-fix-xscvqpdp-register-access.patch41
-rw-r--r--meta/recipes-devtools/qemu/qemu/0014-target-ppc-move-xscvqpdp-to-decodetree.patch130
-rw-r--r--meta/recipes-devtools/qemu/qemu/0015-target-ppc-ppc_store_fpscr-doesn-t-update-bits-0-to-.patch70
-rw-r--r--meta/recipes-devtools/qemu/qemu/0016-target-ppc-Introduce-TRANS-FLAGS-macros.patch133
-rw-r--r--meta/recipes-devtools/qemu/qemu/0017-target-ppc-Implement-Vector-Expand-Mask.patch105
-rw-r--r--meta/recipes-devtools/qemu/qemu/0018-target-ppc-Implement-Vector-Extract-Mask.patch141
-rw-r--r--meta/recipes-devtools/qemu/qemu/0019-target-ppc-Implement-Vector-Mask-Move-insns.patch187
-rw-r--r--meta/recipes-devtools/qemu/qemu/0020-target-ppc-move-xs-n-madd-am-ds-p-xs-n-msub-am-ds-p-.patch258
-rw-r--r--meta/recipes-devtools/qemu/qemu/0021-target-ppc-implement-xs-n-maddqp-o-xs-n-msubqp-o.patch174
22 files changed, 2400 insertions, 0 deletions
diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc
index 76ae603ee4..14feb4f1e0 100644
--- a/meta/recipes-devtools/qemu/qemu.inc
+++ b/meta/recipes-devtools/qemu/qemu.inc
@@ -71,6 +71,27 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \
71 file://CVE-2021-3611_1.patch \ 71 file://CVE-2021-3611_1.patch \
72 file://CVE-2021-3611_2.patch \ 72 file://CVE-2021-3611_2.patch \
73 file://0001-net-tulip-Restrict-DMA-engine-to-memories.patch \ 73 file://0001-net-tulip-Restrict-DMA-engine-to-memories.patch \
74 file://0001-softfloat-Extend-float_exception_flags-to-16-bits.patch \
75 file://0002-softfloat-Add-flag-specific-to-Inf-Inf.patch \
76 file://0003-softfloat-Add-flag-specific-to-Inf-0.patch \
77 file://0004-softfloat-Add-flags-specific-to-Inf-Inf-and-0-0.patch \
78 file://0005-softfloat-Add-flag-specific-to-signaling-nans.patch \
79 file://0006-target-ppc-Update-float_invalid_op_addsub-for-new-fl.patch \
80 file://0007-target-ppc-Update-float_invalid_op_mul-for-new-flags.patch \
81 file://0008-target-ppc-Update-float_invalid_op_div-for-new-flags.patch \
82 file://0009-target-ppc-Update-fmadd-for-new-flags.patch \
83 file://0010-target-ppc-Split-out-do_fmadd.patch \
84 file://0011-target-ppc-Fix-xs-max-min-cj-dp-to-use-VSX-registers.patch \
85 file://0012-target-ppc-Move-xs-max-min-cj-dp-to-decodetree.patch \
86 file://0013-target-ppc-fix-xscvqpdp-register-access.patch \
87 file://0014-target-ppc-move-xscvqpdp-to-decodetree.patch \
88 file://0015-target-ppc-ppc_store_fpscr-doesn-t-update-bits-0-to-.patch \
89 file://0016-target-ppc-Introduce-TRANS-FLAGS-macros.patch \
90 file://0017-target-ppc-Implement-Vector-Expand-Mask.patch \
91 file://0018-target-ppc-Implement-Vector-Extract-Mask.patch \
92 file://0019-target-ppc-Implement-Vector-Mask-Move-insns.patch \
93 file://0020-target-ppc-move-xs-n-madd-am-ds-p-xs-n-msub-am-ds-p-.patch \
94 file://0021-target-ppc-implement-xs-n-maddqp-o-xs-n-msubqp-o.patch \
74 " 95 "
75UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar" 96UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar"
76 97
diff --git a/meta/recipes-devtools/qemu/qemu/0001-softfloat-Extend-float_exception_flags-to-16-bits.patch b/meta/recipes-devtools/qemu/qemu/0001-softfloat-Extend-float_exception_flags-to-16-bits.patch
new file mode 100644
index 0000000000..e9c47f6901
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0001-softfloat-Extend-float_exception_flags-to-16-bits.patch
@@ -0,0 +1,75 @@
1From 0bec1ded33a857f59cf5f3ceca2f72694256e710 Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 01/21] softfloat: Extend float_exception_flags to 16 bits
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9We will shortly have more than 8 bits of exceptions.
10Repack the existing flags into low bits and reformat to hex.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=149a48f6e6ccedfa01307d45884aa480f5bf77c5]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17Message-Id: <20211119160502.17432-2-richard.henderson@linaro.org>
18Signed-off-by: Cédric Le Goater <clg@kaod.org>
19Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
20---
21 include/fpu/softfloat-types.h | 16 ++++++++--------
22 include/fpu/softfloat.h | 2 +-
23 2 files changed, 9 insertions(+), 9 deletions(-)
24
25diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
26index 5bcbd041f7..65a43aff59 100644
27--- a/include/fpu/softfloat-types.h
28+++ b/include/fpu/softfloat-types.h
29@@ -145,13 +145,13 @@ typedef enum __attribute__((__packed__)) {
30 */
31
32 enum {
33- float_flag_invalid = 1,
34- float_flag_divbyzero = 4,
35- float_flag_overflow = 8,
36- float_flag_underflow = 16,
37- float_flag_inexact = 32,
38- float_flag_input_denormal = 64,
39- float_flag_output_denormal = 128
40+ float_flag_invalid = 0x0001,
41+ float_flag_divbyzero = 0x0002,
42+ float_flag_overflow = 0x0004,
43+ float_flag_underflow = 0x0008,
44+ float_flag_inexact = 0x0010,
45+ float_flag_input_denormal = 0x0020,
46+ float_flag_output_denormal = 0x0040,
47 };
48
49 /*
50@@ -171,8 +171,8 @@ typedef enum __attribute__((__packed__)) {
51 */
52
53 typedef struct float_status {
54+ uint16_t float_exception_flags;
55 FloatRoundMode float_rounding_mode;
56- uint8_t float_exception_flags;
57 FloatX80RoundPrec floatx80_rounding_precision;
58 bool tininess_before_rounding;
59 /* should denormalised results go to zero and set the inexact flag? */
60diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
61index a249991e61..0d3b407807 100644
62--- a/include/fpu/softfloat.h
63+++ b/include/fpu/softfloat.h
64@@ -100,7 +100,7 @@ typedef enum {
65 | Routine to raise any or all of the software IEC/IEEE floating-point
66 | exception flags.
67 *----------------------------------------------------------------------------*/
68-static inline void float_raise(uint8_t flags, float_status *status)
69+static inline void float_raise(uint16_t flags, float_status *status)
70 {
71 status->float_exception_flags |= flags;
72 }
73--
742.17.1
75
diff --git a/meta/recipes-devtools/qemu/qemu/0002-softfloat-Add-flag-specific-to-Inf-Inf.patch b/meta/recipes-devtools/qemu/qemu/0002-softfloat-Add-flag-specific-to-Inf-Inf.patch
new file mode 100644
index 0000000000..2713ff370d
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0002-softfloat-Add-flag-specific-to-Inf-Inf.patch
@@ -0,0 +1,59 @@
1From 9b0737858b2b68c3a4d1e0611f2732679c997c6d Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 02/21] softfloat: Add flag specific to Inf - Inf
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9PowerPC has this flag, and it's easier to compute it here
10than after the fact.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=ba11446c40903b9d97fb75a078d43fee6444d3b6]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 fpu/softfloat-parts.c.inc | 3 ++-
21 include/fpu/softfloat-types.h | 1 +
22 2 files changed, 3 insertions(+), 1 deletion(-)
23
24diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
25index 41d4b17e41..eb2b475ca4 100644
26--- a/fpu/softfloat-parts.c.inc
27+++ b/fpu/softfloat-parts.c.inc
28@@ -354,7 +354,7 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b,
29 return a;
30 }
31 /* Inf - Inf */
32- float_raise(float_flag_invalid, s);
33+ float_raise(float_flag_invalid | float_flag_invalid_isi, s);
34 parts_default_nan(a, s);
35 return a;
36 }
37@@ -494,6 +494,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
38
39 if (ab_mask & float_cmask_inf) {
40 if (c->cls == float_class_inf && a->sign != c->sign) {
41+ float_raise(float_flag_invalid | float_flag_invalid_isi, s);
42 goto d_nan;
43 }
44 goto return_inf;
45diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
46index 65a43aff59..eaa12e1e00 100644
47--- a/include/fpu/softfloat-types.h
48+++ b/include/fpu/softfloat-types.h
49@@ -152,6 +152,7 @@ enum {
50 float_flag_inexact = 0x0010,
51 float_flag_input_denormal = 0x0020,
52 float_flag_output_denormal = 0x0040,
53+ float_flag_invalid_isi = 0x0080, /* inf - inf */
54 };
55
56 /*
57--
582.17.1
59
diff --git a/meta/recipes-devtools/qemu/qemu/0003-softfloat-Add-flag-specific-to-Inf-0.patch b/meta/recipes-devtools/qemu/qemu/0003-softfloat-Add-flag-specific-to-Inf-0.patch
new file mode 100644
index 0000000000..1b21e3cfeb
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0003-softfloat-Add-flag-specific-to-Inf-0.patch
@@ -0,0 +1,126 @@
1From 613f373f0b652ab2fb2572633e7a23807096790b Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 03/21] softfloat: Add flag specific to Inf * 0
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9PowerPC has this flag, and it's easier to compute it here
10than after the fact.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=bead3c9b0ff8efd652afb27923d8ab4458b3bbd9]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 fpu/softfloat-parts.c.inc | 4 ++--
21 fpu/softfloat-specialize.c.inc | 12 ++++++------
22 include/fpu/softfloat-types.h | 1 +
23 3 files changed, 9 insertions(+), 8 deletions(-)
24
25diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
26index eb2b475ca4..3ed793347b 100644
27--- a/fpu/softfloat-parts.c.inc
28+++ b/fpu/softfloat-parts.c.inc
29@@ -423,7 +423,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,
30
31 /* Inf * Zero == NaN */
32 if (unlikely(ab_mask == float_cmask_infzero)) {
33- float_raise(float_flag_invalid, s);
34+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
35 parts_default_nan(a, s);
36 return a;
37 }
38@@ -489,6 +489,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
39
40 if (unlikely(ab_mask != float_cmask_normal)) {
41 if (unlikely(ab_mask == float_cmask_infzero)) {
42+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
43 goto d_nan;
44 }
45
46@@ -567,7 +568,6 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
47 goto finish_sign;
48
49 d_nan:
50- float_raise(float_flag_invalid, s);
51 parts_default_nan(a, s);
52 return a;
53 }
54diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
55index f2ad0f335e..943e3301d2 100644
56--- a/fpu/softfloat-specialize.c.inc
57+++ b/fpu/softfloat-specialize.c.inc
58@@ -506,7 +506,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
59 * the default NaN
60 */
61 if (infzero && is_qnan(c_cls)) {
62- float_raise(float_flag_invalid, status);
63+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
64 return 3;
65 }
66
67@@ -533,7 +533,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
68 * case sets InvalidOp and returns the default NaN
69 */
70 if (infzero) {
71- float_raise(float_flag_invalid, status);
72+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
73 return 3;
74 }
75 /* Prefer sNaN over qNaN, in the a, b, c order. */
76@@ -556,7 +556,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
77 * case sets InvalidOp and returns the input value 'c'
78 */
79 if (infzero) {
80- float_raise(float_flag_invalid, status);
81+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82 return 2;
83 }
84 /* Prefer sNaN over qNaN, in the c, a, b order. */
85@@ -580,7 +580,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86 * a default NaN
87 */
88 if (infzero) {
89- float_raise(float_flag_invalid, status);
90+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
91 return 2;
92 }
93
94@@ -597,7 +597,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
95 #elif defined(TARGET_RISCV)
96 /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
97 if (infzero) {
98- float_raise(float_flag_invalid, status);
99+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
100 }
101 return 3; /* default NaN */
102 #elif defined(TARGET_XTENSA)
103@@ -606,7 +606,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
104 * an input NaN if we have one (ie c).
105 */
106 if (infzero) {
107- float_raise(float_flag_invalid, status);
108+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
109 return 2;
110 }
111 if (status->use_first_nan) {
112diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
113index eaa12e1e00..56b4cf7835 100644
114--- a/include/fpu/softfloat-types.h
115+++ b/include/fpu/softfloat-types.h
116@@ -153,6 +153,7 @@ enum {
117 float_flag_input_denormal = 0x0020,
118 float_flag_output_denormal = 0x0040,
119 float_flag_invalid_isi = 0x0080, /* inf - inf */
120+ float_flag_invalid_imz = 0x0100, /* inf * 0 */
121 };
122
123 /*
124--
1252.17.1
126
diff --git a/meta/recipes-devtools/qemu/qemu/0004-softfloat-Add-flags-specific-to-Inf-Inf-and-0-0.patch b/meta/recipes-devtools/qemu/qemu/0004-softfloat-Add-flags-specific-to-Inf-Inf-and-0-0.patch
new file mode 100644
index 0000000000..c5377fbe70
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0004-softfloat-Add-flags-specific-to-Inf-Inf-and-0-0.patch
@@ -0,0 +1,73 @@
1From 52f1760d2d65e1a61028cb9d8610c8a38aa44cfc Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 04/21] softfloat: Add flags specific to Inf / Inf and 0 / 0
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9PowerPC has these flags, and it's easier to compute them here
10than after the fact.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=10cc964030fca459591d9353571f3b1b4e1b5aec]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 fpu/softfloat-parts.c.inc | 16 +++++++++++-----
21 include/fpu/softfloat-types.h | 2 ++
22 2 files changed, 13 insertions(+), 5 deletions(-)
23
24diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
25index 3ed793347b..b8563cd2df 100644
26--- a/fpu/softfloat-parts.c.inc
27+++ b/fpu/softfloat-parts.c.inc
28@@ -590,11 +590,13 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b,
29 }
30
31 /* 0/0 or Inf/Inf => NaN */
32- if (unlikely(ab_mask == float_cmask_zero) ||
33- unlikely(ab_mask == float_cmask_inf)) {
34- float_raise(float_flag_invalid, s);
35- parts_default_nan(a, s);
36- return a;
37+ if (unlikely(ab_mask == float_cmask_zero)) {
38+ float_raise(float_flag_invalid | float_flag_invalid_zdz, s);
39+ goto d_nan;
40+ }
41+ if (unlikely(ab_mask == float_cmask_inf)) {
42+ float_raise(float_flag_invalid | float_flag_invalid_idi, s);
43+ goto d_nan;
44 }
45
46 /* All the NaN cases */
47@@ -625,6 +627,10 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b,
48 float_raise(float_flag_divbyzero, s);
49 a->cls = float_class_inf;
50 return a;
51+
52+ d_nan:
53+ parts_default_nan(a, s);
54+ return a;
55 }
56
57 /*
58diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
59index 56b4cf7835..5a9671e564 100644
60--- a/include/fpu/softfloat-types.h
61+++ b/include/fpu/softfloat-types.h
62@@ -154,6 +154,8 @@ enum {
63 float_flag_output_denormal = 0x0040,
64 float_flag_invalid_isi = 0x0080, /* inf - inf */
65 float_flag_invalid_imz = 0x0100, /* inf * 0 */
66+ float_flag_invalid_idi = 0x0200, /* inf / inf */
67+ float_flag_invalid_zdz = 0x0400, /* 0 / 0 */
68 };
69
70 /*
71--
722.17.1
73
diff --git a/meta/recipes-devtools/qemu/qemu/0005-softfloat-Add-flag-specific-to-signaling-nans.patch b/meta/recipes-devtools/qemu/qemu/0005-softfloat-Add-flag-specific-to-signaling-nans.patch
new file mode 100644
index 0000000000..e4ecb496ae
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0005-softfloat-Add-flag-specific-to-signaling-nans.patch
@@ -0,0 +1,121 @@
1From 6bc0b2cffab0ee280ae9730262f162f25c16f6c2 Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 05/21] softfloat: Add flag specific to signaling nans
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9PowerPC has this flag, and it's easier to compute it here
10than after the fact.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=e706d4455b8d54252b11fc504c56df060151cb89]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 fpu/softfloat-parts.c.inc | 18 ++++++++++++------
21 fpu/softfloat.c | 4 +++-
22 include/fpu/softfloat-types.h | 1 +
23 3 files changed, 16 insertions(+), 7 deletions(-)
24
25diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
26index b8563cd2df..9518f3dc61 100644
27--- a/fpu/softfloat-parts.c.inc
28+++ b/fpu/softfloat-parts.c.inc
29@@ -19,7 +19,7 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
30 {
31 switch (a->cls) {
32 case float_class_snan:
33- float_raise(float_flag_invalid, s);
34+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
35 if (s->default_nan_mode) {
36 parts_default_nan(a, s);
37 } else {
38@@ -40,7 +40,7 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
39 float_status *s)
40 {
41 if (is_snan(a->cls) || is_snan(b->cls)) {
42- float_raise(float_flag_invalid, s);
43+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
44 }
45
46 if (s->default_nan_mode) {
47@@ -68,7 +68,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
48 int which;
49
50 if (unlikely(abc_mask & float_cmask_snan)) {
51- float_raise(float_flag_invalid, s);
52+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
53 }
54
55 which = pickNaNMulAdd(a->cls, b->cls, c->cls,
56@@ -1049,8 +1049,10 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode,
57
58 switch (p->cls) {
59 case float_class_snan:
60+ flags |= float_flag_invalid_snan;
61+ /* fall through */
62 case float_class_qnan:
63- flags = float_flag_invalid;
64+ flags |= float_flag_invalid;
65 r = max;
66 break;
67
68@@ -1114,8 +1116,10 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode,
69
70 switch (p->cls) {
71 case float_class_snan:
72+ flags |= float_flag_invalid_snan;
73+ /* fall through */
74 case float_class_qnan:
75- flags = float_flag_invalid;
76+ flags |= float_flag_invalid;
77 r = max;
78 break;
79
80@@ -1341,7 +1345,9 @@ static FloatRelation partsN(compare)(FloatPartsN *a, FloatPartsN *b,
81 }
82
83 if (unlikely(ab_mask & float_cmask_anynan)) {
84- if (!is_quiet || (ab_mask & float_cmask_snan)) {
85+ if (ab_mask & float_cmask_snan) {
86+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
87+ } else if (!is_quiet) {
88 float_raise(float_flag_invalid, s);
89 }
90 return float_relation_unordered;
91diff --git a/fpu/softfloat.c b/fpu/softfloat.c
92index 9a28720d82..834ed3a054 100644
93--- a/fpu/softfloat.c
94+++ b/fpu/softfloat.c
95@@ -2543,8 +2543,10 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status)
96 static void parts_float_to_ahp(FloatParts64 *a, float_status *s)
97 {
98 switch (a->cls) {
99- case float_class_qnan:
100 case float_class_snan:
101+ float_raise(float_flag_invalid_snan, s);
102+ /* fall through */
103+ case float_class_qnan:
104 /*
105 * There is no NaN in the destination format. Raise Invalid
106 * and return a zero with the sign of the input NaN.
107diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
108index 5a9671e564..e557b9126b 100644
109--- a/include/fpu/softfloat-types.h
110+++ b/include/fpu/softfloat-types.h
111@@ -156,6 +156,7 @@ enum {
112 float_flag_invalid_imz = 0x0100, /* inf * 0 */
113 float_flag_invalid_idi = 0x0200, /* inf / inf */
114 float_flag_invalid_zdz = 0x0400, /* 0 / 0 */
115+ float_flag_invalid_snan = 0x2000, /* any operand was snan */
116 };
117
118 /*
119--
1202.17.1
121
diff --git a/meta/recipes-devtools/qemu/qemu/0006-target-ppc-Update-float_invalid_op_addsub-for-new-fl.patch b/meta/recipes-devtools/qemu/qemu/0006-target-ppc-Update-float_invalid_op_addsub-for-new-fl.patch
new file mode 100644
index 0000000000..5f38c7265f
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0006-target-ppc-Update-float_invalid_op_addsub-for-new-fl.patch
@@ -0,0 +1,114 @@
1From ba4a60dd5df31b9fff8b7b8006bf9f15140cc6c5 Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 06/21] target/ppc: Update float_invalid_op_addsub for new
5 flags
6MIME-Version: 1.0
7Content-Type: text/plain; charset=UTF-8
8Content-Transfer-Encoding: 8bit
9
10Now that vxisi and vxsnan are computed directly by
11softfloat, we don't need to recompute it via classes.
12
13Upstream-Status: Backport
14[https://git.qemu.org/?p=qemu.git;a=commit;h=941298ecd7e3103d3789d2dd87dd0f119e81c69e]
15
16Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17Message-Id: <20211119160502.17432-9-richard.henderson@linaro.org>
18Signed-off-by: Cédric Le Goater <clg@kaod.org>
19Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
20---
21 target/ppc/fpu_helper.c | 38 ++++++++++++++------------------------
22 1 file changed, 14 insertions(+), 24 deletions(-)
23
24diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
25index c4896cecc8..f0deada84b 100644
26--- a/target/ppc/fpu_helper.c
27+++ b/target/ppc/fpu_helper.c
28@@ -450,13 +450,12 @@ void helper_reset_fpstatus(CPUPPCState *env)
29 set_float_exception_flags(0, &env->fp_status);
30 }
31
32-static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
33- uintptr_t retaddr, int classes)
34+static void float_invalid_op_addsub(CPUPPCState *env, int flags,
35+ bool set_fpcc, uintptr_t retaddr)
36 {
37- if ((classes & ~is_neg) == is_inf) {
38- /* Magnitude subtraction of infinities */
39+ if (flags & float_flag_invalid_isi) {
40 float_invalid_op_vxisi(env, set_fpcc, retaddr);
41- } else if (classes & is_snan) {
42+ } else if (flags & float_flag_invalid_snan) {
43 float_invalid_op_vxsnan(env, retaddr);
44 }
45 }
46@@ -465,12 +464,10 @@ static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
47 float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
48 {
49 float64 ret = float64_add(arg1, arg2, &env->fp_status);
50- int status = get_float_exception_flags(&env->fp_status);
51+ int flags = get_float_exception_flags(&env->fp_status);
52
53- if (unlikely(status & float_flag_invalid)) {
54- float_invalid_op_addsub(env, 1, GETPC(),
55- float64_classify(arg1) |
56- float64_classify(arg2));
57+ if (unlikely(flags & float_flag_invalid)) {
58+ float_invalid_op_addsub(env, flags, 1, GETPC());
59 }
60
61 return ret;
62@@ -480,12 +477,10 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
63 float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
64 {
65 float64 ret = float64_sub(arg1, arg2, &env->fp_status);
66- int status = get_float_exception_flags(&env->fp_status);
67+ int flags = get_float_exception_flags(&env->fp_status);
68
69- if (unlikely(status & float_flag_invalid)) {
70- float_invalid_op_addsub(env, 1, GETPC(),
71- float64_classify(arg1) |
72- float64_classify(arg2));
73+ if (unlikely(flags & float_flag_invalid)) {
74+ float_invalid_op_addsub(env, flags, 1, GETPC());
75 }
76
77 return ret;
78@@ -1616,9 +1611,8 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
79 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
80 \
81 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
82- float_invalid_op_addsub(env, sfprf, GETPC(), \
83- tp##_classify(xa->fld) | \
84- tp##_classify(xb->fld)); \
85+ float_invalid_op_addsub(env, tstat.float_exception_flags, \
86+ sfprf, GETPC()); \
87 } \
88 \
89 if (r2sp) { \
90@@ -1660,9 +1654,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
91 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
92
93 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
94- float_invalid_op_addsub(env, 1, GETPC(),
95- float128_classify(xa->f128) |
96- float128_classify(xb->f128));
97+ float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
98 }
99
100 helper_compute_fprf_float128(env, t.f128);
101@@ -3278,9 +3270,7 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
102 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
103
104 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
105- float_invalid_op_addsub(env, 1, GETPC(),
106- float128_classify(xa->f128) |
107- float128_classify(xb->f128));
108+ float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
109 }
110
111 helper_compute_fprf_float128(env, t.f128);
112--
1132.17.1
114
diff --git a/meta/recipes-devtools/qemu/qemu/0007-target-ppc-Update-float_invalid_op_mul-for-new-flags.patch b/meta/recipes-devtools/qemu/qemu/0007-target-ppc-Update-float_invalid_op_mul-for-new-flags.patch
new file mode 100644
index 0000000000..1cc4e9e35c
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0007-target-ppc-Update-float_invalid_op_mul-for-new-flags.patch
@@ -0,0 +1,86 @@
1From ee8ba2dbb046f48457566b64ad95bf0440d2513e Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 07/21] target/ppc: Update float_invalid_op_mul for new flags
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Now that vximz and vxsnan are computed directly by
10softfloat, we don't need to recompute it via classes.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=4edf55698fc2ea30903657c63ed95db0d5548943]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-10-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 target/ppc/fpu_helper.c | 26 ++++++++++----------------
21 1 file changed, 10 insertions(+), 16 deletions(-)
22
23diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
24index f0deada84b..23264e6528 100644
25--- a/target/ppc/fpu_helper.c
26+++ b/target/ppc/fpu_helper.c
27@@ -486,13 +486,12 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
28 return ret;
29 }
30
31-static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc,
32- uintptr_t retaddr, int classes)
33+static void float_invalid_op_mul(CPUPPCState *env, int flags,
34+ bool set_fprc, uintptr_t retaddr)
35 {
36- if ((classes & (is_zero | is_inf)) == (is_zero | is_inf)) {
37- /* Multiplication of zero by infinity */
38+ if (flags & float_flag_invalid_imz) {
39 float_invalid_op_vximz(env, set_fprc, retaddr);
40- } else if (classes & is_snan) {
41+ } else if (flags & float_flag_invalid_snan) {
42 float_invalid_op_vxsnan(env, retaddr);
43 }
44 }
45@@ -501,12 +500,10 @@ static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc,
46 float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
47 {
48 float64 ret = float64_mul(arg1, arg2, &env->fp_status);
49- int status = get_float_exception_flags(&env->fp_status);
50+ int flags = get_float_exception_flags(&env->fp_status);
51
52- if (unlikely(status & float_flag_invalid)) {
53- float_invalid_op_mul(env, 1, GETPC(),
54- float64_classify(arg1) |
55- float64_classify(arg2));
56+ if (unlikely(flags & float_flag_invalid)) {
57+ float_invalid_op_mul(env, flags, 1, GETPC());
58 }
59
60 return ret;
61@@ -1687,9 +1684,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
62 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
63 \
64 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
65- float_invalid_op_mul(env, sfprf, GETPC(), \
66- tp##_classify(xa->fld) | \
67- tp##_classify(xb->fld)); \
68+ float_invalid_op_mul(env, tstat.float_exception_flags, \
69+ sfprf, GETPC()); \
70 } \
71 \
72 if (r2sp) { \
73@@ -1727,9 +1723,7 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
74 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
75
76 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
77- float_invalid_op_mul(env, 1, GETPC(),
78- float128_classify(xa->f128) |
79- float128_classify(xb->f128));
80+ float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC());
81 }
82 helper_compute_fprf_float128(env, t.f128);
83
84--
852.17.1
86
diff --git a/meta/recipes-devtools/qemu/qemu/0008-target-ppc-Update-float_invalid_op_div-for-new-flags.patch b/meta/recipes-devtools/qemu/qemu/0008-target-ppc-Update-float_invalid_op_div-for-new-flags.patch
new file mode 100644
index 0000000000..cb657eefd5
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0008-target-ppc-Update-float_invalid_op_div-for-new-flags.patch
@@ -0,0 +1,99 @@
1From a13c0819ef14120a0e30077fcc6a7470409fa732 Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 08/21] target/ppc: Update float_invalid_op_div for new flags
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Now that vxidi, vxzdz, and vxsnan are computed directly by
10softfloat, we don't need to recompute it via classes.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=c07f82416cb7973c64d1e21c09957182b4b033dc]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-11-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 target/ppc/fpu_helper.c | 38 ++++++++++++++------------------------
21 1 file changed, 14 insertions(+), 24 deletions(-)
22
23diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
24index 23264e6528..2ab34236a3 100644
25--- a/target/ppc/fpu_helper.c
26+++ b/target/ppc/fpu_helper.c
27@@ -509,17 +509,14 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
28 return ret;
29 }
30
31-static void float_invalid_op_div(CPUPPCState *env, bool set_fprc,
32- uintptr_t retaddr, int classes)
33+static void float_invalid_op_div(CPUPPCState *env, int flags,
34+ bool set_fprc, uintptr_t retaddr)
35 {
36- classes &= ~is_neg;
37- if (classes == is_inf) {
38- /* Division of infinity by infinity */
39+ if (flags & float_flag_invalid_idi) {
40 float_invalid_op_vxidi(env, set_fprc, retaddr);
41- } else if (classes == is_zero) {
42- /* Division of zero by zero */
43+ } else if (flags & float_flag_invalid_zdz) {
44 float_invalid_op_vxzdz(env, set_fprc, retaddr);
45- } else if (classes & is_snan) {
46+ } else if (flags & float_flag_invalid_snan) {
47 float_invalid_op_vxsnan(env, retaddr);
48 }
49 }
50@@ -528,17 +525,13 @@ static void float_invalid_op_div(CPUPPCState *env, bool set_fprc,
51 float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
52 {
53 float64 ret = float64_div(arg1, arg2, &env->fp_status);
54- int status = get_float_exception_flags(&env->fp_status);
55+ int flags = get_float_exception_flags(&env->fp_status);
56
57- if (unlikely(status)) {
58- if (status & float_flag_invalid) {
59- float_invalid_op_div(env, 1, GETPC(),
60- float64_classify(arg1) |
61- float64_classify(arg2));
62- }
63- if (status & float_flag_divbyzero) {
64- float_zero_divide_excp(env, GETPC());
65- }
66+ if (unlikely(flags & float_flag_invalid)) {
67+ float_invalid_op_div(env, flags, 1, GETPC());
68+ }
69+ if (unlikely(flags & float_flag_divbyzero)) {
70+ float_zero_divide_excp(env, GETPC());
71 }
72
73 return ret;
74@@ -1755,9 +1748,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
75 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
76 \
77 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
78- float_invalid_op_div(env, sfprf, GETPC(), \
79- tp##_classify(xa->fld) | \
80- tp##_classify(xb->fld)); \
81+ float_invalid_op_div(env, tstat.float_exception_flags, \
82+ sfprf, GETPC()); \
83 } \
84 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
85 float_zero_divide_excp(env, GETPC()); \
86@@ -1798,9 +1790,7 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
87 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
88
89 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
90- float_invalid_op_div(env, 1, GETPC(),
91- float128_classify(xa->f128) |
92- float128_classify(xb->f128));
93+ float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC());
94 }
95 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
96 float_zero_divide_excp(env, GETPC());
97--
982.17.1
99
diff --git a/meta/recipes-devtools/qemu/qemu/0009-target-ppc-Update-fmadd-for-new-flags.patch b/meta/recipes-devtools/qemu/qemu/0009-target-ppc-Update-fmadd-for-new-flags.patch
new file mode 100644
index 0000000000..2e723582b7
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0009-target-ppc-Update-fmadd-for-new-flags.patch
@@ -0,0 +1,102 @@
1From ce768160ee1ee9673d60e800389c41b3c707411a Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:15 +0100
4Subject: [PATCH 09/21] target/ppc: Update fmadd for new flags
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Now that vximz, vxisi, and vxsnan are computed directly by
10softfloat, we don't need to recompute it. This replaces the
11separate float{32,64}_maddsub_update_excp functions with a
12single float_invalid_op_madd function.
13
14Fix VSX_MADD by passing sfprf to float_invalid_op_madd,
15whereas the previous *_maddsub_update_excp assumed it true.
16
17Upstream-Status: Backport
18[https://git.qemu.org/?p=qemu.git;a=commit;h=e4052bb773cc829a27786d68caa22f28cff19d39]
19
20Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
21Message-Id: <20211119160502.17432-19-richard.henderson@linaro.org>
22Signed-off-by: Cédric Le Goater <clg@kaod.org>
23Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
24---
25 target/ppc/fpu_helper.c | 46 ++++++++++-------------------------------
26 1 file changed, 11 insertions(+), 35 deletions(-)
27
28diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
29index 2ab34236a3..3b1cb25666 100644
30--- a/target/ppc/fpu_helper.c
31+++ b/target/ppc/fpu_helper.c
32@@ -639,38 +639,15 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
33 return do_fri(env, arg, float_round_down);
34 }
35
36-#define FPU_MADDSUB_UPDATE(NAME, TP) \
37-static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \
38- unsigned int madd_flags, uintptr_t retaddr) \
39-{ \
40- if (TP##_is_signaling_nan(arg1, &env->fp_status) || \
41- TP##_is_signaling_nan(arg2, &env->fp_status) || \
42- TP##_is_signaling_nan(arg3, &env->fp_status)) { \
43- /* sNaN operation */ \
44- float_invalid_op_vxsnan(env, retaddr); \
45- } \
46- if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \
47- (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \
48- /* Multiplication of zero by infinity */ \
49- float_invalid_op_vximz(env, 1, retaddr); \
50- } \
51- if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \
52- TP##_is_infinity(arg3)) { \
53- uint8_t aSign, bSign, cSign; \
54- \
55- aSign = TP##_is_neg(arg1); \
56- bSign = TP##_is_neg(arg2); \
57- cSign = TP##_is_neg(arg3); \
58- if (madd_flags & float_muladd_negate_c) { \
59- cSign ^= 1; \
60- } \
61- if (aSign ^ bSign ^ cSign) { \
62- float_invalid_op_vxisi(env, 1, retaddr); \
63- } \
64- } \
65+static void float_invalid_op_madd(CPUPPCState *env, int flags,
66+ bool set_fpcc, uintptr_t retaddr)
67+{
68+ if (flags & float_flag_invalid_imz) {
69+ float_invalid_op_vximz(env, set_fpcc, retaddr);
70+ } else {
71+ float_invalid_op_addsub(env, flags, set_fpcc, retaddr);
72+ }
73 }
74-FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32)
75-FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64)
76
77 #define FPU_FMADD(op, madd_flags) \
78 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
79@@ -682,8 +659,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
80 flags = get_float_exception_flags(&env->fp_status); \
81 if (flags) { \
82 if (flags & float_flag_invalid) { \
83- float64_maddsub_update_excp(env, arg1, arg2, arg3, \
84- madd_flags, GETPC()); \
85+ float_invalid_op_madd(env, flags, 1, GETPC()); \
86 } \
87 do_float_check_status(env, GETPC()); \
88 } \
89@@ -2087,8 +2063,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
90 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
91 \
92 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
93- tp##_maddsub_update_excp(env, xa->fld, b->fld, \
94- c->fld, maddflgs, GETPC()); \
95+ float_invalid_op_madd(env, tstat.float_exception_flags, \
96+ sfprf, GETPC()); \
97 } \
98 \
99 if (r2sp) { \
100--
1012.17.1
102
diff --git a/meta/recipes-devtools/qemu/qemu/0010-target-ppc-Split-out-do_fmadd.patch b/meta/recipes-devtools/qemu/qemu/0010-target-ppc-Split-out-do_fmadd.patch
new file mode 100644
index 0000000000..4d19773200
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0010-target-ppc-Split-out-do_fmadd.patch
@@ -0,0 +1,71 @@
1From f024b8937d8b614994b94e86d2240fafcc7d2d73 Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:15 +0100
4Subject: [PATCH 10/21] target/ppc: Split out do_fmadd
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Create a common function for all of the madd helpers.
10Let the compiler tail call or inline as it chooses.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=ffdaff8e9c698061f57a6b1827570562c5a1c909]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-20-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 target/ppc/fpu_helper.c | 33 ++++++++++++++++++---------------
21 1 file changed, 18 insertions(+), 15 deletions(-)
22
23diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
24index 3b1cb25666..9a1e7e6244 100644
25--- a/target/ppc/fpu_helper.c
26+++ b/target/ppc/fpu_helper.c
27@@ -649,23 +649,26 @@ static void float_invalid_op_madd(CPUPPCState *env, int flags,
28 }
29 }
30
31-#define FPU_FMADD(op, madd_flags) \
32-uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
33- uint64_t arg2, uint64_t arg3) \
34-{ \
35- uint32_t flags; \
36- float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \
37- &env->fp_status); \
38- flags = get_float_exception_flags(&env->fp_status); \
39- if (flags) { \
40- if (flags & float_flag_invalid) { \
41- float_invalid_op_madd(env, flags, 1, GETPC()); \
42- } \
43- do_float_check_status(env, GETPC()); \
44- } \
45- return ret; \
46+static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
47+ float64 c, int madd_flags, uintptr_t retaddr)
48+{
49+ float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status);
50+ int flags = get_float_exception_flags(&env->fp_status);
51+
52+ if (flags) {
53+ if (flags & float_flag_invalid) {
54+ float_invalid_op_madd(env, flags, 1, retaddr);
55+ }
56+ do_float_check_status(env, retaddr);
57+ }
58+ return ret;
59 }
60
61+#define FPU_FMADD(op, madd_flags) \
62+ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
63+ uint64_t arg2, uint64_t arg3) \
64+ { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); }
65+
66 #define MADD_FLGS 0
67 #define MSUB_FLGS float_muladd_negate_c
68 #define NMADD_FLGS float_muladd_negate_result
69--
702.17.1
71
diff --git a/meta/recipes-devtools/qemu/qemu/0011-target-ppc-Fix-xs-max-min-cj-dp-to-use-VSX-registers.patch b/meta/recipes-devtools/qemu/qemu/0011-target-ppc-Fix-xs-max-min-cj-dp-to-use-VSX-registers.patch
new file mode 100644
index 0000000000..0daae55b99
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0011-target-ppc-Fix-xs-max-min-cj-dp-to-use-VSX-registers.patch
@@ -0,0 +1,93 @@
1From a1821ad612994b95cb6597efd15e0a888676386c Mon Sep 17 00:00:00 2001
2From: Victor Colombo <victor.colombo@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:18 +0100
4Subject: [PATCH 11/21] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
10vector registers when they should be using VSX ones. This happens
11because the instructions are using GEN_VSX_HELPER_R3, which adds 32
12to the register numbers, effectively making them vector registers.
13
14This patch fixes it by changing these instructions to use
15GEN_VSX_HELPER_X3.
16
17Upstream-Status: Backport
18[https://git.qemu.org/?p=qemu.git;a=commit;h=201fc774e0e1cc76ec23b595968004a7b14fb6e8]
19
20Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
22Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br>
23Signed-off-by: Cédric Le Goater <clg@kaod.org>
24Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
25---
26 target/ppc/fpu_helper.c | 4 ++--
27 target/ppc/helper.h | 8 ++++----
28 target/ppc/translate/vsx-impl.c.inc | 8 ++++----
29 3 files changed, 10 insertions(+), 10 deletions(-)
30
31diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
32index 9a1e7e6244..ecdcd36a11 100644
33--- a/target/ppc/fpu_helper.c
34+++ b/target/ppc/fpu_helper.c
35@@ -2375,7 +2375,7 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
36 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
37
38 #define VSX_MAX_MINC(name, max) \
39-void helper_##name(CPUPPCState *env, uint32_t opcode, \
40+void helper_##name(CPUPPCState *env, \
41 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
42 { \
43 ppc_vsr_t t = *xt; \
44@@ -2410,7 +2410,7 @@ VSX_MAX_MINC(xsmaxcdp, 1);
45 VSX_MAX_MINC(xsmincdp, 0);
46
47 #define VSX_MAX_MINJ(name, max) \
48-void helper_##name(CPUPPCState *env, uint32_t opcode, \
49+void helper_##name(CPUPPCState *env, \
50 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
51 { \
52 ppc_vsr_t t = *xt; \
53diff --git a/target/ppc/helper.h b/target/ppc/helper.h
54index 627811cefc..12a3d5f269 100644
55--- a/target/ppc/helper.h
56+++ b/target/ppc/helper.h
57@@ -392,10 +392,10 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr)
58 DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr)
59 DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr)
60 DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr)
61-DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr)
62-DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr)
63-DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr)
64-DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr)
65+DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr)
66+DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr)
67+DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr)
68+DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr)
69 DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
70 DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
71 DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
72diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
73index c0e38060b4..02df75339e 100644
74--- a/target/ppc/translate/vsx-impl.c.inc
75+++ b/target/ppc/translate/vsx-impl.c.inc
76@@ -1098,10 +1098,10 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
77 GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
78 GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
79 GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
80-GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
81-GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
82-GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
83-GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
84+GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
85+GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
86+GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
87+GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
88 GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
89 GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
90 GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
91--
922.17.1
93
diff --git a/meta/recipes-devtools/qemu/qemu/0012-target-ppc-Move-xs-max-min-cj-dp-to-decodetree.patch b/meta/recipes-devtools/qemu/qemu/0012-target-ppc-Move-xs-max-min-cj-dp-to-decodetree.patch
new file mode 100644
index 0000000000..e9b99c9b4e
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0012-target-ppc-Move-xs-max-min-cj-dp-to-decodetree.patch
@@ -0,0 +1,121 @@
1From 1cbb2622de34ee034f1dd7196567673c52c84805 Mon Sep 17 00:00:00 2001
2From: Victor Colombo <victor.colombo@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:18 +0100
4Subject: [PATCH 12/21] target/ppc: Move xs{max,min}[cj]dp to decodetree
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Upstream-Status: Backport
10[https://git.qemu.org/?p=qemu.git;a=commit;h=c5df1898a147c232f0502cda5dac8df6074070fc]
11
12Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
14Message-Id: <20211213120958.24443-3-victor.colombo@eldorado.org.br>
15Signed-off-by: Cédric Le Goater <clg@kaod.org>
16Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
17---
18 target/ppc/insn32.decode | 17 +++++++++++++---
19 target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++----
20 target/ppc/translate/vsx-ops.c.inc | 4 ----
21 3 files changed, 40 insertions(+), 11 deletions(-)
22
23diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
24index e135b8aba4..759b2a9aa5 100644
25--- a/target/ppc/insn32.decode
26+++ b/target/ppc/insn32.decode
27@@ -123,10 +123,14 @@
28 &X_vrt_frbp vrt frbp
29 @X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
30
31+%xx_xt 0:1 21:5
32+%xx_xb 1:1 11:5
33+%xx_xa 2:1 16:5
34 &XX2 xt xb uim:uint8_t
35-%xx2_xt 0:1 21:5
36-%xx2_xb 1:1 11:5
37-@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
38+@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
39+
40+&XX3 xt xa xb
41+@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
42
43 &Z22_bf_fra bf fra dm
44 @Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
45@@ -427,3 +431,10 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
46 ## VSX Vector Load Special Value Instruction
47
48 LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
49+
50+## VSX Comparison Instructions
51+
52+XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
53+XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
54+XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
55+XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
56diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
57index 02df75339e..e2447750dd 100644
58--- a/target/ppc/translate/vsx-impl.c.inc
59+++ b/target/ppc/translate/vsx-impl.c.inc
60@@ -1098,10 +1098,6 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
61 GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
62 GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
63 GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
64-GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
65-GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
66-GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
67-GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
68 GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
69 GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
70 GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
71@@ -2185,6 +2181,32 @@ TRANS(XXBLENDVH, do_xxblendv, MO_16)
72 TRANS(XXBLENDVW, do_xxblendv, MO_32)
73 TRANS(XXBLENDVD, do_xxblendv, MO_64)
74
75+static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a,
76+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
77+{
78+ TCGv_ptr xt, xa, xb;
79+
80+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
81+ REQUIRE_VSX(ctx);
82+
83+ xt = gen_vsr_ptr(a->xt);
84+ xa = gen_vsr_ptr(a->xa);
85+ xb = gen_vsr_ptr(a->xb);
86+
87+ helper(cpu_env, xt, xa, xb);
88+
89+ tcg_temp_free_ptr(xt);
90+ tcg_temp_free_ptr(xa);
91+ tcg_temp_free_ptr(xb);
92+
93+ return true;
94+}
95+
96+TRANS(XSMAXCDP, do_xsmaxmincjdp, gen_helper_xsmaxcdp)
97+TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp)
98+TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp)
99+TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp)
100+
101 #undef GEN_XX2FORM
102 #undef GEN_XX3FORM
103 #undef GEN_XX2IFORM
104diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
105index 152d1e5c3b..f980bc1bae 100644
106--- a/target/ppc/translate/vsx-ops.c.inc
107+++ b/target/ppc/translate/vsx-ops.c.inc
108@@ -207,10 +207,6 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
109 GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
110 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
111 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
112-GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
113-GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
114-GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300),
115-GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300),
116 GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
117 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
118 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
119--
1202.17.1
121
diff --git a/meta/recipes-devtools/qemu/qemu/0013-target-ppc-fix-xscvqpdp-register-access.patch b/meta/recipes-devtools/qemu/qemu/0013-target-ppc-fix-xscvqpdp-register-access.patch
new file mode 100644
index 0000000000..100dcd25bc
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0013-target-ppc-fix-xscvqpdp-register-access.patch
@@ -0,0 +1,41 @@
1From 98ff271a4d1a1d60ae53b1f742df7c188b163375 Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:18 +0100
4Subject: [PATCH 13/21] target/ppc: fix xscvqpdp register access
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9This instruction has VRT and VRB fields instead of T/TX and B/BX.
10
11Upstream-Status: Backport
12[https://git.qemu.org/?p=qemu.git;a=commit;h=38d4914c5065e14f0969161274793ded448f067f]
13
14Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
16Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 target/ppc/translate/vsx-impl.c.inc | 5 +++--
21 1 file changed, 3 insertions(+), 2 deletions(-)
22
23diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
24index e2447750dd..ab5cb21f13 100644
25--- a/target/ppc/translate/vsx-impl.c.inc
26+++ b/target/ppc/translate/vsx-impl.c.inc
27@@ -913,8 +913,9 @@ static void gen_xscvqpdp(DisasContext *ctx)
28 return;
29 }
30 opc = tcg_const_i32(ctx->opcode);
31- xt = gen_vsr_ptr(xT(ctx->opcode));
32- xb = gen_vsr_ptr(xB(ctx->opcode));
33+
34+ xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
35+ xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
36 gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
37 tcg_temp_free_i32(opc);
38 tcg_temp_free_ptr(xt);
39--
402.17.1
41
diff --git a/meta/recipes-devtools/qemu/qemu/0014-target-ppc-move-xscvqpdp-to-decodetree.patch b/meta/recipes-devtools/qemu/qemu/0014-target-ppc-move-xscvqpdp-to-decodetree.patch
new file mode 100644
index 0000000000..345a49c90c
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0014-target-ppc-move-xscvqpdp-to-decodetree.patch
@@ -0,0 +1,130 @@
1From c76ea6322bd70c36c9b396cf356167b36928e811 Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:18 +0100
4Subject: [PATCH 14/21] target/ppc: move xscvqpdp to decodetree
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Upstream-Status: Backport
10[https://git.qemu.org/?p=qemu.git;a=commit;h=caf6f9b568479bea6f6d97798be670f21641a006]
11
12Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
14Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br>
15Signed-off-by: Cédric Le Goater <clg@kaod.org>
16Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
17---
18 target/ppc/fpu_helper.c | 10 +++-------
19 target/ppc/helper.h | 2 +-
20 target/ppc/insn32.decode | 4 ++++
21 target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++-----------
22 target/ppc/translate/vsx-ops.c.inc | 1 -
23 5 files changed, 21 insertions(+), 20 deletions(-)
24
25diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
26index ecdcd36a11..5cc7fb1dcb 100644
27--- a/target/ppc/fpu_helper.c
28+++ b/target/ppc/fpu_helper.c
29@@ -2631,18 +2631,14 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
30 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
31 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
32
33-/*
34- * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
35- * added to this later.
36- */
37-void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
38- ppc_vsr_t *xt, ppc_vsr_t *xb)
39+void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
40+ ppc_vsr_t *xb)
41 {
42 ppc_vsr_t t = { };
43 float_status tstat;
44
45 tstat = env->fp_status;
46- if (unlikely(Rc(opcode) != 0)) {
47+ if (ro != 0) {
48 tstat.float_rounding_mode = float_round_to_odd;
49 }
50
51diff --git a/target/ppc/helper.h b/target/ppc/helper.h
52index 12a3d5f269..ef5bdd38a7 100644
53--- a/target/ppc/helper.h
54+++ b/target/ppc/helper.h
55@@ -400,7 +400,7 @@ DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
56 DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
57 DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
58 DEF_HELPER_2(xscvdpspn, i64, env, i64)
59-DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr)
60+DEF_HELPER_4(XSCVQPDP, void, env, i32, vsr, vsr)
61 DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
62 DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
63 DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
64diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
65index 759b2a9aa5..fd6bb13fa0 100644
66--- a/target/ppc/insn32.decode
67+++ b/target/ppc/insn32.decode
68@@ -438,3 +438,7 @@ XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
69 XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
70 XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
71 XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
72+
73+## VSX Binary Floating-Point Convert Instructions
74+
75+XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
76diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
77index ab5cb21f13..c08185e857 100644
78--- a/target/ppc/translate/vsx-impl.c.inc
79+++ b/target/ppc/translate/vsx-impl.c.inc
80@@ -904,22 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
81 VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
82 VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
83
84-static void gen_xscvqpdp(DisasContext *ctx)
85+static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
86 {
87- TCGv_i32 opc;
88+ TCGv_i32 ro;
89 TCGv_ptr xt, xb;
90- if (unlikely(!ctx->vsx_enabled)) {
91- gen_exception(ctx, POWERPC_EXCP_VSXU);
92- return;
93- }
94- opc = tcg_const_i32(ctx->opcode);
95
96- xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
97- xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
98- gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
99- tcg_temp_free_i32(opc);
100+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
101+ REQUIRE_VSX(ctx);
102+
103+ ro = tcg_const_i32(a->rc);
104+
105+ xt = gen_avr_ptr(a->rt);
106+ xb = gen_avr_ptr(a->rb);
107+ gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
108+ tcg_temp_free_i32(ro);
109 tcg_temp_free_ptr(xt);
110 tcg_temp_free_ptr(xb);
111+
112+ return true;
113 }
114
115 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
116diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
117index f980bc1bae..c974324c4c 100644
118--- a/target/ppc/translate/vsx-ops.c.inc
119+++ b/target/ppc/translate/vsx-ops.c.inc
120@@ -133,7 +133,6 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
121 GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
122 GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
123 GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
124-GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
125 GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
126 GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
127 GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
128--
1292.17.1
130
diff --git a/meta/recipes-devtools/qemu/qemu/0015-target-ppc-ppc_store_fpscr-doesn-t-update-bits-0-to-.patch b/meta/recipes-devtools/qemu/qemu/0015-target-ppc-ppc_store_fpscr-doesn-t-update-bits-0-to-.patch
new file mode 100644
index 0000000000..5c5f972961
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0015-target-ppc-ppc_store_fpscr-doesn-t-update-bits-0-to-.patch
@@ -0,0 +1,70 @@
1From 7448ee811d86b18a7f7f59e20853bd852e548f59 Mon Sep 17 00:00:00 2001
2From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:13 +0100
4Subject: [PATCH 15/21] target/ppc: ppc_store_fpscr doesn't update bits 0 to 28
5 and 52
6MIME-Version: 1.0
7Content-Type: text/plain; charset=UTF-8
8Content-Transfer-Encoding: 8bit
9
10This commit fixes the difference reported in the bug in the reserved
11bit 52, it does this by adding this bit to the mask of bits to not be
12directly altered in the ppc_store_fpscr function (the hardware used to
13compare to QEMU was a Power9).
14
15The bits 0 to 27 were also added to the mask, as they are marked as
16reserved in the PowerISA and bit 28 is a reserved extension of the DRN
17field (bits 29:31) but can't be set using mtfsfi, while the other DRN
18bits may be set using mtfsfi instruction, so bit 28 was also added to
19the mask.
20
21Although this is a difference reported in the bug, since it's a reserved
22bit it may be a "don't care" case, as put in the bug report. Looking at
23the ISA it doesn't explicitly mention this bit can't be set, like it
24does for FEX and VX, so I'm unsure if this is necessary.
25
26Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266
27
28Upstream-Status: Backport
29[https://git.qemu.org/?p=qemu.git;a=commit;h=25ee608d79c1890c0f4e8c495ec8629d5712de45]
30
31Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
32Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br>
33Signed-off-by: Cédric Le Goater <clg@kaod.org>
34Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
35---
36 target/ppc/cpu.c | 2 +-
37 target/ppc/cpu.h | 4 ++++
38 2 files changed, 5 insertions(+), 1 deletion(-)
39
40diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
41index f933d9f2bd..d7b42bae52 100644
42--- a/target/ppc/cpu.c
43+++ b/target/ppc/cpu.c
44@@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env)
45
46 void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
47 {
48- val &= ~(FP_VX | FP_FEX);
49+ val &= FPSCR_MTFS_MASK;
50 if (val & FPSCR_IX) {
51 val |= FP_VX;
52 }
53diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
54index e946da5f3a..441d3dce19 100644
55--- a/target/ppc/cpu.h
56+++ b/target/ppc/cpu.h
57@@ -759,6 +759,10 @@ enum {
58 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
59 FP_VXSQRT | FP_VXCVI)
60
61+/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
62+#define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
63+ FP_FEX | FP_VX | PPC_BIT(52)))
64+
65 /*****************************************************************************/
66 /* Vector status and control register */
67 #define VSCR_NJ 16 /* Vector non-java */
68--
692.17.1
70
diff --git a/meta/recipes-devtools/qemu/qemu/0016-target-ppc-Introduce-TRANS-FLAGS-macros.patch b/meta/recipes-devtools/qemu/qemu/0016-target-ppc-Introduce-TRANS-FLAGS-macros.patch
new file mode 100644
index 0000000000..3b651c0b3e
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0016-target-ppc-Introduce-TRANS-FLAGS-macros.patch
@@ -0,0 +1,133 @@
1From 232f979babccd6dfac40a54ee33521e652a0577c Mon Sep 17 00:00:00 2001
2From: Luis Pires <luis.pires@eldorado.org.br>
3Date: Wed, 2 Mar 2022 06:51:36 +0100
4Subject: [PATCH 16/21] target/ppc: Introduce TRANS*FLAGS macros
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9New macros that add FLAGS and FLAGS2 checking were added for
10both TRANS and TRANS64.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=19f0862dd8fa6510b2f5b3aff4859363602cd0cf]
14
15Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
17[ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E
18 - Use the new macros in load/store vector insns ]
19Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
20Message-Id: <20220225210936.1749575-2-matheus.ferst@eldorado.org.br>
21Signed-off-by: Cédric Le Goater <clg@kaod.org>
22Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
23---
24 target/ppc/translate.c | 19 +++++++++++++++
25 target/ppc/translate/vsx-impl.c.inc | 37 ++++++++++-------------------
26 2 files changed, 31 insertions(+), 25 deletions(-)
27
28diff --git a/target/ppc/translate.c b/target/ppc/translate.c
29index 9960df6e18..c12abc32f6 100644
30--- a/target/ppc/translate.c
31+++ b/target/ppc/translate.c
32@@ -7377,10 +7377,29 @@ static int times_16(DisasContext *ctx, int x)
33 #define TRANS(NAME, FUNC, ...) \
34 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
35 { return FUNC(ctx, a, __VA_ARGS__); }
36+#define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \
37+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
38+ { \
39+ REQUIRE_INSNS_FLAGS(ctx, FLAGS); \
40+ return FUNC(ctx, a, __VA_ARGS__); \
41+ }
42+#define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \
43+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
44+ { \
45+ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \
46+ return FUNC(ctx, a, __VA_ARGS__); \
47+ }
48
49 #define TRANS64(NAME, FUNC, ...) \
50 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
51 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
52+#define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \
53+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
54+ { \
55+ REQUIRE_64BIT(ctx); \
56+ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \
57+ return FUNC(ctx, a, __VA_ARGS__); \
58+ }
59
60 /* TODO: More TRANS* helpers for extra insn_flags checks. */
61
62diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
63index c08185e857..99c8a57e50 100644
64--- a/target/ppc/translate/vsx-impl.c.inc
65+++ b/target/ppc/translate/vsx-impl.c.inc
66@@ -2070,12 +2070,6 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
67
68 static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
69 {
70- if (paired) {
71- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
72- } else {
73- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
74- }
75-
76 if (paired || a->rt >= 32) {
77 REQUIRE_VSX(ctx);
78 } else {
79@@ -2089,7 +2083,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
80 bool store, bool paired)
81 {
82 arg_D d;
83- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
84 REQUIRE_VSX(ctx);
85
86 if (!resolve_PLS_D(ctx, &d, a)) {
87@@ -2101,12 +2094,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
88
89 static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
90 {
91- if (paired) {
92- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
93- } else {
94- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
95- }
96-
97 if (paired || a->rt >= 32) {
98 REQUIRE_VSX(ctx);
99 } else {
100@@ -2116,18 +2103,18 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
101 return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
102 }
103
104-TRANS(STXV, do_lstxv_D, true, false)
105-TRANS(LXV, do_lstxv_D, false, false)
106-TRANS(STXVP, do_lstxv_D, true, true)
107-TRANS(LXVP, do_lstxv_D, false, true)
108-TRANS(STXVX, do_lstxv_X, true, false)
109-TRANS(LXVX, do_lstxv_X, false, false)
110-TRANS(STXVPX, do_lstxv_X, true, true)
111-TRANS(LXVPX, do_lstxv_X, false, true)
112-TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
113-TRANS64(PLXV, do_lstxv_PLS_D, false, false)
114-TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
115-TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
116+TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
117+TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
118+TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
119+TRANS_FLAGS2(ISA310, LXVP, do_lstxv_D, false, true)
120+TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false)
121+TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false)
122+TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
123+TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
124+TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
125+TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
126+TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
127+TRANS64_FLAGS2(ISA310, PLXVP, do_lstxv_PLS_D, false, true)
128
129 static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
130 TCGv_vec c)
131--
1322.17.1
133
diff --git a/meta/recipes-devtools/qemu/qemu/0017-target-ppc-Implement-Vector-Expand-Mask.patch b/meta/recipes-devtools/qemu/qemu/0017-target-ppc-Implement-Vector-Expand-Mask.patch
new file mode 100644
index 0000000000..6d6d6b86ed
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0017-target-ppc-Implement-Vector-Expand-Mask.patch
@@ -0,0 +1,105 @@
1From 4c6a16c2bcdd14249eef876d3d029c445716fb13 Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:13 +0100
4Subject: [PATCH 17/21] target/ppc: Implement Vector Expand Mask
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Implement the following PowerISA v3.1 instructions:
10vexpandbm: Vector Expand Byte Mask
11vexpandhm: Vector Expand Halfword Mask
12vexpandwm: Vector Expand Word Mask
13vexpanddm: Vector Expand Doubleword Mask
14vexpandqm: Vector Expand Quadword Mask
15
16Upstream-Status: Backport
17[https://git.qemu.org/?p=qemu.git;a=commit;h=5f1470b091007f24035d6d33149df49a6dd61682]
18
19Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
21Message-Id: <20211203194229.746275-2-matheus.ferst@eldorado.org.br>
22Signed-off-by: Cédric Le Goater <clg@kaod.org>
23Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
24---
25 target/ppc/insn32.decode | 11 ++++++++++
26 target/ppc/translate/vmx-impl.c.inc | 34 +++++++++++++++++++++++++++++
27 2 files changed, 45 insertions(+)
28
29diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
30index fd6bb13fa0..e032251c74 100644
31--- a/target/ppc/insn32.decode
32+++ b/target/ppc/insn32.decode
33@@ -56,6 +56,9 @@
34 &VX_uim4 vrt uim vrb
35 @VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
36
37+&VX_tb vrt vrb
38+@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb
39+
40 &X rt ra rb
41 @X ...... rt:5 ra:5 rb:5 .......... . &X
42
43@@ -412,6 +415,14 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
44 VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
45 VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
46
47+## Vector Mask Manipulation Instructions
48+
49+VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb
50+VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb
51+VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb
52+VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb
53+VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb
54+
55 # VSX Load/Store Instructions
56
57 LXV 111101 ..... ..... ............ . 001 @DQ_TSX
58diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
59index 8eb8d3a067..ebb0484323 100644
60--- a/target/ppc/translate/vmx-impl.c.inc
61+++ b/target/ppc/translate/vmx-impl.c.inc
62@@ -1491,6 +1491,40 @@ static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
63 return true;
64 }
65
66+static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
67+{
68+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
69+ REQUIRE_VECTOR(ctx);
70+
71+ tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
72+ (8 << vece) - 1, 16, 16);
73+
74+ return true;
75+}
76+
77+TRANS(VEXPANDBM, do_vexpand, MO_8)
78+TRANS(VEXPANDHM, do_vexpand, MO_16)
79+TRANS(VEXPANDWM, do_vexpand, MO_32)
80+TRANS(VEXPANDDM, do_vexpand, MO_64)
81+
82+static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
83+{
84+ TCGv_i64 tmp;
85+
86+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
87+ REQUIRE_VECTOR(ctx);
88+
89+ tmp = tcg_temp_new_i64();
90+
91+ get_avr64(tmp, a->vrb, true);
92+ tcg_gen_sari_i64(tmp, tmp, 63);
93+ set_avr64(a->vrt, tmp, false);
94+ set_avr64(a->vrt, tmp, true);
95+
96+ tcg_temp_free_i64(tmp);
97+ return true;
98+}
99+
100 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
101 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
102 { \
103--
1042.17.1
105
diff --git a/meta/recipes-devtools/qemu/qemu/0018-target-ppc-Implement-Vector-Extract-Mask.patch b/meta/recipes-devtools/qemu/qemu/0018-target-ppc-Implement-Vector-Extract-Mask.patch
new file mode 100644
index 0000000000..57450c6fb7
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0018-target-ppc-Implement-Vector-Extract-Mask.patch
@@ -0,0 +1,141 @@
1From 2dc8450e80b82c481904570dce789843b031db13 Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:13 +0100
4Subject: [PATCH 18/21] target/ppc: Implement Vector Extract Mask
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Implement the following PowerISA v3.1 instructions:
10vextractbm: Vector Extract Byte Mask
11vextracthm: Vector Extract Halfword Mask
12vextractwm: Vector Extract Word Mask
13vextractdm: Vector Extract Doubleword Mask
14vextractqm: Vector Extract Quadword Mask
15
16Upstream-Status: Backport
17[https://git.qemu.org/?p=qemu.git;a=commit;h=17868d81e0074905b2c1e414af6618570e8059eb]
18
19Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
20Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21Message-Id: <20211203194229.746275-3-matheus.ferst@eldorado.org.br>
22Signed-off-by: Cédric Le Goater <clg@kaod.org>
23Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
24---
25 target/ppc/insn32.decode | 6 +++
26 target/ppc/translate/vmx-impl.c.inc | 82 +++++++++++++++++++++++++++++
27 2 files changed, 88 insertions(+)
28
29diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
30index e032251c74..b0568b1356 100644
31--- a/target/ppc/insn32.decode
32+++ b/target/ppc/insn32.decode
33@@ -423,6 +423,12 @@ VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb
34 VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb
35 VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb
36
37+VEXTRACTBM 000100 ..... 01000 ..... 11001000010 @VX_tb
38+VEXTRACTHM 000100 ..... 01001 ..... 11001000010 @VX_tb
39+VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb
40+VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb
41+VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb
42+
43 # VSX Load/Store Instructions
44
45 LXV 111101 ..... ..... ............ . 001 @DQ_TSX
46diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
47index ebb0484323..96c97bf6e7 100644
48--- a/target/ppc/translate/vmx-impl.c.inc
49+++ b/target/ppc/translate/vmx-impl.c.inc
50@@ -1525,6 +1525,88 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
51 return true;
52 }
53
54+static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
55+{
56+ const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
57+ mask = dup_const(vece, 1 << (elem_width - 1));
58+ uint64_t i, j;
59+ TCGv_i64 lo, hi, t0, t1;
60+
61+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
62+ REQUIRE_VECTOR(ctx);
63+
64+ hi = tcg_temp_new_i64();
65+ lo = tcg_temp_new_i64();
66+ t0 = tcg_temp_new_i64();
67+ t1 = tcg_temp_new_i64();
68+
69+ get_avr64(lo, a->vrb, false);
70+ get_avr64(hi, a->vrb, true);
71+
72+ tcg_gen_andi_i64(lo, lo, mask);
73+ tcg_gen_andi_i64(hi, hi, mask);
74+
75+ /*
76+ * Gather the most significant bit of each element in the highest element
77+ * element. E.g. for bytes:
78+ * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
79+ * & dup(1 << (elem_width - 1))
80+ * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
81+ * << 32 - 4
82+ * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
83+ * |
84+ * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
85+ * << 16 - 2
86+ * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
87+ * |
88+ * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
89+ * << 8 - 1
90+ * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
91+ * |
92+ * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
93+ */
94+ for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
95+ tcg_gen_shli_i64(t0, hi, j - i);
96+ tcg_gen_shli_i64(t1, lo, j - i);
97+ tcg_gen_or_i64(hi, hi, t0);
98+ tcg_gen_or_i64(lo, lo, t1);
99+ }
100+
101+ tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
102+ tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
103+ tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
104+
105+ tcg_temp_free_i64(hi);
106+ tcg_temp_free_i64(lo);
107+ tcg_temp_free_i64(t0);
108+ tcg_temp_free_i64(t1);
109+
110+ return true;
111+}
112+
113+TRANS(VEXTRACTBM, do_vextractm, MO_8)
114+TRANS(VEXTRACTHM, do_vextractm, MO_16)
115+TRANS(VEXTRACTWM, do_vextractm, MO_32)
116+TRANS(VEXTRACTDM, do_vextractm, MO_64)
117+
118+static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
119+{
120+ TCGv_i64 tmp;
121+
122+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
123+ REQUIRE_VECTOR(ctx);
124+
125+ tmp = tcg_temp_new_i64();
126+
127+ get_avr64(tmp, a->vrb, true);
128+ tcg_gen_shri_i64(tmp, tmp, 63);
129+ tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
130+
131+ tcg_temp_free_i64(tmp);
132+
133+ return true;
134+}
135+
136 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
137 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
138 { \
139--
1402.17.1
141
diff --git a/meta/recipes-devtools/qemu/qemu/0019-target-ppc-Implement-Vector-Mask-Move-insns.patch b/meta/recipes-devtools/qemu/qemu/0019-target-ppc-Implement-Vector-Mask-Move-insns.patch
new file mode 100644
index 0000000000..96fda98771
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0019-target-ppc-Implement-Vector-Mask-Move-insns.patch
@@ -0,0 +1,187 @@
1From 4d5202aad706fd338646d19aafbf255c3864333c Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:13 +0100
4Subject: [PATCH 19/21] target/ppc: Implement Vector Mask Move insns
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Implement the following PowerISA v3.1 instructions:
10mtvsrbm: Move to VSR Byte Mask
11mtvsrhm: Move to VSR Halfword Mask
12mtvsrwm: Move to VSR Word Mask
13mtvsrdm: Move to VSR Doubleword Mask
14mtvsrqm: Move to VSR Quadword Mask
15mtvsrbmi: Move to VSR Byte Mask Immediate
16
17Upstream-Status: Backport
18[https://git.qemu.org/?p=qemu.git;a=commit;h=9193eaa901c54dbff4a91ea0b12a99e0135dbca1]
19
20Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
22Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br>
23Signed-off-by: Cédric Le Goater <clg@kaod.org>
24Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
25---
26 target/ppc/insn32.decode | 11 +++
27 target/ppc/translate/vmx-impl.c.inc | 115 ++++++++++++++++++++++++++++
28 2 files changed, 126 insertions(+)
29
30diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
31index b0568b1356..8bdc059a4c 100644
32--- a/target/ppc/insn32.decode
33+++ b/target/ppc/insn32.decode
34@@ -40,6 +40,10 @@
35 %ds_rtp 22:4 !function=times_2
36 @DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
37
38+&DX_b vrt b
39+%dx_b 6:10 16:5 0:1
40+@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b
41+
42 &DX rt d
43 %dx_d 6:s10 16:5 0:1
44 @DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
45@@ -417,6 +421,13 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
46
47 ## Vector Mask Manipulation Instructions
48
49+MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb
50+MTVSRHM 000100 ..... 10001 ..... 11001000010 @VX_tb
51+MTVSRWM 000100 ..... 10010 ..... 11001000010 @VX_tb
52+MTVSRDM 000100 ..... 10011 ..... 11001000010 @VX_tb
53+MTVSRQM 000100 ..... 10100 ..... 11001000010 @VX_tb
54+MTVSRBMI 000100 ..... ..... .......... 01010 . @DX_b
55+
56 VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb
57 VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb
58 VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb
59diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
60index 96c97bf6e7..d5e02fd7f2 100644
61--- a/target/ppc/translate/vmx-impl.c.inc
62+++ b/target/ppc/translate/vmx-impl.c.inc
63@@ -1607,6 +1607,121 @@ static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
64 return true;
65 }
66
67+static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
68+{
69+ const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece;
70+ uint64_t c;
71+ int i, j;
72+ TCGv_i64 hi, lo, t0, t1;
73+
74+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
75+ REQUIRE_VECTOR(ctx);
76+
77+ hi = tcg_temp_new_i64();
78+ lo = tcg_temp_new_i64();
79+ t0 = tcg_temp_new_i64();
80+ t1 = tcg_temp_new_i64();
81+
82+ tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]);
83+ tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half);
84+ tcg_gen_extract_i64(lo, t0, 0, elem_count_half);
85+
86+ /*
87+ * Spread the bits into their respective elements.
88+ * E.g. for bytes:
89+ * 00000000000000000000000000000000000000000000000000000000abcdefgh
90+ * << 32 - 4
91+ * 0000000000000000000000000000abcdefgh0000000000000000000000000000
92+ * |
93+ * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh
94+ * << 16 - 2
95+ * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000
96+ * |
97+ * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh
98+ * << 8 - 1
99+ * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000
100+ * |
101+ * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh
102+ * & dup(1)
103+ * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
104+ * * 0xff
105+ * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
106+ */
107+ for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
108+ tcg_gen_shli_i64(t0, hi, j - i);
109+ tcg_gen_shli_i64(t1, lo, j - i);
110+ tcg_gen_or_i64(hi, hi, t0);
111+ tcg_gen_or_i64(lo, lo, t1);
112+ }
113+
114+ c = dup_const(vece, 1);
115+ tcg_gen_andi_i64(hi, hi, c);
116+ tcg_gen_andi_i64(lo, lo, c);
117+
118+ c = MAKE_64BIT_MASK(0, elem_width);
119+ tcg_gen_muli_i64(hi, hi, c);
120+ tcg_gen_muli_i64(lo, lo, c);
121+
122+ set_avr64(a->vrt, lo, false);
123+ set_avr64(a->vrt, hi, true);
124+
125+ tcg_temp_free_i64(hi);
126+ tcg_temp_free_i64(lo);
127+ tcg_temp_free_i64(t0);
128+ tcg_temp_free_i64(t1);
129+
130+ return true;
131+}
132+
133+TRANS(MTVSRBM, do_mtvsrm, MO_8)
134+TRANS(MTVSRHM, do_mtvsrm, MO_16)
135+TRANS(MTVSRWM, do_mtvsrm, MO_32)
136+TRANS(MTVSRDM, do_mtvsrm, MO_64)
137+
138+static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a)
139+{
140+ TCGv_i64 tmp;
141+
142+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
143+ REQUIRE_VECTOR(ctx);
144+
145+ tmp = tcg_temp_new_i64();
146+
147+ tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]);
148+ tcg_gen_sextract_i64(tmp, tmp, 0, 1);
149+ set_avr64(a->vrt, tmp, false);
150+ set_avr64(a->vrt, tmp, true);
151+
152+ tcg_temp_free_i64(tmp);
153+
154+ return true;
155+}
156+
157+static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
158+{
159+ const uint64_t mask = dup_const(MO_8, 1);
160+ uint64_t hi, lo;
161+
162+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
163+ REQUIRE_VECTOR(ctx);
164+
165+ hi = extract16(a->b, 8, 8);
166+ lo = extract16(a->b, 0, 8);
167+
168+ for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) {
169+ hi |= hi << (j - i);
170+ lo |= lo << (j - i);
171+ }
172+
173+ hi = (hi & mask) * 0xFF;
174+ lo = (lo & mask) * 0xFF;
175+
176+ set_avr64(a->vrt, tcg_constant_i64(hi), true);
177+ set_avr64(a->vrt, tcg_constant_i64(lo), false);
178+
179+ return true;
180+}
181+
182 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
183 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
184 { \
185--
1862.17.1
187
diff --git a/meta/recipes-devtools/qemu/qemu/0020-target-ppc-move-xs-n-madd-am-ds-p-xs-n-msub-am-ds-p-.patch b/meta/recipes-devtools/qemu/qemu/0020-target-ppc-move-xs-n-madd-am-ds-p-xs-n-msub-am-ds-p-.patch
new file mode 100644
index 0000000000..7e747298a9
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0020-target-ppc-move-xs-n-madd-am-ds-p-xs-n-msub-am-ds-p-.patch
@@ -0,0 +1,258 @@
1From a3c7553efdec661a8f7d7dfc0c0618a35fab005c Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Wed, 2 Mar 2022 06:51:38 +0100
4Subject: [PATCH 20/21] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p
5 to decodetree
6MIME-Version: 1.0
7Content-Type: text/plain; charset=UTF-8
8Content-Transfer-Encoding: 8bit
9
10Upstream-Status: Backport
11[https://git.qemu.org/?p=qemu.git;a=commit;h=e4318ab2e423c4caf9a88a4e99b5e234096b81a9]
12
13Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
15Message-Id: <20220225210936.1749575-37-matheus.ferst@eldorado.org.br>
16Signed-off-by: Cédric Le Goater <clg@kaod.org>
17Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
18---
19 target/ppc/fpu_helper.c | 23 ++++++------
20 target/ppc/helper.h | 16 ++++-----
21 target/ppc/insn32.decode | 22 ++++++++++++
22 target/ppc/translate/vsx-impl.c.inc | 56 ++++++++++++++++++++++++-----
23 target/ppc/translate/vsx-ops.c.inc | 16 ---------
24 5 files changed, 90 insertions(+), 43 deletions(-)
25
26diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
27index 5cc7fb1dcb..853e5f6029 100644
28--- a/target/ppc/fpu_helper.c
29+++ b/target/ppc/fpu_helper.c
30@@ -2036,10 +2036,11 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
31 * maddflgs - flags for the float*muladd routine that control the
32 * various forms (madd, msub, nmadd, nmsub)
33 * sfprf - set FPRF
34+ * r2sp - round intermediate double precision result to single precision
35 */
36 #define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) \
37 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
38- ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) \
39+ ppc_vsr_t *s1, ppc_vsr_t *s2, ppc_vsr_t *s3) \
40 { \
41 ppc_vsr_t t = *xt; \
42 int i; \
43@@ -2055,12 +2056,12 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
44 * result to odd. \
45 */ \
46 set_float_rounding_mode(float_round_to_zero, &tstat); \
47- t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
48+ t.fld = tp##_muladd(s1->fld, s3->fld, s2->fld, \
49 maddflgs, &tstat); \
50 t.fld |= (get_float_exception_flags(&tstat) & \
51 float_flag_inexact) != 0; \
52 } else { \
53- t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
54+ t.fld = tp##_muladd(s1->fld, s3->fld, s2->fld, \
55 maddflgs, &tstat); \
56 } \
57 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
58@@ -2082,14 +2083,14 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
59 do_float_check_status(env, GETPC()); \
60 }
61
62-VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
63-VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
64-VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
65-VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
66-VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
67-VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
68-VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
69-VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
70+VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
71+VSX_MADD(XSMSUBDP, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
72+VSX_MADD(XSNMADDDP, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
73+VSX_MADD(XSNMSUBDP, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
74+VSX_MADD(XSMADDSP, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
75+VSX_MADD(XSMSUBSP, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
76+VSX_MADD(XSNMADDSP, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
77+VSX_MADD(XSNMSUBSP, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
78
79 VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0)
80 VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0)
81diff --git a/target/ppc/helper.h b/target/ppc/helper.h
82index ef5bdd38a7..e147b37644 100644
83--- a/target/ppc/helper.h
84+++ b/target/ppc/helper.h
85@@ -376,10 +376,10 @@ DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr)
86 DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr)
87 DEF_HELPER_4(xstdivdp, void, env, i32, vsr, vsr)
88 DEF_HELPER_3(xstsqrtdp, void, env, i32, vsr)
89-DEF_HELPER_5(xsmadddp, void, env, vsr, vsr, vsr, vsr)
90-DEF_HELPER_5(xsmsubdp, void, env, vsr, vsr, vsr, vsr)
91-DEF_HELPER_5(xsnmadddp, void, env, vsr, vsr, vsr, vsr)
92-DEF_HELPER_5(xsnmsubdp, void, env, vsr, vsr, vsr, vsr)
93+DEF_HELPER_5(XSMADDDP, void, env, vsr, vsr, vsr, vsr)
94+DEF_HELPER_5(XSMSUBDP, void, env, vsr, vsr, vsr, vsr)
95+DEF_HELPER_5(XSNMADDDP, void, env, vsr, vsr, vsr, vsr)
96+DEF_HELPER_5(XSNMSUBDP, void, env, vsr, vsr, vsr, vsr)
97 DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr)
98 DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr)
99 DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr)
100@@ -439,10 +439,10 @@ DEF_HELPER_3(xsresp, void, env, vsr, vsr)
101 DEF_HELPER_2(xsrsp, i64, env, i64)
102 DEF_HELPER_3(xssqrtsp, void, env, vsr, vsr)
103 DEF_HELPER_3(xsrsqrtesp, void, env, vsr, vsr)
104-DEF_HELPER_5(xsmaddsp, void, env, vsr, vsr, vsr, vsr)
105-DEF_HELPER_5(xsmsubsp, void, env, vsr, vsr, vsr, vsr)
106-DEF_HELPER_5(xsnmaddsp, void, env, vsr, vsr, vsr, vsr)
107-DEF_HELPER_5(xsnmsubsp, void, env, vsr, vsr, vsr, vsr)
108+DEF_HELPER_5(XSMADDSP, void, env, vsr, vsr, vsr, vsr)
109+DEF_HELPER_5(XSMSUBSP, void, env, vsr, vsr, vsr, vsr)
110+DEF_HELPER_5(XSNMADDSP, void, env, vsr, vsr, vsr, vsr)
111+DEF_HELPER_5(XSNMSUBSP, void, env, vsr, vsr, vsr, vsr)
112
113 DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr)
114 DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr)
115diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
116index 8bdc059a4c..0ff8818084 100644
117--- a/target/ppc/insn32.decode
118+++ b/target/ppc/insn32.decode
119@@ -451,6 +451,28 @@ STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
120 LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
121 STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
122
123+## VSX Scalar Multiply-Add Instructions
124+
125+XSMADDADP 111100 ..... ..... ..... 00100001 . . . @XX3
126+XSMADDMDP 111100 ..... ..... ..... 00101001 . . . @XX3
127+XSMADDASP 111100 ..... ..... ..... 00000001 . . . @XX3
128+XSMADDMSP 111100 ..... ..... ..... 00001001 . . . @XX3
129+
130+XSMSUBADP 111100 ..... ..... ..... 00110001 . . . @XX3
131+XSMSUBMDP 111100 ..... ..... ..... 00111001 . . . @XX3
132+XSMSUBASP 111100 ..... ..... ..... 00010001 . . . @XX3
133+XSMSUBMSP 111100 ..... ..... ..... 00011001 . . . @XX3
134+
135+XSNMADDASP 111100 ..... ..... ..... 10000001 . . . @XX3
136+XSNMADDMSP 111100 ..... ..... ..... 10001001 . . . @XX3
137+XSNMADDADP 111100 ..... ..... ..... 10100001 . . . @XX3
138+XSNMADDMDP 111100 ..... ..... ..... 10101001 . . . @XX3
139+
140+XSNMSUBASP 111100 ..... ..... ..... 10010001 . . . @XX3
141+XSNMSUBMSP 111100 ..... ..... ..... 10011001 . . . @XX3
142+XSNMSUBADP 111100 ..... ..... ..... 10110001 . . . @XX3
143+XSNMSUBMDP 111100 ..... ..... ..... 10111001 . . . @XX3
144+
145 ## VSX splat instruction
146
147 XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
148diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
149index 99c8a57e50..90d3ac665b 100644
150--- a/target/ppc/translate/vsx-impl.c.inc
151+++ b/target/ppc/translate/vsx-impl.c.inc
152@@ -1201,6 +1201,54 @@ GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
153 GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
154 GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
155
156+static bool do_xsmadd(DisasContext *ctx, int tgt, int src1, int src2, int src3,
157+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
158+{
159+ TCGv_ptr t, s1, s2, s3;
160+
161+ t = gen_vsr_ptr(tgt);
162+ s1 = gen_vsr_ptr(src1);
163+ s2 = gen_vsr_ptr(src2);
164+ s3 = gen_vsr_ptr(src3);
165+
166+ gen_helper(cpu_env, t, s1, s2, s3);
167+
168+ tcg_temp_free_ptr(t);
169+ tcg_temp_free_ptr(s1);
170+ tcg_temp_free_ptr(s2);
171+ tcg_temp_free_ptr(s3);
172+
173+ return true;
174+}
175+
176+static bool do_xsmadd_XX3(DisasContext *ctx, arg_XX3 *a, bool type_a,
177+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
178+{
179+ REQUIRE_VSX(ctx);
180+
181+ if (type_a) {
182+ return do_xsmadd(ctx, a->xt, a->xa, a->xt, a->xb, gen_helper);
183+ }
184+ return do_xsmadd(ctx, a->xt, a->xa, a->xb, a->xt, gen_helper);
185+}
186+
187+TRANS_FLAGS2(VSX, XSMADDADP, do_xsmadd_XX3, true, gen_helper_XSMADDDP)
188+TRANS_FLAGS2(VSX, XSMADDMDP, do_xsmadd_XX3, false, gen_helper_XSMADDDP)
189+TRANS_FLAGS2(VSX, XSMSUBADP, do_xsmadd_XX3, true, gen_helper_XSMSUBDP)
190+TRANS_FLAGS2(VSX, XSMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSMSUBDP)
191+TRANS_FLAGS2(VSX, XSNMADDADP, do_xsmadd_XX3, true, gen_helper_XSNMADDDP)
192+TRANS_FLAGS2(VSX, XSNMADDMDP, do_xsmadd_XX3, false, gen_helper_XSNMADDDP)
193+TRANS_FLAGS2(VSX, XSNMSUBADP, do_xsmadd_XX3, true, gen_helper_XSNMSUBDP)
194+TRANS_FLAGS2(VSX, XSNMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSNMSUBDP)
195+TRANS_FLAGS2(VSX207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP)
196+TRANS_FLAGS2(VSX207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP)
197+TRANS_FLAGS2(VSX207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP)
198+TRANS_FLAGS2(VSX207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP)
199+TRANS_FLAGS2(VSX207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP)
200+TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
201+TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
202+TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
203+
204 #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
205 static void gen_##name(DisasContext *ctx) \
206 { \
207@@ -1231,14 +1279,6 @@ static void gen_##name(DisasContext *ctx) \
208 tcg_temp_free_ptr(c); \
209 }
210
211-GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX)
212-GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX)
213-GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX)
214-GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX)
215-GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207)
216-GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207)
217-GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207)
218-GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207)
219 GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
220 GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX)
221 GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX)
222diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
223index c974324c4c..ef0200eead 100644
224--- a/target/ppc/translate/vsx-ops.c.inc
225+++ b/target/ppc/translate/vsx-ops.c.inc
226@@ -186,14 +186,6 @@ GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
227 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
228 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
229 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
230-GEN_XX3FORM_NAME(xsmadddp, "xsmaddadp", 0x04, 0x04, PPC2_VSX),
231-GEN_XX3FORM_NAME(xsmadddp, "xsmaddmdp", 0x04, 0x05, PPC2_VSX),
232-GEN_XX3FORM_NAME(xsmsubdp, "xsmsubadp", 0x04, 0x06, PPC2_VSX),
233-GEN_XX3FORM_NAME(xsmsubdp, "xsmsubmdp", 0x04, 0x07, PPC2_VSX),
234-GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddadp", 0x04, 0x14, PPC2_VSX),
235-GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddmdp", 0x04, 0x15, PPC2_VSX),
236-GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubadp", 0x04, 0x16, PPC2_VSX),
237-GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubmdp", 0x04, 0x17, PPC2_VSX),
238 GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
239 GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
240 GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
241@@ -235,14 +227,6 @@ GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
242 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
243 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
244 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
245-GEN_XX3FORM_NAME(xsmaddsp, "xsmaddasp", 0x04, 0x00, PPC2_VSX207),
246-GEN_XX3FORM_NAME(xsmaddsp, "xsmaddmsp", 0x04, 0x01, PPC2_VSX207),
247-GEN_XX3FORM_NAME(xsmsubsp, "xsmsubasp", 0x04, 0x02, PPC2_VSX207),
248-GEN_XX3FORM_NAME(xsmsubsp, "xsmsubmsp", 0x04, 0x03, PPC2_VSX207),
249-GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddasp", 0x04, 0x10, PPC2_VSX207),
250-GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddmsp", 0x04, 0x11, PPC2_VSX207),
251-GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubasp", 0x04, 0x12, PPC2_VSX207),
252-GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubmsp", 0x04, 0x13, PPC2_VSX207),
253 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
254 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
255
256--
2572.17.1
258
diff --git a/meta/recipes-devtools/qemu/qemu/0021-target-ppc-implement-xs-n-maddqp-o-xs-n-msubqp-o.patch b/meta/recipes-devtools/qemu/qemu/0021-target-ppc-implement-xs-n-maddqp-o-xs-n-msubqp-o.patch
new file mode 100644
index 0000000000..11d732ac13
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0021-target-ppc-implement-xs-n-maddqp-o-xs-n-msubqp-o.patch
@@ -0,0 +1,174 @@
1From 1c1f82fbf0a434948b041eb35c671137628d5538 Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Wed, 2 Mar 2022 06:51:38 +0100
4Subject: [PATCH 21/21] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Implement the following PowerISA v3.0 instuctions:
10xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd]
11xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round
12 to Odd]
13xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision [using
14 round to Odd]
15xsnmsubqp[o]: VSX Scalar Negative Multiply-Subtract Quad-Precision
16 [using round to Odd]
17
18Upstream-Status: Backport
19[https://git.qemu.org/?p=qemu.git;a=commit;h=3bb1aed246d7b59ceee625a82628f7369d492a8f]
20
21Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
23Message-Id: <20220225210936.1749575-38-matheus.ferst@eldorado.org.br>
24Signed-off-by: Cédric Le Goater <clg@kaod.org>
25Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
26---
27 target/ppc/fpu_helper.c | 42 +++++++++++++++++++++++++++++
28 target/ppc/helper.h | 9 +++++++
29 target/ppc/insn32.decode | 4 +++
30 target/ppc/translate/vsx-impl.c.inc | 25 +++++++++++++++++
31 4 files changed, 80 insertions(+)
32
33diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
34index 853e5f6029..bdbbdb3b11 100644
35--- a/target/ppc/fpu_helper.c
36+++ b/target/ppc/fpu_helper.c
37@@ -2102,6 +2102,48 @@ VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
38 VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
39 VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
40
41+/*
42+ * VSX_MADDQ - VSX floating point quad-precision muliply/add
43+ * op - instruction mnemonic
44+ * maddflgs - flags for the float*muladd routine that control the
45+ * various forms (madd, msub, nmadd, nmsub)
46+ * ro - round to odd
47+ */
48+#define VSX_MADDQ(op, maddflgs, ro) \
49+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *s1, ppc_vsr_t *s2,\
50+ ppc_vsr_t *s3) \
51+{ \
52+ ppc_vsr_t t = *xt; \
53+ \
54+ helper_reset_fpstatus(env); \
55+ \
56+ float_status tstat = env->fp_status; \
57+ set_float_exception_flags(0, &tstat); \
58+ if (ro) { \
59+ tstat.float_rounding_mode = float_round_to_odd; \
60+ } \
61+ t.f128 = float128_muladd(s1->f128, s3->f128, s2->f128, maddflgs, &tstat); \
62+ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
63+ \
64+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
65+ float_invalid_op_madd(env, tstat.float_exception_flags, \
66+ false, GETPC()); \
67+ } \
68+ \
69+ helper_compute_fprf_float128(env, t.f128); \
70+ *xt = t; \
71+ do_float_check_status(env, GETPC()); \
72+}
73+
74+VSX_MADDQ(XSMADDQP, MADD_FLGS, 0)
75+VSX_MADDQ(XSMADDQPO, MADD_FLGS, 1)
76+VSX_MADDQ(XSMSUBQP, MSUB_FLGS, 0)
77+VSX_MADDQ(XSMSUBQPO, MSUB_FLGS, 1)
78+VSX_MADDQ(XSNMADDQP, NMADD_FLGS, 0)
79+VSX_MADDQ(XSNMADDQPO, NMADD_FLGS, 1)
80+VSX_MADDQ(XSNMSUBQP, NMSUB_FLGS, 0)
81+VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
82+
83 /*
84 * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
85 * op - instruction mnemonic
86diff --git a/target/ppc/helper.h b/target/ppc/helper.h
87index e147b37644..b5080c4955 100644
88--- a/target/ppc/helper.h
89+++ b/target/ppc/helper.h
90@@ -444,6 +444,15 @@ DEF_HELPER_5(XSMSUBSP, void, env, vsr, vsr, vsr, vsr)
91 DEF_HELPER_5(XSNMADDSP, void, env, vsr, vsr, vsr, vsr)
92 DEF_HELPER_5(XSNMSUBSP, void, env, vsr, vsr, vsr, vsr)
93
94+DEF_HELPER_5(XSMADDQP, void, env, vsr, vsr, vsr, vsr)
95+DEF_HELPER_5(XSMADDQPO, void, env, vsr, vsr, vsr, vsr)
96+DEF_HELPER_5(XSMSUBQP, void, env, vsr, vsr, vsr, vsr)
97+DEF_HELPER_5(XSMSUBQPO, void, env, vsr, vsr, vsr, vsr)
98+DEF_HELPER_5(XSNMADDQP, void, env, vsr, vsr, vsr, vsr)
99+DEF_HELPER_5(XSNMADDQPO, void, env, vsr, vsr, vsr, vsr)
100+DEF_HELPER_5(XSNMSUBQP, void, env, vsr, vsr, vsr, vsr)
101+DEF_HELPER_5(XSNMSUBQPO, void, env, vsr, vsr, vsr, vsr)
102+
103 DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr)
104 DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr)
105 DEF_HELPER_4(xvmuldp, void, env, vsr, vsr, vsr)
106diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
107index 0ff8818084..6bcb1e6804 100644
108--- a/target/ppc/insn32.decode
109+++ b/target/ppc/insn32.decode
110@@ -457,21 +457,25 @@ XSMADDADP 111100 ..... ..... ..... 00100001 . . . @XX3
111 XSMADDMDP 111100 ..... ..... ..... 00101001 . . . @XX3
112 XSMADDASP 111100 ..... ..... ..... 00000001 . . . @XX3
113 XSMADDMSP 111100 ..... ..... ..... 00001001 . . . @XX3
114+XSMADDQP 111111 ..... ..... ..... 0110000100 . @X_rc
115
116 XSMSUBADP 111100 ..... ..... ..... 00110001 . . . @XX3
117 XSMSUBMDP 111100 ..... ..... ..... 00111001 . . . @XX3
118 XSMSUBASP 111100 ..... ..... ..... 00010001 . . . @XX3
119 XSMSUBMSP 111100 ..... ..... ..... 00011001 . . . @XX3
120+XSMSUBQP 111111 ..... ..... ..... 0110100100 . @X_rc
121
122 XSNMADDASP 111100 ..... ..... ..... 10000001 . . . @XX3
123 XSNMADDMSP 111100 ..... ..... ..... 10001001 . . . @XX3
124 XSNMADDADP 111100 ..... ..... ..... 10100001 . . . @XX3
125 XSNMADDMDP 111100 ..... ..... ..... 10101001 . . . @XX3
126+XSNMADDQP 111111 ..... ..... ..... 0111000100 . @X_rc
127
128 XSNMSUBASP 111100 ..... ..... ..... 10010001 . . . @XX3
129 XSNMSUBMSP 111100 ..... ..... ..... 10011001 . . . @XX3
130 XSNMSUBADP 111100 ..... ..... ..... 10110001 . . . @XX3
131 XSNMSUBMDP 111100 ..... ..... ..... 10111001 . . . @XX3
132+XSNMSUBQP 111111 ..... ..... ..... 0111100100 . @X_rc
133
134 ## VSX splat instruction
135
136diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
137index 90d3ac665b..4253f01319 100644
138--- a/target/ppc/translate/vsx-impl.c.inc
139+++ b/target/ppc/translate/vsx-impl.c.inc
140@@ -1249,6 +1249,31 @@ TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
141 TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
142 TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
143
144+static bool do_xsmadd_X(DisasContext *ctx, arg_X_rc *a,
145+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr),
146+ void (*gen_helper_ro)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
147+{
148+ int vrt, vra, vrb;
149+
150+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
151+ REQUIRE_VSX(ctx);
152+
153+ vrt = a->rt + 32;
154+ vra = a->ra + 32;
155+ vrb = a->rb + 32;
156+
157+ if (a->rc) {
158+ return do_xsmadd(ctx, vrt, vra, vrt, vrb, gen_helper_ro);
159+ }
160+
161+ return do_xsmadd(ctx, vrt, vra, vrt, vrb, gen_helper);
162+}
163+
164+TRANS(XSMADDQP, do_xsmadd_X, gen_helper_XSMADDQP, gen_helper_XSMADDQPO)
165+TRANS(XSMSUBQP, do_xsmadd_X, gen_helper_XSMSUBQP, gen_helper_XSMSUBQPO)
166+TRANS(XSNMADDQP, do_xsmadd_X, gen_helper_XSNMADDQP, gen_helper_XSNMADDQPO)
167+TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO)
168+
169 #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
170 static void gen_##name(DisasContext *ctx) \
171 { \
172--
1732.17.1
174
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 19:11:46 +0000