summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--meta/recipes-devtools/binutils/binutils-2.23.2.inc1
-rw-r--r--meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch398
2 files changed, 399 insertions, 0 deletions
diff --git a/meta/recipes-devtools/binutils/binutils-2.23.2.inc b/meta/recipes-devtools/binutils/binutils-2.23.2.inc
index ddbe522c9c..07bc7e0f7f 100644
--- a/meta/recipes-devtools/binutils/binutils-2.23.2.inc
+++ b/meta/recipes-devtools/binutils/binutils-2.23.2.inc
@@ -29,6 +29,7 @@ SRC_URI = "\
29 file://mips64-default-ld-emulation.patch \ 29 file://mips64-default-ld-emulation.patch \
30 ${BACKPORT} \ 30 ${BACKPORT} \
31 file://binutils-fix-over-array-bounds-issue.patch \ 31 file://binutils-fix-over-array-bounds-issue.patch \
32 file://binutils-xlp-support.patch \
32 " 33 "
33 34
34BACKPORT = "\ 35BACKPORT = "\
diff --git a/meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch b/meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch
new file mode 100644
index 0000000000..b0f727ac64
--- /dev/null
+++ b/meta/recipes-devtools/binutils/binutils-2.23.2/binutils-xlp-support.patch
@@ -0,0 +1,398 @@
1Upstream-Status: Unknown
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From 26adb06ce515aadfec08ce13109b4b98287f677b Mon Sep 17 00:00:00 2001
5From: Nebu Philips <nphilips@netlogicmicro.com>
6Date: Fri, 30 Jul 2010 15:10:03 -0700
7Subject: [PATCH] Add support for Netlogic XLP
8
9Using the mipsisa64r2nlm target, add support for XLP from
10Netlogic. Also, update vendor name to NLM wherever applicable.
11---
12 bfd/aoutx.h | 1 +
13 bfd/archures.c | 1 +
14 bfd/bfd-in2.h | 1 +
15 bfd/config.bfd | 5 +++++
16 bfd/cpu-mips.c | 6 ++++--
17 bfd/elfxx-mips.c | 8 ++++++++
18 binutils/readelf.c | 1 +
19 config.sub | 6 ++++++
20 gas/config/tc-mips.c | 7 ++++++-
21 gas/configure | 3 +++
22 gas/configure.tgt | 2 +-
23 gas/doc/c-mips.texi | 3 ++-
24 include/elf/mips.h | 1 +
25 include/opcode/mips.h | 6 +++++-
26 ld/configure.tgt | 2 ++
27 opcodes/mips-dis.c | 6 ++++++
28 opcodes/mips-opc.c | 31 ++++++++++++++++++++-----------
29 17 files changed, 73 insertions(+), 17 deletions(-)
30
31Index: binutils-2.23.2/bfd/aoutx.h
32===================================================================
33--- binutils-2.23.2.orig/bfd/aoutx.h 2013-04-16 04:19:48.241282004 -0700
34+++ binutils-2.23.2/bfd/aoutx.h 2013-04-16 04:19:52.741282087 -0700
35@@ -798,6 +798,7 @@
36 case bfd_mach_mipsisa64r2:
37 case bfd_mach_mips_sb1:
38 case bfd_mach_mips_xlr:
39+ case bfd_mach_mips_xlp:
40 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
41 arch_flags = M_MIPS2;
42 break;
43Index: binutils-2.23.2/bfd/archures.c
44===================================================================
45--- binutils-2.23.2.orig/bfd/archures.c 2013-04-16 04:19:48.241282004 -0700
46+++ binutils-2.23.2/bfd/archures.c 2013-04-16 04:19:52.741282087 -0700
47@@ -179,6 +179,7 @@
48 .#define bfd_mach_mips_octeonp 6601
49 .#define bfd_mach_mips_octeon2 6502
50 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
51+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
52 .#define bfd_mach_mipsisa32 32
53 .#define bfd_mach_mipsisa32r2 33
54 .#define bfd_mach_mipsisa64 64
55Index: binutils-2.23.2/bfd/bfd-in2.h
56===================================================================
57--- binutils-2.23.2.orig/bfd/bfd-in2.h 2013-04-16 04:19:48.241282004 -0700
58+++ binutils-2.23.2/bfd/bfd-in2.h 2013-04-16 04:19:52.745282088 -0700
59@@ -1908,6 +1908,7 @@
60 #define bfd_mach_mips_octeonp 6601
61 #define bfd_mach_mips_octeon2 6502
62 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
63+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
64 #define bfd_mach_mipsisa32 32
65 #define bfd_mach_mipsisa32r2 33
66 #define bfd_mach_mipsisa64 64
67Index: binutils-2.23.2/bfd/config.bfd
68===================================================================
69--- binutils-2.23.2.orig/bfd/config.bfd 2013-04-16 04:19:50.897282052 -0700
70+++ binutils-2.23.2/bfd/config.bfd 2013-04-16 04:19:52.745282088 -0700
71@@ -992,6 +992,11 @@
72 targ_defvec=bfd_elf32_littlemips_vec
73 targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
74 ;;
75+ mipsisa64*-*-elf*)
76+ targ_defvec=bfd_elf32_tradbigmips_vec
77+ targ_selvecs="bfd_elf32_tradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec"
78+ want64=true
79+ ;;
80 mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss)
81 targ_defvec=bfd_elf32_bigmips_vec
82 targ_selvecs="bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
83Index: binutils-2.23.2/bfd/cpu-mips.c
84===================================================================
85--- binutils-2.23.2.orig/bfd/cpu-mips.c 2013-04-16 04:19:48.241282004 -0700
86+++ binutils-2.23.2/bfd/cpu-mips.c 2013-04-16 04:27:21.097290918 -0700
87@@ -97,7 +97,8 @@
88 I_mipsocteonp,
89 I_mipsocteon2,
90 I_xlr,
91- I_micromips
92+ I_micromips,
93+ I_xlp
94 };
95
96 #define NN(index) (&arch_info_struct[(index) + 1])
97@@ -140,7 +141,8 @@
98 N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
99 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
100 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
101- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
102+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
103+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
104 };
105
106 /* The default architecture is mips:3000, but with a machine number of
107Index: binutils-2.23.2/bfd/elfxx-mips.c
108===================================================================
109--- binutils-2.23.2.orig/bfd/elfxx-mips.c 2013-04-16 04:19:48.241282004 -0700
110+++ binutils-2.23.2/bfd/elfxx-mips.c 2013-04-16 04:19:52.749282089 -0700
111@@ -6293,6 +6293,9 @@
112 case E_MIPS_MACH_XLR:
113 return bfd_mach_mips_xlr;
114
115+ case E_MIPS_MACH_XLP:
116+ return bfd_mach_mips_xlp;
117+
118 default:
119 switch (flags & EF_MIPS_ARCH)
120 {
121@@ -11048,6 +11051,10 @@
122 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
123 break;
124
125+ case bfd_mach_mips_xlp:
126+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
127+ break;
128+
129 case bfd_mach_mipsisa32:
130 val = E_MIPS_ARCH_32;
131 break;
132@@ -13639,6 +13646,7 @@
133 { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
134 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
135 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
136+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
137
138 /* MIPS64 extensions. */
139 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
140Index: binutils-2.23.2/binutils/readelf.c
141===================================================================
142--- binutils-2.23.2.orig/binutils/readelf.c 2013-04-16 04:19:48.241282004 -0700
143+++ binutils-2.23.2/binutils/readelf.c 2013-04-16 04:19:52.753282089 -0700
144@@ -2435,6 +2435,7 @@
145 case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
146 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
147 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
148+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
149 case 0:
150 /* We simply ignore the field in this case to avoid confusion:
151 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
152Index: binutils-2.23.2/gas/config/tc-mips.c
153===================================================================
154--- binutils-2.23.2.orig/gas/config/tc-mips.c 2013-04-16 04:19:48.241282004 -0700
155+++ binutils-2.23.2/gas/config/tc-mips.c 2013-04-16 04:19:52.761282087 -0700
156@@ -530,6 +530,7 @@
157 || mips_opts.arch == CPU_RM7000 \
158 || mips_opts.arch == CPU_VR5500 \
159 || mips_opts.micromips \
160+ || mips_opts.arch == CPU_XLP \
161 )
162
163 /* Whether the processor uses hardware interlocks to protect reads
164@@ -558,6 +559,7 @@
165 && mips_opts.isa != ISA_MIPS3) \
166 || mips_opts.arch == CPU_R4300 \
167 || mips_opts.micromips \
168+ || mips_opts.arch == CPU_XLP \
169 )
170
171 /* Whether the processor uses hardware interlocks to protect reads
172@@ -19176,9 +19178,12 @@
173 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
174 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
175
176- /* RMI Xlr */
177+ /* Netlogic Xlr */
178 { "xlr", 0, ISA_MIPS64, CPU_XLR },
179
180+ /* Netlogic Xlp */
181+ { "xlp", 0, ISA_MIPS64R2, CPU_XLP },
182+
183 /* Broadcom XLP.
184 XLP is mostly like XLR, with the prominent exception that it is
185 MIPS64R2 rather than MIPS64. */
186Index: binutils-2.23.2/gas/configure
187===================================================================
188--- binutils-2.23.2.orig/gas/configure 2013-04-16 04:19:50.353282044 -0700
189+++ binutils-2.23.2/gas/configure 2013-04-16 04:19:52.765282087 -0700
190@@ -12695,6 +12695,9 @@
191 mipsisa64r2 | mipsisa64r2el)
192 mips_cpu=mips64r2
193 ;;
194+ mipsisa64r2nlm | mipsisa64r2nlmel)
195+ mips_cpu=xlp
196+ ;;
197 mipstx39 | mipstx39el)
198 mips_cpu=r3900
199 ;;
200Index: binutils-2.23.2/gas/configure.tgt
201===================================================================
202--- binutils-2.23.2.orig/gas/configure.tgt 2013-04-16 04:19:50.097282037 -0700
203+++ binutils-2.23.2/gas/configure.tgt 2013-04-16 04:19:52.765282087 -0700
204@@ -310,7 +310,7 @@
205 mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;;
206 mips*-sde-elf*) fmt=elf em=tmips ;;
207 mips-*-sysv*) fmt=ecoff ;;
208- mips-*-elf* | mips-*-rtems*) fmt=elf ;;
209+ mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;;
210 mips-*-netbsd*) fmt=elf em=tmips ;;
211 mips-*-openbsd*) fmt=elf em=tmips ;;
212
213Index: binutils-2.23.2/include/elf/mips.h
214===================================================================
215--- binutils-2.23.2.orig/include/elf/mips.h 2013-04-16 04:19:48.241282004 -0700
216+++ binutils-2.23.2/include/elf/mips.h 2013-04-16 04:19:52.765282087 -0700
217@@ -268,6 +268,7 @@
218 #define E_MIPS_MACH_SB1 0x008a0000
219 #define E_MIPS_MACH_OCTEON 0x008b0000
220 #define E_MIPS_MACH_XLR 0x008c0000
221+#define E_MIPS_MACH_XLP 0x008e0000
222 #define E_MIPS_MACH_OCTEON2 0x008d0000
223 #define E_MIPS_MACH_5400 0x00910000
224 #define E_MIPS_MACH_5500 0x00980000
225Index: binutils-2.23.2/include/opcode/mips.h
226===================================================================
227--- binutils-2.23.2.orig/include/opcode/mips.h 2013-04-16 04:19:48.241282004 -0700
228+++ binutils-2.23.2/include/opcode/mips.h 2013-04-16 04:19:52.769282089 -0700
229@@ -772,8 +772,10 @@
230 #define INSN_LOONGSON_2F 0x80000000
231 /* Loongson 3A. */
232 #define INSN_LOONGSON_3A 0x00000400
233-/* RMI Xlr instruction */
234+/* Netlogic Xlr instruction */
235 #define INSN_XLR 0x00000020
236+/* Netlogic Xlp instruction */
237+#define INSN_XLP 0x00000040
238
239 /* MCU (MicroController) ASE */
240 #define INSN_MCU 0x00000010
241@@ -833,6 +835,7 @@
242 #define CPU_OCTEONP 6601
243 #define CPU_OCTEON2 6502
244 #define CPU_XLR 887682 /* decimal 'XLR' */
245+#define CPU_XLP 887680 /* decimal 'XLP' */
246
247 /* Return true if the given CPU is included in INSN_* mask MASK. */
248
249@@ -897,6 +900,9 @@
250 case CPU_XLR:
251 return (mask & INSN_XLR) != 0;
252
253+ case CPU_XLP:
254+ return (mask & INSN_XLP) != 0;
255+
256 default:
257 return FALSE;
258 }
259Index: binutils-2.23.2/ld/configure.tgt
260===================================================================
261--- binutils-2.23.2.orig/ld/configure.tgt 2013-04-16 04:19:50.897282052 -0700
262+++ binutils-2.23.2/ld/configure.tgt 2013-04-16 04:19:52.769282089 -0700
263@@ -426,6 +426,8 @@
264 targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" ;;
265 mips*-sde-elf*) targ_emul=elf32btsmip
266 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
267+mipsisa64*-*-elf*) targ_emul=elf32btsmip
268+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;;
269 mips*el-*-elf*) targ_emul=elf32elmip ;;
270 mips*-*-elf*) targ_emul=elf32ebmip ;;
271 mips*-*-rtems*) targ_emul=elf32ebmip ;;
272Index: binutils-2.23.2/opcodes/mips-dis.c
273===================================================================
274--- binutils-2.23.2.orig/opcodes/mips-dis.c 2013-04-16 04:19:48.241282004 -0700
275+++ binutils-2.23.2/opcodes/mips-dis.c 2013-04-16 04:19:52.769282089 -0700
276@@ -627,6 +627,12 @@
277 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
278 mips_hwr_names_numeric },
279
280+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
281+ (ISA_MIPS64R2 | INSN_XLP),
282+ mips_cp0_names_mips3264r2,
283+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
284+ mips_hwr_names_mips3264r2 },
285+
286 /* This entry, mips16, is here only for ISA/processor selection; do
287 not print its name. */
288 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
289Index: binutils-2.23.2/opcodes/mips-opc.c
290===================================================================
291--- binutils-2.23.2.orig/opcodes/mips-opc.c 2013-04-16 04:19:48.241282004 -0700
292+++ binutils-2.23.2/opcodes/mips-opc.c 2013-04-16 04:19:52.773282090 -0700
293@@ -126,6 +126,7 @@
294 #define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
295 #define IOCT2 INSN_OCTEON2
296 #define XLR INSN_XLR
297+#define XLP INSN_XLP
298
299 #define G1 (T3 \
300 )
301@@ -606,6 +607,7 @@
302 {"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
303 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
304 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
305+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, XLP },
306 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
307 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
308 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
309@@ -638,10 +640,11 @@
310 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
311 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
312 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
313-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR },
314+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0,0, XLR|XLP },
315 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
316 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
317 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
318+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, XLP },
319 /* dctr and dctw are used on the r5000. */
320 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
321 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
322@@ -697,6 +700,7 @@
323 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
324 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
325 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
326+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_t, 0, XLP},
327 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
328 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
329 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
330@@ -710,6 +714,8 @@
331 /* dmtc2 is at the bottom of the table. */
332 /* dmfc3 is at the bottom of the table. */
333 /* dmtc3 is at the bottom of the table. */
334+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_t, 0, XLP},
335+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_d|RD_s|RD_t, 0, XLP},
336 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCT },
337 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
338 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
339@@ -848,9 +854,9 @@
340 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
341 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
342 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
343-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
344-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
345-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
346+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP },
347+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP },
348+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP },
349 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
350 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
351 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
352@@ -985,7 +991,7 @@
353 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
354 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
355 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
356-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR },
357+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR|XLP },
358 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
359 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
360 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
361@@ -1029,10 +1035,13 @@
362 /* move is at the top of the table. */
363 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
364 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR },
365+{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_d|RD_t|RD_C0|WR_C0, 0, XLP },
366 {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR },
367 {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR },
368-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR },
369-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR },
370+{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_d|RD_t|RD_C0|WR_C0, 0, XLP },
371+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP },
372+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP },
373+{"msgsync", "", 0x4a000004, 0xffffffff, 0, 0, XLP },
374 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 },
375 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
376 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
377@@ -1066,7 +1075,7 @@
378 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
379 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
380 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
381-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR },
382+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR|XLP },
383 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCT },
384 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCT },
385 {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCT },
386@@ -1425,9 +1434,9 @@
387 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55},
388 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
389 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
390-{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
391-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
392-{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
393+{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP },
394+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP },
395+{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR|XLP },
396 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
397 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
398 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-12-06 01:56:47 +0000