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-rw-r--r--meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch1087
-rw-r--r--meta/recipes-devtools/llvm/llvm_git.bb1
2 files changed, 1088 insertions, 0 deletions
diff --git a/meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch b/meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch
new file mode 100644
index 0000000000..cbe6f5bf3f
--- /dev/null
+++ b/meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch
@@ -0,0 +1,1087 @@
1commit 78ff617d3f573fb3a9b2fef180fa0fd43d5584ea
2Author: Lucas Duarte Prates <lucas.prates@arm.com>
3Date: Thu Jun 20 10:22:01 2024 +0100
4
5 [ARM] CMSE security mitigation on function arguments and returned values (#89944)
6
7 The ABI mandates two things related to function calls:
8 - Function arguments must be sign- or zero-extended to the register
9 size by the caller.
10 - Return values must be sign- or zero-extended to the register size by
11 the callee.
12
13 As consequence, callees can assume that function arguments have been
14 extended and so can callers with regards to return values.
15
16 Here lies the problem: Nonsecure code might deliberately ignore this
17 mandate with the intent of attempting an exploit. It might try to pass
18 values that lie outside the expected type's value range in order to
19 trigger undefined behaviour, e.g. out of bounds access.
20
21 With the mitigation implemented, Secure code always performs extension
22 of values passed by Nonsecure code.
23
24 This addresses the vulnerability described in CVE-2024-0151.
25
26 Patches by Victor Campos.
27
28 ---------
29
30 Co-authored-by: Victor Campos <victor.campos@arm.com>
31
32Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/78ff617d3f573fb3a9b2fef180fa0fd43d5584ea]
33CVE: CVE-2024-0151
34Signed-off-by: Deepesh Varatharajan <Deepesh.Varatharajan@windriver.com>
35---
36diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
37index 900113244e41..e12f8c183db2 100644
38--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
39+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
40@@ -154,6 +154,17 @@ static const MCPhysReg GPRArgRegs[] = {
41 ARM::R0, ARM::R1, ARM::R2, ARM::R3
42 };
43
44+static SDValue handleCMSEValue(const SDValue &Value, const ISD::InputArg &Arg,
45+ SelectionDAG &DAG, const SDLoc &DL) {
46+ assert(Arg.ArgVT.isScalarInteger());
47+ assert(Arg.ArgVT.bitsLT(MVT::i32));
48+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, Arg.ArgVT, Value);
49+ SDValue Ext =
50+ DAG.getNode(Arg.Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,
51+ MVT::i32, Trunc);
52+ return Ext;
53+}
54+
55 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
56 if (VT != PromotedLdStVT) {
57 setOperationAction(ISD::LOAD, VT, Promote);
58@@ -2113,7 +2124,7 @@ SDValue ARMTargetLowering::LowerCallResult(
59 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
60 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
61 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
62- SDValue ThisVal) const {
63+ SDValue ThisVal, bool isCmseNSCall) const {
64 // Assign locations to each value returned by this call.
65 SmallVector<CCValAssign, 16> RVLocs;
66 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
67@@ -2191,6 +2202,15 @@ SDValue ARMTargetLowering::LowerCallResult(
68 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
69 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
70
71+ // On CMSE Non-secure Calls, call results (returned values) whose bitwidth
72+ // is less than 32 bits must be sign- or zero-extended after the call for
73+ // security reasons. Although the ABI mandates an extension done by the
74+ // callee, the latter cannot be trusted to follow the rules of the ABI.
75+ const ISD::InputArg &Arg = Ins[VA.getValNo()];
76+ if (isCmseNSCall && Arg.ArgVT.isScalarInteger() &&
77+ VA.getLocVT().isScalarInteger() && Arg.ArgVT.bitsLT(MVT::i32))
78+ Val = handleCMSEValue(Val, Arg, DAG, dl);
79+
80 InVals.push_back(Val);
81 }
82
83@@ -2787,7 +2807,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
84 // return.
85 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
86 InVals, isThisReturn,
87- isThisReturn ? OutVals[0] : SDValue());
88+ isThisReturn ? OutVals[0] : SDValue(), isCmseNSCall);
89 }
90
91 /// HandleByVal - Every parameter *after* a byval parameter is passed
92@@ -4377,8 +4397,6 @@ SDValue ARMTargetLowering::LowerFormalArguments(
93 *DAG.getContext());
94 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
95
96- SmallVector<SDValue, 16> ArgValues;
97- SDValue ArgValue;
98 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
99 unsigned CurArgIdx = 0;
100
101@@ -4432,7 +4450,7 @@ SDValue ARMTargetLowering::LowerFormalArguments(
102 }
103 // Arguments stored in registers.
104 if (VA.isRegLoc()) {
105- EVT RegVT = VA.getLocVT();
106+ SDValue ArgValue;
107
108 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
109 // f64 and vector types are split up into multiple registers or
110@@ -4496,16 +4514,6 @@ SDValue ARMTargetLowering::LowerFormalArguments(
111 case CCValAssign::BCvt:
112 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
113 break;
114- case CCValAssign::SExt:
115- ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
116- DAG.getValueType(VA.getValVT()));
117- ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
118- break;
119- case CCValAssign::ZExt:
120- ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
121- DAG.getValueType(VA.getValVT()));
122- ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
123- break;
124 }
125
126 // f16 arguments have their size extended to 4 bytes and passed as if they
127@@ -4515,6 +4523,15 @@ SDValue ARMTargetLowering::LowerFormalArguments(
128 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
129 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
130
131+ // On CMSE Entry Functions, formal integer arguments whose bitwidth is
132+ // less than 32 bits must be sign- or zero-extended in the callee for
133+ // security reasons. Although the ABI mandates an extension done by the
134+ // caller, the latter cannot be trusted to follow the rules of the ABI.
135+ const ISD::InputArg &Arg = Ins[VA.getValNo()];
136+ if (AFI->isCmseNSEntryFunction() && Arg.ArgVT.isScalarInteger() &&
137+ RegVT.isScalarInteger() && Arg.ArgVT.bitsLT(MVT::i32))
138+ ArgValue = handleCMSEValue(ArgValue, Arg, DAG, dl);
139+
140 InVals.push_back(ArgValue);
141 } else { // VA.isRegLoc()
142 // sanity check
143diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
144index 844b7d4f1707..2168a4a73589 100644
145--- a/llvm/lib/Target/ARM/ARMISelLowering.h
146+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
147@@ -865,7 +865,7 @@ class VectorType;
148 const SmallVectorImpl<ISD::InputArg> &Ins,
149 const SDLoc &dl, SelectionDAG &DAG,
150 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
151- SDValue ThisVal) const;
152+ SDValue ThisVal, bool isCmseNSCall) const;
153
154 bool supportSplitCSR(MachineFunction *MF) const override {
155 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
156diff --git a/llvm/test/CodeGen/ARM/cmse-harden-call-returned-values.ll b/llvm/test/CodeGen/ARM/cmse-harden-call-returned-values.ll
157new file mode 100644
158index 0000000000..58eef443c2
159--- /dev/null
160+++ b/llvm/test/CodeGen/ARM/cmse-harden-call-returned-values.ll
161@@ -0,0 +1,552 @@
162+; RUN: llc %s -mtriple=thumbv8m.main -o - | FileCheck %s --check-prefixes V8M-COMMON,V8M-LE
163+; RUN: llc %s -mtriple=thumbebv8m.main -o - | FileCheck %s --check-prefixes V8M-COMMON,V8M-BE
164+; RUN: llc %s -mtriple=thumbv8.1m.main -o - | FileCheck %s --check-prefixes V81M-COMMON,V81M-LE
165+; RUN: llc %s -mtriple=thumbebv8.1m.main -o - | FileCheck %s --check-prefixes V81M-COMMON,V81M-BE
166+
167+@get_idx = hidden local_unnamed_addr global ptr null, align 4
168+@arr = hidden local_unnamed_addr global [256 x i32] zeroinitializer, align 4
169+
170+define i32 @access_i16() {
171+; V8M-COMMON-LABEL: access_i16:
172+; V8M-COMMON: @ %bb.0: @ %entry
173+; V8M-COMMON-NEXT: push {r7, lr}
174+; V8M-COMMON-NEXT: movw r0, :lower16:get_idx
175+; V8M-COMMON-NEXT: movt r0, :upper16:get_idx
176+; V8M-COMMON-NEXT: ldr r0, [r0]
177+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
178+; V8M-COMMON-NEXT: bic r0, r0, #1
179+; V8M-COMMON-NEXT: sub sp, #136
180+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
181+; V8M-COMMON-NEXT: mov r1, r0
182+; V8M-COMMON-NEXT: mov r2, r0
183+; V8M-COMMON-NEXT: mov r3, r0
184+; V8M-COMMON-NEXT: mov r4, r0
185+; V8M-COMMON-NEXT: mov r5, r0
186+; V8M-COMMON-NEXT: mov r6, r0
187+; V8M-COMMON-NEXT: mov r7, r0
188+; V8M-COMMON-NEXT: mov r8, r0
189+; V8M-COMMON-NEXT: mov r9, r0
190+; V8M-COMMON-NEXT: mov r10, r0
191+; V8M-COMMON-NEXT: mov r11, r0
192+; V8M-COMMON-NEXT: mov r12, r0
193+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
194+; V8M-COMMON-NEXT: blxns r0
195+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
196+; V8M-COMMON-NEXT: add sp, #136
197+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
198+; V8M-COMMON-NEXT: movw r1, :lower16:arr
199+; V8M-COMMON-NEXT: sxth r0, r0
200+; V8M-COMMON-NEXT: movt r1, :upper16:arr
201+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
202+; V8M-COMMON-NEXT: pop {r7, pc}
203+;
204+; V81M-COMMON-LABEL: access_i16:
205+; V81M-COMMON: @ %bb.0: @ %entry
206+; V81M-COMMON-NEXT: push {r7, lr}
207+; V81M-COMMON-NEXT: movw r0, :lower16:get_idx
208+; V81M-COMMON-NEXT: movt r0, :upper16:get_idx
209+; V81M-COMMON-NEXT: ldr r0, [r0]
210+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
211+; V81M-COMMON-NEXT: bic r0, r0, #1
212+; V81M-COMMON-NEXT: sub sp, #136
213+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
214+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
215+; V81M-COMMON-NEXT: blxns r0
216+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
217+; V81M-COMMON-NEXT: add sp, #136
218+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
219+; V81M-COMMON-NEXT: movw r1, :lower16:arr
220+; V81M-COMMON-NEXT: sxth r0, r0
221+; V81M-COMMON-NEXT: movt r1, :upper16:arr
222+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
223+; V81M-COMMON-NEXT: pop {r7, pc}
224+entry:
225+ %0 = load ptr, ptr @get_idx, align 4
226+ %call = tail call signext i16 %0() "cmse_nonsecure_call"
227+ %idxprom = sext i16 %call to i32
228+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
229+ %1 = load i32, ptr %arrayidx, align 4
230+ ret i32 %1
231+}
232+
233+define i32 @access_u16() {
234+; V8M-COMMON-LABEL: access_u16:
235+; V8M-COMMON: @ %bb.0: @ %entry
236+; V8M-COMMON-NEXT: push {r7, lr}
237+; V8M-COMMON-NEXT: movw r0, :lower16:get_idx
238+; V8M-COMMON-NEXT: movt r0, :upper16:get_idx
239+; V8M-COMMON-NEXT: ldr r0, [r0]
240+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
241+; V8M-COMMON-NEXT: bic r0, r0, #1
242+; V8M-COMMON-NEXT: sub sp, #136
243+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
244+; V8M-COMMON-NEXT: mov r1, r0
245+; V8M-COMMON-NEXT: mov r2, r0
246+; V8M-COMMON-NEXT: mov r3, r0
247+; V8M-COMMON-NEXT: mov r4, r0
248+; V8M-COMMON-NEXT: mov r5, r0
249+; V8M-COMMON-NEXT: mov r6, r0
250+; V8M-COMMON-NEXT: mov r7, r0
251+; V8M-COMMON-NEXT: mov r8, r0
252+; V8M-COMMON-NEXT: mov r9, r0
253+; V8M-COMMON-NEXT: mov r10, r0
254+; V8M-COMMON-NEXT: mov r11, r0
255+; V8M-COMMON-NEXT: mov r12, r0
256+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
257+; V8M-COMMON-NEXT: blxns r0
258+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
259+; V8M-COMMON-NEXT: add sp, #136
260+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
261+; V8M-COMMON-NEXT: movw r1, :lower16:arr
262+; V8M-COMMON-NEXT: uxth r0, r0
263+; V8M-COMMON-NEXT: movt r1, :upper16:arr
264+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
265+; V8M-COMMON-NEXT: pop {r7, pc}
266+;
267+; V81M-COMMON-LABEL: access_u16:
268+; V81M-COMMON: @ %bb.0: @ %entry
269+; V81M-COMMON-NEXT: push {r7, lr}
270+; V81M-COMMON-NEXT: movw r0, :lower16:get_idx
271+; V81M-COMMON-NEXT: movt r0, :upper16:get_idx
272+; V81M-COMMON-NEXT: ldr r0, [r0]
273+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
274+; V81M-COMMON-NEXT: bic r0, r0, #1
275+; V81M-COMMON-NEXT: sub sp, #136
276+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
277+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
278+; V81M-COMMON-NEXT: blxns r0
279+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
280+; V81M-COMMON-NEXT: add sp, #136
281+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
282+; V81M-COMMON-NEXT: movw r1, :lower16:arr
283+; V81M-COMMON-NEXT: uxth r0, r0
284+; V81M-COMMON-NEXT: movt r1, :upper16:arr
285+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
286+; V81M-COMMON-NEXT: pop {r7, pc}
287+entry:
288+ %0 = load ptr, ptr @get_idx, align 4
289+ %call = tail call zeroext i16 %0() "cmse_nonsecure_call"
290+ %idxprom = zext i16 %call to i32
291+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
292+ %1 = load i32, ptr %arrayidx, align 4
293+ ret i32 %1
294+}
295+
296+define i32 @access_i8() {
297+; V8M-COMMON-LABEL: access_i8:
298+; V8M-COMMON: @ %bb.0: @ %entry
299+; V8M-COMMON-NEXT: push {r7, lr}
300+; V8M-COMMON-NEXT: movw r0, :lower16:get_idx
301+; V8M-COMMON-NEXT: movt r0, :upper16:get_idx
302+; V8M-COMMON-NEXT: ldr r0, [r0]
303+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
304+; V8M-COMMON-NEXT: bic r0, r0, #1
305+; V8M-COMMON-NEXT: sub sp, #136
306+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
307+; V8M-COMMON-NEXT: mov r1, r0
308+; V8M-COMMON-NEXT: mov r2, r0
309+; V8M-COMMON-NEXT: mov r3, r0
310+; V8M-COMMON-NEXT: mov r4, r0
311+; V8M-COMMON-NEXT: mov r5, r0
312+; V8M-COMMON-NEXT: mov r6, r0
313+; V8M-COMMON-NEXT: mov r7, r0
314+; V8M-COMMON-NEXT: mov r8, r0
315+; V8M-COMMON-NEXT: mov r9, r0
316+; V8M-COMMON-NEXT: mov r10, r0
317+; V8M-COMMON-NEXT: mov r11, r0
318+; V8M-COMMON-NEXT: mov r12, r0
319+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
320+; V8M-COMMON-NEXT: blxns r0
321+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
322+; V8M-COMMON-NEXT: add sp, #136
323+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
324+; V8M-COMMON-NEXT: movw r1, :lower16:arr
325+; V8M-COMMON-NEXT: sxtb r0, r0
326+; V8M-COMMON-NEXT: movt r1, :upper16:arr
327+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
328+; V8M-COMMON-NEXT: pop {r7, pc}
329+;
330+; V81M-COMMON-LABEL: access_i8:
331+; V81M-COMMON: @ %bb.0: @ %entry
332+; V81M-COMMON-NEXT: push {r7, lr}
333+; V81M-COMMON-NEXT: movw r0, :lower16:get_idx
334+; V81M-COMMON-NEXT: movt r0, :upper16:get_idx
335+; V81M-COMMON-NEXT: ldr r0, [r0]
336+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
337+; V81M-COMMON-NEXT: bic r0, r0, #1
338+; V81M-COMMON-NEXT: sub sp, #136
339+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
340+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
341+; V81M-COMMON-NEXT: blxns r0
342+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
343+; V81M-COMMON-NEXT: add sp, #136
344+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
345+; V81M-COMMON-NEXT: movw r1, :lower16:arr
346+; V81M-COMMON-NEXT: sxtb r0, r0
347+; V81M-COMMON-NEXT: movt r1, :upper16:arr
348+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
349+; V81M-COMMON-NEXT: pop {r7, pc}
350+entry:
351+ %0 = load ptr, ptr @get_idx, align 4
352+ %call = tail call signext i8 %0() "cmse_nonsecure_call"
353+ %idxprom = sext i8 %call to i32
354+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
355+ %1 = load i32, ptr %arrayidx, align 4
356+ ret i32 %1
357+}
358+
359+define i32 @access_u8() {
360+; V8M-COMMON-LABEL: access_u8:
361+; V8M-COMMON: @ %bb.0: @ %entry
362+; V8M-COMMON-NEXT: push {r7, lr}
363+; V8M-COMMON-NEXT: movw r0, :lower16:get_idx
364+; V8M-COMMON-NEXT: movt r0, :upper16:get_idx
365+; V8M-COMMON-NEXT: ldr r0, [r0]
366+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
367+; V8M-COMMON-NEXT: bic r0, r0, #1
368+; V8M-COMMON-NEXT: sub sp, #136
369+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
370+; V8M-COMMON-NEXT: mov r1, r0
371+; V8M-COMMON-NEXT: mov r2, r0
372+; V8M-COMMON-NEXT: mov r3, r0
373+; V8M-COMMON-NEXT: mov r4, r0
374+; V8M-COMMON-NEXT: mov r5, r0
375+; V8M-COMMON-NEXT: mov r6, r0
376+; V8M-COMMON-NEXT: mov r7, r0
377+; V8M-COMMON-NEXT: mov r8, r0
378+; V8M-COMMON-NEXT: mov r9, r0
379+; V8M-COMMON-NEXT: mov r10, r0
380+; V8M-COMMON-NEXT: mov r11, r0
381+; V8M-COMMON-NEXT: mov r12, r0
382+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
383+; V8M-COMMON-NEXT: blxns r0
384+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
385+; V8M-COMMON-NEXT: add sp, #136
386+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
387+; V8M-COMMON-NEXT: movw r1, :lower16:arr
388+; V8M-COMMON-NEXT: uxtb r0, r0
389+; V8M-COMMON-NEXT: movt r1, :upper16:arr
390+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
391+; V8M-COMMON-NEXT: pop {r7, pc}
392+;
393+; V81M-COMMON-LABEL: access_u8:
394+; V81M-COMMON: @ %bb.0: @ %entry
395+; V81M-COMMON-NEXT: push {r7, lr}
396+; V81M-COMMON-NEXT: movw r0, :lower16:get_idx
397+; V81M-COMMON-NEXT: movt r0, :upper16:get_idx
398+; V81M-COMMON-NEXT: ldr r0, [r0]
399+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
400+; V81M-COMMON-NEXT: bic r0, r0, #1
401+; V81M-COMMON-NEXT: sub sp, #136
402+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
403+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
404+; V81M-COMMON-NEXT: blxns r0
405+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
406+; V81M-COMMON-NEXT: add sp, #136
407+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
408+; V81M-COMMON-NEXT: movw r1, :lower16:arr
409+; V81M-COMMON-NEXT: uxtb r0, r0
410+; V81M-COMMON-NEXT: movt r1, :upper16:arr
411+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
412+; V81M-COMMON-NEXT: pop {r7, pc}
413+entry:
414+ %0 = load ptr, ptr @get_idx, align 4
415+ %call = tail call zeroext i8 %0() "cmse_nonsecure_call"
416+ %idxprom = zext i8 %call to i32
417+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
418+ %1 = load i32, ptr %arrayidx, align 4
419+ ret i32 %1
420+}
421+
422+define i32 @access_i1() {
423+; V8M-COMMON-LABEL: access_i1:
424+; V8M-COMMON: @ %bb.0: @ %entry
425+; V8M-COMMON-NEXT: push {r7, lr}
426+; V8M-COMMON-NEXT: movw r0, :lower16:get_idx
427+; V8M-COMMON-NEXT: movt r0, :upper16:get_idx
428+; V8M-COMMON-NEXT: ldr r0, [r0]
429+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
430+; V8M-COMMON-NEXT: bic r0, r0, #1
431+; V8M-COMMON-NEXT: sub sp, #136
432+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
433+; V8M-COMMON-NEXT: mov r1, r0
434+; V8M-COMMON-NEXT: mov r2, r0
435+; V8M-COMMON-NEXT: mov r3, r0
436+; V8M-COMMON-NEXT: mov r4, r0
437+; V8M-COMMON-NEXT: mov r5, r0
438+; V8M-COMMON-NEXT: mov r6, r0
439+; V8M-COMMON-NEXT: mov r7, r0
440+; V8M-COMMON-NEXT: mov r8, r0
441+; V8M-COMMON-NEXT: mov r9, r0
442+; V8M-COMMON-NEXT: mov r10, r0
443+; V8M-COMMON-NEXT: mov r11, r0
444+; V8M-COMMON-NEXT: mov r12, r0
445+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
446+; V8M-COMMON-NEXT: blxns r0
447+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
448+; V8M-COMMON-NEXT: add sp, #136
449+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
450+; V8M-COMMON-NEXT: movw r1, :lower16:arr
451+; V8M-COMMON-NEXT: and r0, r0, #1
452+; V8M-COMMON-NEXT: movt r1, :upper16:arr
453+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
454+; V8M-COMMON-NEXT: pop {r7, pc}
455+;
456+; V81M-COMMON-LABEL: access_i1:
457+; V81M-COMMON: @ %bb.0: @ %entry
458+; V81M-COMMON-NEXT: push {r7, lr}
459+; V81M-COMMON-NEXT: movw r0, :lower16:get_idx
460+; V81M-COMMON-NEXT: movt r0, :upper16:get_idx
461+; V81M-COMMON-NEXT: ldr r0, [r0]
462+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
463+; V81M-COMMON-NEXT: bic r0, r0, #1
464+; V81M-COMMON-NEXT: sub sp, #136
465+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
466+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
467+; V81M-COMMON-NEXT: blxns r0
468+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
469+; V81M-COMMON-NEXT: add sp, #136
470+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
471+; V81M-COMMON-NEXT: movw r1, :lower16:arr
472+; V81M-COMMON-NEXT: and r0, r0, #1
473+; V81M-COMMON-NEXT: movt r1, :upper16:arr
474+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
475+; V81M-COMMON-NEXT: pop {r7, pc}
476+entry:
477+ %0 = load ptr, ptr @get_idx, align 4
478+ %call = tail call zeroext i1 %0() "cmse_nonsecure_call"
479+ %idxprom = zext i1 %call to i32
480+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
481+ %1 = load i32, ptr %arrayidx, align 4
482+ ret i32 %1
483+}
484+
485+define i32 @access_i5() {
486+; V8M-COMMON-LABEL: access_i5:
487+; V8M-COMMON: @ %bb.0: @ %entry
488+; V8M-COMMON-NEXT: push {r7, lr}
489+; V8M-COMMON-NEXT: movw r0, :lower16:get_idx
490+; V8M-COMMON-NEXT: movt r0, :upper16:get_idx
491+; V8M-COMMON-NEXT: ldr r0, [r0]
492+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
493+; V8M-COMMON-NEXT: bic r0, r0, #1
494+; V8M-COMMON-NEXT: sub sp, #136
495+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
496+; V8M-COMMON-NEXT: mov r1, r0
497+; V8M-COMMON-NEXT: mov r2, r0
498+; V8M-COMMON-NEXT: mov r3, r0
499+; V8M-COMMON-NEXT: mov r4, r0
500+; V8M-COMMON-NEXT: mov r5, r0
501+; V8M-COMMON-NEXT: mov r6, r0
502+; V8M-COMMON-NEXT: mov r7, r0
503+; V8M-COMMON-NEXT: mov r8, r0
504+; V8M-COMMON-NEXT: mov r9, r0
505+; V8M-COMMON-NEXT: mov r10, r0
506+; V8M-COMMON-NEXT: mov r11, r0
507+; V8M-COMMON-NEXT: mov r12, r0
508+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
509+; V8M-COMMON-NEXT: blxns r0
510+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
511+; V8M-COMMON-NEXT: add sp, #136
512+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
513+; V8M-COMMON-NEXT: movw r1, :lower16:arr
514+; V8M-COMMON-NEXT: sbfx r0, r0, #0, #5
515+; V8M-COMMON-NEXT: movt r1, :upper16:arr
516+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
517+; V8M-COMMON-NEXT: pop {r7, pc}
518+;
519+; V81M-COMMON-LABEL: access_i5:
520+; V81M-COMMON: @ %bb.0: @ %entry
521+; V81M-COMMON-NEXT: push {r7, lr}
522+; V81M-COMMON-NEXT: movw r0, :lower16:get_idx
523+; V81M-COMMON-NEXT: movt r0, :upper16:get_idx
524+; V81M-COMMON-NEXT: ldr r0, [r0]
525+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
526+; V81M-COMMON-NEXT: bic r0, r0, #1
527+; V81M-COMMON-NEXT: sub sp, #136
528+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
529+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
530+; V81M-COMMON-NEXT: blxns r0
531+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
532+; V81M-COMMON-NEXT: add sp, #136
533+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
534+; V81M-COMMON-NEXT: movw r1, :lower16:arr
535+; V81M-COMMON-NEXT: sbfx r0, r0, #0, #5
536+; V81M-COMMON-NEXT: movt r1, :upper16:arr
537+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
538+; V81M-COMMON-NEXT: pop {r7, pc}
539+entry:
540+ %0 = load ptr, ptr @get_idx, align 4
541+ %call = tail call signext i5 %0() "cmse_nonsecure_call"
542+ %idxprom = sext i5 %call to i32
543+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
544+ %1 = load i32, ptr %arrayidx, align 4
545+ ret i32 %1
546+}
547+
548+define i32 @access_u5() {
549+; V8M-COMMON-LABEL: access_u5:
550+; V8M-COMMON: @ %bb.0: @ %entry
551+; V8M-COMMON-NEXT: push {r7, lr}
552+; V8M-COMMON-NEXT: movw r0, :lower16:get_idx
553+; V8M-COMMON-NEXT: movt r0, :upper16:get_idx
554+; V8M-COMMON-NEXT: ldr r0, [r0]
555+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
556+; V8M-COMMON-NEXT: bic r0, r0, #1
557+; V8M-COMMON-NEXT: sub sp, #136
558+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
559+; V8M-COMMON-NEXT: mov r1, r0
560+; V8M-COMMON-NEXT: mov r2, r0
561+; V8M-COMMON-NEXT: mov r3, r0
562+; V8M-COMMON-NEXT: mov r4, r0
563+; V8M-COMMON-NEXT: mov r5, r0
564+; V8M-COMMON-NEXT: mov r6, r0
565+; V8M-COMMON-NEXT: mov r7, r0
566+; V8M-COMMON-NEXT: mov r8, r0
567+; V8M-COMMON-NEXT: mov r9, r0
568+; V8M-COMMON-NEXT: mov r10, r0
569+; V8M-COMMON-NEXT: mov r11, r0
570+; V8M-COMMON-NEXT: mov r12, r0
571+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
572+; V8M-COMMON-NEXT: blxns r0
573+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
574+; V8M-COMMON-NEXT: add sp, #136
575+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
576+; V8M-COMMON-NEXT: movw r1, :lower16:arr
577+; V8M-COMMON-NEXT: and r0, r0, #31
578+; V8M-COMMON-NEXT: movt r1, :upper16:arr
579+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
580+; V8M-COMMON-NEXT: pop {r7, pc}
581+;
582+; V81M-COMMON-LABEL: access_u5:
583+; V81M-COMMON: @ %bb.0: @ %entry
584+; V81M-COMMON-NEXT: push {r7, lr}
585+; V81M-COMMON-NEXT: movw r0, :lower16:get_idx
586+; V81M-COMMON-NEXT: movt r0, :upper16:get_idx
587+; V81M-COMMON-NEXT: ldr r0, [r0]
588+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
589+; V81M-COMMON-NEXT: bic r0, r0, #1
590+; V81M-COMMON-NEXT: sub sp, #136
591+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
592+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
593+; V81M-COMMON-NEXT: blxns r0
594+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
595+; V81M-COMMON-NEXT: add sp, #136
596+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
597+; V81M-COMMON-NEXT: movw r1, :lower16:arr
598+; V81M-COMMON-NEXT: and r0, r0, #31
599+; V81M-COMMON-NEXT: movt r1, :upper16:arr
600+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
601+; V81M-COMMON-NEXT: pop {r7, pc}
602+entry:
603+ %0 = load ptr, ptr @get_idx, align 4
604+ %call = tail call zeroext i5 %0() "cmse_nonsecure_call"
605+ %idxprom = zext i5 %call to i32
606+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
607+ %1 = load i32, ptr %arrayidx, align 4
608+ ret i32 %1
609+}
610+
611+define i32 @access_i33(ptr %f) {
612+; V8M-COMMON-LABEL: access_i33:
613+; V8M-COMMON: @ %bb.0: @ %entry
614+; V8M-COMMON-NEXT: push {r7, lr}
615+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
616+; V8M-COMMON-NEXT: bic r0, r0, #1
617+; V8M-COMMON-NEXT: sub sp, #136
618+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
619+; V8M-COMMON-NEXT: mov r1, r0
620+; V8M-COMMON-NEXT: mov r2, r0
621+; V8M-COMMON-NEXT: mov r3, r0
622+; V8M-COMMON-NEXT: mov r4, r0
623+; V8M-COMMON-NEXT: mov r5, r0
624+; V8M-COMMON-NEXT: mov r6, r0
625+; V8M-COMMON-NEXT: mov r7, r0
626+; V8M-COMMON-NEXT: mov r8, r0
627+; V8M-COMMON-NEXT: mov r9, r0
628+; V8M-COMMON-NEXT: mov r10, r0
629+; V8M-COMMON-NEXT: mov r11, r0
630+; V8M-COMMON-NEXT: mov r12, r0
631+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
632+; V8M-COMMON-NEXT: blxns r0
633+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
634+; V8M-COMMON-NEXT: add sp, #136
635+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
636+; V8M-LE-NEXT: and r0, r1, #1
637+; V8M-BE-NEXT: and r0, r0, #1
638+; V8M-COMMON-NEXT: rsb.w r0, r0, #0
639+; V8M-COMMON-NEXT: pop {r7, pc}
640+;
641+; V81M-COMMON-LABEL: access_i33:
642+; V81M-COMMON: @ %bb.0: @ %entry
643+; V81M-COMMON-NEXT: push {r7, lr}
644+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
645+; V81M-COMMON-NEXT: bic r0, r0, #1
646+; V81M-COMMON-NEXT: sub sp, #136
647+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
648+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
649+; V81M-COMMON-NEXT: blxns r0
650+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
651+; V81M-COMMON-NEXT: add sp, #136
652+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
653+; V81M-LE-NEXT: and r0, r1, #1
654+; V81M-BE-NEXT: and r0, r0, #1
655+; V81M-COMMON-NEXT: rsb.w r0, r0, #0
656+; V81M-COMMON-NEXT: pop {r7, pc}
657+entry:
658+ %call = tail call i33 %f() "cmse_nonsecure_call"
659+ %shr = ashr i33 %call, 32
660+ %conv = trunc nsw i33 %shr to i32
661+ ret i32 %conv
662+}
663+
664+define i32 @access_u33(ptr %f) {
665+; V8M-COMMON-LABEL: access_u33:
666+; V8M-COMMON: @ %bb.0: @ %entry
667+; V8M-COMMON-NEXT: push {r7, lr}
668+; V8M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
669+; V8M-COMMON-NEXT: bic r0, r0, #1
670+; V8M-COMMON-NEXT: sub sp, #136
671+; V8M-COMMON-NEXT: vlstm sp, {d0 - d15}
672+; V8M-COMMON-NEXT: mov r1, r0
673+; V8M-COMMON-NEXT: mov r2, r0
674+; V8M-COMMON-NEXT: mov r3, r0
675+; V8M-COMMON-NEXT: mov r4, r0
676+; V8M-COMMON-NEXT: mov r5, r0
677+; V8M-COMMON-NEXT: mov r6, r0
678+; V8M-COMMON-NEXT: mov r7, r0
679+; V8M-COMMON-NEXT: mov r8, r0
680+; V8M-COMMON-NEXT: mov r9, r0
681+; V8M-COMMON-NEXT: mov r10, r0
682+; V8M-COMMON-NEXT: mov r11, r0
683+; V8M-COMMON-NEXT: mov r12, r0
684+; V8M-COMMON-NEXT: msr apsr_nzcvq, r0
685+; V8M-COMMON-NEXT: blxns r0
686+; V8M-COMMON-NEXT: vlldm sp, {d0 - d15}
687+; V8M-COMMON-NEXT: add sp, #136
688+; V8M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
689+; V8M-LE-NEXT: and r0, r1, #1
690+; V8M-BE-NEXT: and r0, r0, #1
691+; V8M-COMMON-NEXT: pop {r7, pc}
692+;
693+; V81M-COMMON-LABEL: access_u33:
694+; V81M-COMMON: @ %bb.0: @ %entry
695+; V81M-COMMON-NEXT: push {r7, lr}
696+; V81M-COMMON-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
697+; V81M-COMMON-NEXT: bic r0, r0, #1
698+; V81M-COMMON-NEXT: sub sp, #136
699+; V81M-COMMON-NEXT: vlstm sp, {d0 - d15}
700+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
701+; V81M-COMMON-NEXT: blxns r0
702+; V81M-COMMON-NEXT: vlldm sp, {d0 - d15}
703+; V81M-COMMON-NEXT: add sp, #136
704+; V81M-COMMON-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
705+; V81M-LE-NEXT: and r0, r1, #1
706+; V81M-BE-NEXT: and r0, r0, #1
707+; V81M-COMMON-NEXT: pop {r7, pc}
708+entry:
709+ %call = tail call i33 %f() "cmse_nonsecure_call"
710+ %shr = lshr i33 %call, 32
711+ %conv = trunc nuw nsw i33 %shr to i32
712+ ret i32 %conv
713+}
714diff --git a/llvm/test/CodeGen/ARM/cmse-harden-entry-arguments.ll b/llvm/test/CodeGen/ARM/cmse-harden-entry-arguments.ll
715new file mode 100644
716index 0000000000..c66ab00566
717--- /dev/null
718+++ b/llvm/test/CodeGen/ARM/cmse-harden-entry-arguments.ll
719@@ -0,0 +1,368 @@
720+; RUN: llc %s -mtriple=thumbv8m.main -o - | FileCheck %s --check-prefixes V8M-COMMON,V8M-LE
721+; RUN: llc %s -mtriple=thumbebv8m.main -o - | FileCheck %s --check-prefixes V8M-COMMON,V8M-BE
722+; RUN: llc %s -mtriple=thumbv8.1m.main -o - | FileCheck %s --check-prefixes V81M-COMMON,V81M-LE
723+; RUN: llc %s -mtriple=thumbebv8.1m.main -o - | FileCheck %s --check-prefixes V81M-COMMON,V81M-BE
724+
725+@arr = hidden local_unnamed_addr global [256 x i32] zeroinitializer, align 4
726+
727+define i32 @access_i16(i16 signext %idx) "cmse_nonsecure_entry" {
728+; V8M-COMMON-LABEL: access_i16:
729+; V8M-COMMON: @ %bb.0: @ %entry
730+; V8M-COMMON-NEXT: movw r1, :lower16:arr
731+; V8M-COMMON-NEXT: sxth r0, r0
732+; V8M-COMMON-NEXT: movt r1, :upper16:arr
733+; V8M-COMMON-NEXT: mov r2, lr
734+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
735+; V8M-COMMON-NEXT: mov r1, lr
736+; V8M-COMMON-NEXT: mov r3, lr
737+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
738+; V8M-COMMON-NEXT: mov r12, lr
739+; V8M-COMMON-NEXT: bxns lr
740+;
741+; V81M-COMMON-LABEL: access_i16:
742+; V81M-COMMON: @ %bb.0: @ %entry
743+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
744+; V81M-COMMON-NEXT: movw r1, :lower16:arr
745+; V81M-COMMON-NEXT: sxth r0, r0
746+; V81M-COMMON-NEXT: movt r1, :upper16:arr
747+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
748+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
749+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
750+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
751+; V81M-COMMON-NEXT: bxns lr
752+entry:
753+ %idxprom = sext i16 %idx to i32
754+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
755+ %0 = load i32, ptr %arrayidx, align 4
756+ ret i32 %0
757+}
758+
759+define i32 @access_u16(i16 zeroext %idx) "cmse_nonsecure_entry" {
760+; V8M-COMMON-LABEL: access_u16:
761+; V8M-COMMON: @ %bb.0: @ %entry
762+; V8M-COMMON-NEXT: movw r1, :lower16:arr
763+; V8M-COMMON-NEXT: uxth r0, r0
764+; V8M-COMMON-NEXT: movt r1, :upper16:arr
765+; V8M-COMMON-NEXT: mov r2, lr
766+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
767+; V8M-COMMON-NEXT: mov r1, lr
768+; V8M-COMMON-NEXT: mov r3, lr
769+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
770+; V8M-COMMON-NEXT: mov r12, lr
771+; V8M-COMMON-NEXT: bxns lr
772+;
773+; V81M-COMMON-LABEL: access_u16:
774+; V81M-COMMON: @ %bb.0: @ %entry
775+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
776+; V81M-COMMON-NEXT: movw r1, :lower16:arr
777+; V81M-COMMON-NEXT: uxth r0, r0
778+; V81M-COMMON-NEXT: movt r1, :upper16:arr
779+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
780+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
781+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
782+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
783+; V81M-COMMON-NEXT: bxns lr
784+entry:
785+ %idxprom = zext i16 %idx to i32
786+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
787+ %0 = load i32, ptr %arrayidx, align 4
788+ ret i32 %0
789+}
790+
791+define i32 @access_i8(i8 signext %idx) "cmse_nonsecure_entry" {
792+; V8M-COMMON-LABEL: access_i8:
793+; V8M-COMMON: @ %bb.0: @ %entry
794+; V8M-COMMON-NEXT: movw r1, :lower16:arr
795+; V8M-COMMON-NEXT: sxtb r0, r0
796+; V8M-COMMON-NEXT: movt r1, :upper16:arr
797+; V8M-COMMON-NEXT: mov r2, lr
798+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
799+; V8M-COMMON-NEXT: mov r1, lr
800+; V8M-COMMON-NEXT: mov r3, lr
801+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
802+; V8M-COMMON-NEXT: mov r12, lr
803+; V8M-COMMON-NEXT: bxns lr
804+;
805+; V81M-COMMON-LABEL: access_i8:
806+; V81M-COMMON: @ %bb.0: @ %entry
807+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
808+; V81M-COMMON-NEXT: movw r1, :lower16:arr
809+; V81M-COMMON-NEXT: sxtb r0, r0
810+; V81M-COMMON-NEXT: movt r1, :upper16:arr
811+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
812+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
813+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
814+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
815+; V81M-COMMON-NEXT: bxns lr
816+entry:
817+ %idxprom = sext i8 %idx to i32
818+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
819+ %0 = load i32, ptr %arrayidx, align 4
820+ ret i32 %0
821+}
822+
823+define i32 @access_u8(i8 zeroext %idx) "cmse_nonsecure_entry" {
824+; V8M-COMMON-LABEL: access_u8:
825+; V8M-COMMON: @ %bb.0: @ %entry
826+; V8M-COMMON-NEXT: movw r1, :lower16:arr
827+; V8M-COMMON-NEXT: uxtb r0, r0
828+; V8M-COMMON-NEXT: movt r1, :upper16:arr
829+; V8M-COMMON-NEXT: mov r2, lr
830+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
831+; V8M-COMMON-NEXT: mov r1, lr
832+; V8M-COMMON-NEXT: mov r3, lr
833+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
834+; V8M-COMMON-NEXT: mov r12, lr
835+; V8M-COMMON-NEXT: bxns lr
836+;
837+; V81M-COMMON-LABEL: access_u8:
838+; V81M-COMMON: @ %bb.0: @ %entry
839+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
840+; V81M-COMMON-NEXT: movw r1, :lower16:arr
841+; V81M-COMMON-NEXT: uxtb r0, r0
842+; V81M-COMMON-NEXT: movt r1, :upper16:arr
843+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
844+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
845+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
846+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
847+; V81M-COMMON-NEXT: bxns lr
848+entry:
849+ %idxprom = zext i8 %idx to i32
850+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
851+ %0 = load i32, ptr %arrayidx, align 4
852+ ret i32 %0
853+}
854+
855+define i32 @access_i1(i1 signext %idx) "cmse_nonsecure_entry" {
856+; V8M-COMMON-LABEL: access_i1:
857+; V8M-COMMON: @ %bb.0: @ %entry
858+; V8M-COMMON-NEXT: and r0, r0, #1
859+; V8M-COMMON-NEXT: movw r1, :lower16:arr
860+; V8M-COMMON-NEXT: rsbs r0, r0, #0
861+; V8M-COMMON-NEXT: movt r1, :upper16:arr
862+; V8M-COMMON-NEXT: and r0, r0, #1
863+; V8M-COMMON-NEXT: mov r2, lr
864+; V8M-COMMON-NEXT: mov r3, lr
865+; V8M-COMMON-NEXT: mov r12, lr
866+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
867+; V8M-COMMON-NEXT: mov r1, lr
868+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
869+; V8M-COMMON-NEXT: bxns lr
870+;
871+; V81M-COMMON-LABEL: access_i1:
872+; V81M-COMMON: @ %bb.0: @ %entry
873+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
874+; V81M-COMMON-NEXT: and r0, r0, #1
875+; V81M-COMMON-NEXT: movw r1, :lower16:arr
876+; V81M-COMMON-NEXT: rsbs r0, r0, #0
877+; V81M-COMMON-NEXT: movt r1, :upper16:arr
878+; V81M-COMMON-NEXT: and r0, r0, #1
879+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
880+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
881+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
882+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
883+; V81M-COMMON-NEXT: bxns lr
884+entry:
885+ %idxprom = zext i1 %idx to i32
886+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
887+ %0 = load i32, ptr %arrayidx, align 4
888+ ret i32 %0
889+}
890+
891+define i32 @access_i5(i5 signext %idx) "cmse_nonsecure_entry" {
892+; V8M-COMMON-LABEL: access_i5:
893+; V8M-COMMON: @ %bb.0: @ %entry
894+; V8M-COMMON-NEXT: movw r1, :lower16:arr
895+; V8M-COMMON-NEXT: sbfx r0, r0, #0, #5
896+; V8M-COMMON-NEXT: movt r1, :upper16:arr
897+; V8M-COMMON-NEXT: mov r2, lr
898+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
899+; V8M-COMMON-NEXT: mov r1, lr
900+; V8M-COMMON-NEXT: mov r3, lr
901+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
902+; V8M-COMMON-NEXT: mov r12, lr
903+; V8M-COMMON-NEXT: bxns lr
904+;
905+; V81M-COMMON-LABEL: access_i5:
906+; V81M-COMMON: @ %bb.0: @ %entry
907+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
908+; V81M-COMMON-NEXT: movw r1, :lower16:arr
909+; V81M-COMMON-NEXT: sbfx r0, r0, #0, #5
910+; V81M-COMMON-NEXT: movt r1, :upper16:arr
911+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
912+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
913+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
914+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
915+; V81M-COMMON-NEXT: bxns lr
916+entry:
917+ %idxprom = sext i5 %idx to i32
918+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
919+ %0 = load i32, ptr %arrayidx, align 4
920+ ret i32 %0
921+}
922+
923+define i32 @access_u5(i5 zeroext %idx) "cmse_nonsecure_entry" {
924+; V8M-COMMON-LABEL: access_u5:
925+; V8M-COMMON: @ %bb.0: @ %entry
926+; V8M-COMMON-NEXT: movw r1, :lower16:arr
927+; V8M-COMMON-NEXT: and r0, r0, #31
928+; V8M-COMMON-NEXT: movt r1, :upper16:arr
929+; V8M-COMMON-NEXT: mov r2, lr
930+; V8M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
931+; V8M-COMMON-NEXT: mov r1, lr
932+; V8M-COMMON-NEXT: mov r3, lr
933+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
934+; V8M-COMMON-NEXT: mov r12, lr
935+; V8M-COMMON-NEXT: bxns lr
936+;
937+; V81M-COMMON-LABEL: access_u5:
938+; V81M-COMMON: @ %bb.0: @ %entry
939+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
940+; V81M-COMMON-NEXT: movw r1, :lower16:arr
941+; V81M-COMMON-NEXT: and r0, r0, #31
942+; V81M-COMMON-NEXT: movt r1, :upper16:arr
943+; V81M-COMMON-NEXT: ldr.w r0, [r1, r0, lsl #2]
944+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
945+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
946+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
947+; V81M-COMMON-NEXT: bxns lr
948+entry:
949+ %idxprom = zext i5 %idx to i32
950+ %arrayidx = getelementptr inbounds [256 x i32], ptr @arr, i32 0, i32 %idxprom
951+ %0 = load i32, ptr %arrayidx, align 4
952+ ret i32 %0
953+}
954+
955+define i32 @access_i33(i33 %arg) "cmse_nonsecure_entry" {
956+; V8M-COMMON-LABEL: access_i33:
957+; V8M-COMMON: @ %bb.0: @ %entry
958+; V8M-LE-NEXT: and r0, r1, #1
959+; V8M-BE-NEXT: and r0, r0, #1
960+; V8M-COMMON-NEXT: mov r1, lr
961+; V8M-COMMON-NEXT: rsbs r0, r0, #0
962+; V8M-COMMON-NEXT: mov r2, lr
963+; V8M-COMMON-NEXT: mov r3, lr
964+; V8M-COMMON-NEXT: mov r12, lr
965+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
966+; V8M-COMMON-NEXT: bxns lr
967+;
968+; V81M-COMMON-LABEL: access_i33:
969+; V81M-COMMON: @ %bb.0: @ %entry
970+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
971+; V81M-LE-NEXT: and r0, r1, #1
972+; V81M-BE-NEXT: and r0, r0, #1
973+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
974+; V81M-COMMON-NEXT: rsbs r0, r0, #0
975+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
976+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
977+; V81M-COMMON-NEXT: bxns lr
978+entry:
979+ %shr = ashr i33 %arg, 32
980+ %conv = trunc nsw i33 %shr to i32
981+ ret i32 %conv
982+}
983+
984+define i32 @access_u33(i33 %arg) "cmse_nonsecure_entry" {
985+; V8M-COMMON-LABEL: access_u33:
986+; V8M-COMMON: @ %bb.0: @ %entry
987+; V8M-LE-NEXT: and r0, r1, #1
988+; V8M-BE-NEXT: and r0, r0, #1
989+; V8M-COMMON-NEXT: mov r1, lr
990+; V8M-COMMON-NEXT: mov r2, lr
991+; V8M-COMMON-NEXT: mov r3, lr
992+; V8M-COMMON-NEXT: mov r12, lr
993+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
994+; V8M-COMMON-NEXT: bxns lr
995+;
996+; V81M-COMMON-LABEL: access_u33:
997+; V81M-COMMON: @ %bb.0: @ %entry
998+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
999+; V81M-LE-NEXT: and r0, r1, #1
1000+; V81M-BE-NEXT: and r0, r0, #1
1001+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
1002+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
1003+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
1004+; V81M-COMMON-NEXT: bxns lr
1005+entry:
1006+ %shr = lshr i33 %arg, 32
1007+ %conv = trunc nuw nsw i33 %shr to i32
1008+ ret i32 %conv
1009+}
1010+
1011+define i32 @access_i65(ptr byval(i65) %0) "cmse_nonsecure_entry" {
1012+; V8M-COMMON-LABEL: access_i65:
1013+; V8M-COMMON: @ %bb.0: @ %entry
1014+; V8M-COMMON-NEXT: sub sp, #16
1015+; V8M-COMMON-NEXT: stm.w sp, {r0, r1, r2, r3}
1016+; V8M-LE-NEXT: ldrb.w r0, [sp, #8]
1017+; V8M-LE-NEXT: and r0, r0, #1
1018+; V8M-LE-NEXT: rsbs r0, r0, #0
1019+; V8M-BE-NEXT: movs r1, #0
1020+; V8M-BE-NEXT: sub.w r0, r1, r0, lsr #24
1021+; V8M-COMMON-NEXT: add sp, #16
1022+; V8M-COMMON-NEXT: mov r1, lr
1023+; V8M-COMMON-NEXT: mov r2, lr
1024+; V8M-COMMON-NEXT: mov r3, lr
1025+; V8M-COMMON-NEXT: mov r12, lr
1026+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
1027+; V8M-COMMON-NEXT: bxns lr
1028+;
1029+; V81M-COMMON-LABEL: access_i65:
1030+; V81M-COMMON: @ %bb.0: @ %entry
1031+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
1032+; V81M-COMMON-NEXT: sub sp, #16
1033+; V81M-COMMON-NEXT: add sp, #4
1034+; V81M-COMMON-NEXT: stm.w sp, {r0, r1, r2, r3}
1035+; V81M-LE-NEXT: ldrb.w r0, [sp, #8]
1036+; V81M-LE-NEXT: and r0, r0, #1
1037+; V81M-LE-NEXT: rsbs r0, r0, #0
1038+; V81M-BE-NEXT: movs r1, #0
1039+; V81M-BE-NEXT: sub.w r0, r1, r0, lsr #24
1040+; V81M-COMMON-NEXT: sub sp, #4
1041+; V81M-COMMON-NEXT: add sp, #16
1042+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
1043+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
1044+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
1045+; V81M-COMMON-NEXT: bxns lr
1046+entry:
1047+ %arg = load i65, ptr %0, align 8
1048+ %shr = ashr i65 %arg, 64
1049+ %conv = trunc nsw i65 %shr to i32
1050+ ret i32 %conv
1051+}
1052+
1053+define i32 @access_u65(ptr byval(i65) %0) "cmse_nonsecure_entry" {
1054+; V8M-COMMON-LABEL: access_u65:
1055+; V8M-COMMON: @ %bb.0: @ %entry
1056+; V8M-COMMON-NEXT: sub sp, #16
1057+; V8M-COMMON-NEXT: stm.w sp, {r0, r1, r2, r3}
1058+; V8M-LE-NEXT: ldrb.w r0, [sp, #8]
1059+; V8M-BE-NEXT: lsrs r0, r0, #24
1060+; V8M-COMMON-NEXT: add sp, #16
1061+; V8M-COMMON-NEXT: mov r1, lr
1062+; V8M-COMMON-NEXT: mov r2, lr
1063+; V8M-COMMON-NEXT: mov r3, lr
1064+; V8M-COMMON-NEXT: mov r12, lr
1065+; V8M-COMMON-NEXT: msr apsr_nzcvq, lr
1066+; V8M-COMMON-NEXT: bxns lr
1067+;
1068+; V81M-COMMON-LABEL: access_u65:
1069+; V81M-COMMON: @ %bb.0: @ %entry
1070+; V81M-COMMON-NEXT: vstr fpcxtns, [sp, #-4]!
1071+; V81M-COMMON-NEXT: sub sp, #16
1072+; V81M-COMMON-NEXT: add sp, #4
1073+; V81M-COMMON-NEXT: stm.w sp, {r0, r1, r2, r3}
1074+; V81M-LE-NEXT: ldrb.w r0, [sp, #8]
1075+; V81M-BE-NEXT: lsrs r0, r0, #24
1076+; V81M-COMMON-NEXT: sub sp, #4
1077+; V81M-COMMON-NEXT: add sp, #16
1078+; V81M-COMMON-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
1079+; V81M-COMMON-NEXT: vldr fpcxtns, [sp], #4
1080+; V81M-COMMON-NEXT: clrm {r1, r2, r3, r12, apsr}
1081+; V81M-COMMON-NEXT: bxns lr
1082+entry:
1083+ %arg = load i65, ptr %0, align 8
1084+ %shr = lshr i65 %arg, 64
1085+ %conv = trunc nuw nsw i65 %shr to i32
1086+ ret i32 %conv
1087+}
diff --git a/meta/recipes-devtools/llvm/llvm_git.bb b/meta/recipes-devtools/llvm/llvm_git.bb
index 8dcd124c71..1531e12fff 100644
--- a/meta/recipes-devtools/llvm/llvm_git.bb
+++ b/meta/recipes-devtools/llvm/llvm_git.bb
@@ -36,6 +36,7 @@ SRC_URI = "git://github.com/llvm/llvm-project.git;branch=${BRANCH};protocol=http
36 file://CVE-2023-46049.patch;striplevel=2 \ 36 file://CVE-2023-46049.patch;striplevel=2 \
37 file://CVE-2024-31852-1.patch;striplevel=2 \ 37 file://CVE-2024-31852-1.patch;striplevel=2 \
38 file://CVE-2024-31852-2.patch;striplevel=2 \ 38 file://CVE-2024-31852-2.patch;striplevel=2 \
39 file://CVE-2024-0151.patch;striplevel=2 \
39 " 40 "
40 41
41UPSTREAM_CHECK_GITTAGREGEX = "llvmorg-(?P<pver>\d+(\.\d+)+)" 42UPSTREAM_CHECK_GITTAGREGEX = "llvmorg-(?P<pver>\d+(\.\d+)+)"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-01-08 20:47:47 +0000