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-rw-r--r--meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch13
1 files changed, 8 insertions, 5 deletions
diff --git a/meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch b/meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch
index cbe6f5bf3f..f5ef7e8d4f 100644
--- a/meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch
+++ b/meta/recipes-devtools/llvm/llvm/CVE-2024-0151.patch
@@ -32,6 +32,10 @@ Date: Thu Jun 20 10:22:01 2024 +0100
32Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/78ff617d3f573fb3a9b2fef180fa0fd43d5584ea] 32Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/78ff617d3f573fb3a9b2fef180fa0fd43d5584ea]
33CVE: CVE-2024-0151 33CVE: CVE-2024-0151
34Signed-off-by: Deepesh Varatharajan <Deepesh.Varatharajan@windriver.com> 34Signed-off-by: Deepesh Varatharajan <Deepesh.Varatharajan@windriver.com>
35
36Added back RegVT variable, which was accidentally removed during backporting.
37
38Signed-off-by: Gyorgy Sarvari <skandigraun@gmail.com>
35--- 39---
36diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp 40diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
37index 900113244e41..e12f8c183db2 100644 41index 900113244e41..e12f8c183db2 100644
@@ -98,16 +102,15 @@ index 900113244e41..e12f8c183db2 100644
98 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin(); 102 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
99 unsigned CurArgIdx = 0; 103 unsigned CurArgIdx = 0;
100 104
101@@ -4432,7 +4450,7 @@ SDValue ARMTargetLowering::LowerFormalArguments( 105@@ -4433,6 +4451,7 @@ SDValue ARMTargetLowering::LowerFormalArguments(
102 }
103 // Arguments stored in registers. 106 // Arguments stored in registers.
104 if (VA.isRegLoc()) { 107 if (VA.isRegLoc()) {
105- EVT RegVT = VA.getLocVT(); 108 EVT RegVT = VA.getLocVT();
106+ SDValue ArgValue; 109+ SDValue ArgValue;
107 110
108 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) { 111 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
109 // f64 and vector types are split up into multiple registers or 112 // f64 and vector types are split up into multiple registers or
110@@ -4496,16 +4514,6 @@ SDValue ARMTargetLowering::LowerFormalArguments( 113@@ -4496,16 +4515,6 @@ SDValue ARMTargetLowering::LowerFormalArguments(
111 case CCValAssign::BCvt: 114 case CCValAssign::BCvt:
112 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 115 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
113 break; 116 break;
@@ -124,7 +127,7 @@ index 900113244e41..e12f8c183db2 100644
124 } 127 }
125 128
126 // f16 arguments have their size extended to 4 bytes and passed as if they 129 // f16 arguments have their size extended to 4 bytes and passed as if they
127@@ -4515,6 +4523,15 @@ SDValue ARMTargetLowering::LowerFormalArguments( 130@@ -4515,6 +4524,15 @@ SDValue ARMTargetLowering::LowerFormalArguments(
128 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) 131 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
129 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue); 132 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
130 133