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authorKhem Raj <raj.khem@gmail.com>2019-10-03 04:22:48 (GMT)
committerRichard Purdie <richard.purdie@linuxfoundation.org>2019-10-08 10:22:24 (GMT)
commit66f27001ebfd3c8a13814e76b3d1ef1ef35f2dd9 (patch)
tree574198cd831b0c666446b2d581aa4c4568252d22 /meta/recipes-core
parent7a1d68d136c9746242d2243c7e9959758437a3fa (diff)
downloadpoky-66f27001ebfd3c8a13814e76b3d1ef1ef35f2dd9.tar.gz
musl: Update to latest
Drop upstream'ed patch Fix libgcc build with musl Detailed ChangeLog [1] [1] https://git.musl-libc.org/cgit/musl/log/?qt=range&q=1f0e9f9cc2e3fa354f94e18b3b362de5f1ec7272..2c2477da9a553c0b9b2fa18073a5dcdbe6d395af (From OE-Core rev: 88ab64956762cd51d953128262fd9bc0338a4488) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-core')
-rw-r--r--meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch67
-rw-r--r--meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch55
-rw-r--r--meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch48
-rw-r--r--meta/recipes-core/musl/musl_git.bb5
4 files changed, 50 insertions, 125 deletions
diff --git a/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch b/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch
deleted file mode 100644
index a9abb18..0000000
--- a/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch
+++ /dev/null
@@ -1,67 +0,0 @@
1From 52a37610650e7366a398dd07393d3902d2f3faa3 Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Sat, 28 Sep 2019 12:19:57 -0700
4Subject: [PATCH] Change container for riscv floating-point state to __riscv_mc_fp_state
5
6Match the struct elements with glibc
7glibc also uses __riscv_mc prefix, some packages like gdb uses that
8
9Upstream-Status: Submitted [https://www.openwall.com/lists/musl/2019/09/28/1]
10Signed-off-by: Khem Raj <raj.khem@gmail.com>
11---
12 arch/riscv64/bits/signal.h | 18 +++++++++---------
13 arch/riscv64/bits/user.h | 2 +-
14 2 files changed, 10 insertions(+), 10 deletions(-)
15
16diff --git a/arch/riscv64/bits/signal.h b/arch/riscv64/bits/signal.h
17index 76d7ad80..aba7ab00 100644
18--- a/arch/riscv64/bits/signal.h
19+++ b/arch/riscv64/bits/signal.h
20@@ -13,25 +13,25 @@ typedef unsigned long greg_t;
21 typedef unsigned long gregset_t[32];
22
23 struct __riscv_mc_f_ext_state {
24- unsigned int f[32];
25- unsigned int fcsr;
26+ unsigned int __f[32];
27+ unsigned int __fcsr;
28 };
29
30 struct __riscv_mc_d_ext_state {
31- unsigned long long f[32];
32- unsigned int fcsr;
33+ unsigned long long __f[32];
34+ unsigned int __fcsr;
35 };
36
37 struct __riscv_mc_q_ext_state {
38- unsigned long long f[64] __attribute__((aligned(16)));
39- unsigned int fcsr;
40+ unsigned long long __f[64] __attribute__((aligned(16)));
41+ unsigned int __fcsr;
42 unsigned int reserved[3];
43 };
44
45 union __riscv_mc_fp_state {
46- struct __riscv_mc_f_ext_state f;
47- struct __riscv_mc_d_ext_state d;
48- struct __riscv_mc_q_ext_state q;
49+ struct __riscv_mc_f_ext_state __f;
50+ struct __riscv_mc_d_ext_state __d;
51+ struct __riscv_mc_q_ext_state __q;
52 };
53
54 typedef union __riscv_mc_fp_state fpregset_t;
55diff --git a/arch/riscv64/bits/user.h b/arch/riscv64/bits/user.h
56index d2e383b2..9918a2fe 100644
57--- a/arch/riscv64/bits/user.h
58+++ b/arch/riscv64/bits/user.h
59@@ -5,4 +5,4 @@ struct user_fpregs_struct {
60
61 #define ELF_NGREG 32
62 typedef unsigned long elf_greg_t, elf_gregset_t[ELF_NGREG];
63-typedef struct user_fpregs_struct elf_fpregset_t;
64+typedef union __riscv_mc_fp_state elf_fpregset_t;
65--
662.23.0
67
diff --git a/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch b/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch
deleted file mode 100644
index 09b71cb..0000000
--- a/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch
+++ /dev/null
@@ -1,55 +0,0 @@
1From 59f2954fcaacd9426827c69a729e2647cb9977e5 Mon Sep 17 00:00:00 2001
2From: Palmer Dabbelt <palmer@sifive.com>
3Date: Tue, 24 Sep 2019 20:30:15 -0700
4Subject: [PATCH] correct the operand specifiers in the riscv64 CAS routines
5
6The operand sepcifiers in a_cas and a_casp for riscv64 were incorrect:
7there's a backwards branch in the routine, so despite tmp being written
8at the end of the assembly fragment it cannot be allocated in one of the
9input registers because the input values may be needed for another trip
10around the loop.
11
12For code that follows the guarnteed forward progress requirements, he
13backwards branch is rarely taken: SiFive's hardware only fails a store
14conditional on execptional cases (ie, instruction cache misses inside
15the loop), and until recently a bug in QEMU allowed back-to-back
16store conditionals to succeed. The bug has been fixed in the latest
17QEMU release, but it turns out that the fix caused this latent bug in
18musl to manifest.
19
20Full disclosure: I haven't actually even compiled musl. I just guessed
21this would fix a bug introducted by the new QEMU behavior, Alistair
22(CC'd) actually checked it fixes the problem. The rest is just
23conjecture.
24
25Upstream-Status: Submitted
26Signed-off-by: Khem Raj <raj.khem@gmail.com>
27---
28 arch/riscv64/atomic_arch.h | 4 ++--
29 1 file changed, 2 insertions(+), 2 deletions(-)
30
31diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
32index c9765342..41ad4d04 100644
33--- a/arch/riscv64/atomic_arch.h
34+++ b/arch/riscv64/atomic_arch.h
35@@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int s)
36 " sc.w.aqrl %1, %4, (%2)\n"
37 " bnez %1, 1b\n"
38 "1:"
39- : "=&r"(old), "=r"(tmp)
40+ : "=&r"(old), "=&r"(tmp)
41 : "r"(p), "r"(t), "r"(s)
42 : "memory");
43 return old;
44@@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
45 " sc.d.aqrl %1, %4, (%2)\n"
46 " bnez %1, 1b\n"
47 "1:"
48- : "=&r"(old), "=r"(tmp)
49+ : "=&r"(old), "=&r"(tmp)
50 : "r"(p), "r"(t), "r"(s)
51 : "memory");
52 return old;
53--
542.23.0
55
diff --git a/meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch b/meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch
new file mode 100644
index 0000000..fcb324e
--- /dev/null
+++ b/meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch
@@ -0,0 +1,48 @@
1commit a0993f8f0f161423ecdcb754f282ffd2fe47a7b5
2Author: Rich Felker <dalias@aerifal.cx>
3Date: Wed Oct 2 09:28:03 2019 -0400
4
5 reintroduce riscv64 struct sigcontext
6
7 commit ab3eb89a8b83353cdaab12ed017a67a7730f90e9 removed it as part of
8 correcting the mcontext_t definition, but there is still code using
9 struct sigcontext and expecting the member names present in it, most
10 notably libgcc_eh. almost all such usage is incorrect, but bring back
11 struct sigcontext at least for now so as not to introduce regressions.
12
13Upstream-Status: Pending
14Signed-off-by: Khem Raj <raj.khem@gmail.com>
15diff --git a/arch/riscv64/bits/signal.h b/arch/riscv64/bits/signal.h
16index 03fe48c1..2ff4be30 100644
17--- a/arch/riscv64/bits/signal.h
18+++ b/arch/riscv64/bits/signal.h
19@@ -6,12 +6,6 @@
20 # define SIGSTKSZ 8192
21 #endif
22
23-#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
24-typedef unsigned long greg_t;
25-typedef unsigned long gregset_t[32];
26-typedef union __riscv_mc_fp_state fpregset_t;
27-#endif
28-
29 typedef unsigned long __riscv_mc_gp_state[32];
30
31 struct __riscv_mc_f_ext_state {
32@@ -41,6 +35,16 @@ typedef struct mcontext_t {
33 union __riscv_mc_fp_state __fpregs;
34 } mcontext_t;
35
36+#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
37+typedef unsigned long greg_t;
38+typedef unsigned long gregset_t[32];
39+typedef union __riscv_mc_fp_state fpregset_t;
40+struct sigcontext {
41+ gregset_t gregs;
42+ fpregset_t fpregs;
43+};
44+#endif
45+
46 struct sigaltstack {
47 void *ss_sp;
48 int ss_flags;
diff --git a/meta/recipes-core/musl/musl_git.bb b/meta/recipes-core/musl/musl_git.bb
index 13fd173..aacff79 100644
--- a/meta/recipes-core/musl/musl_git.bb
+++ b/meta/recipes-core/musl/musl_git.bb
@@ -4,7 +4,7 @@
4require musl.inc 4require musl.inc
5inherit linuxloader 5inherit linuxloader
6 6
7SRCREV = "1f0e9f9cc2e3fa354f94e18b3b362de5f1ec7272" 7SRCREV = "2c2477da9a553c0b9b2fa18073a5dcdbe6d395af"
8 8
9BASEVER = "1.1.23" 9BASEVER = "1.1.23"
10 10
@@ -15,8 +15,7 @@ PV = "${BASEVER}+git${SRCPV}"
15SRC_URI = "git://git.musl-libc.org/musl \ 15SRC_URI = "git://git.musl-libc.org/musl \
16 file://0001-Make-dynamic-linker-a-relative-symlink-to-libc.patch \ 16 file://0001-Make-dynamic-linker-a-relative-symlink-to-libc.patch \
17 file://0002-ldso-Use-syslibdir-and-libdir-as-default-pathes-to-l.patch \ 17 file://0002-ldso-Use-syslibdir-and-libdir-as-default-pathes-to-l.patch \
18 file://0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch \ 18 file://0001-riscv-Define-sigcontext-again.patch \
19 file://0001-Change-container-for-riscv-floating-point-state-to-_.patch \
20 " 19 "
21 20
22S = "${WORKDIR}/git" 21S = "${WORKDIR}/git"