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authorKhem Raj <raj.khem@gmail.com>2012-07-06 20:49:24 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2012-07-17 10:54:02 +0100
commit3cf4c8d3e94048b24c812f6a83ea84603c684e7a (patch)
tree260b3755be786244ee8b23ab8a0cde3aee1f09ea
parent656417a9901dbd27398b2adc0a32e7efd86542fb (diff)
downloadpoky-3cf4c8d3e94048b24c812f6a83ea84603c684e7a.tar.gz
gcc: Refresh support for fsl E5500/E6500
These patches are backport from gcc mainline they fix issues where eglibc was not compilable for e5500+ due to missing vector intrinsics It obsoletes the existing e5500 patch (From OE-Core rev: b440aeeceb8c2e9f412d98793fb1dd55ff9d73f5) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.7.inc7
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.7/define_insn_reservation.patch118
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.7/powerpc-e5500.patch469
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch752
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch713
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.7/rs6000-tables.patch135
6 files changed, 1723 insertions, 471 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.7.inc b/meta/recipes-devtools/gcc/gcc-4.7.inc
index 7a0d231bd8..35332b4c7e 100644
--- a/meta/recipes-devtools/gcc/gcc-4.7.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.7.inc
@@ -1,6 +1,6 @@
1require gcc-common.inc 1require gcc-common.inc
2 2
3PR = "r5" 3PR = "r6"
4 4
5# Third digit in PV should be incremented after a minor release 5# Third digit in PV should be incremented after a minor release
6# happens from this branch on gcc e.g. currently its 4.7.1 6# happens from this branch on gcc e.g. currently its 4.7.1
@@ -59,7 +59,10 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};protocol=http \
59 file://disable_relax_pic_calls_flag.patch \ 59 file://disable_relax_pic_calls_flag.patch \
60 file://COLLECT_GCC_OPTIONS.patch \ 60 file://COLLECT_GCC_OPTIONS.patch \
61 file://use-defaults.h-and-t-oe-in-B.patch \ 61 file://use-defaults.h-and-t-oe-in-B.patch \
62 file://powerpc-e5500.patch \ 62 file://ppc_with_cpu.patch \
63 file://ppce5500-e6500-support.patch \
64 file://rs6000-tables.patch \
65 file://define_insn_reservation.patch \
63 file://pr32219.patch \ 66 file://pr32219.patch \
64 file://fortran-cross-compile-hack.patch \ 67 file://fortran-cross-compile-hack.patch \
65 file://libgcc-sjlj-check.patch \ 68 file://libgcc-sjlj-check.patch \
diff --git a/meta/recipes-devtools/gcc/gcc-4.7/define_insn_reservation.patch b/meta/recipes-devtools/gcc/gcc-4.7/define_insn_reservation.patch
new file mode 100644
index 0000000000..2b0ff677fe
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.7/define_insn_reservation.patch
@@ -0,0 +1,118 @@
1Upstream-Status: Backport
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From aab806a131efe9706396692ecc67d324371e39bc Mon Sep 17 00:00:00 2001
5From: edmarwjr <edmarwjr@138bc75d-0d04-0410-961f-82ee72b054a4>
6Date: Fri, 22 Jun 2012 20:13:23 +0000
7Subject: [PATCH] 2012-06-22 Edmar Wienskoski <edmar@freescale.com>
8
9 * config/rs6000/rs6000.md (define_attr "type"): New type popcnt.
10 (popcntb<mode>2): Add attribute type popcnt.
11 (popcntd<mode>2): Ditto.
12 * config/rs6000/power4.md (define_insn_reservation): Add type popcnt.
13 * config/rs6000/power5.md (define_insn_reservation): Ditto.
14 * config/rs6000/power7.md (define_insn_reservation): Ditto.
15 * config/rs6000/476.md (define_insn_reservation): Ditto.
16 * config/rs6000/power6.md (define_insn_reservation): New
17 reservation for popcnt instructions.
18
19
20
21git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@188901 138bc75d-0d04-0410-961f-82ee72b054a4
22---
23 gcc/ChangeLog | 12 ++++++++++++
24 gcc/config/rs6000/476.md | 2 +-
25 gcc/config/rs6000/power5.md | 2 +-
26 gcc/config/rs6000/power6.md | 5 +++++
27 gcc/config/rs6000/power7.md | 2 +-
28 gcc/config/rs6000/rs6000.md | 10 +++++++---
29 6 files changed, 27 insertions(+), 6 deletions(-)
30
31Index: gcc-4_7-branch/gcc/config/rs6000/476.md
32===================================================================
33--- gcc-4_7-branch.orig/gcc/config/rs6000/476.md 2012-07-05 23:49:07.000000000 -0700
34+++ gcc-4_7-branch/gcc/config/rs6000/476.md 2012-07-06 19:50:30.078779999 -0700
35@@ -71,7 +71,7 @@
36 ppc476_i_pipe|ppc476_lj_pipe")
37
38 (define_insn_reservation "ppc476-complex-integer" 1
39- (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap")
40+ (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap,popcnt")
41 (eq_attr "cpu" "ppc476"))
42 "ppc476_issue,\
43 ppc476_i_pipe")
44Index: gcc-4_7-branch/gcc/config/rs6000/power5.md
45===================================================================
46--- gcc-4_7-branch.orig/gcc/config/rs6000/power5.md 2012-07-05 23:49:07.000000000 -0700
47+++ gcc-4_7-branch/gcc/config/rs6000/power5.md 2012-07-06 19:50:30.078779999 -0700
48@@ -142,7 +142,7 @@
49 ; Integer latency is 2 cycles
50 (define_insn_reservation "power5-integer" 2
51 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
52- var_shift_rotate,cntlz,exts,isel")
53+ var_shift_rotate,cntlz,exts,isel,popcnt")
54 (eq_attr "cpu" "power5"))
55 "iq_power5")
56
57Index: gcc-4_7-branch/gcc/config/rs6000/power6.md
58===================================================================
59--- gcc-4_7-branch.orig/gcc/config/rs6000/power6.md 2012-07-05 23:49:07.000000000 -0700
60+++ gcc-4_7-branch/gcc/config/rs6000/power6.md 2012-07-06 19:50:30.078779999 -0700
61@@ -216,6 +216,11 @@
62 (eq_attr "cpu" "power6"))
63 "FXU_power6")
64
65+(define_insn_reservation "power6-popcnt" 1
66+ (and (eq_attr "type" "popcnt")
67+ (eq_attr "cpu" "power6"))
68+ "FXU_power6")
69+
70 (define_insn_reservation "power6-insert" 1
71 (and (eq_attr "type" "insert_word")
72 (eq_attr "cpu" "power6"))
73Index: gcc-4_7-branch/gcc/config/rs6000/power7.md
74===================================================================
75--- gcc-4_7-branch.orig/gcc/config/rs6000/power7.md 2012-07-05 23:49:07.000000000 -0700
76+++ gcc-4_7-branch/gcc/config/rs6000/power7.md 2012-07-06 19:50:30.078779999 -0700
77@@ -150,7 +150,7 @@
78 ; FX Unit
79 (define_insn_reservation "power7-integer" 1
80 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
81- var_shift_rotate,exts,isel")
82+ var_shift_rotate,exts,isel,popcnt")
83 (eq_attr "cpu" "power7"))
84 "DU_power7,FXU_power7")
85
86Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
87===================================================================
88--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:44:38.000000000 -0700
89+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:50:30.078779999 -0700
90@@ -144,7 +144,7 @@
91
92 ;; Define an insn type attribute. This is used in function unit delay
93 ;; computations.
94-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
95+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
96 (const_string "integer"))
97
98 ;; Define floating point instruction sub-types for use with Xfpu.md
99@@ -2329,13 +2329,17 @@
100 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
101 UNSPEC_POPCNTB))]
102 "TARGET_POPCNTB"
103- "popcntb %0,%1")
104+ "popcntb %0,%1"
105+ [(set_attr "length" "4")
106+ (set_attr "type" "popcnt")])
107
108 (define_insn "popcntd<mode>2"
109 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
110 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
111 "TARGET_POPCNTD"
112- "popcnt<wd> %0,%1")
113+ "popcnt<wd> %0,%1"
114+ [(set_attr "length" "4")
115+ (set_attr "type" "popcnt")])
116
117 (define_expand "popcount<mode>2"
118 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
diff --git a/meta/recipes-devtools/gcc/gcc-4.7/powerpc-e5500.patch b/meta/recipes-devtools/gcc/gcc-4.7/powerpc-e5500.patch
deleted file mode 100644
index 1c9736b326..0000000000
--- a/meta/recipes-devtools/gcc/gcc-4.7/powerpc-e5500.patch
+++ /dev/null
@@ -1,469 +0,0 @@
1Upstream-Status: Pending
2
3Implements basic e5500 enablement in gcc, with a scheduler, -mcpu
4flag, etc...
5
6Also splits the masks for popcntb, popcntd, and cmpb. Originally those
7masks would also control other instructions that e5500 does not
8support (so, we either get none or all).
9
10For the lack of means to do tests, those instructions were never
11enabled until now. The new instructions enabled with this patch are:
12popcntb, popcntw, popcntd, bpermd, prtyw, prtyd, cmpb, ldbrx, and
13stdbrx.
14
15Signed-off-by: Edmar Wienskoski <edmar@freescale.com>
16Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
17
18Index: gcc-4_7-branch/gcc/config.gcc
19===================================================================
20--- gcc-4_7-branch.orig/gcc/config.gcc 2012-04-10 10:32:36.823374222 -0700
21+++ gcc-4_7-branch/gcc/config.gcc 2012-04-10 10:39:32.543394369 -0700
22@@ -413,7 +413,7 @@
23 extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
24 need_64bit_hwint=yes
25 case x$with_cpu in
26- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64)
27+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500)
28 cpu_is_64bit=yes
29 ;;
30 esac
31@@ -3342,7 +3342,7 @@
32 | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
33 | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
34 | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
35- | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\
36+ | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | titan\
37 | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
38 # OK
39 ;;
40Index: gcc-4_7-branch/gcc/config/rs6000/e5500.md
41===================================================================
42--- /dev/null 1970-01-01 00:00:00.000000000 +0000
43+++ gcc-4_7-branch/gcc/config/rs6000/e5500.md 2012-04-10 10:39:32.543394369 -0700
44@@ -0,0 +1,176 @@
45+;; Pipeline description for Freescale PowerPC e5500 core.
46+;; Copyright (C) 2011 Free Software Foundation, Inc.
47+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
48+;;
49+;; This file is part of GCC.
50+;;
51+;; GCC is free software; you can redistribute it and/or modify it
52+;; under the terms of the GNU General Public License as published
53+;; by the Free Software Foundation; either version 3, or (at your
54+;; option) any later version.
55+;;
56+;; GCC is distributed in the hope that it will be useful, but WITHOUT
57+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
58+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
59+;; License for more details.
60+;;
61+;; You should have received a copy of the GNU General Public License
62+;; along with GCC; see the file COPYING3. If not see
63+;; <http://www.gnu.org/licenses/>.
64+;;
65+;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
66+;; Max issue 3 insns/clock cycle (includes 1 branch)
67+
68+(define_automaton "e5500_most,e5500_long")
69+(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
70+
71+;; SFX.
72+(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
73+
74+;; CFX.
75+(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
76+
77+;; Non-pipelined division.
78+(define_cpu_unit "e5500_cfx_div" "e5500_long")
79+
80+;; LSU.
81+(define_cpu_unit "e5500_lsu" "e5500_most")
82+
83+;; FPU.
84+(define_cpu_unit "e5500_fpu" "e5500_long")
85+
86+;; BU.
87+(define_cpu_unit "e5500_bu" "e5500_most")
88+
89+;; The following units are used to make the automata deterministic.
90+(define_cpu_unit "present_e5500_decode_0" "e5500_most")
91+(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
92+(presence_set "present_e5500_decode_0" "e5500_decode_0")
93+(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
94+
95+;; Some useful abbreviations.
96+(define_reservation "e5500_decode"
97+ "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
98+(define_reservation "e5500_sfx"
99+ "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
100+
101+;; SFX.
102+(define_insn_reservation "e5500_sfx" 1
103+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
104+ shift,cntlz,exts")
105+ (eq_attr "cpu" "ppce5500"))
106+ "e5500_decode,e5500_sfx")
107+
108+(define_insn_reservation "e5500_sfx2" 2
109+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
110+ (eq_attr "cpu" "ppce5500"))
111+ "e5500_decode,e5500_sfx")
112+
113+(define_insn_reservation "e5500_delayed" 2
114+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt")
115+ (eq_attr "cpu" "ppce5500"))
116+ "e5500_decode,e5500_sfx*2")
117+
118+(define_insn_reservation "e5500_two" 2
119+ (and (eq_attr "type" "two")
120+ (eq_attr "cpu" "ppce5500"))
121+ "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
122+
123+(define_insn_reservation "e5500_three" 3
124+ (and (eq_attr "type" "three")
125+ (eq_attr "cpu" "ppce5500"))
126+ "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
127+
128+;; SFX - Mfcr.
129+(define_insn_reservation "e5500_mfcr" 4
130+ (and (eq_attr "type" "mfcr")
131+ (eq_attr "cpu" "ppce5500"))
132+ "e5500_decode,e5500_sfx_0*4")
133+
134+;; SFX - Mtcrf.
135+(define_insn_reservation "e5500_mtcrf" 1
136+ (and (eq_attr "type" "mtcr")
137+ (eq_attr "cpu" "ppce5500"))
138+ "e5500_decode,e5500_sfx_0")
139+
140+;; SFX - Mtjmpr.
141+(define_insn_reservation "e5500_mtjmpr" 1
142+ (and (eq_attr "type" "mtjmpr,mfjmpr")
143+ (eq_attr "cpu" "ppce5500"))
144+ "e5500_decode,e5500_sfx")
145+
146+;; CFX - Multiply.
147+(define_insn_reservation "e5500_multiply" 4
148+ (and (eq_attr "type" "imul")
149+ (eq_attr "cpu" "ppce5500"))
150+ "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
151+
152+(define_insn_reservation "e5500_multiply_i" 5
153+ (and (eq_attr "type" "imul2,imul3,imul_compare")
154+ (eq_attr "cpu" "ppce5500"))
155+ "e5500_decode,e5500_cfx_stage0,\
156+ e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
157+
158+;; CFX - Divide.
159+(define_insn_reservation "e5500_divide" 16
160+ (and (eq_attr "type" "idiv")
161+ (eq_attr "cpu" "ppce5500"))
162+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
163+ e5500_cfx_div*15")
164+
165+(define_insn_reservation "e5500_divide_d" 26
166+ (and (eq_attr "type" "ldiv")
167+ (eq_attr "cpu" "ppce5500"))
168+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
169+ e5500_cfx_div*25")
170+
171+;; LSU - Loads.
172+(define_insn_reservation "e5500_load" 3
173+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
174+ load_l,sync")
175+ (eq_attr "cpu" "ppce5500"))
176+ "e5500_decode,e5500_lsu")
177+
178+(define_insn_reservation "e5500_fpload" 4
179+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
180+ (eq_attr "cpu" "ppce5500"))
181+ "e5500_decode,e5500_lsu")
182+
183+;; LSU - Stores.
184+(define_insn_reservation "e5500_store" 3
185+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
186+ (eq_attr "cpu" "ppce5500"))
187+ "e5500_decode,e5500_lsu")
188+
189+(define_insn_reservation "e5500_fpstore" 3
190+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
191+ (eq_attr "cpu" "ppce5500"))
192+ "e5500_decode,e5500_lsu")
193+
194+;; FP.
195+(define_insn_reservation "e5500_float" 7
196+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
197+ (eq_attr "cpu" "ppce5500"))
198+ "e5500_decode,e5500_fpu")
199+
200+(define_insn_reservation "e5500_sdiv" 20
201+ (and (eq_attr "type" "sdiv")
202+ (eq_attr "cpu" "ppce5500"))
203+ "e5500_decode,e5500_fpu*20")
204+
205+(define_insn_reservation "e5500_ddiv" 35
206+ (and (eq_attr "type" "ddiv")
207+ (eq_attr "cpu" "ppce5500"))
208+ "e5500_decode,e5500_fpu*35")
209+
210+;; BU.
211+(define_insn_reservation "e5500_branch" 1
212+ (and (eq_attr "type" "jmpreg,branch,isync")
213+ (eq_attr "cpu" "ppce5500"))
214+ "e5500_decode,e5500_bu")
215+
216+;; BU - CR logical.
217+(define_insn_reservation "e5500_cr_logical" 1
218+ (and (eq_attr "type" "cr_logical,delayed_cr")
219+ (eq_attr "cpu" "ppce5500"))
220+ "e5500_decode,e5500_bu")
221Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h
222===================================================================
223--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-opts.h 2012-04-10 10:17:24.283330056 -0700
224+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h 2012-04-10 10:39:32.543394369 -0700
225@@ -53,6 +53,7 @@
226 PROCESSOR_PPCE300C3,
227 PROCESSOR_PPCE500MC,
228 PROCESSOR_PPCE500MC64,
229+ PROCESSOR_PPCE5500,
230 PROCESSOR_POWER4,
231 PROCESSOR_POWER5,
232 PROCESSOR_POWER6,
233Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.c
234===================================================================
235--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.c 2012-04-10 10:17:24.263330055 -0700
236+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.c 2012-04-10 10:39:32.547394389 -0700
237@@ -755,6 +755,25 @@
238 1, /* prefetch streams /*/
239 };
240
241+/* Instruction costs on PPCE5500 processors. */
242+static const
243+struct processor_costs ppce5500_cost = {
244+ COSTS_N_INSNS (5), /* mulsi */
245+ COSTS_N_INSNS (5), /* mulsi_const */
246+ COSTS_N_INSNS (5), /* mulsi_const9 */
247+ COSTS_N_INSNS (5), /* muldi */
248+ COSTS_N_INSNS (14), /* divsi */
249+ COSTS_N_INSNS (14), /* divdi */
250+ COSTS_N_INSNS (7), /* fp */
251+ COSTS_N_INSNS (10), /* dmul */
252+ COSTS_N_INSNS (36), /* sdiv */
253+ COSTS_N_INSNS (66), /* ddiv */
254+ 64, /* cache line size */
255+ 32, /* l1 cache */
256+ 128, /* l2 cache */
257+ 1, /* prefetch streams /*/
258+};
259+
260 /* Instruction costs on AppliedMicro Titan processors. */
261 static const
262 struct processor_costs titan_cost = {
263@@ -2704,7 +2723,8 @@
264 rs6000_cpu = processor_target_table[tune_index].processor;
265
266 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
267- || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
268+ || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
269+ || rs6000_cpu == PROCESSOR_PPCE5500)
270 {
271 if (TARGET_ALTIVEC)
272 error ("AltiVec not supported in this target");
273@@ -2805,9 +2825,14 @@
274 user's opinion, though. */
275 if (rs6000_block_move_inline_limit == 0
276 && (rs6000_cpu == PROCESSOR_PPCE500MC
277- || rs6000_cpu == PROCESSOR_PPCE500MC64))
278+ || rs6000_cpu == PROCESSOR_PPCE500MC64
279+ || rs6000_cpu == PROCESSOR_PPCE5500))
280 rs6000_block_move_inline_limit = 128;
281
282+ /* Those machines does not have fsqrt instruction */
283+ if (rs6000_cpu == PROCESSOR_PPCE5500)
284+ target_flags &= ~MASK_PPC_GPOPT;
285+
286 /* store_one_arg depends on expand_block_move to handle at least the
287 size of reg_parm_stack_space. */
288 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
289@@ -2939,7 +2964,8 @@
290 #endif
291
292 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
293- || rs6000_cpu == PROCESSOR_PPCE500MC64)
294+ || rs6000_cpu == PROCESSOR_PPCE500MC64
295+ || rs6000_cpu == PROCESSOR_PPCE5500)
296 {
297 /* The e500 and e500mc do not have string instructions, and we set
298 MASK_STRING above when optimizing for size. */
299@@ -2987,7 +3013,8 @@
300 || rs6000_cpu == PROCESSOR_POWER6
301 || rs6000_cpu == PROCESSOR_POWER7
302 || rs6000_cpu == PROCESSOR_PPCE500MC
303- || rs6000_cpu == PROCESSOR_PPCE500MC64);
304+ || rs6000_cpu == PROCESSOR_PPCE500MC64
305+ || rs6000_cpu == PROCESSOR_PPCE5500);
306
307 /* Allow debug switches to override the above settings. These are set to -1
308 in rs6000.opt to indicate the user hasn't directly set the switch. */
309@@ -3209,6 +3236,10 @@
310 rs6000_cost = &ppce500mc64_cost;
311 break;
312
313+ case PROCESSOR_PPCE5500:
314+ rs6000_cost = &ppce5500_cost;
315+ break;
316+
317 case PROCESSOR_TITAN:
318 rs6000_cost = &titan_cost;
319 break;
320@@ -22295,6 +22326,7 @@
321 || rs6000_cpu_attr == CPU_PPC750
322 || rs6000_cpu_attr == CPU_PPC7400
323 || rs6000_cpu_attr == CPU_PPC7450
324+ || rs6000_cpu_attr == CPU_PPCE5500
325 || rs6000_cpu_attr == CPU_POWER4
326 || rs6000_cpu_attr == CPU_POWER5
327 || rs6000_cpu_attr == CPU_POWER7
328@@ -22839,6 +22871,7 @@
329 case CPU_PPCE300C3:
330 case CPU_PPCE500MC:
331 case CPU_PPCE500MC64:
332+ case CPU_PPCE5500:
333 case CPU_TITAN:
334 return 2;
335 case CPU_RIOS2:
336Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.h
337===================================================================
338--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.h 2012-04-10 10:17:24.251330055 -0700
339+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.h 2012-04-10 10:39:32.551394375 -0700
340@@ -168,6 +168,7 @@
341 %{mcpu=e300c3: -me300} \
342 %{mcpu=e500mc: -me500mc} \
343 %{mcpu=e500mc64: -me500mc64} \
344+%{mcpu=e5500: -me5500} \
345 %{maltivec: -maltivec} \
346 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
347 -many"
348@@ -475,13 +476,13 @@
349
350 #define TARGET_FCTIDZ TARGET_FCFID
351 #define TARGET_STFIWX TARGET_PPC_GFXOPT
352-#define TARGET_LFIWAX TARGET_CMPB
353-#define TARGET_LFIWZX TARGET_POPCNTD
354-#define TARGET_FCFIDS TARGET_POPCNTD
355-#define TARGET_FCFIDU TARGET_POPCNTD
356-#define TARGET_FCFIDUS TARGET_POPCNTD
357-#define TARGET_FCTIDUZ TARGET_POPCNTD
358-#define TARGET_FCTIWUZ TARGET_POPCNTD
359+#define TARGET_LFIWAX (TARGET_CMPB && rs6000_cpu != PROCESSOR_PPCE5500)
360+#define TARGET_LFIWZX (TARGET_POPCNTD && rs6000_cpu != PROCESSOR_PPCE5500)
361+#define TARGET_FCFIDS TARGET_LFIWZX
362+#define TARGET_FCFIDU TARGET_LFIWZX
363+#define TARGET_FCFIDUS TARGET_LFIWZX
364+#define TARGET_FCTIDUZ TARGET_LFIWZX
365+#define TARGET_FCTIWUZ TARGET_LFIWZX
366
367 /* For power systems, we want to enable Altivec and VSX builtins even if the
368 user did not use -maltivec or -mvsx to allow the builtins to be used inside
369@@ -510,10 +511,12 @@
370
371 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
372 && TARGET_DOUBLE_FLOAT \
373- && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
374+ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) \
375+ && rs6000_cpu != PROCESSOR_PPCE5500)
376
377 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
378- && TARGET_FPRS && TARGET_SINGLE_FLOAT)
379+ && TARGET_FPRS && TARGET_SINGLE_FLOAT \
380+ && rs6000_cpu != PROCESSOR_PPCE5500)
381
382 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
383 && TARGET_DOUBLE_FLOAT \
384Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
385===================================================================
386--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-04-10 10:17:24.275330056 -0700
387+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-04-10 10:39:32.555394355 -0700
388@@ -144,7 +144,7 @@
389
390 ;; Define an insn type attribute. This is used in function unit delay
391 ;; computations.
392-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
393+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
394 (const_string "integer"))
395
396 ;; Define floating point instruction sub-types for use with Xfpu.md
397@@ -166,7 +166,7 @@
398 ;; Processor type -- this attribute must exactly match the processor_type
399 ;; enumeration in rs6000.h.
400
401-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
402+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,power4,power5,power6,power7,cell,ppca2,titan"
403 (const (symbol_ref "rs6000_cpu_attr")))
404
405
406@@ -194,6 +194,7 @@
407 (include "e300c2c3.md")
408 (include "e500mc.md")
409 (include "e500mc64.md")
410+(include "e5500.md")
411 (include "power4.md")
412 (include "power5.md")
413 (include "power6.md")
414@@ -2329,13 +2330,17 @@
415 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
416 UNSPEC_POPCNTB))]
417 "TARGET_POPCNTB"
418- "popcntb %0,%1")
419+ "popcntb %0,%1"
420+ [(set_attr "length" "4")
421+ (set_attr "type" "popcnt")])
422
423 (define_insn "popcntd<mode>2"
424 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
425 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
426 "TARGET_POPCNTD"
427- "popcnt<wd> %0,%1")
428+ "popcnt<wd> %0,%1"
429+ [(set_attr "length" "4")
430+ (set_attr "type" "popcnt")])
431
432 (define_expand "popcount<mode>2"
433 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
434@@ -5984,10 +5989,10 @@
435 && ((TARGET_PPC_GFXOPT
436 && !HONOR_NANS (<MODE>mode)
437 && !HONOR_SIGNED_ZEROS (<MODE>mode))
438- || TARGET_CMPB
439+ || TARGET_LFIWAX
440 || VECTOR_UNIT_VSX_P (<MODE>mode))"
441 {
442- if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
443+ if (TARGET_LFIWAX || VECTOR_UNIT_VSX_P (<MODE>mode))
444 {
445 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
446 operands[2]));
447@@ -6006,7 +6011,7 @@
448 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
449 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
450 UNSPEC_COPYSIGN))]
451- "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
452+ "TARGET_LFIWAX && !VECTOR_UNIT_VSX_P (<MODE>mode)"
453 "fcpsgn %0,%2,%1"
454 [(set_attr "type" "fp")])
455
456Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def
457===================================================================
458--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-cpus.def 2012-04-10 10:17:24.295330058 -0700
459+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def 2012-04-10 10:39:32.555394355 -0700
460@@ -88,6 +88,9 @@
461 | MASK_ISEL)
462 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
463 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
464+RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
465+ POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL
466+ | MASK_CMPB | MASK_POPCNTB | MASK_POPCNTD)
467 RS6000_CPU ("860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
468 RS6000_CPU ("970", PROCESSOR_POWER4,
469 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
diff --git a/meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch b/meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch
new file mode 100644
index 0000000000..5ca12a6848
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch
@@ -0,0 +1,752 @@
1Upstream-Status: Backport
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From 7630308303ea21c318bd57c35590fc4f249a30d8 Mon Sep 17 00:00:00 2001
5From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4>
6Date: Wed, 16 May 2012 08:43:41 +0000
7Subject: [PATCH] * config/rs6000/rs6000-opts.h (enum processor_type):
8 Add PROCESSOR_PPC8548. *
9 config/rs6000/rs6000-cpus.def: Reference it for cpu="8548".
10 * config/rs6000/rs6000.md (cpu attribute
11 definition): Add ppc8548. * config/rs6000/8540.md:
12 indicate that the units/patterns apply to ppc8548
13 as well.
14
15 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
16 default_cpu into implicit_cpu, conveying what --with-cpu was passed at
17 configure time. Treat implicit_cpu as have_CPU. Pick defaults for SPE
18 related flags, check that what is queried is supported by the selected
19 configuration. Rework the single/double_float and MASK_STRING resets to
20 hit for all the E500 cores (854x + E500MC variants). Select the ppc8540
21 costs for PROCESSOR_PPC8548 as well.
22 (rs6000_issue_rate): case CPU_PPC8548 together with CPU_PPC8540.
23 (rs6000_use_sched_lookahead): Likewise, rewriting function as a case
24 statement instead of a sequence of ifs.
25
26 * config/rs6000/rs6000.h (TARGET_E500): Remove.
27 (TARGET_NO_LWSYNC): Adjust accordingly.
28 * config/rs6000/e500.h (TARGET_E500): Remove.
29 (CHECK_E500_OPTIONS): Adjust accordingly.
30 * config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Remove.
31 (TARGET_DEFAULT): Reformat definition to match the one in linuxspe.h.
32 * config/rs6000/linuxspe.h: Likewise.
33 * config/rs6000/vxworks.h: Remove bogus TARGET_E500 overrides and
34 superfluous comments.
35 * config/rs6000/e500-double.h: Remove.
36
37 * config.gcc (pick a default with_cpu): For powerpc*-*-*spe*,
38 default to with_cpu=8548 if --enable-e500-double, and to 8540
39 otherwise.
40 (set misc flags section): For powerpc*|rs6000*, remove inclusion
41 of e500-double.h for --enable-e500-double.
42
43
44
45git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187581 138bc75d-0d04-0410-961f-82ee72b054a4
46---
47 gcc/ChangeLog | 37 +++++++++
48 gcc/config.gcc | 12 +--
49 gcc/config/rs6000/8540.md | 50 ++++++------
50 gcc/config/rs6000/e500-double.h | 24 ------
51 gcc/config/rs6000/e500.h | 10 +--
52 gcc/config/rs6000/eabispe.h | 17 +---
53 gcc/config/rs6000/linuxspe.h | 16 +---
54 gcc/config/rs6000/rs6000-cpus.def | 3 +-
55 gcc/config/rs6000/rs6000-opts.h | 1 +
56 gcc/config/rs6000/rs6000.c | 155 +++++++++++++++++++++++--------------
57 gcc/config/rs6000/rs6000.h | 7 +-
58 gcc/config/rs6000/rs6000.md | 2 +-
59 gcc/config/rs6000/rtems.h | 14 ----
60 gcc/config/rs6000/vxworks.h | 11 ---
61 14 files changed, 178 insertions(+), 181 deletions(-)
62
63Index: gcc-4_7-branch/gcc/config.gcc
64===================================================================
65--- gcc-4_7-branch.orig/gcc/config.gcc 2012-07-06 19:43:53.000000000 -0700
66+++ gcc-4_7-branch/gcc/config.gcc 2012-07-06 19:44:38.000000000 -0700
67@@ -2876,6 +2876,13 @@
68 mips*-*-vxworks)
69 with_arch=mips2
70 ;;
71+ powerpc*-*-*spe*)
72+ if test x$enable_e500_double = xyes; then
73+ with_cpu=8548
74+ else
75+ with_cpu=8540
76+ fi
77+ ;;
78 sparc-leon*-*)
79 with_cpu=v8;
80 ;;
81@@ -3564,11 +3571,6 @@
82 c_target_objs="${c_target_objs} rs6000-c.o"
83 cxx_target_objs="${cxx_target_objs} rs6000-c.o"
84 tmake_file="rs6000/t-rs6000 ${tmake_file}"
85-
86- if test x$enable_e500_double = xyes
87- then
88- tm_file="$tm_file rs6000/e500-double.h"
89- fi
90 ;;
91
92 sh[123456ble]*-*-* | sh-*-*)
93Index: gcc-4_7-branch/gcc/config/rs6000/8540.md
94===================================================================
95--- gcc-4_7-branch.orig/gcc/config/rs6000/8540.md 2012-07-05 23:49:07.000000000 -0700
96+++ gcc-4_7-branch/gcc/config/rs6000/8540.md 2012-07-06 19:44:38.466780001 -0700
97@@ -87,18 +87,18 @@
98 (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
99 delayed_compare,var_delayed_compare,fast_compare,\
100 shift,trap,var_shift_rotate,cntlz,exts,isel")
101- (eq_attr "cpu" "ppc8540"))
102+ (eq_attr "cpu" "ppc8540,ppc8548"))
103 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
104
105 (define_insn_reservation "ppc8540_two" 1
106 (and (eq_attr "type" "two")
107- (eq_attr "cpu" "ppc8540"))
108+ (eq_attr "cpu" "ppc8540,ppc8548"))
109 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
110 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
111
112 (define_insn_reservation "ppc8540_three" 1
113 (and (eq_attr "type" "three")
114- (eq_attr "cpu" "ppc8540"))
115+ (eq_attr "cpu" "ppc8540,ppc8548"))
116 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
117 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
118 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
119@@ -106,13 +106,13 @@
120 ;; Branch. Actually this latency time is not used by the scheduler.
121 (define_insn_reservation "ppc8540_branch" 1
122 (and (eq_attr "type" "jmpreg,branch,isync")
123- (eq_attr "cpu" "ppc8540"))
124+ (eq_attr "cpu" "ppc8540,ppc8548"))
125 "ppc8540_decode,ppc8540_bu,ppc8540_retire")
126
127 ;; Multiply
128 (define_insn_reservation "ppc8540_multiply" 4
129 (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
130- (eq_attr "cpu" "ppc8540"))
131+ (eq_attr "cpu" "ppc8540,ppc8548"))
132 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
133 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
134
135@@ -122,57 +122,57 @@
136 ;; time.
137 (define_insn_reservation "ppc8540_divide" 14
138 (and (eq_attr "type" "idiv")
139- (eq_attr "cpu" "ppc8540"))
140+ (eq_attr "cpu" "ppc8540,ppc8548"))
141 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
142 ppc8540_mu_div*13")
143
144 ;; CR logical
145 (define_insn_reservation "ppc8540_cr_logical" 1
146 (and (eq_attr "type" "cr_logical,delayed_cr")
147- (eq_attr "cpu" "ppc8540"))
148+ (eq_attr "cpu" "ppc8540,ppc8548"))
149 "ppc8540_decode,ppc8540_bu,ppc8540_retire")
150
151 ;; Mfcr
152 (define_insn_reservation "ppc8540_mfcr" 1
153 (and (eq_attr "type" "mfcr")
154- (eq_attr "cpu" "ppc8540"))
155+ (eq_attr "cpu" "ppc8540,ppc8548"))
156 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
157
158 ;; Mtcrf
159 (define_insn_reservation "ppc8540_mtcrf" 1
160 (and (eq_attr "type" "mtcr")
161- (eq_attr "cpu" "ppc8540"))
162+ (eq_attr "cpu" "ppc8540,ppc8548"))
163 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
164
165 ;; Mtjmpr
166 (define_insn_reservation "ppc8540_mtjmpr" 1
167 (and (eq_attr "type" "mtjmpr,mfjmpr")
168- (eq_attr "cpu" "ppc8540"))
169+ (eq_attr "cpu" "ppc8540,ppc8548"))
170 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
171
172 ;; Loads
173 (define_insn_reservation "ppc8540_load" 3
174 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
175 load_l,sync")
176- (eq_attr "cpu" "ppc8540"))
177+ (eq_attr "cpu" "ppc8540,ppc8548"))
178 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
179
180 ;; Stores.
181 (define_insn_reservation "ppc8540_store" 3
182 (and (eq_attr "type" "store,store_ux,store_u,store_c")
183- (eq_attr "cpu" "ppc8540"))
184+ (eq_attr "cpu" "ppc8540,ppc8548"))
185 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
186
187 ;; Simple FP
188 (define_insn_reservation "ppc8540_simple_float" 1
189 (and (eq_attr "type" "fpsimple")
190- (eq_attr "cpu" "ppc8540"))
191+ (eq_attr "cpu" "ppc8540,ppc8548"))
192 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
193
194 ;; FP
195 (define_insn_reservation "ppc8540_float" 4
196 (and (eq_attr "type" "fp")
197- (eq_attr "cpu" "ppc8540"))
198+ (eq_attr "cpu" "ppc8540,ppc8548"))
199 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
200 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
201
202@@ -180,44 +180,44 @@
203 ;; because of the result automata will be huge.
204 (define_insn_reservation "ppc8540_float_vector_divide" 29
205 (and (eq_attr "type" "vecfdiv")
206- (eq_attr "cpu" "ppc8540"))
207+ (eq_attr "cpu" "ppc8540,ppc8548"))
208 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
209 ppc8540_mu_div*28")
210
211 ;; Brinc
212 (define_insn_reservation "ppc8540_brinc" 1
213 (and (eq_attr "type" "brinc")
214- (eq_attr "cpu" "ppc8540"))
215+ (eq_attr "cpu" "ppc8540,ppc8548"))
216 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
217
218 ;; Simple vector
219 (define_insn_reservation "ppc8540_simple_vector" 1
220 (and (eq_attr "type" "vecsimple")
221- (eq_attr "cpu" "ppc8540"))
222+ (eq_attr "cpu" "ppc8540,ppc8548"))
223 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
224
225 ;; Simple vector compare
226 (define_insn_reservation "ppc8540_simple_vector_compare" 1
227 (and (eq_attr "type" "veccmpsimple")
228- (eq_attr "cpu" "ppc8540"))
229+ (eq_attr "cpu" "ppc8540,ppc8548"))
230 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
231
232 ;; Vector compare
233 (define_insn_reservation "ppc8540_vector_compare" 1
234 (and (eq_attr "type" "veccmp")
235- (eq_attr "cpu" "ppc8540"))
236+ (eq_attr "cpu" "ppc8540,ppc8548"))
237 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
238
239 ;; evsplatfi evsplati
240 (define_insn_reservation "ppc8540_vector_perm" 1
241 (and (eq_attr "type" "vecperm")
242- (eq_attr "cpu" "ppc8540"))
243+ (eq_attr "cpu" "ppc8540,ppc8548"))
244 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
245
246 ;; Vector float
247 (define_insn_reservation "ppc8540_float_vector" 4
248 (and (eq_attr "type" "vecfloat")
249- (eq_attr "cpu" "ppc8540"))
250+ (eq_attr "cpu" "ppc8540,ppc8548"))
251 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
252 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
253
254@@ -226,25 +226,25 @@
255 ;; of miu_stage3 here because we use the average latency time.
256 (define_insn_reservation "ppc8540_vector_divide" 14
257 (and (eq_attr "type" "vecdiv")
258- (eq_attr "cpu" "ppc8540"))
259+ (eq_attr "cpu" "ppc8540,ppc8548"))
260 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
261 ppc8540_mu_div*13")
262
263 ;; Complex vector.
264 (define_insn_reservation "ppc8540_complex_vector" 4
265 (and (eq_attr "type" "veccomplex")
266- (eq_attr "cpu" "ppc8540"))
267+ (eq_attr "cpu" "ppc8540,ppc8548"))
268 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
269 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
270
271 ;; Vector load
272 (define_insn_reservation "ppc8540_vector_load" 3
273 (and (eq_attr "type" "vecload")
274- (eq_attr "cpu" "ppc8540"))
275+ (eq_attr "cpu" "ppc8540,ppc8548"))
276 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
277
278 ;; Vector store
279 (define_insn_reservation "ppc8540_vector_store" 3
280 (and (eq_attr "type" "vecstore")
281- (eq_attr "cpu" "ppc8540"))
282+ (eq_attr "cpu" "ppc8540,ppc8548"))
283 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
284Index: gcc-4_7-branch/gcc/config/rs6000/e500-double.h
285===================================================================
286--- gcc-4_7-branch.orig/gcc/config/rs6000/e500-double.h 2012-07-05 23:49:07.000000000 -0700
287+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
288@@ -1,24 +0,0 @@
289-/* Target definitions for E500 with double precision FP.
290- Copyright (C) 2004, 2006, 2007, 2011 Free Software Foundation, Inc.
291- Contributed by Aldy Hernandez (aldyh@redhat.com).
292-
293- This file is part of GCC.
294-
295- GCC is free software; you can redistribute it and/or modify it
296- under the terms of the GNU General Public License as published
297- by the Free Software Foundation; either version 3, or (at your
298- option) any later version.
299-
300- GCC is distributed in the hope that it will be useful, but WITHOUT
301- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
302- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
303- License for more details.
304-
305- You should have received a copy of the GNU General Public License
306- along with GCC; see the file COPYING3. If not see
307- <http://www.gnu.org/licenses/>. */
308-
309-#undef SUB3TARGET_OVERRIDE_OPTIONS
310-#define SUB3TARGET_OVERRIDE_OPTIONS \
311- if (!global_options_set.x_rs6000_float_gprs) \
312- rs6000_float_gprs = 2;
313Index: gcc-4_7-branch/gcc/config/rs6000/e500.h
314===================================================================
315--- gcc-4_7-branch.orig/gcc/config/rs6000/e500.h 2012-07-05 23:49:07.000000000 -0700
316+++ gcc-4_7-branch/gcc/config/rs6000/e500.h 2012-07-06 19:44:38.466780001 -0700
317@@ -19,7 +19,6 @@
318
319 #undef TARGET_SPE_ABI
320 #undef TARGET_SPE
321-#undef TARGET_E500
322 #undef TARGET_FPRS
323 #undef TARGET_E500_SINGLE
324 #undef TARGET_E500_DOUBLE
325@@ -27,21 +26,20 @@
326
327 #define TARGET_SPE_ABI rs6000_spe_abi
328 #define TARGET_SPE rs6000_spe
329-#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
330 #define TARGET_FPRS (rs6000_float_gprs == 0)
331 #define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
332 #define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
333 #define CHECK_E500_OPTIONS \
334 do { \
335- if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI \
336+ if (TARGET_SPE || TARGET_SPE_ABI \
337 || TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
338 { \
339 if (TARGET_ALTIVEC) \
340- error ("AltiVec and E500 instructions cannot coexist"); \
341+ error ("AltiVec and SPE instructions cannot coexist"); \
342 if (TARGET_VSX) \
343- error ("VSX and E500 instructions cannot coexist"); \
344+ error ("VSX and SPE instructions cannot coexist"); \
345 if (TARGET_64BIT) \
346- error ("64-bit E500 not supported"); \
347+ error ("64-bit SPE not supported"); \
348 if (TARGET_HARD_FLOAT && TARGET_FPRS) \
349 error ("E500 and FPRs not supported"); \
350 } \
351Index: gcc-4_7-branch/gcc/config/rs6000/eabispe.h
352===================================================================
353--- gcc-4_7-branch.orig/gcc/config/rs6000/eabispe.h 2012-07-05 23:49:07.000000000 -0700
354+++ gcc-4_7-branch/gcc/config/rs6000/eabispe.h 2012-07-06 19:44:38.466780001 -0700
355@@ -21,21 +21,8 @@
356 <http://www.gnu.org/licenses/>. */
357
358 #undef TARGET_DEFAULT
359-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI \
360- | MASK_STRICT_ALIGN)
361-
362-#undef SUBSUBTARGET_OVERRIDE_OPTIONS
363-#define SUBSUBTARGET_OVERRIDE_OPTIONS \
364- if (!global_options_set.x_rs6000_cpu_index) \
365- rs6000_cpu = PROCESSOR_PPC8540; \
366- if (!global_options_set.x_rs6000_spe_abi) \
367- rs6000_spe_abi = 1; \
368- if (!global_options_set.x_rs6000_float_gprs) \
369- rs6000_float_gprs = 1; \
370- if (!global_options_set.x_rs6000_spe) \
371- rs6000_spe = 1; \
372- if (target_flags & MASK_64BIT) \
373- error ("-m64 not supported in this configuration")
374+#define TARGET_DEFAULT \
375+ (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI)
376
377 #undef ASM_DEFAULT_SPEC
378 #define ASM_DEFAULT_SPEC "-mppc -mspe -me500"
379Index: gcc-4_7-branch/gcc/config/rs6000/linuxspe.h
380===================================================================
381--- gcc-4_7-branch.orig/gcc/config/rs6000/linuxspe.h 2012-07-05 23:52:14.000000000 -0700
382+++ gcc-4_7-branch/gcc/config/rs6000/linuxspe.h 2012-07-06 19:44:38.466780001 -0700
383@@ -22,20 +22,8 @@
384
385 /* Override rs6000.h and sysv4.h definition. */
386 #undef TARGET_DEFAULT
387-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN)
388-
389-#undef SUBSUBTARGET_OVERRIDE_OPTIONS
390-#define SUBSUBTARGET_OVERRIDE_OPTIONS \
391- if (!global_options_set.x_rs6000_cpu_index) \
392- rs6000_cpu = PROCESSOR_PPC8540; \
393- if (!global_options_set.x_rs6000_spe_abi) \
394- rs6000_spe_abi = 1; \
395- if (!global_options_set.x_rs6000_float_gprs) \
396- rs6000_float_gprs = 1; \
397- if (!global_options_set.x_rs6000_spe) \
398- rs6000_spe = 1; \
399- if (target_flags & MASK_64BIT) \
400- error ("-m64 not supported in this configuration")
401+#define TARGET_DEFAULT \
402+ (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN)
403
404 #undef ASM_DEFAULT_SPEC
405 #define ASM_DEFAULT_SPEC "-mppc -mspe -me500"
406Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def
407===================================================================
408--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:43:53.000000000 -0700
409+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:44:38.000000000 -0700
410@@ -76,8 +76,7 @@
411 RS6000_CPU ("823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
412 RS6000_CPU ("8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
413 | MASK_ISEL)
414-/* 8548 has a dummy entry for now. */
415-RS6000_CPU ("8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
416+RS6000_CPU ("8548", PROCESSOR_PPC8548, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
417 | MASK_ISEL)
418 RS6000_CPU ("a2", PROCESSOR_PPCA2,
419 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB
420Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h
421===================================================================
422--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:43:53.000000000 -0700
423+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:44:38.000000000 -0700
424@@ -49,6 +49,7 @@
425 PROCESSOR_PPC7400,
426 PROCESSOR_PPC7450,
427 PROCESSOR_PPC8540,
428+ PROCESSOR_PPC8548,
429 PROCESSOR_PPCE300C2,
430 PROCESSOR_PPCE300C3,
431 PROCESSOR_PPCE500MC,
432Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.c
433===================================================================
434--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.c 2012-07-06 19:43:53.194780001 -0700
435+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.c 2012-07-06 19:44:38.000000000 -0700
436@@ -2597,7 +2597,10 @@
437 {
438 bool ret = true;
439 bool have_cpu = false;
440- const char *default_cpu = OPTION_TARGET_CPU_DEFAULT;
441+
442+ /* The default cpu requested at configure time, if any. */
443+ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
444+
445 int set_masks;
446 int cpu_index;
447 int tune_index;
448@@ -2616,11 +2619,6 @@
449 warning (0, "-malign-power is not supported for 64-bit Darwin;"
450 " it is incompatible with the installed C and C++ libraries");
451
452- if (global_options_set.x_rs6000_spe_abi
453- && rs6000_spe_abi
454- && !TARGET_SPE_ABI)
455- error ("not configured for SPE ABI");
456-
457 /* Numerous experiment shows that IRA based loop pressure
458 calculation works better for RTL loop invariant motion on targets
459 with enough (>= 32) registers. It is an expensive optimization.
460@@ -2656,7 +2654,8 @@
461 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
462 the cpu in a target attribute or pragma, but did not specify a tuning
463 option, use the cpu for the tuning option rather than the option specified
464- with -mtune on the command line. */
465+ with -mtune on the command line. Process a '--with-cpu' configuration
466+ request as an implicit --cpu. */
467 if (rs6000_cpu_index >= 0)
468 {
469 cpu_index = rs6000_cpu_index;
470@@ -2669,10 +2668,12 @@
471 }
472 else
473 {
474- if (!default_cpu)
475- default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc");
476+ const char *default_cpu =
477+ (implicit_cpu ? implicit_cpu
478+ : (TARGET_POWERPC64 ? "powerpc64" : "powerpc"));
479
480 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
481+ have_cpu = implicit_cpu != 0;
482 }
483
484 gcc_assert (cpu_index >= 0);
485@@ -2703,6 +2704,42 @@
486 gcc_assert (tune_index >= 0);
487 rs6000_cpu = processor_target_table[tune_index].processor;
488
489+ /* Pick defaults for SPE related control flags. Do this early to make sure
490+ that the TARGET_ macros are representative ASAP. */
491+ {
492+ int spe_capable_cpu =
493+ (rs6000_cpu == PROCESSOR_PPC8540
494+ || rs6000_cpu == PROCESSOR_PPC8548);
495+
496+ if (!global_options_set.x_rs6000_spe_abi)
497+ rs6000_spe_abi = spe_capable_cpu;
498+
499+ if (!global_options_set.x_rs6000_spe)
500+ rs6000_spe = spe_capable_cpu;
501+
502+ if (!global_options_set.x_rs6000_float_gprs)
503+ rs6000_float_gprs =
504+ (rs6000_cpu == PROCESSOR_PPC8540 ? 1
505+ : rs6000_cpu == PROCESSOR_PPC8548 ? 2
506+ : 0);
507+ }
508+
509+ if (global_options_set.x_rs6000_spe_abi
510+ && rs6000_spe_abi
511+ && !TARGET_SPE_ABI)
512+ error ("not configured for SPE ABI");
513+
514+ if (global_options_set.x_rs6000_spe
515+ && rs6000_spe
516+ && !TARGET_SPE)
517+ error ("not configured for SPE instruction set");
518+
519+ if (main_target_opt != NULL
520+ && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
521+ || (main_target_opt->x_rs6000_spe != rs6000_spe)
522+ || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
523+ error ("target attribute or pragma changes SPE ABI");
524+
525 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
526 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
527 {
528@@ -2938,35 +2975,44 @@
529 SUB3TARGET_OVERRIDE_OPTIONS;
530 #endif
531
532- if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
533- || rs6000_cpu == PROCESSOR_PPCE500MC64)
534+ /* For the E500 family of cores, reset the single/double FP flags to let us
535+ check that they remain constant across attributes or pragmas. Also,
536+ clear a possible request for string instructions, not supported and which
537+ we might have silently queried above for -Os.
538+
539+ For other families, clear ISEL in case it was set implicitly.
540+ */
541+
542+ switch (rs6000_cpu)
543 {
544- /* The e500 and e500mc do not have string instructions, and we set
545- MASK_STRING above when optimizing for size. */
546- if ((target_flags & MASK_STRING) != 0)
547- target_flags = target_flags & ~MASK_STRING;
548- }
549- else if (global_options_set.x_rs6000_cpu_index)
550- {
551- /* For the powerpc-eabispe configuration, we set all these by
552- default, so let's unset them if we manually set another
553- CPU that is not the E500. */
554- if (main_target_opt != NULL
555- && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
556- || (main_target_opt->x_rs6000_spe != rs6000_spe)
557- || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
558- error ("target attribute or pragma changes SPE ABI");
559- else
560- {
561- if (!global_options_set.x_rs6000_spe_abi)
562- rs6000_spe_abi = 0;
563- if (!global_options_set.x_rs6000_spe)
564- rs6000_spe = 0;
565- if (!global_options_set.x_rs6000_float_gprs)
566- rs6000_float_gprs = 0;
567- }
568- if (!(target_flags_explicit & MASK_ISEL))
569+ case PROCESSOR_PPC8540:
570+ case PROCESSOR_PPC8548:
571+ case PROCESSOR_PPCE500MC:
572+ case PROCESSOR_PPCE500MC64:
573+
574+ rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
575+ rs6000_double_float = TARGET_E500_DOUBLE;
576+
577+ target_flags &= ~MASK_STRING;
578+
579+ break;
580+
581+ default:
582+
583+ if (have_cpu && !(target_flags_explicit & MASK_ISEL))
584 target_flags &= ~MASK_ISEL;
585+
586+ break;
587+ }
588+
589+ if (main_target_opt)
590+ {
591+ if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
592+ error ("target attribute or pragma changes single precision floating "
593+ "point");
594+ if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
595+ error ("target attribute or pragma changes double precision floating "
596+ "point");
597 }
598
599 /* Detect invalid option combinations with E500. */
600@@ -3193,6 +3239,7 @@
601 break;
602
603 case PROCESSOR_PPC8540:
604+ case PROCESSOR_PPC8548:
605 rs6000_cost = &ppc8540_cost;
606 break;
607
608@@ -3265,26 +3312,6 @@
609 && rs6000_single_float == 0 && rs6000_double_float == 0)
610 rs6000_single_float = rs6000_double_float = 1;
611
612- /* Reset single and double FP flags if target is E500. */
613- if (TARGET_E500)
614- {
615- rs6000_single_float = rs6000_double_float = 0;
616- if (TARGET_E500_SINGLE)
617- rs6000_single_float = 1;
618- if (TARGET_E500_DOUBLE)
619- rs6000_single_float = rs6000_double_float = 1;
620- }
621-
622- if (main_target_opt)
623- {
624- if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
625- error ("target attribute or pragma changes single precision floating "
626- "point");
627- if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
628- error ("target attribute or pragma changes double precision floating "
629- "point");
630- }
631-
632 /* If not explicitly specified via option, decide whether to generate indexed
633 load/store instructions. */
634 if (TARGET_AVOID_XFORM == -1)
635@@ -22816,6 +22843,7 @@
636 case CPU_PPC750:
637 case CPU_PPC7400:
638 case CPU_PPC8540:
639+ case CPU_PPC8548:
640 case CPU_CELL:
641 case CPU_PPCE300C2:
642 case CPU_PPCE300C3:
643@@ -22846,11 +22874,18 @@
644 static int
645 rs6000_use_sched_lookahead (void)
646 {
647- if (rs6000_cpu_attr == CPU_PPC8540)
648- return 4;
649- if (rs6000_cpu_attr == CPU_CELL)
650- return (reload_completed ? 8 : 0);
651- return 0;
652+ switch (rs6000_cpu_attr)
653+ {
654+ case CPU_PPC8540:
655+ case CPU_PPC8548:
656+ return 4;
657+
658+ case CPU_CELL:
659+ return (reload_completed ? 8 : 0);
660+
661+ default:
662+ return 0;
663+ }
664 }
665
666 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
667Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.h
668===================================================================
669--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.h 2012-07-06 19:43:53.000000000 -0700
670+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.h 2012-07-06 19:44:38.000000000 -0700
671@@ -457,7 +457,6 @@
672
673 #define TARGET_SPE_ABI 0
674 #define TARGET_SPE 0
675-#define TARGET_E500 0
676 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
677 #define TARGET_FPRS 1
678 #define TARGET_E500_SINGLE 0
679@@ -500,11 +499,11 @@
680 || TARGET_ALTIVEC \
681 || TARGET_VSX)))
682
683+/* E500 cores only support plain "sync", not lwsync. */
684+#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
685+ || rs6000_cpu == PROCESSOR_PPC8548)
686
687
688-/* E500 processors only support plain "sync", not lwsync. */
689-#define TARGET_NO_LWSYNC TARGET_E500
690-
691 /* Which machine supports the various reciprocal estimate instructions. */
692 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
693 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
694Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
695===================================================================
696--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:43:53.000000000 -0700
697+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:44:38.000000000 -0700
698@@ -166,7 +166,7 @@
699 ;; Processor type -- this attribute must exactly match the processor_type
700 ;; enumeration in rs6000.h.
701
702-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
703+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
704 (const (symbol_ref "rs6000_cpu_attr")))
705
706
707Index: gcc-4_7-branch/gcc/config/rs6000/rtems.h
708===================================================================
709--- gcc-4_7-branch.orig/gcc/config/rs6000/rtems.h 2012-07-05 23:49:07.000000000 -0700
710+++ gcc-4_7-branch/gcc/config/rs6000/rtems.h 2012-07-06 19:44:38.470780001 -0700
711@@ -55,17 +55,3 @@
712 #undef SUBSUBTARGET_EXTRA_SPECS
713 #define SUBSUBTARGET_EXTRA_SPECS \
714 { "cpp_os_rtems", CPP_OS_RTEMS_SPEC }
715-
716-#undef SUBSUBTARGET_OVERRIDE_OPTIONS
717-#define SUBSUBTARGET_OVERRIDE_OPTIONS \
718- do { \
719- if (TARGET_E500) \
720- { \
721- if (TARGET_HARD_FLOAT && !global_options_set.x_rs6000_float_gprs) \
722- rs6000_float_gprs = 1; \
723- if (rs6000_float_gprs != 0 && !global_options_set.x_rs6000_spe) \
724- rs6000_spe = 1; \
725- if (rs6000_spe && !global_options_set.x_rs6000_spe_abi) \
726- rs6000_spe_abi = 1; \
727- } \
728- } while(0)
729Index: gcc-4_7-branch/gcc/config/rs6000/vxworks.h
730===================================================================
731--- gcc-4_7-branch.orig/gcc/config/rs6000/vxworks.h 2012-07-05 23:49:07.000000000 -0700
732+++ gcc-4_7-branch/gcc/config/rs6000/vxworks.h 2012-07-06 19:44:38.470780001 -0700
733@@ -122,19 +122,8 @@
734
735 #undef ABI_STACK_BOUNDARY
736
737-/* Make -mcpu=8540 imply SPE. ISEL is automatically enabled, the
738- others must be done by hand. Handle -mrtp. Disable -fPIC
739- for -mrtp - the VxWorks PIC model is not compatible with it. */
740 #undef SUBSUBTARGET_OVERRIDE_OPTIONS
741 #define SUBSUBTARGET_OVERRIDE_OPTIONS \
742- do { \
743- if (TARGET_E500) \
744- { \
745- rs6000_spe = 1; \
746- rs6000_spe_abi = 1; \
747- rs6000_float_gprs = 1; \
748- } \
749- \
750 if (!global_options_set.x_g_switch_value) \
751 g_switch_value = SDATA_DEFAULT_SIZE; \
752 VXWORKS_OVERRIDE_OPTIONS; \
diff --git a/meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch b/meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch
new file mode 100644
index 0000000000..e3341fc0a6
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.7/ppce5500-e6500-support.patch
@@ -0,0 +1,713 @@
1Upstream-Status: Backport
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From b770074cee13445eba1bf4e99649c5ceac9a4b5a Mon Sep 17 00:00:00 2001
5From: edmarwjr <edmarwjr@138bc75d-0d04-0410-961f-82ee72b054a4>
6Date: Tue, 5 Jun 2012 16:05:16 +0000
7Subject: [PATCH] 2012-06-01 Edmar Wienskoski <edmar@freescale.com>
8
9 * config/rs6000/e5500.md: New file.
10 * config/rs6000/e6500.md: New file.
11 * config/rs6000/rs6000.c (processor_costs): Add new costs for
12 e5500 and e6500.
13 (rs6000_option_override_internal): Altivec and Spe options not
14 allowed with e5500. Spe options not allowed with e6500. Increase
15 move inline limit for e5500 and e6500. Disable string instructions
16 for e5500 and e6500. Enable branch targets alignment for e5500 and
17 e6500. Initialize rs6000_cost for e5500 and e6500.
18 (rs6000_adjust_cost): Add extra scheduling cycles between compare
19 and brnach for e5500 and e6500.
20 (rs6000_issue_rate): Set issue rate for e5500 and e6500.
21 * config/rs6000/rs6000-cpus.def: Add cpu definitions for e5500 and
22 e6500.
23 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add e5500 and e6500.
24 * config/rs6000/rs6000.md (define_attr "cpu"): Add ppce5500 and
25 ppce6500.
26 Include e5500.md and e6500.md.
27 * config/rs6000/rs6000-opt.h (processor_type): Add
28 PROCESSOR_PPCE5500 and PROCESSOR_PPCE6500.
29 * config.gcc (cpu_is_64bit): Add new cores e5500, e6500.
30 (powerpc*-*-*): Add new cores e5500, e6500.
31 * doc/invoke.texi: (item -mcpu): Add e5500 and e6500 to list of cpus.
32
33gcc/testsuite
342012-06-01 Edmar Wienskoski <edmar@freescale.com>
35
36 * gcc.dg/tree-ssa/vector-3.c: Adjust regular expression.
37
38
39
40git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@188244 138bc75d-0d04-0410-961f-82ee72b054a4
41---
42 gcc/ChangeLog | 26 ++++
43 gcc/config.gcc | 6 +-
44 gcc/config/rs6000/e5500.md | 176 ++++++++++++++++++++++++
45 gcc/config/rs6000/e6500.md | 213 ++++++++++++++++++++++++++++++
46 gcc/config/rs6000/rs6000-cpus.def | 4 +
47 gcc/config/rs6000/rs6000-opts.h | 2 +
48 gcc/config/rs6000/rs6000.c | 68 +++++++++-
49 gcc/config/rs6000/rs6000.h | 2 +
50 gcc/config/rs6000/rs6000.md | 4 +-
51 gcc/doc/invoke.texi | 12 +-
52 gcc/testsuite/ChangeLog | 4 +
53 gcc/testsuite/gcc.dg/tree-ssa/vector-3.c | 2 +-
54 12 files changed, 506 insertions(+), 13 deletions(-)
55 create mode 100644 gcc/config/rs6000/e5500.md
56 create mode 100644 gcc/config/rs6000/e6500.md
57
58Index: gcc-4_7-branch/gcc/config.gcc
59===================================================================
60--- gcc-4_7-branch.orig/gcc/config.gcc 2012-07-06 19:52:30.000000000 -0700
61+++ gcc-4_7-branch/gcc/config.gcc 2012-07-06 19:53:26.350779999 -0700
62@@ -413,7 +413,7 @@
63 extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
64 need_64bit_hwint=yes
65 case x$with_cpu in
66- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64)
67+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|Xe6500)
68 cpu_is_64bit=yes
69 ;;
70 esac
71@@ -3361,8 +3361,8 @@
72 | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
73 | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
74 | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
75- | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\
76- | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
77+ | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | e6500 \
78+ | titan | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
79 # OK
80 ;;
81 *)
82Index: gcc-4_7-branch/gcc/config/rs6000/e5500.md
83===================================================================
84--- /dev/null 1970-01-01 00:00:00.000000000 +0000
85+++ gcc-4_7-branch/gcc/config/rs6000/e5500.md 2012-07-06 19:53:26.350779999 -0700
86@@ -0,0 +1,176 @@
87+;; Pipeline description for Freescale PowerPC e5500 core.
88+;; Copyright (C) 2012 Free Software Foundation, Inc.
89+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
90+;;
91+;; This file is part of GCC.
92+;;
93+;; GCC is free software; you can redistribute it and/or modify it
94+;; under the terms of the GNU General Public License as published
95+;; by the Free Software Foundation; either version 3, or (at your
96+;; option) any later version.
97+;;
98+;; GCC is distributed in the hope that it will be useful, but WITHOUT
99+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
100+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
101+;; License for more details.
102+;;
103+;; You should have received a copy of the GNU General Public License
104+;; along with GCC; see the file COPYING3. If not see
105+;; <http://www.gnu.org/licenses/>.
106+;;
107+;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
108+;; Max issue 3 insns/clock cycle (includes 1 branch)
109+
110+(define_automaton "e5500_most,e5500_long")
111+(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
112+
113+;; SFX.
114+(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
115+
116+;; CFX.
117+(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
118+
119+;; Non-pipelined division.
120+(define_cpu_unit "e5500_cfx_div" "e5500_long")
121+
122+;; LSU.
123+(define_cpu_unit "e5500_lsu" "e5500_most")
124+
125+;; FPU.
126+(define_cpu_unit "e5500_fpu" "e5500_long")
127+
128+;; BU.
129+(define_cpu_unit "e5500_bu" "e5500_most")
130+
131+;; The following units are used to make the automata deterministic.
132+(define_cpu_unit "present_e5500_decode_0" "e5500_most")
133+(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
134+(presence_set "present_e5500_decode_0" "e5500_decode_0")
135+(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
136+
137+;; Some useful abbreviations.
138+(define_reservation "e5500_decode"
139+ "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
140+(define_reservation "e5500_sfx"
141+ "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
142+
143+;; SFX.
144+(define_insn_reservation "e5500_sfx" 1
145+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
146+ shift,cntlz,exts")
147+ (eq_attr "cpu" "ppce5500"))
148+ "e5500_decode,e5500_sfx")
149+
150+(define_insn_reservation "e5500_sfx2" 2
151+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
152+ (eq_attr "cpu" "ppce5500"))
153+ "e5500_decode,e5500_sfx")
154+
155+(define_insn_reservation "e5500_delayed" 2
156+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
157+ (eq_attr "cpu" "ppce5500"))
158+ "e5500_decode,e5500_sfx*2")
159+
160+(define_insn_reservation "e5500_two" 2
161+ (and (eq_attr "type" "two")
162+ (eq_attr "cpu" "ppce5500"))
163+ "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
164+
165+(define_insn_reservation "e5500_three" 3
166+ (and (eq_attr "type" "three")
167+ (eq_attr "cpu" "ppce5500"))
168+ "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
169+
170+;; SFX - Mfcr.
171+(define_insn_reservation "e5500_mfcr" 4
172+ (and (eq_attr "type" "mfcr")
173+ (eq_attr "cpu" "ppce5500"))
174+ "e5500_decode,e5500_sfx_0*4")
175+
176+;; SFX - Mtcrf.
177+(define_insn_reservation "e5500_mtcrf" 1
178+ (and (eq_attr "type" "mtcr")
179+ (eq_attr "cpu" "ppce5500"))
180+ "e5500_decode,e5500_sfx_0")
181+
182+;; SFX - Mtjmpr.
183+(define_insn_reservation "e5500_mtjmpr" 1
184+ (and (eq_attr "type" "mtjmpr,mfjmpr")
185+ (eq_attr "cpu" "ppce5500"))
186+ "e5500_decode,e5500_sfx")
187+
188+;; CFX - Multiply.
189+(define_insn_reservation "e5500_multiply" 4
190+ (and (eq_attr "type" "imul")
191+ (eq_attr "cpu" "ppce5500"))
192+ "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
193+
194+(define_insn_reservation "e5500_multiply_i" 5
195+ (and (eq_attr "type" "imul2,imul3,imul_compare")
196+ (eq_attr "cpu" "ppce5500"))
197+ "e5500_decode,e5500_cfx_stage0,\
198+ e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
199+
200+;; CFX - Divide.
201+(define_insn_reservation "e5500_divide" 16
202+ (and (eq_attr "type" "idiv")
203+ (eq_attr "cpu" "ppce5500"))
204+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
205+ e5500_cfx_div*15")
206+
207+(define_insn_reservation "e5500_divide_d" 26
208+ (and (eq_attr "type" "ldiv")
209+ (eq_attr "cpu" "ppce5500"))
210+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
211+ e5500_cfx_div*25")
212+
213+;; LSU - Loads.
214+(define_insn_reservation "e5500_load" 3
215+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
216+ load_l,sync")
217+ (eq_attr "cpu" "ppce5500"))
218+ "e5500_decode,e5500_lsu")
219+
220+(define_insn_reservation "e5500_fpload" 4
221+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
222+ (eq_attr "cpu" "ppce5500"))
223+ "e5500_decode,e5500_lsu")
224+
225+;; LSU - Stores.
226+(define_insn_reservation "e5500_store" 3
227+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
228+ (eq_attr "cpu" "ppce5500"))
229+ "e5500_decode,e5500_lsu")
230+
231+(define_insn_reservation "e5500_fpstore" 3
232+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
233+ (eq_attr "cpu" "ppce5500"))
234+ "e5500_decode,e5500_lsu")
235+
236+;; FP.
237+(define_insn_reservation "e5500_float" 7
238+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
239+ (eq_attr "cpu" "ppce5500"))
240+ "e5500_decode,e5500_fpu")
241+
242+(define_insn_reservation "e5500_sdiv" 20
243+ (and (eq_attr "type" "sdiv")
244+ (eq_attr "cpu" "ppce5500"))
245+ "e5500_decode,e5500_fpu*20")
246+
247+(define_insn_reservation "e5500_ddiv" 35
248+ (and (eq_attr "type" "ddiv")
249+ (eq_attr "cpu" "ppce5500"))
250+ "e5500_decode,e5500_fpu*35")
251+
252+;; BU.
253+(define_insn_reservation "e5500_branch" 1
254+ (and (eq_attr "type" "jmpreg,branch,isync")
255+ (eq_attr "cpu" "ppce5500"))
256+ "e5500_decode,e5500_bu")
257+
258+;; BU - CR logical.
259+(define_insn_reservation "e5500_cr_logical" 1
260+ (and (eq_attr "type" "cr_logical,delayed_cr")
261+ (eq_attr "cpu" "ppce5500"))
262+ "e5500_decode,e5500_bu")
263Index: gcc-4_7-branch/gcc/config/rs6000/e6500.md
264===================================================================
265--- /dev/null 1970-01-01 00:00:00.000000000 +0000
266+++ gcc-4_7-branch/gcc/config/rs6000/e6500.md 2012-07-06 19:53:26.354779999 -0700
267@@ -0,0 +1,213 @@
268+;; Pipeline description for Freescale PowerPC e6500 core.
269+;; Copyright (C) 2012 Free Software Foundation, Inc.
270+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
271+;;
272+;; This file is part of GCC.
273+;;
274+;; GCC is free software; you can redistribute it and/or modify it
275+;; under the terms of the GNU General Public License as published
276+;; by the Free Software Foundation; either version 3, or (at your
277+;; option) any later version.
278+;;
279+;; GCC is distributed in the hope that it will be useful, but WITHOUT
280+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
281+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
282+;; License for more details.
283+;;
284+;; You should have received a copy of the GNU General Public License
285+;; along with GCC; see the file COPYING3. If not see
286+;; <http://www.gnu.org/licenses/>.
287+;;
288+;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
289+;; Max issue 3 insns/clock cycle (includes 1 branch)
290+
291+(define_automaton "e6500_most,e6500_long,e6500_vec")
292+(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
293+
294+;; SFX.
295+(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
296+
297+;; CFX.
298+(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
299+
300+;; Non-pipelined division.
301+(define_cpu_unit "e6500_cfx_div" "e6500_long")
302+
303+;; LSU.
304+(define_cpu_unit "e6500_lsu" "e6500_most")
305+
306+;; FPU.
307+(define_cpu_unit "e6500_fpu" "e6500_long")
308+
309+;; BU.
310+(define_cpu_unit "e6500_bu" "e6500_most")
311+
312+;; Altivec unit
313+(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
314+
315+;; The following units are used to make the automata deterministic.
316+(define_cpu_unit "present_e6500_decode_0" "e6500_most")
317+(define_cpu_unit "present_e6500_sfx_0" "e6500_most")
318+(presence_set "present_e6500_decode_0" "e6500_decode_0")
319+(presence_set "present_e6500_sfx_0" "e6500_sfx_0")
320+
321+;; Some useful abbreviations.
322+(define_reservation "e6500_decode"
323+ "e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
324+(define_reservation "e6500_sfx"
325+ "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
326+
327+;; SFX.
328+(define_insn_reservation "e6500_sfx" 1
329+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
330+ shift,cntlz,exts")
331+ (eq_attr "cpu" "ppce6500"))
332+ "e6500_decode,e6500_sfx")
333+
334+(define_insn_reservation "e6500_sfx2" 2
335+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
336+ (eq_attr "cpu" "ppce6500"))
337+ "e6500_decode,e6500_sfx")
338+
339+(define_insn_reservation "e6500_delayed" 2
340+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
341+ (eq_attr "cpu" "ppce6500"))
342+ "e6500_decode,e6500_sfx*2")
343+
344+(define_insn_reservation "e6500_two" 2
345+ (and (eq_attr "type" "two")
346+ (eq_attr "cpu" "ppce6500"))
347+ "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
348+
349+(define_insn_reservation "e6500_three" 3
350+ (and (eq_attr "type" "three")
351+ (eq_attr "cpu" "ppce6500"))
352+ "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
353+
354+;; SFX - Mfcr.
355+(define_insn_reservation "e6500_mfcr" 4
356+ (and (eq_attr "type" "mfcr")
357+ (eq_attr "cpu" "ppce6500"))
358+ "e6500_decode,e6500_sfx_0*4")
359+
360+;; SFX - Mtcrf.
361+(define_insn_reservation "e6500_mtcrf" 1
362+ (and (eq_attr "type" "mtcr")
363+ (eq_attr "cpu" "ppce6500"))
364+ "e6500_decode,e6500_sfx_0")
365+
366+;; SFX - Mtjmpr.
367+(define_insn_reservation "e6500_mtjmpr" 1
368+ (and (eq_attr "type" "mtjmpr,mfjmpr")
369+ (eq_attr "cpu" "ppce6500"))
370+ "e6500_decode,e6500_sfx")
371+
372+;; CFX - Multiply.
373+(define_insn_reservation "e6500_multiply" 4
374+ (and (eq_attr "type" "imul")
375+ (eq_attr "cpu" "ppce6500"))
376+ "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
377+
378+(define_insn_reservation "e6500_multiply_i" 5
379+ (and (eq_attr "type" "imul2,imul3,imul_compare")
380+ (eq_attr "cpu" "ppce6500"))
381+ "e6500_decode,e6500_cfx_stage0,\
382+ e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
383+
384+;; CFX - Divide.
385+(define_insn_reservation "e6500_divide" 16
386+ (and (eq_attr "type" "idiv")
387+ (eq_attr "cpu" "ppce6500"))
388+ "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
389+ e6500_cfx_div*15")
390+
391+(define_insn_reservation "e6500_divide_d" 26
392+ (and (eq_attr "type" "ldiv")
393+ (eq_attr "cpu" "ppce6500"))
394+ "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
395+ e6500_cfx_div*25")
396+
397+;; LSU - Loads.
398+(define_insn_reservation "e6500_load" 3
399+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
400+ load_l,sync")
401+ (eq_attr "cpu" "ppce6500"))
402+ "e6500_decode,e6500_lsu")
403+
404+(define_insn_reservation "e6500_fpload" 4
405+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
406+ (eq_attr "cpu" "ppce6500"))
407+ "e6500_decode,e6500_lsu")
408+
409+(define_insn_reservation "e6500_vecload" 4
410+ (and (eq_attr "type" "vecload")
411+ (eq_attr "cpu" "ppce6500"))
412+ "e6500_decode,e6500_lsu")
413+
414+;; LSU - Stores.
415+(define_insn_reservation "e6500_store" 3
416+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
417+ (eq_attr "cpu" "ppce6500"))
418+ "e6500_decode,e6500_lsu")
419+
420+(define_insn_reservation "e6500_fpstore" 3
421+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
422+ (eq_attr "cpu" "ppce6500"))
423+ "e6500_decode,e6500_lsu")
424+
425+(define_insn_reservation "e6500_vecstore" 4
426+ (and (eq_attr "type" "vecstore")
427+ (eq_attr "cpu" "ppce6500"))
428+ "e6500_decode,e6500_lsu")
429+
430+;; FP.
431+(define_insn_reservation "e6500_float" 7
432+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
433+ (eq_attr "cpu" "ppce6500"))
434+ "e6500_decode,e6500_fpu")
435+
436+(define_insn_reservation "e6500_sdiv" 20
437+ (and (eq_attr "type" "sdiv")
438+ (eq_attr "cpu" "ppce6500"))
439+ "e6500_decode,e6500_fpu*20")
440+
441+(define_insn_reservation "e6500_ddiv" 35
442+ (and (eq_attr "type" "ddiv")
443+ (eq_attr "cpu" "ppce6500"))
444+ "e6500_decode,e6500_fpu*35")
445+
446+;; BU.
447+(define_insn_reservation "e6500_branch" 1
448+ (and (eq_attr "type" "jmpreg,branch,isync")
449+ (eq_attr "cpu" "ppce6500"))
450+ "e6500_decode,e6500_bu")
451+
452+;; BU - CR logical.
453+(define_insn_reservation "e6500_cr_logical" 1
454+ (and (eq_attr "type" "cr_logical,delayed_cr")
455+ (eq_attr "cpu" "ppce6500"))
456+ "e6500_decode,e6500_bu")
457+
458+;; VSFX.
459+(define_insn_reservation "e6500_vecsimple" 1
460+ (and (eq_attr "type" "vecsimple,veccmp")
461+ (eq_attr "cpu" "ppce6500"))
462+ "e6500_decode,e6500_vec")
463+
464+;; VCFX.
465+(define_insn_reservation "e6500_veccomplex" 4
466+ (and (eq_attr "type" "veccomplex")
467+ (eq_attr "cpu" "ppce6500"))
468+ "e6500_decode,e6500_vec")
469+
470+;; VFPU.
471+(define_insn_reservation "e6500_vecfloat" 6
472+ (and (eq_attr "type" "vecfloat")
473+ (eq_attr "cpu" "ppce6500"))
474+ "e6500_decode,e6500_vec")
475+
476+;; VPERM.
477+(define_insn_reservation "e6500_vecperm" 2
478+ (and (eq_attr "type" "vecperm")
479+ (eq_attr "cpu" "ppce6500"))
480+ "e6500_decode,e6500_vecperm")
481Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def
482===================================================================
483--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:52:30.000000000 -0700
484+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:53:26.354779999 -0700
485@@ -87,6 +87,10 @@
486 | MASK_ISEL)
487 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
488 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
489+RS6000_CPU ("e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64
490+ | MASK_PPC_GFXOPT | MASK_ISEL)
491+RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
492+ | MASK_MFCRF | MASK_ISEL)
493 RS6000_CPU ("860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
494 RS6000_CPU ("970", PROCESSOR_POWER4,
495 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
496Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h
497===================================================================
498--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:52:30.000000000 -0700
499+++ gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:53:26.354779999 -0700
500@@ -54,6 +54,8 @@
501 PROCESSOR_PPCE300C3,
502 PROCESSOR_PPCE500MC,
503 PROCESSOR_PPCE500MC64,
504+ PROCESSOR_PPCE5500,
505+ PROCESSOR_PPCE6500,
506 PROCESSOR_POWER4,
507 PROCESSOR_POWER5,
508 PROCESSOR_POWER6,
509Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.c
510===================================================================
511--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.c 2012-07-06 19:52:30.000000000 -0700
512+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.c 2012-07-06 19:53:26.354779999 -0700
513@@ -755,6 +755,44 @@
514 1, /* prefetch streams /*/
515 };
516
517+/* Instruction costs on PPCE5500 processors. */
518+static const
519+struct processor_costs ppce5500_cost = {
520+ COSTS_N_INSNS (5), /* mulsi */
521+ COSTS_N_INSNS (5), /* mulsi_const */
522+ COSTS_N_INSNS (4), /* mulsi_const9 */
523+ COSTS_N_INSNS (5), /* muldi */
524+ COSTS_N_INSNS (14), /* divsi */
525+ COSTS_N_INSNS (14), /* divdi */
526+ COSTS_N_INSNS (7), /* fp */
527+ COSTS_N_INSNS (10), /* dmul */
528+ COSTS_N_INSNS (36), /* sdiv */
529+ COSTS_N_INSNS (66), /* ddiv */
530+ 64, /* cache line size */
531+ 32, /* l1 cache */
532+ 128, /* l2 cache */
533+ 1, /* prefetch streams /*/
534+};
535+
536+/* Instruction costs on PPCE6500 processors. */
537+static const
538+struct processor_costs ppce6500_cost = {
539+ COSTS_N_INSNS (5), /* mulsi */
540+ COSTS_N_INSNS (5), /* mulsi_const */
541+ COSTS_N_INSNS (4), /* mulsi_const9 */
542+ COSTS_N_INSNS (5), /* muldi */
543+ COSTS_N_INSNS (14), /* divsi */
544+ COSTS_N_INSNS (14), /* divdi */
545+ COSTS_N_INSNS (7), /* fp */
546+ COSTS_N_INSNS (10), /* dmul */
547+ COSTS_N_INSNS (36), /* sdiv */
548+ COSTS_N_INSNS (66), /* ddiv */
549+ 64, /* cache line size */
550+ 32, /* l1 cache */
551+ 128, /* l2 cache */
552+ 1, /* prefetch streams /*/
553+};
554+
555 /* Instruction costs on AppliedMicro Titan processors. */
556 static const
557 struct processor_costs titan_cost = {
558@@ -2741,13 +2779,19 @@
559 error ("target attribute or pragma changes SPE ABI");
560
561 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
562- || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
563+ || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
564+ || rs6000_cpu == PROCESSOR_PPCE5500)
565 {
566 if (TARGET_ALTIVEC)
567 error ("AltiVec not supported in this target");
568 if (TARGET_SPE)
569 error ("SPE not supported in this target");
570 }
571+ if (rs6000_cpu == PROCESSOR_PPCE6500)
572+ {
573+ if (TARGET_SPE)
574+ error ("SPE not supported in this target");
575+ }
576
577 /* Disable Cell microcode if we are optimizing for the Cell
578 and not optimizing for size. */
579@@ -2842,7 +2886,9 @@
580 user's opinion, though. */
581 if (rs6000_block_move_inline_limit == 0
582 && (rs6000_cpu == PROCESSOR_PPCE500MC
583- || rs6000_cpu == PROCESSOR_PPCE500MC64))
584+ || rs6000_cpu == PROCESSOR_PPCE500MC64
585+ || rs6000_cpu == PROCESSOR_PPCE5500
586+ || rs6000_cpu == PROCESSOR_PPCE6500))
587 rs6000_block_move_inline_limit = 128;
588
589 /* store_one_arg depends on expand_block_move to handle at least the
590@@ -2989,6 +3035,8 @@
591 case PROCESSOR_PPC8548:
592 case PROCESSOR_PPCE500MC:
593 case PROCESSOR_PPCE500MC64:
594+ case PROCESSOR_PPCE5500:
595+ case PROCESSOR_PPCE6500:
596
597 rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
598 rs6000_double_float = TARGET_E500_DOUBLE;
599@@ -3033,7 +3081,9 @@
600 || rs6000_cpu == PROCESSOR_POWER6
601 || rs6000_cpu == PROCESSOR_POWER7
602 || rs6000_cpu == PROCESSOR_PPCE500MC
603- || rs6000_cpu == PROCESSOR_PPCE500MC64);
604+ || rs6000_cpu == PROCESSOR_PPCE500MC64
605+ || rs6000_cpu == PROCESSOR_PPCE5500
606+ || rs6000_cpu == PROCESSOR_PPCE6500);
607
608 /* Allow debug switches to override the above settings. These are set to -1
609 in rs6000.opt to indicate the user hasn't directly set the switch. */
610@@ -3256,6 +3306,14 @@
611 rs6000_cost = &ppce500mc64_cost;
612 break;
613
614+ case PROCESSOR_PPCE5500:
615+ rs6000_cost = &ppce5500_cost;
616+ break;
617+
618+ case PROCESSOR_PPCE6500:
619+ rs6000_cost = &ppce6500_cost;
620+ break;
621+
622 case PROCESSOR_TITAN:
623 rs6000_cost = &titan_cost;
624 break;
625@@ -22304,6 +22362,8 @@
626 || rs6000_cpu_attr == CPU_PPC750
627 || rs6000_cpu_attr == CPU_PPC7400
628 || rs6000_cpu_attr == CPU_PPC7450
629+ || rs6000_cpu_attr == CPU_PPCE5500
630+ || rs6000_cpu_attr == CPU_PPCE6500
631 || rs6000_cpu_attr == CPU_POWER4
632 || rs6000_cpu_attr == CPU_POWER5
633 || rs6000_cpu_attr == CPU_POWER7
634@@ -22849,6 +22909,8 @@
635 case CPU_PPCE300C3:
636 case CPU_PPCE500MC:
637 case CPU_PPCE500MC64:
638+ case CPU_PPCE5500:
639+ case CPU_PPCE6500:
640 case CPU_TITAN:
641 return 2;
642 case CPU_RIOS2:
643Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.h
644===================================================================
645--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.h 2012-07-06 19:52:30.000000000 -0700
646+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.h 2012-07-06 19:53:26.358779999 -0700
647@@ -168,6 +168,8 @@
648 %{mcpu=e300c3: -me300} \
649 %{mcpu=e500mc: -me500mc} \
650 %{mcpu=e500mc64: -me500mc64} \
651+%{mcpu=e5500: -me5500} \
652+%{mcpu=e6500: -me6500} \
653 %{maltivec: -maltivec} \
654 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
655 -many"
656Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md
657===================================================================
658--- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:52:32.000000000 -0700
659+++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:53:26.358779999 -0700
660@@ -166,7 +166,7 @@
661 ;; Processor type -- this attribute must exactly match the processor_type
662 ;; enumeration in rs6000.h.
663
664-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
665+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
666 (const (symbol_ref "rs6000_cpu_attr")))
667
668
669@@ -194,6 +194,8 @@
670 (include "e300c2c3.md")
671 (include "e500mc.md")
672 (include "e500mc64.md")
673+(include "e5500.md")
674+(include "e6500.md")
675 (include "power4.md")
676 (include "power5.md")
677 (include "power6.md")
678Index: gcc-4_7-branch/gcc/doc/invoke.texi
679===================================================================
680--- gcc-4_7-branch.orig/gcc/doc/invoke.texi 2012-07-06 19:43:53.000000000 -0700
681+++ gcc-4_7-branch/gcc/doc/invoke.texi 2012-07-06 19:53:26.362779999 -0700
682@@ -16565,11 +16565,13 @@
683 @samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
684 @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
685 @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
686-@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3},
687-@samp{G4}, @samp{G5}, @samp{titan}, @samp{power}, @samp{power2}, @samp{power3},
688-@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x},
689-@samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
690-@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
691+@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
692+@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
693+@samp{titan}, @samp{power}, @samp{power2}, @samp{power3},
694+@samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6},
695+@samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc},
696+@samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc},
697+and @samp{rs64}.
698
699 @option{-mcpu=common} selects a completely generic processor. Code
700 generated under this option will run on any POWER or PowerPC processor.
701Index: gcc-4_7-branch/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c
702===================================================================
703--- gcc-4_7-branch.orig/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c 2012-07-06 19:43:53.000000000 -0700
704+++ gcc-4_7-branch/gcc/testsuite/gcc.dg/tree-ssa/vector-3.c 2012-07-06 19:53:26.362779999 -0700
705@@ -14,7 +14,7 @@
706
707 /* We should be able to optimize this to just "return 0.0;" */
708 /* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 0 "optimized"} } */
709-/* { dg-final { scan-tree-dump-times "0.0" 1 "optimized"} } */
710+/* { dg-final { scan-tree-dump-times "0\\\.0" 1 "optimized"} } */
711
712 /* { dg-final { cleanup-tree-dump "optimized" } } */
713
diff --git a/meta/recipes-devtools/gcc/gcc-4.7/rs6000-tables.patch b/meta/recipes-devtools/gcc/gcc-4.7/rs6000-tables.patch
new file mode 100644
index 0000000000..5b8064b02d
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.7/rs6000-tables.patch
@@ -0,0 +1,135 @@
1Upstream-Status: Backport
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From 98da658b6944d0bf54beb10001e567d8b8922666 Mon Sep 17 00:00:00 2001
5From: edmarwjr <edmarwjr@138bc75d-0d04-0410-961f-82ee72b054a4>
6Date: Wed, 6 Jun 2012 18:09:18 +0000
7Subject: [PATCH] 2012-06-06 Edmar Wienskoski <edmar@freescale.com>
8
9 * config/rs6000/rs6000-tables.opt: Regenerated.
10
11
12
13git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@188274 138bc75d-0d04-0410-961f-82ee72b054a4
14---
15 gcc/ChangeLog | 4 +++
16 gcc/config/rs6000/rs6000-tables.opt | 58 +++++++++++++++++++----------------
17 2 files changed, 36 insertions(+), 26 deletions(-)
18
19Index: git/gcc/config/rs6000/rs6000-tables.opt
20===================================================================
21--- git.orig/gcc/config/rs6000/rs6000-tables.opt 2012-07-06 20:54:29.000000000 -0700
22+++ git/gcc/config/rs6000/rs6000-tables.opt 2012-07-06 20:58:12.436646819 -0700
23@@ -126,80 +126,86 @@
24 Enum(rs6000_cpu_opt_value) String(e500mc64) Value(32)
25
26 EnumValue
27-Enum(rs6000_cpu_opt_value) String(860) Value(33)
28+Enum(rs6000_cpu_opt_value) String(e5500) Value(33)
29
30 EnumValue
31-Enum(rs6000_cpu_opt_value) String(970) Value(34)
32+Enum(rs6000_cpu_opt_value) String(e6500) Value(34)
33
34 EnumValue
35-Enum(rs6000_cpu_opt_value) String(cell) Value(35)
36+Enum(rs6000_cpu_opt_value) String(860) Value(35)
37
38 EnumValue
39-Enum(rs6000_cpu_opt_value) String(common) Value(36)
40+Enum(rs6000_cpu_opt_value) String(970) Value(36)
41
42 EnumValue
43-Enum(rs6000_cpu_opt_value) String(ec603e) Value(37)
44+Enum(rs6000_cpu_opt_value) String(cell) Value(37)
45
46 EnumValue
47-Enum(rs6000_cpu_opt_value) String(G3) Value(38)
48+Enum(rs6000_cpu_opt_value) String(common) Value(38)
49
50 EnumValue
51-Enum(rs6000_cpu_opt_value) String(G4) Value(39)
52+Enum(rs6000_cpu_opt_value) String(ec603e) Value(39)
53
54 EnumValue
55-Enum(rs6000_cpu_opt_value) String(G5) Value(40)
56+Enum(rs6000_cpu_opt_value) String(G3) Value(40)
57
58 EnumValue
59-Enum(rs6000_cpu_opt_value) String(titan) Value(41)
60+Enum(rs6000_cpu_opt_value) String(G4) Value(41)
61
62 EnumValue
63-Enum(rs6000_cpu_opt_value) String(power) Value(42)
64+Enum(rs6000_cpu_opt_value) String(G5) Value(42)
65
66 EnumValue
67-Enum(rs6000_cpu_opt_value) String(power2) Value(43)
68+Enum(rs6000_cpu_opt_value) String(titan) Value(43)
69
70 EnumValue
71-Enum(rs6000_cpu_opt_value) String(power3) Value(44)
72+Enum(rs6000_cpu_opt_value) String(power) Value(44)
73
74 EnumValue
75-Enum(rs6000_cpu_opt_value) String(power4) Value(45)
76+Enum(rs6000_cpu_opt_value) String(power2) Value(45)
77
78 EnumValue
79-Enum(rs6000_cpu_opt_value) String(power5) Value(46)
80+Enum(rs6000_cpu_opt_value) String(power3) Value(46)
81
82 EnumValue
83-Enum(rs6000_cpu_opt_value) String(power5+) Value(47)
84+Enum(rs6000_cpu_opt_value) String(power4) Value(47)
85
86 EnumValue
87-Enum(rs6000_cpu_opt_value) String(power6) Value(48)
88+Enum(rs6000_cpu_opt_value) String(power5) Value(48)
89
90 EnumValue
91-Enum(rs6000_cpu_opt_value) String(power6x) Value(49)
92+Enum(rs6000_cpu_opt_value) String(power5+) Value(49)
93
94 EnumValue
95-Enum(rs6000_cpu_opt_value) String(power7) Value(50)
96+Enum(rs6000_cpu_opt_value) String(power6) Value(50)
97
98 EnumValue
99-Enum(rs6000_cpu_opt_value) String(powerpc) Value(51)
100+Enum(rs6000_cpu_opt_value) String(power6x) Value(51)
101
102 EnumValue
103-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52)
104+Enum(rs6000_cpu_opt_value) String(power7) Value(52)
105
106 EnumValue
107-Enum(rs6000_cpu_opt_value) String(rios) Value(53)
108+Enum(rs6000_cpu_opt_value) String(powerpc) Value(53)
109
110 EnumValue
111-Enum(rs6000_cpu_opt_value) String(rios1) Value(54)
112+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(54)
113
114 EnumValue
115-Enum(rs6000_cpu_opt_value) String(rios2) Value(55)
116+Enum(rs6000_cpu_opt_value) String(rios) Value(55)
117
118 EnumValue
119-Enum(rs6000_cpu_opt_value) String(rsc) Value(56)
120+Enum(rs6000_cpu_opt_value) String(rios1) Value(56)
121
122 EnumValue
123-Enum(rs6000_cpu_opt_value) String(rsc1) Value(57)
124+Enum(rs6000_cpu_opt_value) String(rios2) Value(57)
125
126 EnumValue
127-Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
128+Enum(rs6000_cpu_opt_value) String(rsc) Value(58)
129+
130+EnumValue
131+Enum(rs6000_cpu_opt_value) String(rsc1) Value(59)
132+
133+EnumValue
134+Enum(rs6000_cpu_opt_value) String(rs64) Value(60)
135
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-01-24 18:47:31 +0000