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<title>linux/poky.git/meta/conf/machine/include, branch uninative-1.4</title>
<subtitle>Mirror of git.yoctoproject.org/poky</subtitle>
<id>https://git.enea.com/cgit/linux/poky.git/atom?h=uninative-1.4</id>
<link rel='self' href='https://git.enea.com/cgit/linux/poky.git/atom?h=uninative-1.4'/>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/'/>
<updated>2016-09-23T13:56:39+00:00</updated>
<entry>
<title>runqemu: Move virtio RNG to machine configuration</title>
<updated>2016-09-23T13:56:39+00:00</updated>
<author>
<name>Nathan Rossi</name>
<email>nathan@nathanrossi.com</email>
</author>
<published>2016-09-22T13:53:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=deba7cac00c9ff72409f021a8aef0a4a4692864d'/>
<id>urn:sha1:deba7cac00c9ff72409f021a8aef0a4a4692864d</id>
<content type='text'>
Not all QEMU machines (outside of those available in OE-Core) are
capable of using the virtio-rng-pci device due to various machine models
not having a pci/virtio bus. This makes it such that the use of the
'-device virtio-rng-pci' flag to QEMU is machine specific.

This patch removes the general addition of the flag to all runqemu
targets and adds the flag into the QB_OPT_APPEND for all the qemu*
machines in OE-Core that support its use (which is all of them).

(From OE-Core rev: e890c05e66a21702e9e8ccce794b74cb7f5518ed)

Signed-off-by: Nathan Rossi &lt;nathan@nathanrossi.com&gt;
Signed-off-by: Ross Burton &lt;ross.burton@intel.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>qemuboot-x86: Add task_timeout = -1 to uvesafb</title>
<updated>2016-09-16T14:24:03+00:00</updated>
<author>
<name>Saul Wold</name>
<email>sgw@linux.intel.com</email>
</author>
<published>2016-09-15T20:29:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=8d3f71234f8e14b5aa1e5ced4676d5b3d7ac014f'/>
<id>urn:sha1:8d3f71234f8e14b5aa1e5ced4676d5b3d7ac014f</id>
<content type='text'>
This causes the default timeout to be set to infinity, it will still report out
every 5000 milliseconds

(From OE-Core rev: fd9e1ba8f70402bd3c4b873d349057f96f5bcb19)

Signed-off-by: Saul Wold &lt;sgw@linux.intel.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>qemu.inc: inherit qemuboot.bbclass</title>
<updated>2016-09-09T11:07:32+00:00</updated>
<author>
<name>Robert Yang</name>
<email>liezhi.yang@windriver.com</email>
</author>
<published>2016-08-25T14:41:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=638d19adb4eefc7e801f9409d0b348a5a39cc25a'/>
<id>urn:sha1:638d19adb4eefc7e801f9409d0b348a5a39cc25a</id>
<content type='text'>
All qemu boards should be able to boot by runqemu.

(From OE-Core rev: 5174889d59a5d6da29b4290376010dd176767e1f)

Signed-off-by: Robert Yang &lt;liezhi.yang@windriver.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>qemumips/qemumips64.conf: set vars for runqemu</title>
<updated>2016-09-09T11:07:31+00:00</updated>
<author>
<name>Robert Yang</name>
<email>liezhi.yang@windriver.com</email>
</author>
<published>2016-08-25T14:41:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=09a77107e7e5b407999830143505708c6b9bddc3'/>
<id>urn:sha1:09a77107e7e5b407999830143505708c6b9bddc3</id>
<content type='text'>
Add qemuboot-mips.inc to reduce duplicated code, the various mips bsps
which can be boot by runqemu can require qemuboot-mips.inc

(From OE-Core rev: cb28128477e98ed7dc7a90dd197f6dd04cf75be0)

Signed-off-by: Robert Yang &lt;liezhi.yang@windriver.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>qemux86.conf/qemux86-64.conf: set vars for runqemu</title>
<updated>2016-09-09T11:07:31+00:00</updated>
<author>
<name>Robert Yang</name>
<email>liezhi.yang@windriver.com</email>
</author>
<published>2016-08-25T14:41:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=64da0d77991c3bdd98a64060a338a4a2aac9551e'/>
<id>urn:sha1:64da0d77991c3bdd98a64060a338a4a2aac9551e</id>
<content type='text'>
Add qemuboot-x86.inc to reduce duplicated code, the x86/x86_64 bsps
which can be boot by runqemu can require qemuboot-x86.inc.

(From OE-Core rev: b5ff3dda2a576ba7e5d68198ea6c6eb49cf80eb8)

Signed-off-by: Robert Yang &lt;liezhi.yang@windriver.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>arch-mips.inc: Disable QEMU usermode usage when building with n32 ABI</title>
<updated>2016-09-03T22:45:54+00:00</updated>
<author>
<name>Alexander Kanavin</name>
<email>alexander.kanavin@linux.intel.com</email>
</author>
<published>2016-09-01T17:50:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=51afd4515f7373765e7fbe15aefc63668d927f5a'/>
<id>urn:sha1:51afd4515f7373765e7fbe15aefc63668d927f5a</id>
<content type='text'>
QEMU usermode doesn't support n32 binaries, erroring with "Invalid
ELF image for this architecture".

(From OE-Core rev: 66aa39a959bd41f7063fe64a9225eb9fd6c3293b)

Signed-off-by: Alexander Kanavin &lt;alexander.kanavin@linux.intel.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>tune-mips-24k: add QEMU_EXTRAOPTIONS for DSP and MIPS16e cores</title>
<updated>2016-08-01T10:47:11+00:00</updated>
<author>
<name>André Draszik</name>
<email>git@andred.net</email>
</author>
<published>2016-07-26T15:49:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=1ebec491aac49020b58d885a89ef8a9d33b0daf5'/>
<id>urn:sha1:1ebec491aac49020b58d885a89ef8a9d33b0daf5</id>
<content type='text'>
The core emulated by default by qemu-mips(el) just crashes with
illegal instruction when encountering DSP and/or MIPS16e
instructions - we have to specify a CPU that supports the extra
instructions.

This is an issue when generating a rootfs and e.g. running some
of the package postinstall scriptlets.

The patch to qemu to add 24KEc as a CPU has been accepted
upstream, so let's use that CPU here as well as needed.

(From OE-Core rev: 8af17075f56241dd8f3ea86c609adbd73f248218)

Signed-off-by: André Draszik &lt;git@andred.net&gt;
Signed-off-by: Ross Burton &lt;ross.burton@intel.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>tune-ppce500mc.inc: pass -mcpu=e500mc for ppce500mc kernel compile</title>
<updated>2016-07-10T13:12:17+00:00</updated>
<author>
<name>Zhenhua Luo</name>
<email>zhenhua.luo@nxp.com</email>
</author>
<published>2016-06-28T07:25:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=6bb3069eeff76373041f8da08418386fe5ef5897'/>
<id>urn:sha1:6bb3069eeff76373041f8da08418386fe5ef5897</id>
<content type='text'>
Currently the -mcpu parameter is not passed to cross gcc when assembling
kernel .S file, the implicit -mcpu option that defaults to the latest
server cpu might casuse incorrect assembling.

A existent case is that wait instruction of ppce500mc is incorrectly assembled
to power9 version with default -mcpu setting, accordingly kernel boot calltrace
happend when wait instruction is executed on ppce500mc targets.

(From OE-Core rev: b17f91ed06a604e3d356fe17756bfe2ca61594b7)

Signed-off-by: Zhenhua Luo &lt;zhenhua.luo@nxp.com&gt;
Signed-off-by: Ross Burton &lt;ross.burton@intel.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>mips: add tunes for (some) 24K cores</title>
<updated>2016-06-12T22:47:19+00:00</updated>
<author>
<name>André Draszik</name>
<email>adraszik@tycoint.com</email>
</author>
<published>2016-06-10T15:12:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=a9120996e032fbc6472dadbe39a3616b8826d9e5'/>
<id>urn:sha1:a9120996e032fbc6472dadbe39a3616b8826d9e5</id>
<content type='text'>
- add 24kc big and little endian, which is based on mips32r2 w/o FPU
- add 24kec which is 24kc + DSP
- both can have the MIPS16e ASE enabled in their tunes

(From OE-Core rev: cccd8b09523d8f0c1df97d08181737681db13f37)

Signed-off-by: André Draszik &lt;adraszik@tycoint.com&gt;
Signed-off-by: Ross Burton &lt;ross.burton@intel.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>mips: add a tune for using MIPS16e ASE instructions</title>
<updated>2016-06-12T22:47:18+00:00</updated>
<author>
<name>André Draszik</name>
<email>adraszik@tycoint.com</email>
</author>
<published>2016-06-10T15:12:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.enea.com/cgit/linux/poky.git/commit/?id=7acb3db0b1a93977e67e4e31ff05c4b081e34d90'/>
<id>urn:sha1:7acb3db0b1a93977e67e4e31ff05c4b081e34d90</id>
<content type='text'>
The MIPS16e instruction set still has to be enabled by setting
MIPS_INSTRUCTION_SET = 'mips16e'
in e.g. distro.conf and can be disabled on a per-recipe basis as
needed.

This is a similar approach as is available on ARM for Thumb support.

Note that contrary to the ARM Thumb support in OE, we do add a new
OVERRIDE (mips16e), as there are some recipes in OE that need to be
compiled slightly differently if mips16e mode is requested.

(From OE-Core rev: e9d8b02a42eb08802e202770409cb5378b79b281)

Signed-off-by: André Draszik &lt;adraszik@tycoint.com&gt;
Signed-off-by: Ross Burton &lt;ross.burton@intel.com&gt;
Signed-off-by: Richard Purdie &lt;richard.purdie@linuxfoundation.org&gt;
</content>
</entry>
</feed>
