From ffc8f2c9c676161379a26bd99e3101b995959344 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 30 Sep 2024 11:14:37 +0530 Subject: embeddedsw : Updated SRCREV for 2024.2_4867 v_hdmiphy1: Added min max for DPLL scripts: pyesw: validate_hw: Add special handling for dhrystone xilpm: versal_aiepg2: Fix plm build error sw_services: xilsecure: Add Redundancy check for XPlmi_MemCpy64 xdmapcie:Modify the format specifier for BAR allocation debug prints pciepsu:Modify format specifier for BAR allocation debug prints bsp: standalone: Add support for AXI NOC2 DDR region in MPU initialization sw_services:xilasu:Added timeout xilpm: versal_common: server: Fix compilation warning versalnet: xilnvm doxygen updates to RTF versal: xilnvm doxygen updates for RTF xilnvm: fixed doxygen grouping peripheral_tests: Fixed source code-format issue. peripheral_tests: Fix compilation warnings sw_services:xilnvm: Fix for debug prints in efuse client example spdif: Fix the interrupt id mapping xilpm: versal: support skipping ADC/DAC housecleaning sw_services: xilplmi: Fix compilation errors ThirdParty: openamp: libmetal version dependency sw_services: xilpuf: Corrected comments in function header lib: sw_apps: openamp: sdt: versal: Add RPU1 to A72 channel --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'meta-xilinx-standalone') diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index d893a559..471379db 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -19,7 +19,7 @@ ESW_REV[2022.2] = "5330a64c8efd14f0eef09befdbb8d3d738c33ec2" ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" ESW_REV[2024.1] = "b173d246826f662b9a98215d8f39e93d39d699b4" -ESW_REV[2024.2] = "06b156a1f3e09cc33ca333180a772bbfa4f614c2" +ESW_REV[2024.2] = "449d38b0c5e4bf00ea763525b4c11c35f528c2f4" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf