From 90d68b2194163ad5317771c67716a4f0119e4bc6 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 16 Jul 2024 08:44:39 -0600 Subject: meta-microblaze: Update Upstream-Status Signed-off-by: Mark Hatle (cherry picked from commit 79fa542cb1202cd491fd8a1395892b3e9f905773) Signed-off-by: Mark Hatle --- .../recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch | 2 +- .../gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch index af8ebf3b..56d8c223 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch @@ -27,7 +27,7 @@ Do same for riscv64 and aarch64 RP 15/8/11 -Upstream-Status: Inappropriate[OE-Specific] +Upstream-Status: Inappropriate [OE-Specific] Signed-off-by: Khem Raj Signed-off-by: Elvis Dowson diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch index 93f67800..6a930420 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch @@ -3,6 +3,8 @@ From: Aayush Misra Date: Fri, 29 Mar 2024 14:59:16 +0530 Subject: [PATCH] gdb/gdserver: Fix ABI settings for gdbserver +Upstream-Status: Pending + --- gdb/microblaze-tdep.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- cgit v1.2.3-54-g00ecf From c5b5967008a48fcf4e988189db0830db7bfc00c6 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 23 Jul 2024 15:43:00 -0600 Subject: meta-microblaze: binutils: Add local patches, including 64-bit support Signed-off-by: Mark Hatle --- .../binutils/binutils-microblaze.inc | 59 + ...-port-of-linux-gdbserver-add-gdb_proc_ser.patch | 42 + ...-port-of-linux-gdbserver-add-gdb_proc_ser.patch | 639 +++ ...t-of-core-reading-support-Added-support-f.patch | 301 ++ ...ebug-message-when-register-is-unavailable.patch | 45 + .../binutils/0005-MicroBlaze-native-gdb-port.patch | 834 ++++ ...it-MB-support-Added-new-architecture-to-M.patch | 1841 +++++++++ ...es-will-make-64-bit-vectors-as-default-ta.patch | 35 + ...bi-for-64-bit-target-descriptions.-set-m6.patch | 4104 ++++++++++++++++++++ ...-number-of-inline-functions-refer-inline-.patch | 74 + ...build-errors-for-microblaze-xilinx-elf-20.patch | 133 + ...roblaze-xilinx-elf-crash-issue-on-invocat.patch | 28 + ...-Add-mlittle-endian-and-mbig-endian-flags.patch | 46 + ...able-the-warning-message-for-eh_frame_hdr.patch | 35 + ...ion-of-assembler-resolved-references-Fixu.patch | 48 + ...ange-to-garbage-collection-sweep-causes-m.patch | 43 + .../0016-Add-new-bit-field-instructions.patch | 219 ++ ...n-GCC-so-that-It-will-support-.long-0U-an.patch | 34 + ...ll-give-error-messages-in-more-detail-for.patch | 37 + ...initial-support-for-MicroBlaze-64-bit-m64.patch | 202 + ...initial-support-for-MicroBlaze-64-bit-m64.patch | 82 + .../binutils/0021-Added-relocations-for-MB-X.patch | 108 + ...initial-support-for-MicroBlaze-64-bit-m64.patch | 958 +++++ .../binutils/0023-Added-relocations-for-MB-X.patch | 246 ++ ...relocation-issues-Added-imml-for-required.patch | 52 + ...ss-computation-issues-with-64bit-address-.patch | 160 + ...Blaze-Adding-new-relocation-to-support-64.patch | 110 + ...emove-unused-expression-state-defsym-symb.patch | 84 + ...-the-long-long-long-mingw-toolchain-issue.patch | 58 + ...rt-to-new-arithmetic-single-register-inst.patch | 371 ++ ...-double-imml-generation-for-64-bit-values.patch | 545 +++ ...in-generation-of-IMML-instruction-for-the.patch | 88 + ...will-remove-imml-0-and-imml-1-instruction.patch | 38 + ...e-long-to-long-long-as-in-Windows-long-is.patch | 32 + ...vert-moving-of-md_pseudo_table-from-const.patch | 62 + ...ms-elf64microblaze-Fix-emulation-generati.patch | 44 + ...a-offsets-pointer-after-relaxation.-Propo.patch | 79 + ...-with-ld-no-keep-memory.-Proposed-patches.patch | 107 + .../0038-MB-binutils-Upstream-port-issues.patch | 99 + ...t-of-core-reading-support-Added-support-f.patch | 89 + ...issues-after-Xilinx-2023.2-binutils-merge.patch | 185 + ...e-truncated-register-warning-gdb-remote.c.patch | 26 + ...solved-conflicts-from-binutils_2_42_merge.patch | 42 + ...gdbarch_init-set-microblaze_abi-based-on-.patch | 177 + ...ach_microblaze-values-from-0-0-1-instead-.patch | 32 + ...ssues-bfd-reloc.c-add-missing-relocs-used.patch | 61 + ...046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch | 116 + ...c-revert-earlier-change-to-process_g_pack.patch | 32 + ...ssues-after-Xilinx-2023.2-binutils-patch-.patch | 465 +++ ...unwinding-pc-value-adjust-return-pc-value.patch | 92 + ...info-reg-pc-does-not-print-symbolic-value.patch | 116 + ...t-description-accepted-by-microblaze-arch.patch | 51 + ...icroblaze-linux-tdep.c-to-gdb-14-and-fix-.patch | 42 + ...n-improvement-which-inlines-target_gdbarc.patch | 29 + meta-vitis-tc/conf/machine/microblaze-tc.conf | 32 +- 55 files changed, 13693 insertions(+), 16 deletions(-) create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0003-Initial-port-of-core-reading-support-Added-support-f.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0004-Fix-debug-message-when-register-is-unavailable.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0005-MicroBlaze-native-gdb-port.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0012-Add-mlittle-endian-and-mbig-endian-flags.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0013-Disable-the-warning-message-for-eh_frame_hdr.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0016-Add-new-bit-field-instructions.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0018-Compiler-will-give-error-messages-in-more-detail-for.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0019-initial-support-for-MicroBlaze-64-bit-m64.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0020-initial-support-for-MicroBlaze-64-bit-m64.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0021-Added-relocations-for-MB-X.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0022-initial-support-for-MicroBlaze-64-bit-m64.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-relocations-for-MB-X.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0025-Fixed-address-computation-issues-with-64bit-address-.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0029-Added-support-to-new-arithmetic-single-register-inst.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0030-double-imml-generation-for-64-bit-values.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0034-gas-revert-moving-of-md_pseudo_table-from-const.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0038-MB-binutils-Upstream-port-issues.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-port-of-core-reading-support-Added-support-f.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0041-disable-truncated-register-warning-gdb-remote.c.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0049-When-unwinding-pc-value-adjust-return-pc-value.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0050-info-reg-pc-does-not-print-symbolic-value.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0051-Wrong-target-description-accepted-by-microblaze-arch.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch create mode 100644 meta-microblaze/recipes-devtools/binutils/binutils/0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc b/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc index 3701d245..014729a5 100644 --- a/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc +++ b/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc @@ -2,3 +2,62 @@ FILESEXTRAPATHS:append := ":${THISDIR}/binutils" LDGOLD_ALTS:microblaze = "" USE_ALTERNATIVES_FOR:remove:microblaze = "gprof" + +# Our changes are all local, no real patch-status +ERROR_QA:remove = "patch-status" + +SRC_URI += " \ + file://0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \ + file://0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \ + file://0003-Initial-port-of-core-reading-support-Added-support-f.patch \ + file://0004-Fix-debug-message-when-register-is-unavailable.patch \ + file://0005-MicroBlaze-native-gdb-port.patch \ + file://0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch \ + file://0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch \ + file://0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch \ + file://0009-Depth-Total-number-of-inline-functions-refer-inline-.patch \ + file://0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch \ + file://0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch \ + file://0012-Add-mlittle-endian-and-mbig-endian-flags.patch \ + file://0013-Disable-the-warning-message-for-eh_frame_hdr.patch \ + file://0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch \ + file://0015-upstream-change-to-garbage-collection-sweep-causes-m.patch \ + file://0016-Add-new-bit-field-instructions.patch \ + file://0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch \ + file://0018-Compiler-will-give-error-messages-in-more-detail-for.patch \ + file://0019-initial-support-for-MicroBlaze-64-bit-m64.patch \ + file://0020-initial-support-for-MicroBlaze-64-bit-m64.patch \ + file://0021-Added-relocations-for-MB-X.patch \ + file://0022-initial-support-for-MicroBlaze-64-bit-m64.patch \ + file://0023-Added-relocations-for-MB-X.patch \ + file://0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch \ + file://0025-Fixed-address-computation-issues-with-64bit-address-.patch \ + file://0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch \ + file://0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch \ + file://0028-fixing-the-long-long-long-mingw-toolchain-issue.patch \ + file://0029-Added-support-to-new-arithmetic-single-register-inst.patch \ + file://0030-double-imml-generation-for-64-bit-values.patch \ + file://0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch \ + file://0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch \ + file://0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch \ + file://0034-gas-revert-moving-of-md_pseudo_table-from-const.patch \ + file://0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch \ + file://0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch \ + file://0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch \ + file://0038-MB-binutils-Upstream-port-issues.patch \ + file://0039-Initial-port-of-core-reading-support-Added-support-f.patch \ + file://0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch \ + file://0041-disable-truncated-register-warning-gdb-remote.c.patch \ + file://0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch \ + file://0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch \ + file://0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch \ + file://0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch \ + file://0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch \ + file://0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch \ + file://0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch \ + file://0049-When-unwinding-pc-value-adjust-return-pc-value.patch \ + file://0050-info-reg-pc-does-not-print-symbolic-value.patch \ + file://0051-Wrong-target-description-accepted-by-microblaze-arch.patch \ + file://0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch \ + file://0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch \ +" diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch new file mode 100644 index 00000000..fd8a96c9 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch @@ -0,0 +1,42 @@ +From add4545f804219232f16f96e3a83af2fadf41463 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 15:07:22 +0530 +Subject: [PATCH 01/53] Add initial port of linux gdbserver add + gdb_proc_service_h to gdbserver microblaze-linux + +gdbserver needs to initialise the microblaze registers + +other archs use this step to run a *_arch_setup() to carry out all +architecture specific setup - may need to add in future + + * add linux-ptrace.o to gdbserver configure + * Update breakpoint opcode + * fix segfault on connecting gdbserver + * add microblaze_linux_memory_remove_breakpoint + * add set_solib_svr4_fetch_link_map_offsets + * add set_gdbarch_fetch_tls_load_module_address + * Force reading of r0 as 0, prevent stores + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + gdbserver/Makefile.in | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in +index d12f8746611..ee606908bae 100644 +--- a/gdbserver/Makefile.in ++++ b/gdbserver/Makefile.in +@@ -180,6 +180,7 @@ SFILES = \ + $(srcdir)/linux-loongarch-low.cc \ + $(srcdir)/linux-low.cc \ + $(srcdir)/linux-m68k-low.cc \ ++ $(srcdir)/linux-microblaze-low.cc \ + $(srcdir)/linux-mips-low.cc \ + $(srcdir)/linux-nios2-low.cc \ + $(srcdir)/linux-or1k-low.cc \ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch new file mode 100644 index 00000000..ea6689fe --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch @@ -0,0 +1,639 @@ +From aebe2fdb45467fe4a07874cc310e441a38c23f84 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 15:07:22 +0530 +Subject: [PATCH 02/53] Add initial port of linux gdbserver add + gdb_proc_service_h to gdbserver microblaze-linux + +gdbserver needs to initialise the microblaze registers + +other archs use this step to run a *_arch_setup() to carry out all +architecture specific setup - may need to add in future + + * add linux-ptrace.o to gdbserver configure + * Update breakpoint opcode + * fix segfault on connecting gdbserver + * add microblaze_linux_memory_remove_breakpoint + * add set_solib_svr4_fetch_link_map_offsets + * add set_gdbarch_fetch_tls_load_module_address + * Force reading of r0 as 0, prevent stores + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + gdb/configure.host | 2 + + gdb/features/Makefile | 1 + + gdb/features/microblaze-linux.xml | 13 ++ + gdb/microblaze-linux-tdep.c | 29 ++- + gdb/microblaze-tdep.c | 35 +++- + gdb/microblaze-tdep.h | 4 +- + gdb/regformats/microblaze-linux.dat | 64 +++++++ + gdb/regformats/reg-microblaze.dat | 41 +++++ + gdbserver/configure.srv | 10 ++ + gdbserver/linux-microblaze-low.cc | 269 ++++++++++++++++++++++++++++ + 10 files changed, 465 insertions(+), 3 deletions(-) + create mode 100644 gdb/features/microblaze-linux.xml + create mode 100644 gdb/regformats/microblaze-linux.dat + create mode 100644 gdb/regformats/reg-microblaze.dat + create mode 100644 gdbserver/linux-microblaze-low.cc + +diff --git a/gdb/configure.host b/gdb/configure.host +index da71675b201..877537d06ef 100644 +--- a/gdb/configure.host ++++ b/gdb/configure.host +@@ -61,6 +61,7 @@ i[34567]86*) gdb_host_cpu=i386 ;; + loongarch*) gdb_host_cpu=loongarch ;; + m68*) gdb_host_cpu=m68k ;; + mips*) gdb_host_cpu=mips ;; ++microblaze*) gdb_host_cpu=microblaze ;; + powerpc* | rs6000) gdb_host_cpu=powerpc ;; + sparcv9 | sparc64) gdb_host_cpu=sparc ;; + s390*) gdb_host_cpu=s390 ;; +@@ -127,6 +128,7 @@ m68*-*-openbsd*) gdb_host=obsd ;; + + m88*-*-openbsd*) gdb_host=obsd ;; + ++microblaze*-*linux*) gdb_host=linux ;; + mips*-*-linux*) gdb_host=linux ;; + mips*-*-netbsdaout* | mips*-*-knetbsd*-gnu) + gdb_host=nbsd ;; +diff --git a/gdb/features/Makefile b/gdb/features/Makefile +index cda6a49d563..8ac30d8cea3 100644 +--- a/gdb/features/Makefile ++++ b/gdb/features/Makefile +@@ -46,6 +46,7 @@ + # List of .dat files to create in ../regformats/ + WHICH = mips-linux mips-dsp-linux \ + mips64-linux mips64-dsp-linux \ ++ microblaze-linux \ + nios2-linux \ + or1k-linux \ + rs6000/powerpc-32 \ +diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml +new file mode 100644 +index 00000000000..688a3f83d1e +--- /dev/null ++++ b/gdb/features/microblaze-linux.xml +@@ -0,0 +1,13 @@ ++ ++ ++ ++ ++ ++ microblaze ++ GNU/Linux ++ ++ +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 7d620a3688b..d25100ef867 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,6 +37,22 @@ + #include "tramp-frame.h" + #include "linux-tdep.h" + ++static int microblaze_debug_flag = 0; ++ ++static void ++microblaze_debug (const char *fmt, ...) ++{ ++ if (microblaze_debug_flag) ++ { ++ va_list args; ++ ++ va_start (args, fmt); ++ printf_unfiltered ("MICROBLAZE LINUX: "); ++ vprintf_unfiltered (fmt, args); ++ va_end (args); ++ } ++} ++ + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + /* Determine appropriate breakpoint contents and size for this address. */ + bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); + ++ /* Make sure we see the memory breakpoints. */ ++ scoped_restore restore_memory ++ = make_scoped_restore_show_memory_breakpoints (1); ++ + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the + program modified the code on us, so it is wrong to put back the + old value. */ + if (val == 0 && memcmp (bp, old_contents, bplen) == 0) +- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } + + return val; + } +@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info, + /* Trampolines. */ + tramp_frame_prepend_unwinder (gdbarch, + µblaze_linux_sighandler_tramp_frame); ++ ++ /* Enable TLS support. */ ++ set_gdbarch_fetch_tls_load_module_address (gdbarch, ++ svr4_fetch_objfile_link_map); + } + + void _initialize_microblaze_linux_tdep (); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index fc83634d1e6..3ff7ec644b6 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -128,7 +128,38 @@ microblaze_fetch_instruction (CORE_ADDR pc) + constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; + + typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; +- ++static int ++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, ++ struct bp_target_info *bp_tgt) ++{ ++ CORE_ADDR addr = bp_tgt->placed_address; ++ const unsigned char *bp; ++ int val; ++ int bplen; ++ gdb_byte old_contents[BREAKPOINT_MAX]; ++ ++ /* Determine appropriate breakpoint contents and size for this address. */ ++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); ++ if (bp == NULL) ++ error (_("Software breakpoints not implemented for this target.")); ++ ++ /* Make sure we see the memory breakpoints. */ ++ scoped_restore restore_memory ++ = make_scoped_restore_show_memory_breakpoints (1); ++ ++ val = target_read_memory (addr, old_contents, bplen); ++ ++ /* If our breakpoint is no longer at the address, this means that the ++ program modified the code on us, so it is wrong to put back the ++ old value. */ ++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0) ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } ++ ++ return val; ++} + + /* Allocate and initialize a frame cache. */ + +@@ -714,6 +745,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + microblaze_breakpoint::bp_from_kind); ++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + + set_gdbarch_frame_args_skip (gdbarch, 8); + +@@ -754,4 +786,5 @@ When non-zero, microblaze specific debugging is enabled."), + NULL, + &setdebuglist, &showdebuglist); + ++ + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 0b4a5a3f472..56736b9b0c9 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -118,6 +118,8 @@ struct microblaze_frame_cache + + /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. + Only used for native debugging. */ +-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60} ++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} ++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} ++ + + #endif /* microblaze-tdep.h */ +diff --git a/gdb/regformats/microblaze-linux.dat b/gdb/regformats/microblaze-linux.dat +new file mode 100644 +index 00000000000..b5b49f485cd +--- /dev/null ++++ b/gdb/regformats/microblaze-linux.dat +@@ -0,0 +1,64 @@ ++# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro: ++# Generated from: microblaze-linux.xml ++name:microblaze_linux ++xmltarget:microblaze-linux.xml ++expedite:r1,rpc ++32:r0 ++32:r1 ++32:r2 ++32:r3 ++32:r4 ++32:r5 ++32:r6 ++32:r7 ++32:r8 ++32:r9 ++32:r10 ++32:r11 ++32:r12 ++32:r13 ++32:r14 ++32:r15 ++32:r16 ++32:r17 ++32:r18 ++32:r19 ++32:r20 ++32:r21 ++32:r22 ++32:r23 ++32:r24 ++32:r25 ++32:r26 ++32:r27 ++32:r28 ++32:r29 ++32:r30 ++32:r31 ++32:rpc ++32:rmsr ++32:rear ++32:resr ++32:rfsr ++32:rbtr ++32:rpvr0 ++32:rpvr1 ++32:rpvr2 ++32:rpvr3 ++32:rpvr4 ++32:rpvr5 ++32:rpvr6 ++32:rpvr7 ++32:rpvr8 ++32:rpvr9 ++32:rpvr10 ++32:rpvr11 ++32:redr ++32:rpid ++32:rzpr ++32:rtlbx ++32:rtlbsx ++32:rtlblo ++32:rtlbhi ++32:slr ++32:shr +diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat +new file mode 100644 +index 00000000000..bd8a4384424 +--- /dev/null ++++ b/gdb/regformats/reg-microblaze.dat +@@ -0,0 +1,41 @@ ++name:microblaze ++expedite:r1,pc ++32:r0 ++32:r1 ++32:r2 ++32:r3 ++32:r4 ++32:r5 ++32:r6 ++32:r7 ++32:r8 ++32:r9 ++32:r10 ++32:r11 ++32:r12 ++32:r13 ++32:r14 ++32:r15 ++32:r16 ++32:r17 ++32:r18 ++32:r19 ++32:r20 ++32:r21 ++32:r22 ++32:r23 ++32:r24 ++32:r25 ++32:r26 ++32:r27 ++32:r28 ++32:r29 ++32:r30 ++32:r31 ++32:pc ++32:msr ++32:ear ++32:esr ++32:fsr ++32:slr ++32:shr +diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv +index 9e861a75088..11ce617e72f 100644 +--- a/gdbserver/configure.srv ++++ b/gdbserver/configure.srv +@@ -159,6 +159,16 @@ case "${gdbserver_host}" in + srv_linux_regsets=yes + srv_linux_thread_db=yes + ;; ++ ++microblaze*-*-linux*) srv_regobj="microblaze-linux.o" ++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o" ++ srv_xmlfiles="microblaze-linux.xml" ++ srv_xmlfiles="${srv_xmlfiles} microblaze-core.xml" ++ srv_linux_usrregs=yes ++ srv_linux_regsets=yes ++ srv_linux_thread_db=yes ++ ;; ++ + mips*-*-linux*) srv_regobj="mips-linux.o" + srv_regobj="${srv_regobj} mips-dsp-linux.o" + srv_regobj="${srv_regobj} mips64-linux.o" +diff --git a/gdbserver/linux-microblaze-low.cc b/gdbserver/linux-microblaze-low.cc +new file mode 100644 +index 00000000000..bf9eecc41ab +--- /dev/null ++++ b/gdbserver/linux-microblaze-low.cc +@@ -0,0 +1,269 @@ ++/* GNU/Linux/Microblaze specific low level interface, for the remote server for ++ GDB. ++ Copyright (C) 1995-2013 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include "server.h" ++#include "linux-low.h" ++ ++#include "elf/common.h" ++#include "nat/gdb_ptrace.h" ++#include ++ ++#include ++#include ++#include ++ ++#include "gdb_proc_service.h" ++ ++ ++static int microblaze_regmap[] = ++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3), ++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7), ++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11), ++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15), ++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19), ++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23), ++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27), ++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31), ++ PT_PC, PT_MSR, PT_EAR, PT_ESR, ++ PT_FSR ++ }; ++ ++ ++ ++class microblaze_target : public linux_process_target ++{ ++public: ++ ++ const regs_info *get_regs_info () override; ++ ++ const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; ++ // CORE_ADDR microblaze_reinsert_addr (regcache *regcache); ++ ++protected: ++ ++ void low_arch_setup () override; ++ ++ bool low_cannot_fetch_register (int regno) override; ++ ++ bool low_cannot_store_register (int regno) override; ++ ++ // bool low_supports_breakpoints () override; ++ ++ CORE_ADDR low_get_pc (regcache *regcache) override; ++ ++ void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; ++ ++ bool low_breakpoint_at (CORE_ADDR pc) override; ++}; ++ ++/* The singleton target ops object. */ ++ ++static microblaze_target the_microblaze_target; ++ ++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0])) ++ ++/* Defined in auto-generated file microblaze-linux.c. */ ++void init_registers_microblaze_linux (void); ++extern const struct target_desc *tdesc_microblaze_linux; ++ ++bool ++microblaze_target::low_cannot_store_register (int regno) ++{ ++ if (microblaze_regmap[regno] == -1 || regno == 0) ++ return 1; ++ ++ return 0; ++} ++ ++bool ++microblaze_target::low_cannot_fetch_register (int regno) ++{ ++ return 0; ++} ++ ++CORE_ADDR ++microblaze_target::low_get_pc (struct regcache *regcache) ++{ ++ unsigned long pc; ++ ++ collect_register_by_name (regcache, "pc", &pc); ++ return (CORE_ADDR) pc; ++} ++ ++void ++microblaze_target::low_set_pc (struct regcache *regcache, CORE_ADDR pc) ++{ ++ unsigned long newpc = pc; ++ ++ supply_register_by_name (regcache, "pc", &newpc); ++} ++ ++/* dbtrap insn */ ++/* brki r16, 0x18; */ ++static const unsigned long microblaze_breakpoint = 0xba0c0018; ++#define microblaze_breakpoint_len 4 ++ ++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ ++ ++const gdb_byte * ++microblaze_target::sw_breakpoint_from_kind (int kind, int *size) ++{ ++ *size = microblaze_breakpoint_len; ++ return (const gdb_byte *) µblaze_breakpoint; ++} ++ ++bool ++microblaze_target::low_breakpoint_at (CORE_ADDR where) ++{ ++ unsigned long insn; ++ ++ read_memory (where, (unsigned char *) &insn, 4); ++ if (insn == microblaze_breakpoint) ++ return 1; ++ /* If necessary, recognize more trap instructions here. GDB only uses the ++ one. */ ++ return 0; ++} ++#if 0 ++CORE_ADDR ++microblaze_target::microblaze_reinsert_addr (struct regcache *regcache) ++{ ++ unsigned long pc; ++ collect_register_by_name (regcache, "r15", &pc); ++ return pc; ++} ++#endif ++#if 0 ++#ifdef HAVE_PTRACE_GETREGS ++ ++static void ++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) ++{ ++ int size = register_size (regcache->tdesc, regno); ++ ++ memset (buf, 0, sizeof (long)); ++ ++ if (size < sizeof (long)) ++ collect_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ collect_register (regcache, regno, buf); ++} ++ ++static void ++microblaze_supply_ptrace_register (struct regcache *regcache, ++ int regno, const char *buf) ++{ ++ int size = register_size (regcache->tdesc, regno); ++ ++ if (regno == 0) { ++ unsigned long regbuf_0 = 0; ++ /* clobbering r0 so that it is always 0 as enforced by hardware */ ++ supply_register (regcache, regno, (const char*)®buf_0); ++ } else { ++ if (size < sizeof (long)) ++ supply_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ supply_register (regcache, regno, buf); ++ } ++} ++ ++/* Provide only a fill function for the general register set. ps_lgetregs ++ will use this for NPTL support. */ ++ ++static void microblaze_fill_gregset (struct regcache *regcache, void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++static void ++microblaze_store_gregset (struct regcache *regcache, const void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++#endif /* HAVE_PTRACE_GETREGS */ ++#endif ++ ++static struct regset_info microblaze_regsets[] = { ++#if 0 ++#ifdef HAVE_PTRACE_GETREGS ++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, ++#endif /* HAVE_PTRACE_GETREGS */ ++#endif ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, ++ NULL_REGSET ++}; ++ ++static struct usrregs_info microblaze_usrregs_info = ++ { ++ microblaze_num_regs, ++ microblaze_regmap, ++ }; ++ ++static struct regsets_info microblaze_regsets_info = ++ { ++ microblaze_regsets, /* regsets */ ++ 0, /* num_regsets */ ++ NULL, /* disabled_regsets */ ++ }; ++ ++static struct regs_info microblaze_regs_info = ++ { ++ NULL, /* regset_bitmap */ ++ µblaze_usrregs_info, ++ µblaze_regsets_info ++ }; ++ ++const regs_info * ++microblaze_target::get_regs_info (void) ++{ ++ return µblaze_regs_info; ++} ++ ++/* Support for hardware single step. */ ++ ++static int ++microblaze_supports_hardware_single_step (void) ++{ ++ return 1; ++} ++ ++ ++void ++microblaze_target::low_arch_setup (void) ++{ ++ current_process ()->tdesc = tdesc_microblaze_linux; ++} ++ ++linux_process_target *the_linux_target = &the_microblaze_target; ++ ++void ++initialize_low_arch (void) ++{ ++ init_registers_microblaze_linux (); ++ initialize_regsets_info (µblaze_regsets_info); ++} ++ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0003-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0003-Initial-port-of-core-reading-support-Added-support-f.patch new file mode 100644 index 00000000..c0515aa6 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0003-Initial-port-of-core-reading-support-Added-support-f.patch @@ -0,0 +1,301 @@ +From 67943e124abc6b1228d84399fbde5b129015ac7f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 16:37:53 +0530 +Subject: [PATCH 03/53] Initial port of core reading support Added support for + reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO + information for rebuilding ".reg" sections of core dumps at run time. + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + bfd/elf32-microblaze.c | 84 +++++++++++++++++++++++++++++++++++++ + gdb/configure.tgt | 2 +- + gdb/microblaze-linux-tdep.c | 17 +++++++- + gdb/microblaze-tdep.c | 48 +++++++++++++++++++++ + gdb/microblaze-tdep.h | 28 +++++++++++++ + 5 files changed, 177 insertions(+), 2 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 64198b8f1a6..022ce365c59 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -772,6 +772,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name) + return _bfd_elf_is_local_label_name (abfd, name); + } + ++/* Support for core dump NOTE sections. */ ++static bool ++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) ++{ ++ int offset; ++ unsigned int size; ++ ++ switch (note->descsz) ++ { ++ default: ++ return false; ++ ++ case 228: /* Linux/MicroBlaze */ ++ /* pr_cursig */ ++ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); ++ ++ /* pr_pid */ ++ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24); ++ ++ /* pr_reg */ ++ offset = 72; ++ size = 50 * 4; ++ ++ break; ++ } ++ ++ /* Make a ".reg/999" section. */ ++ return _bfd_elfcore_make_pseudosection (abfd, ".reg", ++ size, note->descpos + offset); ++} ++ ++static bool ++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) ++{ ++ switch (note->descsz) ++ { ++ default: ++ return false; ++ ++ case 128: /* Linux/MicroBlaze elf_prpsinfo */ ++ elf_tdata (abfd)->core->program ++ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16); ++ elf_tdata (abfd)->core->command ++ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80); ++ } ++ ++ /* Note that for some reason, a spurious space is tacked ++ onto the end of the args in some (at least one anyway) ++ implementations, so strip it off if it exists. */ ++ ++ { ++ char *command = elf_tdata (abfd)->core->command; ++ int n = strlen (command); ++ ++ if (0 < n && command[n - 1] == ' ') ++ command[n - 1] = '\0'; ++ } ++ ++ return true; ++} ++ ++/* The microblaze linker (like many others) needs to keep track of ++ the number of relocs that it decides to copy as dynamic relocs in ++ check_relocs for each symbol. This is so that it can later discard ++ them if they are found to be unnecessary. We store the information ++ in a field extending the regular ELF linker hash table. */ ++ ++struct elf32_mb_dyn_relocs ++{ ++ struct elf32_mb_dyn_relocs *next; ++ ++ /* The input section of the reloc. */ ++ asection *sec; ++ ++ /* Total number of relocs copied for the input section. */ ++ bfd_size_type count; ++ ++ /* Number of pc-relative relocs copied for the input section. */ ++ bfd_size_type pc_count; ++}; ++ + /* ELF linker hash entry. */ + + struct elf32_mb_link_hash_entry +@@ -3500,4 +3581,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd, + #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections + #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook + ++#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus ++#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo ++ + #include "elf32-target.h" +diff --git a/gdb/configure.tgt b/gdb/configure.tgt +index 47a674201f9..d0673abd2b8 100644 +--- a/gdb/configure.tgt ++++ b/gdb/configure.tgt +@@ -415,7 +415,7 @@ mep-*-*) + + microblaze*-linux-*|microblaze*-*-linux*) + # Target: Xilinx MicroBlaze running Linux +- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \ ++ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \ + symfile-mem.o linux-tdep.o" + ;; + microblaze*-*-*) +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index d25100ef867..eef09bacec0 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -36,6 +36,7 @@ + #include "frame-unwind.h" + #include "tramp-frame.h" + #include "linux-tdep.h" ++#include "glibc-tdep.h" + + static int microblaze_debug_flag = 0; + +@@ -135,11 +136,14 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame = + microblaze_linux_sighandler_cache_init + }; + +- + static void + microblaze_linux_init_abi (struct gdbarch_info info, + struct gdbarch *gdbarch) + { ++ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ ++ tdep->sizeof_gregset = 200; ++ + linux_init_abi (info, gdbarch, 0); + + set_gdbarch_memory_remove_breakpoint (gdbarch, +@@ -153,6 +157,17 @@ microblaze_linux_init_abi (struct gdbarch_info info, + tramp_frame_prepend_unwinder (gdbarch, + µblaze_linux_sighandler_tramp_frame); + ++ /* BFD target for core files. */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ ++ ++ /* Shared library handling. */ ++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); ++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); ++ + /* Enable TLS support. */ + set_gdbarch_fetch_tls_load_module_address (gdbarch, + svr4_fetch_objfile_link_map); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 3ff7ec644b6..7c98331f8a9 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -665,6 +665,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) + tdesc_microblaze_with_stack_protect); + } + ++void ++microblaze_supply_gregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *gregs) ++{ ++ const unsigned int *regs = (const unsigned int *)gregs; ++ if (regnum >= 0) ++ regcache->raw_supply (regnum, regs + regnum); ++ ++ if (regnum == -1) { ++ int i; ++ ++ for (i = 0; i < 50; i++) { ++ regcache->raw_supply (i, regs + i); ++ } ++ } ++} ++ ++ ++/* Return the appropriate register set for the core section identified ++ by SECT_NAME and SECT_SIZE. */ ++ ++static void ++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, ++ iterate_over_regset_sections_cb *cb, ++ void *cb_data, ++ const struct regcache *regcache) ++{ ++ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ ++ cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); ++ ++ cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); ++} ++ ++ ++ + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { +@@ -716,6 +753,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + gdbarch *gdbarch + = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep)); + ++ tdep->gregset = NULL; ++ tdep->sizeof_gregset = 0; ++ tdep->fpregset = NULL; ++ tdep->sizeof_fpregset = 0; + set_gdbarch_long_double_bit (gdbarch, 128); + + set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS); +@@ -764,6 +805,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); + if (tdesc_data != NULL) + tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); ++ //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); ++ ++ /* If we have register sets, enable the generic core file support. */ ++ if (tdep->gregset) { ++ set_gdbarch_iterate_over_regset_sections (gdbarch, ++ microblaze_iterate_over_regset_sections); ++ } + + return gdbarch; + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 56736b9b0c9..07a160a463c 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -23,8 +23,23 @@ + #include "gdbarch.h" + + /* Microblaze architecture-specific information. */ ++struct microblaze_gregset ++{ ++ microblaze_gregset() {} ++ unsigned int gregs[32]; ++ unsigned int fpregs[32]; ++ unsigned int pregs[16]; ++}; ++ + struct microblaze_gdbarch_tdep : gdbarch_tdep_base + { ++ int dummy; // declare something. ++ ++ /* Register sets. */ ++ struct regset *gregset; ++ size_t sizeof_gregset; ++ struct regset *fpregset; ++ size_t sizeof_fpregset; + }; + + /* Register numbers. */ +@@ -121,5 +136,18 @@ struct microblaze_frame_cache + #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} + #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} + ++extern void microblaze_supply_gregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *gregs); ++extern void microblaze_collect_gregset (const struct regset *regset, ++ const struct regcache *regcache, ++ int regnum, void *gregs); ++extern void microblaze_supply_fpregset (struct regcache *regcache, ++ int regnum, const void *fpregs); ++extern void microblaze_collect_fpregset (const struct regcache *regcache, ++ int regnum, void *fpregs); ++ ++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch, ++ const char *sect_name, size_t sect_size); + + #endif /* microblaze-tdep.h */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0004-Fix-debug-message-when-register-is-unavailable.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0004-Fix-debug-message-when-register-is-unavailable.patch new file mode 100644 index 00000000..1383efd8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0004-Fix-debug-message-when-register-is-unavailable.patch @@ -0,0 +1,45 @@ +From 087f77ebdbdf5b9b5d199ba92b31c6503cb66b37 Mon Sep 17 00:00:00 2001 +From: Nathan Rossi +Date: Tue, 8 May 2012 18:11:17 +1000 +Subject: [PATCH 04/53] Fix debug message when register is unavailable + +Signed-off-by: Nathan Rossi + +Conflicts: + gdb/frame.c +Signed-off-by: Aayush Misra +--- + gdb/frame.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/gdb/frame.c b/gdb/frame.c +index d95d63eb0f6..859e1a6553d 100644 +--- a/gdb/frame.c ++++ b/gdb/frame.c +@@ -1317,12 +1317,20 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum) + else + { + int i; +- gdb::array_view buf = value->contents (); ++ ++ const gdb_byte *buf = NULL; ++ if (value_entirely_available(value)) { ++ gdb::array_view buf = value->contents (); ++ } + + gdb_printf (&debug_file, " bytes="); + gdb_printf (&debug_file, "["); +- for (i = 0; i < register_size (gdbarch, regnum); i++) +- gdb_printf (&debug_file, "%02x", buf[i]); ++ if (buf != NULL) { ++ for (i = 0; i < register_size (gdbarch, regnum); i++) ++ gdb_printf (&debug_file, "%02x", buf[i]); ++ } else { ++ gdb_printf (&debug_file, "unavailable"); ++ } + gdb_printf (&debug_file, "]"); + } + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0005-MicroBlaze-native-gdb-port.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0005-MicroBlaze-native-gdb-port.patch new file mode 100644 index 00000000..75c06b62 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0005-MicroBlaze-native-gdb-port.patch @@ -0,0 +1,834 @@ +From 5b633480eb0b45dc15b6416c54535c54c062d23c Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 18:53:46 +0530 +Subject: [PATCH 05/53] MicroBlaze native gdb port. + +signed-off-by : Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + gdb/Makefile.in | 2 + + gdb/configure.nat | 4 + + gdb/features/microblaze-linux.c | 79 +++++++ + gdb/microblaze-linux-nat.c | 366 ++++++++++++++++++++++++++++++++ + gdb/microblaze-linux-tdep.c | 2 + + gdb/microblaze-linux-tdep.h | 24 +++ + gdb/microblaze-tdep.c | 151 ++++++++++++- + gdb/microblaze-tdep.h | 15 +- + 8 files changed, 629 insertions(+), 14 deletions(-) + create mode 100755 gdb/features/microblaze-linux.c + create mode 100755 gdb/microblaze-linux-nat.c + create mode 100644 gdb/microblaze-linux-tdep.h + +diff --git a/gdb/Makefile.in b/gdb/Makefile.in +index 0e0f19c40c9..056588d88d0 100644 +--- a/gdb/Makefile.in ++++ b/gdb/Makefile.in +@@ -1409,6 +1409,7 @@ HFILES_NO_SRCDIR = \ + memory-map.h \ + memrange.h \ + microblaze-tdep.h \ ++ microblaze-linux-tdep.h \ + mips-linux-tdep.h \ + mips-netbsd-tdep.h \ + mips-tdep.h \ +@@ -1757,6 +1758,7 @@ ALLDEPFILES = \ + m68k-linux-nat.c \ + m68k-linux-tdep.c \ + m68k-tdep.c \ ++ microblaze-linux-nat.c \ + microblaze-linux-tdep.c \ + microblaze-tdep.c \ + mingw-hdep.c \ +diff --git a/gdb/configure.nat b/gdb/configure.nat +index 8b98511cef7..c9f0fb25010 100644 +--- a/gdb/configure.nat ++++ b/gdb/configure.nat +@@ -274,6 +274,10 @@ case ${gdb_host} in + # Host: Motorola m68k running GNU/Linux. + NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o" + ;; ++ microblaze) ++ # Host: Microblaze running GNU/Linux. ++ NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o" ++ ;; + mips) + # Host: Linux/MIPS + NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \ +diff --git a/gdb/features/microblaze-linux.c b/gdb/features/microblaze-linux.c +new file mode 100755 +index 00000000000..267e12f6d59 +--- /dev/null ++++ b/gdb/features/microblaze-linux.c +@@ -0,0 +1,79 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze_linux; ++static void ++initialize_tdesc_microblaze_linux (void) ++{ ++ target_desc_up result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ set_tdesc_architecture (result.get(), bfd_scan_arch ("microblaze")); ++ set_tdesc_osabi (result.get(), osabi_from_tdesc_string ("GNU/Linux")); ++ ++ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze_linux = result.release(); ++} +diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c +new file mode 100755 +index 00000000000..a348001a3e2 +--- /dev/null ++++ b/gdb/microblaze-linux-nat.c +@@ -0,0 +1,366 @@ ++/* Native-dependent code for GNU/Linux MicroBlaze. ++ Copyright (C) 2021 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include "defs.h" ++#include "arch-utils.h" ++#include "dis-asm.h" ++#include "frame.h" ++#include "trad-frame.h" ++#include "symtab.h" ++#include "value.h" ++#include "gdbcmd.h" ++#include "breakpoint.h" ++#include "inferior.h" ++#include "gdbthread.h" ++#include "gdbcore.h" ++#include "regcache.h" ++#include "regset.h" ++#include "target.h" ++#include "frame.h" ++#include "frame-base.h" ++#include "frame-unwind.h" ++#include "osabi.h" ++#include "gdbsupport/gdb_assert.h" ++#include ++#include "target-descriptions.h" ++#include "opcodes/microblaze-opcm.h" ++#include "opcodes/microblaze-dis.h" ++#include "gregset.h" ++ ++#include "linux-nat.h" ++#include "linux-tdep.h" ++#include "target-descriptions.h" ++ ++#include ++#include ++#include ++#include "gdbsupport/gdb_wait.h" ++#include ++#include ++#include "nat/gdb_ptrace.h" ++#include "nat/linux-ptrace.h" ++#include "inf-ptrace.h" ++#include ++#include ++#include ++#include ++ ++/* Prototypes for supply_gregset etc. */ ++#include "gregset.h" ++ ++#include "microblaze-tdep.h" ++#include "microblaze-linux-tdep.h" ++#include "inferior.h" ++ ++#include "elf/common.h" ++ ++#include "auxv.h" ++#include "linux-tdep.h" ++ ++#include ++ ++ ++//int have_ptrace_getsetregs=1; ++ ++/* MicroBlaze Linux native additions to the default linux support. */ ++ ++class microblaze_linux_nat_target final : public linux_nat_target ++{ ++public: ++ /* Add our register access methods. */ ++ void fetch_registers (struct regcache *regcache, int regnum) override; ++ void store_registers (struct regcache *regcache, int regnum) override; ++ ++ /* Read suitable target description. */ ++ const struct target_desc *read_description () override; ++}; ++ ++static microblaze_linux_nat_target the_microblaze_linux_nat_target; ++ ++static int ++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) ++{ ++ int u_addr = -1; ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace ++ * interface, and not the wordsize of the program's ABI. */ ++ int wordsize = sizeof (long); ++ ++ /* General purpose registers occupy 1 slot each in the buffer. */ ++ if (regno >= MICROBLAZE_R0_REGNUM ++ && regno <= MICROBLAZE_FSR_REGNUM) ++ u_addr = ((regno - MICROBLAZE_R0_REGNUM)* wordsize); ++ ++ return u_addr; ++} ++ ++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) ++ from regset GREGS into REGCACHE. */ ++ ++static void ++supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs, ++ int regnum) ++{ ++ int i; ++ const elf_greg_t *regp = *gregs; ++ /* Access all registers */ ++ if (regnum == -1) ++ { ++ /* We fill the general purpose registers. */ ++ for (i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) ++ regcache->raw_supply (i, regp + i); ++ ++ /* Supply MICROBLAZE_PC_REGNUM from index 32. */ ++ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); ++ ++ /* Fill the inaccessible zero register with zero. */ ++ regcache->raw_supply_zeroed (0); ++ } ++ else if (regnum == MICROBLAZE_R0_REGNUM) ++ regcache->raw_supply_zeroed (0); ++ else if (regnum == MICROBLAZE_PC_REGNUM) ++ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); ++ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) ++ regcache->raw_supply (regnum, regp + regnum); ++} ++ ++/* Copy all general purpose registers from regset GREGS into REGCACHE. */ ++ ++void ++supply_gregset (struct regcache *regcache, const prgregset_t *gregs) ++{ ++ supply_gregset_regnum (regcache, gregs, -1); ++} ++ ++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) ++ from REGCACHE into regset GREGS. */ ++ ++void ++fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum) ++{ ++ elf_greg_t *regp = *gregs; ++ if (regnum == -1) ++ { ++ /* We fill the general purpose registers. */ ++ for (int i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) ++ regcache->raw_collect (i, regp + i); ++ ++ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); ++ } ++ else if (regnum == MICROBLAZE_R0_REGNUM) ++ /* Nothing to do here. */ ++ ; ++ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) ++ regcache->raw_collect (regnum, regp + regnum); ++ else if (regnum == MICROBLAZE_PC_REGNUM) ++ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); ++} ++ ++/* Transfering floating-point registers between GDB, inferiors and cores. ++ Since MicroBlaze floating-point registers are the same as GPRs these do ++ nothing. */ ++ ++void ++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregs) ++{ ++} ++ ++void ++fill_fpregset (const struct regcache *regcache, ++ gdb_fpregset_t *fpregs, int regno) ++{ ++} ++ ++ ++static void ++fetch_register (struct regcache *regcache, int tid, int regno) ++{ ++ struct gdbarch *gdbarch = regcache->arch (); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int bytes_transferred; ++ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ { ++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ ++ regcache->raw_supply (regno, buf); ++ return; ++ } ++ ++ /* Read the raw register using sizeof(long) sized chunks. On a ++ * 32-bit platform, 64-bit floating-point registers will require two ++ * transfers. */ ++ for (bytes_transferred = 0; ++ bytes_transferred < register_size (gdbarch, regno); ++ bytes_transferred += sizeof (long)) ++ { ++ long l; ++ ++ errno = 0; ++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); ++ if (errno == EIO) ++ { ++ printf("ptrace io error\n"); ++ } ++ regaddr += sizeof (long); ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "reading register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ memcpy (&buf[bytes_transferred], &l, sizeof (l)); ++ } ++ ++ /* Now supply the register. Keep in mind that the regcache's idea ++ * of the register's size may not be a multiple of sizeof ++ * (long). */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values are always found at the left end of the ++ * bytes transferred. */ ++ regcache->raw_supply (regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values are found at the right end of the bytes ++ * transferred. */ ++ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); ++ regcache->raw_supply (regno, buf + padding); ++ } ++ else ++ internal_error (__FILE__, __LINE__, ++ _("fetch_register: unexpected byte order: %d"), ++ gdbarch_byte_order (gdbarch)); ++} ++ ++ ++/* This is a wrapper for the fetch_all_gp_regs function. It is ++ * responsible for verifying if this target has the ptrace request ++ * that can be used to fetch all general-purpose registers at one ++ * shot. If it doesn't, then we should fetch them using the ++ * old-fashioned way, which is to iterate over the registers and ++ * request them one by one. */ ++static void ++fetch_gp_regs (struct regcache *regcache, int tid) ++{ ++ int i; ++/* If we've hit this point, it doesn't really matter which ++ architecture we are using. We just need to read the ++ registers in the "old-fashioned way". */ ++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) ++ fetch_register (regcache, tid, i); ++} ++ ++/* Return a target description for the current target. */ ++ ++const struct target_desc * ++microblaze_linux_nat_target::read_description () ++{ ++ return tdesc_microblaze_linux; ++} ++ ++/* Fetch REGNUM (or all registers if REGNUM == -1) from the target ++ into REGCACHE using PTRACE_GETREGSET. */ ++ ++void ++microblaze_linux_nat_target::fetch_registers (struct regcache * regcache, ++ int regno) ++{ ++ /* Get the thread id for the ptrace call. */ ++ int tid = regcache->ptid ().lwp (); ++//int tid = get_ptrace_pid (regcache->ptid()); ++#if 1 ++ if (regno == -1) ++#endif ++ fetch_gp_regs (regcache, tid); ++#if 1 ++ else ++ fetch_register (regcache, tid, regno); ++#endif ++} ++ ++ ++/* Store REGNUM (or all registers if REGNUM == -1) to the target ++ from REGCACHE using PTRACE_SETREGSET. */ ++ ++void ++microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno) ++{ ++ int tid; ++ ++ tid = get_ptrace_pid (regcache->ptid ()); ++ ++ struct gdbarch *gdbarch = regcache->arch (); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int i; ++ size_t bytes_to_transfer; ++ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ return; ++ ++ /* First collect the register. Keep in mind that the regcache's ++ * idea of the register's size may not be a multiple of sizeof ++ * (long). */ ++ memset (buf, 0, sizeof buf); ++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values always sit at the left end of the buffer. */ ++ regcache->raw_collect (regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values sit at the right end of the buffer. */ ++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); ++ regcache->raw_collect (regno, buf + padding); ++ } ++ ++ for (i = 0; i < bytes_to_transfer; i += sizeof (long)) ++ { ++ long l; ++ ++ memcpy (&l, &buf[i], sizeof (l)); ++ errno = 0; ++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); ++ regaddr += sizeof (long); ++ ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "writing register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ } ++} ++ ++void _initialize_microblaze_linux_nat (void); ++ ++void ++_initialize_microblaze_linux_nat (void) ++{ ++ /* Register the target. */ ++ linux_target = &the_microblaze_linux_nat_target; ++ add_inf_child_target (linux_target); ++} +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index eef09bacec0..d086debc4f8 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,6 +37,7 @@ + #include "tramp-frame.h" + #include "linux-tdep.h" + #include "glibc-tdep.h" ++#include "features/microblaze-linux.c" + + static int microblaze_debug_flag = 0; + +@@ -179,4 +180,5 @@ _initialize_microblaze_linux_tdep () + { + gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, + microblaze_linux_init_abi); ++ initialize_tdesc_microblaze_linux (); + } +diff --git a/gdb/microblaze-linux-tdep.h b/gdb/microblaze-linux-tdep.h +new file mode 100644 +index 00000000000..a2c744e2961 +--- /dev/null ++++ b/gdb/microblaze-linux-tdep.h +@@ -0,0 +1,24 @@ ++/* Target-dependent code for GNU/Linux on OpenRISC. ++ ++ Copyright (C) 2021 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++#ifndef MICROBLAZE_LINUX_TDEP_H ++#define MICROBLAZE_LINUX_TDEP_H ++ /* Target descriptions. */ ++ extern struct target_desc *tdesc_microblaze_linux; ++ ++#endif /* MICROBLAZE_LINUX_TDEP_H */ +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 7c98331f8a9..b0b4c1b2614 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -285,6 +285,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, + cache->frameless_p = 0; /* Frame found. */ + save_hidden_pointer_found = 0; + non_stack_instruction_found = 0; ++ cache->register_offsets[rd] = -imm; + continue; + } + else if (IS_SPILL_SP(op, rd, ra)) +@@ -431,15 +432,17 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) + if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) + { + sal = find_pc_line (func_start, 0); +- +- if (sal.end < func_end +- && start_pc <= sal.end) ++ ++ if (sal.line !=0 && sal.end <= func_end && start_pc <= sal.end) { + start_pc = sal.end; ++ microblaze_debug("start_pc is %d\t sal.end is %d\t func_end is %d\t",start_pc,sal.end,func_end); ++ } + } + + ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, + &cache); + ++ + if (ostart_pc > start_pc) + return ostart_pc; + return start_pc; +@@ -453,6 +456,7 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache) + struct microblaze_frame_cache *cache; + struct gdbarch *gdbarch = get_frame_arch (next_frame); + int rn; ++ CORE_ADDR current_pc; + + if (*this_cache) + return (struct microblaze_frame_cache *) *this_cache; +@@ -466,10 +470,17 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache) + cache->register_offsets[rn] = -1; + + /* Call for side effects. */ +- get_frame_func (next_frame); +- +- cache->pc = get_frame_address_in_block (next_frame); +- ++ cache->pc = get_frame_func (next_frame); ++ ++// cache->pc = get_frame_address_in_block (next_frame); ++ current_pc = get_frame_pc (next_frame); ++ if (cache->pc) ++ microblaze_analyze_prologue (gdbarch, cache->pc, current_pc, cache); ++ ++ cache->saved_sp = cache->base + cache->framesize; ++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base; ++ cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp; ++ + return cache; + } + +@@ -494,6 +505,25 @@ microblaze_frame_prev_register (frame_info_ptr this_frame, + struct microblaze_frame_cache *cache = + microblaze_frame_cache (this_frame, this_cache); + ++if ((regnum == MICROBLAZE_SP_REGNUM && ++ cache->register_offsets[MICROBLAZE_SP_REGNUM]) ++ || (regnum == MICROBLAZE_FP_REGNUM && ++ cache->register_offsets[MICROBLAZE_SP_REGNUM])) ++ ++ return frame_unwind_got_constant (this_frame, regnum, ++ cache->register_offsets[MICROBLAZE_SP_REGNUM]); ++ ++if (regnum == MICROBLAZE_PC_REGNUM) ++{ ++ regnum = 15; ++ return frame_unwind_got_memory (this_frame, regnum, ++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]); ++ ++} ++if (regnum == MICROBLAZE_SP_REGNUM) ++ regnum = 1; ++#if 0 ++ + if (cache->frameless_p) + { + if (regnum == MICROBLAZE_PC_REGNUM) +@@ -506,7 +536,9 @@ microblaze_frame_prev_register (frame_info_ptr this_frame, + else + return trad_frame_get_prev_register (this_frame, cache->saved_regs, + regnum); +- ++#endif ++ return trad_frame_get_prev_register (this_frame, cache->saved_regs, ++ regnum); + } + + static const struct frame_unwind microblaze_frame_unwind = +@@ -621,7 +653,106 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) + return (type->length () == 16); + } + +- ++#if 1 ++static std::vector ++microblaze_software_single_step (struct regcache *regcache) ++{ ++ struct gdbarch *arch = regcache->arch (); ++ //struct gdbarch_tdep *tdep = gdbarch_tdep (arch); ++ static int le_breakp[] = MICROBLAZE_BREAKPOINT_LE; ++ static int be_breakp[] = MICROBLAZE_BREAKPOINT; ++ enum bfd_endian byte_order = gdbarch_byte_order (arch); ++ int *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp; ++// std::vector ret = NULL; ++ ++ /* Save the address and the values of the next_pc and the target */ ++ static struct sstep_breaks ++ { ++ CORE_ADDR address; ++ bfd_boolean valid; ++ /* Shadow contents. */ ++ char data[INST_WORD_SIZE]; ++ } stepbreaks[2]; ++ int ii; ++ ++ CORE_ADDR pc; ++ std::vector next_pcs; ++ long insn; ++ enum microblaze_instr minstr; ++ bfd_boolean isunsignednum; ++ enum microblaze_instr_type insn_type; ++ short delay_slots; ++ int imm; ++ bfd_boolean immfound = FALSE; ++ ++ /* Set a breakpoint at the next instruction */ ++ /* If the current instruction is an imm, set it at the inst after */ ++ /* If the instruction has a delay slot, skip the delay slot */ ++ pc = regcache_read_pc (regcache); ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ if (insn_type == immediate_inst) ++ { ++ int rd, ra, rb; ++ immfound = TRUE; ++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); ++ pc = pc + INST_WORD_SIZE; ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ } ++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE; ++ if (insn_type != return_inst) { ++ stepbreaks[0].valid = TRUE; ++ } else { ++ stepbreaks[0].valid = FALSE; ++ } ++ ++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn); ++ /* Now check for branch or return instructions */ ++ if (insn_type == branch_inst || insn_type == return_inst) { ++ int limm; ++ int lrd, lra, lrb; ++ int ra, rb; ++ bfd_boolean targetvalid; ++ bfd_boolean unconditionalbranch; ++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm); ++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS) ++ ra = regcache_raw_get_unsigned(regcache, lra); ++ else ++ ra = 0; ++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS) ++ rb = regcache_raw_get_unsigned(regcache, lrb); ++ else ++ rb = 0; ++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch); ++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address); ++ if (unconditionalbranch) ++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */ ++ if (targetvalid && (stepbreaks[0].valid == FALSE || ++ (stepbreaks[0].address != stepbreaks[1].address)) ++ && (stepbreaks[1].address != pc)) { ++ stepbreaks[1].valid = TRUE; ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ ++ /* Insert the breakpoints */ ++ for (ii = 0; ii < 2; ++ii) ++ { ++ ++ /* ignore invalid breakpoint. */ ++ if (stepbreaks[ii].valid) { ++ // VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);; ++ next_pcs.push_back (stepbreaks[ii].address); ++ } ++ } ++ return next_pcs; ++} ++#endif ++ + static int dwarf2_to_reg_map[78] = + { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ + 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ +@@ -788,6 +919,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::bp_from_kind); + set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + ++ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); ++ + set_gdbarch_frame_args_skip (gdbarch, 8); + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 07a160a463c..c4c8098308f 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -60,11 +60,11 @@ enum microblaze_regnum + MICROBLAZE_R12_REGNUM, + MICROBLAZE_R13_REGNUM, + MICROBLAZE_R14_REGNUM, +- MICROBLAZE_R15_REGNUM, ++ MICROBLAZE_R15_REGNUM,MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM, + MICROBLAZE_R16_REGNUM, + MICROBLAZE_R17_REGNUM, + MICROBLAZE_R18_REGNUM, +- MICROBLAZE_R19_REGNUM, ++ MICROBLAZE_R19_REGNUM,MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM, + MICROBLAZE_R20_REGNUM, + MICROBLAZE_R21_REGNUM, + MICROBLAZE_R22_REGNUM, +@@ -77,7 +77,8 @@ enum microblaze_regnum + MICROBLAZE_R29_REGNUM, + MICROBLAZE_R30_REGNUM, + MICROBLAZE_R31_REGNUM, +- MICROBLAZE_PC_REGNUM, ++ MICROBLAZE_MAX_GPR_REGS, ++ MICROBLAZE_PC_REGNUM=32, + MICROBLAZE_MSR_REGNUM, + MICROBLAZE_EAR_REGNUM, + MICROBLAZE_ESR_REGNUM, +@@ -102,17 +103,21 @@ enum microblaze_regnum + MICROBLAZE_RTLBSX_REGNUM, + MICROBLAZE_RTLBLO_REGNUM, + MICROBLAZE_RTLBHI_REGNUM, +- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM, ++ MICROBLAZE_SLR_REGNUM, + MICROBLAZE_SHR_REGNUM, +- MICROBLAZE_NUM_REGS ++ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS + }; + ++/* Big enough to hold the size of the largest register in bytes. */ ++#define MICROBLAZE_MAX_REGISTER_SIZE 64 ++ + struct microblaze_frame_cache + { + /* Base address. */ + CORE_ADDR base; + CORE_ADDR pc; + ++ CORE_ADDR saved_sp; + /* Do we have a frame? */ + int frameless_p; + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch new file mode 100644 index 00000000..a61c17d9 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch @@ -0,0 +1,1841 @@ +From ff4596845becf48fa17f06ea30a59658e9722e06 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 31 Jan 2019 14:36:00 +0530 +Subject: [PATCH 06/53] Adding 64 bit MB support Added new architecture to + Microblaze 64-bit support to GDB Signed-off-by :Nagaraju Mekala + Signed-off-by :Mahesh Bodapati + +Conflicts: + gdb/Makefile.in + +Conflicts: + bfd/cpu-microblaze.c + gdb/microblaze-tdep.c + ld/Makefile.am + ld/Makefile.in + opcodes/microblaze-dis.c + +Conflicts: + bfd/configure + gas/config/tc-microblaze.c + ld/Makefile.in + opcodes/microblaze-opcm.h + +Conflicts: + gdb/microblaze-tdep.c + +Conflicts: + bfd/elf32-microblaze.c + gas/config/tc-microblaze.c + gdb/features/Makefile + gdb/features/microblaze-with-stack-protect.c + gdb/microblaze-tdep.c + gdb/regformats/microblaze-with-stack-protect.dat + gdbserver/linux-microblaze-low.c + include/elf/common.h + +Signed-off-by: Aayush Misra +--- + bfd/Makefile.am | 2 + + bfd/Makefile.in | 3 + + bfd/archures.c | 2 + + bfd/bfd-in2.h | 41 ++++- + bfd/config.bfd | 4 + + bfd/configure | 2 + + bfd/cpu-microblaze.c | 55 +++++- + bfd/elf32-microblaze.c | 133 ++++++++++++-- + bfd/libbfd.h | 2 + + bfd/reloc.c | 20 +++ + bfd/targets.c | 6 + + gdb/features/Makefile | 2 + + gdb/features/microblaze-core.xml | 6 +- + gdb/features/microblaze-stack-protect.xml | 4 +- + gdb/features/microblaze-with-stack-protect.c | 8 +- + gdb/features/microblaze.c | 6 +- + gdb/features/microblaze64-core.xml | 69 ++++++++ + gdb/features/microblaze64-stack-protect.xml | 12 ++ + .../microblaze64-with-stack-protect.c | 79 +++++++++ + .../microblaze64-with-stack-protect.xml | 12 ++ + gdb/features/microblaze64.c | 77 +++++++++ + gdb/features/microblaze64.xml | 11 ++ + gdb/microblaze-linux-tdep.c | 36 +++- + gdb/microblaze-tdep.c | 125 ++++++++++---- + gdb/microblaze-tdep.h | 4 +- + include/elf/common.h | 1 + + include/elf/microblaze.h | 2 + + opcodes/microblaze-dis.c | 52 +++--- + opcodes/microblaze-opc.h | 162 ++++++++++++++++-- + opcodes/microblaze-opcm.h | 24 ++- + 30 files changed, 853 insertions(+), 109 deletions(-) + create mode 100644 gdb/features/microblaze64-core.xml + create mode 100644 gdb/features/microblaze64-stack-protect.xml + create mode 100644 gdb/features/microblaze64-with-stack-protect.c + create mode 100644 gdb/features/microblaze64-with-stack-protect.xml + create mode 100644 gdb/features/microblaze64.c + create mode 100644 gdb/features/microblaze64.xml + +diff --git a/bfd/Makefile.am b/bfd/Makefile.am +index 4f67b59585d..510f96439b7 100644 +--- a/bfd/Makefile.am ++++ b/bfd/Makefile.am +@@ -568,6 +568,7 @@ BFD64_BACKENDS = \ + elf64-ppc.lo \ + elf64-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -617,6 +618,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +diff --git a/bfd/Makefile.in b/bfd/Makefile.in +index faaa0c424b8..71982d9f729 100644 +--- a/bfd/Makefile.in ++++ b/bfd/Makefile.in +@@ -1036,6 +1036,7 @@ BFD64_BACKENDS = \ + elf64-ppc.lo \ + elf64-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -1085,6 +1086,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +@@ -1661,6 +1663,7 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@ +diff --git a/bfd/archures.c b/bfd/archures.c +index 94118b8d2cf..b9db26627ea 100644 +--- a/bfd/archures.c ++++ b/bfd/archures.c +@@ -515,6 +515,8 @@ DESCRIPTION + . bfd_arch_lm32, {* Lattice Mico32. *} + .#define bfd_mach_lm32 1 + . bfd_arch_microblaze,{* Xilinx MicroBlaze. *} ++.#define bfd_mach_microblaze 1 ++.#define bfd_mach_microblaze64 2 + . bfd_arch_kvx, {* Kalray VLIW core of the MPPA processor family *} + .#define bfd_mach_kv3_unknown 0 + .#define bfd_mach_kv3_1 1 +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 581d8fe0b3e..7ccc155394d 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -1771,6 +1771,8 @@ enum bfd_architecture + bfd_arch_lm32, /* Lattice Mico32. */ + #define bfd_mach_lm32 1 + bfd_arch_microblaze,/* Xilinx MicroBlaze. */ ++#define bfd_mach_microblaze 1 ++#define bfd_mach_microblaze64 2 + bfd_arch_kvx, /* Kalray VLIW core of the MPPA processor family */ + #define bfd_mach_kv3_unknown 0 + #define bfd_mach_kv3_1 1 +@@ -6444,23 +6446,44 @@ enum bfd_reloc_code_real + the form "Symbol Op Symbol". */ + BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, + +- /* This is a 32 bit reloc that stores the 32 bit pc relative value in +- two words (with an imm instruction). No relocation is done here - +- only used for relaxing. */ ++/* This is a 32 bit reloc that stores the 32 bit pc relative ++value in two words (with an imm instruction). No relocation is ++done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_32_NONE, + +- /* This is a 64 bit reloc that stores the 32 bit pc relative value in +- two words (with an imm instruction). No relocation is done here - +- only used for relaxing. */ +- BFD_RELOC_MICROBLAZE_64_NONE, ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_PCREL, ++ ++/* This is a 64 bit reloc that stores the 32 bit relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ ++/* This is a 64 bit reloc that stores the 32 bit relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_EA64, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imm instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative value in + two words (with an imm instruction). The relocation is PC-relative + GOT offset. */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + +- /* This is a 64 bit reloc that stores the 32 bit pc relative value in +- two words (with an imm instruction). The relocation is GOT offset. */ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). The relocation is ++PC-relative GOT offset */ ++ BFD_RELOC_MICROBLAZE_64_GPC, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imm instruction). The relocation is ++GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOT, + + /* This is a 64 bit reloc that stores the 32 bit pc relative value in +diff --git a/bfd/config.bfd b/bfd/config.bfd +index bbf12447517..cbba305354f 100644 +--- a/bfd/config.bfd ++++ b/bfd/config.bfd +@@ -884,11 +884,15 @@ case "${targ}" in + microblazeel*-*) + targ_defvec=microblaze_elf32_le_vec + targ_selvecs=microblaze_elf32_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + microblaze*-*) + targ_defvec=microblaze_elf32_vec + targ_selvecs=microblaze_elf32_le_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + #ifdef BFD64 +diff --git a/bfd/configure b/bfd/configure +index 5618c5d3217..3c5b58c33b4 100755 +--- a/bfd/configure ++++ b/bfd/configure +@@ -16016,6 +16016,8 @@ do + rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; + s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; + score_elf32_be_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;; + score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;; + sh_coff_vec) tb="$tb coff-sh.lo $coff" ;; +diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c +index a7af3a17237..caf4fb66826 100644 +--- a/bfd/cpu-microblaze.c ++++ b/bfd/cpu-microblaze.c +@@ -23,13 +23,30 @@ + #include "bfd.h" + #include "libbfd.h" + +-const bfd_arch_info_type bfd_microblaze_arch = ++const bfd_arch_info_type bfd_microblaze_arch[] = ++{ ++#if BFD_DEFAULT_TARGET_SIZE == 64 ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze64, /* 64 bit Machine */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ false, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, + { + 32, /* Bits in a word. */ + 32, /* Bits in an address. */ + 8, /* Bits in a byte. */ + bfd_arch_microblaze, /* Architecture number. */ +- 0, /* Machine number - 0 for now. */ ++ bfd_mach_microblaze, /* Machine number - 0 for now. */ + "microblaze", /* Architecture name. */ + "MicroBlaze", /* Printable name. */ + 3, /* Section align power. */ +@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_arch = + bfd_arch_default_fill, /* Default fill. */ + NULL, /* Next in list. */ + 0 /* Maximum offset of a reloc from the start of an insn. */ ++} ++#else ++{ ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze, /* 32 bit Machine */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ true, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze64, /* 64 bit Machine */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ false, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ NULL, /* Next in list. */ ++ 0 ++} ++#endif + }; +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 022ce365c59..7e7c4bf471d 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -114,6 +114,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + true), /* PC relative offset? */ + ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ + 0, /* Rightshift. */ +@@ -279,6 +293,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + true), /* PC relative offset? */ + ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ + /* A 64 bit GOT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ + 0, /* Rightshift. */ +@@ -618,9 +647,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; ++ case BFD_RELOC_MICROBLAZE_64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: + microblaze_reloc = R_MICROBLAZE_GOTPC_64; + break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOT: + microblaze_reloc = R_MICROBLAZE_GOT_64; + break; +@@ -1582,7 +1617,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) + { + relocation += addend; +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { +@@ -1987,8 +2022,7 @@ microblaze_elf_relax_section (bfd *abfd, + else + symval += irel->r_addend; + +- if ((symval & 0xffff8000) == 0 +- || (symval & 0xffff8000) == 0xffff8000) ++ if ((symval & 0xffff8000) == 0) + { + /* We can delete this instruction. */ + sdata->relax[sdata->relax_count].addr = irel->r_offset; +@@ -2052,16 +2086,45 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); + } + break; ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; + case R_MICROBLAZE_NONE: + case R_MICROBLAZE_32_NONE: + { + /* This was a PC-relative instruction that was + completely resolved. */ + size_t sfix, efix; ++ unsigned int val; + bfd_vma target_address; + target_address = irel->r_addend + irel->r_offset; + sfix = calc_fixup (irel->r_offset, 0, sec); + efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } + irel->r_addend -= (efix - sfix); + /* Should use HOWTO. */ + microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, +@@ -2078,8 +2141,8 @@ microblaze_elf_relax_section (bfd *abfd, + sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); + efix = calc_fixup (target_address, 0, sec); + irel->r_addend -= (efix - sfix); +- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset +- + INST_WORD_SIZE, irel->r_addend); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); + } + break; + } +@@ -2109,10 +2172,50 @@ microblaze_elf_relax_section (bfd *abfd, + irelscanend = irelocs + o->reloc_count; + for (irelscan = irelocs; irelscan < irelscanend; irelscan++) + { +- if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) +- || (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)) +- { +- isym = isymbuf + ELF32_R_SYM (irelscan->r_info); ++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) ++ { ++ unsigned int val; ++ ++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); ++ ++ /* hax: We only do the following fixup for debug location lists. */ ++ if (strcmp(".debug_loc", o->name)) ++ continue; ++ ++ /* This was a PC-relative instruction that was completely resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ if (val != irelscan->r_addend) { ++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) ++ { ++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx +@@ -3510,6 +3613,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd, + return true; + } + ++ ++static bool ++elf_microblaze_object_p (bfd *abfd) ++{ ++ /* Set the right machine number for an s390 elf32 file. */ ++ return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze); ++} ++ + /* Hook called by the linker routine which adds symbols from an object + file. We use it to put .comm items in .sbss, and not .bss. */ + +@@ -3580,8 +3691,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd, + #define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol + #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections + #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook +- +-#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus +-#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo ++#define elf_backend_object_p elf_microblaze_object_p + + #include "elf32-target.h" +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index ebd4f24149b..7a3e558d70a 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -3011,6 +3011,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", + "BFD_RELOC_MICROBLAZE_32_GOTOFF", + "BFD_RELOC_MICROBLAZE_COPY", ++ "BFD_RELOC_MICROBLAZE_64", ++ "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_64_TLS", + "BFD_RELOC_MICROBLAZE_64_TLSGD", + "BFD_RELOC_MICROBLAZE_64_TLSLD", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index e74cbd75e96..fda67e5ffda 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6665,6 +6665,12 @@ ENUMDOC + This is a 32 bit reloc that stores the 32 bit pc relative value in + two words (with an imm instruction). No relocation is done here - + only used for relaxing. ++ENUM ++ BFD_RELOC_MICROBLAZE_32_NONE ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC +@@ -7886,6 +7892,20 @@ ENUMX + ENUMDOC + Tilera TILE-Gx Relocations. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_BPF_64 + ENUMX +diff --git a/bfd/targets.c b/bfd/targets.c +index 3addf2fe373..a9a9b975c82 100644 +--- a/bfd/targets.c ++++ b/bfd/targets.c +@@ -799,6 +799,8 @@ extern const bfd_target mep_elf32_le_vec; + extern const bfd_target metag_elf32_vec; + extern const bfd_target microblaze_elf32_vec; + extern const bfd_target microblaze_elf32_le_vec; ++extern const bfd_target microblaze_elf64_vec; ++extern const bfd_target microblaze_elf64_le_vec; + extern const bfd_target mips_ecoff_be_vec; + extern const bfd_target mips_ecoff_le_vec; + extern const bfd_target mips_ecoff_bele_vec; +@@ -1167,6 +1169,10 @@ static const bfd_target * const _bfd_target_vector[] = + + &metag_elf32_vec, + ++#ifdef BFD64 ++ µblaze_elf64_vec, ++ µblaze_elf64_le_vec, ++#endif + µblaze_elf32_vec, + + &mips_ecoff_be_vec, +diff --git a/gdb/features/Makefile b/gdb/features/Makefile +index 8ac30d8cea3..690f1e94570 100644 +--- a/gdb/features/Makefile ++++ b/gdb/features/Makefile +@@ -102,7 +102,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH)) + # to make on the command line. + XMLTOC = \ + microblaze-with-stack-protect.xml \ ++ microblaze64-with-stack-protect.xml \ + microblaze.xml \ ++ microblaze64.xml \ + mips-dsp-linux.xml \ + mips-linux.xml \ + mips64-dsp-linux.xml \ +diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml +index d1d7d538461..4d77d9d898f 100644 +--- a/gdb/features/microblaze-core.xml ++++ b/gdb/features/microblaze-core.xml +@@ -8,7 +8,7 @@ + + + +- ++ + + + +@@ -39,7 +39,7 @@ + + + +- ++ + + + +@@ -64,4 +64,6 @@ + + + ++ ++ + +diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml +index b5f68403bd5..013240ce798 100644 +--- a/gdb/features/microblaze-stack-protect.xml ++++ b/gdb/features/microblaze-stack-protect.xml +@@ -7,6 +7,6 @@ + + + +- +- ++ ++ + +diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c +index 574dc02db67..8ab9565a047 100644 +--- a/gdb/features/microblaze-with-stack-protect.c ++++ b/gdb/features/microblaze-with-stack-protect.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect"); +- tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); + + tdesc_microblaze_with_stack_protect = result.release (); + } +diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c +index 8f1fb0a142f..ed12e5bcfd2 100644 +--- a/gdb/features/microblaze.c ++++ b/gdb/features/microblaze.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); + + tdesc_microblaze = result.release (); + } +diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml +new file mode 100644 +index 00000000000..96e99e2fb24 +--- /dev/null ++++ b/gdb/features/microblaze64-core.xml +@@ -0,0 +1,69 @@ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml +new file mode 100644 +index 00000000000..1bbf5fc3cea +--- /dev/null ++++ b/gdb/features/microblaze64-stack-protect.xml +@@ -0,0 +1,12 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c +new file mode 100644 +index 00000000000..a4de4666c76 +--- /dev/null ++++ b/gdb/features/microblaze64-with-stack-protect.c +@@ -0,0 +1,79 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze-with-stack-protect.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze64_with_stack_protect; ++static void ++initialize_tdesc_microblaze64_with_stack_protect (void) ++{ ++ target_desc_up result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ ++ feature = tdesc_create_feature (result.get() , "org.gnu.gdb.microblaze64.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ ++ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.stack-protect"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze64_with_stack_protect = result.release(); ++} +diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml +new file mode 100644 +index 00000000000..0e9f01611f3 +--- /dev/null ++++ b/gdb/features/microblaze64-with-stack-protect.xml +@@ -0,0 +1,12 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c +new file mode 100644 +index 00000000000..8ab7a90dd95 +--- /dev/null ++++ b/gdb/features/microblaze64.c +@@ -0,0 +1,77 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze64; ++static void ++initialize_tdesc_microblaze64 (void) ++{ ++ target_desc_up result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ ++ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze64 = result.release(); ++} +diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml +new file mode 100644 +index 00000000000..515d18e65cf +--- /dev/null ++++ b/gdb/features/microblaze64.xml +@@ -0,0 +1,11 @@ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index d086debc4f8..f34b0fa9fd4 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -40,6 +40,7 @@ + #include "features/microblaze-linux.c" + + static int microblaze_debug_flag = 0; ++int MICROBLAZE_REGISTER_SIZE=4; + + static void + microblaze_debug (const char *fmt, ...) +@@ -55,6 +56,7 @@ microblaze_debug (const char *fmt, ...) + } + } + ++#if 0 + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -86,6 +88,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + return val; + } + ++#endif ++ + static void + microblaze_linux_sigtramp_cache (frame_info_ptr next_frame, + struct trad_frame_cache *this_cache, +@@ -147,8 +151,8 @@ microblaze_linux_init_abi (struct gdbarch_info info, + + linux_init_abi (info, gdbarch, 0); + +- set_gdbarch_memory_remove_breakpoint (gdbarch, +- microblaze_linux_memory_remove_breakpoint); ++ // set_gdbarch_memory_remove_breakpoint (gdbarch, ++ // microblaze_linux_memory_remove_breakpoint); + + /* Shared library handling. */ + set_solib_svr4_fetch_link_map_offsets (gdbarch, +@@ -160,10 +164,30 @@ microblaze_linux_init_abi (struct gdbarch_info info, + + /* BFD target for core files. */ + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) +- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze"); ++ MICROBLAZE_REGISTER_SIZE=8; ++ } ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ } + else +- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel"); ++ MICROBLAZE_REGISTER_SIZE=8; ++ } ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ } + ++ switch (info.bfd_arch_info->mach) ++ { ++ case bfd_mach_microblaze64: ++ set_gdbarch_ptr_bit (gdbarch, 64); ++ break; ++ } + + /* Shared library handling. */ + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); +@@ -178,7 +202,9 @@ void _initialize_microblaze_linux_tdep (); + void + _initialize_microblaze_linux_tdep () + { +- gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, ++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, ++ microblaze_linux_init_abi); ++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, + microblaze_linux_init_abi); + initialize_tdesc_microblaze_linux (); + } +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index b0b4c1b2614..7cbbc8986a1 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -40,7 +40,9 @@ + #include "remote.h" + + #include "features/microblaze-with-stack-protect.c" ++#include "features/microblaze64-with-stack-protect.c" + #include "features/microblaze.c" ++#include "features/microblaze64.c" + + /* Instruction macros used for analyzing the prologue. */ + /* This set of instruction macros need to be changed whenever the +@@ -75,12 +77,13 @@ static const char * const microblaze_register_names[] = + "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6", + "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11", + "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi", +- "rslr", "rshr" ++ "slr", "shr" + }; + + #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names) + + static unsigned int microblaze_debug_flag = 0; ++int reg_size = 4; + + #define microblaze_debug(fmt, ...) \ + debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \ +@@ -128,6 +131,15 @@ microblaze_fetch_instruction (CORE_ADDR pc) + constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; + + typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; ++static CORE_ADDR ++microblaze_store_arguments (struct regcache *regcache, int nargs, ++ struct value **args, CORE_ADDR sp, ++ int struct_return, CORE_ADDR struct_addr) ++{ ++ error (_("store_arguments not implemented")); ++ return sp; ++} ++#if 0 + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -146,7 +158,6 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + /* Make sure we see the memory breakpoints. */ + scoped_restore restore_memory + = make_scoped_restore_show_memory_breakpoints (1); +- + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the +@@ -161,6 +172,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + return val; + } + ++#endif + /* Allocate and initialize a frame cache. */ + + static struct microblaze_frame_cache * +@@ -583,11 +595,11 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache, + { + case 1: /* return last byte in the register. */ + regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); +- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1); ++ memcpy(valbuf, buf + reg_size - 1, 1); + return; + case 2: /* return last 2 bytes in register. */ + regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); +- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2); ++ memcpy(valbuf, buf + reg_size - 2, 2); + return; + case 4: /* for sizes 4 or 8, copy the required length. */ + case 8: +@@ -753,6 +765,12 @@ microblaze_software_single_step (struct regcache *regcache) + } + #endif + ++static void ++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) ++{ ++ regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc); ++} ++ + static int dwarf2_to_reg_map[78] = + { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ + 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ +@@ -787,13 +805,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) + static void + microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) + { ++ + register_remote_g_packet_guess (gdbarch, + 4 * MICROBLAZE_NUM_CORE_REGS, +- tdesc_microblaze); ++ tdesc_microblaze64); + + register_remote_g_packet_guess (gdbarch, + 4 * MICROBLAZE_NUM_REGS, +- tdesc_microblaze_with_stack_protect); ++ tdesc_microblaze64_with_stack_protect); + } + + void +@@ -801,7 +820,7 @@ microblaze_supply_gregset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *gregs) + { +- const unsigned int *regs = (const unsigned int *)gregs; ++ const gdb_byte *regs = (const gdb_byte *) gregs; + if (regnum >= 0) + regcache->raw_supply (regnum, regs + regnum); + +@@ -809,7 +828,7 @@ microblaze_supply_gregset (const struct regset *regset, + int i; + + for (i = 0; i < 50; i++) { +- regcache->raw_supply (i, regs + i); ++ regcache->raw_supply (regnum, regs + i); + } + } + } +@@ -832,6 +851,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, + } + + ++static void ++make_regs (struct gdbarch *arch) ++{ ++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch); ++ int mach = gdbarch_bfd_arch_info (arch)->mach; ++ ++ if (mach == bfd_mach_microblaze64) ++ { ++ set_gdbarch_ptr_bit (arch, 64); ++ } ++} + + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -844,8 +874,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + if (arches != NULL) + return arches->gdbarch; + if (tdesc == NULL) +- tdesc = tdesc_microblaze; +- ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } ++ else ++ tdesc = tdesc_microblaze; ++ } + /* Check any target description for validity. */ + if (tdesc_has_registers (tdesc)) + { +@@ -853,31 +890,42 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- feature = tdesc_find_feature (tdesc, +- "org.gnu.gdb.microblaze.core"); ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze64.core"); ++ else ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze.core"); + if (feature == NULL) + return NULL; + tdesc_data = tdesc_data_alloc (); + + valid_p = 1; +- for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++) +- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, +- microblaze_register_names[i]); +- feature = tdesc_find_feature (tdesc, +- "org.gnu.gdb.microblaze.stack-protect"); ++ for (i = 0; i < MICROBLAZE_NUM_REGS; i++) ++ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, ++ microblaze_register_names[i]); ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze64.stack-protect"); ++ else ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze.stack-protect"); + if (feature != NULL) +- { +- valid_p = 1; +- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), +- MICROBLAZE_SLR_REGNUM, +- "rslr"); +- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), +- MICROBLAZE_SHR_REGNUM, +- "rshr"); +- } ++ { ++ valid_p = 1; ++ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), ++ MICROBLAZE_SLR_REGNUM, ++ "slr"); ++ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), ++ MICROBLAZE_SHR_REGNUM, ++ "shr"); ++ } + + if (!valid_p) +- return NULL; ++ { ++ // tdesc_data_cleanup (tdesc_data.get ()); ++ return NULL; ++ } + } + + /* Allocate space for the new architecture. */ +@@ -897,7 +945,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + /* Register numbers of various important registers. */ + set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); + set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); ++ ++ /* Register set. ++ make_regs (gdbarch); */ ++ switch (info.bfd_arch_info->mach) ++ { ++ case bfd_mach_microblaze64: ++ set_gdbarch_ptr_bit (gdbarch, 64); ++ break; ++ } + ++ + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); + +@@ -917,7 +975,9 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + microblaze_breakpoint::bp_from_kind); +- set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); ++// set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); ++ ++// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + + set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + +@@ -925,7 +985,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); + +- microblaze_register_g_packet_guesses (gdbarch); ++ //microblaze_register_g_packet_guesses (gdbarch); + + frame_base_set_default (gdbarch, µblaze_frame_base); + +@@ -940,12 +1000,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); + //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); + +- /* If we have register sets, enable the generic core file support. */ ++ /* If we have register sets, enable the generic core file support. + if (tdep->gregset) { + set_gdbarch_iterate_over_regset_sections (gdbarch, + microblaze_iterate_over_regset_sections); +- } +- ++ }*/ + return gdbarch; + } + +@@ -957,6 +1016,8 @@ _initialize_microblaze_tdep () + + initialize_tdesc_microblaze_with_stack_protect (); + initialize_tdesc_microblaze (); ++ initialize_tdesc_microblaze64_with_stack_protect (); ++ initialize_tdesc_microblaze64 (); + /* Debug this files internals. */ + add_setshow_zuinteger_cmd ("microblaze", class_maintenance, + µblaze_debug_flag, _("\ +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index c4c8098308f..81f7f30cb8e 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -28,7 +28,7 @@ struct microblaze_gregset + microblaze_gregset() {} + unsigned int gregs[32]; + unsigned int fpregs[32]; +- unsigned int pregs[16]; ++ unsigned int pregs[18]; + }; + + struct microblaze_gdbarch_tdep : gdbarch_tdep_base +@@ -134,7 +134,7 @@ struct microblaze_frame_cache + struct trad_frame_saved_reg *saved_regs; + }; + /* All registers are 32 bits. */ +-#define MICROBLAZE_REGISTER_SIZE 4 ++//#define MICROBLAZE_REGISTER_SIZE 8 + + /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. + Only used for native debugging. */ +diff --git a/include/elf/common.h b/include/elf/common.h +index 6a66456cd22..11f5d1a3cc9 100644 +--- a/include/elf/common.h ++++ b/include/elf/common.h +@@ -360,6 +360,7 @@ + #define EM_U16_U8CORE 260 /* LAPIS nX-U16/U8 */ + #define EM_TACHYUM 261 /* Tachyum */ + #define EM_56800EF 262 /* NXP 56800EF Digital Signal Controller (DSC) */ ++#define EM_MB_64 263 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ + + /* If it is necessary to assign new unofficial EM_* values, please pick large + random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision +diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h +index a48b1358efd..c515f15bfb8 100644 +--- a/include/elf/microblaze.h ++++ b/include/elf/microblaze.h +@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type) + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */ + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */ + RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33) ++ RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34) ++ RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35) /* GOT entry offset. */ + END_RELOC_NUMBERS (R_MICROBLAZE_max) + + /* Global base address names. */ +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 3d696325803..ee447cecc3f 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -33,6 +33,7 @@ + #define get_field_r1(buf, instr) get_field (buf, instr, RA_MASK, RA_LOW) + #define get_field_r2(buf, instr) get_field (buf, instr, RB_MASK, RB_LOW) + #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) ++#define get_int_field_imml(instr) ((instr & IMML_MASK) >> IMM_LOW) + #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) + + #define NUM_STRBUFS 4 +@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr) + } + + static char * +-get_field_imm5 (struct string_buf *buf, long instr) ++get_field_imml (struct string_buf *buf, long instr) + { + char *p = strbuf (buf); + +- sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); ++ sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW)); ++ return p; ++} ++ ++static char * ++get_field_imms (struct string_buf *buf, long instr) ++{ ++ char *p = strbuf (buf); ++ ++ sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW)); + return p; + } + +@@ -96,12 +106,9 @@ get_field_immw (struct string_buf *buf, long instr) + char *p = strbuf (buf); + + if (instr & 0x00004000) +- sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) +- >> IMM_WIDTH_LOW))); /* bsefi */ +- else +- sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> +- IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> +- IMM_LOW) + 1)); /* bsifi */ ++ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ ++ else ++ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */ + return p; + } + +@@ -311,9 +318,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; +- case INST_TYPE_RD_R1_IMM5: ++ case INST_TYPE_RD_R1_IMML: ++ print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), ++ get_field_r1(&buf, inst), get_field_imm (&buf, inst)); ++ /* TODO: Also print symbol */ ++ break; ++ case INST_TYPE_RD_R1_IMMS: + print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), +- get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst)); ++ get_field_r1(&buf, inst), get_field_imms (&buf, inst)); + break; + case INST_TYPE_RD_RFSL: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), +@@ -417,9 +429,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; +- case INST_TYPE_RD_R2: +- print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), +- get_field_r2 (&buf, inst)); ++ case INST_TYPE_IMML: ++ print_func (stream, "\t%s", get_field_imml (&buf, inst)); ++ /* TODO: Also print symbol */ ++ break; ++ case INST_TYPE_RD_R2: ++ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst)); + break; + case INST_TYPE_R2: + print_func (stream, "\t%s", get_field_r2 (&buf, inst)); +@@ -442,15 +457,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + /* For mbar 16 or sleep insn. */ + case INST_TYPE_NONE: + break; +- /* For bit field insns. */ ++ /* For bit field insns. */ + case INST_TYPE_RD_R1_IMMW_IMMS: +- print_func (stream, "\t%s, %s, %s, %s", +- get_field_rd (&buf, inst), +- get_field_r1 (&buf, inst), +- get_field_immw (&buf, inst), +- get_field_imm5 (&buf, inst)); ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), ++ get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; +- /* For tuqula instruction */ ++ /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (&buf, inst)); + break; +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index fe23b0af56a..afc1220e357 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -40,7 +40,7 @@ + #define INST_TYPE_RD_SPECIAL 11 + #define INST_TYPE_R1 12 + /* New instn type for barrel shift imms. */ +-#define INST_TYPE_RD_R1_IMM5 13 ++#define INST_TYPE_RD_R1_IMMS 13 + #define INST_TYPE_RD_RFSL 14 + #define INST_TYPE_R1_RFSL 15 + +@@ -62,6 +62,11 @@ + /* For bsefi and bsifi */ + #define INST_TYPE_RD_R1_IMMW_IMMS 21 + ++/* For 64-bit instructions */ ++#define INST_TYPE_IMML 22 ++#define INST_TYPE_RD_R1_IMML 23 ++#define INST_TYPE_R1_IMML 24 ++ + #define INST_TYPE_NONE 25 + + +@@ -91,15 +96,14 @@ + #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ + #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ + #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ +-#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ +-#define OPCODE_MASK_H3B 0xFC00F9E0 /* High 6 bits and bits 16:20 and +- bits 23:26. */ ++#define OPCODE_MASK_H3 0xFC000700 /* High 6 bits and bits 21, 22, 23. */ ++#define OPCODE_MASK_H3B 0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22. */ + #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ +-#define OPCODE_MASK_H32B 0xFC00F820 /* High 6 bits and bits 16:20 and +- bit 26 */ ++#define OPCODE_MASK_H32B 0xFC00E000 /* High 6 bits and bit 16, 17, 18. */ + #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ + #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ ++#define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ + + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ +@@ -109,7 +113,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 291 ++#define MAX_OPCODES 412 + + const struct op_code_struct + { +@@ -127,6 +131,7 @@ const struct op_code_struct + /* More info about output format here. */ + } microblaze_opcodes[MAX_OPCODES] = + { ++ /* 32-bit instructions */ + {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, + {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, + {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, +@@ -163,9 +168,9 @@ const struct op_code_struct + {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, + {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, + {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, +- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, +- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, +- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, ++ {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, ++ {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, ++ {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, + {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, + {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, +@@ -269,9 +274,7 @@ const struct op_code_struct + {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */ + {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */ + {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */ +- {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ + {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */ +- {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, + {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, + {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, +@@ -427,7 +430,131 @@ const struct op_code_struct + {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */ + {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst }, + {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, +- {NULL, 0, 0, 0, 0, 0, 0, 0, 0}, ++ /* 64-bit instructions */ ++ {"addl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst }, ++ {"rsubl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst }, ++ {"addlc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst }, ++ {"rsublc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst }, ++ {"addlk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst }, ++ {"rsublk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst }, ++ {"addlkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst }, ++ {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst }, ++ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, ++ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, ++ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, ++ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, ++ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, ++ {"bslrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst }, ++ {"bsllli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst }, ++ {"bslrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst }, ++ {"bslrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst }, ++ {"bslefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst }, ++ {"bslifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst }, ++ {"orl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst }, ++ {"andl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst }, ++ {"xorl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst }, ++ {"andnl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst }, ++ {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst }, ++ {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst }, ++ {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst }, ++ {"srla", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst }, ++ {"srlc", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst }, ++ {"srll", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst }, ++ {"sextl8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst }, ++ {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst }, ++ {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst }, ++ {"brea", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst }, ++ {"bread", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst }, ++ {"breald", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst }, ++ {"beaeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst }, ++ {"bealeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst }, ++ {"beaeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst }, ++ {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst }, ++ {"beane", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst }, ++ {"bealne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst }, ++ {"beaned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst }, ++ {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst }, ++ {"bealt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst }, ++ {"beallt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst }, ++ {"bealtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst }, ++ {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst }, ++ {"beale", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst }, ++ {"bealle", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst }, ++ {"bealed", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst }, ++ {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst }, ++ {"beagt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst }, ++ {"bealgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst }, ++ {"beagtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst }, ++ {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst }, ++ {"beage", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst }, ++ {"bealge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst }, ++ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, ++ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, ++ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, ++ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, ++ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, ++ {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst }, ++ {"beaeqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst }, ++ {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */ ++ {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst }, ++ {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqid */ ++ {"beanei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst }, ++ {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */ ++ {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst }, ++ {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaneid */ ++ {"bealti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst }, ++ {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */ ++ {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst }, ++ {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealtid */ ++ {"bealei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst }, ++ {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */ ++ {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst }, ++ {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealeid */ ++ {"beagti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst }, ++ {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */ ++ {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst }, ++ {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagtid */ ++ {"beagei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst }, ++ {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */ ++ {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst }, ++ {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beageid */ ++ {"ll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst }, ++ {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst }, ++ {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst }, ++ {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst }, ++ {"lli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ ++ {"sli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ ++ {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */ ++ {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst }, ++ {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst }, ++ {"dmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst }, ++ {"ddiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst }, ++ {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst }, ++ {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst }, ++ {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst }, ++ {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst }, ++ {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst }, ++ {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst }, ++ {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst }, ++ {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst }, ++ {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst }, ++ {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst }, ++ {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ ++ {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ ++ ++ {"", 0, 0, 0, 0, 0, 0, 0, 0}, + }; + + /* Prefix for register names. */ +@@ -447,8 +574,17 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM5 ((int) 0x00000000) + #define MAX_IMM5 ((int) 0x0000001f) + ++#define MIN_IMM6 ((int) 0x00000000) ++#define MAX_IMM6 ((int) 0x0000003f) ++ + #define MIN_IMM_WIDTH ((int) 0x00000001) + #define MAX_IMM_WIDTH ((int) 0x00000020) + ++#define MIN_IMM6_WIDTH ((int) 0x00000001) ++#define MAX_IMM6_WIDTH ((int) 0x00000040) ++ ++#define MIN_IMML ((long) 0xffffff8000000000L) ++#define MAX_IMML ((long) 0x0000007fffffffffL) ++ + #endif /* MICROBLAZE_OPC */ + +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index cb8d3a59949..08ed44352ee 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -25,6 +25,7 @@ + + enum microblaze_instr + { ++ /* 32-bit instructions */ + add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, + addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, + mulh, mulhu, mulhsu, swapb, swaph, +@@ -39,8 +40,8 @@ enum microblaze_instr + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, + bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, +- sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, +- sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, ++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli, ++ sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, + fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, + /* 'fsqrt' is a glibc:math.h symbol. */ + fint, microblaze_fsqrt, +@@ -59,6 +60,18 @@ enum microblaze_instr + aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, + eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, ++ ++ /* 64-bit instructions */ ++ addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, ++ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, ++ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, ++ bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt, ++ bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid, ++ beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti, ++ beagtid, beagei, beageid, imml, ll, llr, sl, slr, ++ dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge, ++ dcmp_un, dbl, dlong, dsqrt, + invalid_inst + }; + +@@ -136,15 +149,18 @@ enum microblaze_instr_type + #define RA_MASK 0x001F0000 + #define RB_MASK 0x0000F800 + #define IMM_MASK 0x0000FFFF ++#define IMML_MASK 0x00FFFFFF + +-/* Imm mask for barrel shifts. */ ++/* Imm masks for barrel shifts. */ + #define IMM5_MASK 0x0000001F ++#define IMM6_MASK 0x0000003F + + /* Imm mask for mbar. */ + #define IMM5_MBAR_MASK 0x03E00000 + +-/* Imm mask for extract/insert width. */ ++/* Imm masks for extract/insert width. */ + #define IMM5_WIDTH_MASK 0x000007C0 ++#define IMM6_WIDTH_MASK 0x00000FC0 + + /* FSL imm mask for get, put instructions. */ + #define RFSL_MASK 0x000000F +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch new file mode 100644 index 00000000..a744bcb4 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch @@ -0,0 +1,35 @@ +From 6c699df5c33f13ea3226d144f544d5a295edcf17 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 19 Apr 2021 14:33:27 +0530 +Subject: [PATCH 07/53] these changes will make 64 bit vectors as default + target types when we built gdb with microblaze 64 bit type targets,for + instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64 + +Signed-off-by: Aayush Misra +--- + bfd/config.bfd | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/bfd/config.bfd b/bfd/config.bfd +index cbba305354f..f7134608693 100644 +--- a/bfd/config.bfd ++++ b/bfd/config.bfd +@@ -880,7 +880,15 @@ case "${targ}" in + targ_defvec=metag_elf32_vec + targ_underscore=yes + ;; ++ microblazeel*-*64) ++ targ_defvec=microblaze_elf64_le_vec ++ targ_selvecs=microblaze_elf64_vec ++ ;; + ++ microblaze*-*64) ++ targ_defvec=microblaze_elf64_vec ++ targ_selvecs=microblaze_elf64_le_vec ++ ;; + microblazeel*-*) + targ_defvec=microblaze_elf32_le_vec + targ_selvecs=microblaze_elf32_vec +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch new file mode 100644 index 00000000..10517953 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch @@ -0,0 +1,4104 @@ +From 815e641399628fcde8e13f925e4a6d3bc565a762 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 9 Nov 2021 16:19:17 +0530 +Subject: [PATCH 08/53] Added m64 abi for 64 bit target descriptions. set m64 + abi for 64 bit elf. + +Conflicts: + gdb/microblaze-tdep.c + gdb/microblaze-tdep.h + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 3810 ++++++++++++++++++++++++++++++++++++++++ + gdb/microblaze-tdep.c | 160 +- + gdb/microblaze-tdep.h | 13 +- + 3 files changed, 3975 insertions(+), 8 deletions(-) + create mode 100755 bfd/elf64-microblaze.c + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +new file mode 100755 +index 00000000000..6cd9753a592 +--- /dev/null ++++ b/bfd/elf64-microblaze.c +@@ -0,0 +1,3810 @@ ++/* Xilinx MicroBlaze-specific support for 32-bit ELF ++ ++ Copyright (C) 2009-2021 Free Software Foundation, Inc. ++ ++ This file is part of BFD, the Binary File Descriptor library. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the ++ Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, ++ Boston, MA 02110-1301, USA. */ ++ ++ ++#include "sysdep.h" ++#include "bfd.h" ++#include "bfdlink.h" ++#include "libbfd.h" ++#include "elf-bfd.h" ++#include "elf/microblaze.h" ++#include ++ ++#define USE_RELA /* Only USE_REL is actually significant, but this is ++ here are a reminder... */ ++#define INST_WORD_SIZE 4 ++ ++static int ro_small_data_pointer = 0; ++static int rw_small_data_pointer = 0; ++ ++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max]; ++ ++static reloc_howto_type microblaze_elf_howto_raw[] = ++{ ++ /* This reloc does nothing. */ ++ HOWTO (R_MICROBLAZE_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 0, /* Size. */ ++ 0, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_NONE", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A standard 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 32, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A standard PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 32, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_PCREL", /* Name. */ ++ true, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit PCREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_64_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64_PCREL", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* The low half of a PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_32_PCREL_LO", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 64, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffffffffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit relocation. Table entry not really used. */ ++ HOWTO (R_MICROBLAZE_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* The low half of a 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_LO", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Read-only small data section relocation. */ ++ HOWTO (R_MICROBLAZE_SRO32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRO32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Read-write small data area relocation. */ ++ HOWTO (R_MICROBLAZE_SRW32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRW32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_32_NONE",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 0, /* Size. */ ++ 0, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_64_NONE",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Symbol Op Symbol relocation. */ ++ HOWTO (R_MICROBLAZE_32_SYM_OP_SYM, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 32, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_SYM_OP_SYM", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable hierarchy. */ ++ HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 0, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTINHERIT", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable member usage. */ ++ HOWTO (R_MICROBLAZE_GNU_VTENTRY, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 0, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ _bfd_elf_rel_vtable_reloc_fn, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTENTRY", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTPC_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit TEXTPCREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_TEXTPCREL_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_TEXTPCREL_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOT_64",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit TEXTREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_TEXTREL_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_TEXTREL_64",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit PLT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_PLT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_PLT_64",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_REL, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_REL", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_JUMP_SLOT", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GLOB_DAT", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 32 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* COPY relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_COPY, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_COPY", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Marker relocs for TLS. */ ++ HOWTO (R_MICROBLAZE_TLS, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLS", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSGD, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGD", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSLD, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSLD", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes the load module index of the load module that contains the ++ definition of its TLS sym. */ ++ HOWTO (R_MICROBLAZE_TLSDTPMOD32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPMOD32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. Used for initializing GOT */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL32, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL64, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL64", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSGOTTPREL32, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGOTTPREL32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSTPREL32, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSTPREL32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++}; ++ ++#ifndef NUM_ELEM ++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) ++#endif ++ ++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done. */ ++ ++static void ++microblaze_elf_howto_init (void) ++{ ++ unsigned int i; ++ ++ for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;) ++ { ++ unsigned int type; ++ ++ type = microblaze_elf_howto_raw[i].type; ++ ++ BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table)); ++ ++ microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i]; ++ } ++} ++ ++static reloc_howto_type * ++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, ++ bfd_reloc_code_real_type code) ++{ ++ enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE; ++ ++ switch (code) ++ { ++ case BFD_RELOC_NONE: ++ microblaze_reloc = R_MICROBLAZE_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_NONE: ++ microblaze_reloc = R_MICROBLAZE_32_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_NONE: ++ microblaze_reloc = R_MICROBLAZE_64_NONE; ++ break; ++ case BFD_RELOC_32: ++ microblaze_reloc = R_MICROBLAZE_32; ++ break; ++ /* RVA is treated the same as 64 */ ++ case BFD_RELOC_RVA: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; ++ case BFD_RELOC_32_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL; ++ break; ++ case BFD_RELOC_64_PCREL: ++ microblaze_reloc = R_MICROBLAZE_64_PCREL; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL_LO; ++ break; ++ case BFD_RELOC_64: ++ microblaze_reloc = R_MICROBLAZE_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO: ++ microblaze_reloc = R_MICROBLAZE_32_LO; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_ROSDA: ++ microblaze_reloc = R_MICROBLAZE_SRO32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_RWSDA: ++ microblaze_reloc = R_MICROBLAZE_SRW32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: ++ microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM; ++ break; ++ case BFD_RELOC_VTABLE_INHERIT: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT; ++ break; ++ case BFD_RELOC_VTABLE_ENTRY: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; ++ break; ++ case BFD_RELOC_MICROBLAZE_EA64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ microblaze_reloc = R_MICROBLAZE_GOTPC_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOT: ++ microblaze_reloc = R_MICROBLAZE_GOT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TEXTPCREL: ++ microblaze_reloc = R_MICROBLAZE_TEXTPCREL_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TEXTREL: ++ microblaze_reloc = R_MICROBLAZE_TEXTREL_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_PLT: ++ microblaze_reloc = R_MICROBLAZE_PLT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGD: ++ microblaze_reloc = R_MICROBLAZE_TLSGD; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSLD: ++ microblaze_reloc = R_MICROBLAZE_TLSLD; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_COPY: ++ microblaze_reloc = R_MICROBLAZE_COPY; ++ break; ++ default: ++ return (reloc_howto_type *) NULL; ++ } ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ return microblaze_elf_howto_table [(int) microblaze_reloc]; ++}; ++ ++static reloc_howto_type * ++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, ++ const char *r_name) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++) ++ if (microblaze_elf_howto_raw[i].name != NULL ++ && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0) ++ return µblaze_elf_howto_raw[i]; ++ ++ return NULL; ++} ++ ++/* Set the howto pointer for a RCE ELF reloc. */ ++ ++static bool ++microblaze_elf_info_to_howto (bfd * abfd, ++ arelent * cache_ptr, ++ Elf_Internal_Rela * dst) ++{ ++ unsigned int r_type; ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ r_type = ELF64_R_TYPE (dst->r_info); ++ if (r_type >= R_MICROBLAZE_max) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler (_("%pB: unsupported relocation type %#x"), ++ abfd, r_type); ++ bfd_set_error (bfd_error_bad_value); ++ return false; ++ } ++ ++ cache_ptr->howto = microblaze_elf_howto_table [r_type]; ++ return true; ++} ++ ++struct _microblaze_elf_section_data ++{ ++ struct bfd_elf_section_data elf; ++ /* Count of used relaxation table entries. */ ++ size_t relax_count; ++ /* Relaxation table. */ ++ struct relax_table *relax; ++}; ++ ++#define microblaze_elf_section_data(sec) \ ++ ((struct _microblaze_elf_section_data *) elf_section_data (sec)) ++ ++static bool ++microblaze_elf_new_section_hook (bfd *abfd, asection *sec) ++{ ++ if (!sec->used_by_bfd) ++ { ++ struct _microblaze_elf_section_data *sdata; ++ size_t amt = sizeof (*sdata); ++ ++ sdata = bfd_zalloc (abfd, amt); ++ if (sdata == NULL) ++ return false; ++ sec->used_by_bfd = sdata; ++ } ++ ++ return _bfd_elf_new_section_hook (abfd, sec); ++} ++ ++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */ ++ ++static bool ++microblaze_elf_is_local_label_name (bfd *abfd, const char *name) ++{ ++ if (name[0] == 'L' && name[1] == '.') ++ return true; ++ ++ if (name[0] == '$' && name[1] == 'L') ++ return true; ++ ++ /* With gcc, the labels go back to starting with '.', so we accept ++ the generic ELF local label syntax as well. */ ++ return _bfd_elf_is_local_label_name (abfd, name); ++} ++ ++/* The microblaze linker (like many others) needs to keep track of ++ the number of relocs that it decides to copy as dynamic relocs in ++ check_relocs for each symbol. This is so that it can later discard ++ them if they are found to be unnecessary. We store the information ++ in a field extending the regular ELF linker hash table. */ ++ ++struct elf64_mb_dyn_relocs ++{ ++ struct elf64_mb_dyn_relocs *next; ++ ++ /* The input section of the reloc. */ ++ asection *sec; ++ ++ /* Total number of relocs copied for the input section. */ ++ bfd_size_type count; ++ ++ /* Number of pc-relative relocs copied for the input section. */ ++ bfd_size_type pc_count; ++}; ++ ++/* ELF linker hash entry. */ ++ ++struct elf64_mb_link_hash_entry ++{ ++ struct elf_link_hash_entry elf; ++ ++ /* Track dynamic relocs copied for this symbol. */ ++ struct elf64_mb_dyn_relocs *dyn_relocs; ++ ++ /* TLS Reference Types for the symbol; Updated by check_relocs */ ++#define TLS_GD 1 /* GD reloc. */ ++#define TLS_LD 2 /* LD reloc. */ ++#define TLS_TPREL 4 /* TPREL reloc, => IE. */ ++#define TLS_DTPREL 8 /* DTPREL reloc, => LD. */ ++#define TLS_TLS 16 /* Any TLS reloc. */ ++ unsigned char tls_mask; ++ ++}; ++ ++#define IS_TLS_GD(x) (x == (TLS_TLS | TLS_GD)) ++#define IS_TLS_LD(x) (x == (TLS_TLS | TLS_LD)) ++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL)) ++#define IS_TLS_NONE(x) (x == 0) ++ ++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent)) ++ ++/* ELF linker hash table. */ ++ ++struct elf64_mb_link_hash_table ++{ ++ struct elf_link_hash_table elf; ++ ++ /* Short-cuts to get to dynamic linker sections. */ ++ asection *sgot; ++ asection *sgotplt; ++ asection *srelgot; ++ asection *splt; ++ asection *srelplt; ++ asection *sdynbss; ++ asection *srelbss; ++ ++ /* Small local sym to section mapping cache. */ ++ struct sym_cache sym_sec; ++ ++ /* TLS Local Dynamic GOT Entry */ ++ union { ++ bfd_signed_vma refcount; ++ bfd_vma offset; ++ } tlsld_got; ++}; ++ ++/* Nonzero if this section has TLS related relocations. */ ++#define has_tls_reloc sec_flg0 ++ ++/* Get the ELF linker hash table from a link_info structure. */ ++ ++#define elf64_mb_hash_table(p) \ ++ ((is_elf_hash_table ((p)->hash) \ ++ && elf_hash_table_id (elf_hash_table (p)) == MICROBLAZE_ELF_DATA) \ ++ ? (struct elf64_mb_link_hash_table *) (p)->hash : NULL) ++ ++/* Create an entry in a microblaze ELF linker hash table. */ ++ ++static struct bfd_hash_entry * ++link_hash_newfunc (struct bfd_hash_entry *entry, ++ struct bfd_hash_table *table, ++ const char *string) ++{ ++ /* Allocate the structure if it has not already been allocated by a ++ subclass. */ ++ if (entry == NULL) ++ { ++ entry = bfd_hash_allocate (table, ++ sizeof (struct elf64_mb_link_hash_entry)); ++ if (entry == NULL) ++ return entry; ++ } ++ ++ /* Call the allocation method of the superclass. */ ++ entry = _bfd_elf_link_hash_newfunc (entry, table, string); ++ if (entry != NULL) ++ { ++ struct elf64_mb_link_hash_entry *eh; ++ ++ eh = (struct elf64_mb_link_hash_entry *) entry; ++ eh->tls_mask = 0; ++ } ++ ++ return entry; ++} ++ ++/* Create a mb ELF linker hash table. */ ++ ++static struct bfd_link_hash_table * ++microblaze_elf_link_hash_table_create (bfd *abfd) ++{ ++ struct elf64_mb_link_hash_table *ret; ++ size_t amt = sizeof (struct elf64_mb_link_hash_table); ++ ++ ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt); ++ if (ret == NULL) ++ return NULL; ++ ++ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, ++ sizeof (struct elf64_mb_link_hash_entry), ++ MICROBLAZE_ELF_DATA)) ++ { ++ free (ret); ++ return NULL; ++ } ++ ++ return &ret->elf.root; ++} ++ ++/* Set the values of the small data pointers. */ ++ ++static void ++microblaze_elf_final_sdp (struct bfd_link_info *info) ++{ ++ struct bfd_link_hash_entry *h; ++ ++ h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, false, false, true); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ ro_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++ ++ h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, false, false, true); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ rw_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++} ++ ++static bfd_vma ++dtprel_base (struct bfd_link_info *info) ++{ ++ /* If tls_sec is NULL, we should have signalled an error already. */ ++ if (elf_hash_table (info)->tls_sec == NULL) ++ return 0; ++ return elf_hash_table (info)->tls_sec->vma; ++} ++ ++/* The size of the thread control block. */ ++#define TCB_SIZE 8 ++ ++/* Output a simple dynamic relocation into SRELOC. */ ++ ++static void ++microblaze_elf_output_dynamic_relocation (bfd *output_bfd, ++ asection *sreloc, ++ unsigned long reloc_index, ++ unsigned long indx, ++ int r_type, ++ bfd_vma offset, ++ bfd_vma addend) ++{ ++ ++ Elf_Internal_Rela rel; ++ ++ rel.r_info = ELF64_R_INFO (indx, r_type); ++ rel.r_offset = offset; ++ rel.r_addend = addend; ++ ++ bfd_elf64_swap_reloca_out (output_bfd, &rel, ++ (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela))); ++} ++ ++/* This code is taken from elf64-m32r.c ++ There is some attempt to make this function usable for many architectures, ++ both USE_REL and USE_RELA ['twould be nice if such a critter existed], ++ if only to serve as a learning tool. ++ ++ The RELOCATE_SECTION function is called by the new ELF backend linker ++ to handle the relocations for a section. ++ ++ The relocs are always passed as Rela structures; if the section ++ actually uses Rel structures, the r_addend field will always be ++ zero. ++ ++ This function is responsible for adjust the section contents as ++ necessary, and (if using Rela relocs and generating a ++ relocatable output file) adjusting the reloc addend as ++ necessary. ++ ++ This function does not have to worry about setting the reloc ++ address or the reloc symbol index. ++ ++ LOCAL_SYMS is a pointer to the swapped in local symbols. ++ ++ LOCAL_SECTIONS is an array giving the section in the input file ++ corresponding to the st_shndx field of each local symbol. ++ ++ The global hash table entry for the global symbols can be found ++ via elf_sym_hashes (input_bfd). ++ ++ When generating relocatable output, this function must handle ++ STB_LOCAL/STT_SECTION symbols specially. The output symbol is ++ going to be the section symbol corresponding to the output ++ section, which means that the addend must be adjusted ++ accordingly. */ ++ ++static int ++microblaze_elf_relocate_section (bfd *output_bfd, ++ struct bfd_link_info *info, ++ bfd *input_bfd, ++ asection *input_section, ++ bfd_byte *contents, ++ Elf_Internal_Rela *relocs, ++ Elf_Internal_Sym *local_syms, ++ asection **local_sections) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; ++ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); ++ Elf_Internal_Rela *rel, *relend; ++ int endian = (bfd_little_endian (output_bfd)) ? 0 : 2; ++ /* Assume success. */ ++ bool ret = true; ++ asection *sreloc; ++ bfd_vma *local_got_offsets; ++ unsigned int tls_type; ++ ++ if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1]) ++ microblaze_elf_howto_init (); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ local_got_offsets = elf_local_got_offsets (input_bfd); ++ ++ sreloc = elf_section_data (input_section)->sreloc; ++ ++ rel = relocs; ++ relend = relocs + input_section->reloc_count; ++ for (; rel < relend; rel++) ++ { ++ int r_type; ++ reloc_howto_type *howto; ++ unsigned long r_symndx; ++ bfd_vma addend = rel->r_addend; ++ bfd_vma offset = rel->r_offset; ++ struct elf_link_hash_entry *h; ++ Elf_Internal_Sym *sym; ++ asection *sec; ++ const char *sym_name; ++ bfd_reloc_status_type r = bfd_reloc_ok; ++ const char *errmsg = NULL; ++ bool unresolved_reloc = false; ++ ++ h = NULL; ++ r_type = ELF64_R_TYPE (rel->r_info); ++ tls_type = 0; ++ ++ if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler (_("%pB: unsupported relocation type %#x"), ++ input_bfd, (int) r_type); ++ bfd_set_error (bfd_error_bad_value); ++ ret = false; ++ continue; ++ } ++ ++ howto = microblaze_elf_howto_table[r_type]; ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ ++ if (bfd_link_relocatable (info)) ++ { ++ /* This is a relocatable link. We don't have to change ++ anything, unless the reloc is against a section symbol, ++ in which case we have to adjust according to where the ++ section symbol winds up in the output section. */ ++ sec = NULL; ++ if (r_symndx >= symtab_hdr->sh_info) ++ /* External symbol. */ ++ continue; ++ ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sym_name = ""; ++ /* STT_SECTION: symbol is associated with a section. */ ++ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) ++ /* Symbol isn't associated with a section. Nothing to do. */ ++ continue; ++ ++ sec = local_sections[r_symndx]; ++ addend += sec->output_offset + sym->st_value; ++#ifndef USE_REL ++ /* This can't be done for USE_REL because it doesn't mean anything ++ and elf_link_input_bfd asserts this stays zero. */ ++ /* rel->r_addend = addend; */ ++#endif ++ ++#ifndef USE_REL ++ /* Addends are stored with relocs. We're done. */ ++ continue; ++#else /* USE_REL */ ++ /* If partial_inplace, we need to store any additional addend ++ back in the section. */ ++ if (!howto->partial_inplace) ++ continue; ++ /* ??? Here is a nice place to call a special_function like handler. */ ++ r = _bfd_relocate_contents (howto, input_bfd, addend, ++ contents + offset); ++#endif /* USE_REL */ ++ } ++ else ++ { ++ bfd_vma relocation; ++ bool resolved_to_zero; ++ ++ /* This is a final link. */ ++ sym = NULL; ++ sec = NULL; ++ unresolved_reloc = false; ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ { ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sec = local_sections[r_symndx]; ++ if (sec == 0) ++ continue; ++ sym_name = ""; ++ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); ++ /* r_addend may have changed if the reference section was ++ a merge section. */ ++ addend = rel->r_addend; ++ } ++ else ++ { ++ /* External symbol. */ ++ bool warned ATTRIBUTE_UNUSED; ++ bool ignored ATTRIBUTE_UNUSED; ++ ++ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, ++ r_symndx, symtab_hdr, sym_hashes, ++ h, sec, relocation, ++ unresolved_reloc, warned, ignored); ++ sym_name = h->root.root.string; ++ } ++ ++ /* Sanity check the address. */ ++ if (offset > bfd_get_section_limit (input_bfd, input_section)) ++ { ++ r = bfd_reloc_outofrange; ++ goto check_reloc; ++ } ++ ++ resolved_to_zero = (h != NULL ++ && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)); ++ ++ switch ((int) r_type) ++ { ++ case (int) R_MICROBLAZE_SRO32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_section_name (sec); ++ ++ if (strcmp (name, ".sdata2") == 0 ++ || strcmp (name, ".sbss2") == 0) ++ { ++ if (ro_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (ro_small_data_pointer == 0) ++ { ++ ret = false; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= ro_small_data_pointer; ++ /* Now it contains the offset from _SDA2_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ _bfd_error_handler ++ /* xgettext:c-format */ ++ (_("%pB: the target (%s) of an %s relocation" ++ " is in the wrong section (%pA)"), ++ input_bfd, ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ sec); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = false; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_SRW32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_section_name (sec); ++ ++ if (strcmp (name, ".sdata") == 0 ++ || strcmp (name, ".sbss") == 0) ++ { ++ if (rw_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (rw_small_data_pointer == 0) ++ { ++ ret = false; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= rw_small_data_pointer; ++ /* Now it contains the offset from _SDA_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ _bfd_error_handler ++ /* xgettext:c-format */ ++ (_("%pB: the target (%s) of an %s relocation" ++ " is in the wrong section (%pA)"), ++ input_bfd, ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ sec); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = false; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_32_SYM_OP_SYM: ++ break; /* Do nothing. */ ++ ++ case (int) R_MICROBLAZE_GOTPC_64: ++ relocation = (htab->elf.sgotplt->output_section->vma ++ + htab->elf.sgotplt->output_offset); ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ relocation += addend; ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ ++ case (int) R_MICROBLAZE_TEXTPCREL_64: ++ relocation = input_section->output_section->vma; ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ relocation += addend; ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ ++ case (int) R_MICROBLAZE_PLT_64: ++ { ++ bfd_vma immediate; ++ if (htab->elf.splt != NULL && h != NULL ++ && h->plt.offset != (bfd_vma) -1) ++ { ++ relocation = (htab->elf.splt->output_section->vma ++ + htab->elf.splt->output_offset ++ + h->plt.offset); ++ unresolved_reloc = false; ++ immediate = relocation - (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ else ++ { ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ immediate = relocation; ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSGD: ++ tls_type = (TLS_TLS | TLS_GD); ++ goto dogot; ++ case (int) R_MICROBLAZE_TLSLD: ++ tls_type = (TLS_TLS | TLS_LD); ++ /* Fall through. */ ++ dogot: ++ case (int) R_MICROBLAZE_GOT_64: ++ { ++ bfd_vma *offp; ++ bfd_vma off, off2; ++ unsigned long indx; ++ bfd_vma static_value; ++ ++ bool need_relocs = false; ++ if (htab->elf.sgot == NULL) ++ abort (); ++ ++ indx = 0; ++ offp = NULL; ++ ++ /* 1. Identify GOT Offset; ++ 2. Compute Static Values ++ 3. Process Module Id, Process Offset ++ 4. Fixup Relocation with GOT offset value. */ ++ ++ /* 1. Determine GOT Offset to use : TLS_LD, global, local */ ++ if (IS_TLS_LD (tls_type)) ++ offp = &htab->tlsld_got.offset; ++ else if (h != NULL) ++ { ++ if (htab->elf.sgotplt != NULL ++ && h->got.offset != (bfd_vma) -1) ++ offp = &h->got.offset; ++ else ++ abort (); ++ } ++ else ++ { ++ if (local_got_offsets == NULL) ++ abort (); ++ offp = &local_got_offsets[r_symndx]; ++ } ++ ++ if (!offp) ++ abort (); ++ ++ off = (*offp) & ~1; ++ off2 = off; ++ ++ if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type)) ++ off2 = off + 4; ++ ++ /* Symbol index to use for relocs */ ++ if (h != NULL) ++ { ++ bool dyn = ++ elf_hash_table (info)->dynamic_sections_created; ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, ++ bfd_link_pic (info), ++ h) ++ && (!bfd_link_pic (info) ++ || !SYMBOL_REFERENCES_LOCAL (info, h))) ++ indx = h->dynindx; ++ } ++ ++ /* Need to generate relocs ? */ ++ if ((bfd_link_pic (info) || indx != 0) ++ && (h == NULL ++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ || h->root.type != bfd_link_hash_undefweak)) ++ need_relocs = true; ++ ++ /* 2. Compute/Emit Static value of r-expression */ ++ static_value = relocation + addend; ++ ++ /* 3. Process module-id and offset */ ++ if (! ((*offp) & 1) ) ++ { ++ bfd_vma got_offset; ++ ++ got_offset = (htab->elf.sgot->output_section->vma ++ + htab->elf.sgot->output_offset ++ + off); ++ ++ /* Process module-id */ ++ if (IS_TLS_LD(tls_type)) ++ { ++ if (! bfd_link_pic (info)) ++ bfd_put_32 (output_bfd, 1, ++ htab->elf.sgot->contents + off); ++ else ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, 0); ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ if (! need_relocs) ++ bfd_put_32 (output_bfd, 1, ++ htab->elf.sgot->contents + off); ++ else ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, indx ? 0 : static_value); ++ } ++ ++ /* Process Offset */ ++ if (htab->elf.srelgot == NULL) ++ abort (); ++ ++ got_offset = (htab->elf.sgot->output_section->vma ++ + htab->elf.sgot->output_offset ++ + off2); ++ if (IS_TLS_LD(tls_type)) ++ { ++ /* For LD, offset should be 0 */ ++ *offp |= 1; ++ bfd_put_32 (output_bfd, 0, ++ htab->elf.sgot->contents + off2); ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ *offp |= 1; ++ static_value -= dtprel_base(info); ++ if (need_relocs) ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32, ++ got_offset, indx ? 0 : static_value); ++ else ++ bfd_put_32 (output_bfd, static_value, ++ htab->elf.sgot->contents + off2); ++ } ++ else ++ { ++ bfd_put_32 (output_bfd, static_value, ++ htab->elf.sgot->contents + off2); ++ ++ /* Relocs for dyn symbols generated by ++ finish_dynamic_symbols */ ++ if (bfd_link_pic (info) && h == NULL) ++ { ++ *offp |= 1; ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_REL, ++ got_offset, static_value); ++ } ++ } ++ } ++ ++ /* 4. Fixup Relocation with GOT offset value ++ Compute relative address of GOT entry for applying ++ the current relocation */ ++ relocation = htab->elf.sgot->output_section->vma ++ + htab->elf.sgot->output_offset ++ + off ++ - htab->elf.sgotplt->output_section->vma ++ - htab->elf.sgotplt->output_offset; ++ ++ /* Apply Current Relocation */ ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ ++ unresolved_reloc = false; ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_64: ++ { ++ bfd_vma immediate; ++ unsigned short lo, high; ++ relocation += addend; ++ relocation -= (htab->elf.sgotplt->output_section->vma ++ + htab->elf.sgotplt->output_offset); ++ /* Write this value into correct location. */ ++ immediate = relocation; ++ lo = immediate & 0x0000ffff; ++ high = (immediate >> 16) & 0x0000ffff; ++ bfd_put_16 (input_bfd, high, contents + offset + endian); ++ bfd_put_16 (input_bfd, lo, ++ contents + offset + INST_WORD_SIZE + endian); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_32: ++ { ++ relocation += addend; ++ relocation -= (htab->elf.sgotplt->output_section->vma ++ + htab->elf.sgotplt->output_offset); ++ /* Write this value into correct location. */ ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSDTPREL64: ++ relocation += addend; ++ relocation -= dtprel_base(info); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ case (int) R_MICROBLAZE_TEXTREL_64: ++ case (int) R_MICROBLAZE_TEXTREL_32_LO: ++ case (int) R_MICROBLAZE_64_PCREL : ++ case (int) R_MICROBLAZE_64: ++ case (int) R_MICROBLAZE_32: ++ case (int) R_MICROBLAZE_IMML_64: ++ { ++ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols ++ from removed linkonce sections, or sections discarded by ++ a linker script. */ ++ if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ else if (r_type == R_MICROBLAZE_TEXTREL_64 ++ || r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ relocation -= input_section->output_section->vma; ++ ++ if (r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian); ++ ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if ((insn & 0xff000000) == 0xb2000000) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, ++ contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ if ((bfd_link_pic (info) ++ && (h == NULL ++ || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ && !resolved_to_zero) ++ || h->root.type != bfd_link_hash_undefweak) ++ && (!howto->pc_relative ++ || (h != NULL ++ && h->dynindx != -1 ++ && (!info->symbolic ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && h != NULL ++ && h->dynindx != -1 ++ && !h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined))) ++ { ++ Elf_Internal_Rela outrel; ++ bfd_byte *loc; ++ bool skip; ++ ++ /* When generating a shared object, these relocations ++ are copied into the output file to be resolved at run ++ time. */ ++ ++ BFD_ASSERT (sreloc != NULL); ++ ++ skip = false; ++ ++ outrel.r_offset = ++ _bfd_elf_section_offset (output_bfd, info, input_section, ++ rel->r_offset); ++ if (outrel.r_offset == (bfd_vma) -1) ++ skip = true; ++ else if (outrel.r_offset == (bfd_vma) -2) ++ skip = true; ++ outrel.r_offset += (input_section->output_section->vma ++ + input_section->output_offset); ++ ++ if (skip) ++ memset (&outrel, 0, sizeof outrel); ++ /* h->dynindx may be -1 if the symbol was marked to ++ become local. */ ++ else if (h != NULL ++ && ((! info->symbolic && h->dynindx != -1) ++ || !h->def_regular)) ++ { ++ BFD_ASSERT (h->dynindx != -1); ++ outrel.r_info = ELF64_R_INFO (h->dynindx, r_type); ++ outrel.r_addend = addend; ++ } ++ else ++ { ++ if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64) ++ { ++ outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); ++ outrel.r_addend = relocation + addend; ++ } ++ else ++ { ++ BFD_FAIL (); ++ _bfd_error_handler ++ (_("%pB: probably compiled without -fPIC?"), ++ input_bfd); ++ bfd_set_error (bfd_error_bad_value); ++ return false; ++ } ++ } ++ ++ loc = sreloc->contents; ++ loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc); ++ break; ++ } ++ else ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset + endian); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ { ++ if (!input_section->output_section->vma && ++ !input_section->output_offset && !offset) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset); ++ else ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset + offset + INST_WORD_SIZE); ++ } ++ else if (r_type == R_MICROBLAZE_TEXTREL_64 ++ || r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ relocation -= input_section->output_section->vma; ++ ++ if (r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ { ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian); ++ } ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if ((insn & 0xff000000) == 0xb2000000) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, ++ contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ } ++ ++ default : ++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, ++ contents, offset, ++ relocation, addend); ++ break; ++ } ++ } ++ ++ check_reloc: ++ ++ if (r != bfd_reloc_ok) ++ { ++ /* FIXME: This should be generic enough to go in a utility. */ ++ const char *name; ++ ++ if (h != NULL) ++ name = h->root.root.string; ++ else ++ { ++ name = (bfd_elf_string_from_elf_section ++ (input_bfd, symtab_hdr->sh_link, sym->st_name)); ++ if (name == NULL || *name == '\0') ++ name = bfd_section_name (sec); ++ } ++ ++ if (errmsg != NULL) ++ goto common_error; ++ ++ switch (r) ++ { ++ case bfd_reloc_overflow: ++ (*info->callbacks->reloc_overflow) ++ (info, (h ? &h->root : NULL), name, howto->name, ++ (bfd_vma) 0, input_bfd, input_section, offset); ++ break; ++ ++ case bfd_reloc_undefined: ++ (*info->callbacks->undefined_symbol) ++ (info, name, input_bfd, input_section, offset, true); ++ break; ++ ++ case bfd_reloc_outofrange: ++ errmsg = _("internal error: out of range error"); ++ goto common_error; ++ ++ case bfd_reloc_notsupported: ++ errmsg = _("internal error: unsupported relocation error"); ++ goto common_error; ++ ++ case bfd_reloc_dangerous: ++ errmsg = _("internal error: dangerous error"); ++ goto common_error; ++ ++ default: ++ errmsg = _("internal error: unknown error"); ++ /* Fall through. */ ++ common_error: ++ (*info->callbacks->warning) (info, errmsg, name, input_bfd, ++ input_section, offset); ++ break; ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++/* Merge backend specific data from an object file to the output ++ object file when linking. ++ ++ Note: We only use this hook to catch endian mismatches. */ ++static bool ++microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) ++{ ++ /* Check if we have the same endianess. */ ++ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) ++ return false; ++ ++ return true; ++} ++ ++ ++/* Calculate fixup value for reference. */ ++ ++static size_t ++calc_fixup (bfd_vma start, bfd_vma size, asection *sec) ++{ ++ bfd_vma end = start + size; ++ size_t i, fixup = 0; ++ struct _microblaze_elf_section_data *sdata; ++ ++ if (sec == NULL || (sdata = microblaze_elf_section_data (sec)) == NULL) ++ return 0; ++ ++ /* Look for addr in relax table, total fixup value. */ ++ for (i = 0; i < sdata->relax_count; i++) ++ { ++ if (end <= sdata->relax[i].addr) ++ break; ++ if (end != start && start > sdata->relax[i].addr) ++ continue; ++ fixup += sdata->relax[i].size; ++ } ++ return fixup; ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ a 32-bit instruction. */ ++static void ++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr = bfd_get_32 (abfd, bfd_addr); ++ ++ if ((instr & 0xff000000) == 0xb2000000) ++ { ++ instr &= ~0x00ffffff; ++ instr |= (val & 0xffffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } ++ else ++ { ++ instr &= ~0x0000ffff; ++ instr |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ two consecutive 32-bit instructions. */ ++static void ++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr_hi; ++ unsigned long instr_lo; ++ ++ instr_hi = bfd_get_32 (abfd, bfd_addr); ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ { ++ instr_hi &= ~0x00ffffff; ++ instr_hi |= (val >> 16) & 0xffffff; ++ bfd_put_32 (abfd, instr_hi,bfd_addr); ++ } ++ else ++ { ++ instr_hi &= ~0x0000ffff; ++ instr_hi |= ((val >> 16) & 0x0000ffff); ++ bfd_put_32 (abfd, instr_hi, bfd_addr); ++ } ++ instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE); ++ instr_lo &= ~0x0000ffff; ++ instr_lo |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE); ++} ++ ++static bool ++microblaze_elf_relax_section (bfd *abfd, ++ asection *sec, ++ struct bfd_link_info *link_info, ++ bool *again) ++{ ++ Elf_Internal_Shdr *symtab_hdr; ++ Elf_Internal_Rela *internal_relocs; ++ Elf_Internal_Rela *irel, *irelend; ++ bfd_byte *contents = NULL; ++ int rel_count; ++ unsigned int shndx; ++ size_t i, sym_index; ++ asection *o; ++ struct elf_link_hash_entry *sym_hash; ++ Elf_Internal_Sym *isymbuf, *isymend; ++ Elf_Internal_Sym *isym; ++ size_t symcount; ++ size_t offset; ++ bfd_vma src, dest; ++ struct _microblaze_elf_section_data *sdata; ++ ++ /* We only do this once per section. We may be able to delete some code ++ by running multiple passes, but it is not worth it. */ ++ *again = false; ++ ++ /* Only do this for a text section. */ ++ if (bfd_link_relocatable (link_info) ++ || (sec->flags & SEC_RELOC) == 0 ++ || (sec->flags & SEC_CODE) == 0 ++ || sec->reloc_count == 0 ++ || (sdata = microblaze_elf_section_data (sec)) == NULL) ++ return true; ++ ++ BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0)); ++ ++ /* If this is the first time we have been called for this section, ++ initialize the cooked size. */ ++ if (sec->size == 0) ++ sec->size = sec->rawsize; ++ ++ /* Get symbols for this section. */ ++ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; ++ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; ++ symcount = symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (isymbuf == NULL) ++ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount, ++ 0, NULL, NULL, NULL); ++ BFD_ASSERT (isymbuf != NULL); ++ ++ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); ++ if (internal_relocs == NULL) ++ goto error_return; ++ ++ sdata->relax_count = 0; ++ sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) ++ * sizeof (*sdata->relax)); ++ if (sdata->relax == NULL) ++ goto error_return; ++ ++ irelend = internal_relocs + sec->reloc_count; ++ rel_count = 0; ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma symval; ++ if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL) ++ && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ) ++&& (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_TEXTREL_64)) ++ continue; /* Can't delete this reloc. */ ++ ++ /* Get the section contents. */ ++ if (contents == NULL) ++ { ++ if (elf_section_data (sec)->this_hdr.contents != NULL) ++ contents = elf_section_data (sec)->this_hdr.contents; ++ else ++ { ++ contents = (bfd_byte *) bfd_malloc (sec->size); ++ if (contents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, sec, contents, ++ (file_ptr) 0, sec->size)) ++ goto error_return; ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } ++ } ++ ++ /* Get the value of the symbol referred to by the reloc. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ /* A local symbol. */ ++ asection *sym_sec; ++ ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ if (isym->st_shndx == SHN_UNDEF) ++ sym_sec = bfd_und_section_ptr; ++ else if (isym->st_shndx == SHN_ABS) ++ sym_sec = bfd_abs_section_ptr; ++ else if (isym->st_shndx == SHN_COMMON) ++ sym_sec = bfd_com_section_ptr; ++ else ++ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ ++ symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel); ++ } ++ else ++ { ++ unsigned long indx; ++ struct elf_link_hash_entry *h; ++ ++ indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info; ++ h = elf_sym_hashes (abfd)[indx]; ++ BFD_ASSERT (h != NULL); ++ ++ if (h->root.type != bfd_link_hash_defined ++ && h->root.type != bfd_link_hash_defweak) ++ /* This appears to be a reference to an undefined ++ symbol. Just ignore it--it will be caught by the ++ regular reloc processing. */ ++ continue; ++ ++ symval = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ } ++ ++ /* If this is a PC-relative reloc, subtract the instr offset from ++ the symbol value. */ ++ if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ symval = symval + irel->r_addend ++ - (irel->r_offset ++ + sec->output_section->vma ++ + sec->output_offset); ++ } ++ else if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_TEXTREL_64) ++ { ++ symval = symval + irel->r_addend - (sec->output_section->vma); ++ } ++ else ++ symval += irel->r_addend; ++ ++ if ((symval & 0xffff8000) == 0 ++ || (symval & 0xffff8000) == 0xffff8000) ++ { ++ /* We can delete this instruction. */ ++ sdata->relax[sdata->relax_count].addr = irel->r_offset; ++ sdata->relax[sdata->relax_count].size = INST_WORD_SIZE; ++ sdata->relax_count++; ++ ++ /* Rewrite relocation type. */ ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ case R_MICROBLAZE_64_PCREL: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_PCREL_LO); ++ break; ++ case R_MICROBLAZE_64: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_LO); ++ break; ++ case R_MICROBLAZE_TEXTREL_64: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_TEXTREL_32_LO); ++ break; ++ default: ++ /* Cannot happen. */ ++ BFD_ASSERT (false); ++ } ++ } ++ } /* Loop through all relocations. */ ++ ++ /* Loop through the relocs again, and see if anything needs to change. */ ++ if (sdata->relax_count > 0) ++ { ++ shndx = _bfd_elf_section_from_bfd_section (abfd, sec); ++ rel_count = 0; ++ sdata->relax[sdata->relax_count].addr = sec->size; ++ ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma nraddr; ++ ++ /* Get the new reloc address. */ ++ nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec); ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ default: ++ break; ++ case R_MICROBLAZE_64_PCREL: ++ break; ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_32_LO: ++ /* If this reloc is against a symbol defined in this ++ section, we must check the addend to see it will put the value in ++ range to be adjusted, and hence must be changed. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ /* Only handle relocs against .text. */ ++ if (isym->st_shndx == shndx ++ && ELF64_ST_TYPE (isym->st_info) == STT_SECTION) ++ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); ++ } ++ break; ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_64 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ case R_MICROBLAZE_NONE: ++ case R_MICROBLAZE_32_NONE: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ size_t sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ case R_MICROBLAZE_64_NONE: ++ { ++ /* This was a PC-relative 64-bit instruction that was ++ completely resolved. */ ++ size_t sfix, efix; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE; ++ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ irel->r_addend -= (efix - sfix); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ } ++ irel->r_offset = nraddr; ++ } /* Change all relocs in this section. */ ++ ++ /* Look through all other sections. */ ++ for (o = abfd->sections; o != NULL; o = o->next) ++ { ++ Elf_Internal_Rela *irelocs; ++ Elf_Internal_Rela *irelscan, *irelscanend; ++ bfd_byte *ocontents; ++ ++ if (o == sec ++ || (o->flags & SEC_RELOC) == 0 ++ || o->reloc_count == 0) ++ continue; ++ ++ /* We always cache the relocs. Perhaps, if info->keep_memory is ++ false, we should free them, if we are permitted to. */ ++ ++ irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, true); ++ if (irelocs == NULL) ++ goto error_return; ++ ++ ocontents = NULL; ++ irelscanend = irelocs + o->reloc_count; ++ for (irelscan = irelocs; irelscan < irelscanend; irelscan++) ++ { ++ if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) ++ { ++ unsigned int val; ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* hax: We only do the following fixup for debug location lists. */ ++ if (strcmp(".debug_loc", o->name)) ++ continue; ++ ++ /* This was a PC-relative instruction that was completely resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ if (val != irelscan->r_addend) { ++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32 ++ || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend ++ + isym->st_value, ++ 0, ++ sec); ++ } ++ } ++ else if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO) ++ || (ELF32_R_TYPE (irelscan->r_info) ++ == (int) R_MICROBLAZE_32_LO) ++ || (ELF32_R_TYPE (irelscan->r_info) ++ == (int) R_MICROBLAZE_TEXTREL_32_LO)) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ immediate = instr & 0x0000ffff; ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ } ++ ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64 ++ || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_TEXTREL_64)) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ offset = calc_fixup (irelscan->r_addend, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ ++ } ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_64 (abfd, ocontents ++ + irelscan->r_offset, immediate); ++ } ++ } ++ } ++ } ++ ++ /* Adjust the local symbols defined in this section. */ ++ isymend = isymbuf + symtab_hdr->sh_info; ++ for (isym = isymbuf; isym < isymend; isym++) ++ { ++ if (isym->st_shndx == shndx) ++ { ++ isym->st_value -= calc_fixup (isym->st_value, 0, sec); ++ if (isym->st_size) ++ isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec); ++ } ++ } ++ ++ /* Now adjust the global symbols defined in this section. */ ++ isym = isymbuf + symtab_hdr->sh_info; ++ symcount = (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info; ++ for (sym_index = 0; sym_index < symcount; sym_index++) ++ { ++ sym_hash = elf_sym_hashes (abfd)[sym_index]; ++ if ((sym_hash->root.type == bfd_link_hash_defined ++ || sym_hash->root.type == bfd_link_hash_defweak) ++ && sym_hash->root.u.def.section == sec) ++ { ++ sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value, ++ 0, sec); ++ if (sym_hash->size) ++ sym_hash->size -= calc_fixup (sym_hash->root.u.def.value, ++ sym_hash->size, sec); ++ } ++ } ++ ++ /* Physically move the code and change the cooked size. */ ++ dest = sdata->relax[0].addr; ++ for (i = 0; i < sdata->relax_count; i++) ++ { ++ size_t len; ++ src = sdata->relax[i].addr + sdata->relax[i].size; ++ len = (sdata->relax[i+1].addr - sdata->relax[i].addr ++ - sdata->relax[i].size); ++ ++ memmove (contents + dest, contents + src, len); ++ sec->size -= sdata->relax[i].size; ++ dest += len; ++ } ++ ++ elf_section_data (sec)->relocs = internal_relocs; ++ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ ++ symtab_hdr->contents = (bfd_byte *) isymbuf; ++ } ++ ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); ++ ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ { ++ if (! link_info->keep_memory) ++ free (contents); ++ else ++ { ++ /* Cache the section contents for elf_link_input_bfd. */ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } ++ } ++ ++ if (sdata->relax_count == 0) ++ { ++ *again = false; ++ free (sdata->relax); ++ sdata->relax = NULL; ++ } ++ else ++ *again = true; ++ return true; ++ ++ error_return: ++ if (isymbuf != NULL ++ && symtab_hdr->contents != (unsigned char *) isymbuf) ++ free (isymbuf); ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ free (contents); ++ free (sdata->relax); ++ sdata->relax = NULL; ++ sdata->relax_count = 0; ++ return false; ++} ++ ++/* Return the section that should be marked against GC for a given ++ relocation. */ ++ ++static asection * ++microblaze_elf_gc_mark_hook (asection *sec, ++ struct bfd_link_info * info, ++ Elf_Internal_Rela * rel, ++ struct elf_link_hash_entry * h, ++ Elf_Internal_Sym * sym) ++{ ++ if (h != NULL) ++ switch (ELF64_R_TYPE (rel->r_info)) ++ { ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ case R_MICROBLAZE_GNU_VTENTRY: ++ return NULL; ++ } ++ ++ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); ++} ++ ++/* Update the got entry reference counts for the section being removed. */ ++ ++static bool ++microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info * info ATTRIBUTE_UNUSED, ++ asection * sec ATTRIBUTE_UNUSED, ++ const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) ++{ ++ return true; ++} ++ ++/* PIC support. */ ++ ++#define PLT_ENTRY_SIZE 16 ++ ++#define PLT_ENTRY_WORD_0 0xb0000000 /* "imm 0". */ ++#define PLT_ENTRY_WORD_1 0xe9940000 /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT. */ ++#define PLT_ENTRY_WORD_1_NOPIC 0xe9800000 /* "lwi r12,r0,0" - non-PIC object. */ ++#define PLT_ENTRY_WORD_2 0x98186000 /* "brad r12". */ ++#define PLT_ENTRY_WORD_3 0x80000000 /* "nop". */ ++ ++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up ++ shortcuts to them in our hash table. */ ++ ++static bool ++update_local_sym_info (bfd *abfd, ++ Elf_Internal_Shdr *symtab_hdr, ++ unsigned long r_symndx, ++ unsigned int tls_type) ++{ ++ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd); ++ unsigned char *local_got_tls_masks; ++ ++ if (local_got_refcounts == NULL) ++ { ++ bfd_size_type size = symtab_hdr->sh_info; ++ ++ size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks)); ++ local_got_refcounts = bfd_zalloc (abfd, size); ++ if (local_got_refcounts == NULL) ++ return false; ++ elf_local_got_refcounts (abfd) = local_got_refcounts; ++ } ++ ++ local_got_tls_masks = ++ (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info); ++ local_got_tls_masks[r_symndx] |= tls_type; ++ local_got_refcounts[r_symndx] += 1; ++ ++ return true; ++} ++/* Look through the relocs for a section during the first phase. */ ++ ++static bool ++microblaze_elf_check_relocs (bfd * abfd, ++ struct bfd_link_info * info, ++ asection * sec, ++ const Elf_Internal_Rela * relocs) ++{ ++ Elf_Internal_Shdr * symtab_hdr; ++ struct elf_link_hash_entry ** sym_hashes; ++ struct elf_link_hash_entry ** sym_hashes_end; ++ const Elf_Internal_Rela * rel; ++ const Elf_Internal_Rela * rel_end; ++ struct elf64_mb_link_hash_table *htab; ++ asection *sreloc = NULL; ++ ++ if (bfd_link_relocatable (info)) ++ return true; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ symtab_hdr = & elf_tdata (abfd)->symtab_hdr; ++ sym_hashes = elf_sym_hashes (abfd); ++ sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (!elf_bad_symtab (abfd)) ++ sym_hashes_end -= symtab_hdr->sh_info; ++ ++ rel_end = relocs + sec->reloc_count; ++ ++ for (rel = relocs; rel < rel_end; rel++) ++ { ++ unsigned int r_type; ++ struct elf_link_hash_entry * h; ++ unsigned long r_symndx; ++ unsigned char tls_type = 0; ++ ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ r_type = ELF64_R_TYPE (rel->r_info); ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ h = NULL; ++ else ++ { ++ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; ++ while (h->root.type == bfd_link_hash_indirect ++ || h->root.type == bfd_link_hash_warning) ++ h = (struct elf_link_hash_entry *) h->root.u.i.link; ++ /* PR15323, ref flags aren't set for references in the same ++ object. */ ++ h->root.non_ir_ref_regular = 1; ++ } ++ ++ switch (r_type) ++ { ++ /* This relocation describes the C++ object vtable hierarchy. ++ Reconstruct it for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) ++ return false; ++ break; ++ ++ /* This relocation describes which C++ vtable entries are actually ++ used. Record for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTENTRY: ++ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) ++ return false; ++ break; ++ ++ /* This relocation requires .plt entry. */ ++ case R_MICROBLAZE_PLT_64: ++ if (h != NULL) ++ { ++ h->needs_plt = 1; ++ h->plt.refcount += 1; ++ } ++ break; ++ ++ /* This relocation requires .got entry. */ ++ case R_MICROBLAZE_TLSGD: ++ tls_type |= (TLS_TLS | TLS_GD); ++ goto dogottls; ++ case R_MICROBLAZE_TLSLD: ++ tls_type |= (TLS_TLS | TLS_LD); ++ /* Fall through. */ ++ dogottls: ++ sec->has_tls_reloc = 1; ++ /* Fall through. */ ++ case R_MICROBLAZE_GOT_64: ++ if (htab->elf.sgot == NULL) ++ { ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ if (!_bfd_elf_create_got_section (htab->elf.dynobj, info)) ++ return false; ++ } ++ if (h != NULL) ++ { ++ h->got.refcount += 1; ++ elf64_mb_hash_entry (h)->tls_mask |= tls_type; ++ } ++ else ++ { ++ if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) ) ++ return false; ++ } ++ break; ++ ++ case R_MICROBLAZE_GOTOFF_64: ++ case R_MICROBLAZE_GOTOFF_32: ++ if (htab->elf.sgot == NULL) ++ { ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ if (!_bfd_elf_create_got_section (htab->elf.dynobj, info)) ++ return false; ++ } ++ break; ++ ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_64_PCREL: ++ case R_MICROBLAZE_32: ++ case R_MICROBLAZE_IMML_64: ++ { ++ if (h != NULL && !bfd_link_pic (info)) ++ { ++ /* we may need a copy reloc. */ ++ h->non_got_ref = 1; ++ ++ /* we may also need a .plt entry. */ ++ h->plt.refcount += 1; ++ if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL) ++ h->pointer_equality_needed = 1; ++ } ++ ++ ++ /* If we are creating a shared library, and this is a reloc ++ against a global symbol, or a non PC relative reloc ++ against a local symbol, then we need to copy the reloc ++ into the shared library. However, if we are linking with ++ -Bsymbolic, we do not need to copy a reloc against a ++ global symbol which is defined in an object we are ++ including in the link (i.e., DEF_REGULAR is set). At ++ this point we have not seen all the input files, so it is ++ possible that DEF_REGULAR is not set now but will be set ++ later (it is never cleared). In case of a weak definition, ++ DEF_REGULAR may be cleared later by a strong definition in ++ a shared library. We account for that possibility below by ++ storing information in the relocs_copied field of the hash ++ table entry. A similar situation occurs when creating ++ shared libraries and symbol visibility changes render the ++ symbol local. ++ ++ If on the other hand, we are creating an executable, we ++ may need to keep relocations for symbols satisfied by a ++ dynamic library if we manage to avoid copy relocs for the ++ symbol. */ ++ ++ if ((bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && (r_type != R_MICROBLAZE_64_PCREL ++ || (h != NULL ++ && (! info->symbolic ++ || h->root.type == bfd_link_hash_defweak ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && h != NULL ++ && (h->root.type == bfd_link_hash_defweak ++ || !h->def_regular))) ++ { ++ struct elf64_mb_dyn_relocs *p; ++ struct elf64_mb_dyn_relocs **head; ++ ++ /* When creating a shared object, we must copy these ++ relocs into the output file. We create a reloc ++ section in dynobj and make room for the reloc. */ ++ ++ if (sreloc == NULL) ++ { ++ bfd *dynobj; ++ ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ dynobj = htab->elf.dynobj; ++ ++ sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, ++ 2, abfd, 1); ++ if (sreloc == NULL) ++ return false; ++ } ++ ++ /* If this is a global symbol, we count the number of ++ relocations we need for this symbol. */ ++ if (h != NULL) ++ head = &h->dyn_relocs; ++ else ++ { ++ /* Track dynamic relocs needed for local syms too. ++ We really need local syms available to do this ++ easily. Oh well. */ ++ ++ asection *s; ++ Elf_Internal_Sym *isym; ++ void *vpp; ++ ++ isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, ++ abfd, r_symndx); ++ if (isym == NULL) ++ return false; ++ ++ s = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ if (s == NULL) ++ return false; ++ ++ vpp = &elf_section_data (s)->local_dynrel; ++ head = (struct elf64_mb_dyn_relocs **) vpp; ++ } ++ ++ p = *head; ++ if (p == NULL || p->sec != sec) ++ { ++ size_t amt = sizeof *p; ++ p = ((struct elf64_mb_dyn_relocs *) ++ bfd_alloc (htab->elf.dynobj, amt)); ++ if (p == NULL) ++ return false; ++ p->next = *head; ++ *head = p; ++ p->sec = sec; ++ p->count = 0; ++ p->pc_count = 0; ++ } ++ ++ p->count += 1; ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ p->pc_count += 1; ++ } ++ } ++ break; ++ } ++ } ++ ++ return true; ++} ++ ++static bool ++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ if (!htab->sgot && !_bfd_elf_create_got_section (dynobj, info)) ++ return false; ++ ++ if (!_bfd_elf_create_dynamic_sections (dynobj, info)) ++ return false; ++ ++ htab->splt = bfd_get_linker_section (dynobj, ".plt"); ++ htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt"); ++ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss"); ++ if (!bfd_link_pic (info)) ++ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss"); ++ ++ if (!htab->splt || !htab->srelplt || !htab->sdynbss ++ || (!bfd_link_pic (info) && !htab->srelbss)) ++ abort (); ++ ++ return true; ++} ++ ++/* Copy the extra info we tack onto an elf_link_hash_entry. */ ++ ++static void ++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *dir, ++ struct elf_link_hash_entry *ind) ++{ ++ struct elf64_mb_link_hash_entry *edir, *eind; ++ ++ edir = (struct elf64_mb_link_hash_entry *) dir; ++ eind = (struct elf64_mb_link_hash_entry *) ind; ++ ++ if (eind->dyn_relocs != NULL) ++ { ++ if (edir->dyn_relocs != NULL) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (ind->root.type == bfd_link_hash_indirect) ++ abort (); ++ ++ /* Add reloc counts against the weak sym to the strong sym ++ list. Merge any entries against the same section. */ ++ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ struct elf64_mb_dyn_relocs *q; ++ ++ for (q = edir->dyn_relocs; q != NULL; q = q->next) ++ if (q->sec == p->sec) ++ { ++ q->pc_count += p->pc_count; ++ q->count += p->count; ++ *pp = p->next; ++ break; ++ } ++ if (q == NULL) ++ pp = &p->next; ++ } ++ *pp = edir->dyn_relocs; ++ } ++ ++ edir->dyn_relocs = eind->dyn_relocs; ++ eind->dyn_relocs = NULL; ++ } ++ ++ edir->tls_mask |= eind->tls_mask; ++ ++ _bfd_elf_link_hash_copy_indirect (info, dir, ind); ++} ++ ++static bool ++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *h) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry * eh; ++ struct elf64_mb_dyn_relocs *p; ++ asection *sdynbss; ++ asection *s, *srel; ++ unsigned int power_of_two; ++ bfd *dynobj; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ /* If this is a function, put it in the procedure linkage table. We ++ will fill in the contents of the procedure linkage table later, ++ when we know the address of the .got section. */ ++ if (h->type == STT_FUNC ++ || h->needs_plt) ++ { ++ if (h->plt.refcount <= 0 ++ || SYMBOL_CALLS_LOCAL (info, h) ++ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT ++ && h->root.type == bfd_link_hash_undefweak)) ++ { ++ /* This case can occur if we saw a PLT reloc in an input ++ file, but the symbol was never referred to by a dynamic ++ object, or if all references were garbage collected. In ++ such a case, we don't actually need to build a procedure ++ linkage table, and we can just do a PC32 reloc instead. */ ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ return true; ++ } ++ else ++ /* It's possible that we incorrectly decided a .plt reloc was ++ needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in ++ check_relocs. We can't decide accurately between function and ++ non-function syms in check-relocs; Objects loaded later in ++ the link may change h->type. So fix it now. */ ++ h->plt.offset = (bfd_vma) -1; ++ ++ /* If this is a weak symbol, and there is a real definition, the ++ processor independent code will have arranged for us to see the ++ real definition first, and we can just use the same value. */ ++ if (h->is_weakalias) ++ { ++ struct elf_link_hash_entry *def = weakdef (h); ++ BFD_ASSERT (def->root.type == bfd_link_hash_defined); ++ h->root.u.def.section = def->root.u.def.section; ++ h->root.u.def.value = def->root.u.def.value; ++ return true; ++ } ++ ++ /* This is a reference to a symbol defined by a dynamic object which ++ is not a function. */ ++ ++ /* If we are creating a shared library, we must presume that the ++ only references to the symbol are via the global offset table. ++ For such cases we need not do anything here; the relocations will ++ be handled correctly by relocate_section. */ ++ if (bfd_link_pic (info)) ++ return true; ++ ++ /* If there are no references to this symbol that do not use the ++ GOT, we don't need to generate a copy reloc. */ ++ if (!h->non_got_ref) ++ return true; ++ ++ /* If -z nocopyreloc was given, we won't generate them either. */ ++ if (info->nocopyreloc) ++ { ++ h->non_got_ref = 0; ++ return true; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ for (p = eh->dyn_relocs; p != NULL; p = p->next) ++ { ++ s = p->sec->output_section; ++ if (s != NULL && (s->flags & SEC_READONLY) != 0) ++ break; ++ } ++ ++ /* If we didn't find any dynamic relocs in read-only sections, then ++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ ++ if (p == NULL) ++ { ++ h->non_got_ref = 0; ++ return true; ++ } ++ ++ /* We must allocate the symbol in our .dynbss section, which will ++ become part of the .bss section of the executable. There will be ++ an entry for this symbol in the .dynsym section. The dynamic ++ object will contain position independent code, so all references ++ from the dynamic object to this symbol will go through the global ++ offset table. The dynamic linker will use the .dynsym entry to ++ determine the address it must put in the global offset table, so ++ both the dynamic object and the regular object will refer to the ++ same memory location for the variable. */ ++ ++ /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker ++ to copy the initial value out of the dynamic object and into the ++ runtime process image. */ ++ dynobj = elf_hash_table (info)->dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) ++ { ++ htab->srelbss->size += sizeof (Elf64_External_Rela); ++ h->needs_copy = 1; ++ } ++ ++ /* We need to figure out the alignment required for this symbol. I ++ have no idea how ELF linkers handle this. */ ++ power_of_two = bfd_log2 (h->size); ++ if (power_of_two > 3) ++ power_of_two = 3; ++ ++ sdynbss = htab->sdynbss; ++ /* Apply the required alignment. */ ++ sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two)); ++ if (power_of_two > sdynbss->alignment_power) ++ { ++ if (! bfd_set_section_alignment (sdynbss, power_of_two)) ++ return false; ++ } ++ ++ /* Define the symbol as being at this point in the section. */ ++ h->root.u.def.section = s; ++ h->root.u.def.value = s->size; ++ ++ /* Increment the section size to make room for the symbol. */ ++ s->size += h->size; ++ return true; ++} ++ ++/* Allocate space in .plt, .got and associated reloc sections for ++ dynamic relocs. */ ++ ++static bool ++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat) ++{ ++ struct bfd_link_info *info; ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (h->root.type == bfd_link_hash_indirect) ++ return true; ++ ++ info = (struct bfd_link_info *) dat; ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ if (htab->elf.dynamic_sections_created ++ && h->plt.refcount > 0) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return false; ++ } ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h)) ++ { ++ asection *s = htab->elf.splt; ++ ++ /* The first entry in .plt is reserved. */ ++ if (s->size == 0) ++ s->size = PLT_ENTRY_SIZE; ++ ++ h->plt.offset = s->size; ++ ++ /* If this symbol is not defined in a regular file, and we are ++ not generating a shared library, then set the symbol to this ++ location in the .plt. This is required to make function ++ pointers compare as equal between the normal executable and ++ the shared library. */ ++ if (! bfd_link_pic (info) ++ && !h->def_regular) ++ { ++ h->root.u.def.section = s; ++ h->root.u.def.value = h->plt.offset; ++ } ++ ++ /* Make room for this entry. */ ++ s->size += PLT_ENTRY_SIZE; ++ ++ /* We also need to make an entry in the .got.plt section, which ++ will be placed in the .got section by the linker script. */ ++ htab->elf.sgotplt->size += 4; ++ ++ /* We also need to make an entry in the .rel.plt section. */ ++ htab->elf.srelplt->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ if (h->got.refcount > 0) ++ { ++ unsigned int need; ++ asection *s; ++ ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return false; ++ } ++ ++ need = 0; ++ if ((eh->tls_mask & TLS_TLS) != 0) ++ { ++ /* Handle TLS Symbol */ ++ if ((eh->tls_mask & TLS_LD) != 0) ++ { ++ if (!eh->elf.def_dynamic) ++ /* We'll just use htab->tlsld_got.offset. This should ++ always be the case. It's a little odd if we have ++ a local dynamic reloc against a non-local symbol. */ ++ htab->tlsld_got.refcount += 1; ++ else ++ need += 8; ++ } ++ if ((eh->tls_mask & TLS_GD) != 0) ++ need += 8; ++ } ++ else ++ { ++ /* Regular (non-TLS) symbol */ ++ need += 4; ++ } ++ if (need == 0) ++ { ++ h->got.offset = (bfd_vma) -1; ++ } ++ else ++ { ++ s = htab->elf.sgot; ++ h->got.offset = s->size; ++ s->size += need; ++ htab->elf.srelgot->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ h->got.offset = (bfd_vma) -1; ++ ++ if (eh->dyn_relocs == NULL) ++ return true; ++ ++ /* In the shared -Bsymbolic case, discard space allocated for ++ dynamic pc-relative relocs against symbols which turn out to be ++ defined in regular objects. For the normal shared case, discard ++ space for pc-relative relocs that have become local due to symbol ++ visibility changes. */ ++ ++ if (bfd_link_pic (info)) ++ { ++ if (h->def_regular ++ && (h->forced_local ++ || info->symbolic)) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ ++ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ p->count -= p->pc_count; ++ p->pc_count = 0; ++ if (p->count == 0) ++ *pp = p->next; ++ else ++ pp = &p->next; ++ } ++ } ++ else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) ++ h->dyn_relocs = NULL; ++ } ++ else ++ { ++ /* For the non-shared case, discard space for relocs against ++ symbols which turn out to need copy relocs or are not ++ dynamic. */ ++ ++ if (!h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || (htab->elf.dynamic_sections_created ++ && (h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined)))) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return false; ++ } ++ ++ /* If that succeeded, we know we'll be keeping all the ++ relocs. */ ++ if (h->dynindx != -1) ++ goto keep; ++ } ++ ++ h->dyn_relocs = NULL; ++ ++ keep: ; ++ } ++ ++ /* Finally, allocate space. */ ++ for (p = h->dyn_relocs; p != NULL; p = p->next) ++ { ++ asection *sreloc = elf_section_data (p->sec)->sreloc; ++ sreloc->size += p->count * sizeof (Elf64_External_Rela); ++ } ++ ++ return true; ++} ++ ++/* Set the sizes of the dynamic sections. */ ++ ++static bool ++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ bfd *dynobj; ++ asection *s; ++ bfd *ibfd; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ dynobj = htab->elf.dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ ++ /* Set up .got offsets for local syms, and space for local dynamic ++ relocs. */ ++ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) ++ { ++ bfd_signed_vma *local_got; ++ bfd_signed_vma *end_local_got; ++ bfd_size_type locsymcount; ++ Elf_Internal_Shdr *symtab_hdr; ++ unsigned char *lgot_masks; ++ asection *srel; ++ ++ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) ++ continue; ++ ++ for (s = ibfd->sections; s != NULL; s = s->next) ++ { ++ struct elf_dyn_relocs *p; ++ ++ for (p = ((struct elf64_mb_dyn_relocs *) ++ elf_section_data (s)->local_dynrel); ++ p != NULL; ++ p = p->next) ++ { ++ if (!bfd_is_abs_section (p->sec) ++ && bfd_is_abs_section (p->sec->output_section)) ++ { ++ /* Input section has been discarded, either because ++ it is a copy of a linkonce section or due to ++ linker script /DISCARD/, so we'll be discarding ++ the relocs too. */ ++ } ++ else if (p->count != 0) ++ { ++ srel = elf_section_data (p->sec)->sreloc; ++ srel->size += p->count * sizeof (Elf64_External_Rela); ++ if ((p->sec->output_section->flags & SEC_READONLY) != 0) ++ info->flags |= DF_TEXTREL; ++ } ++ } ++ } ++ ++ local_got = elf_local_got_refcounts (ibfd); ++ if (!local_got) ++ continue; ++ ++ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; ++ locsymcount = symtab_hdr->sh_info; ++ end_local_got = local_got + locsymcount; ++ lgot_masks = (unsigned char *) end_local_got; ++ s = htab->elf.sgot; ++ srel = htab->elf.srelgot; ++ ++ for (; local_got < end_local_got; ++local_got, ++lgot_masks) ++ { ++ if (*local_got > 0) ++ { ++ unsigned int need = 0; ++ if ((*lgot_masks & TLS_TLS) != 0) ++ { ++ if ((*lgot_masks & TLS_GD) != 0) ++ need += 8; ++ if ((*lgot_masks & TLS_LD) != 0) ++ htab->tlsld_got.refcount += 1; ++ } ++ else ++ need += 4; ++ ++ if (need == 0) ++ { ++ *local_got = (bfd_vma) -1; ++ } ++ else ++ { ++ *local_got = s->size; ++ s->size += need; ++ if (bfd_link_pic (info)) ++ srel->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ *local_got = (bfd_vma) -1; ++ } ++ } ++ ++ /* Allocate global sym .plt and .got entries, and space for global ++ sym dynamic relocs. */ ++ elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info); ++ ++ if (htab->tlsld_got.refcount > 0) ++ { ++ htab->tlsld_got.offset = htab->elf.sgot->size; ++ htab->elf.sgot->size += 8; ++ if (bfd_link_pic (info)) ++ htab->elf.srelgot->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ htab->tlsld_got.offset = (bfd_vma) -1; ++ ++ if (elf_hash_table (info)->dynamic_sections_created) ++ { ++ /* Make space for the trailing nop in .plt. */ ++ if (htab->elf.splt->size > 0) ++ htab->elf.splt->size += 4; ++ } ++ ++ /* The check_relocs and adjust_dynamic_symbol entry points have ++ determined the sizes of the various dynamic sections. Allocate ++ memory for them. */ ++ for (s = dynobj->sections; s != NULL; s = s->next) ++ { ++ const char *name; ++ bool strip = false; ++ ++ if ((s->flags & SEC_LINKER_CREATED) == 0) ++ continue; ++ ++ /* It's OK to base decisions on the section name, because none ++ of the dynobj section names depend upon the input files. */ ++ name = bfd_section_name (s); ++ ++ if (startswith (name, ".rela")) ++ { ++ if (s->size == 0) ++ { ++ /* If we don't need this section, strip it from the ++ output file. This is to handle .rela.bss and ++ .rela.plt. We must create it in ++ create_dynamic_sections, because it must be created ++ before the linker maps input sections to output ++ sections. The linker does that before ++ adjust_dynamic_symbol is called, and it is that ++ function which decides whether anything needs to go ++ into these sections. */ ++ strip = true; ++ } ++ else ++ { ++ /* We use the reloc_count field as a counter if we need ++ to copy relocs into the output file. */ ++ s->reloc_count = 0; ++ } ++ } ++ else if (s != htab->elf.splt ++ && s != htab->elf.sgot ++ && s != htab->elf.sgotplt ++ && s != htab->elf.sdynbss ++ && s != htab->elf.sdynrelro) ++ { ++ /* It's not one of our sections, so don't allocate space. */ ++ continue; ++ } ++ ++ if (strip) ++ { ++ s->flags |= SEC_EXCLUDE; ++ continue; ++ } ++ ++ /* Allocate memory for the section contents. */ ++ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. ++ Unused entries should be reclaimed before the section's contents ++ are written out, but at the moment this does not happen. Thus in ++ order to prevent writing out garbage, we initialise the section's ++ contents to zero. */ ++ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); ++ if (s->contents == NULL && s->size != 0) ++ return false; ++ } ++ ++ /* ??? Force DF_BIND_NOW? */ ++ info->flags |= DF_BIND_NOW; ++ return _bfd_elf_add_dynamic_tags (output_bfd, info, true); ++} ++ ++/* Finish up dynamic symbol handling. We set the contents of various ++ dynamic sections here. */ ++ ++static bool ++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd, ++ struct bfd_link_info *info, ++ struct elf_link_hash_entry *h, ++ Elf_Internal_Sym *sym) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ if (h->plt.offset != (bfd_vma) -1) ++ { ++ asection *splt; ++ asection *srela; ++ asection *sgotplt; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ bfd_vma plt_index; ++ bfd_vma got_offset; ++ bfd_vma got_addr; ++ ++ /* This symbol has an entry in the procedure linkage table. Set ++ it up. */ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ splt = htab->elf.splt; ++ srela = htab->elf.srelplt; ++ sgotplt = htab->elf.sgotplt; ++ BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL); ++ ++ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved. */ ++ got_offset = (plt_index + 3) * 4; /* 3 reserved ??? */ ++ got_addr = got_offset; ++ ++ /* For non-PIC objects we need absolute address of the GOT entry. */ ++ if (!bfd_link_pic (info)) ++ got_addr += sgotplt->output_section->vma + sgotplt->output_offset; ++ ++ /* Fill in the entry in the procedure linkage table. */ ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff), ++ splt->contents + h->plt.offset); ++ if (bfd_link_pic (info)) ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ else ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2, ++ splt->contents + h->plt.offset + 8); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3, ++ splt->contents + h->plt.offset + 12); ++ ++ /* Any additions to the .got section??? */ ++ /* bfd_put_32 (output_bfd, ++ splt->output_section->vma + splt->output_offset + h->plt.offset + 4, ++ sgotplt->contents + got_offset); */ ++ ++ /* Fill in the entry in the .rela.plt section. */ ++ rela.r_offset = (sgotplt->output_section->vma ++ + sgotplt->output_offset ++ + got_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT); ++ rela.r_addend = 0; ++ loc = srela->contents; ++ loc += plt_index * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); ++ ++ if (!h->def_regular) ++ { ++ /* Mark the symbol as undefined, rather than as defined in ++ the .plt section. Zero the value. */ ++ sym->st_shndx = SHN_UNDEF; ++ sym->st_value = 0; ++ } ++ } ++ ++ /* h->got.refcount to be checked ? */ ++ if (h->got.offset != (bfd_vma) -1 && ++ ! ((h->got.offset & 1) || ++ IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask))) ++ { ++ asection *sgot; ++ asection *srela; ++ bfd_vma offset; ++ ++ /* This symbol has an entry in the global offset table. Set it ++ up. */ ++ ++ sgot = htab->elf.sgot; ++ srela = htab->elf.srelgot; ++ BFD_ASSERT (sgot != NULL && srela != NULL); ++ ++ offset = (sgot->output_section->vma + sgot->output_offset ++ + (h->got.offset &~ (bfd_vma) 1)); ++ ++ /* If this is a -Bsymbolic link, and the symbol is defined ++ locally, we just want to emit a RELATIVE reloc. Likewise if ++ the symbol was forced to be local because of a version file. ++ The entry in the global offset table will already have been ++ initialized in the relocate_section function. */ ++ if (bfd_link_pic (info) ++ && ((info->symbolic && h->def_regular) ++ || h->dynindx == -1)) ++ { ++ asection *sec = h->root.u.def.section; ++ bfd_vma value; ++ ++ value = h->root.u.def.value; ++ if (sec->output_section != NULL) ++ /* PR 21180: If the output section is NULL, then the symbol is no ++ longer needed, and in theory the GOT entry is redundant. But ++ it is too late to change our minds now... */ ++ value += sec->output_section->vma + sec->output_offset; ++ ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ /* symindex= */ 0, ++ R_MICROBLAZE_REL, offset, ++ value); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ h->dynindx, ++ R_MICROBLAZE_GLOB_DAT, ++ offset, 0); ++ } ++ ++ bfd_put_32 (output_bfd, (bfd_vma) 0, ++ sgot->contents + (h->got.offset &~ (bfd_vma) 1)); ++ } ++ ++ if (h->needs_copy) ++ { ++ asection *s; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ ++ /* This symbols needs a copy reloc. Set it up. */ ++ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ rela.r_offset = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY); ++ rela.r_addend = 0; ++ if (h->root.u.def.section == htab->elf.sdynrelro) ++ s = htab->elf.sreldynrelro; ++ else ++ s = htab->elf.srelbss; ++ loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela); ++ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); ++ } ++ ++ /* Mark some specially defined symbols as absolute. */ ++ if (h == htab->elf.hdynamic ++ || h == htab->elf.hgot ++ || h == htab->elf.hplt) ++ sym->st_shndx = SHN_ABS; ++ ++ return true; ++} ++ ++ ++/* Finish up the dynamic sections. */ ++ ++static bool ++microblaze_elf_finish_dynamic_sections (bfd *output_bfd, ++ struct bfd_link_info *info) ++{ ++ bfd *dynobj; ++ asection *sdyn, *sgot; ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ dynobj = htab->elf.dynobj; ++ ++ sdyn = bfd_get_linker_section (dynobj, ".dynamic"); ++ ++ if (htab->elf.dynamic_sections_created) ++ { ++ asection *splt; ++ Elf64_External_Dyn *dyncon, *dynconend; ++ ++ dyncon = (Elf64_External_Dyn *) sdyn->contents; ++ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size); ++ for (; dyncon < dynconend; dyncon++) ++ { ++ Elf_Internal_Dyn dyn; ++ asection *s; ++ bool size; ++ ++ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn); ++ ++ switch (dyn.d_tag) ++ { ++ case DT_PLTGOT: ++ s = htab->elf.sgotplt; ++ size = false; ++ break; ++ ++ case DT_PLTRELSZ: ++ s = htab->elf.srelplt; ++ size = true; ++ break; ++ ++ case DT_JMPREL: ++ s = htab->elf.srelplt; ++ size = false; ++ break; ++ ++ default: ++ continue; ++ } ++ ++ if (s == NULL) ++ dyn.d_un.d_val = 0; ++ else ++ { ++ if (!size) ++ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; ++ else ++ dyn.d_un.d_val = s->size; ++ } ++ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon); ++ } ++ ++ splt = htab->elf.splt; ++ BFD_ASSERT (splt != NULL && sdyn != NULL); ++ ++ /* Clear the first entry in the procedure linkage table, ++ and put a nop in the last four bytes. */ ++ if (splt->size > 0) ++ { ++ memset (splt->contents, 0, PLT_ENTRY_SIZE); ++ bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop. */, ++ splt->contents + splt->size - 4); ++ ++ if (splt->output_section != bfd_abs_section_ptr) ++ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; ++ } ++ } ++ ++ /* Set the first entry in the global offset table to the address of ++ the dynamic section. */ ++ sgot = htab->elf.sgotplt; ++ if (sgot && sgot->size > 0) ++ { ++ if (sdyn == NULL) ++ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); ++ else ++ bfd_put_32 (output_bfd, ++ sdyn->output_section->vma + sdyn->output_offset, ++ sgot->contents); ++ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; ++ } ++ ++ if (htab->elf.sgot && htab->elf.sgot->size > 0) ++ elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize = 4; ++ ++ return true; ++} ++ ++/* Hook called by the linker routine which adds symbols from an object ++ file. We use it to put .comm items in .sbss, and not .bss. */ ++ ++static bool ++microblaze_elf_add_symbol_hook (bfd *abfd, ++ struct bfd_link_info *info, ++ Elf_Internal_Sym *sym, ++ const char **namep ATTRIBUTE_UNUSED, ++ flagword *flagsp ATTRIBUTE_UNUSED, ++ asection **secp, ++ bfd_vma *valp) ++{ ++ if (sym->st_shndx == SHN_COMMON ++ && !bfd_link_relocatable (info) ++ && sym->st_size <= elf_gp_size (abfd)) ++ { ++ /* Common symbols less than or equal to -G nn bytes are automatically ++ put into .sbss. */ ++ *secp = bfd_make_section_old_way (abfd, ".sbss"); ++ if (*secp == NULL ++ || !bfd_set_section_flags (*secp, SEC_IS_COMMON | SEC_SMALL_DATA)) ++ return false; ++ ++ *valp = sym->st_size; ++ } ++ ++ return true; ++} ++ ++#define TARGET_LITTLE_SYM microblaze_elf64_le_vec ++#define TARGET_LITTLE_NAME "elf64-microblazeel" ++ ++#define TARGET_BIG_SYM microblaze_elf64_vec ++#define TARGET_BIG_NAME "elf64-microblaze" ++ ++#define ELF_ARCH bfd_arch_microblaze ++#define ELF_TARGET_ID MICROBLAZE_ELF_DATA ++#define ELF_MACHINE_CODE EM_MICROBLAZE ++#define ELF_MACHINE_ALT1 EM_MICROBLAZE_OLD ++#define ELF_MAXPAGESIZE 0x1000 ++#define elf_info_to_howto microblaze_elf_info_to_howto ++#define elf_info_to_howto_rel NULL ++ ++#define bfd_elf64_bfd_reloc_type_lookup microblaze_elf_reloc_type_lookup ++#define bfd_elf64_bfd_is_local_label_name microblaze_elf_is_local_label_name ++#define bfd_elf64_new_section_hook microblaze_elf_new_section_hook ++#define elf_backend_relocate_section microblaze_elf_relocate_section ++#define bfd_elf64_bfd_relax_section microblaze_elf_relax_section ++#define bfd_elf64_bfd_merge_private_bfd_data microblaze_elf_merge_private_bfd_data ++#define bfd_elf64_bfd_reloc_name_lookup microblaze_elf_reloc_name_lookup ++ ++#define elf_backend_gc_mark_hook microblaze_elf_gc_mark_hook ++#define elf_backend_gc_sweep_hook microblaze_elf_gc_sweep_hook ++#define elf_backend_check_relocs microblaze_elf_check_relocs ++#define elf_backend_copy_indirect_symbol microblaze_elf_copy_indirect_symbol ++#define bfd_elf64_bfd_link_hash_table_create microblaze_elf_link_hash_table_create ++#define elf_backend_can_gc_sections 1 ++#define elf_backend_can_refcount 1 ++#define elf_backend_want_got_plt 1 ++#define elf_backend_plt_readonly 1 ++#define elf_backend_got_header_size 12 ++#define elf_backend_want_dynrelro 1 ++#define elf_backend_rela_normal 1 ++#define elf_backend_dtrel_excludes_plt 1 ++ ++#define elf_backend_adjust_dynamic_symbol microblaze_elf_adjust_dynamic_symbol ++#define elf_backend_create_dynamic_sections microblaze_elf_create_dynamic_sections ++#define elf_backend_finish_dynamic_sections microblaze_elf_finish_dynamic_sections ++#define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol ++#define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections ++#define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook ++ ++#include "elf64-target.h" +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 7cbbc8986a1..597507e53cd 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -65,8 +65,95 @@ + #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \ + ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0) + ++static const char *microblaze_abi_string; ++ ++static const char *const microblaze_abi_strings[] = { ++ "auto", ++ "m64", ++}; ++ ++enum microblaze_abi ++microblaze_abi (struct gdbarch *gdbarch) ++{ ++ microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ return tdep->microblaze_abi; ++} + /* The registers of the Xilinx microblaze processor. */ + ++ static struct cmd_list_element *setmicroblazecmdlist = NULL; ++ static struct cmd_list_element *showmicroblazecmdlist = NULL; ++ ++static void ++microblaze_abi_update (const char *ignore_args, ++ int from_tty, struct cmd_list_element *c) ++{ ++ struct gdbarch_info info; ++ ++ /* Force the architecture to update, and (if it's a microblaze architecture) ++ * microblaze_gdbarch_init will take care of the rest. */ ++// gdbarch_info_init (&info); ++ gdbarch_update_p (info); ++} ++ ++ ++static enum microblaze_abi ++global_microblaze_abi (void) ++{ ++ int i; ++ ++ for (i = 0; microblaze_abi_strings[i] != NULL; i++) ++ if (microblaze_abi_strings[i] == microblaze_abi_string) ++ return (enum microblaze_abi) i; ++ ++// internal_error (__FILE__, __LINE__, _("unknown ABI string")); ++} ++ ++static void ++show_microblaze_abi (struct ui_file *file, ++ int from_tty, ++ struct cmd_list_element *ignored_cmd, ++ const char *ignored_value) ++{ ++ enum microblaze_abi global_abi = global_microblaze_abi (); ++ enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ()); ++ const char *actual_abi_str = microblaze_abi_strings[actual_abi]; ++ ++#if 1 ++ if (global_abi == MICROBLAZE_ABI_AUTO) ++ fprintf_filtered ++ (file, ++ "The microblaze ABI is set automatically (currently \"%s\").\n", ++ actual_abi_str); ++ else if (global_abi == actual_abi) ++ fprintf_filtered ++ (file, ++ "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n", ++ actual_abi_str); ++ else ++ { ++#endif ++ /* Probably shouldn't happen... */ ++ fprintf_filtered (file, ++ "The (auto detected) microblaze ABI \"%s\" is in use " ++ "even though the user setting was \"%s\".\n", ++ actual_abi_str, microblaze_abi_strings[global_abi]); ++ } ++} ++ ++static void ++show_microblaze_command (const char *args, int from_tty) ++{ ++ help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout); ++} ++ ++static void ++set_microblaze_command (const char *args, int from_tty) ++{ ++ printf_unfiltered ++ ("\"set microblaze\" must be followed by an appropriate subcommand.\n"); ++ help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout); ++} ++ + static const char * const microblaze_register_names[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", +@@ -85,9 +172,21 @@ static const char * const microblaze_register_names[] = + static unsigned int microblaze_debug_flag = 0; + int reg_size = 4; + ++unsigned int ++microblaze_abi_regsize (struct gdbarch *gdbarch) ++{ ++ switch (microblaze_abi (gdbarch)) ++ { ++ case MICROBLAZE_ABI_M64: ++ return 8; ++ default: ++ return 4; ++ } ++} ++ + #define microblaze_debug(fmt, ...) \ + debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \ +- fmt, ## __VA_ARGS__) ++ fmt, ## __VA_ARGS__) + + + /* Return the name of register REGNUM. */ +@@ -867,15 +966,30 @@ static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { + tdesc_arch_data_up tdesc_data; ++ enum microblaze_abi microblaze_abi, found_abi, wanted_abi; + const struct target_desc *tdesc = info.target_desc; + ++ /* What has the user specified from the command line? */ ++ wanted_abi = global_microblaze_abi (); ++ if (gdbarch_debug) ++ fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", ++ wanted_abi); ++ if (wanted_abi != MICROBLAZE_ABI_AUTO) ++ microblaze_abi = wanted_abi; ++ + /* If there is already a candidate, use it. */ + arches = gdbarch_list_lookup_by_info (arches, &info); +- if (arches != NULL) ++ if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) + return arches->gdbarch; ++ ++ if (microblaze_abi == MICROBLAZE_ABI_M64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } + if (tdesc == NULL) + { +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + { + tdesc = tdesc_microblaze64; + reg_size = 8; +@@ -890,7 +1004,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.core"); + else +@@ -904,7 +1018,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + for (i = 0; i < MICROBLAZE_NUM_REGS; i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, + microblaze_register_names[i]); +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.stack-protect"); + else +@@ -954,7 +1068,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + set_gdbarch_ptr_bit (gdbarch, 64); + break; + } +- ++ if(microblaze_abi == MICROBLAZE_ABI_M64) ++ set_gdbarch_ptr_bit (gdbarch, 64); + + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); +@@ -1014,6 +1129,38 @@ _initialize_microblaze_tdep () + { + gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init); + ++// static struct cmd_list_element *setmicroblazecmdlist = NULL; ++// static struct cmd_list_element *showmicroblazecmdlist = NULL; ++ ++ /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ ++ ++ add_setshow_prefix_cmd ("microblaze", no_class, ++ _("Various microblaze specific commands."), ++ _("Various microblaze specific commands."), ++ &setmicroblazecmdlist,&showmicroblazecmdlist, ++ &setlist,&showlist); ++#if 0 ++ add_prefix_cmd ("microblaze", no_class, set_microblaze_command, ++ _("Various microblaze specific commands."), ++ &setmicroblazecmdlist, "set microblaze ", 0, &setlist); ++ ++ add_prefix_cmd ("microblaze", no_class, show_microblaze_command, ++ _("Various microblaze specific commands."), ++ &showmicroblazecmdlist, "show microblaze ", 0, &showlist); ++#endif ++ ++ /* Allow the user to override the ABI. */ ++ add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings, ++ µblaze_abi_string, _("\ ++Set the microblaze ABI used by this program."), _("\ ++Show the microblaze ABI used by this program."), _("\ ++This option can be set to one of:\n\ ++ auto - the default ABI associated with the current binary\n\ ++ m64"), ++ microblaze_abi_update, ++ show_microblaze_abi, ++ &setmicroblazecmdlist, &showmicroblazecmdlist); ++ + initialize_tdesc_microblaze_with_stack_protect (); + initialize_tdesc_microblaze (); + initialize_tdesc_microblaze64_with_stack_protect (); +@@ -1028,5 +1175,4 @@ When non-zero, microblaze specific debugging is enabled."), + NULL, + &setdebuglist, &showdebuglist); + +- + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 81f7f30cb8e..f6cef7c9a33 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -19,9 +19,17 @@ + + #ifndef MICROBLAZE_TDEP_H + #define MICROBLAZE_TDEP_H 1 +- ++#include "objfiles.h" + #include "gdbarch.h" + ++struct gdbarch; ++enum microblaze_abi ++ { ++ MICROBLAZE_ABI_AUTO = 0, ++ MICROBLAZE_ABI_M64, ++ }; ++ ++enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch); + /* Microblaze architecture-specific information. */ + struct microblaze_gregset + { +@@ -35,11 +43,14 @@ struct microblaze_gdbarch_tdep : gdbarch_tdep_base + { + int dummy; // declare something. + ++ enum microblaze_abi microblaze_abi {}; ++ enum microblaze_abi found_abi {}; + /* Register sets. */ + struct regset *gregset; + size_t sizeof_gregset; + struct regset *fpregset; + size_t sizeof_fpregset; ++ int register_size; + }; + + /* Register numbers. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch new file mode 100644 index 00000000..6ec184d0 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch @@ -0,0 +1,74 @@ +From bd2d24cf21943babe2e0a73cf68da273a38d7058 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 21 Jul 2022 11:45:01 +0530 +Subject: [PATCH 09/53] =?UTF-8?q?Depth:=20Total=20number=20of=20inline=20f?= + =?UTF-8?q?unctions=20[refer=20inline-frame.c]=20state->skipped=5Fframes?= + =?UTF-8?q?=20:=20Number=20of=20inline=20functions=20skipped.=20the=20curr?= + =?UTF-8?q?ent=20unwind=5Fpc=20is=20causing=20an=20issue=20when=20we=20try?= + =?UTF-8?q?=20to=20step=20into=20inline=20functions[Depth=20is=20becoming?= + =?UTF-8?q?=200].=20It=E2=80=99s=20incrementing=20pc=20by=208=20even=20wit?= + =?UTF-8?q?h=20si=20instruction.?= +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Aayush Misra +--- + gdb/features/microblaze64.xml | 1 + + gdb/microblaze-tdep.c | 14 +++----------- + 2 files changed, 4 insertions(+), 11 deletions(-) + +diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml +index 515d18e65cf..9c1b7d22003 100644 +--- a/gdb/features/microblaze64.xml ++++ b/gdb/features/microblaze64.xml +@@ -7,5 +7,6 @@ + + + ++ microblaze64 + + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 597507e53cd..aed5f2ec30c 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -513,16 +513,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, + static CORE_ADDR + microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) + { +- gdb_byte buf[4]; + CORE_ADDR pc; +- +- frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf); +- pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); +- /* For sentinel frame, return address is actual PC. For other frames, +- return address is pc+8. This is a workaround because gcc does not +- generate correct return address in CIE. */ +- if (frame_relative_level (next_frame) >= 0) +- pc += 8; ++ pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM); + return pc; + } + +@@ -553,7 +545,6 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) + ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, + &cache); + +- + if (ostart_pc > start_pc) + return ostart_pc; + return start_pc; +@@ -660,7 +651,8 @@ static const struct frame_unwind microblaze_frame_unwind = + microblaze_frame_this_id, + microblaze_frame_prev_register, + NULL, +- default_frame_sniffer ++ default_frame_sniffer, ++ NULL, + }; + + static CORE_ADDR +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch new file mode 100644 index 00000000..78e4970b --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch @@ -0,0 +1,133 @@ +From 3616ef25911d9fa8b5c0e4883f19131da48896d5 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 29 Feb 2024 10:53:04 +0530 +Subject: [PATCH 10/53] Fix gdb-14 build errors for microblaze-xilinx-elf + 2023.2 merge + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 12 ++++++++++++ + gdb/frame.c | 2 +- + gdb/microblaze-tdep.c | 17 +++++++++++------ + 3 files changed, 24 insertions(+), 7 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 6cd9753a592..119d266f95a 100755 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -750,6 +750,18 @@ microblaze_elf_info_to_howto (bfd * abfd, + return true; + } + ++/* Relax table contains information about instructions which can ++ be removed by relaxation -- replacing a long address with a ++ short address. */ ++struct relax_table ++{ ++ /* Address where bytes may be deleted. */ ++ bfd_vma addr; ++ ++ /* Number of bytes to be deleted. */ ++ size_t size; ++}; ++ + struct _microblaze_elf_section_data + { + struct bfd_elf_section_data elf; +diff --git a/gdb/frame.c b/gdb/frame.c +index 859e1a6553d..94bb026c4d9 100644 +--- a/gdb/frame.c ++++ b/gdb/frame.c +@@ -1319,7 +1319,7 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum) + int i; + + const gdb_byte *buf = NULL; +- if (value_entirely_available(value)) { ++ if (value->entirely_available()) { + gdb::array_view buf = value->contents (); + } + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index aed5f2ec30c..e1a7a49eb84 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -75,7 +75,7 @@ static const char *const microblaze_abi_strings[] = { + enum microblaze_abi + microblaze_abi (struct gdbarch *gdbarch) + { +- microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + return tdep->microblaze_abi; + } + /* The registers of the Xilinx microblaze processor. */ +@@ -120,12 +120,12 @@ show_microblaze_abi (struct ui_file *file, + + #if 1 + if (global_abi == MICROBLAZE_ABI_AUTO) +- fprintf_filtered ++ gdb_printf + (file, + "The microblaze ABI is set automatically (currently \"%s\").\n", + actual_abi_str); + else if (global_abi == actual_abi) +- fprintf_filtered ++ gdb_printf + (file, + "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n", + actual_abi_str); +@@ -133,7 +133,7 @@ show_microblaze_abi (struct ui_file *file, + { + #endif + /* Probably shouldn't happen... */ +- fprintf_filtered (file, ++ gdb_printf (file, + "The (auto detected) microblaze ABI \"%s\" is in use " + "even though the user setting was \"%s\".\n", + actual_abi_str, microblaze_abi_strings[global_abi]); +@@ -934,7 +934,7 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, + void *cb_data, + const struct regcache *regcache) + { +- struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); + +@@ -942,6 +942,8 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, + } + + ++#if 0 ++// compilation errors - function is not actually used ? + static void + make_regs (struct gdbarch *arch) + { +@@ -953,6 +955,7 @@ make_regs (struct gdbarch *arch) + set_gdbarch_ptr_bit (arch, 64); + } + } ++#endif + + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -964,7 +967,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + /* What has the user specified from the command line? */ + wanted_abi = global_microblaze_abi (); + if (gdbarch_debug) +- fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", ++ gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", + wanted_abi); + if (wanted_abi != MICROBLAZE_ABI_AUTO) + microblaze_abi = wanted_abi; +@@ -1038,6 +1041,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + gdbarch *gdbarch + = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep)); + ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ + tdep->gregset = NULL; + tdep->sizeof_gregset = 0; + tdep->fpregset = NULL; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch new file mode 100644 index 00000000..d3da41d5 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch @@ -0,0 +1,28 @@ +From 9037b1a9e862263ba935314e8604a922d14c8dd4 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 29 Feb 2024 10:55:16 +0530 +Subject: [PATCH 11/53] fix gdb microblaze-xilinx-elf crash issue on invocation + Regression from merging microblaze 64-bit support + +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index e1a7a49eb84..f9cb3dfda33 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -1124,6 +1124,9 @@ void _initialize_microblaze_tdep (); + void + _initialize_microblaze_tdep () + { ++ //Setting abi to auto manually, should be able to modify in 'arch'_gdbarch_init function ++ microblaze_abi_string = microblaze_abi_strings[0]; ++ + gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init); + + // static struct cmd_list_element *setmicroblazecmdlist = NULL; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0012-Add-mlittle-endian-and-mbig-endian-flags.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0012-Add-mlittle-endian-and-mbig-endian-flags.patch new file mode 100644 index 00000000..e1074c85 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0012-Add-mlittle-endian-and-mbig-endian-flags.patch @@ -0,0 +1,46 @@ +From 05a5677c1b5cd7f109c49e6697b6716f7ac0fb97 Mon Sep 17 00:00:00 2001 +From: nagaraju +Date: Tue, 19 Mar 2013 17:18:23 +0530 +Subject: [PATCH 12/53] Add mlittle-endian and mbig-endian flags + +Added support in gas for mlittle-endian and mbig-endian flags +as options. + +Updated show usage for MicroBlaze specific assembler options +to include new entries. + +Signed-off-by:nagaraju +Signed-off-by: David Holsgrove +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index c971d187095..62238646a52 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -37,6 +37,8 @@ + + #define OPTION_EB (OPTION_MD_BASE + 0) + #define OPTION_EL (OPTION_MD_BASE + 1) ++#define OPTION_LITTLE (OPTION_MD_BASE + 2) ++#define OPTION_BIG (OPTION_MD_BASE + 3) + + void microblaze_generate_symbol (char *sym); + static bool check_spl_reg (unsigned *); +@@ -2565,9 +2567,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + switch (c) + { + case OPTION_EB: ++ case OPTION_BIG: + target_big_endian = 1; + break; + case OPTION_EL: ++ case OPTION_LITTLE: + target_big_endian = 0; + break; + default: +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0013-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0013-Disable-the-warning-message-for-eh_frame_hdr.patch new file mode 100644 index 00000000..31529d0d --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0013-Disable-the-warning-message-for-eh_frame_hdr.patch @@ -0,0 +1,35 @@ +From a622ee3ff40515edf05a61a77fbcd8999ecf0905 Mon Sep 17 00:00:00 2001 +From: "Edgar E. Iglesias" +Date: Fri, 22 Jun 2012 01:20:20 +0200 +Subject: [PATCH 13/53] Disable the warning message for eh_frame_hdr + +Signed-off-by: Edgar E. Iglesias + +Conflicts: + bfd/elf-eh-frame.c +Signed-off-by: Aayush Misra +--- + bfd/elf-eh-frame.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c +index 9a504234163..5e393558293 100644 +--- a/bfd/elf-eh-frame.c ++++ b/bfd/elf-eh-frame.c +@@ -1045,10 +1045,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info, + goto success; + + free_no_table: ++/* FIXME: Remove the microblaze specifics when relaxing gets fixed. */ ++if (bfd_get_arch(abfd) != bfd_arch_microblaze) { + _bfd_error_handler + /* xgettext:c-format */ + (_("error in %pB(%pA); no .eh_frame_hdr table will be created"), + abfd, sec); ++} + hdr_info->u.dwarf.table = false; + free (sec_info); + success: +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch new file mode 100644 index 00000000..7574067d --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0014-Fix-relaxation-of-assembler-resolved-references-Fixu.patch @@ -0,0 +1,48 @@ +From 965a464418e8c8968453206f27763043fb38dc64 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 8 Nov 2016 11:54:08 +0530 +Subject: [PATCH 14/53] Fix relaxation of assembler resolved references,Fixup + debug_loc sections after linker relaxation Adds a new reloctype + R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to the + linker when the linker manages to fully resolve a local symbol reference. + +This is a workaround for design flaws in the assembler to +linker interface with regards to linker relaxation. + +Signed-off-by: Edgar E. Iglesias +Signed-off-by: David Holsgrove + +Conflicts: + bfd/elf32-microblaze.c + binutils/readelf.c + include/elf/microblaze.h + +Conflicts: + binutils/readelf.c + +Conflicts: + bfd/elf32-microblaze.c +Signed-off-by: Aayush Misra +--- + binutils/readelf.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/binutils/readelf.c b/binutils/readelf.c +index 5e4ad6ea6ad..3ca9f3697d1 100644 +--- a/binutils/readelf.c ++++ b/binutils/readelf.c +@@ -15288,6 +15288,11 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) + || reloc_type == 9 /* R_MICROBLAZE_64_NONE. */); + default: + return false; ++ /* REVISIT microblaze-binutils-merge */ ++ case EM_MICROBLAZE: ++ return reloc_type == 33 /* R_MICROBLAZE_32_NONE. */ ++ || reloc_type == 0 /* R_MICROBLAZE_NONE. */ ++ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */ + } + } + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch new file mode 100644 index 00000000..c46af2e7 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch @@ -0,0 +1,43 @@ +From 07743ed9395bfea466cdbdf0bbe9566fa93165de Mon Sep 17 00:00:00 2001 +From: David Holsgrove +Date: Wed, 27 Feb 2013 13:56:11 +1000 +Subject: [PATCH 15/53] upstream change to garbage collection sweep causes mb + regression + +Upstream change for PR13177 now clears the def_regular during gc_sweep of a +section. (All other archs in binutils/bfd/elf32-*.c received an update +to a warning about unresolvable relocations - this warning is not present +in binutils/bfd/elf32-microblaze.c, but this warning check would not +prevent the error being seen) + +The visible issue with this change is when running a c++ application +in Petalinux which links libstdc++.so for exception handling it segfaults +on execution. + +This does not occur if static linking libstdc++.a, so its during the +relocations for a shared lib with garbage collection this occurs + +Signed-off-by: David Holsgrove + +Conflicts: + bfd/elflink.c +Signed-off-by: Aayush Misra +--- + bfd/elflink.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/bfd/elflink.c b/bfd/elflink.c +index c2494b3e12e..1f8f54cd4e6 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -6633,7 +6633,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data) + + inf = (struct elf_gc_sweep_symbol_info *) data; + (*inf->hide_symbol) (inf->info, h, true); +- h->def_regular = 0; + h->ref_regular = 0; + h->ref_regular_nonweak = 0; + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0016-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0016-Add-new-bit-field-instructions.patch new file mode 100644 index 00000000..aab6c5d1 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0016-Add-new-bit-field-instructions.patch @@ -0,0 +1,219 @@ +From 39ef5af3dd4551b24a47c8e48af67478183a7149 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Mon, 18 Jul 2016 12:24:28 +0530 +Subject: [PATCH 16/53] Add new bit-field instructions + +This patches adds new bsefi and bsifi instructions. +BSEFI- The instruction shall extract a bit field from a +register and place it right-adjusted in the destination register. +The other bits in the destination register shall be set to zero +BSIFI- The instruction shall insert a right-adjusted bit field +from a register at another position in the destination register. +The rest of the bits in the destination register shall be unchanged + +Signed-off-by :Nagaraju Mekala + +Conflicts: + opcodes/microblaze-dis.c + +Conflicts: + gas/config/tc-microblaze.c + opcodes/microblaze-opc.h + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 82 ++++++++++++++++---------------------- + opcodes/microblaze-dis.c | 18 ++++++++- + opcodes/microblaze-opc.h | 6 +++ + 3 files changed, 58 insertions(+), 48 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 62238646a52..f13efcae979 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -1150,88 +1150,76 @@ md_assemble (char * str) + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (immed << IMM_LOW) & IMM5_MASK; + break; +- +- case INST_TYPE_RD_R1_IMMW_IMMS: ++ case INST_TYPE_RD_R1_IMM5_IMM5: + if (strcmp (op_end, "")) +- op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else + { +- as_fatal (_("Error in statement syntax")); +- reg1 = 0; +- } +- ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } + if (strcmp (op_end, "")) +- op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ ++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ + else + { +- as_fatal (_("Error in statement syntax")); +- reg2 = 0; +- } ++ as_fatal (_("Error in statement syntax")); ++ reg2 = 0; ++ } + + /* Check for spl registers. */ + if (check_spl_reg (®1)) +- as_fatal (_("Cannot use special register with this instruction")); ++ as_fatal (_("Cannot use special register with this instruction")); + if (check_spl_reg (®2)) +- as_fatal (_("Cannot use special register with this instruction")); ++ as_fatal (_("Cannot use special register with this instruction")); + + /* Width immediate value. */ + if (strcmp (op_end, "")) +- op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH); ++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH); + else +- as_fatal (_("Error in statement syntax")); +- ++ as_fatal (_("Error in statement syntax")); + if (exp.X_op != O_constant) + { +- as_warn (_( +- "Symbol used as immediate width value for bit field instruction")); +- immed = 1; +- } ++ as_warn (_("Symbol used as immediate width value for bit field instruction")); ++ immed = 1; ++ } + else +- immed = exp.X_add_number; +- ++ immed = exp.X_add_number; + if (opcode->instr == bsefi && immed > 31) +- as_fatal (_("Width value must be less than 32")); ++ as_fatal (_("Width value must be less than 32")); + + /* Shift immediate value. */ + if (strcmp (op_end, "")) +- op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM); ++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM); + else +- as_fatal (_("Error in statement syntax")); +- ++ as_fatal (_("Error in statement syntax")); + if (exp.X_op != O_constant) +- { +- as_warn (_( +- "Symbol used as immediate shift value for bit field instruction")); +- immed2 = 0; +- } ++ { ++ as_warn (_("Symbol used as immediate shift value for bit field instruction")); ++ immed2 = 0; ++ } + else +- { +- output = frag_more (isize); +- immed2 = exp.X_add_number; +- } +- ++ { ++ output = frag_more (isize); ++ immed2 = exp.X_add_number; ++ } + if (immed2 != (immed2 % 32)) +- { +- as_warn (_("Shift value greater than 32. using ")); +- immed2 = immed2 % 32; +- } ++ { ++ as_warn (_("Shift value greater than 32. using ")); ++ immed2 = immed2 % 32; ++ } + + /* Check combined value. */ + if (immed + immed2 > 32) +- as_fatal (_("Width value + shift value must not be greater than 32")); ++ as_fatal (_("Width value + shift value must not be greater than 32")); + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; +- + if (opcode->instr == bsefi) +- inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */ ++ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */ + else +- inst |= ((immed + immed2 - 1) & IMM5_MASK) +- << IMM_WIDTH_LOW; /* bsifi */ +- ++ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */ + inst |= (immed2 << IMM_LOW) & IMM5_MASK; + break; +- + case INST_TYPE_R1_R2: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index ee447cecc3f..45135f9d264 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -113,7 +113,19 @@ get_field_immw (struct string_buf *buf, long instr) + } + + static char * +-get_field_rfsl (struct string_buf *buf, long instr) ++get_field_imm5width (struct string_buf *buf, long instr) ++{ ++ char *p = strbuf (buf); ++ ++ if (instr & 0x00004000) ++ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ ++ else ++ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */ ++ return p; ++} ++ ++static char * ++get_field_rfsl (struct string_buf *buf,long instr) + { + char *p = strbuf (buf); + +@@ -462,6 +474,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), + get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; ++ /* For bit field insns. */ ++ case INST_TYPE_RD_R1_IMM5_IMM5: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst)); ++ break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (&buf, inst)); +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index afc1220e357..a952b9ac3c2 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -67,6 +67,9 @@ + #define INST_TYPE_RD_R1_IMML 23 + #define INST_TYPE_R1_IMML 24 + ++/* For bsefi and bsifi */ ++#define INST_TYPE_RD_R1_IMM5_IMM5 21 ++ + #define INST_TYPE_NONE 25 + + +@@ -586,5 +589,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMML ((long) 0xffffff8000000000L) + #define MAX_IMML ((long) 0x0000007fffffffffL) + ++#define MIN_IMM_WIDTH ((int) 0x00000001) ++#define MAX_IMM_WIDTH ((int) 0x00000020) ++ + #endif /* MICROBLAZE_OPC */ + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch new file mode 100644 index 00000000..f679971d --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0017-fixed-bug-in-GCC-so-that-It-will-support-.long-0U-an.patch @@ -0,0 +1,34 @@ +From ea27bc6ec052b20f4c193054ecdef9bd4ecbcde7 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Fri, 29 Sep 2017 18:00:23 +0530 +Subject: [PATCH 17/53] fixed bug in GCC so that It will support .long 0U and + .long 0u + +Signed-off-by: Aayush Misra +--- + gas/expr.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/gas/expr.c b/gas/expr.c +index 3a01b88e310..8214bdf3263 100644 +--- a/gas/expr.c ++++ b/gas/expr.c +@@ -833,6 +833,15 @@ operand (expressionS *expressionP, enum expr_mode mode) + break; + } + } ++ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u')) ++ { ++ input_line_pointer--; ++ ++ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri) ++ ? 0 : 10, ++ expressionP); ++ break; ++ } + c = *input_line_pointer; + switch (c) + { +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0018-Compiler-will-give-error-messages-in-more-detail-for.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0018-Compiler-will-give-error-messages-in-more-detail-for.patch new file mode 100644 index 00000000..c63f4566 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0018-Compiler-will-give-error-messages-in-more-detail-for.patch @@ -0,0 +1,37 @@ +From 3056650d65b5bfa34bf16cd1ee7829a64dfb19ac Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 21 Feb 2018 12:32:02 +0530 +Subject: [PATCH 18/53] Compiler will give error messages in more detail for + mxl-gp-opt flag.. + +Signed-off-by: Aayush Misra +--- + ld/ldmain.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/ld/ldmain.c b/ld/ldmain.c +index e90c2021b33..e135939fade 100644 +--- a/ld/ldmain.c ++++ b/ld/ldmain.c +@@ -1575,6 +1575,18 @@ reloc_overflow (struct bfd_link_info *info, + break; + case bfd_link_hash_defined: + case bfd_link_hash_defweak: ++ ++ if((strcmp(reloc_name,"R_MICROBLAZE_SRW32") == 0) && entry->type == bfd_link_hash_defined) ++ { ++ einfo (_(" relocation truncated to fit: don't enable small data pointer optimizations[mxl-gp-opt] if extern or multiple declarations used: " ++ "%s against symbol `%T' defined in %A section in %B"), ++ reloc_name, entry->root.string, ++ entry->u.def.section, ++ entry->u.def.section == bfd_abs_section_ptr ++ ? info->output_bfd : entry->u.def.section->owner); ++ break; ++ } ++ + einfo (_(" relocation truncated to fit: " + "%s against symbol `%pT' defined in %pA section in %pB"), + reloc_name, entry->root.string, +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0019-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0019-initial-support-for-MicroBlaze-64-bit-m64.patch new file mode 100644 index 00000000..452c1418 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0019-initial-support-for-MicroBlaze-64-bit-m64.patch @@ -0,0 +1,202 @@ +From 06c3e8ef9bdea329af1099e14abbde3d76a114a9 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 1 Nov 2021 19:06:53 +0530 +Subject: [PATCH 19/53] initial support for MicroBlaze 64 bit [-m64] + +Conflicts: + bfd/elf32-microblaze.c + include/elf/common.h + ld/Makefile.am + ld/Makefile.in +signed-off-by:Nagaraju Mekala + Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + bfd/bfd-in2.h | 14 ++++++++++++-- + bfd/libbfd.h | 2 ++ + bfd/reloc.c | 18 +++++++++++++++--- + gas/config/tc-microblaze.h | 4 +++- + ld/Makefile.am | 2 ++ + ld/configure.tgt | 3 +++ + opcodes/microblaze-dis.c | 8 ++++++-- + opcodes/microblaze-opc.h | 11 +++++++---- + 8 files changed, 50 insertions(+), 12 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 7ccc155394d..8b2815d7303 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -6472,8 +6472,13 @@ done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative value in +- two words (with an imm instruction). The relocation is PC-relative +- GOT offset. */ ++ two words (with an imm instruction). No relocation is done here ++ only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imm instruction). The relocation is ++PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + + /* This is a 64 bit reloc that stores the 32 bit pc relative +@@ -6481,6 +6486,11 @@ value in two words (with an imml instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GPC, + ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). The relocation is ++PC-relative GOT offset */ ++ BFD_RELOC_MICROBLAZE_64_GPC, ++ + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + GOT offset */ +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index 7a3e558d70a..603ed8260cb 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -3005,7 +3005,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", ++ "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", ++ "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index fda67e5ffda..3e8647f601e 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6677,12 +6677,24 @@ ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative value in + two words (with an imm instruction). No relocation is done here - + only used for relaxing. ++ENUM ++ BFD_RELOC_MICROBLAZE_64 ++ENUMDOC ++ This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative value in +- two words (with an imm instruction). The relocation is PC-relative +- GOT offset. ++ This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64_GPC ++ENUMDOC ++ This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). The relocation is ++ PC-relative GOT offset + ENUM + BFD_RELOC_MICROBLAZE_64_GOT + ENUMDOC +diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h +index 20d0da5496d..f0f861c3373 100644 +--- a/gas/config/tc-microblaze.h ++++ b/gas/config/tc-microblaze.h +@@ -81,7 +81,9 @@ extern const struct relax_type md_relax_table[]; + + #ifdef OBJ_ELF + +-#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel") ++#define TARGET_FORMAT microblaze_target_format() ++extern const char *microblaze_target_format (void); ++//#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel") + + #define ELF_TC_SPECIAL_SECTIONS \ + { ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, \ +diff --git a/ld/Makefile.am b/ld/Makefile.am +index f9ee05b1400..c1daf842444 100644 +--- a/ld/Makefile.am ++++ b/ld/Makefile.am +@@ -424,6 +424,8 @@ ALL_64_EMULATION_SOURCES = \ + eelf32ltsmipn32.c \ + eelf32ltsmipn32_fbsd.c \ + eelf32mipswindiss.c \ ++ eelf64microblazeel.c \ ++ eelf64microblaze.c \ + eelf64_aix.c \ + eelf64_ia64.c \ + eelf64_ia64_fbsd.c \ +diff --git a/ld/configure.tgt b/ld/configure.tgt +index f937f78b876..a9d3004e445 100644 +--- a/ld/configure.tgt ++++ b/ld/configure.tgt +@@ -527,6 +527,9 @@ microblaze*-linux*) targ_emul="elf32mb_linux" + microblazeel*) targ_emul=elf32microblazeel + targ_extra_emuls=elf32microblaze + ;; ++microblazeel64*) targ_emul=elf64microblazeel ++ targ_extra_emuls=elf64microblaze ++ ;; + microblaze*) targ_emul=elf32microblaze + targ_extra_emuls=elf32microblazeel + ;; +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 45135f9d264..45262aef909 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -457,6 +457,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_R1_R2_SPECIAL: + print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), + get_field_r2 (&buf, inst)); ++ break; ++ case INST_TYPE_IMML: ++ print_func (stream, "\t%s", get_field_imml (&buf, inst)); ++ /* TODO: Also print symbol */ + break; + case INST_TYPE_RD_IMM15: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), +@@ -475,8 +479,8 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; + /* For bit field insns. */ +- case INST_TYPE_RD_R1_IMM5_IMM5: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst)); ++ case INST_TYPE_RD_R1_IMMW_IMMS: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; + /* For tuqula instruction */ + case INST_TYPE_RD: +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index a952b9ac3c2..d9d05721dae 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -68,7 +68,13 @@ + #define INST_TYPE_R1_IMML 24 + + /* For bsefi and bsifi */ +-#define INST_TYPE_RD_R1_IMM5_IMM5 21 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 ++ ++/* For 64-bit instructions */ ++#define INST_TYPE_IMML 22 ++#define INST_TYPE_RD_R1_IMML 23 ++#define INST_TYPE_R1_IMML 24 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 + + #define INST_TYPE_NONE 25 + +@@ -589,8 +595,5 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMML ((long) 0xffffff8000000000L) + #define MAX_IMML ((long) 0x0000007fffffffffL) + +-#define MIN_IMM_WIDTH ((int) 0x00000001) +-#define MAX_IMM_WIDTH ((int) 0x00000020) +- + #endif /* MICROBLAZE_OPC */ + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0020-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0020-initial-support-for-MicroBlaze-64-bit-m64.patch new file mode 100644 index 00000000..f3073f1e --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0020-initial-support-for-MicroBlaze-64-bit-m64.patch @@ -0,0 +1,82 @@ +From f46a81a4ffa73453403a5e99e7005a8f1d974ecf Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 1 Nov 2021 19:06:53 +0530 +Subject: [PATCH 20/53] initial support for MicroBlaze 64 bit [-m64] + +Conflicts: + bfd/elf32-microblaze.c + include/elf/common.h + ld/Makefile.am + ld/Makefile.in +signed-off-by:Nagaraju Mekala + Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + ld/emulparams/elf64microblaze.sh | 23 +++++++++++++++++++++++ + ld/emulparams/elf64microblazeel.sh | 23 +++++++++++++++++++++++ + 2 files changed, 46 insertions(+) + create mode 100644 ld/emulparams/elf64microblaze.sh + create mode 100644 ld/emulparams/elf64microblazeel.sh + +diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh +new file mode 100644 +index 00000000000..9c7b0eb7080 +--- /dev/null ++++ b/ld/emulparams/elf64microblaze.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh +new file mode 100644 +index 00000000000..9c7b0eb7080 +--- /dev/null ++++ b/ld/emulparams/elf64microblazeel.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0021-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0021-Added-relocations-for-MB-X.patch new file mode 100644 index 00000000..24e0894d --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0021-Added-relocations-for-MB-X.patch @@ -0,0 +1,108 @@ +From 39ba1e8a13828ac3c860a72b95c3abae024044b5 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 11 Sep 2018 17:30:17 +0530 +Subject: [PATCH 21/53] Added relocations for MB-X + +Conflicts: + bfd/bfd-in2.h + gas/config/tc-microblaze.c + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/reloc.c | 26 ++++++++++++++------------ + gas/config/tc-microblaze.c | 11 +++++++++++ + 2 files changed, 25 insertions(+), 12 deletions(-) + +diff --git a/bfd/reloc.c b/bfd/reloc.c +index 3e8647f601e..c5c0ce5d060 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6661,12 +6661,6 @@ ENUMDOC + the form "Symbol Op Symbol". + ENUM + BFD_RELOC_MICROBLAZE_32_NONE +-ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative value in +- two words (with an imm instruction). No relocation is done here - +- only used for relaxing. +-ENUM +- BFD_RELOC_MICROBLAZE_32_NONE + ENUMDOC + This is a 32 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is +@@ -6685,12 +6679,6 @@ ENUMDOC + done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64_GPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is +@@ -7929,6 +7917,20 @@ ENUMX + ENUMDOC + Linux eBPF relocations. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_EPIPHANY_SIMM8 + ENUMDOC +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index f13efcae979..9b8b129e309 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -91,6 +91,8 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; + #define TLSTPREL_OFFSET 16 + #define TEXT_OFFSET 17 + #define TEXT_PC_OFFSET 18 ++#define DEFINED_64_OFFSET 19 ++#define DEFINED_64_PC_OFFSET 20 + + /* Initialize the relax table. */ + const relax_typeS md_relax_table[] = +@@ -114,6 +116,8 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 16: TLSTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }, /* 19: DEFINED_64_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 } /* 20: DEFINED_64_PC_OFFSET. */ + }; + + static htab_t opcode_hash_control; /* Opcode mnemonics. */ +@@ -2330,6 +2334,13 @@ md_estimate_size_before_relax (fragS * fragP, + /* Variable part does not change. */ + fragP->fr_var = INST_WORD_SIZE*2; + } ++ else if (streq (fragP->fr_opcode, str_microblaze_64)) ++ { ++ /* Used as an absolute value. */ ++ fragP->fr_subtype = DEFINED_64_OFFSET; ++ /* Variable part does not change. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } + else if (streq (fragP->fr_opcode, str_microblaze_ro_anchor)) + { + /* It is accessed using the small data read only anchor. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0022-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0022-initial-support-for-MicroBlaze-64-bit-m64.patch new file mode 100644 index 00000000..5ef086bd --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0022-initial-support-for-MicroBlaze-64-bit-m64.patch @@ -0,0 +1,958 @@ +From 6e30e2ce72e9257daae0633a6b57e7a5c4c918f2 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 1 Nov 2021 19:06:53 +0530 +Subject: [PATCH 22/53] initial support for MicroBlaze 64 bit [-m64] + +Conflicts: + bfd/elf32-microblaze.c + include/elf/common.h + ld/Makefile.am + ld/Makefile.in +signed-off-by:Nagaraju Mekala + Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 8 + + bfd/reloc.c | 36 +-- + gas/config/tc-microblaze.c | 556 ++++++++++++++++++++++++++++++++----- + 3 files changed, 499 insertions(+), 101 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 119d266f95a..ca92df647c9 100755 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -1666,6 +1666,14 @@ microblaze_elf_relocate_section (bfd *output_bfd, + outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); + outrel.r_addend = relocation + addend; + } ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, ++ contents + offset + endian); ++ } + else + { + BFD_FAIL (); +diff --git a/bfd/reloc.c b/bfd/reloc.c +index c5c0ce5d060..6eb93e993f0 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6677,8 +6677,20 @@ ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC ++ENUMDOC ++ This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64_GPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is +@@ -7894,18 +7906,6 @@ ENUMDOC + + This is a 64 bit reloc that stores 64-bit thread pointer relative offset + to two words (uses imml instruction). +-ENUM +-BFD_RELOC_MICROBLAZE_64, +-ENUMDOC +- This is a 64 bit reloc that stores the 64 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, +-ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing + ENUM + BFD_RELOC_BPF_64 + ENUMX +@@ -7919,18 +7919,6 @@ ENUMDOC + + This is a 64 bit reloc that stores 64-bit thread pointer relative offset + to two words (uses imml instruction). +-ENUM +-BFD_RELOC_MICROBLAZE_64, +-ENUMDOC +- This is a 64 bit reloc that stores the 64 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, +-ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing + ENUM + BFD_RELOC_EPIPHANY_SIMM8 + ENUMDOC +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 9b8b129e309..6640266cc47 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -35,10 +35,13 @@ + #define streq(a,b) (strcmp (a, b) == 0) + #endif + ++static int microblaze_arch_size = 0; ++ + #define OPTION_EB (OPTION_MD_BASE + 0) + #define OPTION_EL (OPTION_MD_BASE + 1) + #define OPTION_LITTLE (OPTION_MD_BASE + 2) + #define OPTION_BIG (OPTION_MD_BASE + 3) ++#define OPTION_M64 (OPTION_MD_BASE + 4) + + void microblaze_generate_symbol (char *sym); + static bool check_spl_reg (unsigned *); +@@ -360,7 +363,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED) + Integer arg to pass to the function. */ + /* If the pseudo-op is not found in this table, it searches in the obj-elf.c, + and then in the read.c table. */ +-const pseudo_typeS md_pseudo_table[] = ++pseudo_typeS md_pseudo_table[] = + { + {"lcomm", microblaze_s_lcomm, 1}, + {"data8", cons, 1}, /* Same as byte. */ +@@ -369,6 +372,7 @@ const pseudo_typeS md_pseudo_table[] = + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ + {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ ++ {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, +@@ -378,6 +382,7 @@ const pseudo_typeS md_pseudo_table[] = + #endif + {"sbss", microblaze_s_sbss, 0}, + {"word", cons, 4}, ++ {"dword", cons, 8}, + {"frame", s_ignore, 0}, + {"mask", s_ignore, 0}, /* Emitted by gcc. */ + {NULL, NULL, 0} +@@ -749,6 +754,74 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) + return new_pointer; + } + ++ static char * ++parse_imml (char * s, expressionS * e, long min, long max) ++{ ++ char *new_pointer; ++ char *atp; ++ int itype, ilen; ++ ++ ilen = 0; ++ ++ /* Find the start of "@GOT" or "@PLT" suffix (if any) */ ++ for (atp = s; *atp != '@'; atp++) ++ if (is_end_of_line[(unsigned char) *atp]) ++ break; ++ ++ if (*atp == '@') ++ { ++ itype = match_imm (atp + 1, &ilen); ++ if (itype != 0) ++ { ++ *atp = 0; ++ e->X_md = itype; ++ } ++ else ++ { ++ atp = NULL; ++ e->X_md = 0; ++ ilen = 0; ++ } ++ *atp = 0; ++ } ++ else ++ { ++ atp = NULL; ++ e->X_md = 0; ++ } ++ ++ if (atp && !GOT_symbol) ++ { ++ GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); ++ } ++ ++ new_pointer = parse_exp (s, e); ++ ++ if (!GOT_symbol && ! strncmp (s, GOT_SYMBOL_NAME, 20)) ++ { ++ GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); ++ } ++ ++ if (e->X_op == O_absent) ++ ; /* An error message has already been emitted. */ ++ else if ((e->X_op != O_constant && e->X_op != O_symbol) ) ++ as_fatal (_("operand must be a constant or a label")); ++ else if ((e->X_op == O_constant) && ((long) e->X_add_number < min ++ || (long) e->X_add_number > max)) ++ { ++ as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"), ++ min, max, (long) e->X_add_number); ++ } ++ ++ if (atp) ++ { ++ *atp = '@'; /* restore back (needed?) */ ++ if (new_pointer >= atp) ++ new_pointer += ilen + 1; /* sizeof (imm_suffix) + 1 for '@' */ ++ } ++ return new_pointer; ++} ++ + static char * + check_got (int * got_type, int * got_len) + { +@@ -803,7 +876,7 @@ check_got (int * got_type, int * got_len) + extern bfd_reloc_code_real_type + parse_cons_expression_microblaze (expressionS *exp, int size) + { +- if (size == 4) ++ if (size == 4 || (microblaze_arch_size == 64 && size == 8)) + { + /* Handle @GOTOFF et.al. */ + char *save, *gotfree_copy; +@@ -835,6 +908,7 @@ parse_cons_expression_microblaze (expressionS *exp, int size) + + static const char * str_microblaze_ro_anchor = "RO"; + static const char * str_microblaze_rw_anchor = "RW"; ++static const char * str_microblaze_64 = "64"; + + static bool + check_spl_reg (unsigned * reg) +@@ -893,9 +967,10 @@ md_assemble (char * str) + unsigned reg2; + unsigned reg3; + unsigned isize; +- unsigned int immed = 0, immed2 = 0, temp; ++ unsigned long immed = 0, immed2 = 0, temp; + expressionS exp; + char name[20]; ++ long immedl; + + /* Drop leading whitespace. */ + while (ISSPACE (* str)) +@@ -1014,8 +1089,9 @@ md_assemble (char * str) + as_fatal (_("lmi pseudo instruction should not use a label in imm field")); + else if (streq (name, "smi")) + as_fatal (_("smi pseudo instruction should not use a label in imm field")); +- +- if (reg2 == REG_ROSDP) ++ if(streq (name, "lli") || streq (name, "sli")) ++ opc = str_microblaze_64; ++ else if (reg2 == REG_ROSDP) + opc = str_microblaze_ro_anchor; + else if (reg2 == REG_RWSDP) + opc = str_microblaze_rw_anchor; +@@ -1082,36 +1158,60 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +- else +- { +- temp = immed & 0xFFFF8000; +- if ((temp != 0) && (temp != 0xFFFF8000)) +- { ++ else if (streq (name, "lli") || streq (name, "sli")) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFF8000) ++ { + /* Needs an immediate inst. */ + opcode1 + = (struct op_code_struct *) str_hash_find (opcode_hash_control, +- "imm"); ++ "imml"); + if (opcode1 == NULL) + { +- as_bad (_("unknown opcode \"%s\""), "imm"); ++ as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } +- + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); +- } +- inst |= (reg1 << RD_LOW) & RD_MASK; +- inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM_MASK; +- } ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { ++ temp = immed & 0xFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + +- case INST_TYPE_RD_R1_IMM5: ++ case INST_TYPE_RD_R1_IMMS: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else +@@ -1145,16 +1245,22 @@ md_assemble (char * str) + immed = exp.X_add_number; + } + +- if (immed != (immed % 32)) ++ if ((immed != (immed % 32)) && ++ (opcode->instr == bslli || opcode->instr == bsrai || opcode->instr == bsrli)) + { + as_warn (_("Shift value > 32. using ")); + immed = immed % 32; + } ++ else if (immed != (immed % 64)) ++ { ++ as_warn (_("Shift value > 64. using ")); ++ immed = immed % 64; ++ } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM5_MASK; ++ inst |= (immed << IMM_LOW) & IMM6_MASK; + break; +- case INST_TYPE_RD_R1_IMM5_IMM5: ++ case INST_TYPE_RD_R1_IMMW_IMMS: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else +@@ -1178,7 +1284,7 @@ md_assemble (char * str) + + /* Width immediate value. */ + if (strcmp (op_end, "")) +- op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH); ++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM); + else + as_fatal (_("Error in statement syntax")); + if (exp.X_op != O_constant) +@@ -1190,6 +1296,8 @@ md_assemble (char * str) + immed = exp.X_add_number; + if (opcode->instr == bsefi && immed > 31) + as_fatal (_("Width value must be less than 32")); ++ else if (opcode->instr == bslefi && immed > 63) ++ as_fatal (_("Width value must be less than 64")); + + /* Shift immediate value. */ + if (strcmp (op_end, "")) +@@ -1206,23 +1314,31 @@ md_assemble (char * str) + output = frag_more (isize); + immed2 = exp.X_add_number; + } +- if (immed2 != (immed2 % 32)) +- { +- as_warn (_("Shift value greater than 32. using ")); ++ if ((immed2 != (immed2 % 32)) && (opcode->instr == bsefi || opcode->instr == bsifi)) ++ { ++ ++ as_warn (_("Shift value greater than 32. using ")); + immed2 = immed2 % 32; + } ++ else if (immed2 != (immed2 % 64)) ++ { ++ as_warn (_("Shift value greater than 64. using ")); ++ immed2 = immed2 % 64; ++ } + + /* Check combined value. */ +- if (immed + immed2 > 32) ++ if ((immed + immed2 > 32) && (opcode->instr == bsefi || opcode->instr == bsifi)) + as_fatal (_("Width value + shift value must not be greater than 32")); ++ else if (immed + immed2 > 64) ++ as_fatal (_("Width value + shift value must not be greater than 64")); + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; +- if (opcode->instr == bsefi) +- inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */ ++ if (opcode->instr == bsefi || opcode->instr == bslefi) ++ inst |= (immed & IMM6_MASK) << IMM_WIDTH_LOW; /* bsefi or bslefi */ + else +- inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */ +- inst |= (immed2 << IMM_LOW) & IMM5_MASK; ++ inst |= ((immed + immed2 - 1) & IMM6_MASK) << IMM_WIDTH_LOW; /* bsifi or bslifi */ ++ inst |= (immed2 << IMM_LOW) & IMM6_MASK; + break; + case INST_TYPE_R1_R2: + if (strcmp (op_end, "")) +@@ -1722,12 +1838,20 @@ md_assemble (char * str) + case INST_TYPE_IMM: + if (streq (name, "imm")) + as_fatal (_("An IMM instruction should not be present in the .s file")); +- +- op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ if (microblaze_arch_size == 64) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + + if (exp.X_op != O_constant) + { +- char *opc = NULL; ++ char *opc; ++ if (microblaze_arch_size == 64 && (streq (name, "breai") || ++ streq (name, "breaid") || ++ streq (name, "brai") || streq (name, "braid"))) ++ opc = str_microblaze_64; ++ else ++ opc = NULL; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -1750,29 +1874,53 @@ md_assemble (char * str) + immed = exp.X_add_number; + } + +- +- temp = immed & 0xFFFF8000; +- if ((temp != 0) && (temp != 0xFFFF8000)) +- { +- /* Needs an immediate inst. */ +- opcode1 +- = (struct op_code_struct *) str_hash_find (opcode_hash_control, +- "imm"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imm"); +- return; ++ if (microblaze_arch_size == 64 && (streq (name, "breai") || ++ streq (name, "breaid") || ++ streq (name, "brai") || streq (name, "braid"))) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); + } ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { ++ temp = immed & 0xFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } + +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- inst |= (immed << IMM_LOW) & IMM_MASK; ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_NONE: +@@ -1903,6 +2051,7 @@ struct option md_longopts[] = + {"EL", no_argument, NULL, OPTION_EL}, + {"mlittle-endian", no_argument, NULL, OPTION_EL}, + {"mbig-endian", no_argument, NULL, OPTION_EB}, ++ {"m64", no_argument, NULL, OPTION_M64}, + { NULL, no_argument, NULL, 0} + }; + +@@ -1947,13 +2096,23 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; ++ case DEFINED_64_OFFSET: ++ if (fragP->fr_symbol == GOT_symbol) ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GPC); ++ else ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64); ++ fragP->fr_fix += INST_WORD_SIZE * 2; ++ fragP->fr_var = 0; ++ break; + case DEFINED_ABS_SEGMENT: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, +- fragP->fr_offset, false, BFD_RELOC_64); ++ fragP->fr_offset, true, BFD_RELOC_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2174,23 +2333,38 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_64_PCREL: + case BFD_RELOC_64: + case BFD_RELOC_MICROBLAZE_64_TEXTREL: ++ case BFD_RELOC_MICROBLAZE_64: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ { ++ /* Generate the imm instruction. */ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + +- /* Generate the imm instruction. */ +- opcode1 +- = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imm"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; +- ++ inst1 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ } ++ else ++ { ++ /* Generate the imm instruction. */ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; ++ } + buf[0] = INST_BYTE0 (inst1); + buf[1] = INST_BYTE1 (inst1); + buf[2] = INST_BYTE2 (inst1); +@@ -2219,6 +2393,7 @@ md_apply_fix (fixS * fixP, + /* Fall through. */ + + case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ case BFD_RELOC_MICROBLAZE_64_GPC: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +@@ -2226,13 +2401,17 @@ md_apply_fix (fixS * fixP, + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; +- + /* Generate the imm instruction. */ +- opcode1 +- = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ else ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { +- as_bad (_("unknown opcode \"%s\""), "imm"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ else ++ as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + +@@ -2256,6 +2435,8 @@ md_apply_fix (fixS * fixP, + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; ++ else if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; + else +@@ -2298,6 +2479,32 @@ md_estimate_size_before_relax (fragS * fragP, + as_bad (_("Absolute PC-relative value in relaxation code. Assembler error.....")); + abort (); + } ++ else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type ++ && !S_IS_WEAK (fragP->fr_symbol)) ++ { ++ if (fragP->fr_opcode != NULL) { ++ if(streq (fragP->fr_opcode, str_microblaze_64)) ++ { ++ /* Used as an absolute value. */ ++ fragP->fr_subtype = DEFINED_64_OFFSET; ++ /* Variable part does not change. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ else ++ { ++ fragP->fr_subtype = DEFINED_PC_OFFSET; ++ /* Don't know now whether we need an imm instruction. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ } ++ else ++ { ++ fragP->fr_subtype = DEFINED_PC_OFFSET; ++ /* Don't know now whether we need an imm instruction. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ } ++#if 0 + else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type && + !S_IS_WEAK (fragP->fr_symbol)) + { +@@ -2305,6 +2512,7 @@ md_estimate_size_before_relax (fragS * fragP, + /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } ++#endif + else if (S_IS_DEFINED (fragP->fr_symbol) + && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0)) + { +@@ -2316,7 +2524,14 @@ md_estimate_size_before_relax (fragS * fragP, + } + else + { +- fragP->fr_subtype = UNDEFINED_PC_OFFSET; ++ if (fragP->fr_opcode != NULL) { ++ if (streq (fragP->fr_opcode, str_microblaze_64)) ++ fragP->fr_subtype = DEFINED_64_PC_OFFSET; ++ else ++ fragP->fr_subtype = UNDEFINED_PC_OFFSET; ++ } ++ else ++ fragP->fr_subtype = UNDEFINED_PC_OFFSET; + fragP->fr_var = INST_WORD_SIZE*2; + } + break; +@@ -2395,6 +2610,33 @@ md_estimate_size_before_relax (fragS * fragP, + abort (); + } + } ++#if 0 //revisit ++ else if (streq (name, "lli") || streq (name, "sli")) ++ { ++ temp = immed & 0xFFFFFFFFFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++#endif + else + { + /* We know the abs value: Should never happen. */ +@@ -2414,6 +2656,7 @@ md_estimate_size_before_relax (fragS * fragP, + case TLSLD_OFFSET: + case TLSTPREL_OFFSET: + case TLSDTPREL_OFFSET: ++ case DEFINED_64_OFFSET: + fragP->fr_var = INST_WORD_SIZE*2; + break; + case DEFINED_RO_SEGMENT: +@@ -2467,7 +2710,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) + else + { + /* The case where we are going to resolve things... */ +- if (fixp->fx_r_type == BFD_RELOC_64_PCREL) ++ if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64) + return fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE; + else + return fixp->fx_where + fixp->fx_frag->fr_address; +@@ -2500,6 +2743,8 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_32_RWSDA: + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +@@ -2515,6 +2760,143 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_64_TEXTREL: + code = fixp->fx_r_type; + break; ++ /* For 64-bit instructions */ ++ case INST_TYPE_RD_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg2 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (& reg1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ if (check_spl_reg (& reg2)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ //char *opc = str_microblaze_64; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ (char *) opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (®1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ //char *opc = NULL; ++ char *opc = str_microblaze_64; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ (char *) opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ ++ inst |= (reg1 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_IMML: ++ as_fatal (_("An IMML instruction should not be present in the .s file")); ++ break; + + default: + switch (F (fixp->fx_size, fixp->fx_pcrel)) +@@ -2560,6 +2942,18 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + return rel; + } + ++/* Called by TARGET_FORMAT. */ ++const char * ++microblaze_target_format (void) ++{ ++ ++ if (microblaze_arch_size == 64) ++ return "elf64-microblazeel"; ++ else ++ return target_big_endian ? "elf32-microblaze" : "elf32-microblazeel"; ++} ++ ++ + int + md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + { +@@ -2573,6 +2967,10 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + case OPTION_LITTLE: + target_big_endian = 0; + break; ++ case OPTION_M64: ++ //if (arg != NULL && strcmp (arg, "64") == 0) ++ microblaze_arch_size = 64; ++ break; + default: + return 0; + } +@@ -2588,6 +2986,7 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED) + fprintf (stream, _(" MicroBlaze specific assembler options:\n")); + fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu")); + fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu")); ++ fprintf (stream, " -%-23s%s\n", "m64", N_("generate 64-bit elf")); + } + + +@@ -2625,7 +3024,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- r = BFD_RELOC_64; ++ if (microblaze_arch_size == 64) ++ r = BFD_RELOC_32; ++ else ++ r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-relocations-for-MB-X.patch new file mode 100644 index 00000000..f92dd068 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-relocations-for-MB-X.patch @@ -0,0 +1,246 @@ +From fb4a4d6855092f5b0b201e40234782822cd63a66 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 11 Sep 2018 17:30:17 +0530 +Subject: [PATCH 23/53] Added relocations for MB-X + +Conflicts: + bfd/bfd-in2.h + gas/config/tc-microblaze.c + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/libbfd.h | 2 -- + bfd/reloc.c | 26 ++++++++------- + gas/config/tc-microblaze.c | 68 ++++++++++++-------------------------- + 3 files changed, 36 insertions(+), 60 deletions(-) + +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index 603ed8260cb..7a3e558d70a 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -3005,9 +3005,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", +- "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", +- "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index 6eb93e993f0..b6c9c22a0be 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6634,6 +6634,20 @@ ENUM + ENUMDOC + Address of a GOT entry. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_32_LO + ENUMDOC +@@ -6671,12 +6685,6 @@ ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative value in + two words (with an imm instruction). No relocation is done here - + only used for relaxing. +-ENUM +- BFD_RELOC_MICROBLAZE_64 +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imm instruction). No relocation is +- done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_PCREL, + ENUMDOC +@@ -6689,12 +6697,6 @@ ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64_GPC +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imm instruction). The relocation is +- PC-relative GOT offset + ENUM + BFD_RELOC_MICROBLAZE_64_GOT + ENUMDOC +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 6640266cc47..29fb6360169 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -2096,23 +2096,29 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; ++ case DEFINED_64_PC_OFFSET: ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PCREL); ++ fragP->fr_fix += INST_WORD_SIZE * 2; ++ fragP->fr_var = 0; ++ break; + case DEFINED_64_OFFSET: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, +- fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GPC); ++ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64_GPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, +- fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64); ++ fragP->fr_offset, false, BFD_RELOC_MICROBLAZE_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; + case DEFINED_ABS_SEGMENT: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, +- fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC); ++ fragP->fr_offset, true, BFD_RELOC_MICROBLAZE_64_GOTPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, +- fragP->fr_offset, true, BFD_RELOC_64); ++ fragP->fr_offset, false, BFD_RELOC_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2334,10 +2340,12 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_64: + case BFD_RELOC_MICROBLAZE_64_TEXTREL: + case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_64_PCREL: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64 ++ || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + { + /* Generate the imm instruction. */ + opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +@@ -2350,6 +2358,10 @@ md_apply_fix (fixS * fixP, + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_64; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; + } + else + { +@@ -2435,8 +2447,6 @@ md_apply_fix (fixS * fixP, + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; +- else if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) +- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; + else +@@ -2486,9 +2496,9 @@ md_estimate_size_before_relax (fragS * fragP, + if(streq (fragP->fr_opcode, str_microblaze_64)) + { + /* Used as an absolute value. */ +- fragP->fr_subtype = DEFINED_64_OFFSET; ++ fragP->fr_subtype = DEFINED_64_PC_OFFSET; + /* Variable part does not change. */ +- fragP->fr_var = INST_WORD_SIZE; ++ fragP->fr_var = INST_WORD_SIZE*2; + } + else + { +@@ -2504,15 +2514,6 @@ md_estimate_size_before_relax (fragS * fragP, + fragP->fr_var = INST_WORD_SIZE; + } + } +-#if 0 +- else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type && +- !S_IS_WEAK (fragP->fr_symbol)) +- { +- fragP->fr_subtype = DEFINED_PC_OFFSET; +- /* Don't know now whether we need an imm instruction. */ +- fragP->fr_var = INST_WORD_SIZE; +- } +-#endif + else if (S_IS_DEFINED (fragP->fr_symbol) + && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0)) + { +@@ -2610,33 +2611,6 @@ md_estimate_size_before_relax (fragS * fragP, + abort (); + } + } +-#if 0 //revisit +- else if (streq (name, "lli") || streq (name, "sli")) +- { +- temp = immed & 0xFFFFFFFFFFFF8000; +- if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000)) +- { +- /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- inst |= (reg1 << RD_LOW) & RD_MASK; +- inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM_MASK; +- } +-#endif + else + { + /* We know the abs value: Should never happen. */ +@@ -2657,6 +2631,7 @@ md_estimate_size_before_relax (fragS * fragP, + case TLSTPREL_OFFSET: + case TLSDTPREL_OFFSET: + case DEFINED_64_OFFSET: ++ case DEFINED_64_PC_OFFSET: + fragP->fr_var = INST_WORD_SIZE*2; + break; + case DEFINED_RO_SEGMENT: +@@ -2710,7 +2685,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) + else + { + /* The case where we are going to resolve things... */ +- if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + return fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE; + else + return fixp->fx_where + fixp->fx_frag->fr_address; +@@ -2745,6 +2720,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GPC: + case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_64_PCREL: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch new file mode 100644 index 00000000..18698b02 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0024-Fixed-MB-x-relocation-issues-Added-imml-for-required.patch @@ -0,0 +1,52 @@ +From 88f7a313f8e21021dacfc8da2c490a433f596fd8 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 28 Sep 2018 12:04:55 +0530 +Subject: [PATCH 24/53] -Fixed MB-x relocation issues -Added imml for required + MB-x instructions + +Conflicts: + bfd/elf64-microblaze.c + gas/config/tc-microblaze.c + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 29fb6360169..e43ea82a2cc 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -363,7 +363,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED) + Integer arg to pass to the function. */ + /* If the pseudo-op is not found in this table, it searches in the obj-elf.c, + and then in the read.c table. */ +-pseudo_typeS md_pseudo_table[] = ++const pseudo_typeS md_pseudo_table[] = + { + {"lcomm", microblaze_s_lcomm, 1}, + {"data8", cons, 1}, /* Same as byte. */ +@@ -2357,7 +2357,7 @@ md_apply_fix (fixS * fixP, + + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) + fixP->fx_r_type = BFD_RELOC_64; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) +@@ -2946,6 +2946,8 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + case OPTION_M64: + //if (arg != NULL && strcmp (arg, "64") == 0) + microblaze_arch_size = 64; ++ // UPSTREAM/REVISIT - md_pseudo_table is const ++ // md_pseudo_table[7].poc_val = 8; + break; + default: + return 0; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0025-Fixed-address-computation-issues-with-64bit-address-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0025-Fixed-address-computation-issues-with-64bit-address-.patch new file mode 100644 index 00000000..d480388c --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0025-Fixed-address-computation-issues-with-64bit-address-.patch @@ -0,0 +1,160 @@ +From 585f95d1510385ed3f67e76e2ad8f9a27b3ee32a Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 9 Oct 2018 10:14:22 +0530 +Subject: [PATCH 25/53] - Fixed address computation issues with 64bit address - + Fixed imml dissassamble issue + +Conflicts: + gas/config/tc-microblaze.c + opcodes/microblaze-dis.c + +Conflicts: + bfd/elf64-microblaze.c + +Conflicts: + bfd/elf64-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 2 +- + gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++----- + 2 files changed, 67 insertions(+), 9 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index ca92df647c9..9f542f55ebd 100755 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -2131,7 +2131,7 @@ microblaze_elf_relax_section (bfd *abfd, + efix = calc_fixup (target_address, 0, sec); + + /* Validate the in-band val. */ +- val = bfd_get_32 (abfd, contents + irel->r_offset); ++ val = bfd_get_64 (abfd, contents + irel->r_offset); + if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { + fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); + } +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index e43ea82a2cc..544732649a5 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -372,7 +372,6 @@ const pseudo_typeS md_pseudo_table[] = + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ + {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ +- {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, +@@ -2317,18 +2316,74 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_RVA: + case BFD_RELOC_32_PCREL: + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: ++ /* Don't do anything if the symbol is not defined. */ ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ { ++ if ((fixP->fx_r_type == BFD_RELOC_RVA) && (microblaze_arch_size == 64)) ++ { ++ if (target_big_endian) ++ { ++ buf[0] |= ((val >> 56) & 0xff); ++ buf[1] |= ((val >> 48) & 0xff); ++ buf[2] |= ((val >> 40) & 0xff); ++ buf[3] |= ((val >> 32) & 0xff); ++ buf[4] |= ((val >> 24) & 0xff); ++ buf[5] |= ((val >> 16) & 0xff); ++ buf[6] |= ((val >> 8) & 0xff); ++ buf[7] |= (val & 0xff); ++ } ++ else ++ { ++ buf[7] |= ((val >> 56) & 0xff); ++ buf[6] |= ((val >> 48) & 0xff); ++ buf[5] |= ((val >> 40) & 0xff); ++ buf[4] |= ((val >> 32) & 0xff); ++ buf[3] |= ((val >> 24) & 0xff); ++ buf[2] |= ((val >> 16) & 0xff); ++ buf[1] |= ((val >> 8) & 0xff); ++ buf[0] |= (val & 0xff); ++ } ++ } ++ else { ++ if (target_big_endian) ++ { ++ buf[0] |= ((val >> 24) & 0xff); ++ buf[1] |= ((val >> 16) & 0xff); ++ buf[2] |= ((val >> 8) & 0xff); ++ buf[3] |= (val & 0xff); ++ } ++ else ++ { ++ buf[3] |= ((val >> 24) & 0xff); ++ buf[2] |= ((val >> 16) & 0xff); ++ buf[1] |= ((val >> 8) & 0xff); ++ buf[0] |= (val & 0xff); ++ } ++ } ++ } ++ break; ++ ++ case BFD_RELOC_MICROBLAZE_EA64: + /* Don't do anything if the symbol is not defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { + if (target_big_endian) + { +- buf[0] |= ((val >> 24) & 0xff); +- buf[1] |= ((val >> 16) & 0xff); +- buf[2] |= ((val >> 8) & 0xff); +- buf[3] |= (val & 0xff); ++ buf[0] |= ((val >> 56) & 0xff); ++ buf[1] |= ((val >> 48) & 0xff); ++ buf[2] |= ((val >> 40) & 0xff); ++ buf[3] |= ((val >> 32) & 0xff); ++ buf[4] |= ((val >> 24) & 0xff); ++ buf[5] |= ((val >> 16) & 0xff); ++ buf[6] |= ((val >> 8) & 0xff); ++ buf[7] |= (val & 0xff); + } + else + { ++ buf[7] |= ((val >> 56) & 0xff); ++ buf[6] |= ((val >> 48) & 0xff); ++ buf[5] |= ((val >> 40) & 0xff); ++ buf[4] |= ((val >> 32) & 0xff); + buf[3] |= ((val >> 24) & 0xff); + buf[2] |= ((val >> 16) & 0xff); + buf[1] |= ((val >> 8) & 0xff); +@@ -2449,6 +2504,8 @@ md_apply_fix (fixS * fixP, + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; ++ else if(fixP->fx_r_type == BFD_RELOC_MICROBLAZE_EA64) ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_EA64; + else + fixP->fx_r_type = BFD_RELOC_NONE; + fixP->fx_addsy = section_symbol (absolute_section); +@@ -2719,6 +2776,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GPC: ++ case BFD_RELOC_MICROBLAZE_EA64: + case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_PCREL: + case BFD_RELOC_MICROBLAZE_64_GOT: +@@ -3002,10 +3060,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- if (microblaze_arch_size == 64) ++ /*if (microblaze_arch_size == 64) + r = BFD_RELOC_32; +- else +- r = BFD_RELOC_64; ++ else*/ ++ r = BFD_RELOC_MICROBLAZE_EA64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch new file mode 100644 index 00000000..03d8e0b8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch @@ -0,0 +1,110 @@ +From d3fd5a77fa218f8f6c296337758d45cab61483fe Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 2 Nov 2021 17:28:24 +0530 +Subject: [PATCH 26/53] [Patch,MicroBlaze : Adding new relocation to support + 64bit rodata. + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++---- + 1 file changed, 45 insertions(+), 4 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 544732649a5..c9757796ae8 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -1090,6 +1090,13 @@ md_assemble (char * str) + as_fatal (_("smi pseudo instruction should not use a label in imm field")); + if(streq (name, "lli") || streq (name, "sli")) + opc = str_microblaze_64; ++ else if ((microblaze_arch_size == 64) && ((streq (name, "lbui") ++ || streq (name, "lhui") || streq (name, "lwi") || streq (name, "sbi") ++ || streq (name, "shi") || streq (name, "swi")))) ++ { ++ opc = str_microblaze_64; ++ subtype = opcode->inst_offset_type; ++ } + else if (reg2 == REG_ROSDP) + opc = str_microblaze_ro_anchor; + else if (reg2 == REG_RWSDP) +@@ -1157,7 +1164,10 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +- else if (streq (name, "lli") || streq (name, "sli")) ++ else if (streq (name, "lli") || streq (name, "sli") || ((microblaze_arch_size == 64) ++ && ((streq (name, "lbui")) || streq (name, "lhui") ++ || streq (name, "lwi") || streq (name, "sbi") ++ || streq (name, "shi") || streq (name, "swi")))) + { + temp = immed & 0xFFFFFF8000; + if (temp != 0 && temp != 0xFFFFFF8000) +@@ -1773,6 +1783,11 @@ md_assemble (char * str) + + if (exp.X_md != 0) + subtype = get_imm_otype(exp.X_md); ++ else if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) ++ { ++ opc = str_microblaze_64; ++ subtype = opcode->inst_offset_type; ++ } + else + subtype = opcode->inst_offset_type; + +@@ -1790,6 +1805,31 @@ md_assemble (char * str) + output = frag_more (isize); + immed = exp.X_add_number; + } ++ if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFF8000) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { + + temp = immed & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) +@@ -1815,6 +1855,7 @@ md_assemble (char * str) + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_R2: +@@ -3060,10 +3101,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- /*if (microblaze_arch_size == 64) +- r = BFD_RELOC_32; +- else*/ ++ if (microblaze_arch_size == 64) + r = BFD_RELOC_MICROBLAZE_EA64; ++ else ++ r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch new file mode 100644 index 00000000..5a8992df --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0027-Revert-ld-Remove-unused-expression-state-defsym-symb.patch @@ -0,0 +1,84 @@ +From e89c2729322ce147e8a5a5e7842944593b4dd474 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 27 Feb 2019 15:12:32 +0530 +Subject: [PATCH 27/53] Revert "ld: Remove unused expression state" --defsym + symbol=expression Create a global symbol in the output file, containing the + absolute address given by expression. + +This reverts commit 65f14869fd3fbee8ed4c4ca49de8aaa86dbc66cb. + +Conflicts: + ld/ChangeLog + +Conflicts: + ld/ldexp.c + ld/ldexp.h + +Signed-off-by: Aayush Misra +--- + ld/ldexp.c | 8 +++++--- + ld/ldexp.h | 1 + + 2 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/ld/ldexp.c b/ld/ldexp.c +index 3c8ab2d3589..525f3e4262c 100644 +--- a/ld/ldexp.c ++++ b/ld/ldexp.c +@@ -1402,6 +1402,7 @@ static etree_type * + exp_assop (const char *dst, + etree_type *src, + enum node_tree_enum class, ++ bool defsym, + bool hidden) + { + etree_type *n; +@@ -1413,6 +1414,7 @@ exp_assop (const char *dst, + n->assign.type.node_class = class; + n->assign.src = src; + n->assign.dst = dst; ++ n->assign.defsym = defsym; + n->assign.hidden = hidden; + return n; + } +@@ -1422,7 +1424,7 @@ exp_assop (const char *dst, + etree_type * + exp_assign (const char *dst, etree_type *src, bool hidden) + { +- return exp_assop (dst, src, etree_assign, hidden); ++ return exp_assop (dst, src, etree_assign, false, hidden); + } + + /* Handle --defsym command-line option. */ +@@ -1430,7 +1432,7 @@ exp_assign (const char *dst, etree_type *src, bool hidden) + etree_type * + exp_defsym (const char *dst, etree_type *src) + { +- return exp_assop (dst, src, etree_assign, false); ++ return exp_assop (dst, src, etree_assign, true, false); + } + + /* Handle PROVIDE. */ +@@ -1438,7 +1440,7 @@ exp_defsym (const char *dst, etree_type *src) + etree_type * + exp_provide (const char *dst, etree_type *src, bool hidden) + { +- return exp_assop (dst, src, etree_provide, hidden); ++ return exp_assop (dst, src, etree_provide, false, hidden); + } + + /* Handle ASSERT. */ +diff --git a/ld/ldexp.h b/ld/ldexp.h +index c779729e900..6d583e1b15a 100644 +--- a/ld/ldexp.h ++++ b/ld/ldexp.h +@@ -66,6 +66,7 @@ typedef union etree_union { + node_type type; + const char *dst; + union etree_union *src; ++ bool defsym; + bool hidden; + } assign; + struct { +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch new file mode 100644 index 00000000..675ce3ee --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -0,0 +1,58 @@ +From 21eacbba925e2aaceaf3d3400030ae61a1aa4fef Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 29 Nov 2018 17:59:25 +0530 +Subject: [PATCH 28/53] fixing the long & long long mingw toolchain issue + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 10 +++++----- + opcodes/microblaze-opc.h | 4 ++-- + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index c9757796ae8..a8194d175e1 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -754,7 +754,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) + } + + static char * +-parse_imml (char * s, expressionS * e, long min, long max) ++parse_imml (char * s, expressionS * e, long long min, long long max) + { + char *new_pointer; + char *atp; +@@ -805,11 +805,11 @@ parse_imml (char * s, expressionS * e, long min, long max) + ; /* An error message has already been emitted. */ + else if ((e->X_op != O_constant && e->X_op != O_symbol) ) + as_fatal (_("operand must be a constant or a label")); +- else if ((e->X_op == O_constant) && ((long) e->X_add_number < min +- || (long) e->X_add_number > max)) ++ else if ((e->X_op == O_constant) && ((long long) e->X_add_number < min ++ || (long long) e->X_add_number > max)) + { +- as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"), +- min, max, (long) e->X_add_number); ++ as_fatal (_("operand must be absolute in range %lld..%lld, not %lld"), ++ min, max, (long long) e->X_add_number); + } + + if (atp) +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index d9d05721dae..f85f5a600cc 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -592,8 +592,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM6_WIDTH ((int) 0x00000001) + #define MAX_IMM6_WIDTH ((int) 0x00000040) + +-#define MIN_IMML ((long) 0xffffff8000000000L) +-#define MAX_IMML ((long) 0x0000007fffffffffL) ++#define MIN_IMML ((long long) 0xffffff8000000000L) ++#define MAX_IMML ((long long) 0x0000007fffffffffL) + + #endif /* MICROBLAZE_OPC */ + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0029-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0029-Added-support-to-new-arithmetic-single-register-inst.patch new file mode 100644 index 00000000..6199a4e5 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0029-Added-support-to-new-arithmetic-single-register-inst.patch @@ -0,0 +1,371 @@ +From c0cff55375899b12045eef8f5755e68a598ee4ff Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Fri, 23 Aug 2019 16:18:43 +0530 +Subject: [PATCH 29/53] Added support to new arithmetic single register + instructions + +Conflicts: + opcodes/microblaze-dis.c + +Conflicts: + gas/config/tc-microblaze.c + opcodes/microblaze-dis.c + +Conflicts: + gas/config/tc-microblaze.c +signed-off-by:Nagaraju + Mahesh + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++- + opcodes/microblaze-dis.c | 11 +++ + opcodes/microblaze-opc.h | 43 ++++++++++- + opcodes/microblaze-opcm.h | 5 +- + 4 files changed, 200 insertions(+), 6 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index a8194d175e1..3c9aec4c1f9 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -394,12 +394,33 @@ void + md_begin (void) + { + const struct op_code_struct * opcode; ++ const char *prev_name = ""; + + opcode_hash_control = str_htab_create (); + + /* Insert unique names into hash table. */ +- for (opcode = microblaze_opcodes; opcode->name; opcode ++) +- str_hash_insert (opcode_hash_control, opcode->name, opcode, 0); ++ for (opcode = (struct microblaze_opcodes *)microblaze_opcodes; opcode->name; opcode ++) ++ { ++ if (strcmp (prev_name, opcode->name)) ++ { ++ prev_name = (char *) opcode->name; ++ str_hash_insert (opcode_hash_control, opcode->name, opcode, 0); ++ } ++ } ++} ++ ++static int ++is_reg (char * s) ++{ ++ int is_reg = 0; ++ /* Strip leading whitespace. */ ++ while (ISSPACE (* s)) ++ ++ s; ++ if (TOLOWER (s[0]) == 'r') ++ { ++ is_reg =1; ++ } ++ return is_reg; + } + + /* Try to parse a reg name. */ +@@ -957,6 +978,7 @@ md_assemble (char * str) + { + char * op_start; + char * op_end; ++ char * temp_op_end; + struct op_code_struct * opcode, *opcode1; + char * output = NULL; + int nlen = 0; +@@ -967,9 +989,10 @@ md_assemble (char * str) + unsigned reg3; + unsigned isize; + unsigned long immed = 0, immed2 = 0, temp; +- expressionS exp; ++ expressionS exp,exp1; + char name[20]; + long immedl; ++ int reg=0; + + /* Drop leading whitespace. */ + while (ISSPACE (* str)) +@@ -1000,7 +1023,78 @@ md_assemble (char * str) + as_bad (_("unknown opcode \"%s\""), name); + return; + } +- ++ ++ if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") || ++ streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli") ++ || streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc") ++ || streq (name, "andli") || streq (name, "andnli") || streq (name, "orli") ++ || streq (name, "xorli"))) ++ { ++ temp_op_end = op_end; ++ if (strcmp (temp_op_end, "")) ++ temp_op_end = parse_reg (temp_op_end + 1, ®1); /* Get rd. */ ++ if (strcmp (temp_op_end, "")) ++ reg = is_reg (temp_op_end + 1); ++ if (reg) ++ { ++ ++ opcode->inst_type=INST_TYPE_RD_R1_IMML; ++ opcode->inst_offset_type = OPCODE_MASK_H; ++ if (streq (name, "addli")) ++ opcode->bit_sequence = ADDLI_MASK; ++ else if (streq (name, "addlic")) ++ opcode->bit_sequence = ADDLIC_MASK; ++ else if (streq (name, "addlik")) ++ opcode->bit_sequence = ADDLIK_MASK; ++ else if (streq (name, "addlikc")) ++ opcode->bit_sequence = ADDLIKC_MASK; ++ else if (streq (name, "rsubli")) ++ opcode->bit_sequence = RSUBLI_MASK; ++ else if (streq (name, "rsublic")) ++ opcode->bit_sequence = RSUBLIC_MASK; ++ else if (streq (name, "rsublik")) ++ opcode->bit_sequence = RSUBLIK_MASK; ++ else if (streq (name, "rsublikc")) ++ opcode->bit_sequence = RSUBLIKC_MASK; ++ else if (streq (name, "andli")) ++ opcode->bit_sequence = ANDLI_MASK; ++ else if (streq (name, "andnli")) ++ opcode->bit_sequence = ANDLNI_MASK; ++ else if (streq (name, "orli")) ++ opcode->bit_sequence = ORLI_MASK; ++ else if (streq (name, "xorli")) ++ opcode->bit_sequence = XORLI_MASK; ++ } ++ else ++ { ++ opcode->inst_type=INST_TYPE_RD_IMML; ++ opcode->inst_offset_type = OPCODE_MASK_LIMM; ++ if (streq (name, "addli")) ++ opcode->bit_sequence = ADDLI_ONE_REG_MASK; ++ else if (streq (name, "addlic")) ++ opcode->bit_sequence = ADDLIC_ONE_REG_MASK; ++ else if (streq (name, "addlik")) ++ opcode->bit_sequence = ADDLIK_ONE_REG_MASK; ++ else if (streq (name, "addlikc")) ++ opcode->bit_sequence = ADDLIKC_ONE_REG_MASK; ++ else if (streq (name, "rsubli")) ++ opcode->bit_sequence = RSUBLI_ONE_REG_MASK; ++ else if (streq (name, "rsublic")) ++ opcode->bit_sequence = RSUBLIC_ONE_REG_MASK; ++ else if (streq (name, "rsublik")) ++ opcode->bit_sequence = RSUBLIK_ONE_REG_MASK; ++ else if (streq (name, "rsublikc")) ++ opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK; ++ else if (streq (name, "andli")) ++ opcode->bit_sequence = ANDLI_ONE_REG_MASK; ++ else if (streq (name, "andnli")) ++ opcode->bit_sequence = ANDLNI_ONE_REG_MASK; ++ else if (streq (name, "orli")) ++ opcode->bit_sequence = ORLI_ONE_REG_MASK; ++ else if (streq (name, "xorli")) ++ opcode->bit_sequence = XORLI_ONE_REG_MASK; ++ } ++ } + inst = opcode->bit_sequence; + isize = 4; + +@@ -1457,6 +1551,51 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM15_MASK; + break; + ++ case INST_TYPE_RD_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (®1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, ++ isize * 2, ++ subtype, ++ exp.X_add_symbol, ++ exp.X_add_number, ++ (char *) opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immed = exp.X_add_number; ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (immed << IMM_LOW) & IMM16_MASK; ++ break; ++ + case INST_TYPE_R1_RFSL: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 45262aef909..bdc6db79726 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -143,6 +143,14 @@ get_field_imm15 (struct string_buf *buf, long instr) + return p; + } + ++get_field_imm16 (struct string_buf *buf, long instr) ++{ ++ char *p = strbuf (buf); ++ ++ sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW)); ++ return p; ++} ++ + static char * + get_field_special (struct string_buf *buf, long instr, + const struct op_code_struct *op) +@@ -473,6 +481,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + /* For mbar 16 or sleep insn. */ + case INST_TYPE_NONE: + break; ++ case INST_TYPE_RD_IMML: ++ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); ++ break; + /* For bit field insns. */ + case INST_TYPE_RD_R1_IMMW_IMMS: + print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index f85f5a600cc..6228114698b 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -77,6 +77,7 @@ + #define INST_TYPE_RD_R1_IMMW_IMMS 21 + + #define INST_TYPE_NONE 25 ++#define INST_TYPE_RD_IMML 26 + + + +@@ -92,6 +93,7 @@ + #define IMMVAL_MASK_MFS 0x0000 + + #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */ ++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */ + #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */ + #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ + #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ +@@ -114,6 +116,33 @@ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ + #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ + ++/*Defines to identify 64-bit single reg instructions */ ++#define ADDLI_ONE_REG_MASK 0x68000000 ++#define ADDLIC_ONE_REG_MASK 0x68020000 ++#define ADDLIK_ONE_REG_MASK 0x68040000 ++#define ADDLIKC_ONE_REG_MASK 0x68060000 ++#define RSUBLI_ONE_REG_MASK 0x68010000 ++#define RSUBLIC_ONE_REG_MASK 0x68030000 ++#define RSUBLIK_ONE_REG_MASK 0x68050000 ++#define RSUBLIKC_ONE_REG_MASK 0x68070000 ++#define ORLI_ONE_REG_MASK 0x68100000 ++#define ANDLI_ONE_REG_MASK 0x68110000 ++#define XORLI_ONE_REG_MASK 0x68120000 ++#define ANDLNI_ONE_REG_MASK 0x68130000 ++#define ADDLI_MASK 0x20000000 ++#define ADDLIC_MASK 0x28000000 ++#define ADDLIK_MASK 0x30000000 ++#define ADDLIKC_MASK 0x38000000 ++#define RSUBLI_MASK 0x24000000 ++#define RSUBLIC_MASK 0x2C000000 ++#define RSUBLIK_MASK 0x34000000 ++#define RSUBLIKC_MASK 0x3C000000 ++#define ANDLI_MASK 0xA4000000 ++#define ANDLNI_MASK 0xAC000000 ++#define ORLI_MASK 0xA0000000 ++#define XORLI_MASK 0xA8000000 ++ ++ + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ + /* Mask for mbar insn. */ +@@ -122,7 +151,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 412 ++#define MAX_OPCODES 424 + + const struct op_code_struct + { +@@ -451,13 +480,21 @@ const struct op_code_struct + {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, + {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, + {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst }, + {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst }, + {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst }, + {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst }, + {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst }, + {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst }, + {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst }, + {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst }, + {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, + {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, + {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, +@@ -508,9 +545,13 @@ const struct op_code_struct + {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, + {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, + {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst }, + {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst }, + {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst }, + {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst }, + {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, + {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, + {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 08ed44352ee..a57cabf905f 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -62,7 +62,9 @@ enum microblaze_instr + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, + + /* 64-bit instructions */ +- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc, ++ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ andli, andnli, orli, xorli, + bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, + andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, + brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, +@@ -167,5 +169,6 @@ enum microblaze_instr_type + + /* Imm mask for msrset, msrclr instructions. */ + #define IMM15_MASK 0x00007FFF ++#define IMM16_MASK 0x0000FFFF + + #endif /* MICROBLAZE-OPCM */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0030-double-imml-generation-for-64-bit-values.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0030-double-imml-generation-for-64-bit-values.patch new file mode 100644 index 00000000..eb62eaeb --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0030-double-imml-generation-for-64-bit-values.patch @@ -0,0 +1,545 @@ +From e4d7207d18e47a9ce5fbf57fc4faa370bf150284 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 26 Aug 2019 15:29:42 +0530 +Subject: [PATCH 30/53] double imml generation for 64 bit values. + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 321 ++++++++++++++++++++++++++++++------- + opcodes/microblaze-opc.h | 4 +- + 2 files changed, 262 insertions(+), 63 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 3c9aec4c1f9..4da765223be 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -979,7 +979,7 @@ md_assemble (char * str) + char * op_start; + char * op_end; + char * temp_op_end; +- struct op_code_struct * opcode, *opcode1; ++ struct op_code_struct * opcode, *opcode1, *opcode2; + char * output = NULL; + int nlen = 0; + int i; +@@ -1163,7 +1163,12 @@ md_assemble (char * str) + reg2 = 0; + } + if (strcmp (op_end, "")) ++ { ++ if(microblaze_arch_size == 64) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ } + else + as_fatal (_("Error in statement syntax")); + +@@ -1263,26 +1268,51 @@ md_assemble (char * str) + || streq (name, "lwi") || streq (name, "sbi") + || streq (name, "shi") || streq (name, "swi")))) + { +- temp = immed & 0xFFFFFF8000; +- if (temp != 0 && temp != 0xFFFFFF8000) ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000) + { + /* Needs an immediate inst. */ +- opcode1 +- = (struct op_code_struct *) str_hash_find (opcode_hash_control, +- "imml"); +- if (opcode1 == NULL) ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } ++ else ++ { ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; + inst |= (immed << IMM_LOW) & IMM_MASK; +@@ -1299,8 +1329,7 @@ md_assemble (char * str) + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } +- +- inst1 = opcode1->bit_sequence; ++ inst1 = opcode1->bit_sequence; + inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); +@@ -1541,7 +1570,7 @@ md_assemble (char * str) + as_fatal (_("Cannot use special register with this instruction")); + + if (exp.X_op != O_constant) +- as_fatal (_("Symbol used as immediate value for msrset/msrclr instructions")); ++ as_fatal (_("Symbol used as immediate value for arithmetic long instructions")); + else + { + output = frag_more (isize); +@@ -1875,6 +1904,7 @@ md_assemble (char * str) + temp = immed & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { ++ + /* Needs an immediate inst. */ + opcode1 + = (struct op_code_struct *) str_hash_find (opcode_hash_control, +@@ -1907,7 +1937,12 @@ md_assemble (char * str) + reg1 = 0; + } + if (strcmp (op_end, "")) ++ { ++ if(microblaze_arch_size == 64) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else + op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ } + else + as_fatal (_("Error in statement syntax")); + +@@ -1946,30 +1981,55 @@ md_assemble (char * str) + } + if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) + { +- temp = immed & 0xFFFFFF8000; +- if (temp != 0 && temp != 0xFFFFFF8000) ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000) + { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } ++ else { ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (immed << IMM_LOW) & IMM_MASK; + } + else + { +- + temp = immed & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) + { +@@ -2057,24 +2117,50 @@ md_assemble (char * str) + streq (name, "breaid") || + streq (name, "brai") || streq (name, "braid"))) + { +- temp = immed & 0xFFFFFF8000; ++ temp = immed & 0xFFFFFFFFFFFF8000; + if (temp != 0) + { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { + as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); + } ++ else { ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } + inst |= (immed << IMM_LOW) & IMM_MASK; + } + else +@@ -2394,8 +2480,8 @@ md_apply_fix (fixS * fixP, + /* Note: use offsetT because it is signed, valueT is unsigned. */ + offsetT val = (offsetT) * valp; + int i; +- struct op_code_struct * opcode1; +- unsigned long inst1; ++ struct op_code_struct * opcode1, * opcode2; ++ unsigned long inst1,inst2; + + symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _(""); + +@@ -2576,30 +2662,75 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_MICROBLAZE_64_TEXTREL: + case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_PCREL: +- /* Add an imm instruction. First save the current instruction. */ +- for (i = 0; i < INST_WORD_SIZE; i++) +- buf[i + INST_WORD_SIZE] = buf[i]; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64 + || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + { + /* Generate the imm instruction. */ +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887) ++ { ++ /* Add an imm instruction. First save the current instruction. */ ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_64; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ buf[0] = INST_BYTE0 (inst1); ++ buf[1] = INST_BYTE1 (inst1); ++ buf[2] = INST_BYTE2 (inst1); ++ buf[3] = INST_BYTE3 (inst1); ++ } ++ else { ++ /* Add an imm instruction. First save the current instruction. */ ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE + 4] = buf[i]; ++ ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 ==NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 40) & IMML_MASK; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_64; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ inst2 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) +- fixP->fx_r_type = BFD_RELOC_64; ++ fixP->fx_r_type = BFD_RELOC_64; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) +- fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; ++ buf[0] = INST_BYTE0 (inst1); ++ buf[1] = INST_BYTE1 (inst1); ++ buf[2] = INST_BYTE2 (inst1); ++ buf[3] = INST_BYTE3 (inst1); ++ buf[4] = INST_BYTE0 (inst2); ++ buf[5] = INST_BYTE1 (inst2); ++ buf[6] = INST_BYTE2 (inst2); ++ buf[7] = INST_BYTE3 (inst2); ++ } + } + else + { ++ /* Add an imm instruction. First save the current instruction. */ ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; + /* Generate the imm instruction. */ + opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) +@@ -2611,12 +2742,11 @@ md_apply_fix (fixS * fixP, + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; +- } + buf[0] = INST_BYTE0 (inst1); + buf[1] = INST_BYTE1 (inst1); + buf[2] = INST_BYTE2 (inst1); + buf[3] = INST_BYTE3 (inst1); +- ++ } + /* Add the value only if the symbol is defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { +@@ -2649,21 +2779,41 @@ md_apply_fix (fixS * fixP, + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; + /* Generate the imm instruction. */ +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) { ++ if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887) ++ { ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ } ++ else { ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE + 4] = buf[i]; ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ inst2 = opcode2->bit_sequence; ++ ++ /* We can fixup call to a defined non-global address ++ * within the same section only. */ ++ buf[4] = INST_BYTE0 (inst2); ++ buf[5] = INST_BYTE1 (inst2); ++ buf[6] = INST_BYTE2 (inst2); ++ buf[7] = INST_BYTE3 (inst2); ++ } ++ } + else + opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { ++ for (i = 0; i < INST_WORD_SIZE; i++) ++ buf[i + INST_WORD_SIZE] = buf[i]; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) + as_bad (_("unknown opcode \"%s\""), "imml"); + else + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } +- + inst1 = opcode1->bit_sequence; +- + /* We can fixup call to a defined non-global address + within the same section only. */ + buf[0] = INST_BYTE0 (inst1); +@@ -3025,21 +3175,45 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + { + output = frag_more (isize); + immedl = exp.X_add_number; +- +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); ++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode2 == NULL || opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } + } + + inst |= (reg1 << RD_LOW) & RD_MASK; +@@ -3088,20 +3262,45 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + { + output = frag_more (isize); + immedl = exp.X_add_number; +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- ++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); ++ } ++ else { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode2 == NULL || opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } + } + + inst |= (reg1 << RA_LOW) & RA_MASK; +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 6228114698b..f46fc76a94a 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -633,8 +633,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM6_WIDTH ((int) 0x00000001) + #define MAX_IMM6_WIDTH ((int) 0x00000040) + +-#define MIN_IMML ((long long) 0xffffff8000000000L) +-#define MAX_IMML ((long long) 0x0000007fffffffffL) ++#define MIN_IMML ((long long) -9223372036854775808) ++#define MAX_IMML ((long long) 9223372036854775807) + + #endif /* MICROBLAZE_OPC */ + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch new file mode 100644 index 00000000..5bc507ce --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0031-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch @@ -0,0 +1,88 @@ +From 3cd07844b77691afeb675806cc4c73fe08d2c30e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 3 Nov 2021 12:13:32 +0530 +Subject: [PATCH 31/53] Fixed bug in generation of IMML instruction for the + +new MB-64 instructions with single register. + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 50 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 47 insertions(+), 3 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 4da765223be..651d855c800 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -1614,12 +1614,56 @@ md_assemble (char * str) + exp.X_add_symbol, + exp.X_add_number, + (char *) opc); +- immedl = 0L; ++ immed = 0L; + } + else + { + output = frag_more (isize); + immed = exp.X_add_number; ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000) ++ { ++ /* Needs an immediate inst. */ ++ if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL || opcode2 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } + } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (immed << IMM_LOW) & IMM16_MASK; +@@ -2117,8 +2161,8 @@ md_assemble (char * str) + streq (name, "breaid") || + streq (name, "brai") || streq (name, "braid"))) + { +- temp = immed & 0xFFFFFFFFFFFF8000; +- if (temp != 0) ++ temp = ((long long)immed) & 0xFFFFFFFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000) + { + /* Needs an immediate inst. */ + if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887) +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch new file mode 100644 index 00000000..686c8827 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0032-This-patch-will-remove-imml-0-and-imml-1-instruction.patch @@ -0,0 +1,38 @@ +From 6e672cb099ae9670a9be1d26e36fa33df5757191 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 16 Apr 2020 18:08:58 +0530 +Subject: [PATCH 32/53] This patch will remove imml 0 and imml -1 instructions + when the offset is less than 16 bit for Type A branch EA instructions. + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 651d855c800..ce0d3e26204 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -2129,9 +2129,7 @@ md_assemble (char * str) + if (exp.X_op != O_constant) + { + char *opc; +- if (microblaze_arch_size == 64 && (streq (name, "breai") || +- streq (name, "breaid") || +- streq (name, "brai") || streq (name, "braid"))) ++ if (microblaze_arch_size == 64 && (streq (name, "brai") || streq (name, "braid"))) + opc = str_microblaze_64; + else + opc = NULL; +@@ -2707,7 +2705,7 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_PCREL: + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64 +- || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL || (fixP->fx_r_type == BFD_RELOC_64_PCREL && microblaze_arch_size == 64)) + { + /* Generate the imm instruction. */ + if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887) +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch new file mode 100644 index 00000000..1dbeaf0e --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0033-Changing-the-long-to-long-long-as-in-Windows-long-is.patch @@ -0,0 +1,32 @@ +From 0c29905801152c8b8230bcca00b49b945054586b Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 20 Apr 2021 21:22:06 +0530 +Subject: [PATCH 33/53] Changing the long to long long as in Windows long is + 32-bit but we need the variable to be 64-bit + +Signed-off-by :Nagaraju Mekala + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index ce0d3e26204..dc87429a4e8 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -988,7 +988,7 @@ md_assemble (char * str) + unsigned reg2; + unsigned reg3; + unsigned isize; +- unsigned long immed = 0, immed2 = 0, temp; ++ unsigned long long immed = 0, immed2 = 0, temp; + expressionS exp,exp1; + char name[20]; + long immedl; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0034-gas-revert-moving-of-md_pseudo_table-from-const.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0034-gas-revert-moving-of-md_pseudo_table-from-const.patch new file mode 100644 index 00000000..943d3158 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0034-gas-revert-moving-of-md_pseudo_table-from-const.patch @@ -0,0 +1,62 @@ +From ec4fac4177c4364f52d1bc6ba53ffd971323cc22 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 8 Nov 2021 21:57:13 +0530 +Subject: [PATCH 34/53] gas: revert moving of md_pseudo_table from const + +The base system expect md_pseudo_table to be constant, Changing the +definition will break other architectures when compiled with a +unified source code. + +Patch reverts the change away from const, and implements a newer +dynamic handler that passes the correct argument value based on word +size. + +Signed-off-by: Mark Hatle +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 15 ++++++++++++--- + 1 file changed, 12 insertions(+), 3 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index dc87429a4e8..faa458af3a0 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -356,6 +356,17 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED) + demand_empty_rest_of_line (); + } + ++/* Handle the .gpword pseudo-op, Pass to s_rva */ ++ ++static void ++microblaze_s_gpword (int ignore ATTRIBUTE_UNUSED) ++{ ++ int size = 4; ++ if (microblaze_arch_size == 64) ++ size = 8; ++ s_rva(size); ++} ++ + /* This table describes all the machine specific pseudo-ops the assembler + has to support. The fields are: + Pseudo-op name without dot +@@ -371,7 +382,7 @@ const pseudo_typeS md_pseudo_table[] = + {"data32", cons, 4}, /* Same as word. */ + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ +- {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ ++ {"gpword", microblaze_s_gpword, 0}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, +@@ -3425,8 +3436,6 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + case OPTION_M64: + //if (arg != NULL && strcmp (arg, "64") == 0) + microblaze_arch_size = 64; +- // UPSTREAM/REVISIT - md_pseudo_table is const +- // md_pseudo_table[7].poc_val = 8; + break; + default: + return 0; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch new file mode 100644 index 00000000..c3ff9baf --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch @@ -0,0 +1,44 @@ +From 2148cf1617fe1168ea747346d407e2ece94e163a Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 8 Nov 2021 22:01:23 +0530 +Subject: [PATCH 35/53] ld/emulparams/elf64microblaze: Fix emulation generation + +Compilation fails when building ld-new with: + +ldemul.o:(.data.rel+0x820): undefined reference to `ld_elf64microblazeel_emulation' +ldemul.o:(.data.rel+0x828): undefined reference to `ld_elf64microblaze_emulation' + +The error appears to be that the elf64 files were referencing the elf32 emulation. + +Signed-off-by: Mark Hatle +Signed-off-by: Aayush Misra +--- + ld/emulparams/elf64microblaze.sh | 2 +- + ld/emulparams/elf64microblazeel.sh | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh +index 9c7b0eb7080..7b4c7c411bd 100644 +--- a/ld/emulparams/elf64microblaze.sh ++++ b/ld/emulparams/elf64microblaze.sh +@@ -19,5 +19,5 @@ NOP=0x80000000 + #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} + #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' + +-TEMPLATE_NAME=elf32 ++TEMPLATE_NAME=elf + #GENERATE_SHLIB_SCRIPT=yes +diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh +index 9c7b0eb7080..7b4c7c411bd 100644 +--- a/ld/emulparams/elf64microblazeel.sh ++++ b/ld/emulparams/elf64microblazeel.sh +@@ -19,5 +19,5 @@ NOP=0x80000000 + #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} + #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' + +-TEMPLATE_NAME=elf32 ++TEMPLATE_NAME=elf + #GENERATE_SHLIB_SCRIPT=yes +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch new file mode 100644 index 00000000..fd03fc4c --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch @@ -0,0 +1,79 @@ +From 9d691c146a484002e678babb0d40a9387272cb97 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 24 Jan 2022 16:04:07 +0530 +Subject: [PATCH 36/53] Invalid data offsets (pointer) after relaxation. + Proposed patch from community member (dednev@rambler.ru) against 2021.1 + [CR-1115232] + +Signed-off-by: Aayush Misra +--- + bfd/elf32-microblaze.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 7e7c4bf471d..0ba7e36aa5f 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -2176,6 +2176,9 @@ microblaze_elf_relax_section (bfd *abfd, + { + unsigned int val; + ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* hax: We only do the following fixup for debug location lists. */ +@@ -2215,6 +2218,9 @@ microblaze_elf_relax_section (bfd *abfd, + } + if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2247,6 +2253,9 @@ microblaze_elf_relax_section (bfd *abfd, + } + else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2284,6 +2293,9 @@ microblaze_elf_relax_section (bfd *abfd, + || (ELF32_R_TYPE (irelscan->r_info) + == (int) R_MICROBLAZE_TEXTREL_32_LO)) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2330,6 +2342,9 @@ microblaze_elf_relax_section (bfd *abfd, + || (ELF32_R_TYPE (irelscan->r_info) + == (int) R_MICROBLAZE_TEXTREL_64)) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2364,6 +2379,9 @@ microblaze_elf_relax_section (bfd *abfd, + } + else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch new file mode 100644 index 00000000..2e632939 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch @@ -0,0 +1,107 @@ +From 36e578efe3e94a6c13b21c364d818d0a8fd675ca Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 24 Jan 2022 16:59:19 +0530 +Subject: [PATCH 37/53] Double free with ld --no-keep-memory. Proposed patches + from the community member (dednev@rambler.ru) for 2021.1. [CR-1115233] + +Conflicts: + bfd/elf32-microblaze.c + bfd/elf64-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/elf32-microblaze.c | 40 ++++++++++++++++++++++------------------ + 1 file changed, 22 insertions(+), 18 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 0ba7e36aa5f..1ff552a151b 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -1882,10 +1882,8 @@ microblaze_elf_relax_section (bfd *abfd, + { + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *internal_relocs; +- Elf_Internal_Rela *free_relocs = NULL; + Elf_Internal_Rela *irel, *irelend; + bfd_byte *contents = NULL; +- bfd_byte *free_contents = NULL; + int rel_count; + unsigned int shndx; + size_t i, sym_index; +@@ -1929,8 +1927,6 @@ microblaze_elf_relax_section (bfd *abfd, + internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); + if (internal_relocs == NULL) + goto error_return; +- if (! link_info->keep_memory) +- free_relocs = internal_relocs; + + sdata->relax_count = 0; + sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) +@@ -1958,7 +1954,6 @@ microblaze_elf_relax_section (bfd *abfd, + contents = (bfd_byte *) bfd_malloc (sec->size); + if (contents == NULL) + goto error_return; +- free_contents = contents; + + if (!bfd_get_section_contents (abfd, sec, contents, + (file_ptr) 0, sec->size)) +@@ -2475,25 +2470,26 @@ microblaze_elf_relax_section (bfd *abfd, + } + + elf_section_data (sec)->relocs = internal_relocs; +- free_relocs = NULL; + + elf_section_data (sec)->this_hdr.contents = contents; +- free_contents = NULL; + + symtab_hdr->contents = (bfd_byte *) isymbuf; + } + +- free (free_relocs); +- free_relocs = NULL; ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); + +- if (free_contents != NULL) +- { +- if (!link_info->keep_memory) +- free (free_contents); ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ { ++ if (! link_info->keep_memory) ++ free (contents); + else +- /* Cache the section contents for elf_link_input_bfd. */ +- elf_section_data (sec)->this_hdr.contents = contents; +- free_contents = NULL; ++ { ++ /* Cache the section contents for elf_link_input_bfd. */ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } + } + + if (sdata->relax_count == 0) +@@ -2507,8 +2503,16 @@ microblaze_elf_relax_section (bfd *abfd, + return true; + + error_return: +- free (free_relocs); +- free (free_contents); ++ ++ if (isymbuf != NULL ++ && symtab_hdr->contents != (unsigned char *) isymbuf) ++ free (isymbuf); ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ free (contents); + free (sdata->relax); + sdata->relax = NULL; + sdata->relax_count = 0; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0038-MB-binutils-Upstream-port-issues.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0038-MB-binutils-Upstream-port-issues.patch new file mode 100644 index 00000000..cfa1a49e --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0038-MB-binutils-Upstream-port-issues.patch @@ -0,0 +1,99 @@ +From b960fb122b35cb327b9db8fd1bb835899b24d106 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Sun, 28 Nov 2021 17:17:15 +0530 +Subject: [PATCH 38/53] MB binutils Upstream port issues. + +It's resolving the seg faults with ADDLIK +Conflicts: + bfd/elf64-microblaze.c + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 2 +- + opcodes/microblaze-dis.c | 12 ++++++------ + opcodes/microblaze-opc.h | 2 +- + 3 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index faa458af3a0..686b1a00177 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -404,7 +404,7 @@ const pseudo_typeS md_pseudo_table[] = + void + md_begin (void) + { +- const struct op_code_struct * opcode; ++ struct op_code_struct * opcode; + const char *prev_name = ""; + + opcode_hash_control = str_htab_create (); +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index bdc6db79726..d61d6bcfeba 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -153,7 +153,7 @@ get_field_imm16 (struct string_buf *buf, long instr) + + static char * + get_field_special (struct string_buf *buf, long instr, +- const struct op_code_struct *op) ++ struct op_code_struct *op) + { + char *p = strbuf (buf); + char *spr; +@@ -226,11 +226,11 @@ get_field_special (struct string_buf *buf, long instr, + static unsigned long + read_insn_microblaze (bfd_vma memaddr, + struct disassemble_info *info, +- const struct op_code_struct **opr) ++ struct op_code_struct **opr) + { + unsigned char ibytes[4]; + int status; +- const struct op_code_struct *op; ++ struct op_code_struct *op; + unsigned long inst; + + status = info->read_memory_func (memaddr, ibytes, 4, info); +@@ -266,7 +266,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + fprintf_ftype print_func = info->fprintf_func; + void *stream = info->stream; + unsigned long inst, prev_inst; +- const struct op_code_struct *op, *pop; ++ struct op_code_struct *op, *pop; + int immval = 0; + bool immfound = false; + static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */ +@@ -518,7 +518,7 @@ get_insn_microblaze (long inst, + enum microblaze_instr_type *insn_type, + short *delay_slots) + { +- const struct op_code_struct *op; ++ struct op_code_struct *op; + *isunsignedimm = false; + + /* Just a linear search of the table. */ +@@ -560,7 +560,7 @@ microblaze_get_target_address (long inst, bool immfound, int immval, + bool *targetvalid, + bool *unconditionalbranch) + { +- const struct op_code_struct *op; ++ struct op_code_struct *op; + long targetaddr = 0; + + *unconditionalbranch = false; +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index f46fc76a94a..9f6d5456701 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -153,7 +153,7 @@ + + #define MAX_OPCODES 424 + +-const struct op_code_struct ++struct op_code_struct + { + const char * name; + short inst_type; /* Registers and immediate values involved. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-port-of-core-reading-support-Added-support-f.patch new file mode 100644 index 00000000..06fefe2f --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-port-of-core-reading-support-Added-support-f.patch @@ -0,0 +1,89 @@ +From ac87f4a6b9e35083a0403f188b61a317b53cfdbc Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 16:37:53 +0530 +Subject: [PATCH 39/53] Initial port of core reading support Added support for + reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO + information for rebuilding ".reg" sections of core dumps at run time. + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + gdb/microblaze-linux-tdep.c | 11 +++++++++++ + gdb/microblaze-tdep.c | 37 +++++++++++++++++++++++++++++++++++++ + 2 files changed, 48 insertions(+) + +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index f34b0fa9fd4..babc9020f0f 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -193,6 +193,17 @@ microblaze_linux_init_abi (struct gdbarch_info info, + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); + set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); + ++ /* BFD target for core files. */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ ++ ++ /* Shared library handling. */ ++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); ++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); ++ + /* Enable TLS support. */ + set_gdbarch_fetch_tls_load_module_address (gdbarch, + svr4_fetch_objfile_link_map); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index f9cb3dfda33..fdea9721b17 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -957,6 +957,43 @@ make_regs (struct gdbarch *arch) + } + #endif + ++void ++microblaze_supply_gregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *gregs) ++{ ++ const unsigned int *regs = (const unsigned int *)gregs; ++ if (regnum >= 0) ++ regcache->raw_supply (regnum, regs + regnum); ++ ++ if (regnum == -1) { ++ int i; ++ ++ for (i = 0; i < 50; i++) { ++ regcache->raw_supply (i, regs + i); ++ } ++ } ++} ++ ++ ++/* Return the appropriate register set for the core section identified ++ by SECT_NAME and SECT_SIZE. */ ++ ++static void ++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, ++ iterate_over_regset_sections_cb *cb, ++ void *cb_data, ++ const struct regcache *regcache) ++{ ++ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ ++ cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); ++ ++ cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); ++} ++ ++ ++ + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch new file mode 100644 index 00000000..85ae3f02 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch @@ -0,0 +1,185 @@ +From fc4d292d4154cad199cbe1635790867c98a84fc6 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 14 Mar 2024 10:41:33 +0530 +Subject: [PATCH 40/53] Fix build issues after Xilinx 2023.2 binutils merge + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + bfd/bfd-in2.h | 10 ------ + gdb/microblaze-tdep.c | 71 ++++++++++++++-------------------------- + opcodes/microblaze-dis.c | 10 ------ + 3 files changed, 25 insertions(+), 66 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 8b2815d7303..cfab5c99b76 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -6456,11 +6456,6 @@ done here - only used for relaxing */ + * +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_PCREL, + +-/* This is a 64 bit reloc that stores the 32 bit relative +- * +value in two words (with an imml instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64, +- + /* This is a 64 bit reloc that stores the 32 bit relative + * +value in two words (with an imml instruction). No relocation is + * +done here - only used for relaxing */ +@@ -6486,11 +6481,6 @@ value in two words (with an imml instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GPC, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative +-value in two words (with an imml instruction). The relocation is +-PC-relative GOT offset */ +- BFD_RELOC_MICROBLAZE_64_GPC, +- + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + GOT offset */ +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index fdea9721b17..d83e508b82b 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -70,6 +70,7 @@ static const char *microblaze_abi_string; + static const char *const microblaze_abi_strings[] = { + "auto", + "m64", ++ NULL + }; + + enum microblaze_abi +@@ -105,7 +106,7 @@ global_microblaze_abi (void) + if (microblaze_abi_strings[i] == microblaze_abi_string) + return (enum microblaze_abi) i; + +-// internal_error (__FILE__, __LINE__, _("unknown ABI string")); ++ internal_error (__FILE__, __LINE__, _("unknown ABI string")); + } + + static void +@@ -894,16 +895,31 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) + } + + static void +-microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) ++microblaze_register_g_packet_guesses (struct gdbarch *gdbarch, enum microblaze_abi abi) + { + +- register_remote_g_packet_guess (gdbarch, +- 4 * MICROBLAZE_NUM_CORE_REGS, +- tdesc_microblaze64); ++ if (abi == MICROBLAZE_ABI_M64) ++ { ++ ++ register_remote_g_packet_guess (gdbarch, ++ 8 * MICROBLAZE_NUM_CORE_REGS, ++ tdesc_microblaze64); ++ ++ register_remote_g_packet_guess (gdbarch, ++ 8 * MICROBLAZE_NUM_REGS, ++ tdesc_microblaze64_with_stack_protect); ++ } ++ else ++ { ++ ++ register_remote_g_packet_guess (gdbarch, ++ 4 * MICROBLAZE_NUM_CORE_REGS, ++ tdesc_microblaze); + +- register_remote_g_packet_guess (gdbarch, +- 4 * MICROBLAZE_NUM_REGS, +- tdesc_microblaze64_with_stack_protect); ++ register_remote_g_packet_guess (gdbarch, ++ 4 * MICROBLAZE_NUM_REGS, ++ tdesc_microblaze_with_stack_protect); ++ } + } + + void +@@ -957,43 +973,6 @@ make_regs (struct gdbarch *arch) + } + #endif + +-void +-microblaze_supply_gregset (const struct regset *regset, +- struct regcache *regcache, +- int regnum, const void *gregs) +-{ +- const unsigned int *regs = (const unsigned int *)gregs; +- if (regnum >= 0) +- regcache->raw_supply (regnum, regs + regnum); +- +- if (regnum == -1) { +- int i; +- +- for (i = 0; i < 50; i++) { +- regcache->raw_supply (i, regs + i); +- } +- } +-} +- +- +-/* Return the appropriate register set for the core section identified +- by SECT_NAME and SECT_SIZE. */ +- +-static void +-microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, +- iterate_over_regset_sections_cb *cb, +- void *cb_data, +- const struct regcache *regcache) +-{ +- struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); +- +- cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); +- +- cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); +-} +- +- +- + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { +@@ -1134,7 +1113,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); + +- //microblaze_register_g_packet_guesses (gdbarch); ++ // microblaze_register_g_packet_guesses (gdbarch, microblaze_abi); + + frame_base_set_default (gdbarch, µblaze_frame_base); + +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index d61d6bcfeba..692c977ac00 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -466,10 +466,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), + get_field_r2 (&buf, inst)); + break; +- case INST_TYPE_IMML: +- print_func (stream, "\t%s", get_field_imml (&buf, inst)); +- /* TODO: Also print symbol */ +- break; + case INST_TYPE_RD_IMM15: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), + get_field_imm15 (&buf, inst)); +@@ -484,12 +480,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_RD_IMML: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); + break; +- /* For bit field insns. */ +- case INST_TYPE_RD_R1_IMMW_IMMS: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), +- get_field_immw (&buf, inst), get_field_imms (&buf, inst)); +- break; +- /* For bit field insns. */ + case INST_TYPE_RD_R1_IMMW_IMMS: + print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0041-disable-truncated-register-warning-gdb-remote.c.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0041-disable-truncated-register-warning-gdb-remote.c.patch new file mode 100644 index 00000000..5a7e4dc3 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0041-disable-truncated-register-warning-gdb-remote.c.patch @@ -0,0 +1,26 @@ +From 0dc1b1aebeba31dff808a20fcc6444c9acfb99a3 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 14 Mar 2024 15:44:56 +0530 +Subject: [PATCH 41/53] disable truncated register warning (gdb/remote.c) + +Signed-off-by: Aayush Misra +--- + gdb/remote.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gdb/remote.c b/gdb/remote.c +index 72f14e28f54..cb99e5bc7b1 100644 +--- a/gdb/remote.c ++++ b/gdb/remote.c +@@ -8857,7 +8857,7 @@ remote_target::process_g_packet (struct regcache *regcache) + if (rsa->regs[i].pnum == -1) + continue; + +- if (offset >= sizeof_g_packet) ++ if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet)) + rsa->regs[i].in_g_packet = 0; + else if (offset + reg_size > sizeof_g_packet) + error (_("Truncated register %d in remote 'g' packet"), i); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch new file mode 100644 index 00000000..88aefa2f --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch @@ -0,0 +1,42 @@ +From 81f86c3d6f787a9694e1c95625736f7c921b74df Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 10:20:48 +0530 +Subject: [PATCH 42/53] Fix unresolved conflicts from binutils_2_42_merge + +opcodes/microblaze-dis.c + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + opcodes/microblaze-dis.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 692c977ac00..912fa31be79 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -478,11 +478,16 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_NONE: + break; + case INST_TYPE_RD_IMML: +- print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); +- break; +- case INST_TYPE_RD_R1_IMMW_IMMS: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst)); +- break; ++ print_func (stream, "\t%s, %s", ++ get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); ++ break; ++ case INST_TYPE_RD_R1_IMMW_IMMS: ++ print_func (stream, "\t%s, %s, %s, %s", ++ get_field_rd (&buf, inst), ++ get_field_r1(&buf, inst), ++ get_field_immw (&buf, inst), ++ get_field_imms (&buf, inst)); ++ break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (&buf, inst)); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch new file mode 100644 index 00000000..c5fa72d8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch @@ -0,0 +1,177 @@ +From a949ac58b5a3e6cbef03fc431f64052827fc9640 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 10:59:40 +0530 +Subject: [PATCH 43/53] microblaze_gdbarch_init: set microblaze_abi based on + wanted_abi and found_abi + +Earlier found_abi was declared but not set, instead gdbarch_info info +was checked every time. Also, microblaze_abi remained undefined for 32-bit +machines. As a result, gdb would show 64-bit registers when connecting +to 32-bit targets with all register values garbled (r5 ended up in r2). +This defect is fixed. found_abi is set from gdbarch_info, microblaze_abi +is set based on wanted_abi and found_abi. Now upon connecting to a 32-bit +remote target (mb-qemu) registers have the correct 32-bit size. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 73 +++++++++++++++++++------------------------ + 1 file changed, 33 insertions(+), 40 deletions(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index d83e508b82b..6dcdeee76b3 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file, + const char *ignored_value) + { + enum microblaze_abi global_abi = global_microblaze_abi (); +- enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ()); ++ enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ()); + const char *actual_abi_str = microblaze_abi_strings[actual_abi]; + + #if 1 +@@ -203,6 +203,13 @@ microblaze_register_name (struct gdbarch *gdbarch, int regnum) + static struct type * + microblaze_register_type (struct gdbarch *gdbarch, int regnum) + { ++ ++ int mb_reg_size = microblaze_abi_regsize(gdbarch); ++ ++ if (gdbarch_debug) ++ gdb_printf (gdb_stdlog, "microblaze_register_type: reg_size = %d\n", ++ mb_reg_size); ++ + if (regnum == MICROBLAZE_SP_REGNUM) + return builtin_type (gdbarch)->builtin_data_ptr; + +@@ -980,34 +987,38 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + enum microblaze_abi microblaze_abi, found_abi, wanted_abi; + const struct target_desc *tdesc = info.target_desc; + ++ /* If there is already a candidate, use it. */ ++ arches = gdbarch_list_lookup_by_info (arches, &info); ++ if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) ++ return arches->gdbarch; ++ + /* What has the user specified from the command line? */ + wanted_abi = global_microblaze_abi (); + if (gdbarch_debug) + gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", + wanted_abi); ++ ++ found_abi = MICROBLAZE_ABI_AUTO; ++ ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ found_abi = MICROBLAZE_ABI_M64; ++ + if (wanted_abi != MICROBLAZE_ABI_AUTO) + microblaze_abi = wanted_abi; +- +- /* If there is already a candidate, use it. */ +- arches = gdbarch_list_lookup_by_info (arches, &info); +- if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) +- return arches->gdbarch; ++ else ++ microblaze_abi = found_abi; + + if (microblaze_abi == MICROBLAZE_ABI_M64) + { +- tdesc = tdesc_microblaze64; +- reg_size = 8; ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; + } +- if (tdesc == NULL) ++ else + { +- if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) +- { +- tdesc = tdesc_microblaze64; +- reg_size = 8; +- } +- else +- tdesc = tdesc_microblaze; ++ tdesc = tdesc_microblaze; ++ reg_size = 4; + } ++ + /* Check any target description for validity. */ + if (tdesc_has_registers (tdesc)) + { +@@ -1015,7 +1026,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) ++ if (microblaze_abi == MICROBLAZE_ABI_M64) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.core"); + else +@@ -1029,7 +1040,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + for (i = 0; i < MICROBLAZE_NUM_REGS; i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, + microblaze_register_names[i]); +- if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) ++ if (microblaze_abi == MICROBLAZE_ABI_M64) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.stack-protect"); + else +@@ -1075,15 +1086,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + + /* Register set. + make_regs (gdbarch); */ +- switch (info.bfd_arch_info->mach) +- { +- case bfd_mach_microblaze64: +- set_gdbarch_ptr_bit (gdbarch, 64); +- break; +- } +- if(microblaze_abi == MICROBLAZE_ABI_M64) ++ if (microblaze_abi == MICROBLAZE_ABI_M64) + set_gdbarch_ptr_bit (gdbarch, 64); +- ++ else ++ set_gdbarch_ptr_bit (gdbarch, 32); ++ + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); + +@@ -1105,8 +1112,6 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::bp_from_kind); + // set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + +-// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); +- + set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + + set_gdbarch_frame_args_skip (gdbarch, 8); +@@ -1145,9 +1150,6 @@ _initialize_microblaze_tdep () + + gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init); + +-// static struct cmd_list_element *setmicroblazecmdlist = NULL; +-// static struct cmd_list_element *showmicroblazecmdlist = NULL; +- + /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ + + add_setshow_prefix_cmd ("microblaze", no_class, +@@ -1155,15 +1157,6 @@ _initialize_microblaze_tdep () + _("Various microblaze specific commands."), + &setmicroblazecmdlist,&showmicroblazecmdlist, + &setlist,&showlist); +-#if 0 +- add_prefix_cmd ("microblaze", no_class, set_microblaze_command, +- _("Various microblaze specific commands."), +- &setmicroblazecmdlist, "set microblaze ", 0, &setlist); +- +- add_prefix_cmd ("microblaze", no_class, show_microblaze_command, +- _("Various microblaze specific commands."), +- &showmicroblazecmdlist, "show microblaze ", 0, &showlist); +-#endif + + /* Allow the user to override the ABI. */ + add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings, +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch new file mode 100644 index 00000000..a22fdb26 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch @@ -0,0 +1,32 @@ +From 70d94c8a627a91b7a59d99abf5c137f650a687d3 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 11:36:32 +0530 +Subject: [PATCH 44/53] Start bfd_mach_microblaze values from 0 (0,1) instead + of (1,2) + +Before 64-bit support there was only bfd_mach_microblaze (implicitly set to 0), +setting microblaze_mach_microblaze64 to 1 + +Signed-off-by: Aayush Misra +--- + bfd/archures.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/bfd/archures.c b/bfd/archures.c +index b9db26627ea..604e65b7256 100644 +--- a/bfd/archures.c ++++ b/bfd/archures.c +@@ -515,8 +515,8 @@ DESCRIPTION + . bfd_arch_lm32, {* Lattice Mico32. *} + .#define bfd_mach_lm32 1 + . bfd_arch_microblaze,{* Xilinx MicroBlaze. *} +-.#define bfd_mach_microblaze 1 +-.#define bfd_mach_microblaze64 2 ++.#define bfd_mach_microblaze 0 ++.#define bfd_mach_microblaze64 1 + . bfd_arch_kvx, {* Kalray VLIW core of the MPPA processor family *} + .#define bfd_mach_kv3_unknown 0 + .#define bfd_mach_kv3_1 1 +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch new file mode 100644 index 00000000..a9f96637 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch @@ -0,0 +1,61 @@ +From 8fd6902a818f28422bd98b18ff3f0fe9b872e5cf Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 15:37:11 +0530 +Subject: [PATCH 45/53] Fix build issues - bfd/reloc.c add missing relocs used + elsewhere + + BFD_RELOC_MICROBLAZE_EA64 + BFD_RELOC_MICROBLAZE_64_GPC + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + bfd/reloc.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/bfd/reloc.c b/bfd/reloc.c +index b6c9c22a0be..86ca1283582 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6637,13 +6637,19 @@ ENUMDOC + This is a 64 bit reloc that stores 64-bit thread pointer relative offset + to two words (uses imml instruction). + ENUM +-BFD_RELOC_MICROBLAZE_64, ++BFD_RELOC_MICROBLAZE_64 + ENUMDOC + This is a 64 bit reloc that stores the 64 bit pc relative + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing + ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, ++BFD_RELOC_MICROBLAZE_EA64 ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL + ENUMDOC + This is a 32 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). No relocation is +@@ -6686,13 +6692,13 @@ ENUMDOC + two words (with an imm instruction). No relocation is done here - + only used for relaxing. + ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, ++BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative ++ This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing + ENUM +- BFD_RELOC_MICROBLAZE_64_GOTPC ++ BFD_RELOC_MICROBLAZE_64_GPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). No relocation is +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch new file mode 100644 index 00000000..3e6be541 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch @@ -0,0 +1,116 @@ +From 84bb72aa81dddd5f21ac49ddf7b38bce74942cdf Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 15:47:56 +0530 +Subject: [PATCH 46/53] Regenerate - bfd/bfd-in2.h bfd/libbfd.h + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + bfd/bfd-in2.h | 70 +++++++++++++++++++++++++-------------------------- + 1 file changed, 35 insertions(+), 35 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index cfab5c99b76..96949605e50 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -1771,8 +1771,8 @@ enum bfd_architecture + bfd_arch_lm32, /* Lattice Mico32. */ + #define bfd_mach_lm32 1 + bfd_arch_microblaze,/* Xilinx MicroBlaze. */ +-#define bfd_mach_microblaze 1 +-#define bfd_mach_microblaze64 2 ++#define bfd_mach_microblaze 0 ++#define bfd_mach_microblaze64 1 + bfd_arch_kvx, /* Kalray VLIW core of the MPPA processor family */ + #define bfd_mach_kv3_unknown 0 + #define bfd_mach_kv3_1 1 +@@ -6426,8 +6426,23 @@ enum bfd_reloc_code_real + /* Address of a GOT entry. */ + BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT, + +- /* This is a 32 bit reloc for the microblaze that stores the low 16 +- bits of a value. */ ++ /* This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ ++ /* This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_EA64, ++ ++ /* This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_PCREL, ++ ++ /* This is a 32 bit reloc for the microblaze that stores the ++ low 16 bits of a value */ + BFD_RELOC_MICROBLAZE_32_LO, + + /* This is a 32 bit pc-relative reloc for the microblaze that stores +@@ -6446,44 +6461,29 @@ enum bfd_reloc_code_real + the form "Symbol Op Symbol". */ + BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, + +-/* This is a 32 bit reloc that stores the 32 bit pc relative +-value in two words (with an imm instruction). No relocation is +-done here - only used for relaxing */ ++ /* This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). No relocation is ++ done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_32_NONE, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative +- * +value in two words (with an imml instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_PCREL, +- +-/* This is a 64 bit reloc that stores the 32 bit relative +- * +value in two words (with an imml instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_EA64, +- +-/* This is a 64 bit reloc that stores the 32 bit pc relative +- * +value in two words (with an imm instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_NONE, +- +- /* This is a 64 bit reloc that stores the 32 bit pc relative value in +- two words (with an imm instruction). No relocation is done here +- only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64, ++ /* This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_NONE, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative +-value in two words (with an imm instruction). The relocation is +-PC-relative GOT offset */ ++ /* This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). The relocation is ++ PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative +-value in two words (with an imml instruction). The relocation is +-PC-relative GOT offset */ ++ /* This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_GPC, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative +-value in two words (with an imm instruction). The relocation is +-GOT offset */ ++ /* This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). The relocation is ++ GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOT, + + /* This is a 64 bit reloc that stores the 32 bit pc relative value in +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch new file mode 100644 index 00000000..bf82b0ef --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch @@ -0,0 +1,32 @@ +From 8deda21efd527564a262dc07a519f8bd03095b3c Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 16:32:22 +0530 +Subject: [PATCH 47/53] gdb/remote.c - revert earlier change to + process_g_packet + +When connecting to remote target, gdb (microblaze-xilinx-elf) was +generating Truncated register 29 error when parsing the g packet, +workaround added being reverted. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/remote.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gdb/remote.c b/gdb/remote.c +index cb99e5bc7b1..72f14e28f54 100644 +--- a/gdb/remote.c ++++ b/gdb/remote.c +@@ -8857,7 +8857,7 @@ remote_target::process_g_packet (struct regcache *regcache) + if (rsa->regs[i].pnum == -1) + continue; + +- if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet)) ++ if (offset >= sizeof_g_packet) + rsa->regs[i].in_g_packet = 0; + else if (offset + reg_size > sizeof_g_packet) + error (_("Truncated register %d in remote 'g' packet"), i); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch new file mode 100644 index 00000000..6c40a7e4 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch @@ -0,0 +1,465 @@ +From e372266dde792b03fb1754769a9615c818336171 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Mon, 1 Apr 2024 16:21:28 +0530 +Subject: [PATCH 48/53] Fix build issues after Xilinx 2023.2 binutils patch + merge + +binutils/readelf.c - duplicate case statement +gas/config/tc-microblaze.c - Missing , between array elements +gas/config/tc-microblaze.c - A whole hunk ended up in wrong function/switch + +Signed-off-by: Aayush Misra +--- + bfd/libbfd.h | 6 +- + binutils/readelf.c | 5 - + gas/config/tc-microblaze.c | 375 +++++++++++++++++++------------------ + 3 files changed, 192 insertions(+), 194 deletions(-) + +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index 7a3e558d70a..5f78d16db18 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -2998,6 +2998,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21", + "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12", + "BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT", ++ "BFD_RELOC_MICROBLAZE_64", ++ "BFD_RELOC_MICROBLAZE_EA64", ++ "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_32_LO", + "BFD_RELOC_MICROBLAZE_32_LO_PCREL", + "BFD_RELOC_MICROBLAZE_32_ROSDA", +@@ -3006,13 +3009,12 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", + "BFD_RELOC_MICROBLAZE_64_GOTPC", ++ "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", + "BFD_RELOC_MICROBLAZE_32_GOTOFF", + "BFD_RELOC_MICROBLAZE_COPY", +- "BFD_RELOC_MICROBLAZE_64", +- "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_64_TLS", + "BFD_RELOC_MICROBLAZE_64_TLSGD", + "BFD_RELOC_MICROBLAZE_64_TLSLD", +diff --git a/binutils/readelf.c b/binutils/readelf.c +index 3ca9f3697d1..5e4ad6ea6ad 100644 +--- a/binutils/readelf.c ++++ b/binutils/readelf.c +@@ -15288,11 +15288,6 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) + || reloc_type == 9 /* R_MICROBLAZE_64_NONE. */); + default: + return false; +- /* REVISIT microblaze-binutils-merge */ +- case EM_MICROBLAZE: +- return reloc_type == 33 /* R_MICROBLAZE_32_NONE. */ +- || reloc_type == 0 /* R_MICROBLAZE_NONE. */ +- || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */ + } + } + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 686b1a00177..d3d1e334bb5 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -118,7 +118,7 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 15: TLSGOTTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 16: TLSTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ +- { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ ++ { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 18: TEXT_PC_OFFSET. */ + { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }, /* 19: DEFINED_64_OFFSET. */ + { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 } /* 20: DEFINED_64_PC_OFFSET. */ + }; +@@ -2263,6 +2263,193 @@ md_assemble (char * str) + inst |= (immed << IMM_MBAR); + break; + ++ /* For 64-bit instructions */ ++ case INST_TYPE_RD_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg2 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (& reg1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ if (check_spl_reg (& reg2)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ //char *opc = str_microblaze_64; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ (char *) opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode2 == NULL || opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } ++ ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (®1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ //char *opc = NULL; ++ char *opc = str_microblaze_64; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ (char *) opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) ++ { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ else { ++ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); ++ if (opcode2 == NULL || opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode2->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ } ++ ++ inst |= (reg1 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_IMML: ++ as_fatal (_("An IMML instruction should not be present in the .s file")); ++ break; ++ + default: + as_fatal (_("unimplemented opcode \"%s\""), name); + } +@@ -3177,192 +3364,6 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_64_TEXTREL: + code = fixp->fx_r_type; + break; +- /* For 64-bit instructions */ +- case INST_TYPE_RD_R1_IMML: +- if (strcmp (op_end, "")) +- op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ +- else +- { +- as_fatal (_("Error in statement syntax")); +- reg1 = 0; +- } +- if (strcmp (op_end, "")) +- op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ +- else +- { +- as_fatal (_("Error in statement syntax")); +- reg2 = 0; +- } +- if (strcmp (op_end, "")) +- op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); +- else +- as_fatal (_("Error in statement syntax")); +- +- /* Check for spl registers. */ +- if (check_spl_reg (& reg1)) +- as_fatal (_("Cannot use special register with this instruction")); +- if (check_spl_reg (& reg2)) +- as_fatal (_("Cannot use special register with this instruction")); +- +- if (exp.X_op != O_constant) +- { +- char *opc = NULL; +- //char *opc = str_microblaze_64; +- relax_substateT subtype; +- +- if (exp.X_md != 0) +- subtype = get_imm_otype(exp.X_md); +- else +- subtype = opcode->inst_offset_type; +- +- output = frag_var (rs_machine_dependent, +- isize * 2, /* maxm of 2 words. */ +- isize * 2, /* minm of 2 words. */ +- subtype, /* PC-relative or not. */ +- exp.X_add_symbol, +- exp.X_add_number, +- (char *) opc); +- immedl = 0L; +- } +- else +- { +- output = frag_more (isize); +- immedl = exp.X_add_number; +- if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) +- { +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- else { +- opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- if (opcode2 == NULL || opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- inst1 = opcode2->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- } +- +- inst |= (reg1 << RD_LOW) & RD_MASK; +- inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immedl << IMM_LOW) & IMM_MASK; +- break; +- +- case INST_TYPE_R1_IMML: +- if (strcmp (op_end, "")) +- op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ +- else +- { +- as_fatal (_("Error in statement syntax")); +- reg1 = 0; +- } +- if (strcmp (op_end, "")) +- op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); +- else +- as_fatal (_("Error in statement syntax")); +- +- /* Check for spl registers. */ +- if (check_spl_reg (®1)) +- as_fatal (_("Cannot use special register with this instruction")); +- +- if (exp.X_op != O_constant) +- { +- //char *opc = NULL; +- char *opc = str_microblaze_64; +- relax_substateT subtype; +- +- if (exp.X_md != 0) +- subtype = get_imm_otype(exp.X_md); +- else +- subtype = opcode->inst_offset_type; +- +- output = frag_var (rs_machine_dependent, +- isize * 2, /* maxm of 2 words. */ +- isize * 2, /* minm of 2 words. */ +- subtype, /* PC-relative or not. */ +- exp.X_add_symbol, +- exp.X_add_number, +- (char *) opc); +- immedl = 0L; +- } +- else +- { +- output = frag_more (isize); +- immedl = exp.X_add_number; +- if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887) +- { +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- else { +- opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- opcode2 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml"); +- if (opcode2 == NULL || opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- inst1 = opcode2->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- } +- +- inst |= (reg1 << RA_LOW) & RA_MASK; +- inst |= (immedl << IMM_LOW) & IMM_MASK; +- break; +- +- case INST_TYPE_IMML: +- as_fatal (_("An IMML instruction should not be present in the .s file")); +- break; + + default: + switch (F (fixp->fx_size, fixp->fx_pcrel)) +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0049-When-unwinding-pc-value-adjust-return-pc-value.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0049-When-unwinding-pc-value-adjust-return-pc-value.patch new file mode 100644 index 00000000..f7869532 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0049-When-unwinding-pc-value-adjust-return-pc-value.patch @@ -0,0 +1,92 @@ +From 21527b2edc1359417cc7978558167ef9c8c92afd Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Wed, 1 May 2024 11:12:32 +0530 +Subject: [PATCH 49/53] When unwinding pc value, adjust return pc value + +A call (branch and link) instruction can include a delay slot, the +value of pc stored in the link register for Microblaze architecture +is the pc value corresponding to last executed instruction (call) +in the caller. The return instruction (branch reg) includes an +offset of 8 so that when function returns execution continues from +the address at : link register + 8, as the instruction in delay slot +(link register + 4) is already executed at the time of call. + +Handle this by adjusting pc value during unwind-pc. + +Basically restoring code to do this that seems to have been removed +as part of a gdb patch (gdb patch #8, Xilinx Yocto 2023.2) + +That patch caused hundreds of regressions in gdb testuite, including +gdb.base/advance.exp, which is now fixed. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 24 ++++++++++++++++++------ + 1 file changed, 18 insertions(+), 6 deletions(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 6dcdeee76b3..2507cfe540f 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -523,6 +523,12 @@ microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) + { + CORE_ADDR pc; + pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM); ++ /* For sentinel frame, return address is actual PC. For other frames, ++ return address is pc+8. This is a workaround because gcc does not ++ generate correct return address in CIE. */ ++ if (frame_relative_level (next_frame) >= 0) ++ pc = pc + 8; ++ microblaze_debug ("unwind pc = 0x%x\n", (int) pc); + return pc; + } + +@@ -615,6 +621,7 @@ microblaze_frame_prev_register (frame_info_ptr this_frame, + struct microblaze_frame_cache *cache = + microblaze_frame_cache (this_frame, this_cache); + ++#if 1 + if ((regnum == MICROBLAZE_SP_REGNUM && + cache->register_offsets[MICROBLAZE_SP_REGNUM]) + || (regnum == MICROBLAZE_FP_REGNUM && +@@ -625,15 +632,22 @@ if ((regnum == MICROBLAZE_SP_REGNUM && + + if (regnum == MICROBLAZE_PC_REGNUM) + { +- regnum = 15; ++ regnum = MICROBLAZE_PREV_PC_REGNUM; ++ ++ microblaze_debug ("prev pc is r15 @ frame offset 0x%x\n", ++ (int) cache->register_offsets[regnum] ); ++ + return frame_unwind_got_memory (this_frame, regnum, + cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]); +- + } ++ + if (regnum == MICROBLAZE_SP_REGNUM) + regnum = 1; +-#if 0 + ++ return trad_frame_get_prev_register (this_frame, cache->saved_regs, ++ regnum); ++ ++#else + if (cache->frameless_p) + { + if (regnum == MICROBLAZE_PC_REGNUM) +@@ -646,9 +660,7 @@ if (regnum == MICROBLAZE_SP_REGNUM) + else + return trad_frame_get_prev_register (this_frame, cache->saved_regs, + regnum); +-#endif +- return trad_frame_get_prev_register (this_frame, cache->saved_regs, +- regnum); ++#endif + } + + static const struct frame_unwind microblaze_frame_unwind = +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0050-info-reg-pc-does-not-print-symbolic-value.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0050-info-reg-pc-does-not-print-symbolic-value.patch new file mode 100644 index 00000000..c9bca41d --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0050-info-reg-pc-does-not-print-symbolic-value.patch @@ -0,0 +1,116 @@ +From 54a6eedd59d70a80be5dc8b4a5abe642113ea291 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 9 May 2024 11:30:22 +0530 +Subject: [PATCH 50/53] info reg pc does not print symbolic value + +Problem - Test gdb.base/pc-fp.exp fails +Fix - Change feature/microblaze-core.xml add type=code_ptr for pc + +Files changed + features/microblaze-core.xml + features/microblaze.c (generated) + features/microblaze-with-stack-protect.c (generated) + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/features/microblaze-core.xml | 4 ++-- + gdb/features/microblaze-with-stack-protect.c | 10 ++++++---- + gdb/features/microblaze.c | 8 ++++---- + 3 files changed, 12 insertions(+), 10 deletions(-) + +diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml +index 4d77d9d898f..f49d048fc73 100644 +--- a/gdb/features/microblaze-core.xml ++++ b/gdb/features/microblaze-core.xml +@@ -8,7 +8,7 @@ + + + +- ++ + + + +@@ -39,7 +39,7 @@ + + + +- ++ + + + +diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c +index 8ab9565a047..95e3eed1a4e 100644 +--- a/gdb/features/microblaze-with-stack-protect.c ++++ b/gdb/features/microblaze-with-stack-protect.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -70,10 +70,12 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); +- +- feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect"); + tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); + ++ feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect"); ++ tdesc_create_reg (feature, "slr", 59, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "shr", 60, 1, NULL, 32, "int"); ++ + tdesc_microblaze_with_stack_protect = result.release (); + } +diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c +index ed12e5bcfd2..ff4865b2acc 100644 +--- a/gdb/features/microblaze.c ++++ b/gdb/features/microblaze.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); +- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); + + tdesc_microblaze = result.release (); + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0051-Wrong-target-description-accepted-by-microblaze-arch.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0051-Wrong-target-description-accepted-by-microblaze-arch.patch new file mode 100644 index 00000000..65993021 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0051-Wrong-target-description-accepted-by-microblaze-arch.patch @@ -0,0 +1,51 @@ +From 80f3d1ca2ece1ef143f00365b938e0d0b575d239 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 9 May 2024 11:34:04 +0530 +Subject: [PATCH 51/53] Wrong target description accepted by microblaze + architecture + +Fix - Modify microblaze_gdbarch_init, set tdesc only when it is NULL + +Files changed - gdb/microblaze-tdep.c + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 2507cfe540f..cc80e4f0e6b 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -1020,15 +1020,18 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + else + microblaze_abi = found_abi; + +- if (microblaze_abi == MICROBLAZE_ABI_M64) +- { +- tdesc = tdesc_microblaze64; +- reg_size = 8; +- } +- else +- { +- tdesc = tdesc_microblaze; +- reg_size = 4; ++ if (tdesc == NULL) ++ { ++ if (microblaze_abi == MICROBLAZE_ABI_M64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } ++ else ++ { ++ tdesc = tdesc_microblaze; ++ reg_size = 4; ++ } + } + + /* Check any target description for validity. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch new file mode 100644 index 00000000..f358e45e --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0052-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch @@ -0,0 +1,42 @@ +From 2e4370f257fae84d18d1f6ef3a756795d77d5707 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 23 May 2024 16:02:59 +0530 +Subject: [PATCH 52/53] Merge gdb/microblaze-linux-tdep.c to gdb-14 and fix + compilation issues. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-linux-tdep.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index babc9020f0f..00112b8f540 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -48,10 +48,12 @@ microblaze_debug (const char *fmt, ...) + if (microblaze_debug_flag) + { + va_list args; ++ string_file file (gdb_stdout->can_emit_style_escape ()); + + va_start (args, fmt); + printf_unfiltered ("MICROBLAZE LINUX: "); +- vprintf_unfiltered (fmt, args); ++ file.vprintf (fmt, args); ++ gdb_stdout->puts_unfiltered (file.string ().c_str ()); + va_end (args); + } + } +@@ -145,7 +147,7 @@ static void + microblaze_linux_init_abi (struct gdbarch_info info, + struct gdbarch *gdbarch) + { +- struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ struct microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + tdep->sizeof_gregset = 200; + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch new file mode 100644 index 00000000..f7d32927 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0053-Roll-back-an-improvement-which-inlines-target_gdbarc.patch @@ -0,0 +1,29 @@ +From 13146f53b89c03b086e883e1f4bd9e14c32e6943 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Fri, 19 Jul 2024 12:39:24 +0530 +Subject: [PATCH 53/53] Roll back an improvement which inlines target_gdbarch + () inherited from binutils 2.42 merge that causes compilation issues on gdb + 14.2 + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index cc80e4f0e6b..86dedafdbd6 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file, + const char *ignored_value) + { + enum microblaze_abi global_abi = global_microblaze_abi (); +- enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ()); ++ enum microblaze_abi actual_abi = microblaze_abi ( target_gdbarch () ); + const char *actual_abi_str = microblaze_abi_strings[actual_abi]; + + #if 1 +-- +2.34.1 + diff --git a/meta-vitis-tc/conf/machine/microblaze-tc.conf b/meta-vitis-tc/conf/machine/microblaze-tc.conf index 8e9d9500..38e0b01b 100644 --- a/meta-vitis-tc/conf/machine/microblaze-tc.conf +++ b/meta-vitis-tc/conf/machine/microblaze-tc.conf @@ -37,7 +37,7 @@ MULTILIBS += "multilib:libmbbsmfpd" MULTILIBS += "multilib:libmbbspm" MULTILIBS += "multilib:libmbbspfpd" MULTILIBS += "multilib:libmbbspmfpd" -#MULTILIBS += "multilib:libmblem64" +MULTILIBS += "multilib:libmblem64" MULTILIBS += "multilib:libmblebs" MULTILIBS += "multilib:libmblep" MULTILIBS += "multilib:libmblem" @@ -53,21 +53,21 @@ MULTILIBS += "multilib:libmblebsmfpd" MULTILIBS += "multilib:libmblebspm" MULTILIBS += "multilib:libmblebspfpd" MULTILIBS += "multilib:libmblebspmfpd" -#MULTILIBS += "multilib:libmblem64bs" -#MULTILIBS += "multilib:libmblem64p" -#MULTILIBS += "multilib:libmblem64m" -#MULTILIBS += "multilib:libmblem64fpd" -#MULTILIBS += "multilib:libmblem64mfpd" -#MULTILIBS += "multilib:libmblem64pm" -#MULTILIBS += "multilib:libmblem64pfpd" -#MULTILIBS += "multilib:libmblem64pmfpd" -#MULTILIBS += "multilib:libmblem64bsp" -#MULTILIBS += "multilib:libmblem64bsm" -#MULTILIBS += "multilib:libmblem64bsfpd" -#MULTILIBS += "multilib:libmblem64bsmfpd" -#MULTILIBS += "multilib:libmblem64bspm" -#MULTILIBS += "multilib:libmblem64bspfpd" -#MULTILIBS += "multilib:libmblem64bspmfpd" +MULTILIBS += "multilib:libmblem64bs" +MULTILIBS += "multilib:libmblem64p" +MULTILIBS += "multilib:libmblem64m" +MULTILIBS += "multilib:libmblem64fpd" +MULTILIBS += "multilib:libmblem64mfpd" +MULTILIBS += "multilib:libmblem64pm" +MULTILIBS += "multilib:libmblem64pfpd" +MULTILIBS += "multilib:libmblem64pmfpd" +MULTILIBS += "multilib:libmblem64bsp" +MULTILIBS += "multilib:libmblem64bsm" +MULTILIBS += "multilib:libmblem64bsfpd" +MULTILIBS += "multilib:libmblem64bsmfpd" +MULTILIBS += "multilib:libmblem64bspm" +MULTILIBS += "multilib:libmblem64bspfpd" +MULTILIBS += "multilib:libmblem64bspmfpd" # Base configuration -- cgit v1.2.3-54-g00ecf From 990ab65ee197cfdb56029deb056312785d34f0fb Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 23 Jul 2024 15:46:09 -0600 Subject: Revert "gdb: Bring in last OE version of gdb 12.1" This reverts commit 5db2df9a364b9fee7402c0bf0e2eaa2ecd7bee48. Signed-off-by: Mark Hatle --- meta-microblaze/conf/layer.conf | 1 - .../recipes-devtools/gdb/gdb-common.inc | 66 ---------------------- .../gdb/gdb-cross-canadian_12.1.bb | 3 - .../recipes-devtools/gdb/gdb-cross_12.1.bb | 2 - meta-microblaze/recipes-devtools/gdb/gdb.inc | 20 ------- ...0001-make-man-install-relative-to-DESTDIR.patch | 28 --------- ...s-linux-nat-Define-_ABIO32-if-not-defined.patch | 35 ------------ ...Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch | 52 ----------------- ...e-libreadline.a-when-using-disable-static.patch | 50 ---------------- .../gdb/gdb/0005-use-asm-sgidefs.h.patch | 36 ------------ .../gdb/gdb/0006-Change-order-of-CFLAGS.patch | 30 ---------- .../0007-resolve-restrict-keyword-conflict.patch | 48 ---------------- ...nof-using-_Alignof-when-using-C11-or-newe.patch | 55 ------------------ .../gdb/0008-Fix-invalid-sigprocmask-call.patch | 49 ---------------- .../gdb/gdb/0009-gdbserver-ctrl-c-handling.patch | 40 ------------- .../recipes-devtools/gdb/gdb/readline-8.2.patch | 39 ------------- meta-microblaze/recipes-devtools/gdb/gdb_12.1.bb | 39 ------------- 17 files changed, 593 deletions(-) delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb-common.inc delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian_12.1.bb delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb-cross_12.1.bb delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb.inc delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0001-make-man-install-relative-to-DESTDIR.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0002-mips-linux-nat-Define-_ABIO32-if-not-defined.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0003-ppc-ptrace-Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0004-Dont-disable-libreadline.a-when-using-disable-static.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0005-use-asm-sgidefs.h.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0006-Change-order-of-CFLAGS.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0007-resolve-restrict-keyword-conflict.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0008-Define-alignof-using-_Alignof-when-using-C11-or-newe.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-invalid-sigprocmask-call.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0009-gdbserver-ctrl-c-handling.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/readline-8.2.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb_12.1.bb (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/conf/layer.conf b/meta-microblaze/conf/layer.conf index d1443c16..dbb83aed 100644 --- a/meta-microblaze/conf/layer.conf +++ b/meta-microblaze/conf/layer.conf @@ -24,7 +24,6 @@ INHERIT += "rust_microblaze" GCCVERSION:microblaze = "12.2.%" SDKGCCVERSION:microblaze = "13.%" -GDBVERSION:microblaze = "12.1" # canon-prefix-map doesn't exist in gcc 12.x DEBUG_PREFIX_MAP:remove:microblaze = "-fcanon-prefix-map" diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-common.inc b/meta-microblaze/recipes-devtools/gdb/gdb-common.inc deleted file mode 100644 index 925b0c2f..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb-common.inc +++ /dev/null @@ -1,66 +0,0 @@ -SUMMARY = "GNU debugger" -HOMEPAGE = "http://www.gnu.org/software/gdb/" -DESCRIPTION = "GDB, the GNU Project debugger, allows you to see what is going on inside another program while it executes -- or what another program was doing at the moment it crashed." -SECTION = "devel" -DEPENDS = "expat gmp zlib ncurses virtual/libiconv ${LTTNGUST} bison-native" - -LTTNGUST = "lttng-ust" -LTTNGUST:arc = "" -LTTNGUST:aarch64 = "" -LTTNGUST:mipsarch = "" -LTTNGUST:sh4 = "" - -inherit autotools texinfo - -UPSTREAM_CHECK_GITTAGREGEX = "gdb\-(?P.+)\-release" - -B = "${WORKDIR}/build-${TARGET_SYS}" - -EXPAT = "--with-expat --with-libexpat-prefix=${STAGING_DIR_HOST}" - -EXTRA_OECONF = "--disable-gdbtk --disable-x --disable-werror \ - --with-curses --disable-multilib --disable-sim \ - --without-guile \ - ${GDBPROPREFIX} ${EXPAT} \ - ${@bb.utils.contains('DISTRO_FEATURES', 'multiarch', '--enable-64-bit-bfd', '', d)} \ - --disable-rpath \ - --disable-gas --disable-binutils \ - --disable-ld --disable-gold \ - --disable-gprof \ - --with-libgmp-prefix=${STAGING_EXECPREFIXDIR} \ -" - -PACKAGECONFIG ??= "readline ${@bb.utils.filter('DISTRO_FEATURES', 'debuginfod', d)}" -# Use --without-system-readline to compile with readline 5. -PACKAGECONFIG[readline] = "--with-system-readline,--without-system-readline,readline" -PACKAGECONFIG[python] = "--with-python=${WORKDIR}/python,--without-python,python3,python3 python3-codecs" -PACKAGECONFIG[babeltrace] = "--with-babeltrace,--without-babeltrace,babeltrace" -# ncurses is already a hard DEPENDS, but would be added here if it weren't -PACKAGECONFIG[tui] = "--enable-tui,--disable-tui" -PACKAGECONFIG[xz] = "--with-lzma --with-liblzma-prefix=${STAGING_DIR_HOST},--without-lzma,xz" -PACKAGECONFIG[debuginfod] = "--with-debuginfod, --without-debuginfod, elfutils" - -GDBPROPREFIX = "--program-prefix=''" - -DISABLE_STATIC = "" - -do_configure () { - # override this function to avoid the autoconf/automake/aclocal/autoheader - # calls for now - (cd ${S} && gnu-configize) || die "failure in running gnu-configize" - oe_runconf -} - -# we don't want gdb to provide bfd/iberty/opcodes, which instead will override the -# right bits installed by binutils. Same for bfd.info -- also from binutils. -do_install:append() { - rm -rf ${D}${libdir} - rm -rf ${D}${includedir} - rm -rf ${D}${datadir}/locale - rm -f ${D}${infodir}/bfd.info -} - -RRECOMMENDS:gdb:append:linux = " glibc-thread-db " -RRECOMMENDS:gdb:append:linux-gnueabi = " glibc-thread-db " -RRECOMMENDS:gdbserver:append:linux = " glibc-thread-db " -RRECOMMENDS:gdbserver:append:linux-gnueabi = " glibc-thread-db " diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian_12.1.bb b/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian_12.1.bb deleted file mode 100644 index 4ab2b715..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian_12.1.bb +++ /dev/null @@ -1,3 +0,0 @@ -require gdb-common.inc -require gdb-cross-canadian.inc -require gdb.inc diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-cross_12.1.bb b/meta-microblaze/recipes-devtools/gdb/gdb-cross_12.1.bb deleted file mode 100644 index 3b654a2f..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb-cross_12.1.bb +++ /dev/null @@ -1,2 +0,0 @@ -require gdb-cross.inc -require gdb.inc diff --git a/meta-microblaze/recipes-devtools/gdb/gdb.inc b/meta-microblaze/recipes-devtools/gdb/gdb.inc deleted file mode 100644 index a5dc5545..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb.inc +++ /dev/null @@ -1,20 +0,0 @@ -LICENSE = "GPL-2.0-only & GPL-3.0-only & LGPL-2.0-only & LGPL-3.0-only" -LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \ - file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \ - file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \ - file://COPYING.LIB;md5=9f604d8a4f8e74f4f5140845a21b6674" - -SRC_URI = "${GNU_MIRROR}/gdb/gdb-${PV}.tar.xz \ - file://0001-make-man-install-relative-to-DESTDIR.patch \ - file://0002-mips-linux-nat-Define-_ABIO32-if-not-defined.patch \ - file://0003-ppc-ptrace-Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch \ - file://0004-Dont-disable-libreadline.a-when-using-disable-static.patch \ - file://0005-use-asm-sgidefs.h.patch \ - file://0006-Change-order-of-CFLAGS.patch \ - file://0007-resolve-restrict-keyword-conflict.patch \ - file://0008-Fix-invalid-sigprocmask-call.patch \ - file://0009-gdbserver-ctrl-c-handling.patch \ - file://readline-8.2.patch \ - file://0008-Define-alignof-using-_Alignof-when-using-C11-or-newe.patch \ - " -SRC_URI[sha256sum] = "0e1793bf8f2b54d53f46dea84ccfd446f48f81b297b28c4f7fc017b818d69fed" diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0001-make-man-install-relative-to-DESTDIR.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0001-make-man-install-relative-to-DESTDIR.patch deleted file mode 100644 index 16d6cf19..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0001-make-man-install-relative-to-DESTDIR.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 8eca28eddcda4ce8a345ca031f43ff1ed6f37089 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Mon, 2 Mar 2015 02:27:55 +0000 -Subject: [PATCH 1/9] make man install relative to DESTDIR - -Upstream-Status: Pending - -Signed-off-by: Khem Raj ---- - sim/common/Make-common.in | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in -index 74e5dad3049..9e95c224ba4 100644 ---- a/sim/common/Make-common.in -+++ b/sim/common/Make-common.in -@@ -70,7 +70,7 @@ tooldir = $(libdir)/$(target_alias) - datadir = @datadir@ - datarootdir = @datarootdir@ - mandir = @mandir@ --man1dir = $(mandir)/man1 -+man1dir = $(DESTDIR)$(mandir)/man1 - infodir = @infodir@ - includedir = @includedir@ - --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0002-mips-linux-nat-Define-_ABIO32-if-not-defined.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0002-mips-linux-nat-Define-_ABIO32-if-not-defined.patch deleted file mode 100644 index 8d263de8..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0002-mips-linux-nat-Define-_ABIO32-if-not-defined.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 37d3afd2eaa95c89ad7cb5d0079b017752e4d0ea Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Wed, 23 Mar 2016 06:30:09 +0000 -Subject: [PATCH 2/9] mips-linux-nat: Define _ABIO32 if not defined - -This helps building gdb on mips64 on musl, since -musl does not provide sgidefs.h this define is -only defined when GCC is using o32 ABI, in that -case gcc emits it as built-in define and hence -it works ok for mips32 - -Upstream-Status: Pending -Signed-off-by: Khem Raj ---- - gdb/mips-linux-nat.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/gdb/mips-linux-nat.c b/gdb/mips-linux-nat.c -index 20e12b6889e..6adc61235aa 100644 ---- a/gdb/mips-linux-nat.c -+++ b/gdb/mips-linux-nat.c -@@ -41,6 +41,10 @@ - #ifndef PTRACE_GET_THREAD_AREA - #define PTRACE_GET_THREAD_AREA 25 - #endif -+/* musl does not define and relies on compiler built-in macros for it */ -+#ifndef _ABIO32 -+#define _ABIO32 1 -+#endif - - class mips_linux_nat_target final : public linux_nat_trad_target - { --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0003-ppc-ptrace-Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0003-ppc-ptrace-Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch deleted file mode 100644 index 7e09404b..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0003-ppc-ptrace-Define-pt_regs-uapi_pt_regs-on-GLIBC-syst.patch +++ /dev/null @@ -1,52 +0,0 @@ -From e689eec672ee8c53b3adb2ade2b5deb9b7cd99d4 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Sat, 30 Apr 2016 18:32:14 -0700 -Subject: [PATCH 3/9] ppc/ptrace: Define pt_regs uapi_pt_regs on !GLIBC systems - -Upstream-Status: Pending - -Signed-off-by: Khem Raj ---- - gdb/nat/ppc-linux.h | 6 ++++++ - gdbserver/linux-ppc-low.cc | 6 ++++++ - 2 files changed, 12 insertions(+) - -diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h -index 1094f6b0be3..d8588a646c2 100644 ---- a/gdb/nat/ppc-linux.h -+++ b/gdb/nat/ppc-linux.h -@@ -18,7 +18,13 @@ - #ifndef NAT_PPC_LINUX_H - #define NAT_PPC_LINUX_H - -+#if !defined(__GLIBC__) -+# define pt_regs uapi_pt_regs -+#endif - #include -+#if !defined(__GLIBC__) -+# undef pt_regs -+#endif - #include - - /* This sometimes isn't defined. */ -diff --git a/gdbserver/linux-ppc-low.cc b/gdbserver/linux-ppc-low.cc -index 08824887003..69afbae5359 100644 ---- a/gdbserver/linux-ppc-low.cc -+++ b/gdbserver/linux-ppc-low.cc -@@ -23,7 +23,13 @@ - #include "elf/common.h" - #include - #include -+#if !defined(__GLIBC__) -+# define pt_regs uapi_pt_regs -+#endif - #include -+#if !defined(__GLIBC__) -+# undef pt_regs -+#endif - - #include "arch/ppc-linux-common.h" - #include "arch/ppc-linux-tdesc.h" --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Dont-disable-libreadline.a-when-using-disable-static.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0004-Dont-disable-libreadline.a-when-using-disable-static.patch deleted file mode 100644 index a1e85e91..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Dont-disable-libreadline.a-when-using-disable-static.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 15ee6a626242efb8f367be49c13e00d0b72317f0 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Sat, 30 Apr 2016 15:25:03 -0700 -Subject: [PATCH 4/9] Dont disable libreadline.a when using --disable-static - -If gdb is configured with --disable-static then this is dutifully passed to -readline which then disables libreadline.a, which causes a problem when gdb -tries to link against that. - -To ensure that readline always builds static libraries, pass --enable-static to -the sub-configure. - -Upstream-Status: Pending -Signed-off-by: Ross Burton -Signed-off-by: Khem Raj ---- - Makefile.def | 3 ++- - Makefile.in | 2 +- - 2 files changed, 3 insertions(+), 2 deletions(-) - -diff --git a/Makefile.def b/Makefile.def -index acdcd625ed6..78fc31e1199 100644 ---- a/Makefile.def -+++ b/Makefile.def -@@ -120,7 +120,8 @@ host_modules= { module= libiconv; - missing= install-html; - missing= install-info; }; - host_modules= { module= m4; }; --host_modules= { module= readline; }; -+host_modules= { module= readline; -+ extra_configure_flags='--enable-static';}; - host_modules= { module= sid; }; - host_modules= { module= sim; }; - host_modules= { module= texinfo; no_install= true; }; -diff --git a/Makefile.in b/Makefile.in -index 3aacd2daac9..aa58adada4a 100644 ---- a/Makefile.in -+++ b/Makefile.in -@@ -32791,7 +32791,7 @@ configure-readline: - $$s/$$module_srcdir/configure \ - --srcdir=$${topdir}/$$module_srcdir \ - $(HOST_CONFIGARGS) --build=${build_alias} --host=${host_alias} \ -- --target=${target_alias} \ -+ --target=${target_alias} --enable-static \ - || exit 1 - @endif readline - --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0005-use-asm-sgidefs.h.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0005-use-asm-sgidefs.h.patch deleted file mode 100644 index 242099b9..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0005-use-asm-sgidefs.h.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 25a75aaf29791f4302f0e4452f7ebaf735d4f083 Mon Sep 17 00:00:00 2001 -From: Andre McCurdy -Date: Sat, 30 Apr 2016 15:29:06 -0700 -Subject: [PATCH 5/9] use - -Build fix for MIPS with musl libc - -The MIPS specific header is provided by glibc and uclibc -but not by musl. Regardless of the libc, the kernel headers provide - which provides the same definitions, so use that -instead. - -Upstream-Status: Pending - -Signed-off-by: Andre McCurdy -Signed-off-by: Khem Raj ---- - gdb/mips-linux-nat.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gdb/mips-linux-nat.c b/gdb/mips-linux-nat.c -index 6adc61235aa..afb40066744 100644 ---- a/gdb/mips-linux-nat.c -+++ b/gdb/mips-linux-nat.c -@@ -31,7 +31,7 @@ - #include "gdb_proc_service.h" - #include "gregset.h" - --#include -+#include - #include "nat/gdb_ptrace.h" - #include - #include "inf-ptrace.h" --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Change-order-of-CFLAGS.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Change-order-of-CFLAGS.patch deleted file mode 100644 index 58c9b1d0..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Change-order-of-CFLAGS.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c0e7c34134aa1f9644075c596a2338a50d3d923e Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Sat, 30 Apr 2016 15:35:39 -0700 -Subject: [PATCH 6/9] Change order of CFLAGS - -Lets us override Werror if need be - -Upstream-Status: Inappropriate - -Signed-off-by: Khem Raj ---- - gdbserver/Makefile.in | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in -index 47648b8d962..5599779de57 100644 ---- a/gdbserver/Makefile.in -+++ b/gdbserver/Makefile.in -@@ -156,7 +156,7 @@ WIN32APILIBS = @WIN32APILIBS@ - INTERNAL_CFLAGS_BASE = ${GLOBAL_CFLAGS} \ - ${PROFILE_CFLAGS} ${INCLUDE_CFLAGS} ${CPPFLAGS} $(PTHREAD_CFLAGS) - INTERNAL_WARN_CFLAGS = ${INTERNAL_CFLAGS_BASE} $(WARN_CFLAGS) --INTERNAL_CFLAGS = ${INTERNAL_WARN_CFLAGS} $(WERROR_CFLAGS) -DGDBSERVER -+INTERNAL_CFLAGS = ${INTERNAL_WARN_CFLAGS} $(WERROR_CFLAGS) ${COMPILER_CFLAGS} -DGDBSERVER - - # LDFLAGS is specifically reserved for setting from the command line - # when running make. --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0007-resolve-restrict-keyword-conflict.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0007-resolve-restrict-keyword-conflict.patch deleted file mode 100644 index bbd1f0b2..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0007-resolve-restrict-keyword-conflict.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 44fa1ecfbd8a5fe0cfea12a175fa041686842a0c Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Tue, 10 May 2016 08:47:05 -0700 -Subject: [PATCH 7/9] resolve restrict keyword conflict - -GCC detects that we call 'restrict' as param name in function -signatures and complains since both params are called 'restrict' -therefore we use __restrict to denote the C99 keywork - -Upstream-Status: Pending - -Signed-off-by: Khem Raj ---- - gnulib/import/sys_time.in.h | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/gnulib/import/sys_time.in.h b/gnulib/import/sys_time.in.h -index 90a67d18426..664641a1fe8 100644 ---- a/gnulib/import/sys_time.in.h -+++ b/gnulib/import/sys_time.in.h -@@ -93,20 +93,20 @@ struct timeval - # define gettimeofday rpl_gettimeofday - # endif - _GL_FUNCDECL_RPL (gettimeofday, int, -- (struct timeval *restrict, void *restrict) -+ (struct timeval *__restrict, void *__restrict) - _GL_ARG_NONNULL ((1))); - _GL_CXXALIAS_RPL (gettimeofday, int, -- (struct timeval *restrict, void *restrict)); -+ (struct timeval *__restrict, void *__restrict)); - # else - # if !@HAVE_GETTIMEOFDAY@ - _GL_FUNCDECL_SYS (gettimeofday, int, -- (struct timeval *restrict, void *restrict) -+ (struct timeval *__restrict, void *__restrict) - _GL_ARG_NONNULL ((1))); - # endif - /* Need to cast, because on glibc systems, by default, the second argument is - struct timezone *. */ - _GL_CXXALIAS_SYS_CAST (gettimeofday, int, -- (struct timeval *restrict, void *restrict)); -+ (struct timeval *__restrict, void *__restrict)); - # endif - _GL_CXXALIASWARN (gettimeofday); - # if defined __cplusplus && defined GNULIB_NAMESPACE --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Define-alignof-using-_Alignof-when-using-C11-or-newe.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Define-alignof-using-_Alignof-when-using-C11-or-newe.patch deleted file mode 100644 index 3e293276..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Define-alignof-using-_Alignof-when-using-C11-or-newe.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 48906e1038e469b429aa35d0f967730a929c3880 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Sun, 15 Jan 2023 00:16:25 -0800 -Subject: [PATCH 8/8] Define alignof using _Alignof when using C11 or newer - -WG14 N2350 made very clear that it is an UB having type definitions -within "offsetof" [1]. This patch enhances the implementation of macro -alignof_slot to use builtin "_Alignof" to avoid undefined behavior on -when using std=c11 or newer - -clang 16+ has started to flag this [2] - -Fixes build when using -std >= gnu11 and using clang16+ - -Older compilers gcc < 4.9 or clang < 8 has buggy _Alignof even though it -may support C11, exclude those compilers too - -gnulib needs this fix and then it will be applied to downstream packages -like gdb [3] - -[1] https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2350.htm -[2] https://reviews.llvm.org/D133574 -[3] https://public-inbox.org/bug-gnulib/20230114232744.215167-1-raj.khem@gmail.com/T/#u - -Upstream-Status: Backport [https://git.savannah.gnu.org/cgit/gnulib.git/commit/?id=2d404c7dd974cc65f894526f4a1b76bc1dcd8d82] -Signed-off-by: Khem Raj ---- - libiberty/sha1.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/libiberty/sha1.c b/libiberty/sha1.c -index 504f06d3b9b..790ada82443 100644 ---- a/libiberty/sha1.c -+++ b/libiberty/sha1.c -@@ -229,7 +229,17 @@ sha1_process_bytes (const void *buffer, size_t len, struct sha1_ctx *ctx) - if (len >= 64) - { - #if !_STRING_ARCH_unaligned -+/* GCC releases before GCC 4.9 had a bug in _Alignof. See GCC bug 52023 -+ . -+ clang versions < 8.0.0 have the same bug. */ -+#if (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112 \ -+ || (defined __GNUC__ && __GNUC__ < 4 + (__GNUC_MINOR__ < 9) \ -+ && !defined __clang__) \ -+ || (defined __clang__ && __clang_major__ < 8)) - # define alignof(type) offsetof (struct { char c; type x; }, x) -+#else -+# define alignof(type) _Alignof(type) -+#endif - # define UNALIGNED_P(p) (((size_t) p) % alignof (sha1_uint32) != 0) - if (UNALIGNED_P (buffer)) - while (len > 64) --- -2.39.0 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-invalid-sigprocmask-call.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-invalid-sigprocmask-call.patch deleted file mode 100644 index ed1310ce..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-invalid-sigprocmask-call.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 5bdd15553daef7370ca3c1f12d8f14247fdd4907 Mon Sep 17 00:00:00 2001 -From: Yousong Zhou -Date: Fri, 24 Mar 2017 10:36:03 +0800 -Subject: [PATCH 8/9] Fix invalid sigprocmask call -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The POSIX document says - - The pthread_sigmask() and sigprocmask() functions shall fail if: - - [EINVAL] - The value of the how argument is not equal to one of the defined values. - -and this is how musl-libc is currently doing. Fix the call to be safe -and correct - - [1] http://pubs.opengroup.org/onlinepubs/9699919799/functions/pthread_sigmask.html - -gdb/ChangeLog: -2017-03-24 Yousong Zhou - - * common/signals-state-save-restore.c (save_original_signals_state): - Fix invalid sigprocmask call. - -Upstream-Status: Pending [not author, cherry-picked from LEDE https://bugs.lede-project.org/index.php?do=details&task_id=637&openedfrom=-1%2Bweek] -Signed-off-by: André Draszik -Signed-off-by: Khem Raj ---- - gdbsupport/signals-state-save-restore.cc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gdbsupport/signals-state-save-restore.cc b/gdbsupport/signals-state-save-restore.cc -index 92e799d3551..a4a0234272a 100644 ---- a/gdbsupport/signals-state-save-restore.cc -+++ b/gdbsupport/signals-state-save-restore.cc -@@ -38,7 +38,7 @@ save_original_signals_state (bool quiet) - int i; - int res; - -- res = gdb_sigmask (0, NULL, &original_signal_mask); -+ res = gdb_sigmask (SIG_BLOCK, NULL, &original_signal_mask); - if (res == -1) - perror_with_name (("sigprocmask")); - --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdbserver-ctrl-c-handling.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdbserver-ctrl-c-handling.patch deleted file mode 100644 index f53d3bd1..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdbserver-ctrl-c-handling.patch +++ /dev/null @@ -1,40 +0,0 @@ -From bc3b1f6aacf2d8fe66b022fbfcf28cd82c76e52f Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Thu, 29 Nov 2018 18:00:23 -0800 -Subject: [PATCH 9/9] gdbserver ctrl-c handling - -This problem was created by the upstream commit 78708b7c8c -After applying the commit, it will send SIGINT to the process -group(-signal_pid). -But if we use gdbserver send SIGINT, and the attached process is not a -process -group leader, then the "kill (-signal_pid, SIGINT)" returns error and -fails to -interrupt the attached process. - -Upstream-Status: Submitted -[https://sourceware.org/bugzilla/show_bug.cgi?id=18945] - -Author: Josh Gao -Signed-off-by: Zhixiong Chi -Signed-off-by: Khem Raj ---- - gdbserver/linux-low.cc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gdbserver/linux-low.cc b/gdbserver/linux-low.cc -index 7726a4a0c36..f750e074a03 100644 ---- a/gdbserver/linux-low.cc -+++ b/gdbserver/linux-low.cc -@@ -5496,7 +5496,7 @@ linux_process_target::request_interrupt () - { - /* Send a SIGINT to the process group. This acts just like the user - typed a ^C on the controlling terminal. */ -- ::kill (-signal_pid, SIGINT); -+ ::kill (signal_pid, SIGINT); - } - - bool --- -2.36.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/readline-8.2.patch b/meta-microblaze/recipes-devtools/gdb/gdb/readline-8.2.patch deleted file mode 100644 index c2db4c0d..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/readline-8.2.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 1add37b567a7dee39d99f37b37802034c3fce9c4 Mon Sep 17 00:00:00 2001 -From: Andreas Schwab -Date: Sun, 20 Mar 2022 14:01:54 +0100 -Subject: [PATCH] Add support for readline 8.2 - -In readline 8.2 the type of rl_completer_word_break_characters changed to -include const. - -Upstream-Status: Backport [https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=1add37b567a7dee39d99f37b37802034c3fce9c4] -Signed-off-by: Alexander Kanavin ---- - gdb/completer.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gdb/completer.c b/gdb/completer.c -index d3900ae2014..a51c16ac7f8 100644 ---- a/gdb/completer.c -+++ b/gdb/completer.c -@@ -36,7 +36,7 @@ - calling a hook instead so we eliminate the CLI dependency. */ - #include "gdbcmd.h" - --/* Needed for rl_completer_word_break_characters() and for -+/* Needed for rl_completer_word_break_characters and for - rl_filename_completion_function. */ - #include "readline/readline.h" - -@@ -2011,7 +2011,7 @@ gdb_completion_word_break_characters_throw () - rl_basic_quote_characters = NULL; - } - -- return rl_completer_word_break_characters; -+ return (char *) rl_completer_word_break_characters; - } - - char * --- -2.31.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb_12.1.bb b/meta-microblaze/recipes-devtools/gdb/gdb_12.1.bb deleted file mode 100644 index 9c6db4ca..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb_12.1.bb +++ /dev/null @@ -1,39 +0,0 @@ -require gdb-common.inc - -inherit gettext pkgconfig - -#LDFLAGS:append = " -s" -#export CFLAGS:append=" -L${STAGING_LIBDIR}" - -# cross-canadian must not see this -PACKAGES =+ "gdbserver" -FILES:gdbserver = "${bindir}/gdbserver" - -require gdb.inc - -inherit python3-dir - -EXTRA_OEMAKE:append:libc-musl = "\ - gt_cv_func_gnugettext1_libc=yes \ - gt_cv_func_gnugettext2_libc=yes \ - gl_cv_func_working_strerror=yes \ - gl_cv_func_strerror_0_works=yes \ - gl_cv_func_gettimeofday_clobber=no \ - " - -do_configure:prepend() { - if [ "${@bb.utils.filter('PACKAGECONFIG', 'python', d)}" ]; then - cat > ${WORKDIR}/python << EOF -#!/bin/sh -case "\$2" in - --includes) echo "-I${STAGING_INCDIR}/${PYTHON_DIR}${PYTHON_ABI}/" ;; - --ldflags) echo "-Wl,-rpath-link,${STAGING_LIBDIR}/.. -Wl,-rpath,${libdir}/.. -lpthread -ldl -lutil -lm -lpython${PYTHON_BASEVERSION}${PYTHON_ABI}" ;; - --exec-prefix) echo "${exec_prefix}" ;; - *) exit 1 ;; -esac -exit 0 -EOF - chmod +x ${WORKDIR}/python - fi -} - -- cgit v1.2.3-54-g00ecf From d059ba9a0a3c5cc209cfb10d4f81ad4cbc3c5700 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 23 Jul 2024 16:33:38 -0600 Subject: meta-microblaze: gdb: Update to latest version Signed-off-by: Mark Hatle --- .../recipes-devtools/gdb/gdb-microblaze.inc | 55 +- ...-port-of-linux-gdbserver-add-gdb_proc_ser.patch | 42 + .../0001-Add-initial-port-of-linux-gdbserver.patch | 653 --- ...-port-of-linux-gdbserver-add-gdb_proc_ser.patch | 639 +++ ...Blaze-Initial-port-of-core-reading-suppor.patch | 303 - ...ebug-message-when-register-is-unavailable.patch | 50 - ...t-of-core-reading-support-Added-support-f.patch | 301 + ...ebug-message-when-register-is-unavailable.patch | 45 + ...tch-MicroBlaze-MicroBlaze-native-gdb-port.patch | 836 --- .../gdb/gdb/0005-MicroBlaze-native-gdb-port.patch | 834 +++ ...Patch-microblaze-Adding-64-bit-MB-support.patch | 5789 -------------------- ...it-MB-support-Added-new-architecture-to-M.patch | 1891 +++++++ ...Blaze-these-changes-will-make-64-bit-vect.patch | 38 - ...Blaze-Added-m64-abi-for-64-bit-target-des.patch | 300 - ...es-will-make-64-bit-vectors-as-default-ta.patch | 35 + ...bi-for-64-bit-target-descriptions.-set-m6.patch | 4104 ++++++++++++++ .../gdb/gdb/0008-Patch-MicroBlaze.patch | 65 - ...-number-of-inline-functions-refer-inline-.patch | 74 + ...b-gdserver-Fix-ABI-settings-for-gdbserver.patch | 35 - ...build-errors-for-microblaze-xilinx-elf-20.patch | 133 + ...roblaze-xilinx-elf-crash-issue-on-invocat.patch | 28 + ...able-the-warning-message-for-eh_frame_hdr.patch | 35 + ...ange-to-garbage-collection-sweep-causes-m.patch | 43 + .../gdb/0016-Add-new-bit-field-instructions.patch | 88 + ...initial-support-for-MicroBlaze-64-bit-m64.patch | 150 + ...initial-support-for-MicroBlaze-64-bit-m64.patch | 82 + .../gdb/gdb/0021-Added-relocations-for-MB-X.patch | 69 + ...initial-support-for-MicroBlaze-64-bit-m64.patch | 113 + .../gdb/gdb/0023-Added-relocations-for-MB-X.patch | 84 + ...ss-computation-issues-with-64bit-address-.patch | 35 + ...-the-long-long-long-mingw-toolchain-issue.patch | 26 + ...rt-to-new-arithmetic-single-register-inst.patch | 176 + ...-double-imml-generation-for-64-bit-values.patch | 29 + ...ms-elf64microblaze-Fix-emulation-generati.patch | 44 + ...a-offsets-pointer-after-relaxation.-Propo.patch | 79 + ...-with-ld-no-keep-memory.-Proposed-patches.patch | 107 + .../0038-MB-binutils-Upstream-port-issues.patch | 83 + ...t-of-core-reading-support-Added-support-f.patch | 89 + ...issues-after-Xilinx-2023.2-binutils-merge.patch | 185 + ...e-truncated-register-warning-gdb-remote.c.patch | 26 + ...solved-conflicts-from-binutils_2_42_merge.patch | 42 + ...gdbarch_init-set-microblaze_abi-based-on-.patch | 177 + ...ach_microblaze-values-from-0-0-1-instead-.patch | 32 + ...ssues-bfd-reloc.c-add-missing-relocs-used.patch | 61 + ...046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch | 125 + ...c-revert-earlier-change-to-process_g_pack.patch | 32 + ...ssues-after-Xilinx-2023.2-binutils-patch-.patch | 46 + ...MICROBLAZE_NONE-for-linker-relaxation-pro.patch | 27 + ...unwinding-pc-value-adjust-return-pc-value.patch | 92 + ...info-reg-pc-does-not-print-symbolic-value.patch | 116 + ...t-description-accepted-by-microblaze-arch.patch | 51 + ...icroblaze-linux-tdep.c-to-gdb-14-and-fix-.patch | 42 + ...n-improvement-which-inlines-target_gdbarc.patch | 29 + 53 files changed, 10587 insertions(+), 8078 deletions(-) create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0003-Initial-port-of-core-reading-support-Added-support-f.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0004-Fix-debug-message-when-register-is-unavailable.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0005-MicroBlaze-native-gdb-port.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0005-Patch-microblaze-Adding-64-bit-MB-support.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0013-Disable-the-warning-message-for-eh_frame_hdr.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0016-Add-new-bit-field-instructions.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0019-initial-support-for-MicroBlaze-64-bit-m64.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0020-initial-support-for-MicroBlaze-64-bit-m64.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0021-Added-relocations-for-MB-X.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0022-initial-support-for-MicroBlaze-64-bit-m64.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0023-Added-relocations-for-MB-X.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0025-Fixed-address-computation-issues-with-64bit-address-.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0029-Added-support-to-new-arithmetic-single-register-inst.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0030-double-imml-generation-for-64-bit-values.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0038-MB-binutils-Upstream-port-issues.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-port-of-core-reading-support-Added-support-f.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0041-disable-truncated-register-warning-gdb-remote.c.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0050-When-unwinding-pc-value-adjust-return-pc-value.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0051-info-reg-pc-does-not-print-symbolic-value.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0052-Wrong-target-description-accepted-by-microblaze-arch.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc index d3618229..151e7c25 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc +++ b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc @@ -4,14 +4,51 @@ LTTNGUST:microblaze = "" # Add MicroBlaze patches FILESEXTRAPATHS:append := ":${THISDIR}/gdb" +# Our changes are all local, no real patch-status +ERROR_QA:remove = "patch-status" + SRC_URI:append:microblaze = " \ - file://0001-Add-initial-port-of-linux-gdbserver.patch \ - file://0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch \ - file://0003-Fix-debug-message-when-register-is-unavailable.patch \ - file://0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch \ - file://0005-Patch-microblaze-Adding-64-bit-MB-support.patch \ - file://0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch \ - file://0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch \ - file://0008-Patch-MicroBlaze.patch \ - file://0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch \ + file://0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \ + file://0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \ + file://0003-Initial-port-of-core-reading-support-Added-support-f.patch \ + file://0004-Fix-debug-message-when-register-is-unavailable.patch \ + file://0005-MicroBlaze-native-gdb-port.patch \ + file://0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch \ + file://0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch \ + file://0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch \ + file://0009-Depth-Total-number-of-inline-functions-refer-inline-.patch \ + file://0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch \ + file://0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch \ + file://0013-Disable-the-warning-message-for-eh_frame_hdr.patch \ + file://0015-upstream-change-to-garbage-collection-sweep-causes-m.patch \ + file://0016-Add-new-bit-field-instructions.patch \ + file://0019-initial-support-for-MicroBlaze-64-bit-m64.patch \ + file://0020-initial-support-for-MicroBlaze-64-bit-m64.patch \ + file://0021-Added-relocations-for-MB-X.patch \ + file://0022-initial-support-for-MicroBlaze-64-bit-m64.patch \ + file://0023-Added-relocations-for-MB-X.patch \ + file://0025-Fixed-address-computation-issues-with-64bit-address-.patch \ + file://0028-fixing-the-long-long-long-mingw-toolchain-issue.patch \ + file://0029-Added-support-to-new-arithmetic-single-register-inst.patch \ + file://0030-double-imml-generation-for-64-bit-values.patch \ + file://0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch \ + file://0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch \ + file://0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch \ + file://0038-MB-binutils-Upstream-port-issues.patch \ + file://0039-Initial-port-of-core-reading-support-Added-support-f.patch \ + file://0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch \ + file://0041-disable-truncated-register-warning-gdb-remote.c.patch \ + file://0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch \ + file://0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch \ + file://0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch \ + file://0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch \ + file://0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch \ + file://0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch \ + file://0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch \ + file://0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch \ + file://0050-When-unwinding-pc-value-adjust-return-pc-value.patch \ + file://0051-info-reg-pc-does-not-print-symbolic-value.patch \ + file://0052-Wrong-target-description-accepted-by-microblaze-arch.patch \ + file://0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch \ + file://0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch \ " diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch new file mode 100644 index 00000000..bf7b3363 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch @@ -0,0 +1,42 @@ +From fc4e376f932514d9e5e3c04a18952d5900334c09 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 15:07:22 +0530 +Subject: [PATCH 01/54] Add initial port of linux gdbserver add + gdb_proc_service_h to gdbserver microblaze-linux + +gdbserver needs to initialise the microblaze registers + +other archs use this step to run a *_arch_setup() to carry out all +architecture specific setup - may need to add in future + + * add linux-ptrace.o to gdbserver configure + * Update breakpoint opcode + * fix segfault on connecting gdbserver + * add microblaze_linux_memory_remove_breakpoint + * add set_solib_svr4_fetch_link_map_offsets + * add set_gdbarch_fetch_tls_load_module_address + * Force reading of r0 as 0, prevent stores + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + gdbserver/Makefile.in | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in +index b597515d428..faf32cd9d42 100644 +--- a/gdbserver/Makefile.in ++++ b/gdbserver/Makefile.in +@@ -180,6 +180,7 @@ SFILES = \ + $(srcdir)/linux-loongarch-low.cc \ + $(srcdir)/linux-low.cc \ + $(srcdir)/linux-m68k-low.cc \ ++ $(srcdir)/linux-microblaze-low.cc \ + $(srcdir)/linux-mips-low.cc \ + $(srcdir)/linux-nios2-low.cc \ + $(srcdir)/linux-or1k-low.cc \ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch deleted file mode 100644 index 050bdde5..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch +++ /dev/null @@ -1,653 +0,0 @@ -From baac387700a72407b3994bfd0a03825112c9745f Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 10 Oct 2022 15:07:22 +0530 -Subject: [PATCH 1/8] Add initial port of linux gdbserver add - gdb_proc_service_h to gdbserver microblaze-linux - -gdbserver needs to initialise the microblaze registers - -other archs use this step to run a *_arch_setup() to carry out all -architecture specific setup - may need to add in future - - * add linux-ptrace.o to gdbserver configure - * Update breakpoint opcode - * fix segfault on connecting gdbserver - * add microblaze_linux_memory_remove_breakpoint - * add set_solib_svr4_fetch_link_map_offsets - * add set_gdbarch_fetch_tls_load_module_address - * Force reading of r0 as 0, prevent stores - -Upstream-Status: Pending - -Signed-off-by: David Holsgrove -Signed-off-by: Nathan Rossi -Signed-off-by: Mahesh Bodapati ---- - gdb/configure.host | 2 + - gdb/features/Makefile | 1 + - gdb/features/microblaze-linux.xml | 13 ++ - gdb/microblaze-linux-tdep.c | 29 ++- - gdb/microblaze-tdep.c | 35 +++- - gdb/microblaze-tdep.h | 4 +- - gdb/regformats/microblaze-linux.dat | 64 +++++++ - gdb/regformats/reg-microblaze.dat | 41 +++++ - gdbserver/Makefile.in | 1 + - gdbserver/configure.srv | 10 ++ - gdbserver/linux-microblaze-low.cc | 269 ++++++++++++++++++++++++++++ - 11 files changed, 466 insertions(+), 3 deletions(-) - create mode 100644 gdb/features/microblaze-linux.xml - create mode 100644 gdb/regformats/microblaze-linux.dat - create mode 100644 gdb/regformats/reg-microblaze.dat - create mode 100644 gdbserver/linux-microblaze-low.cc - -diff --git a/gdb/configure.host b/gdb/configure.host -index da71675b201..877537d06ef 100644 ---- a/gdb/configure.host -+++ b/gdb/configure.host -@@ -61,6 +61,7 @@ i[34567]86*) gdb_host_cpu=i386 ;; - loongarch*) gdb_host_cpu=loongarch ;; - m68*) gdb_host_cpu=m68k ;; - mips*) gdb_host_cpu=mips ;; -+microblaze*) gdb_host_cpu=microblaze ;; - powerpc* | rs6000) gdb_host_cpu=powerpc ;; - sparcv9 | sparc64) gdb_host_cpu=sparc ;; - s390*) gdb_host_cpu=s390 ;; -@@ -127,6 +128,7 @@ m68*-*-openbsd*) gdb_host=obsd ;; - - m88*-*-openbsd*) gdb_host=obsd ;; - -+microblaze*-*linux*) gdb_host=linux ;; - mips*-*-linux*) gdb_host=linux ;; - mips*-*-netbsdaout* | mips*-*-knetbsd*-gnu) - gdb_host=nbsd ;; -diff --git a/gdb/features/Makefile b/gdb/features/Makefile -index 68e17d0085d..fc3196864c9 100644 ---- a/gdb/features/Makefile -+++ b/gdb/features/Makefile -@@ -46,6 +46,7 @@ - # List of .dat files to create in ../regformats/ - WHICH = mips-linux mips-dsp-linux \ - mips64-linux mips64-dsp-linux \ -+ microblaze-linux \ - nios2-linux \ - or1k-linux \ - rs6000/powerpc-32 \ -diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml -new file mode 100644 -index 00000000000..688a3f83d1e ---- /dev/null -+++ b/gdb/features/microblaze-linux.xml -@@ -0,0 +1,13 @@ -+ -+ -+ -+ -+ -+ microblaze -+ GNU/Linux -+ -+ -diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c -index daa7ddf7e4d..5748556a556 100644 ---- a/gdb/microblaze-linux-tdep.c -+++ b/gdb/microblaze-linux-tdep.c -@@ -37,6 +37,22 @@ - #include "tramp-frame.h" - #include "linux-tdep.h" - -+static int microblaze_debug_flag = 0; -+ -+static void -+microblaze_debug (const char *fmt, ...) -+{ -+ if (microblaze_debug_flag) -+ { -+ va_list args; -+ -+ va_start (args, fmt); -+ printf_unfiltered ("MICROBLAZE LINUX: "); -+ vprintf_unfiltered (fmt, args); -+ va_end (args); -+ } -+} -+ - static int - microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - struct bp_target_info *bp_tgt) -@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - /* Determine appropriate breakpoint contents and size for this address. */ - bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); - -+ /* Make sure we see the memory breakpoints. */ -+ scoped_restore restore_memory -+ = make_scoped_restore_show_memory_breakpoints (1); -+ - val = target_read_memory (addr, old_contents, bplen); - - /* If our breakpoint is no longer at the address, this means that the - program modified the code on us, so it is wrong to put back the - old value. */ - if (val == 0 && memcmp (bp, old_contents, bplen) == 0) -- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); -+ { -+ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); -+ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); -+ } - - return val; - } -@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info, - /* Trampolines. */ - tramp_frame_prepend_unwinder (gdbarch, - µblaze_linux_sighandler_tramp_frame); -+ -+ /* Enable TLS support. */ -+ set_gdbarch_fetch_tls_load_module_address (gdbarch, -+ svr4_fetch_objfile_link_map); - } - - void _initialize_microblaze_linux_tdep (); -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index 3d5dd669341..3e8e8fe35b9 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -128,7 +128,38 @@ microblaze_fetch_instruction (CORE_ADDR pc) - constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; - - typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; -- -+static int -+microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, -+ struct bp_target_info *bp_tgt) -+{ -+ CORE_ADDR addr = bp_tgt->placed_address; -+ const unsigned char *bp; -+ int val; -+ int bplen; -+ gdb_byte old_contents[BREAKPOINT_MAX]; -+ -+ /* Determine appropriate breakpoint contents and size for this address. */ -+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); -+ if (bp == NULL) -+ error (_("Software breakpoints not implemented for this target.")); -+ -+ /* Make sure we see the memory breakpoints. */ -+ scoped_restore restore_memory -+ = make_scoped_restore_show_memory_breakpoints (1); -+ -+ val = target_read_memory (addr, old_contents, bplen); -+ -+ /* If our breakpoint is no longer at the address, this means that the -+ program modified the code on us, so it is wrong to put back the -+ old value. */ -+ if (val == 0 && memcmp (bp, old_contents, bplen) == 0) -+ { -+ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); -+ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); -+ } -+ -+ return val; -+} - - /* Allocate and initialize a frame cache. */ - -@@ -716,6 +747,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - microblaze_breakpoint::kind_from_pc); - set_gdbarch_sw_breakpoint_from_kind (gdbarch, - microblaze_breakpoint::bp_from_kind); -+ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); - - set_gdbarch_frame_args_skip (gdbarch, 8); - -@@ -756,4 +788,5 @@ When non-zero, microblaze specific debugging is enabled."), - NULL, - &setdebuglist, &showdebuglist); - -+ - } -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index 4d90e8785dc..53fcb2297e6 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -118,6 +118,8 @@ struct microblaze_frame_cache - - /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. - Only used for native debugging. */ --#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60} -+#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} -+#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} -+ - - #endif /* microblaze-tdep.h */ -diff --git a/gdb/regformats/microblaze-linux.dat b/gdb/regformats/microblaze-linux.dat -new file mode 100644 -index 00000000000..b5b49f485cd ---- /dev/null -+++ b/gdb/regformats/microblaze-linux.dat -@@ -0,0 +1,64 @@ -+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro: -+# Generated from: microblaze-linux.xml -+name:microblaze_linux -+xmltarget:microblaze-linux.xml -+expedite:r1,rpc -+32:r0 -+32:r1 -+32:r2 -+32:r3 -+32:r4 -+32:r5 -+32:r6 -+32:r7 -+32:r8 -+32:r9 -+32:r10 -+32:r11 -+32:r12 -+32:r13 -+32:r14 -+32:r15 -+32:r16 -+32:r17 -+32:r18 -+32:r19 -+32:r20 -+32:r21 -+32:r22 -+32:r23 -+32:r24 -+32:r25 -+32:r26 -+32:r27 -+32:r28 -+32:r29 -+32:r30 -+32:r31 -+32:rpc -+32:rmsr -+32:rear -+32:resr -+32:rfsr -+32:rbtr -+32:rpvr0 -+32:rpvr1 -+32:rpvr2 -+32:rpvr3 -+32:rpvr4 -+32:rpvr5 -+32:rpvr6 -+32:rpvr7 -+32:rpvr8 -+32:rpvr9 -+32:rpvr10 -+32:rpvr11 -+32:redr -+32:rpid -+32:rzpr -+32:rtlbx -+32:rtlbsx -+32:rtlblo -+32:rtlbhi -+32:slr -+32:shr -diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat -new file mode 100644 -index 00000000000..bd8a4384424 ---- /dev/null -+++ b/gdb/regformats/reg-microblaze.dat -@@ -0,0 +1,41 @@ -+name:microblaze -+expedite:r1,pc -+32:r0 -+32:r1 -+32:r2 -+32:r3 -+32:r4 -+32:r5 -+32:r6 -+32:r7 -+32:r8 -+32:r9 -+32:r10 -+32:r11 -+32:r12 -+32:r13 -+32:r14 -+32:r15 -+32:r16 -+32:r17 -+32:r18 -+32:r19 -+32:r20 -+32:r21 -+32:r22 -+32:r23 -+32:r24 -+32:r25 -+32:r26 -+32:r27 -+32:r28 -+32:r29 -+32:r30 -+32:r31 -+32:pc -+32:msr -+32:ear -+32:esr -+32:fsr -+32:slr -+32:shr -diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in -index 47648b8d962..55a5f5b81ae 100644 ---- a/gdbserver/Makefile.in -+++ b/gdbserver/Makefile.in -@@ -178,6 +178,7 @@ SFILES = \ - $(srcdir)/linux-ia64-low.cc \ - $(srcdir)/linux-low.cc \ - $(srcdir)/linux-m68k-low.cc \ -+ $(srcdir)/linux-microblaze-low.cc \ - $(srcdir)/linux-mips-low.cc \ - $(srcdir)/linux-nios2-low.cc \ - $(srcdir)/linux-or1k-low.cc \ -diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv -index 6e09b0eeb79..1817f1f04fb 100644 ---- a/gdbserver/configure.srv -+++ b/gdbserver/configure.srv -@@ -145,6 +145,16 @@ case "${gdbserver_host}" in - srv_linux_regsets=yes - srv_linux_thread_db=yes - ;; -+ -+microblaze*-*-linux*) srv_regobj="microblaze-linux.o" -+ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o" -+ srv_xmlfiles="microblaze-linux.xml" -+ srv_xmlfiles="${srv_xmlfiles} microblaze-core.xml" -+ srv_linux_usrregs=yes -+ srv_linux_regsets=yes -+ srv_linux_thread_db=yes -+ ;; -+ - mips*-*-linux*) srv_regobj="mips-linux.o" - srv_regobj="${srv_regobj} mips-dsp-linux.o" - srv_regobj="${srv_regobj} mips64-linux.o" -diff --git a/gdbserver/linux-microblaze-low.cc b/gdbserver/linux-microblaze-low.cc -new file mode 100644 -index 00000000000..bf9eecc41ab ---- /dev/null -+++ b/gdbserver/linux-microblaze-low.cc -@@ -0,0 +1,269 @@ -+/* GNU/Linux/Microblaze specific low level interface, for the remote server for -+ GDB. -+ Copyright (C) 1995-2013 Free Software Foundation, Inc. -+ -+ This file is part of GDB. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program. If not, see . */ -+ -+#include "server.h" -+#include "linux-low.h" -+ -+#include "elf/common.h" -+#include "nat/gdb_ptrace.h" -+#include -+ -+#include -+#include -+#include -+ -+#include "gdb_proc_service.h" -+ -+ -+static int microblaze_regmap[] = -+ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3), -+ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7), -+ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11), -+ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15), -+ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19), -+ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23), -+ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27), -+ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31), -+ PT_PC, PT_MSR, PT_EAR, PT_ESR, -+ PT_FSR -+ }; -+ -+ -+ -+class microblaze_target : public linux_process_target -+{ -+public: -+ -+ const regs_info *get_regs_info () override; -+ -+ const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; -+ // CORE_ADDR microblaze_reinsert_addr (regcache *regcache); -+ -+protected: -+ -+ void low_arch_setup () override; -+ -+ bool low_cannot_fetch_register (int regno) override; -+ -+ bool low_cannot_store_register (int regno) override; -+ -+ // bool low_supports_breakpoints () override; -+ -+ CORE_ADDR low_get_pc (regcache *regcache) override; -+ -+ void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; -+ -+ bool low_breakpoint_at (CORE_ADDR pc) override; -+}; -+ -+/* The singleton target ops object. */ -+ -+static microblaze_target the_microblaze_target; -+ -+#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0])) -+ -+/* Defined in auto-generated file microblaze-linux.c. */ -+void init_registers_microblaze_linux (void); -+extern const struct target_desc *tdesc_microblaze_linux; -+ -+bool -+microblaze_target::low_cannot_store_register (int regno) -+{ -+ if (microblaze_regmap[regno] == -1 || regno == 0) -+ return 1; -+ -+ return 0; -+} -+ -+bool -+microblaze_target::low_cannot_fetch_register (int regno) -+{ -+ return 0; -+} -+ -+CORE_ADDR -+microblaze_target::low_get_pc (struct regcache *regcache) -+{ -+ unsigned long pc; -+ -+ collect_register_by_name (regcache, "pc", &pc); -+ return (CORE_ADDR) pc; -+} -+ -+void -+microblaze_target::low_set_pc (struct regcache *regcache, CORE_ADDR pc) -+{ -+ unsigned long newpc = pc; -+ -+ supply_register_by_name (regcache, "pc", &newpc); -+} -+ -+/* dbtrap insn */ -+/* brki r16, 0x18; */ -+static const unsigned long microblaze_breakpoint = 0xba0c0018; -+#define microblaze_breakpoint_len 4 -+ -+/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ -+ -+const gdb_byte * -+microblaze_target::sw_breakpoint_from_kind (int kind, int *size) -+{ -+ *size = microblaze_breakpoint_len; -+ return (const gdb_byte *) µblaze_breakpoint; -+} -+ -+bool -+microblaze_target::low_breakpoint_at (CORE_ADDR where) -+{ -+ unsigned long insn; -+ -+ read_memory (where, (unsigned char *) &insn, 4); -+ if (insn == microblaze_breakpoint) -+ return 1; -+ /* If necessary, recognize more trap instructions here. GDB only uses the -+ one. */ -+ return 0; -+} -+#if 0 -+CORE_ADDR -+microblaze_target::microblaze_reinsert_addr (struct regcache *regcache) -+{ -+ unsigned long pc; -+ collect_register_by_name (regcache, "r15", &pc); -+ return pc; -+} -+#endif -+#if 0 -+#ifdef HAVE_PTRACE_GETREGS -+ -+static void -+microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) -+{ -+ int size = register_size (regcache->tdesc, regno); -+ -+ memset (buf, 0, sizeof (long)); -+ -+ if (size < sizeof (long)) -+ collect_register (regcache, regno, buf + sizeof (long) - size); -+ else -+ collect_register (regcache, regno, buf); -+} -+ -+static void -+microblaze_supply_ptrace_register (struct regcache *regcache, -+ int regno, const char *buf) -+{ -+ int size = register_size (regcache->tdesc, regno); -+ -+ if (regno == 0) { -+ unsigned long regbuf_0 = 0; -+ /* clobbering r0 so that it is always 0 as enforced by hardware */ -+ supply_register (regcache, regno, (const char*)®buf_0); -+ } else { -+ if (size < sizeof (long)) -+ supply_register (regcache, regno, buf + sizeof (long) - size); -+ else -+ supply_register (regcache, regno, buf); -+ } -+} -+ -+/* Provide only a fill function for the general register set. ps_lgetregs -+ will use this for NPTL support. */ -+ -+static void microblaze_fill_gregset (struct regcache *regcache, void *buf) -+{ -+ int i; -+ -+ for (i = 0; i < 32; i++) -+ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]); -+} -+ -+static void -+microblaze_store_gregset (struct regcache *regcache, const void *buf) -+{ -+ int i; -+ -+ for (i = 0; i < 32; i++) -+ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]); -+} -+ -+#endif /* HAVE_PTRACE_GETREGS */ -+#endif -+ -+static struct regset_info microblaze_regsets[] = { -+#if 0 -+#ifdef HAVE_PTRACE_GETREGS -+ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, -+ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, -+#endif /* HAVE_PTRACE_GETREGS */ -+#endif -+ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, -+ NULL_REGSET -+}; -+ -+static struct usrregs_info microblaze_usrregs_info = -+ { -+ microblaze_num_regs, -+ microblaze_regmap, -+ }; -+ -+static struct regsets_info microblaze_regsets_info = -+ { -+ microblaze_regsets, /* regsets */ -+ 0, /* num_regsets */ -+ NULL, /* disabled_regsets */ -+ }; -+ -+static struct regs_info microblaze_regs_info = -+ { -+ NULL, /* regset_bitmap */ -+ µblaze_usrregs_info, -+ µblaze_regsets_info -+ }; -+ -+const regs_info * -+microblaze_target::get_regs_info (void) -+{ -+ return µblaze_regs_info; -+} -+ -+/* Support for hardware single step. */ -+ -+static int -+microblaze_supports_hardware_single_step (void) -+{ -+ return 1; -+} -+ -+ -+void -+microblaze_target::low_arch_setup (void) -+{ -+ current_process ()->tdesc = tdesc_microblaze_linux; -+} -+ -+linux_process_target *the_linux_target = &the_microblaze_target; -+ -+void -+initialize_low_arch (void) -+{ -+ init_registers_microblaze_linux (); -+ initialize_regsets_info (µblaze_regsets_info); -+} -+ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch new file mode 100644 index 00000000..02b42cbd --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch @@ -0,0 +1,639 @@ +From fa91dbd8c23e519760213f32de572cbf98ad6bc3 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 15:07:22 +0530 +Subject: [PATCH 02/54] Add initial port of linux gdbserver add + gdb_proc_service_h to gdbserver microblaze-linux + +gdbserver needs to initialise the microblaze registers + +other archs use this step to run a *_arch_setup() to carry out all +architecture specific setup - may need to add in future + + * add linux-ptrace.o to gdbserver configure + * Update breakpoint opcode + * fix segfault on connecting gdbserver + * add microblaze_linux_memory_remove_breakpoint + * add set_solib_svr4_fetch_link_map_offsets + * add set_gdbarch_fetch_tls_load_module_address + * Force reading of r0 as 0, prevent stores + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + gdb/configure.host | 2 + + gdb/features/Makefile | 1 + + gdb/features/microblaze-linux.xml | 13 ++ + gdb/microblaze-linux-tdep.c | 29 ++- + gdb/microblaze-tdep.c | 35 +++- + gdb/microblaze-tdep.h | 4 +- + gdb/regformats/microblaze-linux.dat | 64 +++++++ + gdb/regformats/reg-microblaze.dat | 41 +++++ + gdbserver/configure.srv | 10 ++ + gdbserver/linux-microblaze-low.cc | 269 ++++++++++++++++++++++++++++ + 10 files changed, 465 insertions(+), 3 deletions(-) + create mode 100644 gdb/features/microblaze-linux.xml + create mode 100644 gdb/regformats/microblaze-linux.dat + create mode 100644 gdb/regformats/reg-microblaze.dat + create mode 100644 gdbserver/linux-microblaze-low.cc + +diff --git a/gdb/configure.host b/gdb/configure.host +index da71675b201..877537d06ef 100644 +--- a/gdb/configure.host ++++ b/gdb/configure.host +@@ -61,6 +61,7 @@ i[34567]86*) gdb_host_cpu=i386 ;; + loongarch*) gdb_host_cpu=loongarch ;; + m68*) gdb_host_cpu=m68k ;; + mips*) gdb_host_cpu=mips ;; ++microblaze*) gdb_host_cpu=microblaze ;; + powerpc* | rs6000) gdb_host_cpu=powerpc ;; + sparcv9 | sparc64) gdb_host_cpu=sparc ;; + s390*) gdb_host_cpu=s390 ;; +@@ -127,6 +128,7 @@ m68*-*-openbsd*) gdb_host=obsd ;; + + m88*-*-openbsd*) gdb_host=obsd ;; + ++microblaze*-*linux*) gdb_host=linux ;; + mips*-*-linux*) gdb_host=linux ;; + mips*-*-netbsdaout* | mips*-*-knetbsd*-gnu) + gdb_host=nbsd ;; +diff --git a/gdb/features/Makefile b/gdb/features/Makefile +index 32341f71815..0af9d67c2f7 100644 +--- a/gdb/features/Makefile ++++ b/gdb/features/Makefile +@@ -46,6 +46,7 @@ + # List of .dat files to create in ../regformats/ + WHICH = mips-linux mips-dsp-linux \ + mips64-linux mips64-dsp-linux \ ++ microblaze-linux \ + nios2-linux \ + or1k-linux \ + rs6000/powerpc-32 \ +diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml +new file mode 100644 +index 00000000000..688a3f83d1e +--- /dev/null ++++ b/gdb/features/microblaze-linux.xml +@@ -0,0 +1,13 @@ ++ ++ ++ ++ ++ ++ microblaze ++ GNU/Linux ++ ++ +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index ae33cb5c014..9160b4ad464 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,6 +37,22 @@ + #include "tramp-frame.h" + #include "linux-tdep.h" + ++static int microblaze_debug_flag = 0; ++ ++static void ++microblaze_debug (const char *fmt, ...) ++{ ++ if (microblaze_debug_flag) ++ { ++ va_list args; ++ ++ va_start (args, fmt); ++ printf_unfiltered ("MICROBLAZE LINUX: "); ++ vprintf_unfiltered (fmt, args); ++ va_end (args); ++ } ++} ++ + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + /* Determine appropriate breakpoint contents and size for this address. */ + bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); + ++ /* Make sure we see the memory breakpoints. */ ++ scoped_restore restore_memory ++ = make_scoped_restore_show_memory_breakpoints (1); ++ + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the + program modified the code on us, so it is wrong to put back the + old value. */ + if (val == 0 && memcmp (bp, old_contents, bplen) == 0) +- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } + + return val; + } +@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info, + /* Trampolines. */ + tramp_frame_prepend_unwinder (gdbarch, + µblaze_linux_sighandler_tramp_frame); ++ ++ /* Enable TLS support. */ ++ set_gdbarch_fetch_tls_load_module_address (gdbarch, ++ svr4_fetch_objfile_link_map); + } + + void _initialize_microblaze_linux_tdep (); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index f254a54305c..28a647e940b 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -128,7 +128,38 @@ microblaze_fetch_instruction (CORE_ADDR pc) + constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; + + typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; +- ++static int ++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, ++ struct bp_target_info *bp_tgt) ++{ ++ CORE_ADDR addr = bp_tgt->placed_address; ++ const unsigned char *bp; ++ int val; ++ int bplen; ++ gdb_byte old_contents[BREAKPOINT_MAX]; ++ ++ /* Determine appropriate breakpoint contents and size for this address. */ ++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); ++ if (bp == NULL) ++ error (_("Software breakpoints not implemented for this target.")); ++ ++ /* Make sure we see the memory breakpoints. */ ++ scoped_restore restore_memory ++ = make_scoped_restore_show_memory_breakpoints (1); ++ ++ val = target_read_memory (addr, old_contents, bplen); ++ ++ /* If our breakpoint is no longer at the address, this means that the ++ program modified the code on us, so it is wrong to put back the ++ old value. */ ++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0) ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } ++ ++ return val; ++} + + /* Allocate and initialize a frame cache. */ + +@@ -714,6 +745,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + microblaze_breakpoint::bp_from_kind); ++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + + set_gdbarch_frame_args_skip (gdbarch, 8); + +@@ -754,4 +786,5 @@ When non-zero, microblaze specific debugging is enabled."), + NULL, + &setdebuglist, &showdebuglist); + ++ + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 892e5b3b849..e9f57e97c26 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -118,6 +118,8 @@ struct microblaze_frame_cache + + /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. + Only used for native debugging. */ +-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60} ++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} ++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} ++ + + #endif /* microblaze-tdep.h */ +diff --git a/gdb/regformats/microblaze-linux.dat b/gdb/regformats/microblaze-linux.dat +new file mode 100644 +index 00000000000..b5b49f485cd +--- /dev/null ++++ b/gdb/regformats/microblaze-linux.dat +@@ -0,0 +1,64 @@ ++# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro: ++# Generated from: microblaze-linux.xml ++name:microblaze_linux ++xmltarget:microblaze-linux.xml ++expedite:r1,rpc ++32:r0 ++32:r1 ++32:r2 ++32:r3 ++32:r4 ++32:r5 ++32:r6 ++32:r7 ++32:r8 ++32:r9 ++32:r10 ++32:r11 ++32:r12 ++32:r13 ++32:r14 ++32:r15 ++32:r16 ++32:r17 ++32:r18 ++32:r19 ++32:r20 ++32:r21 ++32:r22 ++32:r23 ++32:r24 ++32:r25 ++32:r26 ++32:r27 ++32:r28 ++32:r29 ++32:r30 ++32:r31 ++32:rpc ++32:rmsr ++32:rear ++32:resr ++32:rfsr ++32:rbtr ++32:rpvr0 ++32:rpvr1 ++32:rpvr2 ++32:rpvr3 ++32:rpvr4 ++32:rpvr5 ++32:rpvr6 ++32:rpvr7 ++32:rpvr8 ++32:rpvr9 ++32:rpvr10 ++32:rpvr11 ++32:redr ++32:rpid ++32:rzpr ++32:rtlbx ++32:rtlbsx ++32:rtlblo ++32:rtlbhi ++32:slr ++32:shr +diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat +new file mode 100644 +index 00000000000..bd8a4384424 +--- /dev/null ++++ b/gdb/regformats/reg-microblaze.dat +@@ -0,0 +1,41 @@ ++name:microblaze ++expedite:r1,pc ++32:r0 ++32:r1 ++32:r2 ++32:r3 ++32:r4 ++32:r5 ++32:r6 ++32:r7 ++32:r8 ++32:r9 ++32:r10 ++32:r11 ++32:r12 ++32:r13 ++32:r14 ++32:r15 ++32:r16 ++32:r17 ++32:r18 ++32:r19 ++32:r20 ++32:r21 ++32:r22 ++32:r23 ++32:r24 ++32:r25 ++32:r26 ++32:r27 ++32:r28 ++32:r29 ++32:r30 ++32:r31 ++32:pc ++32:msr ++32:ear ++32:esr ++32:fsr ++32:slr ++32:shr +diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv +index 9e861a75088..11ce617e72f 100644 +--- a/gdbserver/configure.srv ++++ b/gdbserver/configure.srv +@@ -159,6 +159,16 @@ case "${gdbserver_host}" in + srv_linux_regsets=yes + srv_linux_thread_db=yes + ;; ++ ++microblaze*-*-linux*) srv_regobj="microblaze-linux.o" ++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o" ++ srv_xmlfiles="microblaze-linux.xml" ++ srv_xmlfiles="${srv_xmlfiles} microblaze-core.xml" ++ srv_linux_usrregs=yes ++ srv_linux_regsets=yes ++ srv_linux_thread_db=yes ++ ;; ++ + mips*-*-linux*) srv_regobj="mips-linux.o" + srv_regobj="${srv_regobj} mips-dsp-linux.o" + srv_regobj="${srv_regobj} mips64-linux.o" +diff --git a/gdbserver/linux-microblaze-low.cc b/gdbserver/linux-microblaze-low.cc +new file mode 100644 +index 00000000000..bf9eecc41ab +--- /dev/null ++++ b/gdbserver/linux-microblaze-low.cc +@@ -0,0 +1,269 @@ ++/* GNU/Linux/Microblaze specific low level interface, for the remote server for ++ GDB. ++ Copyright (C) 1995-2013 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include "server.h" ++#include "linux-low.h" ++ ++#include "elf/common.h" ++#include "nat/gdb_ptrace.h" ++#include ++ ++#include ++#include ++#include ++ ++#include "gdb_proc_service.h" ++ ++ ++static int microblaze_regmap[] = ++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3), ++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7), ++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11), ++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15), ++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19), ++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23), ++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27), ++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31), ++ PT_PC, PT_MSR, PT_EAR, PT_ESR, ++ PT_FSR ++ }; ++ ++ ++ ++class microblaze_target : public linux_process_target ++{ ++public: ++ ++ const regs_info *get_regs_info () override; ++ ++ const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; ++ // CORE_ADDR microblaze_reinsert_addr (regcache *regcache); ++ ++protected: ++ ++ void low_arch_setup () override; ++ ++ bool low_cannot_fetch_register (int regno) override; ++ ++ bool low_cannot_store_register (int regno) override; ++ ++ // bool low_supports_breakpoints () override; ++ ++ CORE_ADDR low_get_pc (regcache *regcache) override; ++ ++ void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; ++ ++ bool low_breakpoint_at (CORE_ADDR pc) override; ++}; ++ ++/* The singleton target ops object. */ ++ ++static microblaze_target the_microblaze_target; ++ ++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0])) ++ ++/* Defined in auto-generated file microblaze-linux.c. */ ++void init_registers_microblaze_linux (void); ++extern const struct target_desc *tdesc_microblaze_linux; ++ ++bool ++microblaze_target::low_cannot_store_register (int regno) ++{ ++ if (microblaze_regmap[regno] == -1 || regno == 0) ++ return 1; ++ ++ return 0; ++} ++ ++bool ++microblaze_target::low_cannot_fetch_register (int regno) ++{ ++ return 0; ++} ++ ++CORE_ADDR ++microblaze_target::low_get_pc (struct regcache *regcache) ++{ ++ unsigned long pc; ++ ++ collect_register_by_name (regcache, "pc", &pc); ++ return (CORE_ADDR) pc; ++} ++ ++void ++microblaze_target::low_set_pc (struct regcache *regcache, CORE_ADDR pc) ++{ ++ unsigned long newpc = pc; ++ ++ supply_register_by_name (regcache, "pc", &newpc); ++} ++ ++/* dbtrap insn */ ++/* brki r16, 0x18; */ ++static const unsigned long microblaze_breakpoint = 0xba0c0018; ++#define microblaze_breakpoint_len 4 ++ ++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ ++ ++const gdb_byte * ++microblaze_target::sw_breakpoint_from_kind (int kind, int *size) ++{ ++ *size = microblaze_breakpoint_len; ++ return (const gdb_byte *) µblaze_breakpoint; ++} ++ ++bool ++microblaze_target::low_breakpoint_at (CORE_ADDR where) ++{ ++ unsigned long insn; ++ ++ read_memory (where, (unsigned char *) &insn, 4); ++ if (insn == microblaze_breakpoint) ++ return 1; ++ /* If necessary, recognize more trap instructions here. GDB only uses the ++ one. */ ++ return 0; ++} ++#if 0 ++CORE_ADDR ++microblaze_target::microblaze_reinsert_addr (struct regcache *regcache) ++{ ++ unsigned long pc; ++ collect_register_by_name (regcache, "r15", &pc); ++ return pc; ++} ++#endif ++#if 0 ++#ifdef HAVE_PTRACE_GETREGS ++ ++static void ++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) ++{ ++ int size = register_size (regcache->tdesc, regno); ++ ++ memset (buf, 0, sizeof (long)); ++ ++ if (size < sizeof (long)) ++ collect_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ collect_register (regcache, regno, buf); ++} ++ ++static void ++microblaze_supply_ptrace_register (struct regcache *regcache, ++ int regno, const char *buf) ++{ ++ int size = register_size (regcache->tdesc, regno); ++ ++ if (regno == 0) { ++ unsigned long regbuf_0 = 0; ++ /* clobbering r0 so that it is always 0 as enforced by hardware */ ++ supply_register (regcache, regno, (const char*)®buf_0); ++ } else { ++ if (size < sizeof (long)) ++ supply_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ supply_register (regcache, regno, buf); ++ } ++} ++ ++/* Provide only a fill function for the general register set. ps_lgetregs ++ will use this for NPTL support. */ ++ ++static void microblaze_fill_gregset (struct regcache *regcache, void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++static void ++microblaze_store_gregset (struct regcache *regcache, const void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++#endif /* HAVE_PTRACE_GETREGS */ ++#endif ++ ++static struct regset_info microblaze_regsets[] = { ++#if 0 ++#ifdef HAVE_PTRACE_GETREGS ++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, ++#endif /* HAVE_PTRACE_GETREGS */ ++#endif ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, ++ NULL_REGSET ++}; ++ ++static struct usrregs_info microblaze_usrregs_info = ++ { ++ microblaze_num_regs, ++ microblaze_regmap, ++ }; ++ ++static struct regsets_info microblaze_regsets_info = ++ { ++ microblaze_regsets, /* regsets */ ++ 0, /* num_regsets */ ++ NULL, /* disabled_regsets */ ++ }; ++ ++static struct regs_info microblaze_regs_info = ++ { ++ NULL, /* regset_bitmap */ ++ µblaze_usrregs_info, ++ µblaze_regsets_info ++ }; ++ ++const regs_info * ++microblaze_target::get_regs_info (void) ++{ ++ return µblaze_regs_info; ++} ++ ++/* Support for hardware single step. */ ++ ++static int ++microblaze_supports_hardware_single_step (void) ++{ ++ return 1; ++} ++ ++ ++void ++microblaze_target::low_arch_setup (void) ++{ ++ current_process ()->tdesc = tdesc_microblaze_linux; ++} ++ ++linux_process_target *the_linux_target = &the_microblaze_target; ++ ++void ++initialize_low_arch (void) ++{ ++ init_registers_microblaze_linux (); ++ initialize_regsets_info (µblaze_regsets_info); ++} ++ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch deleted file mode 100644 index f7af2a62..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0002-Patch-MicroBlaze-Initial-port-of-core-reading-suppor.patch +++ /dev/null @@ -1,303 +0,0 @@ -From 7da397cae8c0f8826184d6e12fda9ccd11f92753 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 10 Oct 2022 16:37:53 +0530 -Subject: [PATCH 2/8] [Patch,MicroBlaze]: Initial port of core reading support - Added support for reading notes in linux core dumps Support for reading of - PRSTATUS and PSINFO information for rebuilding ".reg" sections of core dumps - at run time. - -Upstream-Status: Pending - -Signed-off-by: David Holsgrove -Signed-off-by: Nathan Rossi -Signed-off-by: Mahesh Bodapati ---- - bfd/elf32-microblaze.c | 84 +++++++++++++++++++++++++++++++++++++ - gdb/configure.tgt | 2 +- - gdb/microblaze-linux-tdep.c | 17 +++++++- - gdb/microblaze-tdep.c | 48 +++++++++++++++++++++ - gdb/microblaze-tdep.h | 28 +++++++++++++ - 5 files changed, 177 insertions(+), 2 deletions(-) - -diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c -index d09b3f7095d..d3b3c66cf00 100644 ---- a/bfd/elf32-microblaze.c -+++ b/bfd/elf32-microblaze.c -@@ -713,6 +713,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name) - return _bfd_elf_is_local_label_name (abfd, name); - } - -+/* Support for core dump NOTE sections. */ -+static bool -+microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) -+{ -+ int offset; -+ unsigned int size; -+ -+ switch (note->descsz) -+ { -+ default: -+ return false; -+ -+ case 228: /* Linux/MicroBlaze */ -+ /* pr_cursig */ -+ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); -+ -+ /* pr_pid */ -+ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24); -+ -+ /* pr_reg */ -+ offset = 72; -+ size = 50 * 4; -+ -+ break; -+ } -+ -+ /* Make a ".reg/999" section. */ -+ return _bfd_elfcore_make_pseudosection (abfd, ".reg", -+ size, note->descpos + offset); -+} -+ -+static bool -+microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) -+{ -+ switch (note->descsz) -+ { -+ default: -+ return false; -+ -+ case 128: /* Linux/MicroBlaze elf_prpsinfo */ -+ elf_tdata (abfd)->core->program -+ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16); -+ elf_tdata (abfd)->core->command -+ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80); -+ } -+ -+ /* Note that for some reason, a spurious space is tacked -+ onto the end of the args in some (at least one anyway) -+ implementations, so strip it off if it exists. */ -+ -+ { -+ char *command = elf_tdata (abfd)->core->command; -+ int n = strlen (command); -+ -+ if (0 < n && command[n - 1] == ' ') -+ command[n - 1] = '\0'; -+ } -+ -+ return true; -+} -+ -+/* The microblaze linker (like many others) needs to keep track of -+ the number of relocs that it decides to copy as dynamic relocs in -+ check_relocs for each symbol. This is so that it can later discard -+ them if they are found to be unnecessary. We store the information -+ in a field extending the regular ELF linker hash table. */ -+ -+struct elf32_mb_dyn_relocs -+{ -+ struct elf32_mb_dyn_relocs *next; -+ -+ /* The input section of the reloc. */ -+ asection *sec; -+ -+ /* Total number of relocs copied for the input section. */ -+ bfd_size_type count; -+ -+ /* Number of pc-relative relocs copied for the input section. */ -+ bfd_size_type pc_count; -+}; -+ - /* ELF linker hash entry. */ - - struct elf32_mb_link_hash_entry -@@ -3434,4 +3515,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd, - #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections - #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook - -+#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus -+#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo -+ - #include "elf32-target.h" -diff --git a/gdb/configure.tgt b/gdb/configure.tgt -index 0705ccf32b8..7ea186481f3 100644 ---- a/gdb/configure.tgt -+++ b/gdb/configure.tgt -@@ -400,7 +400,7 @@ mep-*-*) - - microblaze*-linux-*|microblaze*-*-linux*) - # Target: Xilinx MicroBlaze running Linux -- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \ -+ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \ - symfile-mem.o linux-tdep.o" - ;; - microblaze*-*-*) -diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c -index 5748556a556..d6197c49dfd 100644 ---- a/gdb/microblaze-linux-tdep.c -+++ b/gdb/microblaze-linux-tdep.c -@@ -36,6 +36,7 @@ - #include "frame-unwind.h" - #include "tramp-frame.h" - #include "linux-tdep.h" -+#include "glibc-tdep.h" - - static int microblaze_debug_flag = 0; - -@@ -135,11 +136,14 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame = - microblaze_linux_sighandler_cache_init - }; - -- - static void - microblaze_linux_init_abi (struct gdbarch_info info, - struct gdbarch *gdbarch) - { -+ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); -+ -+ tdep->sizeof_gregset = 200; -+ - linux_init_abi (info, gdbarch, 0); - - set_gdbarch_memory_remove_breakpoint (gdbarch, -@@ -153,6 +157,17 @@ microblaze_linux_init_abi (struct gdbarch_info info, - tramp_frame_prepend_unwinder (gdbarch, - µblaze_linux_sighandler_tramp_frame); - -+ /* BFD target for core files. */ -+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) -+ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); -+ else -+ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); -+ -+ -+ /* Shared library handling. */ -+ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); -+ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); -+ - /* Enable TLS support. */ - set_gdbarch_fetch_tls_load_module_address (gdbarch, - svr4_fetch_objfile_link_map); -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index 3e8e8fe35b9..ccd37d085d6 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -666,6 +666,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) - tdesc_microblaze_with_stack_protect); - } - -+void -+microblaze_supply_gregset (const struct regset *regset, -+ struct regcache *regcache, -+ int regnum, const void *gregs) -+{ -+ const unsigned int *regs = (const unsigned int *)gregs; -+ if (regnum >= 0) -+ regcache->raw_supply (regnum, regs + regnum); -+ -+ if (regnum == -1) { -+ int i; -+ -+ for (i = 0; i < 50; i++) { -+ regcache->raw_supply (i, regs + i); -+ } -+ } -+} -+ -+ -+/* Return the appropriate register set for the core section identified -+ by SECT_NAME and SECT_SIZE. */ -+ -+static void -+microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, -+ iterate_over_regset_sections_cb *cb, -+ void *cb_data, -+ const struct regcache *regcache) -+{ -+ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); -+ -+ cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); -+ -+ cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); -+} -+ -+ -+ - static struct gdbarch * - microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - { -@@ -718,6 +755,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - microblaze_gdbarch_tdep *tdep = new microblaze_gdbarch_tdep; - gdbarch = gdbarch_alloc (&info, tdep); - -+ tdep->gregset = NULL; -+ tdep->sizeof_gregset = 0; -+ tdep->fpregset = NULL; -+ tdep->sizeof_fpregset = 0; - set_gdbarch_long_double_bit (gdbarch, 128); - - set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS); -@@ -766,6 +807,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); - if (tdesc_data != NULL) - tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); -+ //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); -+ -+ /* If we have register sets, enable the generic core file support. */ -+ if (tdep->gregset) { -+ set_gdbarch_iterate_over_regset_sections (gdbarch, -+ microblaze_iterate_over_regset_sections); -+ } - - return gdbarch; - } -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index 53fcb2297e6..2e853d84d72 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -23,8 +23,23 @@ - #include "gdbarch.h" - - /* Microblaze architecture-specific information. */ -+struct microblaze_gregset -+{ -+ microblaze_gregset() {} -+ unsigned int gregs[32]; -+ unsigned int fpregs[32]; -+ unsigned int pregs[16]; -+}; -+ - struct microblaze_gdbarch_tdep : gdbarch_tdep - { -+ int dummy; // declare something. -+ -+ /* Register sets. */ -+ struct regset *gregset; -+ size_t sizeof_gregset; -+ struct regset *fpregset; -+ size_t sizeof_fpregset; - }; - - /* Register numbers. */ -@@ -121,5 +136,18 @@ struct microblaze_frame_cache - #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} - #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} - -+extern void microblaze_supply_gregset (const struct regset *regset, -+ struct regcache *regcache, -+ int regnum, const void *gregs); -+extern void microblaze_collect_gregset (const struct regset *regset, -+ const struct regcache *regcache, -+ int regnum, void *gregs); -+extern void microblaze_supply_fpregset (struct regcache *regcache, -+ int regnum, const void *fpregs); -+extern void microblaze_collect_fpregset (const struct regcache *regcache, -+ int regnum, void *fpregs); -+ -+extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch, -+ const char *sect_name, size_t sect_size); - - #endif /* microblaze-tdep.h */ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch deleted file mode 100644 index d8ba6fca..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 6ecb1de66a6a5f55e69c9b108a3d5a85b0ebf315 Mon Sep 17 00:00:00 2001 -From: Nathan Rossi -Date: Tue, 8 May 2012 18:11:17 +1000 -Subject: [PATCH 3/8] Fix debug message when register is unavailable - -Upstream-Status: Pending - -Signed-off-by: Nathan Rossi - -Conflicts: - gdb/frame.c ---- - gdb/frame.c | 21 ++++++++++++++------- - 1 file changed, 14 insertions(+), 7 deletions(-) - -diff --git a/gdb/frame.c b/gdb/frame.c -index ce95cf8343b..c49ab9feab2 100644 ---- a/gdb/frame.c -+++ b/gdb/frame.c -@@ -1261,13 +1261,20 @@ frame_unwind_register_value (frame_info *next_frame, int regnum) - else - { - int i; -- gdb::array_view buf = value_contents (value); -- -- fprintf_unfiltered (&debug_file, " bytes="); -- fprintf_unfiltered (&debug_file, "["); -- for (i = 0; i < register_size (gdbarch, regnum); i++) -- fprintf_unfiltered (&debug_file, "%02x", buf[i]); -- fprintf_unfiltered (&debug_file, "]"); -+ const gdb_byte *buf = NULL; -+ if (value_entirely_available(value)) { -+ gdb::array_view buf = value_contents (value); -+ } -+ -+ fprintf_unfiltered (gdb_stdlog, " bytes="); -+ fprintf_unfiltered (gdb_stdlog, "["); -+ if (buf != NULL) { -+ for (i = 0; i < register_size (gdbarch, regnum); i++) -+ fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]); -+ } else { -+ fprintf_unfiltered (gdb_stdlog, "unavailable"); -+ } -+ fprintf_unfiltered (gdb_stdlog, "]"); - } - } - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0003-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Initial-port-of-core-reading-support-Added-support-f.patch new file mode 100644 index 00000000..6e86a773 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Initial-port-of-core-reading-support-Added-support-f.patch @@ -0,0 +1,301 @@ +From 118ce6c252a56ca592a7fdd40919522be00d5fb4 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 16:37:53 +0530 +Subject: [PATCH 03/54] Initial port of core reading support Added support for + reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO + information for rebuilding ".reg" sections of core dumps at run time. + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + bfd/elf32-microblaze.c | 84 +++++++++++++++++++++++++++++++++++++ + gdb/configure.tgt | 2 +- + gdb/microblaze-linux-tdep.c | 17 +++++++- + gdb/microblaze-tdep.c | 48 +++++++++++++++++++++ + gdb/microblaze-tdep.h | 28 +++++++++++++ + 5 files changed, 177 insertions(+), 2 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index a7e81c70fc8..487ddeafc5a 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -754,6 +754,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name) + return _bfd_elf_is_local_label_name (abfd, name); + } + ++/* Support for core dump NOTE sections. */ ++static bool ++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) ++{ ++ int offset; ++ unsigned int size; ++ ++ switch (note->descsz) ++ { ++ default: ++ return false; ++ ++ case 228: /* Linux/MicroBlaze */ ++ /* pr_cursig */ ++ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); ++ ++ /* pr_pid */ ++ elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24); ++ ++ /* pr_reg */ ++ offset = 72; ++ size = 50 * 4; ++ ++ break; ++ } ++ ++ /* Make a ".reg/999" section. */ ++ return _bfd_elfcore_make_pseudosection (abfd, ".reg", ++ size, note->descpos + offset); ++} ++ ++static bool ++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) ++{ ++ switch (note->descsz) ++ { ++ default: ++ return false; ++ ++ case 128: /* Linux/MicroBlaze elf_prpsinfo */ ++ elf_tdata (abfd)->core->program ++ = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16); ++ elf_tdata (abfd)->core->command ++ = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80); ++ } ++ ++ /* Note that for some reason, a spurious space is tacked ++ onto the end of the args in some (at least one anyway) ++ implementations, so strip it off if it exists. */ ++ ++ { ++ char *command = elf_tdata (abfd)->core->command; ++ int n = strlen (command); ++ ++ if (0 < n && command[n - 1] == ' ') ++ command[n - 1] = '\0'; ++ } ++ ++ return true; ++} ++ ++/* The microblaze linker (like many others) needs to keep track of ++ the number of relocs that it decides to copy as dynamic relocs in ++ check_relocs for each symbol. This is so that it can later discard ++ them if they are found to be unnecessary. We store the information ++ in a field extending the regular ELF linker hash table. */ ++ ++struct elf32_mb_dyn_relocs ++{ ++ struct elf32_mb_dyn_relocs *next; ++ ++ /* The input section of the reloc. */ ++ asection *sec; ++ ++ /* Total number of relocs copied for the input section. */ ++ bfd_size_type count; ++ ++ /* Number of pc-relative relocs copied for the input section. */ ++ bfd_size_type pc_count; ++}; ++ + /* ELF linker hash entry. */ + + struct elf32_mb_link_hash_entry +@@ -3480,4 +3561,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd, + #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections + #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook + ++#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus ++#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo ++ + #include "elf32-target.h" +diff --git a/gdb/configure.tgt b/gdb/configure.tgt +index 47a674201f9..d0673abd2b8 100644 +--- a/gdb/configure.tgt ++++ b/gdb/configure.tgt +@@ -415,7 +415,7 @@ mep-*-*) + + microblaze*-linux-*|microblaze*-*-linux*) + # Target: Xilinx MicroBlaze running Linux +- gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \ ++ gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \ + symfile-mem.o linux-tdep.o" + ;; + microblaze*-*-*) +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 9160b4ad464..17bcb50fd4f 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -36,6 +36,7 @@ + #include "frame-unwind.h" + #include "tramp-frame.h" + #include "linux-tdep.h" ++#include "glibc-tdep.h" + + static int microblaze_debug_flag = 0; + +@@ -135,11 +136,14 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame = + microblaze_linux_sighandler_cache_init + }; + +- + static void + microblaze_linux_init_abi (struct gdbarch_info info, + struct gdbarch *gdbarch) + { ++ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ ++ tdep->sizeof_gregset = 200; ++ + linux_init_abi (info, gdbarch, 0); + + set_gdbarch_memory_remove_breakpoint (gdbarch, +@@ -153,6 +157,17 @@ microblaze_linux_init_abi (struct gdbarch_info info, + tramp_frame_prepend_unwinder (gdbarch, + µblaze_linux_sighandler_tramp_frame); + ++ /* BFD target for core files. */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ ++ ++ /* Shared library handling. */ ++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); ++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); ++ + /* Enable TLS support. */ + set_gdbarch_fetch_tls_load_module_address (gdbarch, + svr4_fetch_objfile_link_map); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 28a647e940b..6ab36bd746b 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -665,6 +665,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) + tdesc_microblaze_with_stack_protect); + } + ++void ++microblaze_supply_gregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *gregs) ++{ ++ const unsigned int *regs = (const unsigned int *)gregs; ++ if (regnum >= 0) ++ regcache->raw_supply (regnum, regs + regnum); ++ ++ if (regnum == -1) { ++ int i; ++ ++ for (i = 0; i < 50; i++) { ++ regcache->raw_supply (i, regs + i); ++ } ++ } ++} ++ ++ ++/* Return the appropriate register set for the core section identified ++ by SECT_NAME and SECT_SIZE. */ ++ ++static void ++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, ++ iterate_over_regset_sections_cb *cb, ++ void *cb_data, ++ const struct regcache *regcache) ++{ ++ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ ++ cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); ++ ++ cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); ++} ++ ++ ++ + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { +@@ -716,6 +753,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + gdbarch *gdbarch + = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep)); + ++ tdep->gregset = NULL; ++ tdep->sizeof_gregset = 0; ++ tdep->fpregset = NULL; ++ tdep->sizeof_fpregset = 0; + set_gdbarch_long_double_bit (gdbarch, 128); + + set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS); +@@ -764,6 +805,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); + if (tdesc_data != NULL) + tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); ++ //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); ++ ++ /* If we have register sets, enable the generic core file support. */ ++ if (tdep->gregset) { ++ set_gdbarch_iterate_over_regset_sections (gdbarch, ++ microblaze_iterate_over_regset_sections); ++ } + + return gdbarch; + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index e9f57e97c26..738da4f0531 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -23,8 +23,23 @@ + #include "gdbarch.h" + + /* Microblaze architecture-specific information. */ ++struct microblaze_gregset ++{ ++ microblaze_gregset() {} ++ unsigned int gregs[32]; ++ unsigned int fpregs[32]; ++ unsigned int pregs[16]; ++}; ++ + struct microblaze_gdbarch_tdep : gdbarch_tdep_base + { ++ int dummy; // declare something. ++ ++ /* Register sets. */ ++ struct regset *gregset; ++ size_t sizeof_gregset; ++ struct regset *fpregset; ++ size_t sizeof_fpregset; + }; + + /* Register numbers. */ +@@ -121,5 +136,18 @@ struct microblaze_frame_cache + #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} + #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} + ++extern void microblaze_supply_gregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *gregs); ++extern void microblaze_collect_gregset (const struct regset *regset, ++ const struct regcache *regcache, ++ int regnum, void *gregs); ++extern void microblaze_supply_fpregset (struct regcache *regcache, ++ int regnum, const void *fpregs); ++extern void microblaze_collect_fpregset (const struct regcache *regcache, ++ int regnum, void *fpregs); ++ ++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch, ++ const char *sect_name, size_t sect_size); + + #endif /* microblaze-tdep.h */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Fix-debug-message-when-register-is-unavailable.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0004-Fix-debug-message-when-register-is-unavailable.patch new file mode 100644 index 00000000..1e6aff76 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0004-Fix-debug-message-when-register-is-unavailable.patch @@ -0,0 +1,45 @@ +From a027a1ce861f93bd00d814d6aef28414069330a1 Mon Sep 17 00:00:00 2001 +From: Nathan Rossi +Date: Tue, 8 May 2012 18:11:17 +1000 +Subject: [PATCH 04/54] Fix debug message when register is unavailable + +Signed-off-by: Nathan Rossi + +Conflicts: + gdb/frame.c +Signed-off-by: Aayush Misra +--- + gdb/frame.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/gdb/frame.c b/gdb/frame.c +index 87fb3d7a2d5..c4d967e01d5 100644 +--- a/gdb/frame.c ++++ b/gdb/frame.c +@@ -1313,12 +1313,20 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum) + else + { + int i; +- gdb::array_view buf = value->contents (); ++ ++ const gdb_byte *buf = NULL; ++ if (value_entirely_available(value)) { ++ gdb::array_view buf = value->contents (); ++ } + + gdb_printf (&debug_file, " bytes="); + gdb_printf (&debug_file, "["); +- for (i = 0; i < register_size (gdbarch, regnum); i++) +- gdb_printf (&debug_file, "%02x", buf[i]); ++ if (buf != NULL) { ++ for (i = 0; i < register_size (gdbarch, regnum); i++) ++ gdb_printf (&debug_file, "%02x", buf[i]); ++ } else { ++ gdb_printf (&debug_file, "unavailable"); ++ } + gdb_printf (&debug_file, "]"); + } + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch deleted file mode 100644 index 08b0ae17..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0004-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch +++ /dev/null @@ -1,836 +0,0 @@ -From 8d05b79cda7617f228fa4bb6e5147689b662699e Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 10 Oct 2022 18:53:46 +0530 -Subject: [PATCH 4/8] [Patch,MicroBlaze] : MicroBlaze native gdb port. - -signed-off-by : Mahesh Bodapati -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - ---- - gdb/Makefile.in | 2 + - gdb/configure.nat | 4 + - gdb/features/microblaze-linux.c | 79 +++++++ - gdb/microblaze-linux-nat.c | 366 ++++++++++++++++++++++++++++++++ - gdb/microblaze-linux-tdep.c | 2 + - gdb/microblaze-linux-tdep.h | 24 +++ - gdb/microblaze-tdep.c | 151 ++++++++++++- - gdb/microblaze-tdep.h | 15 +- - 8 files changed, 629 insertions(+), 14 deletions(-) - create mode 100755 gdb/features/microblaze-linux.c - create mode 100755 gdb/microblaze-linux-nat.c - create mode 100644 gdb/microblaze-linux-tdep.h - -diff --git a/gdb/Makefile.in b/gdb/Makefile.in -index aecab41eeb8..fb63e1662c1 100644 ---- a/gdb/Makefile.in -+++ b/gdb/Makefile.in -@@ -1374,6 +1374,7 @@ HFILES_NO_SRCDIR = \ - memory-map.h \ - memrange.h \ - microblaze-tdep.h \ -+ microblaze-linux-tdep.h \ - mips-linux-tdep.h \ - mips-netbsd-tdep.h \ - mips-tdep.h \ -@@ -2249,6 +2250,7 @@ ALLDEPFILES = \ - m68k-linux-nat.c \ - m68k-linux-tdep.c \ - m68k-tdep.c \ -+ microblaze-linux-nat.c \ - microblaze-linux-tdep.c \ - microblaze-tdep.c \ - mingw-hdep.c \ -diff --git a/gdb/configure.nat b/gdb/configure.nat -index b45519fd116..256c666e760 100644 ---- a/gdb/configure.nat -+++ b/gdb/configure.nat -@@ -270,6 +270,10 @@ case ${gdb_host} in - # Host: Motorola m68k running GNU/Linux. - NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o" - ;; -+ microblaze) -+ # Host: Microblaze running GNU/Linux. -+ NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o" -+ ;; - mips) - # Host: Linux/MIPS - NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \ -diff --git a/gdb/features/microblaze-linux.c b/gdb/features/microblaze-linux.c -new file mode 100755 -index 00000000000..267e12f6d59 ---- /dev/null -+++ b/gdb/features/microblaze-linux.c -@@ -0,0 +1,79 @@ -+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: -+ Original: microblaze.xml */ -+ -+#include "defs.h" -+#include "osabi.h" -+#include "target-descriptions.h" -+ -+struct target_desc *tdesc_microblaze_linux; -+static void -+initialize_tdesc_microblaze_linux (void) -+{ -+ target_desc_up result = allocate_target_description (); -+ struct tdesc_feature *feature; -+ set_tdesc_architecture (result.get(), bfd_scan_arch ("microblaze")); -+ set_tdesc_osabi (result.get(), osabi_from_tdesc_string ("GNU/Linux")); -+ -+ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze.core"); -+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); -+ -+ tdesc_microblaze_linux = result.release(); -+} -diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c -new file mode 100755 -index 00000000000..6b9daa23120 ---- /dev/null -+++ b/gdb/microblaze-linux-nat.c -@@ -0,0 +1,366 @@ -+/* Native-dependent code for GNU/Linux MicroBlaze. -+ Copyright (C) 2021 Free Software Foundation, Inc. -+ -+ This file is part of GDB. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program. If not, see . */ -+ -+#include "defs.h" -+#include "arch-utils.h" -+#include "dis-asm.h" -+#include "frame.h" -+#include "trad-frame.h" -+#include "symtab.h" -+#include "value.h" -+#include "gdbcmd.h" -+#include "breakpoint.h" -+#include "inferior.h" -+#include "gdbthread.h" -+#include "gdbcore.h" -+#include "regcache.h" -+#include "regset.h" -+#include "target.h" -+#include "frame.h" -+#include "frame-base.h" -+#include "frame-unwind.h" -+#include "osabi.h" -+#include "gdbsupport/gdb_assert.h" -+#include -+#include "target-descriptions.h" -+#include "opcodes/microblaze-opcm.h" -+#include "opcodes/microblaze-dis.h" -+#include "gregset.h" -+ -+#include "linux-nat.h" -+#include "linux-tdep.h" -+#include "target-descriptions.h" -+ -+#include -+#include -+#include -+#include "gdbsupport/gdb_wait.h" -+#include -+#include -+#include "nat/gdb_ptrace.h" -+#include "nat/linux-ptrace.h" -+#include "inf-ptrace.h" -+#include -+#include -+#include -+#include -+ -+/* Prototypes for supply_gregset etc. */ -+#include "gregset.h" -+ -+#include "microblaze-tdep.h" -+#include "microblaze-linux-tdep.h" -+#include "inferior.h" -+ -+#include "elf/common.h" -+ -+#include "auxv.h" -+#include "linux-tdep.h" -+ -+#include -+ -+ -+//int have_ptrace_getsetregs=1; -+ -+/* MicroBlaze Linux native additions to the default linux support. */ -+ -+class microblaze_linux_nat_target final : public linux_nat_target -+{ -+public: -+ /* Add our register access methods. */ -+ void fetch_registers (struct regcache *regcache, int regnum) override; -+ void store_registers (struct regcache *regcache, int regnum) override; -+ -+ /* Read suitable target description. */ -+ const struct target_desc *read_description () override; -+}; -+ -+static microblaze_linux_nat_target the_microblaze_linux_nat_target; -+ -+static int -+microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) -+{ -+ int u_addr = -1; -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace -+ * interface, and not the wordsize of the program's ABI. */ -+ int wordsize = sizeof (long); -+ -+ /* General purpose registers occupy 1 slot each in the buffer. */ -+ if (regno >= MICROBLAZE_R0_REGNUM -+ && regno <= MICROBLAZE_FSR_REGNUM) -+ u_addr = ((regno - MICROBLAZE_R0_REGNUM)* wordsize); -+ -+ return u_addr; -+} -+ -+/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) -+ from regset GREGS into REGCACHE. */ -+ -+static void -+supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs, -+ int regnum) -+{ -+ int i; -+ const elf_greg_t *regp = *gregs; -+ /* Access all registers */ -+ if (regnum == -1) -+ { -+ /* We fill the general purpose registers. */ -+ for (i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) -+ regcache->raw_supply (i, regp + i); -+ -+ /* Supply MICROBLAZE_PC_REGNUM from index 32. */ -+ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); -+ -+ /* Fill the inaccessible zero register with zero. */ -+ regcache->raw_supply_zeroed (0); -+ } -+ else if (regnum == MICROBLAZE_R0_REGNUM) -+ regcache->raw_supply_zeroed (0); -+ else if (regnum == MICROBLAZE_PC_REGNUM) -+ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); -+ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) -+ regcache->raw_supply (regnum, regp + regnum); -+} -+ -+/* Copy all general purpose registers from regset GREGS into REGCACHE. */ -+ -+void -+supply_gregset (struct regcache *regcache, const prgregset_t *gregs) -+{ -+ supply_gregset_regnum (regcache, gregs, -1); -+} -+ -+/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) -+ from REGCACHE into regset GREGS. */ -+ -+void -+fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum) -+{ -+ elf_greg_t *regp = *gregs; -+ if (regnum == -1) -+ { -+ /* We fill the general purpose registers. */ -+ for (int i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) -+ regcache->raw_collect (i, regp + i); -+ -+ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); -+ } -+ else if (regnum == MICROBLAZE_R0_REGNUM) -+ /* Nothing to do here. */ -+ ; -+ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) -+ regcache->raw_collect (regnum, regp + regnum); -+ else if (regnum == MICROBLAZE_PC_REGNUM) -+ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); -+} -+ -+/* Transfering floating-point registers between GDB, inferiors and cores. -+ Since MicroBlaze floating-point registers are the same as GPRs these do -+ nothing. */ -+ -+void -+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregs) -+{ -+} -+ -+void -+fill_fpregset (const struct regcache *regcache, -+ gdb_fpregset_t *fpregs, int regno) -+{ -+} -+ -+ -+static void -+fetch_register (struct regcache *regcache, int tid, int regno) -+{ -+ struct gdbarch *gdbarch = regcache->arch (); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ /* This isn't really an address. But ptrace thinks of it as one. */ -+ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); -+ int bytes_transferred; -+ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; -+ -+ if (regaddr == -1) -+ { -+ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ -+ regcache->raw_supply (regno, buf); -+ return; -+ } -+ -+ /* Read the raw register using sizeof(long) sized chunks. On a -+ * 32-bit platform, 64-bit floating-point registers will require two -+ * transfers. */ -+ for (bytes_transferred = 0; -+ bytes_transferred < register_size (gdbarch, regno); -+ bytes_transferred += sizeof (long)) -+ { -+ long l; -+ -+ errno = 0; -+ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); -+ if (errno == EIO) -+ { -+ printf("ptrace io error\n"); -+ } -+ regaddr += sizeof (long); -+ if (errno != 0) -+ { -+ char message[128]; -+ sprintf (message, "reading register %s (#%d)", -+ gdbarch_register_name (gdbarch, regno), regno); -+ perror_with_name (message); -+ } -+ memcpy (&buf[bytes_transferred], &l, sizeof (l)); -+ } -+ -+ /* Now supply the register. Keep in mind that the regcache's idea -+ * of the register's size may not be a multiple of sizeof -+ * (long). */ -+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) -+ { -+ /* Little-endian values are always found at the left end of the -+ * bytes transferred. */ -+ regcache->raw_supply (regno, buf); -+ } -+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) -+ { -+ /* Big-endian values are found at the right end of the bytes -+ * transferred. */ -+ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); -+ regcache->raw_supply (regno, buf + padding); -+ } -+ else -+ internal_error (__FILE__, __LINE__, -+ _("fetch_register: unexpected byte order: %d"), -+ gdbarch_byte_order (gdbarch)); -+} -+ -+ -+/* This is a wrapper for the fetch_all_gp_regs function. It is -+ * responsible for verifying if this target has the ptrace request -+ * that can be used to fetch all general-purpose registers at one -+ * shot. If it doesn't, then we should fetch them using the -+ * old-fashioned way, which is to iterate over the registers and -+ * request them one by one. */ -+static void -+fetch_gp_regs (struct regcache *regcache, int tid) -+{ -+ int i; -+/* If we've hit this point, it doesn't really matter which -+ architecture we are using. We just need to read the -+ registers in the "old-fashioned way". */ -+ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) -+ fetch_register (regcache, tid, i); -+} -+ -+/* Return a target description for the current target. */ -+ -+const struct target_desc * -+microblaze_linux_nat_target::read_description () -+{ -+ return tdesc_microblaze_linux; -+} -+ -+/* Fetch REGNUM (or all registers if REGNUM == -1) from the target -+ into REGCACHE using PTRACE_GETREGSET. */ -+ -+void -+microblaze_linux_nat_target::fetch_registers (struct regcache * regcache, -+ int regno) -+{ -+ /* Get the thread id for the ptrace call. */ -+ int tid = regcache->ptid ().lwp (); -+//int tid = get_ptrace_pid (regcache->ptid()); -+#if 1 -+ if (regno == -1) -+#endif -+ fetch_gp_regs (regcache, tid); -+#if 1 -+ else -+ fetch_register (regcache, tid, regno); -+#endif -+} -+ -+ -+/* Store REGNUM (or all registers if REGNUM == -1) to the target -+ from REGCACHE using PTRACE_SETREGSET. */ -+ -+void -+microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno) -+{ -+ int tid; -+ -+ tid = get_ptrace_pid (regcache->ptid ()); -+ -+ struct gdbarch *gdbarch = regcache->arch (); -+ /* This isn't really an address. But ptrace thinks of it as one. */ -+ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); -+ int i; -+ size_t bytes_to_transfer; -+ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; -+ -+ if (regaddr == -1) -+ return; -+ -+ /* First collect the register. Keep in mind that the regcache's -+ * idea of the register's size may not be a multiple of sizeof -+ * (long). */ -+ memset (buf, 0, sizeof buf); -+ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); -+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) -+ { -+ /* Little-endian values always sit at the left end of the buffer. */ -+ regcache->raw_collect (regno, buf); -+ } -+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) -+ { -+ /* Big-endian values sit at the right end of the buffer. */ -+ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); -+ regcache->raw_collect (regno, buf + padding); -+ } -+ -+ for (i = 0; i < bytes_to_transfer; i += sizeof (long)) -+ { -+ long l; -+ -+ memcpy (&l, &buf[i], sizeof (l)); -+ errno = 0; -+ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); -+ regaddr += sizeof (long); -+ -+ if (errno != 0) -+ { -+ char message[128]; -+ sprintf (message, "writing register %s (#%d)", -+ gdbarch_register_name (gdbarch, regno), regno); -+ perror_with_name (message); -+ } -+ } -+} -+ -+void _initialize_microblaze_linux_nat (void); -+ -+void -+_initialize_microblaze_linux_nat (void) -+{ -+ /* Register the target. */ -+ linux_target = &the_microblaze_linux_nat_target; -+ add_inf_child_target (linux_target); -+} -diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c -index d6197c49dfd..fc52adffb72 100644 ---- a/gdb/microblaze-linux-tdep.c -+++ b/gdb/microblaze-linux-tdep.c -@@ -37,6 +37,7 @@ - #include "tramp-frame.h" - #include "linux-tdep.h" - #include "glibc-tdep.h" -+#include "features/microblaze-linux.c" - - static int microblaze_debug_flag = 0; - -@@ -179,4 +180,5 @@ _initialize_microblaze_linux_tdep () - { - gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, - microblaze_linux_init_abi); -+ initialize_tdesc_microblaze_linux (); - } -diff --git a/gdb/microblaze-linux-tdep.h b/gdb/microblaze-linux-tdep.h -new file mode 100644 -index 00000000000..a2c744e2961 ---- /dev/null -+++ b/gdb/microblaze-linux-tdep.h -@@ -0,0 +1,24 @@ -+/* Target-dependent code for GNU/Linux on OpenRISC. -+ -+ Copyright (C) 2021 Free Software Foundation, Inc. -+ -+ This file is part of GDB. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program. If not, see . */ -+#ifndef MICROBLAZE_LINUX_TDEP_H -+#define MICROBLAZE_LINUX_TDEP_H -+ /* Target descriptions. */ -+ extern struct target_desc *tdesc_microblaze_linux; -+ -+#endif /* MICROBLAZE_LINUX_TDEP_H */ -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index ccd37d085d6..ccb6b730d64 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -285,6 +285,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, - cache->frameless_p = 0; /* Frame found. */ - save_hidden_pointer_found = 0; - non_stack_instruction_found = 0; -+ cache->register_offsets[rd] = -imm; - continue; - } - else if (IS_SPILL_SP(op, rd, ra)) -@@ -431,15 +432,17 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) - if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) - { - sal = find_pc_line (func_start, 0); -- -- if (sal.end < func_end -- && start_pc <= sal.end) -+ -+ if (sal.line !=0 && sal.end <= func_end && start_pc <= sal.end) { - start_pc = sal.end; -+ microblaze_debug("start_pc is %d\t sal.end is %d\t func_end is %d\t",start_pc,sal.end,func_end); -+ } - } - - ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, - &cache); - -+ - if (ostart_pc > start_pc) - return ostart_pc; - return start_pc; -@@ -453,6 +456,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache) - struct microblaze_frame_cache *cache; - struct gdbarch *gdbarch = get_frame_arch (next_frame); - int rn; -+ CORE_ADDR current_pc; - - if (*this_cache) - return (struct microblaze_frame_cache *) *this_cache; -@@ -466,10 +470,17 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache) - cache->register_offsets[rn] = -1; - - /* Call for side effects. */ -- get_frame_func (next_frame); -- -- cache->pc = get_frame_address_in_block (next_frame); -- -+ cache->pc = get_frame_func (next_frame); -+ -+// cache->pc = get_frame_address_in_block (next_frame); -+ current_pc = get_frame_pc (next_frame); -+ if (cache->pc) -+ microblaze_analyze_prologue (gdbarch, cache->pc, current_pc, cache); -+ -+ cache->saved_sp = cache->base + cache->framesize; -+ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base; -+ cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp; -+ - return cache; - } - -@@ -494,6 +505,25 @@ microblaze_frame_prev_register (struct frame_info *this_frame, - struct microblaze_frame_cache *cache = - microblaze_frame_cache (this_frame, this_cache); - -+if ((regnum == MICROBLAZE_SP_REGNUM && -+ cache->register_offsets[MICROBLAZE_SP_REGNUM]) -+ || (regnum == MICROBLAZE_FP_REGNUM && -+ cache->register_offsets[MICROBLAZE_SP_REGNUM])) -+ -+ return frame_unwind_got_constant (this_frame, regnum, -+ cache->register_offsets[MICROBLAZE_SP_REGNUM]); -+ -+if (regnum == MICROBLAZE_PC_REGNUM) -+{ -+ regnum = 15; -+ return frame_unwind_got_memory (this_frame, regnum, -+ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]); -+ -+} -+if (regnum == MICROBLAZE_SP_REGNUM) -+ regnum = 1; -+#if 0 -+ - if (cache->frameless_p) - { - if (regnum == MICROBLAZE_PC_REGNUM) -@@ -506,7 +536,9 @@ microblaze_frame_prev_register (struct frame_info *this_frame, - else - return trad_frame_get_prev_register (this_frame, cache->saved_regs, - regnum); -- -+#endif -+ return trad_frame_get_prev_register (this_frame, cache->saved_regs, -+ regnum); - } - - static const struct frame_unwind microblaze_frame_unwind = -@@ -622,7 +654,106 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) - return (TYPE_LENGTH (type) == 16); - } - -- -+#if 1 -+static std::vector -+microblaze_software_single_step (struct regcache *regcache) -+{ -+ struct gdbarch *arch = regcache->arch (); -+ //struct gdbarch_tdep *tdep = gdbarch_tdep (arch); -+ static int le_breakp[] = MICROBLAZE_BREAKPOINT_LE; -+ static int be_breakp[] = MICROBLAZE_BREAKPOINT; -+ enum bfd_endian byte_order = gdbarch_byte_order (arch); -+ int *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp; -+// std::vector ret = NULL; -+ -+ /* Save the address and the values of the next_pc and the target */ -+ static struct sstep_breaks -+ { -+ CORE_ADDR address; -+ bfd_boolean valid; -+ /* Shadow contents. */ -+ char data[INST_WORD_SIZE]; -+ } stepbreaks[2]; -+ int ii; -+ -+ CORE_ADDR pc; -+ std::vector next_pcs; -+ long insn; -+ enum microblaze_instr minstr; -+ bfd_boolean isunsignednum; -+ enum microblaze_instr_type insn_type; -+ short delay_slots; -+ int imm; -+ bfd_boolean immfound = FALSE; -+ -+ /* Set a breakpoint at the next instruction */ -+ /* If the current instruction is an imm, set it at the inst after */ -+ /* If the instruction has a delay slot, skip the delay slot */ -+ pc = regcache_read_pc (regcache); -+ insn = microblaze_fetch_instruction (pc); -+ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); -+ if (insn_type == immediate_inst) -+ { -+ int rd, ra, rb; -+ immfound = TRUE; -+ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); -+ pc = pc + INST_WORD_SIZE; -+ insn = microblaze_fetch_instruction (pc); -+ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); -+ } -+ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE; -+ if (insn_type != return_inst) { -+ stepbreaks[0].valid = TRUE; -+ } else { -+ stepbreaks[0].valid = FALSE; -+ } -+ -+ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn); -+ /* Now check for branch or return instructions */ -+ if (insn_type == branch_inst || insn_type == return_inst) { -+ int limm; -+ int lrd, lra, lrb; -+ int ra, rb; -+ bfd_boolean targetvalid; -+ bfd_boolean unconditionalbranch; -+ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm); -+ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS) -+ ra = regcache_raw_get_unsigned(regcache, lra); -+ else -+ ra = 0; -+ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS) -+ rb = regcache_raw_get_unsigned(regcache, lrb); -+ else -+ rb = 0; -+ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch); -+ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address); -+ if (unconditionalbranch) -+ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */ -+ if (targetvalid && (stepbreaks[0].valid == FALSE || -+ (stepbreaks[0].address != stepbreaks[1].address)) -+ && (stepbreaks[1].address != pc)) { -+ stepbreaks[1].valid = TRUE; -+ } else { -+ stepbreaks[1].valid = FALSE; -+ } -+ } else { -+ stepbreaks[1].valid = FALSE; -+ } -+ -+ /* Insert the breakpoints */ -+ for (ii = 0; ii < 2; ++ii) -+ { -+ -+ /* ignore invalid breakpoint. */ -+ if (stepbreaks[ii].valid) { -+ // VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);; -+ next_pcs.push_back (stepbreaks[ii].address); -+ } -+ } -+ return next_pcs; -+} -+#endif -+ - static int dwarf2_to_reg_map[78] = - { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ - 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ -@@ -790,6 +921,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - microblaze_breakpoint::bp_from_kind); - set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); - -+ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); -+ - set_gdbarch_frame_args_skip (gdbarch, 8); - - set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index 2e853d84d72..2415acfe7b6 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -60,11 +60,11 @@ enum microblaze_regnum - MICROBLAZE_R12_REGNUM, - MICROBLAZE_R13_REGNUM, - MICROBLAZE_R14_REGNUM, -- MICROBLAZE_R15_REGNUM, -+ MICROBLAZE_R15_REGNUM,MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM, - MICROBLAZE_R16_REGNUM, - MICROBLAZE_R17_REGNUM, - MICROBLAZE_R18_REGNUM, -- MICROBLAZE_R19_REGNUM, -+ MICROBLAZE_R19_REGNUM,MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM, - MICROBLAZE_R20_REGNUM, - MICROBLAZE_R21_REGNUM, - MICROBLAZE_R22_REGNUM, -@@ -77,7 +77,8 @@ enum microblaze_regnum - MICROBLAZE_R29_REGNUM, - MICROBLAZE_R30_REGNUM, - MICROBLAZE_R31_REGNUM, -- MICROBLAZE_PC_REGNUM, -+ MICROBLAZE_MAX_GPR_REGS, -+ MICROBLAZE_PC_REGNUM=32, - MICROBLAZE_MSR_REGNUM, - MICROBLAZE_EAR_REGNUM, - MICROBLAZE_ESR_REGNUM, -@@ -102,17 +103,21 @@ enum microblaze_regnum - MICROBLAZE_RTLBSX_REGNUM, - MICROBLAZE_RTLBLO_REGNUM, - MICROBLAZE_RTLBHI_REGNUM, -- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM, -+ MICROBLAZE_SLR_REGNUM, - MICROBLAZE_SHR_REGNUM, -- MICROBLAZE_NUM_REGS -+ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS - }; - -+/* Big enough to hold the size of the largest register in bytes. */ -+#define MICROBLAZE_MAX_REGISTER_SIZE 64 -+ - struct microblaze_frame_cache - { - /* Base address. */ - CORE_ADDR base; - CORE_ADDR pc; - -+ CORE_ADDR saved_sp; - /* Do we have a frame? */ - int frameless_p; - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0005-MicroBlaze-native-gdb-port.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0005-MicroBlaze-native-gdb-port.patch new file mode 100644 index 00000000..a9c6aee4 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0005-MicroBlaze-native-gdb-port.patch @@ -0,0 +1,834 @@ +From 2e84106b932f40eeaa4ae40b441b9eb7b713b2fa Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 18:53:46 +0530 +Subject: [PATCH 05/54] MicroBlaze native gdb port. + +signed-off-by : Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + gdb/Makefile.in | 2 + + gdb/configure.nat | 4 + + gdb/features/microblaze-linux.c | 79 +++++++ + gdb/microblaze-linux-nat.c | 366 ++++++++++++++++++++++++++++++++ + gdb/microblaze-linux-tdep.c | 2 + + gdb/microblaze-linux-tdep.h | 24 +++ + gdb/microblaze-tdep.c | 151 ++++++++++++- + gdb/microblaze-tdep.h | 15 +- + 8 files changed, 629 insertions(+), 14 deletions(-) + create mode 100755 gdb/features/microblaze-linux.c + create mode 100755 gdb/microblaze-linux-nat.c + create mode 100644 gdb/microblaze-linux-tdep.h + +diff --git a/gdb/Makefile.in b/gdb/Makefile.in +index 9c0a0bff2cd..1ad975b50ae 100644 +--- a/gdb/Makefile.in ++++ b/gdb/Makefile.in +@@ -1406,6 +1406,7 @@ HFILES_NO_SRCDIR = \ + memory-map.h \ + memrange.h \ + microblaze-tdep.h \ ++ microblaze-linux-tdep.h \ + mips-linux-tdep.h \ + mips-netbsd-tdep.h \ + mips-tdep.h \ +@@ -1754,6 +1755,7 @@ ALLDEPFILES = \ + m68k-linux-nat.c \ + m68k-linux-tdep.c \ + m68k-tdep.c \ ++ microblaze-linux-nat.c \ + microblaze-linux-tdep.c \ + microblaze-tdep.c \ + mingw-hdep.c \ +diff --git a/gdb/configure.nat b/gdb/configure.nat +index 1dc4206b69c..05003e57020 100644 +--- a/gdb/configure.nat ++++ b/gdb/configure.nat +@@ -274,6 +274,10 @@ case ${gdb_host} in + # Host: Motorola m68k running GNU/Linux. + NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o" + ;; ++ microblaze) ++ # Host: Microblaze running GNU/Linux. ++ NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o" ++ ;; + mips) + # Host: Linux/MIPS + NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \ +diff --git a/gdb/features/microblaze-linux.c b/gdb/features/microblaze-linux.c +new file mode 100755 +index 00000000000..267e12f6d59 +--- /dev/null ++++ b/gdb/features/microblaze-linux.c +@@ -0,0 +1,79 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze_linux; ++static void ++initialize_tdesc_microblaze_linux (void) ++{ ++ target_desc_up result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ set_tdesc_architecture (result.get(), bfd_scan_arch ("microblaze")); ++ set_tdesc_osabi (result.get(), osabi_from_tdesc_string ("GNU/Linux")); ++ ++ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze_linux = result.release(); ++} +diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c +new file mode 100755 +index 00000000000..a348001a3e2 +--- /dev/null ++++ b/gdb/microblaze-linux-nat.c +@@ -0,0 +1,366 @@ ++/* Native-dependent code for GNU/Linux MicroBlaze. ++ Copyright (C) 2021 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include "defs.h" ++#include "arch-utils.h" ++#include "dis-asm.h" ++#include "frame.h" ++#include "trad-frame.h" ++#include "symtab.h" ++#include "value.h" ++#include "gdbcmd.h" ++#include "breakpoint.h" ++#include "inferior.h" ++#include "gdbthread.h" ++#include "gdbcore.h" ++#include "regcache.h" ++#include "regset.h" ++#include "target.h" ++#include "frame.h" ++#include "frame-base.h" ++#include "frame-unwind.h" ++#include "osabi.h" ++#include "gdbsupport/gdb_assert.h" ++#include ++#include "target-descriptions.h" ++#include "opcodes/microblaze-opcm.h" ++#include "opcodes/microblaze-dis.h" ++#include "gregset.h" ++ ++#include "linux-nat.h" ++#include "linux-tdep.h" ++#include "target-descriptions.h" ++ ++#include ++#include ++#include ++#include "gdbsupport/gdb_wait.h" ++#include ++#include ++#include "nat/gdb_ptrace.h" ++#include "nat/linux-ptrace.h" ++#include "inf-ptrace.h" ++#include ++#include ++#include ++#include ++ ++/* Prototypes for supply_gregset etc. */ ++#include "gregset.h" ++ ++#include "microblaze-tdep.h" ++#include "microblaze-linux-tdep.h" ++#include "inferior.h" ++ ++#include "elf/common.h" ++ ++#include "auxv.h" ++#include "linux-tdep.h" ++ ++#include ++ ++ ++//int have_ptrace_getsetregs=1; ++ ++/* MicroBlaze Linux native additions to the default linux support. */ ++ ++class microblaze_linux_nat_target final : public linux_nat_target ++{ ++public: ++ /* Add our register access methods. */ ++ void fetch_registers (struct regcache *regcache, int regnum) override; ++ void store_registers (struct regcache *regcache, int regnum) override; ++ ++ /* Read suitable target description. */ ++ const struct target_desc *read_description () override; ++}; ++ ++static microblaze_linux_nat_target the_microblaze_linux_nat_target; ++ ++static int ++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) ++{ ++ int u_addr = -1; ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace ++ * interface, and not the wordsize of the program's ABI. */ ++ int wordsize = sizeof (long); ++ ++ /* General purpose registers occupy 1 slot each in the buffer. */ ++ if (regno >= MICROBLAZE_R0_REGNUM ++ && regno <= MICROBLAZE_FSR_REGNUM) ++ u_addr = ((regno - MICROBLAZE_R0_REGNUM)* wordsize); ++ ++ return u_addr; ++} ++ ++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) ++ from regset GREGS into REGCACHE. */ ++ ++static void ++supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs, ++ int regnum) ++{ ++ int i; ++ const elf_greg_t *regp = *gregs; ++ /* Access all registers */ ++ if (regnum == -1) ++ { ++ /* We fill the general purpose registers. */ ++ for (i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) ++ regcache->raw_supply (i, regp + i); ++ ++ /* Supply MICROBLAZE_PC_REGNUM from index 32. */ ++ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); ++ ++ /* Fill the inaccessible zero register with zero. */ ++ regcache->raw_supply_zeroed (0); ++ } ++ else if (regnum == MICROBLAZE_R0_REGNUM) ++ regcache->raw_supply_zeroed (0); ++ else if (regnum == MICROBLAZE_PC_REGNUM) ++ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); ++ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) ++ regcache->raw_supply (regnum, regp + regnum); ++} ++ ++/* Copy all general purpose registers from regset GREGS into REGCACHE. */ ++ ++void ++supply_gregset (struct regcache *regcache, const prgregset_t *gregs) ++{ ++ supply_gregset_regnum (regcache, gregs, -1); ++} ++ ++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) ++ from REGCACHE into regset GREGS. */ ++ ++void ++fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum) ++{ ++ elf_greg_t *regp = *gregs; ++ if (regnum == -1) ++ { ++ /* We fill the general purpose registers. */ ++ for (int i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) ++ regcache->raw_collect (i, regp + i); ++ ++ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); ++ } ++ else if (regnum == MICROBLAZE_R0_REGNUM) ++ /* Nothing to do here. */ ++ ; ++ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) ++ regcache->raw_collect (regnum, regp + regnum); ++ else if (regnum == MICROBLAZE_PC_REGNUM) ++ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); ++} ++ ++/* Transfering floating-point registers between GDB, inferiors and cores. ++ Since MicroBlaze floating-point registers are the same as GPRs these do ++ nothing. */ ++ ++void ++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregs) ++{ ++} ++ ++void ++fill_fpregset (const struct regcache *regcache, ++ gdb_fpregset_t *fpregs, int regno) ++{ ++} ++ ++ ++static void ++fetch_register (struct regcache *regcache, int tid, int regno) ++{ ++ struct gdbarch *gdbarch = regcache->arch (); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int bytes_transferred; ++ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ { ++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ ++ regcache->raw_supply (regno, buf); ++ return; ++ } ++ ++ /* Read the raw register using sizeof(long) sized chunks. On a ++ * 32-bit platform, 64-bit floating-point registers will require two ++ * transfers. */ ++ for (bytes_transferred = 0; ++ bytes_transferred < register_size (gdbarch, regno); ++ bytes_transferred += sizeof (long)) ++ { ++ long l; ++ ++ errno = 0; ++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); ++ if (errno == EIO) ++ { ++ printf("ptrace io error\n"); ++ } ++ regaddr += sizeof (long); ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "reading register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ memcpy (&buf[bytes_transferred], &l, sizeof (l)); ++ } ++ ++ /* Now supply the register. Keep in mind that the regcache's idea ++ * of the register's size may not be a multiple of sizeof ++ * (long). */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values are always found at the left end of the ++ * bytes transferred. */ ++ regcache->raw_supply (regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values are found at the right end of the bytes ++ * transferred. */ ++ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); ++ regcache->raw_supply (regno, buf + padding); ++ } ++ else ++ internal_error (__FILE__, __LINE__, ++ _("fetch_register: unexpected byte order: %d"), ++ gdbarch_byte_order (gdbarch)); ++} ++ ++ ++/* This is a wrapper for the fetch_all_gp_regs function. It is ++ * responsible for verifying if this target has the ptrace request ++ * that can be used to fetch all general-purpose registers at one ++ * shot. If it doesn't, then we should fetch them using the ++ * old-fashioned way, which is to iterate over the registers and ++ * request them one by one. */ ++static void ++fetch_gp_regs (struct regcache *regcache, int tid) ++{ ++ int i; ++/* If we've hit this point, it doesn't really matter which ++ architecture we are using. We just need to read the ++ registers in the "old-fashioned way". */ ++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) ++ fetch_register (regcache, tid, i); ++} ++ ++/* Return a target description for the current target. */ ++ ++const struct target_desc * ++microblaze_linux_nat_target::read_description () ++{ ++ return tdesc_microblaze_linux; ++} ++ ++/* Fetch REGNUM (or all registers if REGNUM == -1) from the target ++ into REGCACHE using PTRACE_GETREGSET. */ ++ ++void ++microblaze_linux_nat_target::fetch_registers (struct regcache * regcache, ++ int regno) ++{ ++ /* Get the thread id for the ptrace call. */ ++ int tid = regcache->ptid ().lwp (); ++//int tid = get_ptrace_pid (regcache->ptid()); ++#if 1 ++ if (regno == -1) ++#endif ++ fetch_gp_regs (regcache, tid); ++#if 1 ++ else ++ fetch_register (regcache, tid, regno); ++#endif ++} ++ ++ ++/* Store REGNUM (or all registers if REGNUM == -1) to the target ++ from REGCACHE using PTRACE_SETREGSET. */ ++ ++void ++microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno) ++{ ++ int tid; ++ ++ tid = get_ptrace_pid (regcache->ptid ()); ++ ++ struct gdbarch *gdbarch = regcache->arch (); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int i; ++ size_t bytes_to_transfer; ++ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ return; ++ ++ /* First collect the register. Keep in mind that the regcache's ++ * idea of the register's size may not be a multiple of sizeof ++ * (long). */ ++ memset (buf, 0, sizeof buf); ++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values always sit at the left end of the buffer. */ ++ regcache->raw_collect (regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values sit at the right end of the buffer. */ ++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); ++ regcache->raw_collect (regno, buf + padding); ++ } ++ ++ for (i = 0; i < bytes_to_transfer; i += sizeof (long)) ++ { ++ long l; ++ ++ memcpy (&l, &buf[i], sizeof (l)); ++ errno = 0; ++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); ++ regaddr += sizeof (long); ++ ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "writing register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ } ++} ++ ++void _initialize_microblaze_linux_nat (void); ++ ++void ++_initialize_microblaze_linux_nat (void) ++{ ++ /* Register the target. */ ++ linux_target = &the_microblaze_linux_nat_target; ++ add_inf_child_target (linux_target); ++} +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 17bcb50fd4f..5b57bb4d3ba 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,6 +37,7 @@ + #include "tramp-frame.h" + #include "linux-tdep.h" + #include "glibc-tdep.h" ++#include "features/microblaze-linux.c" + + static int microblaze_debug_flag = 0; + +@@ -179,4 +180,5 @@ _initialize_microblaze_linux_tdep () + { + gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, + microblaze_linux_init_abi); ++ initialize_tdesc_microblaze_linux (); + } +diff --git a/gdb/microblaze-linux-tdep.h b/gdb/microblaze-linux-tdep.h +new file mode 100644 +index 00000000000..a2c744e2961 +--- /dev/null ++++ b/gdb/microblaze-linux-tdep.h +@@ -0,0 +1,24 @@ ++/* Target-dependent code for GNU/Linux on OpenRISC. ++ ++ Copyright (C) 2021 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++#ifndef MICROBLAZE_LINUX_TDEP_H ++#define MICROBLAZE_LINUX_TDEP_H ++ /* Target descriptions. */ ++ extern struct target_desc *tdesc_microblaze_linux; ++ ++#endif /* MICROBLAZE_LINUX_TDEP_H */ +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 6ab36bd746b..066602b385a 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -285,6 +285,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, + cache->frameless_p = 0; /* Frame found. */ + save_hidden_pointer_found = 0; + non_stack_instruction_found = 0; ++ cache->register_offsets[rd] = -imm; + continue; + } + else if (IS_SPILL_SP(op, rd, ra)) +@@ -431,15 +432,17 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) + if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) + { + sal = find_pc_line (func_start, 0); +- +- if (sal.end < func_end +- && start_pc <= sal.end) ++ ++ if (sal.line !=0 && sal.end <= func_end && start_pc <= sal.end) { + start_pc = sal.end; ++ microblaze_debug("start_pc is %d\t sal.end is %d\t func_end is %d\t",start_pc,sal.end,func_end); ++ } + } + + ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, + &cache); + ++ + if (ostart_pc > start_pc) + return ostart_pc; + return start_pc; +@@ -453,6 +456,7 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache) + struct microblaze_frame_cache *cache; + struct gdbarch *gdbarch = get_frame_arch (next_frame); + int rn; ++ CORE_ADDR current_pc; + + if (*this_cache) + return (struct microblaze_frame_cache *) *this_cache; +@@ -466,10 +470,17 @@ microblaze_frame_cache (frame_info_ptr next_frame, void **this_cache) + cache->register_offsets[rn] = -1; + + /* Call for side effects. */ +- get_frame_func (next_frame); +- +- cache->pc = get_frame_address_in_block (next_frame); +- ++ cache->pc = get_frame_func (next_frame); ++ ++// cache->pc = get_frame_address_in_block (next_frame); ++ current_pc = get_frame_pc (next_frame); ++ if (cache->pc) ++ microblaze_analyze_prologue (gdbarch, cache->pc, current_pc, cache); ++ ++ cache->saved_sp = cache->base + cache->framesize; ++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base; ++ cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp; ++ + return cache; + } + +@@ -494,6 +505,25 @@ microblaze_frame_prev_register (frame_info_ptr this_frame, + struct microblaze_frame_cache *cache = + microblaze_frame_cache (this_frame, this_cache); + ++if ((regnum == MICROBLAZE_SP_REGNUM && ++ cache->register_offsets[MICROBLAZE_SP_REGNUM]) ++ || (regnum == MICROBLAZE_FP_REGNUM && ++ cache->register_offsets[MICROBLAZE_SP_REGNUM])) ++ ++ return frame_unwind_got_constant (this_frame, regnum, ++ cache->register_offsets[MICROBLAZE_SP_REGNUM]); ++ ++if (regnum == MICROBLAZE_PC_REGNUM) ++{ ++ regnum = 15; ++ return frame_unwind_got_memory (this_frame, regnum, ++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]); ++ ++} ++if (regnum == MICROBLAZE_SP_REGNUM) ++ regnum = 1; ++#if 0 ++ + if (cache->frameless_p) + { + if (regnum == MICROBLAZE_PC_REGNUM) +@@ -506,7 +536,9 @@ microblaze_frame_prev_register (frame_info_ptr this_frame, + else + return trad_frame_get_prev_register (this_frame, cache->saved_regs, + regnum); +- ++#endif ++ return trad_frame_get_prev_register (this_frame, cache->saved_regs, ++ regnum); + } + + static const struct frame_unwind microblaze_frame_unwind = +@@ -621,7 +653,106 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) + return (type->length () == 16); + } + +- ++#if 1 ++static std::vector ++microblaze_software_single_step (struct regcache *regcache) ++{ ++ struct gdbarch *arch = regcache->arch (); ++ //struct gdbarch_tdep *tdep = gdbarch_tdep (arch); ++ static int le_breakp[] = MICROBLAZE_BREAKPOINT_LE; ++ static int be_breakp[] = MICROBLAZE_BREAKPOINT; ++ enum bfd_endian byte_order = gdbarch_byte_order (arch); ++ int *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp; ++// std::vector ret = NULL; ++ ++ /* Save the address and the values of the next_pc and the target */ ++ static struct sstep_breaks ++ { ++ CORE_ADDR address; ++ bfd_boolean valid; ++ /* Shadow contents. */ ++ char data[INST_WORD_SIZE]; ++ } stepbreaks[2]; ++ int ii; ++ ++ CORE_ADDR pc; ++ std::vector next_pcs; ++ long insn; ++ enum microblaze_instr minstr; ++ bfd_boolean isunsignednum; ++ enum microblaze_instr_type insn_type; ++ short delay_slots; ++ int imm; ++ bfd_boolean immfound = FALSE; ++ ++ /* Set a breakpoint at the next instruction */ ++ /* If the current instruction is an imm, set it at the inst after */ ++ /* If the instruction has a delay slot, skip the delay slot */ ++ pc = regcache_read_pc (regcache); ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ if (insn_type == immediate_inst) ++ { ++ int rd, ra, rb; ++ immfound = TRUE; ++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); ++ pc = pc + INST_WORD_SIZE; ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ } ++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE; ++ if (insn_type != return_inst) { ++ stepbreaks[0].valid = TRUE; ++ } else { ++ stepbreaks[0].valid = FALSE; ++ } ++ ++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn); ++ /* Now check for branch or return instructions */ ++ if (insn_type == branch_inst || insn_type == return_inst) { ++ int limm; ++ int lrd, lra, lrb; ++ int ra, rb; ++ bfd_boolean targetvalid; ++ bfd_boolean unconditionalbranch; ++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm); ++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS) ++ ra = regcache_raw_get_unsigned(regcache, lra); ++ else ++ ra = 0; ++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS) ++ rb = regcache_raw_get_unsigned(regcache, lrb); ++ else ++ rb = 0; ++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch); ++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address); ++ if (unconditionalbranch) ++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */ ++ if (targetvalid && (stepbreaks[0].valid == FALSE || ++ (stepbreaks[0].address != stepbreaks[1].address)) ++ && (stepbreaks[1].address != pc)) { ++ stepbreaks[1].valid = TRUE; ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ ++ /* Insert the breakpoints */ ++ for (ii = 0; ii < 2; ++ii) ++ { ++ ++ /* ignore invalid breakpoint. */ ++ if (stepbreaks[ii].valid) { ++ // VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);; ++ next_pcs.push_back (stepbreaks[ii].address); ++ } ++ } ++ return next_pcs; ++} ++#endif ++ + static int dwarf2_to_reg_map[78] = + { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ + 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ +@@ -788,6 +919,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::bp_from_kind); + set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + ++ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); ++ + set_gdbarch_frame_args_skip (gdbarch, 8); + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 738da4f0531..21f206777f0 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -60,11 +60,11 @@ enum microblaze_regnum + MICROBLAZE_R12_REGNUM, + MICROBLAZE_R13_REGNUM, + MICROBLAZE_R14_REGNUM, +- MICROBLAZE_R15_REGNUM, ++ MICROBLAZE_R15_REGNUM,MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM, + MICROBLAZE_R16_REGNUM, + MICROBLAZE_R17_REGNUM, + MICROBLAZE_R18_REGNUM, +- MICROBLAZE_R19_REGNUM, ++ MICROBLAZE_R19_REGNUM,MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM, + MICROBLAZE_R20_REGNUM, + MICROBLAZE_R21_REGNUM, + MICROBLAZE_R22_REGNUM, +@@ -77,7 +77,8 @@ enum microblaze_regnum + MICROBLAZE_R29_REGNUM, + MICROBLAZE_R30_REGNUM, + MICROBLAZE_R31_REGNUM, +- MICROBLAZE_PC_REGNUM, ++ MICROBLAZE_MAX_GPR_REGS, ++ MICROBLAZE_PC_REGNUM=32, + MICROBLAZE_MSR_REGNUM, + MICROBLAZE_EAR_REGNUM, + MICROBLAZE_ESR_REGNUM, +@@ -102,17 +103,21 @@ enum microblaze_regnum + MICROBLAZE_RTLBSX_REGNUM, + MICROBLAZE_RTLBLO_REGNUM, + MICROBLAZE_RTLBHI_REGNUM, +- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM, ++ MICROBLAZE_SLR_REGNUM, + MICROBLAZE_SHR_REGNUM, +- MICROBLAZE_NUM_REGS ++ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS + }; + ++/* Big enough to hold the size of the largest register in bytes. */ ++#define MICROBLAZE_MAX_REGISTER_SIZE 64 ++ + struct microblaze_frame_cache + { + /* Base address. */ + CORE_ADDR base; + CORE_ADDR pc; + ++ CORE_ADDR saved_sp; + /* Do we have a frame? */ + int frameless_p; + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0005-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0005-Patch-microblaze-Adding-64-bit-MB-support.patch deleted file mode 100644 index 6eea28fe..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0005-Patch-microblaze-Adding-64-bit-MB-support.patch +++ /dev/null @@ -1,5789 +0,0 @@ -From 6aadc445a00275c37112e431c6a29f5a331e6e16 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Thu, 31 Jan 2019 14:36:00 +0530 -Subject: [PATCH 5/8] [Patch, microblaze]: Adding 64 bit MB support Added new - architecture to Microblaze 64-bit support to GDB Signed-off-by :Nagaraju - Mekala Signed-off-by :Mahesh Bodapati - - -Conflicts: - gdb/Makefile.in - -Conflicts: - bfd/cpu-microblaze.c - gdb/microblaze-tdep.c - ld/Makefile.am - ld/Makefile.in - opcodes/microblaze-dis.c - -Conflicts: - bfd/configure - gas/config/tc-microblaze.c - ld/Makefile.in - opcodes/microblaze-opcm.h - -Conflicts: - gdb/microblaze-tdep.c - -Conflicts: - bfd/elf32-microblaze.c - gas/config/tc-microblaze.c - gdb/features/Makefile - gdb/features/microblaze-with-stack-protect.c - gdb/microblaze-tdep.c - gdb/regformats/microblaze-with-stack-protect.dat - gdbserver/linux-microblaze-low.c - include/elf/common.h -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - ---- - bfd/Makefile.am | 2 + - bfd/Makefile.in | 3 + - bfd/archures.c | 2 + - bfd/bfd-in2.h | 31 +- - bfd/config.bfd | 4 + - bfd/configure | 2 + - bfd/cpu-microblaze.c | 55 +- - bfd/elf32-microblaze.c | 162 +- - bfd/elf64-microblaze.c | 3810 +++++++++++++++++ - bfd/libbfd.h | 3 + - bfd/reloc.c | 20 + - bfd/targets.c | 6 + - gdb/features/Makefile | 2 + - gdb/features/microblaze-core.xml | 6 +- - gdb/features/microblaze-stack-protect.xml | 4 +- - gdb/features/microblaze-with-stack-protect.c | 8 +- - gdb/features/microblaze.c | 6 +- - gdb/features/microblaze64-core.xml | 69 + - gdb/features/microblaze64-stack-protect.xml | 12 + - .../microblaze64-with-stack-protect.c | 79 + - .../microblaze64-with-stack-protect.xml | 12 + - gdb/features/microblaze64.c | 77 + - gdb/features/microblaze64.xml | 11 + - gdb/microblaze-linux-tdep.c | 36 +- - gdb/microblaze-tdep.c | 126 +- - gdb/microblaze-tdep.h | 4 +- - include/elf/common.h | 1 + - include/elf/microblaze.h | 4 + - opcodes/microblaze-dis.c | 51 +- - opcodes/microblaze-opc.h | 180 +- - opcodes/microblaze-opcm.h | 36 +- - 31 files changed, 4729 insertions(+), 95 deletions(-) - create mode 100755 bfd/elf64-microblaze.c - create mode 100644 gdb/features/microblaze64-core.xml - create mode 100644 gdb/features/microblaze64-stack-protect.xml - create mode 100644 gdb/features/microblaze64-with-stack-protect.c - create mode 100644 gdb/features/microblaze64-with-stack-protect.xml - create mode 100644 gdb/features/microblaze64.c - create mode 100644 gdb/features/microblaze64.xml - -diff --git a/bfd/Makefile.am b/bfd/Makefile.am -index b9a3f8207ac..2ddd7891661 100644 ---- a/bfd/Makefile.am -+++ b/bfd/Makefile.am -@@ -571,6 +571,7 @@ BFD64_BACKENDS = \ - elf64-riscv.lo \ - elfxx-riscv.lo \ - elf64-s390.lo \ -+ elf64-microblaze.lo \ - elf64-sparc.lo \ - elf64-tilegx.lo \ - elf64-x86-64.lo \ -@@ -608,6 +609,7 @@ BFD64_BACKENDS_CFILES = \ - elf64-nfp.c \ - elf64-ppc.c \ - elf64-s390.c \ -+ elf64-microblaze.c \ - elf64-sparc.c \ - elf64-tilegx.c \ - elf64-x86-64.c \ -diff --git a/bfd/Makefile.in b/bfd/Makefile.in -index 934dd4bc066..7efb10f111d 100644 ---- a/bfd/Makefile.in -+++ b/bfd/Makefile.in -@@ -1040,6 +1040,7 @@ BFD64_BACKENDS = \ - elf64-riscv.lo \ - elfxx-riscv.lo \ - elf64-s390.lo \ -+ elf64-microblaze.lo \ - elf64-sparc.lo \ - elf64-tilegx.lo \ - elf64-x86-64.lo \ -@@ -1077,6 +1078,7 @@ BFD64_BACKENDS_CFILES = \ - elf64-nfp.c \ - elf64-ppc.c \ - elf64-s390.c \ -+ elf64-microblaze.c \ - elf64-sparc.c \ - elf64-tilegx.c \ - elf64-x86-64.c \ -@@ -1664,6 +1666,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@ -diff --git a/bfd/archures.c b/bfd/archures.c -index fac9fe82a08..1790c741c58 100644 ---- a/bfd/archures.c -+++ b/bfd/archures.c -@@ -524,6 +524,8 @@ DESCRIPTION - . bfd_arch_lm32, {* Lattice Mico32. *} - .#define bfd_mach_lm32 1 - . bfd_arch_microblaze,{* Xilinx MicroBlaze. *} -+.#define bfd_mach_microblaze 1 -+.#define bfd_mach_microblaze64 2 - . bfd_arch_tilepro, {* Tilera TILEPro. *} - . bfd_arch_tilegx, {* Tilera TILE-Gx. *} - .#define bfd_mach_tilepro 1 -diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index c0b563aec02..ccaeecb9476 100644 ---- a/bfd/bfd-in2.h -+++ b/bfd/bfd-in2.h -@@ -1903,6 +1903,8 @@ enum bfd_architecture - bfd_arch_lm32, /* Lattice Mico32. */ - #define bfd_mach_lm32 1 - bfd_arch_microblaze,/* Xilinx MicroBlaze. */ -+#define bfd_mach_microblaze 1 -+#define bfd_mach_microblaze64 2 - bfd_arch_tilepro, /* Tilera TILEPro. */ - bfd_arch_tilegx, /* Tilera TILE-Gx. */ - #define bfd_mach_tilepro 1 -@@ -5443,16 +5445,41 @@ value relative to the read-write small data area anchor */ - expressions of the form "Symbol Op Symbol" */ - BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, - --/* This is a 64 bit reloc that stores the 32 bit pc relative -+/* This is a 32 bit reloc that stores the 32 bit pc relative - value in two words (with an imm instruction). No relocation is - done here - only used for relaxing */ -- BFD_RELOC_MICROBLAZE_64_NONE, -+ BFD_RELOC_MICROBLAZE_32_NONE, -+ -+/* This is a 64 bit reloc that stores the 32 bit pc relative -+ * +value in two words (with an imml instruction). No relocation is -+ * +done here - only used for relaxing */ -+ BFD_RELOC_MICROBLAZE_64_PCREL, -+ -+/* This is a 64 bit reloc that stores the 32 bit relative -+ * +value in two words (with an imml instruction). No relocation is -+ * +done here - only used for relaxing */ -+ BFD_RELOC_MICROBLAZE_64, -+ -+/* This is a 64 bit reloc that stores the 32 bit relative -+ * +value in two words (with an imml instruction). No relocation is -+ * +done here - only used for relaxing */ -+ BFD_RELOC_MICROBLAZE_EA64, -+ -+/* This is a 64 bit reloc that stores the 32 bit pc relative -+ * +value in two words (with an imm instruction). No relocation is -+ * +done here - only used for relaxing */ -+ BFD_RELOC_MICROBLAZE_64_NONE, - - /* This is a 64 bit reloc that stores the 32 bit pc relative - value in two words (with an imm instruction). The relocation is - PC-relative GOT offset */ - BFD_RELOC_MICROBLAZE_64_GOTPC, - -+/* This is a 64 bit reloc that stores the 32 bit pc relative -+value in two words (with an imml instruction). The relocation is -+PC-relative GOT offset */ -+ BFD_RELOC_MICROBLAZE_64_GPC, -+ - /* This is a 64 bit reloc that stores the 32 bit pc relative - value in two words (with an imm instruction). The relocation is - GOT offset */ -diff --git a/bfd/config.bfd b/bfd/config.bfd -index 872685cfb72..5e9ba3d9805 100644 ---- a/bfd/config.bfd -+++ b/bfd/config.bfd -@@ -860,11 +860,15 @@ case "${targ}" in - microblazeel*-*) - targ_defvec=microblaze_elf32_le_vec - targ_selvecs=microblaze_elf32_vec -+ targ64_selvecs=microblaze_elf64_vec -+ targ64_selvecs=microblaze_elf64_le_vec - ;; - - microblaze*-*) - targ_defvec=microblaze_elf32_vec - targ_selvecs=microblaze_elf32_le_vec -+ targ64_selvecs=microblaze_elf64_vec -+ targ64_selvecs=microblaze_elf64_le_vec - ;; - - #ifdef BFD64 -diff --git a/bfd/configure b/bfd/configure -index 0ef4c206fb0..b7547c6777c 100755 ---- a/bfd/configure -+++ b/bfd/configure -@@ -13547,6 +13547,8 @@ do - rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; - s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; - s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; -+ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; -+ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; - score_elf32_be_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;; - score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;; - sh_coff_vec) tb="$tb coff-sh.lo $coff" ;; -diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c -index 0c1d2b1aa69..106f78229b5 100644 ---- a/bfd/cpu-microblaze.c -+++ b/bfd/cpu-microblaze.c -@@ -23,13 +23,30 @@ - #include "bfd.h" - #include "libbfd.h" - --const bfd_arch_info_type bfd_microblaze_arch = -+const bfd_arch_info_type bfd_microblaze_arch[] = -+{ -+#if BFD_DEFAULT_TARGET_SIZE == 64 -+{ -+ 64, /* 32 bits in a word. */ -+ 64, /* 32 bits in an address. */ -+ 8, /* 8 bits in a byte. */ -+ bfd_arch_microblaze, /* Architecture. */ -+ bfd_mach_microblaze64, /* 64 bit Machine */ -+ "microblaze", /* Architecture name. */ -+ "MicroBlaze", /* Printable name. */ -+ 3, /* Section align power. */ -+ false, /* Is this the default architecture ? */ -+ bfd_default_compatible, /* Architecture comparison function. */ -+ bfd_default_scan, /* String to architecture conversion. */ -+ bfd_arch_default_fill, /* Default fill. */ -+ &bfd_microblaze_arch[1] /* Next in list. */ -+}, - { - 32, /* Bits in a word. */ - 32, /* Bits in an address. */ - 8, /* Bits in a byte. */ - bfd_arch_microblaze, /* Architecture number. */ -- 0, /* Machine number - 0 for now. */ -+ bfd_mach_microblaze, /* Machine number - 0 for now. */ - "microblaze", /* Architecture name. */ - "MicroBlaze", /* Printable name. */ - 3, /* Section align power. */ -@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_arch = - bfd_arch_default_fill, /* Default fill. */ - NULL, /* Next in list. */ - 0 /* Maximum offset of a reloc from the start of an insn. */ -+} -+#else -+{ -+ 32, /* 32 bits in a word. */ -+ 32, /* 32 bits in an address. */ -+ 8, /* 8 bits in a byte. */ -+ bfd_arch_microblaze, /* Architecture. */ -+ bfd_mach_microblaze, /* 32 bit Machine */ -+ "microblaze", /* Architecture name. */ -+ "MicroBlaze", /* Printable name. */ -+ 3, /* Section align power. */ -+ true, /* Is this the default architecture ? */ -+ bfd_default_compatible, /* Architecture comparison function. */ -+ bfd_default_scan, /* String to architecture conversion. */ -+ bfd_arch_default_fill, /* Default fill. */ -+ &bfd_microblaze_arch[1] /* Next in list. */ -+}, -+{ -+ 64, /* 32 bits in a word. */ -+ 64, /* 32 bits in an address. */ -+ 8, /* 8 bits in a byte. */ -+ bfd_arch_microblaze, /* Architecture. */ -+ bfd_mach_microblaze64, /* 64 bit Machine */ -+ "microblaze", /* Architecture name. */ -+ "MicroBlaze", /* Printable name. */ -+ 3, /* Section align power. */ -+ false, /* Is this the default architecture ? */ -+ bfd_default_compatible, /* Architecture comparison function. */ -+ bfd_default_scan, /* String to architecture conversion. */ -+ bfd_arch_default_fill, /* Default fill. */ -+ NULL, /* Next in list. */ -+ 0 -+} -+#endif - }; -diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c -index d3b3c66cf00..053c1b432f9 100644 ---- a/bfd/elf32-microblaze.c -+++ b/bfd/elf32-microblaze.c -@@ -114,6 +114,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] = - 0x0000ffff, /* Dest Mask. */ - true), /* PC relative offset? */ - -+ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_IMML_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ - /* A 64 bit relocation. Table entry not really used. */ - HOWTO (R_MICROBLAZE_64, /* Type. */ - 0, /* Rightshift. */ -@@ -174,7 +188,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = - 0x0000ffff, /* Dest Mask. */ - false), /* PC relative offset? */ - -- /* This reloc does nothing. Used for relaxation. */ -+ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 32, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_bitfield, /* Complain on overflow. */ -+ NULL, /* Special Function. */ -+ "R_MICROBLAZE_32_NONE",/* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* This reloc does nothing. Used for relaxation. */ - HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ - 0, /* Rightshift. */ - 3, /* Size (0 = byte, 1 = short, 2 = long). */ -@@ -264,6 +292,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = - 0x0000ffff, /* Dest Mask. */ - true), /* PC relative offset? */ - -+ /* A 64 bit GOTPC relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc, /* Special Function. */ -+ "R_MICROBLAZE_GPC_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ - /* A 64 bit GOT relocation. Table-entry not really used. */ - HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ - 0, /* Rightshift. */ -@@ -560,6 +603,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, - case BFD_RELOC_NONE: - microblaze_reloc = R_MICROBLAZE_NONE; - break; -+ case BFD_RELOC_MICROBLAZE_32_NONE: -+ microblaze_reloc = R_MICROBLAZE_32_NONE; -+ break; - case BFD_RELOC_MICROBLAZE_64_NONE: - microblaze_reloc = R_MICROBLAZE_64_NONE; - break; -@@ -600,9 +646,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, - case BFD_RELOC_VTABLE_ENTRY: - microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; - break; -+ case BFD_RELOC_MICROBLAZE_64: -+ microblaze_reloc = R_MICROBLAZE_IMML_64; -+ break; - case BFD_RELOC_MICROBLAZE_64_GOTPC: - microblaze_reloc = R_MICROBLAZE_GOTPC_64; - break; -+ case BFD_RELOC_MICROBLAZE_64_GPC: -+ microblaze_reloc = R_MICROBLAZE_GPC_64; -+ break; - case BFD_RELOC_MICROBLAZE_64_GOT: - microblaze_reloc = R_MICROBLAZE_GOT_64; - break; -@@ -1507,9 +1559,9 @@ microblaze_elf_relocate_section (bfd *output_bfd, - relocation += addend; - relocation -= dtprel_base(info); - bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, -- contents + offset + 2); -+ contents + offset + endian); - bfd_put_16 (input_bfd, relocation & 0xffff, -- contents + offset + 2 + INST_WORD_SIZE); -+ contents + offset + endian + INST_WORD_SIZE); - break; - case (int) R_MICROBLAZE_TEXTREL_64: - case (int) R_MICROBLAZE_TEXTREL_32_LO: -@@ -1523,7 +1575,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, - if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) - { - relocation += addend; -- if (r_type == R_MICROBLAZE_32) -+ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) - bfd_put_32 (input_bfd, relocation, contents + offset); - else - { -@@ -1925,8 +1977,7 @@ microblaze_elf_relax_section (bfd *abfd, - else - symval += irel->r_addend; - -- if ((symval & 0xffff8000) == 0 -- || (symval & 0xffff8000) == 0xffff8000) -+ if ((symval & 0xffff8000) == 0) - { - /* We can delete this instruction. */ - sec->relax[sec->relax_count].addr = irel->r_offset; -@@ -1990,21 +2041,51 @@ microblaze_elf_relax_section (bfd *abfd, - irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); - } - break; -+ case R_MICROBLAZE_IMML_64: -+ { -+ /* This was a PC-relative instruction that was -+ completely resolved. */ -+ int sfix, efix; -+ unsigned int val; -+ bfd_vma target_address; -+ target_address = irel->r_addend + irel->r_offset; -+ sfix = calc_fixup (irel->r_offset, 0, sec); -+ efix = calc_fixup (target_address, 0, sec); -+ -+ /* Validate the in-band val. */ -+ val = bfd_get_32 (abfd, contents + irel->r_offset); -+ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { -+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); -+ } -+ irel->r_addend -= (efix - sfix); -+ /* Should use HOWTO. */ -+ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, -+ irel->r_addend); -+ } -+ break; - case R_MICROBLAZE_NONE: -+ case R_MICROBLAZE_32_NONE: - { - /* This was a PC-relative instruction that was - completely resolved. */ - int sfix, efix; -+ unsigned int val; - bfd_vma target_address; - target_address = irel->r_addend + irel->r_offset; - sfix = calc_fixup (irel->r_offset, 0, sec); - efix = calc_fixup (target_address, 0, sec); -+ -+ /* Validate the in-band val. */ -+ val = bfd_get_32 (abfd, contents + irel->r_offset); -+ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { -+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); -+ } - irel->r_addend -= (efix - sfix); - /* Should use HOWTO. */ - microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, - irel->r_addend); -- } -- break; -+ } -+ break; - case R_MICROBLAZE_64_NONE: - { - /* This was a PC-relative 64-bit instruction that was -@@ -2015,8 +2096,8 @@ microblaze_elf_relax_section (bfd *abfd, - sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); - efix = calc_fixup (target_address, 0, sec); - irel->r_addend -= (efix - sfix); -- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset -- + INST_WORD_SIZE, irel->r_addend); -+ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, -+ irel->r_addend); - } - break; - } -@@ -2046,9 +2127,50 @@ microblaze_elf_relax_section (bfd *abfd, - irelscanend = irelocs + o->reloc_count; - for (irelscan = irelocs; irelscan < irelscanend; irelscan++) - { -- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) -- { -- isym = isymbuf + ELF32_R_SYM (irelscan->r_info); -+ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) -+ { -+ unsigned int val; -+ -+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); -+ -+ /* hax: We only do the following fixup for debug location lists. */ -+ if (strcmp(".debug_loc", o->name)) -+ continue; -+ -+ /* This was a PC-relative instruction that was completely resolved. */ -+ if (ocontents == NULL) -+ { -+ if (elf_section_data (o)->this_hdr.contents != NULL) -+ ocontents = elf_section_data (o)->this_hdr.contents; -+ else -+ { -+ /* We always cache the section contents. -+ Perhaps, if info->keep_memory is FALSE, we -+ should free them, if we are permitted to. */ -+ -+ if (o->rawsize == 0) -+ o->rawsize = o->size; -+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); -+ if (ocontents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, o, ocontents, -+ (file_ptr) 0, -+ o->rawsize)) -+ goto error_return; -+ elf_section_data (o)->this_hdr.contents = ocontents; -+ } -+ } -+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); -+ if (val != irelscan->r_addend) { -+ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); -+ } -+ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); -+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, -+ irelscan->r_addend); -+ } -+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) -+ { -+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); - - /* Look at the reloc only if the value has been resolved. */ - if (isym->st_shndx == shndx -@@ -2105,7 +2227,7 @@ microblaze_elf_relax_section (bfd *abfd, - elf_section_data (o)->this_hdr.contents = ocontents; - } - } -- irelscan->r_addend -= calc_fixup (irel->r_addend -+ irelscan->r_addend -= calc_fixup (irelscan->r_addend - + isym->st_value, - 0, - sec); -@@ -3445,6 +3567,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd, - return true; - } - -+ -+static bool -+elf_microblaze_object_p (bfd *abfd) -+{ -+ /* Set the right machine number for an s390 elf32 file. */ -+ return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze); -+} -+ - /* Hook called by the linker routine which adds symbols from an object - file. We use it to put .comm items in .sbss, and not .bss. */ - -@@ -3514,8 +3644,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd, - #define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol - #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections - #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook -- --#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus --#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo -+#define elf_backend_object_p elf_microblaze_object_p - - #include "elf32-target.h" -diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c -new file mode 100755 -index 00000000000..6cd9753a592 ---- /dev/null -+++ b/bfd/elf64-microblaze.c -@@ -0,0 +1,3810 @@ -+/* Xilinx MicroBlaze-specific support for 32-bit ELF -+ -+ Copyright (C) 2009-2021 Free Software Foundation, Inc. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the -+ Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, -+ Boston, MA 02110-1301, USA. */ -+ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "bfdlink.h" -+#include "libbfd.h" -+#include "elf-bfd.h" -+#include "elf/microblaze.h" -+#include -+ -+#define USE_RELA /* Only USE_REL is actually significant, but this is -+ here are a reminder... */ -+#define INST_WORD_SIZE 4 -+ -+static int ro_small_data_pointer = 0; -+static int rw_small_data_pointer = 0; -+ -+static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max]; -+ -+static reloc_howto_type microblaze_elf_howto_raw[] = -+{ -+ /* This reloc does nothing. */ -+ HOWTO (R_MICROBLAZE_NONE, /* Type. */ -+ 0, /* Rightshift. */ -+ 0, /* Size. */ -+ 0, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ NULL, /* Special Function. */ -+ "R_MICROBLAZE_NONE", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* A standard 32 bit relocation. */ -+ HOWTO (R_MICROBLAZE_32, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 32, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_bitfield, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_32", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0xffffffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* A standard PCREL 32 bit relocation. */ -+ HOWTO (R_MICROBLAZE_32_PCREL,/* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 32, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_bitfield, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_32_PCREL", /* Name. */ -+ true, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0xffffffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* A 64 bit PCREL relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_64_PCREL,/* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_64_PCREL", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* The low half of a PCREL 32 bit relocation. */ -+ HOWTO (R_MICROBLAZE_32_PCREL_LO, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_signed, /* Complain on overflow. */ -+ bfd_elf_generic_reloc, /* Special Function. */ -+ "R_MICROBLAZE_32_PCREL_LO", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 64, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_IMML_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0xffffffffffffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* A 64 bit relocation. Table entry not really used. */ -+ HOWTO (R_MICROBLAZE_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* The low half of a 32 bit relocation. */ -+ HOWTO (R_MICROBLAZE_32_LO, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_signed, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_32_LO", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* Read-only small data section relocation. */ -+ HOWTO (R_MICROBLAZE_SRO32, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_bitfield, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_SRO32", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* Read-write small data area relocation. */ -+ HOWTO (R_MICROBLAZE_SRW32, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_bitfield, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_SRW32", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* This reloc does nothing. Used for relaxation. */ -+ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 32, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_bitfield, /* Complain on overflow. */ -+ NULL, /* Special Function. */ -+ "R_MICROBLAZE_32_NONE",/* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* This reloc does nothing. Used for relaxation. */ -+ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ -+ 0, /* Rightshift. */ -+ 0, /* Size. */ -+ 0, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ NULL, /* Special Function. */ -+ "R_MICROBLAZE_64_NONE",/* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* Symbol Op Symbol relocation. */ -+ HOWTO (R_MICROBLAZE_32_SYM_OP_SYM, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 32, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_bitfield, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_32_SYM_OP_SYM", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0xffffffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* GNU extension to record C++ vtable hierarchy. */ -+ HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 0, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont,/* Complain on overflow. */ -+ NULL, /* Special Function. */ -+ "R_MICROBLAZE_GNU_VTINHERIT", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* GNU extension to record C++ vtable member usage. */ -+ HOWTO (R_MICROBLAZE_GNU_VTENTRY, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 0, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont,/* Complain on overflow. */ -+ _bfd_elf_rel_vtable_reloc_fn, /* Special Function. */ -+ "R_MICROBLAZE_GNU_VTENTRY", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* A 64 bit GOTPC relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_GOTPC_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc, /* Special Function. */ -+ "R_MICROBLAZE_GOTPC_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* A 64 bit TEXTPCREL relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_TEXTPCREL_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc, /* Special Function. */ -+ "R_MICROBLAZE_TEXTPCREL_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* A 64 bit GOTPC relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc, /* Special Function. */ -+ "R_MICROBLAZE_GPC_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* A 64 bit GOT relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_GOT_64",/* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* A 64 bit TEXTREL relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_TEXTREL_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 2, /* Size (0 = byte, 1 = short, 2 = long). */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_TEXTREL_64",/* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* A 64 bit PLT relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_PLT_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_PLT_64",/* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_REL, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_REL", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_JUMP_SLOT", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ true, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_GLOB_DAT", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ true), /* PC relative offset? */ -+ -+ /* A 64 bit GOT relative relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_GOTOFF_64, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_GOTOFF_64", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* A 32 bit GOT relative relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_GOTOFF_32, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc, /* Special Function. */ -+ "R_MICROBLAZE_GOTOFF_32", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* COPY relocation. Table-entry not really used. */ -+ HOWTO (R_MICROBLAZE_COPY, /* Type. */ -+ 0, /* Rightshift. */ -+ 4, /* Size. */ -+ 16, /* Bitsize. */ -+ false, /* PC_relative. */ -+ 0, /* Bitpos. */ -+ complain_overflow_dont, /* Complain on overflow. */ -+ bfd_elf_generic_reloc,/* Special Function. */ -+ "R_MICROBLAZE_COPY", /* Name. */ -+ false, /* Partial Inplace. */ -+ 0, /* Source Mask. */ -+ 0x0000ffff, /* Dest Mask. */ -+ false), /* PC relative offset? */ -+ -+ /* Marker relocs for TLS. */ -+ HOWTO (R_MICROBLAZE_TLS, -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLS", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ HOWTO (R_MICROBLAZE_TLSGD, -+ 0, /* rightshift */ -+ 4, /* size */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLSGD", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ HOWTO (R_MICROBLAZE_TLSLD, -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLSLD", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Computes the load module index of the load module that contains the -+ definition of its TLS sym. */ -+ HOWTO (R_MICROBLAZE_TLSDTPMOD32, -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLSDTPMOD32", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Computes a dtv-relative displacement, the difference between the value -+ of sym+add and the base address of the thread-local storage block that -+ contains the definition of sym, minus 0x8000. Used for initializing GOT */ -+ HOWTO (R_MICROBLAZE_TLSDTPREL32, -+ 0, /* rightshift */ -+ 4, /* size */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLSDTPREL32", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Computes a dtv-relative displacement, the difference between the value -+ of sym+add and the base address of the thread-local storage block that -+ contains the definition of sym, minus 0x8000. */ -+ HOWTO (R_MICROBLAZE_TLSDTPREL64, -+ 0, /* rightshift */ -+ 4, /* size */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLSDTPREL64", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Computes a tp-relative displacement, the difference between the value of -+ sym+add and the value of the thread pointer (r13). */ -+ HOWTO (R_MICROBLAZE_TLSGOTTPREL32, -+ 0, /* rightshift */ -+ 4, /* size */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLSGOTTPREL32", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Computes a tp-relative displacement, the difference between the value of -+ sym+add and the value of the thread pointer (r13). */ -+ HOWTO (R_MICROBLAZE_TLSTPREL32, -+ 0, /* rightshift */ -+ 4, /* size */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_MICROBLAZE_TLSTPREL32", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0x0000ffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+}; -+ -+#ifndef NUM_ELEM -+#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) -+#endif -+ -+/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done. */ -+ -+static void -+microblaze_elf_howto_init (void) -+{ -+ unsigned int i; -+ -+ for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;) -+ { -+ unsigned int type; -+ -+ type = microblaze_elf_howto_raw[i].type; -+ -+ BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table)); -+ -+ microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i]; -+ } -+} -+ -+static reloc_howto_type * -+microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, -+ bfd_reloc_code_real_type code) -+{ -+ enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE; -+ -+ switch (code) -+ { -+ case BFD_RELOC_NONE: -+ microblaze_reloc = R_MICROBLAZE_NONE; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_NONE: -+ microblaze_reloc = R_MICROBLAZE_32_NONE; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_NONE: -+ microblaze_reloc = R_MICROBLAZE_64_NONE; -+ break; -+ case BFD_RELOC_32: -+ microblaze_reloc = R_MICROBLAZE_32; -+ break; -+ /* RVA is treated the same as 64 */ -+ case BFD_RELOC_RVA: -+ microblaze_reloc = R_MICROBLAZE_IMML_64; -+ break; -+ case BFD_RELOC_32_PCREL: -+ microblaze_reloc = R_MICROBLAZE_32_PCREL; -+ break; -+ case BFD_RELOC_64_PCREL: -+ microblaze_reloc = R_MICROBLAZE_64_PCREL; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_LO_PCREL: -+ microblaze_reloc = R_MICROBLAZE_32_PCREL_LO; -+ break; -+ case BFD_RELOC_64: -+ microblaze_reloc = R_MICROBLAZE_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_LO: -+ microblaze_reloc = R_MICROBLAZE_32_LO; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_ROSDA: -+ microblaze_reloc = R_MICROBLAZE_SRO32; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_RWSDA: -+ microblaze_reloc = R_MICROBLAZE_SRW32; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: -+ microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM; -+ break; -+ case BFD_RELOC_VTABLE_INHERIT: -+ microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT; -+ break; -+ case BFD_RELOC_VTABLE_ENTRY: -+ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; -+ break; -+ case BFD_RELOC_MICROBLAZE_EA64: -+ microblaze_reloc = R_MICROBLAZE_IMML_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_GOTPC: -+ microblaze_reloc = R_MICROBLAZE_GOTPC_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_GPC: -+ microblaze_reloc = R_MICROBLAZE_GPC_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_GOT: -+ microblaze_reloc = R_MICROBLAZE_GOT_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_TEXTPCREL: -+ microblaze_reloc = R_MICROBLAZE_TEXTPCREL_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_TEXTREL: -+ microblaze_reloc = R_MICROBLAZE_TEXTREL_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_PLT: -+ microblaze_reloc = R_MICROBLAZE_PLT_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_GOTOFF: -+ microblaze_reloc = R_MICROBLAZE_GOTOFF_64; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_GOTOFF: -+ microblaze_reloc = R_MICROBLAZE_GOTOFF_32; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_TLSGD: -+ microblaze_reloc = R_MICROBLAZE_TLSGD; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_TLSLD: -+ microblaze_reloc = R_MICROBLAZE_TLSLD; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_TLSDTPREL: -+ microblaze_reloc = R_MICROBLAZE_TLSDTPREL32; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_TLSDTPREL: -+ microblaze_reloc = R_MICROBLAZE_TLSDTPREL64; -+ break; -+ case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD: -+ microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL: -+ microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32; -+ break; -+ case BFD_RELOC_MICROBLAZE_64_TLSTPREL: -+ microblaze_reloc = R_MICROBLAZE_TLSTPREL32; -+ break; -+ case BFD_RELOC_MICROBLAZE_COPY: -+ microblaze_reloc = R_MICROBLAZE_COPY; -+ break; -+ default: -+ return (reloc_howto_type *) NULL; -+ } -+ -+ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) -+ /* Initialize howto table if needed. */ -+ microblaze_elf_howto_init (); -+ -+ return microblaze_elf_howto_table [(int) microblaze_reloc]; -+}; -+ -+static reloc_howto_type * -+microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, -+ const char *r_name) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++) -+ if (microblaze_elf_howto_raw[i].name != NULL -+ && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0) -+ return µblaze_elf_howto_raw[i]; -+ -+ return NULL; -+} -+ -+/* Set the howto pointer for a RCE ELF reloc. */ -+ -+static bool -+microblaze_elf_info_to_howto (bfd * abfd, -+ arelent * cache_ptr, -+ Elf_Internal_Rela * dst) -+{ -+ unsigned int r_type; -+ -+ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) -+ /* Initialize howto table if needed. */ -+ microblaze_elf_howto_init (); -+ -+ r_type = ELF64_R_TYPE (dst->r_info); -+ if (r_type >= R_MICROBLAZE_max) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler (_("%pB: unsupported relocation type %#x"), -+ abfd, r_type); -+ bfd_set_error (bfd_error_bad_value); -+ return false; -+ } -+ -+ cache_ptr->howto = microblaze_elf_howto_table [r_type]; -+ return true; -+} -+ -+struct _microblaze_elf_section_data -+{ -+ struct bfd_elf_section_data elf; -+ /* Count of used relaxation table entries. */ -+ size_t relax_count; -+ /* Relaxation table. */ -+ struct relax_table *relax; -+}; -+ -+#define microblaze_elf_section_data(sec) \ -+ ((struct _microblaze_elf_section_data *) elf_section_data (sec)) -+ -+static bool -+microblaze_elf_new_section_hook (bfd *abfd, asection *sec) -+{ -+ if (!sec->used_by_bfd) -+ { -+ struct _microblaze_elf_section_data *sdata; -+ size_t amt = sizeof (*sdata); -+ -+ sdata = bfd_zalloc (abfd, amt); -+ if (sdata == NULL) -+ return false; -+ sec->used_by_bfd = sdata; -+ } -+ -+ return _bfd_elf_new_section_hook (abfd, sec); -+} -+ -+/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */ -+ -+static bool -+microblaze_elf_is_local_label_name (bfd *abfd, const char *name) -+{ -+ if (name[0] == 'L' && name[1] == '.') -+ return true; -+ -+ if (name[0] == '$' && name[1] == 'L') -+ return true; -+ -+ /* With gcc, the labels go back to starting with '.', so we accept -+ the generic ELF local label syntax as well. */ -+ return _bfd_elf_is_local_label_name (abfd, name); -+} -+ -+/* The microblaze linker (like many others) needs to keep track of -+ the number of relocs that it decides to copy as dynamic relocs in -+ check_relocs for each symbol. This is so that it can later discard -+ them if they are found to be unnecessary. We store the information -+ in a field extending the regular ELF linker hash table. */ -+ -+struct elf64_mb_dyn_relocs -+{ -+ struct elf64_mb_dyn_relocs *next; -+ -+ /* The input section of the reloc. */ -+ asection *sec; -+ -+ /* Total number of relocs copied for the input section. */ -+ bfd_size_type count; -+ -+ /* Number of pc-relative relocs copied for the input section. */ -+ bfd_size_type pc_count; -+}; -+ -+/* ELF linker hash entry. */ -+ -+struct elf64_mb_link_hash_entry -+{ -+ struct elf_link_hash_entry elf; -+ -+ /* Track dynamic relocs copied for this symbol. */ -+ struct elf64_mb_dyn_relocs *dyn_relocs; -+ -+ /* TLS Reference Types for the symbol; Updated by check_relocs */ -+#define TLS_GD 1 /* GD reloc. */ -+#define TLS_LD 2 /* LD reloc. */ -+#define TLS_TPREL 4 /* TPREL reloc, => IE. */ -+#define TLS_DTPREL 8 /* DTPREL reloc, => LD. */ -+#define TLS_TLS 16 /* Any TLS reloc. */ -+ unsigned char tls_mask; -+ -+}; -+ -+#define IS_TLS_GD(x) (x == (TLS_TLS | TLS_GD)) -+#define IS_TLS_LD(x) (x == (TLS_TLS | TLS_LD)) -+#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL)) -+#define IS_TLS_NONE(x) (x == 0) -+ -+#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent)) -+ -+/* ELF linker hash table. */ -+ -+struct elf64_mb_link_hash_table -+{ -+ struct elf_link_hash_table elf; -+ -+ /* Short-cuts to get to dynamic linker sections. */ -+ asection *sgot; -+ asection *sgotplt; -+ asection *srelgot; -+ asection *splt; -+ asection *srelplt; -+ asection *sdynbss; -+ asection *srelbss; -+ -+ /* Small local sym to section mapping cache. */ -+ struct sym_cache sym_sec; -+ -+ /* TLS Local Dynamic GOT Entry */ -+ union { -+ bfd_signed_vma refcount; -+ bfd_vma offset; -+ } tlsld_got; -+}; -+ -+/* Nonzero if this section has TLS related relocations. */ -+#define has_tls_reloc sec_flg0 -+ -+/* Get the ELF linker hash table from a link_info structure. */ -+ -+#define elf64_mb_hash_table(p) \ -+ ((is_elf_hash_table ((p)->hash) \ -+ && elf_hash_table_id (elf_hash_table (p)) == MICROBLAZE_ELF_DATA) \ -+ ? (struct elf64_mb_link_hash_table *) (p)->hash : NULL) -+ -+/* Create an entry in a microblaze ELF linker hash table. */ -+ -+static struct bfd_hash_entry * -+link_hash_newfunc (struct bfd_hash_entry *entry, -+ struct bfd_hash_table *table, -+ const char *string) -+{ -+ /* Allocate the structure if it has not already been allocated by a -+ subclass. */ -+ if (entry == NULL) -+ { -+ entry = bfd_hash_allocate (table, -+ sizeof (struct elf64_mb_link_hash_entry)); -+ if (entry == NULL) -+ return entry; -+ } -+ -+ /* Call the allocation method of the superclass. */ -+ entry = _bfd_elf_link_hash_newfunc (entry, table, string); -+ if (entry != NULL) -+ { -+ struct elf64_mb_link_hash_entry *eh; -+ -+ eh = (struct elf64_mb_link_hash_entry *) entry; -+ eh->tls_mask = 0; -+ } -+ -+ return entry; -+} -+ -+/* Create a mb ELF linker hash table. */ -+ -+static struct bfd_link_hash_table * -+microblaze_elf_link_hash_table_create (bfd *abfd) -+{ -+ struct elf64_mb_link_hash_table *ret; -+ size_t amt = sizeof (struct elf64_mb_link_hash_table); -+ -+ ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt); -+ if (ret == NULL) -+ return NULL; -+ -+ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, -+ sizeof (struct elf64_mb_link_hash_entry), -+ MICROBLAZE_ELF_DATA)) -+ { -+ free (ret); -+ return NULL; -+ } -+ -+ return &ret->elf.root; -+} -+ -+/* Set the values of the small data pointers. */ -+ -+static void -+microblaze_elf_final_sdp (struct bfd_link_info *info) -+{ -+ struct bfd_link_hash_entry *h; -+ -+ h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, false, false, true); -+ if (h != (struct bfd_link_hash_entry *) NULL -+ && h->type == bfd_link_hash_defined) -+ ro_small_data_pointer = (h->u.def.value -+ + h->u.def.section->output_section->vma -+ + h->u.def.section->output_offset); -+ -+ h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, false, false, true); -+ if (h != (struct bfd_link_hash_entry *) NULL -+ && h->type == bfd_link_hash_defined) -+ rw_small_data_pointer = (h->u.def.value -+ + h->u.def.section->output_section->vma -+ + h->u.def.section->output_offset); -+} -+ -+static bfd_vma -+dtprel_base (struct bfd_link_info *info) -+{ -+ /* If tls_sec is NULL, we should have signalled an error already. */ -+ if (elf_hash_table (info)->tls_sec == NULL) -+ return 0; -+ return elf_hash_table (info)->tls_sec->vma; -+} -+ -+/* The size of the thread control block. */ -+#define TCB_SIZE 8 -+ -+/* Output a simple dynamic relocation into SRELOC. */ -+ -+static void -+microblaze_elf_output_dynamic_relocation (bfd *output_bfd, -+ asection *sreloc, -+ unsigned long reloc_index, -+ unsigned long indx, -+ int r_type, -+ bfd_vma offset, -+ bfd_vma addend) -+{ -+ -+ Elf_Internal_Rela rel; -+ -+ rel.r_info = ELF64_R_INFO (indx, r_type); -+ rel.r_offset = offset; -+ rel.r_addend = addend; -+ -+ bfd_elf64_swap_reloca_out (output_bfd, &rel, -+ (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela))); -+} -+ -+/* This code is taken from elf64-m32r.c -+ There is some attempt to make this function usable for many architectures, -+ both USE_REL and USE_RELA ['twould be nice if such a critter existed], -+ if only to serve as a learning tool. -+ -+ The RELOCATE_SECTION function is called by the new ELF backend linker -+ to handle the relocations for a section. -+ -+ The relocs are always passed as Rela structures; if the section -+ actually uses Rel structures, the r_addend field will always be -+ zero. -+ -+ This function is responsible for adjust the section contents as -+ necessary, and (if using Rela relocs and generating a -+ relocatable output file) adjusting the reloc addend as -+ necessary. -+ -+ This function does not have to worry about setting the reloc -+ address or the reloc symbol index. -+ -+ LOCAL_SYMS is a pointer to the swapped in local symbols. -+ -+ LOCAL_SECTIONS is an array giving the section in the input file -+ corresponding to the st_shndx field of each local symbol. -+ -+ The global hash table entry for the global symbols can be found -+ via elf_sym_hashes (input_bfd). -+ -+ When generating relocatable output, this function must handle -+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is -+ going to be the section symbol corresponding to the output -+ section, which means that the addend must be adjusted -+ accordingly. */ -+ -+static int -+microblaze_elf_relocate_section (bfd *output_bfd, -+ struct bfd_link_info *info, -+ bfd *input_bfd, -+ asection *input_section, -+ bfd_byte *contents, -+ Elf_Internal_Rela *relocs, -+ Elf_Internal_Sym *local_syms, -+ asection **local_sections) -+{ -+ struct elf64_mb_link_hash_table *htab; -+ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; -+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); -+ Elf_Internal_Rela *rel, *relend; -+ int endian = (bfd_little_endian (output_bfd)) ? 0 : 2; -+ /* Assume success. */ -+ bool ret = true; -+ asection *sreloc; -+ bfd_vma *local_got_offsets; -+ unsigned int tls_type; -+ -+ if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1]) -+ microblaze_elf_howto_init (); -+ -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ local_got_offsets = elf_local_got_offsets (input_bfd); -+ -+ sreloc = elf_section_data (input_section)->sreloc; -+ -+ rel = relocs; -+ relend = relocs + input_section->reloc_count; -+ for (; rel < relend; rel++) -+ { -+ int r_type; -+ reloc_howto_type *howto; -+ unsigned long r_symndx; -+ bfd_vma addend = rel->r_addend; -+ bfd_vma offset = rel->r_offset; -+ struct elf_link_hash_entry *h; -+ Elf_Internal_Sym *sym; -+ asection *sec; -+ const char *sym_name; -+ bfd_reloc_status_type r = bfd_reloc_ok; -+ const char *errmsg = NULL; -+ bool unresolved_reloc = false; -+ -+ h = NULL; -+ r_type = ELF64_R_TYPE (rel->r_info); -+ tls_type = 0; -+ -+ if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler (_("%pB: unsupported relocation type %#x"), -+ input_bfd, (int) r_type); -+ bfd_set_error (bfd_error_bad_value); -+ ret = false; -+ continue; -+ } -+ -+ howto = microblaze_elf_howto_table[r_type]; -+ r_symndx = ELF64_R_SYM (rel->r_info); -+ -+ if (bfd_link_relocatable (info)) -+ { -+ /* This is a relocatable link. We don't have to change -+ anything, unless the reloc is against a section symbol, -+ in which case we have to adjust according to where the -+ section symbol winds up in the output section. */ -+ sec = NULL; -+ if (r_symndx >= symtab_hdr->sh_info) -+ /* External symbol. */ -+ continue; -+ -+ /* Local symbol. */ -+ sym = local_syms + r_symndx; -+ sym_name = ""; -+ /* STT_SECTION: symbol is associated with a section. */ -+ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) -+ /* Symbol isn't associated with a section. Nothing to do. */ -+ continue; -+ -+ sec = local_sections[r_symndx]; -+ addend += sec->output_offset + sym->st_value; -+#ifndef USE_REL -+ /* This can't be done for USE_REL because it doesn't mean anything -+ and elf_link_input_bfd asserts this stays zero. */ -+ /* rel->r_addend = addend; */ -+#endif -+ -+#ifndef USE_REL -+ /* Addends are stored with relocs. We're done. */ -+ continue; -+#else /* USE_REL */ -+ /* If partial_inplace, we need to store any additional addend -+ back in the section. */ -+ if (!howto->partial_inplace) -+ continue; -+ /* ??? Here is a nice place to call a special_function like handler. */ -+ r = _bfd_relocate_contents (howto, input_bfd, addend, -+ contents + offset); -+#endif /* USE_REL */ -+ } -+ else -+ { -+ bfd_vma relocation; -+ bool resolved_to_zero; -+ -+ /* This is a final link. */ -+ sym = NULL; -+ sec = NULL; -+ unresolved_reloc = false; -+ -+ if (r_symndx < symtab_hdr->sh_info) -+ { -+ /* Local symbol. */ -+ sym = local_syms + r_symndx; -+ sec = local_sections[r_symndx]; -+ if (sec == 0) -+ continue; -+ sym_name = ""; -+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); -+ /* r_addend may have changed if the reference section was -+ a merge section. */ -+ addend = rel->r_addend; -+ } -+ else -+ { -+ /* External symbol. */ -+ bool warned ATTRIBUTE_UNUSED; -+ bool ignored ATTRIBUTE_UNUSED; -+ -+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, -+ r_symndx, symtab_hdr, sym_hashes, -+ h, sec, relocation, -+ unresolved_reloc, warned, ignored); -+ sym_name = h->root.root.string; -+ } -+ -+ /* Sanity check the address. */ -+ if (offset > bfd_get_section_limit (input_bfd, input_section)) -+ { -+ r = bfd_reloc_outofrange; -+ goto check_reloc; -+ } -+ -+ resolved_to_zero = (h != NULL -+ && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)); -+ -+ switch ((int) r_type) -+ { -+ case (int) R_MICROBLAZE_SRO32 : -+ { -+ const char *name; -+ -+ /* Only relocate if the symbol is defined. */ -+ if (sec) -+ { -+ name = bfd_section_name (sec); -+ -+ if (strcmp (name, ".sdata2") == 0 -+ || strcmp (name, ".sbss2") == 0) -+ { -+ if (ro_small_data_pointer == 0) -+ microblaze_elf_final_sdp (info); -+ if (ro_small_data_pointer == 0) -+ { -+ ret = false; -+ r = bfd_reloc_undefined; -+ goto check_reloc; -+ } -+ -+ /* At this point `relocation' contains the object's -+ address. */ -+ relocation -= ro_small_data_pointer; -+ /* Now it contains the offset from _SDA2_BASE_. */ -+ r = _bfd_final_link_relocate (howto, input_bfd, -+ input_section, -+ contents, offset, -+ relocation, addend); -+ } -+ else -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_("%pB: the target (%s) of an %s relocation" -+ " is in the wrong section (%pA)"), -+ input_bfd, -+ sym_name, -+ microblaze_elf_howto_table[(int) r_type]->name, -+ sec); -+ /*bfd_set_error (bfd_error_bad_value); ??? why? */ -+ ret = false; -+ continue; -+ } -+ } -+ } -+ break; -+ -+ case (int) R_MICROBLAZE_SRW32 : -+ { -+ const char *name; -+ -+ /* Only relocate if the symbol is defined. */ -+ if (sec) -+ { -+ name = bfd_section_name (sec); -+ -+ if (strcmp (name, ".sdata") == 0 -+ || strcmp (name, ".sbss") == 0) -+ { -+ if (rw_small_data_pointer == 0) -+ microblaze_elf_final_sdp (info); -+ if (rw_small_data_pointer == 0) -+ { -+ ret = false; -+ r = bfd_reloc_undefined; -+ goto check_reloc; -+ } -+ -+ /* At this point `relocation' contains the object's -+ address. */ -+ relocation -= rw_small_data_pointer; -+ /* Now it contains the offset from _SDA_BASE_. */ -+ r = _bfd_final_link_relocate (howto, input_bfd, -+ input_section, -+ contents, offset, -+ relocation, addend); -+ } -+ else -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_("%pB: the target (%s) of an %s relocation" -+ " is in the wrong section (%pA)"), -+ input_bfd, -+ sym_name, -+ microblaze_elf_howto_table[(int) r_type]->name, -+ sec); -+ /*bfd_set_error (bfd_error_bad_value); ??? why? */ -+ ret = false; -+ continue; -+ } -+ } -+ } -+ break; -+ -+ case (int) R_MICROBLAZE_32_SYM_OP_SYM: -+ break; /* Do nothing. */ -+ -+ case (int) R_MICROBLAZE_GOTPC_64: -+ relocation = (htab->elf.sgotplt->output_section->vma -+ + htab->elf.sgotplt->output_offset); -+ relocation -= (input_section->output_section->vma -+ + input_section->output_offset -+ + offset + INST_WORD_SIZE); -+ relocation += addend; -+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ break; -+ -+ case (int) R_MICROBLAZE_TEXTPCREL_64: -+ relocation = input_section->output_section->vma; -+ relocation -= (input_section->output_section->vma -+ + input_section->output_offset -+ + offset + INST_WORD_SIZE); -+ relocation += addend; -+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ break; -+ -+ case (int) R_MICROBLAZE_PLT_64: -+ { -+ bfd_vma immediate; -+ if (htab->elf.splt != NULL && h != NULL -+ && h->plt.offset != (bfd_vma) -1) -+ { -+ relocation = (htab->elf.splt->output_section->vma -+ + htab->elf.splt->output_offset -+ + h->plt.offset); -+ unresolved_reloc = false; -+ immediate = relocation - (input_section->output_section->vma -+ + input_section->output_offset -+ + offset + INST_WORD_SIZE); -+ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, immediate & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ } -+ else -+ { -+ relocation -= (input_section->output_section->vma -+ + input_section->output_offset -+ + offset + INST_WORD_SIZE); -+ immediate = relocation; -+ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, immediate & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ } -+ break; -+ } -+ -+ case (int) R_MICROBLAZE_TLSGD: -+ tls_type = (TLS_TLS | TLS_GD); -+ goto dogot; -+ case (int) R_MICROBLAZE_TLSLD: -+ tls_type = (TLS_TLS | TLS_LD); -+ /* Fall through. */ -+ dogot: -+ case (int) R_MICROBLAZE_GOT_64: -+ { -+ bfd_vma *offp; -+ bfd_vma off, off2; -+ unsigned long indx; -+ bfd_vma static_value; -+ -+ bool need_relocs = false; -+ if (htab->elf.sgot == NULL) -+ abort (); -+ -+ indx = 0; -+ offp = NULL; -+ -+ /* 1. Identify GOT Offset; -+ 2. Compute Static Values -+ 3. Process Module Id, Process Offset -+ 4. Fixup Relocation with GOT offset value. */ -+ -+ /* 1. Determine GOT Offset to use : TLS_LD, global, local */ -+ if (IS_TLS_LD (tls_type)) -+ offp = &htab->tlsld_got.offset; -+ else if (h != NULL) -+ { -+ if (htab->elf.sgotplt != NULL -+ && h->got.offset != (bfd_vma) -1) -+ offp = &h->got.offset; -+ else -+ abort (); -+ } -+ else -+ { -+ if (local_got_offsets == NULL) -+ abort (); -+ offp = &local_got_offsets[r_symndx]; -+ } -+ -+ if (!offp) -+ abort (); -+ -+ off = (*offp) & ~1; -+ off2 = off; -+ -+ if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type)) -+ off2 = off + 4; -+ -+ /* Symbol index to use for relocs */ -+ if (h != NULL) -+ { -+ bool dyn = -+ elf_hash_table (info)->dynamic_sections_created; -+ -+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, -+ bfd_link_pic (info), -+ h) -+ && (!bfd_link_pic (info) -+ || !SYMBOL_REFERENCES_LOCAL (info, h))) -+ indx = h->dynindx; -+ } -+ -+ /* Need to generate relocs ? */ -+ if ((bfd_link_pic (info) || indx != 0) -+ && (h == NULL -+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT -+ || h->root.type != bfd_link_hash_undefweak)) -+ need_relocs = true; -+ -+ /* 2. Compute/Emit Static value of r-expression */ -+ static_value = relocation + addend; -+ -+ /* 3. Process module-id and offset */ -+ if (! ((*offp) & 1) ) -+ { -+ bfd_vma got_offset; -+ -+ got_offset = (htab->elf.sgot->output_section->vma -+ + htab->elf.sgot->output_offset -+ + off); -+ -+ /* Process module-id */ -+ if (IS_TLS_LD(tls_type)) -+ { -+ if (! bfd_link_pic (info)) -+ bfd_put_32 (output_bfd, 1, -+ htab->elf.sgot->contents + off); -+ else -+ microblaze_elf_output_dynamic_relocation -+ (output_bfd, -+ htab->elf.srelgot, -+ htab->elf.srelgot->reloc_count++, -+ /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32, -+ got_offset, 0); -+ } -+ else if (IS_TLS_GD(tls_type)) -+ { -+ if (! need_relocs) -+ bfd_put_32 (output_bfd, 1, -+ htab->elf.sgot->contents + off); -+ else -+ microblaze_elf_output_dynamic_relocation -+ (output_bfd, -+ htab->elf.srelgot, -+ htab->elf.srelgot->reloc_count++, -+ /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32, -+ got_offset, indx ? 0 : static_value); -+ } -+ -+ /* Process Offset */ -+ if (htab->elf.srelgot == NULL) -+ abort (); -+ -+ got_offset = (htab->elf.sgot->output_section->vma -+ + htab->elf.sgot->output_offset -+ + off2); -+ if (IS_TLS_LD(tls_type)) -+ { -+ /* For LD, offset should be 0 */ -+ *offp |= 1; -+ bfd_put_32 (output_bfd, 0, -+ htab->elf.sgot->contents + off2); -+ } -+ else if (IS_TLS_GD(tls_type)) -+ { -+ *offp |= 1; -+ static_value -= dtprel_base(info); -+ if (need_relocs) -+ microblaze_elf_output_dynamic_relocation -+ (output_bfd, -+ htab->elf.srelgot, -+ htab->elf.srelgot->reloc_count++, -+ /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32, -+ got_offset, indx ? 0 : static_value); -+ else -+ bfd_put_32 (output_bfd, static_value, -+ htab->elf.sgot->contents + off2); -+ } -+ else -+ { -+ bfd_put_32 (output_bfd, static_value, -+ htab->elf.sgot->contents + off2); -+ -+ /* Relocs for dyn symbols generated by -+ finish_dynamic_symbols */ -+ if (bfd_link_pic (info) && h == NULL) -+ { -+ *offp |= 1; -+ microblaze_elf_output_dynamic_relocation -+ (output_bfd, -+ htab->elf.srelgot, -+ htab->elf.srelgot->reloc_count++, -+ /* symindex= */ indx, R_MICROBLAZE_REL, -+ got_offset, static_value); -+ } -+ } -+ } -+ -+ /* 4. Fixup Relocation with GOT offset value -+ Compute relative address of GOT entry for applying -+ the current relocation */ -+ relocation = htab->elf.sgot->output_section->vma -+ + htab->elf.sgot->output_offset -+ + off -+ - htab->elf.sgotplt->output_section->vma -+ - htab->elf.sgotplt->output_offset; -+ -+ /* Apply Current Relocation */ -+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ -+ unresolved_reloc = false; -+ break; -+ } -+ -+ case (int) R_MICROBLAZE_GOTOFF_64: -+ { -+ bfd_vma immediate; -+ unsigned short lo, high; -+ relocation += addend; -+ relocation -= (htab->elf.sgotplt->output_section->vma -+ + htab->elf.sgotplt->output_offset); -+ /* Write this value into correct location. */ -+ immediate = relocation; -+ lo = immediate & 0x0000ffff; -+ high = (immediate >> 16) & 0x0000ffff; -+ bfd_put_16 (input_bfd, high, contents + offset + endian); -+ bfd_put_16 (input_bfd, lo, -+ contents + offset + INST_WORD_SIZE + endian); -+ break; -+ } -+ -+ case (int) R_MICROBLAZE_GOTOFF_32: -+ { -+ relocation += addend; -+ relocation -= (htab->elf.sgotplt->output_section->vma -+ + htab->elf.sgotplt->output_offset); -+ /* Write this value into correct location. */ -+ bfd_put_32 (input_bfd, relocation, contents + offset); -+ break; -+ } -+ -+ case (int) R_MICROBLAZE_TLSDTPREL64: -+ relocation += addend; -+ relocation -= dtprel_base(info); -+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ break; -+ case (int) R_MICROBLAZE_TEXTREL_64: -+ case (int) R_MICROBLAZE_TEXTREL_32_LO: -+ case (int) R_MICROBLAZE_64_PCREL : -+ case (int) R_MICROBLAZE_64: -+ case (int) R_MICROBLAZE_32: -+ case (int) R_MICROBLAZE_IMML_64: -+ { -+ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols -+ from removed linkonce sections, or sections discarded by -+ a linker script. */ -+ if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) -+ { -+ relocation += addend; -+ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) -+ bfd_put_32 (input_bfd, relocation, contents + offset); -+ else if (r_type == R_MICROBLAZE_IMML_64) -+ bfd_put_64 (input_bfd, relocation, contents + offset); -+ else -+ { -+ if (r_type == R_MICROBLAZE_64_PCREL) -+ relocation -= (input_section->output_section->vma -+ + input_section->output_offset -+ + offset + INST_WORD_SIZE); -+ else if (r_type == R_MICROBLAZE_TEXTREL_64 -+ || r_type == R_MICROBLAZE_TEXTREL_32_LO) -+ relocation -= input_section->output_section->vma; -+ -+ if (r_type == R_MICROBLAZE_TEXTREL_32_LO) -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian); -+ -+ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); -+ if ((insn & 0xff000000) == 0xb2000000) -+ { -+ insn &= ~0x00ffffff; -+ insn |= (relocation >> 16) & 0xffffff; -+ bfd_put_32 (input_bfd, insn, -+ contents + offset + endian); -+ } -+ else -+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ } -+ break; -+ } -+ -+ if ((bfd_link_pic (info) -+ && (h == NULL -+ || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT -+ && !resolved_to_zero) -+ || h->root.type != bfd_link_hash_undefweak) -+ && (!howto->pc_relative -+ || (h != NULL -+ && h->dynindx != -1 -+ && (!info->symbolic -+ || !h->def_regular)))) -+ || (!bfd_link_pic (info) -+ && h != NULL -+ && h->dynindx != -1 -+ && !h->non_got_ref -+ && ((h->def_dynamic -+ && !h->def_regular) -+ || h->root.type == bfd_link_hash_undefweak -+ || h->root.type == bfd_link_hash_undefined))) -+ { -+ Elf_Internal_Rela outrel; -+ bfd_byte *loc; -+ bool skip; -+ -+ /* When generating a shared object, these relocations -+ are copied into the output file to be resolved at run -+ time. */ -+ -+ BFD_ASSERT (sreloc != NULL); -+ -+ skip = false; -+ -+ outrel.r_offset = -+ _bfd_elf_section_offset (output_bfd, info, input_section, -+ rel->r_offset); -+ if (outrel.r_offset == (bfd_vma) -1) -+ skip = true; -+ else if (outrel.r_offset == (bfd_vma) -2) -+ skip = true; -+ outrel.r_offset += (input_section->output_section->vma -+ + input_section->output_offset); -+ -+ if (skip) -+ memset (&outrel, 0, sizeof outrel); -+ /* h->dynindx may be -1 if the symbol was marked to -+ become local. */ -+ else if (h != NULL -+ && ((! info->symbolic && h->dynindx != -1) -+ || !h->def_regular)) -+ { -+ BFD_ASSERT (h->dynindx != -1); -+ outrel.r_info = ELF64_R_INFO (h->dynindx, r_type); -+ outrel.r_addend = addend; -+ } -+ else -+ { -+ if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64) -+ { -+ outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); -+ outrel.r_addend = relocation + addend; -+ } -+ else -+ { -+ BFD_FAIL (); -+ _bfd_error_handler -+ (_("%pB: probably compiled without -fPIC?"), -+ input_bfd); -+ bfd_set_error (bfd_error_bad_value); -+ return false; -+ } -+ } -+ -+ loc = sreloc->contents; -+ loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela); -+ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc); -+ break; -+ } -+ else -+ { -+ relocation += addend; -+ if (r_type == R_MICROBLAZE_32) -+ bfd_put_32 (input_bfd, relocation, contents + offset); -+ else if (r_type == R_MICROBLAZE_IMML_64) -+ bfd_put_64 (input_bfd, relocation, contents + offset + endian); -+ else -+ { -+ if (r_type == R_MICROBLAZE_64_PCREL) -+ { -+ if (!input_section->output_section->vma && -+ !input_section->output_offset && !offset) -+ relocation -= (input_section->output_section->vma -+ + input_section->output_offset -+ + offset); -+ else -+ relocation -= (input_section->output_section->vma -+ + input_section->output_offset + offset + INST_WORD_SIZE); -+ } -+ else if (r_type == R_MICROBLAZE_TEXTREL_64 -+ || r_type == R_MICROBLAZE_TEXTREL_32_LO) -+ relocation -= input_section->output_section->vma; -+ -+ if (r_type == R_MICROBLAZE_TEXTREL_32_LO) -+ { -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian); -+ } -+ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); -+ if ((insn & 0xff000000) == 0xb2000000) -+ { -+ insn &= ~0x00ffffff; -+ insn |= (relocation >> 16) & 0xffffff; -+ bfd_put_32 (input_bfd, insn, -+ contents + offset + endian); -+ } -+ else -+ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, -+ contents + offset + endian); -+ bfd_put_16 (input_bfd, relocation & 0xffff, -+ contents + offset + endian + INST_WORD_SIZE); -+ } -+ break; -+ } -+ } -+ -+ default : -+ r = _bfd_final_link_relocate (howto, input_bfd, input_section, -+ contents, offset, -+ relocation, addend); -+ break; -+ } -+ } -+ -+ check_reloc: -+ -+ if (r != bfd_reloc_ok) -+ { -+ /* FIXME: This should be generic enough to go in a utility. */ -+ const char *name; -+ -+ if (h != NULL) -+ name = h->root.root.string; -+ else -+ { -+ name = (bfd_elf_string_from_elf_section -+ (input_bfd, symtab_hdr->sh_link, sym->st_name)); -+ if (name == NULL || *name == '\0') -+ name = bfd_section_name (sec); -+ } -+ -+ if (errmsg != NULL) -+ goto common_error; -+ -+ switch (r) -+ { -+ case bfd_reloc_overflow: -+ (*info->callbacks->reloc_overflow) -+ (info, (h ? &h->root : NULL), name, howto->name, -+ (bfd_vma) 0, input_bfd, input_section, offset); -+ break; -+ -+ case bfd_reloc_undefined: -+ (*info->callbacks->undefined_symbol) -+ (info, name, input_bfd, input_section, offset, true); -+ break; -+ -+ case bfd_reloc_outofrange: -+ errmsg = _("internal error: out of range error"); -+ goto common_error; -+ -+ case bfd_reloc_notsupported: -+ errmsg = _("internal error: unsupported relocation error"); -+ goto common_error; -+ -+ case bfd_reloc_dangerous: -+ errmsg = _("internal error: dangerous error"); -+ goto common_error; -+ -+ default: -+ errmsg = _("internal error: unknown error"); -+ /* Fall through. */ -+ common_error: -+ (*info->callbacks->warning) (info, errmsg, name, input_bfd, -+ input_section, offset); -+ break; -+ } -+ } -+ } -+ -+ return ret; -+} -+ -+/* Merge backend specific data from an object file to the output -+ object file when linking. -+ -+ Note: We only use this hook to catch endian mismatches. */ -+static bool -+microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) -+{ -+ /* Check if we have the same endianess. */ -+ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) -+ return false; -+ -+ return true; -+} -+ -+ -+/* Calculate fixup value for reference. */ -+ -+static size_t -+calc_fixup (bfd_vma start, bfd_vma size, asection *sec) -+{ -+ bfd_vma end = start + size; -+ size_t i, fixup = 0; -+ struct _microblaze_elf_section_data *sdata; -+ -+ if (sec == NULL || (sdata = microblaze_elf_section_data (sec)) == NULL) -+ return 0; -+ -+ /* Look for addr in relax table, total fixup value. */ -+ for (i = 0; i < sdata->relax_count; i++) -+ { -+ if (end <= sdata->relax[i].addr) -+ break; -+ if (end != start && start > sdata->relax[i].addr) -+ continue; -+ fixup += sdata->relax[i].size; -+ } -+ return fixup; -+} -+ -+/* Read-modify-write into the bfd, an immediate value into appropriate fields of -+ a 32-bit instruction. */ -+static void -+microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) -+{ -+ unsigned long instr = bfd_get_32 (abfd, bfd_addr); -+ -+ if ((instr & 0xff000000) == 0xb2000000) -+ { -+ instr &= ~0x00ffffff; -+ instr |= (val & 0xffffff); -+ bfd_put_32 (abfd, instr, bfd_addr); -+ } -+ else -+ { -+ instr &= ~0x0000ffff; -+ instr |= (val & 0x0000ffff); -+ bfd_put_32 (abfd, instr, bfd_addr); -+ } -+} -+ -+/* Read-modify-write into the bfd, an immediate value into appropriate fields of -+ two consecutive 32-bit instructions. */ -+static void -+microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) -+{ -+ unsigned long instr_hi; -+ unsigned long instr_lo; -+ -+ instr_hi = bfd_get_32 (abfd, bfd_addr); -+ if ((instr_hi & 0xff000000) == 0xb2000000) -+ { -+ instr_hi &= ~0x00ffffff; -+ instr_hi |= (val >> 16) & 0xffffff; -+ bfd_put_32 (abfd, instr_hi,bfd_addr); -+ } -+ else -+ { -+ instr_hi &= ~0x0000ffff; -+ instr_hi |= ((val >> 16) & 0x0000ffff); -+ bfd_put_32 (abfd, instr_hi, bfd_addr); -+ } -+ instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE); -+ instr_lo &= ~0x0000ffff; -+ instr_lo |= (val & 0x0000ffff); -+ bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE); -+} -+ -+static bool -+microblaze_elf_relax_section (bfd *abfd, -+ asection *sec, -+ struct bfd_link_info *link_info, -+ bool *again) -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Rela *internal_relocs; -+ Elf_Internal_Rela *irel, *irelend; -+ bfd_byte *contents = NULL; -+ int rel_count; -+ unsigned int shndx; -+ size_t i, sym_index; -+ asection *o; -+ struct elf_link_hash_entry *sym_hash; -+ Elf_Internal_Sym *isymbuf, *isymend; -+ Elf_Internal_Sym *isym; -+ size_t symcount; -+ size_t offset; -+ bfd_vma src, dest; -+ struct _microblaze_elf_section_data *sdata; -+ -+ /* We only do this once per section. We may be able to delete some code -+ by running multiple passes, but it is not worth it. */ -+ *again = false; -+ -+ /* Only do this for a text section. */ -+ if (bfd_link_relocatable (link_info) -+ || (sec->flags & SEC_RELOC) == 0 -+ || (sec->flags & SEC_CODE) == 0 -+ || sec->reloc_count == 0 -+ || (sdata = microblaze_elf_section_data (sec)) == NULL) -+ return true; -+ -+ BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0)); -+ -+ /* If this is the first time we have been called for this section, -+ initialize the cooked size. */ -+ if (sec->size == 0) -+ sec->size = sec->rawsize; -+ -+ /* Get symbols for this section. */ -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; -+ symcount = symtab_hdr->sh_size / sizeof (Elf64_External_Sym); -+ if (isymbuf == NULL) -+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount, -+ 0, NULL, NULL, NULL); -+ BFD_ASSERT (isymbuf != NULL); -+ -+ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); -+ if (internal_relocs == NULL) -+ goto error_return; -+ -+ sdata->relax_count = 0; -+ sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) -+ * sizeof (*sdata->relax)); -+ if (sdata->relax == NULL) -+ goto error_return; -+ -+ irelend = internal_relocs + sec->reloc_count; -+ rel_count = 0; -+ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) -+ { -+ bfd_vma symval; -+ if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL) -+ && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ) -+&& (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_TEXTREL_64)) -+ continue; /* Can't delete this reloc. */ -+ -+ /* Get the section contents. */ -+ if (contents == NULL) -+ { -+ if (elf_section_data (sec)->this_hdr.contents != NULL) -+ contents = elf_section_data (sec)->this_hdr.contents; -+ else -+ { -+ contents = (bfd_byte *) bfd_malloc (sec->size); -+ if (contents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, sec, contents, -+ (file_ptr) 0, sec->size)) -+ goto error_return; -+ elf_section_data (sec)->this_hdr.contents = contents; -+ } -+ } -+ -+ /* Get the value of the symbol referred to by the reloc. */ -+ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) -+ { -+ /* A local symbol. */ -+ asection *sym_sec; -+ -+ isym = isymbuf + ELF64_R_SYM (irel->r_info); -+ if (isym->st_shndx == SHN_UNDEF) -+ sym_sec = bfd_und_section_ptr; -+ else if (isym->st_shndx == SHN_ABS) -+ sym_sec = bfd_abs_section_ptr; -+ else if (isym->st_shndx == SHN_COMMON) -+ sym_sec = bfd_com_section_ptr; -+ else -+ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); -+ -+ symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel); -+ } -+ else -+ { -+ unsigned long indx; -+ struct elf_link_hash_entry *h; -+ -+ indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info; -+ h = elf_sym_hashes (abfd)[indx]; -+ BFD_ASSERT (h != NULL); -+ -+ if (h->root.type != bfd_link_hash_defined -+ && h->root.type != bfd_link_hash_defweak) -+ /* This appears to be a reference to an undefined -+ symbol. Just ignore it--it will be caught by the -+ regular reloc processing. */ -+ continue; -+ -+ symval = (h->root.u.def.value -+ + h->root.u.def.section->output_section->vma -+ + h->root.u.def.section->output_offset); -+ } -+ -+ /* If this is a PC-relative reloc, subtract the instr offset from -+ the symbol value. */ -+ if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL) -+ { -+ symval = symval + irel->r_addend -+ - (irel->r_offset -+ + sec->output_section->vma -+ + sec->output_offset); -+ } -+ else if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_TEXTREL_64) -+ { -+ symval = symval + irel->r_addend - (sec->output_section->vma); -+ } -+ else -+ symval += irel->r_addend; -+ -+ if ((symval & 0xffff8000) == 0 -+ || (symval & 0xffff8000) == 0xffff8000) -+ { -+ /* We can delete this instruction. */ -+ sdata->relax[sdata->relax_count].addr = irel->r_offset; -+ sdata->relax[sdata->relax_count].size = INST_WORD_SIZE; -+ sdata->relax_count++; -+ -+ /* Rewrite relocation type. */ -+ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) -+ { -+ case R_MICROBLAZE_64_PCREL: -+ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), -+ (int) R_MICROBLAZE_32_PCREL_LO); -+ break; -+ case R_MICROBLAZE_64: -+ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), -+ (int) R_MICROBLAZE_32_LO); -+ break; -+ case R_MICROBLAZE_TEXTREL_64: -+ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), -+ (int) R_MICROBLAZE_TEXTREL_32_LO); -+ break; -+ default: -+ /* Cannot happen. */ -+ BFD_ASSERT (false); -+ } -+ } -+ } /* Loop through all relocations. */ -+ -+ /* Loop through the relocs again, and see if anything needs to change. */ -+ if (sdata->relax_count > 0) -+ { -+ shndx = _bfd_elf_section_from_bfd_section (abfd, sec); -+ rel_count = 0; -+ sdata->relax[sdata->relax_count].addr = sec->size; -+ -+ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) -+ { -+ bfd_vma nraddr; -+ -+ /* Get the new reloc address. */ -+ nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec); -+ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) -+ { -+ default: -+ break; -+ case R_MICROBLAZE_64_PCREL: -+ break; -+ case R_MICROBLAZE_64: -+ case R_MICROBLAZE_32_LO: -+ /* If this reloc is against a symbol defined in this -+ section, we must check the addend to see it will put the value in -+ range to be adjusted, and hence must be changed. */ -+ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) -+ { -+ isym = isymbuf + ELF64_R_SYM (irel->r_info); -+ /* Only handle relocs against .text. */ -+ if (isym->st_shndx == shndx -+ && ELF64_ST_TYPE (isym->st_info) == STT_SECTION) -+ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); -+ } -+ break; -+ case R_MICROBLAZE_IMML_64: -+ { -+ /* This was a PC-relative instruction that was -+ completely resolved. */ -+ int sfix, efix; -+ unsigned int val; -+ bfd_vma target_address; -+ target_address = irel->r_addend + irel->r_offset; -+ sfix = calc_fixup (irel->r_offset, 0, sec); -+ efix = calc_fixup (target_address, 0, sec); -+ -+ /* Validate the in-band val. */ -+ val = bfd_get_64 (abfd, contents + irel->r_offset); -+ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { -+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); -+ } -+ irel->r_addend -= (efix - sfix); -+ /* Should use HOWTO. */ -+ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, -+ irel->r_addend); -+ } -+ break; -+ case R_MICROBLAZE_NONE: -+ case R_MICROBLAZE_32_NONE: -+ { -+ /* This was a PC-relative instruction that was -+ completely resolved. */ -+ size_t sfix, efix; -+ unsigned int val; -+ bfd_vma target_address; -+ target_address = irel->r_addend + irel->r_offset; -+ sfix = calc_fixup (irel->r_offset, 0, sec); -+ efix = calc_fixup (target_address, 0, sec); -+ -+ /* Validate the in-band val. */ -+ val = bfd_get_32 (abfd, contents + irel->r_offset); -+ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { -+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); -+ } -+ irel->r_addend -= (efix - sfix); -+ /* Should use HOWTO. */ -+ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, -+ irel->r_addend); -+ } -+ break; -+ case R_MICROBLAZE_64_NONE: -+ { -+ /* This was a PC-relative 64-bit instruction that was -+ completely resolved. */ -+ size_t sfix, efix; -+ bfd_vma target_address; -+ target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE; -+ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); -+ efix = calc_fixup (target_address, 0, sec); -+ irel->r_addend -= (efix - sfix); -+ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, -+ irel->r_addend); -+ } -+ break; -+ } -+ irel->r_offset = nraddr; -+ } /* Change all relocs in this section. */ -+ -+ /* Look through all other sections. */ -+ for (o = abfd->sections; o != NULL; o = o->next) -+ { -+ Elf_Internal_Rela *irelocs; -+ Elf_Internal_Rela *irelscan, *irelscanend; -+ bfd_byte *ocontents; -+ -+ if (o == sec -+ || (o->flags & SEC_RELOC) == 0 -+ || o->reloc_count == 0) -+ continue; -+ -+ /* We always cache the relocs. Perhaps, if info->keep_memory is -+ false, we should free them, if we are permitted to. */ -+ -+ irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, true); -+ if (irelocs == NULL) -+ goto error_return; -+ -+ ocontents = NULL; -+ irelscanend = irelocs + o->reloc_count; -+ for (irelscan = irelocs; irelscan < irelscanend; irelscan++) -+ { -+ if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) -+ { -+ unsigned int val; -+ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) -+ continue; -+ -+ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); -+ -+ /* hax: We only do the following fixup for debug location lists. */ -+ if (strcmp(".debug_loc", o->name)) -+ continue; -+ -+ /* This was a PC-relative instruction that was completely resolved. */ -+ if (ocontents == NULL) -+ { -+ if (elf_section_data (o)->this_hdr.contents != NULL) -+ ocontents = elf_section_data (o)->this_hdr.contents; -+ else -+ { -+ /* We always cache the section contents. -+ Perhaps, if info->keep_memory is false, we -+ should free them, if we are permitted to. */ -+ -+ if (o->rawsize == 0) -+ o->rawsize = o->size; -+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); -+ if (ocontents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, o, ocontents, -+ (file_ptr) 0, -+ o->rawsize)) -+ goto error_return; -+ elf_section_data (o)->this_hdr.contents = ocontents; -+ } -+ } -+ -+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); -+ if (val != irelscan->r_addend) { -+ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); -+ } -+ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); -+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, -+ irelscan->r_addend); -+ } -+ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32 -+ || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) -+ { -+ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) -+ continue; -+ -+ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); -+ -+ /* Look at the reloc only if the value has been resolved. */ -+ if (isym->st_shndx == shndx -+ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) -+ { -+ if (ocontents == NULL) -+ { -+ if (elf_section_data (o)->this_hdr.contents != NULL) -+ ocontents = elf_section_data (o)->this_hdr.contents; -+ else -+ { -+ /* We always cache the section contents. -+ Perhaps, if info->keep_memory is false, we -+ should free them, if we are permitted to. */ -+ if (o->rawsize == 0) -+ o->rawsize = o->size; -+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); -+ if (ocontents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, o, ocontents, -+ (file_ptr) 0, -+ o->rawsize)) -+ goto error_return; -+ elf_section_data (o)->this_hdr.contents = ocontents; -+ } -+ -+ } -+ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); -+ } -+ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) -+ { -+ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) -+ continue; -+ -+ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); -+ -+ /* Look at the reloc only if the value has been resolved. */ -+ if (ocontents == NULL) -+ { -+ if (elf_section_data (o)->this_hdr.contents != NULL) -+ ocontents = elf_section_data (o)->this_hdr.contents; -+ else -+ { -+ /* We always cache the section contents. -+ Perhaps, if info->keep_memory is false, we -+ should free them, if we are permitted to. */ -+ -+ if (o->rawsize == 0) -+ o->rawsize = o->size; -+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); -+ if (ocontents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, o, ocontents, -+ (file_ptr) 0, -+ o->rawsize)) -+ goto error_return; -+ elf_section_data (o)->this_hdr.contents = ocontents; -+ } -+ } -+ irelscan->r_addend -= calc_fixup (irelscan->r_addend -+ + isym->st_value, -+ 0, -+ sec); -+ } -+ } -+ else if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO) -+ || (ELF32_R_TYPE (irelscan->r_info) -+ == (int) R_MICROBLAZE_32_LO) -+ || (ELF32_R_TYPE (irelscan->r_info) -+ == (int) R_MICROBLAZE_TEXTREL_32_LO)) -+ { -+ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) -+ continue; -+ -+ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); -+ -+ /* Look at the reloc only if the value has been resolved. */ -+ if (isym->st_shndx == shndx -+ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) -+ { -+ bfd_vma immediate; -+ bfd_vma target_address; -+ -+ if (ocontents == NULL) -+ { -+ if (elf_section_data (o)->this_hdr.contents != NULL) -+ ocontents = elf_section_data (o)->this_hdr.contents; -+ else -+ { -+ /* We always cache the section contents. -+ Perhaps, if info->keep_memory is false, we -+ should free them, if we are permitted to. */ -+ if (o->rawsize == 0) -+ o->rawsize = o->size; -+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); -+ if (ocontents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, o, ocontents, -+ (file_ptr) 0, -+ o->rawsize)) -+ goto error_return; -+ elf_section_data (o)->this_hdr.contents = ocontents; -+ } -+ } -+ -+ unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset); -+ immediate = instr & 0x0000ffff; -+ target_address = immediate; -+ offset = calc_fixup (target_address, 0, sec); -+ immediate -= offset; -+ irelscan->r_addend -= offset; -+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, -+ irelscan->r_addend); -+ } -+ } -+ -+ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64 -+ || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_TEXTREL_64)) -+ { -+ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) -+ continue; -+ -+ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); -+ -+ /* Look at the reloc only if the value has been resolved. */ -+ if (isym->st_shndx == shndx -+ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) -+ { -+ bfd_vma immediate; -+ -+ if (ocontents == NULL) -+ { -+ if (elf_section_data (o)->this_hdr.contents != NULL) -+ ocontents = elf_section_data (o)->this_hdr.contents; -+ else -+ { -+ /* We always cache the section contents. -+ Perhaps, if info->keep_memory is false, we -+ should free them, if we are permitted to. */ -+ -+ if (o->rawsize == 0) -+ o->rawsize = o->size; -+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); -+ if (ocontents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, o, ocontents, -+ (file_ptr) 0, -+ o->rawsize)) -+ goto error_return; -+ elf_section_data (o)->this_hdr.contents = ocontents; -+ } -+ } -+ unsigned long instr_hi = bfd_get_32 (abfd, ocontents -+ + irelscan->r_offset); -+ unsigned long instr_lo = bfd_get_32 (abfd, ocontents -+ + irelscan->r_offset -+ + INST_WORD_SIZE); -+ if ((instr_hi & 0xff000000) == 0xb2000000) -+ immediate = (instr_hi & 0x00ffffff) << 24; -+ else -+ immediate = (instr_hi & 0x0000ffff) << 16; -+ immediate |= (instr_lo & 0x0000ffff); -+ offset = calc_fixup (irelscan->r_addend, 0, sec); -+ immediate -= offset; -+ irelscan->r_addend -= offset; -+ -+ } -+ } -+ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) -+ { -+ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) -+ continue; -+ -+ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); -+ -+ /* Look at the reloc only if the value has been resolved. */ -+ if (isym->st_shndx == shndx -+ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) -+ { -+ bfd_vma immediate; -+ bfd_vma target_address; -+ -+ if (ocontents == NULL) -+ { -+ if (elf_section_data (o)->this_hdr.contents != NULL) -+ ocontents = elf_section_data (o)->this_hdr.contents; -+ else -+ { -+ /* We always cache the section contents. -+ Perhaps, if info->keep_memory is false, we -+ should free them, if we are permitted to. */ -+ if (o->rawsize == 0) -+ o->rawsize = o->size; -+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); -+ if (ocontents == NULL) -+ goto error_return; -+ if (!bfd_get_section_contents (abfd, o, ocontents, -+ (file_ptr) 0, -+ o->rawsize)) -+ goto error_return; -+ elf_section_data (o)->this_hdr.contents = ocontents; -+ } -+ } -+ unsigned long instr_hi = bfd_get_32 (abfd, ocontents -+ + irelscan->r_offset); -+ unsigned long instr_lo = bfd_get_32 (abfd, ocontents -+ + irelscan->r_offset -+ + INST_WORD_SIZE); -+ if ((instr_hi & 0xff000000) == 0xb2000000) -+ immediate = (instr_hi & 0x00ffffff) << 24; -+ else -+ immediate = (instr_hi & 0x0000ffff) << 16; -+ immediate |= (instr_lo & 0x0000ffff); -+ target_address = immediate; -+ offset = calc_fixup (target_address, 0, sec); -+ immediate -= offset; -+ irelscan->r_addend -= offset; -+ microblaze_bfd_write_imm_value_64 (abfd, ocontents -+ + irelscan->r_offset, immediate); -+ } -+ } -+ } -+ } -+ -+ /* Adjust the local symbols defined in this section. */ -+ isymend = isymbuf + symtab_hdr->sh_info; -+ for (isym = isymbuf; isym < isymend; isym++) -+ { -+ if (isym->st_shndx == shndx) -+ { -+ isym->st_value -= calc_fixup (isym->st_value, 0, sec); -+ if (isym->st_size) -+ isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec); -+ } -+ } -+ -+ /* Now adjust the global symbols defined in this section. */ -+ isym = isymbuf + symtab_hdr->sh_info; -+ symcount = (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info; -+ for (sym_index = 0; sym_index < symcount; sym_index++) -+ { -+ sym_hash = elf_sym_hashes (abfd)[sym_index]; -+ if ((sym_hash->root.type == bfd_link_hash_defined -+ || sym_hash->root.type == bfd_link_hash_defweak) -+ && sym_hash->root.u.def.section == sec) -+ { -+ sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value, -+ 0, sec); -+ if (sym_hash->size) -+ sym_hash->size -= calc_fixup (sym_hash->root.u.def.value, -+ sym_hash->size, sec); -+ } -+ } -+ -+ /* Physically move the code and change the cooked size. */ -+ dest = sdata->relax[0].addr; -+ for (i = 0; i < sdata->relax_count; i++) -+ { -+ size_t len; -+ src = sdata->relax[i].addr + sdata->relax[i].size; -+ len = (sdata->relax[i+1].addr - sdata->relax[i].addr -+ - sdata->relax[i].size); -+ -+ memmove (contents + dest, contents + src, len); -+ sec->size -= sdata->relax[i].size; -+ dest += len; -+ } -+ -+ elf_section_data (sec)->relocs = internal_relocs; -+ -+ elf_section_data (sec)->this_hdr.contents = contents; -+ -+ symtab_hdr->contents = (bfd_byte *) isymbuf; -+ } -+ -+ if (internal_relocs != NULL -+ && elf_section_data (sec)->relocs != internal_relocs) -+ free (internal_relocs); -+ -+ if (contents != NULL -+ && elf_section_data (sec)->this_hdr.contents != contents) -+ { -+ if (! link_info->keep_memory) -+ free (contents); -+ else -+ { -+ /* Cache the section contents for elf_link_input_bfd. */ -+ elf_section_data (sec)->this_hdr.contents = contents; -+ } -+ } -+ -+ if (sdata->relax_count == 0) -+ { -+ *again = false; -+ free (sdata->relax); -+ sdata->relax = NULL; -+ } -+ else -+ *again = true; -+ return true; -+ -+ error_return: -+ if (isymbuf != NULL -+ && symtab_hdr->contents != (unsigned char *) isymbuf) -+ free (isymbuf); -+ if (internal_relocs != NULL -+ && elf_section_data (sec)->relocs != internal_relocs) -+ free (internal_relocs); -+ if (contents != NULL -+ && elf_section_data (sec)->this_hdr.contents != contents) -+ free (contents); -+ free (sdata->relax); -+ sdata->relax = NULL; -+ sdata->relax_count = 0; -+ return false; -+} -+ -+/* Return the section that should be marked against GC for a given -+ relocation. */ -+ -+static asection * -+microblaze_elf_gc_mark_hook (asection *sec, -+ struct bfd_link_info * info, -+ Elf_Internal_Rela * rel, -+ struct elf_link_hash_entry * h, -+ Elf_Internal_Sym * sym) -+{ -+ if (h != NULL) -+ switch (ELF64_R_TYPE (rel->r_info)) -+ { -+ case R_MICROBLAZE_GNU_VTINHERIT: -+ case R_MICROBLAZE_GNU_VTENTRY: -+ return NULL; -+ } -+ -+ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); -+} -+ -+/* Update the got entry reference counts for the section being removed. */ -+ -+static bool -+microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info * info ATTRIBUTE_UNUSED, -+ asection * sec ATTRIBUTE_UNUSED, -+ const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) -+{ -+ return true; -+} -+ -+/* PIC support. */ -+ -+#define PLT_ENTRY_SIZE 16 -+ -+#define PLT_ENTRY_WORD_0 0xb0000000 /* "imm 0". */ -+#define PLT_ENTRY_WORD_1 0xe9940000 /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT. */ -+#define PLT_ENTRY_WORD_1_NOPIC 0xe9800000 /* "lwi r12,r0,0" - non-PIC object. */ -+#define PLT_ENTRY_WORD_2 0x98186000 /* "brad r12". */ -+#define PLT_ENTRY_WORD_3 0x80000000 /* "nop". */ -+ -+/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up -+ shortcuts to them in our hash table. */ -+ -+static bool -+update_local_sym_info (bfd *abfd, -+ Elf_Internal_Shdr *symtab_hdr, -+ unsigned long r_symndx, -+ unsigned int tls_type) -+{ -+ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd); -+ unsigned char *local_got_tls_masks; -+ -+ if (local_got_refcounts == NULL) -+ { -+ bfd_size_type size = symtab_hdr->sh_info; -+ -+ size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks)); -+ local_got_refcounts = bfd_zalloc (abfd, size); -+ if (local_got_refcounts == NULL) -+ return false; -+ elf_local_got_refcounts (abfd) = local_got_refcounts; -+ } -+ -+ local_got_tls_masks = -+ (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info); -+ local_got_tls_masks[r_symndx] |= tls_type; -+ local_got_refcounts[r_symndx] += 1; -+ -+ return true; -+} -+/* Look through the relocs for a section during the first phase. */ -+ -+static bool -+microblaze_elf_check_relocs (bfd * abfd, -+ struct bfd_link_info * info, -+ asection * sec, -+ const Elf_Internal_Rela * relocs) -+{ -+ Elf_Internal_Shdr * symtab_hdr; -+ struct elf_link_hash_entry ** sym_hashes; -+ struct elf_link_hash_entry ** sym_hashes_end; -+ const Elf_Internal_Rela * rel; -+ const Elf_Internal_Rela * rel_end; -+ struct elf64_mb_link_hash_table *htab; -+ asection *sreloc = NULL; -+ -+ if (bfd_link_relocatable (info)) -+ return true; -+ -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ symtab_hdr = & elf_tdata (abfd)->symtab_hdr; -+ sym_hashes = elf_sym_hashes (abfd); -+ sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym); -+ if (!elf_bad_symtab (abfd)) -+ sym_hashes_end -= symtab_hdr->sh_info; -+ -+ rel_end = relocs + sec->reloc_count; -+ -+ for (rel = relocs; rel < rel_end; rel++) -+ { -+ unsigned int r_type; -+ struct elf_link_hash_entry * h; -+ unsigned long r_symndx; -+ unsigned char tls_type = 0; -+ -+ r_symndx = ELF64_R_SYM (rel->r_info); -+ r_type = ELF64_R_TYPE (rel->r_info); -+ -+ if (r_symndx < symtab_hdr->sh_info) -+ h = NULL; -+ else -+ { -+ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ /* PR15323, ref flags aren't set for references in the same -+ object. */ -+ h->root.non_ir_ref_regular = 1; -+ } -+ -+ switch (r_type) -+ { -+ /* This relocation describes the C++ object vtable hierarchy. -+ Reconstruct it for later use during GC. */ -+ case R_MICROBLAZE_GNU_VTINHERIT: -+ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) -+ return false; -+ break; -+ -+ /* This relocation describes which C++ vtable entries are actually -+ used. Record for later use during GC. */ -+ case R_MICROBLAZE_GNU_VTENTRY: -+ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) -+ return false; -+ break; -+ -+ /* This relocation requires .plt entry. */ -+ case R_MICROBLAZE_PLT_64: -+ if (h != NULL) -+ { -+ h->needs_plt = 1; -+ h->plt.refcount += 1; -+ } -+ break; -+ -+ /* This relocation requires .got entry. */ -+ case R_MICROBLAZE_TLSGD: -+ tls_type |= (TLS_TLS | TLS_GD); -+ goto dogottls; -+ case R_MICROBLAZE_TLSLD: -+ tls_type |= (TLS_TLS | TLS_LD); -+ /* Fall through. */ -+ dogottls: -+ sec->has_tls_reloc = 1; -+ /* Fall through. */ -+ case R_MICROBLAZE_GOT_64: -+ if (htab->elf.sgot == NULL) -+ { -+ if (htab->elf.dynobj == NULL) -+ htab->elf.dynobj = abfd; -+ if (!_bfd_elf_create_got_section (htab->elf.dynobj, info)) -+ return false; -+ } -+ if (h != NULL) -+ { -+ h->got.refcount += 1; -+ elf64_mb_hash_entry (h)->tls_mask |= tls_type; -+ } -+ else -+ { -+ if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) ) -+ return false; -+ } -+ break; -+ -+ case R_MICROBLAZE_GOTOFF_64: -+ case R_MICROBLAZE_GOTOFF_32: -+ if (htab->elf.sgot == NULL) -+ { -+ if (htab->elf.dynobj == NULL) -+ htab->elf.dynobj = abfd; -+ if (!_bfd_elf_create_got_section (htab->elf.dynobj, info)) -+ return false; -+ } -+ break; -+ -+ case R_MICROBLAZE_64: -+ case R_MICROBLAZE_64_PCREL: -+ case R_MICROBLAZE_32: -+ case R_MICROBLAZE_IMML_64: -+ { -+ if (h != NULL && !bfd_link_pic (info)) -+ { -+ /* we may need a copy reloc. */ -+ h->non_got_ref = 1; -+ -+ /* we may also need a .plt entry. */ -+ h->plt.refcount += 1; -+ if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL) -+ h->pointer_equality_needed = 1; -+ } -+ -+ -+ /* If we are creating a shared library, and this is a reloc -+ against a global symbol, or a non PC relative reloc -+ against a local symbol, then we need to copy the reloc -+ into the shared library. However, if we are linking with -+ -Bsymbolic, we do not need to copy a reloc against a -+ global symbol which is defined in an object we are -+ including in the link (i.e., DEF_REGULAR is set). At -+ this point we have not seen all the input files, so it is -+ possible that DEF_REGULAR is not set now but will be set -+ later (it is never cleared). In case of a weak definition, -+ DEF_REGULAR may be cleared later by a strong definition in -+ a shared library. We account for that possibility below by -+ storing information in the relocs_copied field of the hash -+ table entry. A similar situation occurs when creating -+ shared libraries and symbol visibility changes render the -+ symbol local. -+ -+ If on the other hand, we are creating an executable, we -+ may need to keep relocations for symbols satisfied by a -+ dynamic library if we manage to avoid copy relocs for the -+ symbol. */ -+ -+ if ((bfd_link_pic (info) -+ && (sec->flags & SEC_ALLOC) != 0 -+ && (r_type != R_MICROBLAZE_64_PCREL -+ || (h != NULL -+ && (! info->symbolic -+ || h->root.type == bfd_link_hash_defweak -+ || !h->def_regular)))) -+ || (!bfd_link_pic (info) -+ && (sec->flags & SEC_ALLOC) != 0 -+ && h != NULL -+ && (h->root.type == bfd_link_hash_defweak -+ || !h->def_regular))) -+ { -+ struct elf64_mb_dyn_relocs *p; -+ struct elf64_mb_dyn_relocs **head; -+ -+ /* When creating a shared object, we must copy these -+ relocs into the output file. We create a reloc -+ section in dynobj and make room for the reloc. */ -+ -+ if (sreloc == NULL) -+ { -+ bfd *dynobj; -+ -+ if (htab->elf.dynobj == NULL) -+ htab->elf.dynobj = abfd; -+ dynobj = htab->elf.dynobj; -+ -+ sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, -+ 2, abfd, 1); -+ if (sreloc == NULL) -+ return false; -+ } -+ -+ /* If this is a global symbol, we count the number of -+ relocations we need for this symbol. */ -+ if (h != NULL) -+ head = &h->dyn_relocs; -+ else -+ { -+ /* Track dynamic relocs needed for local syms too. -+ We really need local syms available to do this -+ easily. Oh well. */ -+ -+ asection *s; -+ Elf_Internal_Sym *isym; -+ void *vpp; -+ -+ isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, -+ abfd, r_symndx); -+ if (isym == NULL) -+ return false; -+ -+ s = bfd_section_from_elf_index (abfd, isym->st_shndx); -+ if (s == NULL) -+ return false; -+ -+ vpp = &elf_section_data (s)->local_dynrel; -+ head = (struct elf64_mb_dyn_relocs **) vpp; -+ } -+ -+ p = *head; -+ if (p == NULL || p->sec != sec) -+ { -+ size_t amt = sizeof *p; -+ p = ((struct elf64_mb_dyn_relocs *) -+ bfd_alloc (htab->elf.dynobj, amt)); -+ if (p == NULL) -+ return false; -+ p->next = *head; -+ *head = p; -+ p->sec = sec; -+ p->count = 0; -+ p->pc_count = 0; -+ } -+ -+ p->count += 1; -+ if (r_type == R_MICROBLAZE_64_PCREL) -+ p->pc_count += 1; -+ } -+ } -+ break; -+ } -+ } -+ -+ return true; -+} -+ -+static bool -+microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) -+{ -+ struct elf64_mb_link_hash_table *htab; -+ -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ if (!htab->sgot && !_bfd_elf_create_got_section (dynobj, info)) -+ return false; -+ -+ if (!_bfd_elf_create_dynamic_sections (dynobj, info)) -+ return false; -+ -+ htab->splt = bfd_get_linker_section (dynobj, ".plt"); -+ htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt"); -+ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss"); -+ if (!bfd_link_pic (info)) -+ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss"); -+ -+ if (!htab->splt || !htab->srelplt || !htab->sdynbss -+ || (!bfd_link_pic (info) && !htab->srelbss)) -+ abort (); -+ -+ return true; -+} -+ -+/* Copy the extra info we tack onto an elf_link_hash_entry. */ -+ -+static void -+microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info, -+ struct elf_link_hash_entry *dir, -+ struct elf_link_hash_entry *ind) -+{ -+ struct elf64_mb_link_hash_entry *edir, *eind; -+ -+ edir = (struct elf64_mb_link_hash_entry *) dir; -+ eind = (struct elf64_mb_link_hash_entry *) ind; -+ -+ if (eind->dyn_relocs != NULL) -+ { -+ if (edir->dyn_relocs != NULL) -+ { -+ struct elf64_mb_dyn_relocs **pp; -+ struct elf64_mb_dyn_relocs *p; -+ -+ if (ind->root.type == bfd_link_hash_indirect) -+ abort (); -+ -+ /* Add reloc counts against the weak sym to the strong sym -+ list. Merge any entries against the same section. */ -+ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) -+ { -+ struct elf64_mb_dyn_relocs *q; -+ -+ for (q = edir->dyn_relocs; q != NULL; q = q->next) -+ if (q->sec == p->sec) -+ { -+ q->pc_count += p->pc_count; -+ q->count += p->count; -+ *pp = p->next; -+ break; -+ } -+ if (q == NULL) -+ pp = &p->next; -+ } -+ *pp = edir->dyn_relocs; -+ } -+ -+ edir->dyn_relocs = eind->dyn_relocs; -+ eind->dyn_relocs = NULL; -+ } -+ -+ edir->tls_mask |= eind->tls_mask; -+ -+ _bfd_elf_link_hash_copy_indirect (info, dir, ind); -+} -+ -+static bool -+microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, -+ struct elf_link_hash_entry *h) -+{ -+ struct elf64_mb_link_hash_table *htab; -+ struct elf64_mb_link_hash_entry * eh; -+ struct elf64_mb_dyn_relocs *p; -+ asection *sdynbss; -+ asection *s, *srel; -+ unsigned int power_of_two; -+ bfd *dynobj; -+ -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ /* If this is a function, put it in the procedure linkage table. We -+ will fill in the contents of the procedure linkage table later, -+ when we know the address of the .got section. */ -+ if (h->type == STT_FUNC -+ || h->needs_plt) -+ { -+ if (h->plt.refcount <= 0 -+ || SYMBOL_CALLS_LOCAL (info, h) -+ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT -+ && h->root.type == bfd_link_hash_undefweak)) -+ { -+ /* This case can occur if we saw a PLT reloc in an input -+ file, but the symbol was never referred to by a dynamic -+ object, or if all references were garbage collected. In -+ such a case, we don't actually need to build a procedure -+ linkage table, and we can just do a PC32 reloc instead. */ -+ h->plt.offset = (bfd_vma) -1; -+ h->needs_plt = 0; -+ } -+ -+ return true; -+ } -+ else -+ /* It's possible that we incorrectly decided a .plt reloc was -+ needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in -+ check_relocs. We can't decide accurately between function and -+ non-function syms in check-relocs; Objects loaded later in -+ the link may change h->type. So fix it now. */ -+ h->plt.offset = (bfd_vma) -1; -+ -+ /* If this is a weak symbol, and there is a real definition, the -+ processor independent code will have arranged for us to see the -+ real definition first, and we can just use the same value. */ -+ if (h->is_weakalias) -+ { -+ struct elf_link_hash_entry *def = weakdef (h); -+ BFD_ASSERT (def->root.type == bfd_link_hash_defined); -+ h->root.u.def.section = def->root.u.def.section; -+ h->root.u.def.value = def->root.u.def.value; -+ return true; -+ } -+ -+ /* This is a reference to a symbol defined by a dynamic object which -+ is not a function. */ -+ -+ /* If we are creating a shared library, we must presume that the -+ only references to the symbol are via the global offset table. -+ For such cases we need not do anything here; the relocations will -+ be handled correctly by relocate_section. */ -+ if (bfd_link_pic (info)) -+ return true; -+ -+ /* If there are no references to this symbol that do not use the -+ GOT, we don't need to generate a copy reloc. */ -+ if (!h->non_got_ref) -+ return true; -+ -+ /* If -z nocopyreloc was given, we won't generate them either. */ -+ if (info->nocopyreloc) -+ { -+ h->non_got_ref = 0; -+ return true; -+ } -+ -+ eh = (struct elf64_mb_link_hash_entry *) h; -+ for (p = eh->dyn_relocs; p != NULL; p = p->next) -+ { -+ s = p->sec->output_section; -+ if (s != NULL && (s->flags & SEC_READONLY) != 0) -+ break; -+ } -+ -+ /* If we didn't find any dynamic relocs in read-only sections, then -+ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ -+ if (p == NULL) -+ { -+ h->non_got_ref = 0; -+ return true; -+ } -+ -+ /* We must allocate the symbol in our .dynbss section, which will -+ become part of the .bss section of the executable. There will be -+ an entry for this symbol in the .dynsym section. The dynamic -+ object will contain position independent code, so all references -+ from the dynamic object to this symbol will go through the global -+ offset table. The dynamic linker will use the .dynsym entry to -+ determine the address it must put in the global offset table, so -+ both the dynamic object and the regular object will refer to the -+ same memory location for the variable. */ -+ -+ /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker -+ to copy the initial value out of the dynamic object and into the -+ runtime process image. */ -+ dynobj = elf_hash_table (info)->dynobj; -+ BFD_ASSERT (dynobj != NULL); -+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) -+ { -+ htab->srelbss->size += sizeof (Elf64_External_Rela); -+ h->needs_copy = 1; -+ } -+ -+ /* We need to figure out the alignment required for this symbol. I -+ have no idea how ELF linkers handle this. */ -+ power_of_two = bfd_log2 (h->size); -+ if (power_of_two > 3) -+ power_of_two = 3; -+ -+ sdynbss = htab->sdynbss; -+ /* Apply the required alignment. */ -+ sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two)); -+ if (power_of_two > sdynbss->alignment_power) -+ { -+ if (! bfd_set_section_alignment (sdynbss, power_of_two)) -+ return false; -+ } -+ -+ /* Define the symbol as being at this point in the section. */ -+ h->root.u.def.section = s; -+ h->root.u.def.value = s->size; -+ -+ /* Increment the section size to make room for the symbol. */ -+ s->size += h->size; -+ return true; -+} -+ -+/* Allocate space in .plt, .got and associated reloc sections for -+ dynamic relocs. */ -+ -+static bool -+allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat) -+{ -+ struct bfd_link_info *info; -+ struct elf64_mb_link_hash_table *htab; -+ struct elf64_mb_link_hash_entry *eh; -+ struct elf64_mb_dyn_relocs *p; -+ -+ if (h->root.type == bfd_link_hash_indirect) -+ return true; -+ -+ info = (struct bfd_link_info *) dat; -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ if (htab->elf.dynamic_sections_created -+ && h->plt.refcount > 0) -+ { -+ /* Make sure this symbol is output as a dynamic symbol. -+ Undefined weak syms won't yet be marked as dynamic. */ -+ if (h->dynindx == -1 -+ && !h->forced_local) -+ { -+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return false; -+ } -+ -+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h)) -+ { -+ asection *s = htab->elf.splt; -+ -+ /* The first entry in .plt is reserved. */ -+ if (s->size == 0) -+ s->size = PLT_ENTRY_SIZE; -+ -+ h->plt.offset = s->size; -+ -+ /* If this symbol is not defined in a regular file, and we are -+ not generating a shared library, then set the symbol to this -+ location in the .plt. This is required to make function -+ pointers compare as equal between the normal executable and -+ the shared library. */ -+ if (! bfd_link_pic (info) -+ && !h->def_regular) -+ { -+ h->root.u.def.section = s; -+ h->root.u.def.value = h->plt.offset; -+ } -+ -+ /* Make room for this entry. */ -+ s->size += PLT_ENTRY_SIZE; -+ -+ /* We also need to make an entry in the .got.plt section, which -+ will be placed in the .got section by the linker script. */ -+ htab->elf.sgotplt->size += 4; -+ -+ /* We also need to make an entry in the .rel.plt section. */ -+ htab->elf.srelplt->size += sizeof (Elf64_External_Rela); -+ } -+ else -+ { -+ h->plt.offset = (bfd_vma) -1; -+ h->needs_plt = 0; -+ } -+ } -+ else -+ { -+ h->plt.offset = (bfd_vma) -1; -+ h->needs_plt = 0; -+ } -+ -+ eh = (struct elf64_mb_link_hash_entry *) h; -+ if (h->got.refcount > 0) -+ { -+ unsigned int need; -+ asection *s; -+ -+ /* Make sure this symbol is output as a dynamic symbol. -+ Undefined weak syms won't yet be marked as dynamic. */ -+ if (h->dynindx == -1 -+ && !h->forced_local) -+ { -+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return false; -+ } -+ -+ need = 0; -+ if ((eh->tls_mask & TLS_TLS) != 0) -+ { -+ /* Handle TLS Symbol */ -+ if ((eh->tls_mask & TLS_LD) != 0) -+ { -+ if (!eh->elf.def_dynamic) -+ /* We'll just use htab->tlsld_got.offset. This should -+ always be the case. It's a little odd if we have -+ a local dynamic reloc against a non-local symbol. */ -+ htab->tlsld_got.refcount += 1; -+ else -+ need += 8; -+ } -+ if ((eh->tls_mask & TLS_GD) != 0) -+ need += 8; -+ } -+ else -+ { -+ /* Regular (non-TLS) symbol */ -+ need += 4; -+ } -+ if (need == 0) -+ { -+ h->got.offset = (bfd_vma) -1; -+ } -+ else -+ { -+ s = htab->elf.sgot; -+ h->got.offset = s->size; -+ s->size += need; -+ htab->elf.srelgot->size += need * (sizeof (Elf64_External_Rela) / 4); -+ } -+ } -+ else -+ h->got.offset = (bfd_vma) -1; -+ -+ if (eh->dyn_relocs == NULL) -+ return true; -+ -+ /* In the shared -Bsymbolic case, discard space allocated for -+ dynamic pc-relative relocs against symbols which turn out to be -+ defined in regular objects. For the normal shared case, discard -+ space for pc-relative relocs that have become local due to symbol -+ visibility changes. */ -+ -+ if (bfd_link_pic (info)) -+ { -+ if (h->def_regular -+ && (h->forced_local -+ || info->symbolic)) -+ { -+ struct elf64_mb_dyn_relocs **pp; -+ -+ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) -+ { -+ p->count -= p->pc_count; -+ p->pc_count = 0; -+ if (p->count == 0) -+ *pp = p->next; -+ else -+ pp = &p->next; -+ } -+ } -+ else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) -+ h->dyn_relocs = NULL; -+ } -+ else -+ { -+ /* For the non-shared case, discard space for relocs against -+ symbols which turn out to need copy relocs or are not -+ dynamic. */ -+ -+ if (!h->non_got_ref -+ && ((h->def_dynamic -+ && !h->def_regular) -+ || (htab->elf.dynamic_sections_created -+ && (h->root.type == bfd_link_hash_undefweak -+ || h->root.type == bfd_link_hash_undefined)))) -+ { -+ /* Make sure this symbol is output as a dynamic symbol. -+ Undefined weak syms won't yet be marked as dynamic. */ -+ if (h->dynindx == -1 -+ && !h->forced_local) -+ { -+ if (! bfd_elf_link_record_dynamic_symbol (info, h)) -+ return false; -+ } -+ -+ /* If that succeeded, we know we'll be keeping all the -+ relocs. */ -+ if (h->dynindx != -1) -+ goto keep; -+ } -+ -+ h->dyn_relocs = NULL; -+ -+ keep: ; -+ } -+ -+ /* Finally, allocate space. */ -+ for (p = h->dyn_relocs; p != NULL; p = p->next) -+ { -+ asection *sreloc = elf_section_data (p->sec)->sreloc; -+ sreloc->size += p->count * sizeof (Elf64_External_Rela); -+ } -+ -+ return true; -+} -+ -+/* Set the sizes of the dynamic sections. */ -+ -+static bool -+microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info) -+{ -+ struct elf64_mb_link_hash_table *htab; -+ bfd *dynobj; -+ asection *s; -+ bfd *ibfd; -+ -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ dynobj = htab->elf.dynobj; -+ BFD_ASSERT (dynobj != NULL); -+ -+ /* Set up .got offsets for local syms, and space for local dynamic -+ relocs. */ -+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) -+ { -+ bfd_signed_vma *local_got; -+ bfd_signed_vma *end_local_got; -+ bfd_size_type locsymcount; -+ Elf_Internal_Shdr *symtab_hdr; -+ unsigned char *lgot_masks; -+ asection *srel; -+ -+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) -+ continue; -+ -+ for (s = ibfd->sections; s != NULL; s = s->next) -+ { -+ struct elf_dyn_relocs *p; -+ -+ for (p = ((struct elf64_mb_dyn_relocs *) -+ elf_section_data (s)->local_dynrel); -+ p != NULL; -+ p = p->next) -+ { -+ if (!bfd_is_abs_section (p->sec) -+ && bfd_is_abs_section (p->sec->output_section)) -+ { -+ /* Input section has been discarded, either because -+ it is a copy of a linkonce section or due to -+ linker script /DISCARD/, so we'll be discarding -+ the relocs too. */ -+ } -+ else if (p->count != 0) -+ { -+ srel = elf_section_data (p->sec)->sreloc; -+ srel->size += p->count * sizeof (Elf64_External_Rela); -+ if ((p->sec->output_section->flags & SEC_READONLY) != 0) -+ info->flags |= DF_TEXTREL; -+ } -+ } -+ } -+ -+ local_got = elf_local_got_refcounts (ibfd); -+ if (!local_got) -+ continue; -+ -+ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; -+ locsymcount = symtab_hdr->sh_info; -+ end_local_got = local_got + locsymcount; -+ lgot_masks = (unsigned char *) end_local_got; -+ s = htab->elf.sgot; -+ srel = htab->elf.srelgot; -+ -+ for (; local_got < end_local_got; ++local_got, ++lgot_masks) -+ { -+ if (*local_got > 0) -+ { -+ unsigned int need = 0; -+ if ((*lgot_masks & TLS_TLS) != 0) -+ { -+ if ((*lgot_masks & TLS_GD) != 0) -+ need += 8; -+ if ((*lgot_masks & TLS_LD) != 0) -+ htab->tlsld_got.refcount += 1; -+ } -+ else -+ need += 4; -+ -+ if (need == 0) -+ { -+ *local_got = (bfd_vma) -1; -+ } -+ else -+ { -+ *local_got = s->size; -+ s->size += need; -+ if (bfd_link_pic (info)) -+ srel->size += need * (sizeof (Elf64_External_Rela) / 4); -+ } -+ } -+ else -+ *local_got = (bfd_vma) -1; -+ } -+ } -+ -+ /* Allocate global sym .plt and .got entries, and space for global -+ sym dynamic relocs. */ -+ elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info); -+ -+ if (htab->tlsld_got.refcount > 0) -+ { -+ htab->tlsld_got.offset = htab->elf.sgot->size; -+ htab->elf.sgot->size += 8; -+ if (bfd_link_pic (info)) -+ htab->elf.srelgot->size += sizeof (Elf64_External_Rela); -+ } -+ else -+ htab->tlsld_got.offset = (bfd_vma) -1; -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ /* Make space for the trailing nop in .plt. */ -+ if (htab->elf.splt->size > 0) -+ htab->elf.splt->size += 4; -+ } -+ -+ /* The check_relocs and adjust_dynamic_symbol entry points have -+ determined the sizes of the various dynamic sections. Allocate -+ memory for them. */ -+ for (s = dynobj->sections; s != NULL; s = s->next) -+ { -+ const char *name; -+ bool strip = false; -+ -+ if ((s->flags & SEC_LINKER_CREATED) == 0) -+ continue; -+ -+ /* It's OK to base decisions on the section name, because none -+ of the dynobj section names depend upon the input files. */ -+ name = bfd_section_name (s); -+ -+ if (startswith (name, ".rela")) -+ { -+ if (s->size == 0) -+ { -+ /* If we don't need this section, strip it from the -+ output file. This is to handle .rela.bss and -+ .rela.plt. We must create it in -+ create_dynamic_sections, because it must be created -+ before the linker maps input sections to output -+ sections. The linker does that before -+ adjust_dynamic_symbol is called, and it is that -+ function which decides whether anything needs to go -+ into these sections. */ -+ strip = true; -+ } -+ else -+ { -+ /* We use the reloc_count field as a counter if we need -+ to copy relocs into the output file. */ -+ s->reloc_count = 0; -+ } -+ } -+ else if (s != htab->elf.splt -+ && s != htab->elf.sgot -+ && s != htab->elf.sgotplt -+ && s != htab->elf.sdynbss -+ && s != htab->elf.sdynrelro) -+ { -+ /* It's not one of our sections, so don't allocate space. */ -+ continue; -+ } -+ -+ if (strip) -+ { -+ s->flags |= SEC_EXCLUDE; -+ continue; -+ } -+ -+ /* Allocate memory for the section contents. */ -+ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. -+ Unused entries should be reclaimed before the section's contents -+ are written out, but at the moment this does not happen. Thus in -+ order to prevent writing out garbage, we initialise the section's -+ contents to zero. */ -+ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); -+ if (s->contents == NULL && s->size != 0) -+ return false; -+ } -+ -+ /* ??? Force DF_BIND_NOW? */ -+ info->flags |= DF_BIND_NOW; -+ return _bfd_elf_add_dynamic_tags (output_bfd, info, true); -+} -+ -+/* Finish up dynamic symbol handling. We set the contents of various -+ dynamic sections here. */ -+ -+static bool -+microblaze_elf_finish_dynamic_symbol (bfd *output_bfd, -+ struct bfd_link_info *info, -+ struct elf_link_hash_entry *h, -+ Elf_Internal_Sym *sym) -+{ -+ struct elf64_mb_link_hash_table *htab; -+ struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h); -+ -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ if (h->plt.offset != (bfd_vma) -1) -+ { -+ asection *splt; -+ asection *srela; -+ asection *sgotplt; -+ Elf_Internal_Rela rela; -+ bfd_byte *loc; -+ bfd_vma plt_index; -+ bfd_vma got_offset; -+ bfd_vma got_addr; -+ -+ /* This symbol has an entry in the procedure linkage table. Set -+ it up. */ -+ BFD_ASSERT (h->dynindx != -1); -+ -+ splt = htab->elf.splt; -+ srela = htab->elf.srelplt; -+ sgotplt = htab->elf.sgotplt; -+ BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL); -+ -+ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved. */ -+ got_offset = (plt_index + 3) * 4; /* 3 reserved ??? */ -+ got_addr = got_offset; -+ -+ /* For non-PIC objects we need absolute address of the GOT entry. */ -+ if (!bfd_link_pic (info)) -+ got_addr += sgotplt->output_section->vma + sgotplt->output_offset; -+ -+ /* Fill in the entry in the procedure linkage table. */ -+ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff), -+ splt->contents + h->plt.offset); -+ if (bfd_link_pic (info)) -+ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff), -+ splt->contents + h->plt.offset + 4); -+ else -+ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff), -+ splt->contents + h->plt.offset + 4); -+ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2, -+ splt->contents + h->plt.offset + 8); -+ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3, -+ splt->contents + h->plt.offset + 12); -+ -+ /* Any additions to the .got section??? */ -+ /* bfd_put_32 (output_bfd, -+ splt->output_section->vma + splt->output_offset + h->plt.offset + 4, -+ sgotplt->contents + got_offset); */ -+ -+ /* Fill in the entry in the .rela.plt section. */ -+ rela.r_offset = (sgotplt->output_section->vma -+ + sgotplt->output_offset -+ + got_offset); -+ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT); -+ rela.r_addend = 0; -+ loc = srela->contents; -+ loc += plt_index * sizeof (Elf64_External_Rela); -+ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); -+ -+ if (!h->def_regular) -+ { -+ /* Mark the symbol as undefined, rather than as defined in -+ the .plt section. Zero the value. */ -+ sym->st_shndx = SHN_UNDEF; -+ sym->st_value = 0; -+ } -+ } -+ -+ /* h->got.refcount to be checked ? */ -+ if (h->got.offset != (bfd_vma) -1 && -+ ! ((h->got.offset & 1) || -+ IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask))) -+ { -+ asection *sgot; -+ asection *srela; -+ bfd_vma offset; -+ -+ /* This symbol has an entry in the global offset table. Set it -+ up. */ -+ -+ sgot = htab->elf.sgot; -+ srela = htab->elf.srelgot; -+ BFD_ASSERT (sgot != NULL && srela != NULL); -+ -+ offset = (sgot->output_section->vma + sgot->output_offset -+ + (h->got.offset &~ (bfd_vma) 1)); -+ -+ /* If this is a -Bsymbolic link, and the symbol is defined -+ locally, we just want to emit a RELATIVE reloc. Likewise if -+ the symbol was forced to be local because of a version file. -+ The entry in the global offset table will already have been -+ initialized in the relocate_section function. */ -+ if (bfd_link_pic (info) -+ && ((info->symbolic && h->def_regular) -+ || h->dynindx == -1)) -+ { -+ asection *sec = h->root.u.def.section; -+ bfd_vma value; -+ -+ value = h->root.u.def.value; -+ if (sec->output_section != NULL) -+ /* PR 21180: If the output section is NULL, then the symbol is no -+ longer needed, and in theory the GOT entry is redundant. But -+ it is too late to change our minds now... */ -+ value += sec->output_section->vma + sec->output_offset; -+ -+ microblaze_elf_output_dynamic_relocation (output_bfd, -+ srela, srela->reloc_count++, -+ /* symindex= */ 0, -+ R_MICROBLAZE_REL, offset, -+ value); -+ } -+ else -+ { -+ microblaze_elf_output_dynamic_relocation (output_bfd, -+ srela, srela->reloc_count++, -+ h->dynindx, -+ R_MICROBLAZE_GLOB_DAT, -+ offset, 0); -+ } -+ -+ bfd_put_32 (output_bfd, (bfd_vma) 0, -+ sgot->contents + (h->got.offset &~ (bfd_vma) 1)); -+ } -+ -+ if (h->needs_copy) -+ { -+ asection *s; -+ Elf_Internal_Rela rela; -+ bfd_byte *loc; -+ -+ /* This symbols needs a copy reloc. Set it up. */ -+ -+ BFD_ASSERT (h->dynindx != -1); -+ -+ rela.r_offset = (h->root.u.def.value -+ + h->root.u.def.section->output_section->vma -+ + h->root.u.def.section->output_offset); -+ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY); -+ rela.r_addend = 0; -+ if (h->root.u.def.section == htab->elf.sdynrelro) -+ s = htab->elf.sreldynrelro; -+ else -+ s = htab->elf.srelbss; -+ loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela); -+ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); -+ } -+ -+ /* Mark some specially defined symbols as absolute. */ -+ if (h == htab->elf.hdynamic -+ || h == htab->elf.hgot -+ || h == htab->elf.hplt) -+ sym->st_shndx = SHN_ABS; -+ -+ return true; -+} -+ -+ -+/* Finish up the dynamic sections. */ -+ -+static bool -+microblaze_elf_finish_dynamic_sections (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *sdyn, *sgot; -+ struct elf64_mb_link_hash_table *htab; -+ -+ htab = elf64_mb_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ dynobj = htab->elf.dynobj; -+ -+ sdyn = bfd_get_linker_section (dynobj, ".dynamic"); -+ -+ if (htab->elf.dynamic_sections_created) -+ { -+ asection *splt; -+ Elf64_External_Dyn *dyncon, *dynconend; -+ -+ dyncon = (Elf64_External_Dyn *) sdyn->contents; -+ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size); -+ for (; dyncon < dynconend; dyncon++) -+ { -+ Elf_Internal_Dyn dyn; -+ asection *s; -+ bool size; -+ -+ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn); -+ -+ switch (dyn.d_tag) -+ { -+ case DT_PLTGOT: -+ s = htab->elf.sgotplt; -+ size = false; -+ break; -+ -+ case DT_PLTRELSZ: -+ s = htab->elf.srelplt; -+ size = true; -+ break; -+ -+ case DT_JMPREL: -+ s = htab->elf.srelplt; -+ size = false; -+ break; -+ -+ default: -+ continue; -+ } -+ -+ if (s == NULL) -+ dyn.d_un.d_val = 0; -+ else -+ { -+ if (!size) -+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; -+ else -+ dyn.d_un.d_val = s->size; -+ } -+ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon); -+ } -+ -+ splt = htab->elf.splt; -+ BFD_ASSERT (splt != NULL && sdyn != NULL); -+ -+ /* Clear the first entry in the procedure linkage table, -+ and put a nop in the last four bytes. */ -+ if (splt->size > 0) -+ { -+ memset (splt->contents, 0, PLT_ENTRY_SIZE); -+ bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop. */, -+ splt->contents + splt->size - 4); -+ -+ if (splt->output_section != bfd_abs_section_ptr) -+ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; -+ } -+ } -+ -+ /* Set the first entry in the global offset table to the address of -+ the dynamic section. */ -+ sgot = htab->elf.sgotplt; -+ if (sgot && sgot->size > 0) -+ { -+ if (sdyn == NULL) -+ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); -+ else -+ bfd_put_32 (output_bfd, -+ sdyn->output_section->vma + sdyn->output_offset, -+ sgot->contents); -+ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; -+ } -+ -+ if (htab->elf.sgot && htab->elf.sgot->size > 0) -+ elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize = 4; -+ -+ return true; -+} -+ -+/* Hook called by the linker routine which adds symbols from an object -+ file. We use it to put .comm items in .sbss, and not .bss. */ -+ -+static bool -+microblaze_elf_add_symbol_hook (bfd *abfd, -+ struct bfd_link_info *info, -+ Elf_Internal_Sym *sym, -+ const char **namep ATTRIBUTE_UNUSED, -+ flagword *flagsp ATTRIBUTE_UNUSED, -+ asection **secp, -+ bfd_vma *valp) -+{ -+ if (sym->st_shndx == SHN_COMMON -+ && !bfd_link_relocatable (info) -+ && sym->st_size <= elf_gp_size (abfd)) -+ { -+ /* Common symbols less than or equal to -G nn bytes are automatically -+ put into .sbss. */ -+ *secp = bfd_make_section_old_way (abfd, ".sbss"); -+ if (*secp == NULL -+ || !bfd_set_section_flags (*secp, SEC_IS_COMMON | SEC_SMALL_DATA)) -+ return false; -+ -+ *valp = sym->st_size; -+ } -+ -+ return true; -+} -+ -+#define TARGET_LITTLE_SYM microblaze_elf64_le_vec -+#define TARGET_LITTLE_NAME "elf64-microblazeel" -+ -+#define TARGET_BIG_SYM microblaze_elf64_vec -+#define TARGET_BIG_NAME "elf64-microblaze" -+ -+#define ELF_ARCH bfd_arch_microblaze -+#define ELF_TARGET_ID MICROBLAZE_ELF_DATA -+#define ELF_MACHINE_CODE EM_MICROBLAZE -+#define ELF_MACHINE_ALT1 EM_MICROBLAZE_OLD -+#define ELF_MAXPAGESIZE 0x1000 -+#define elf_info_to_howto microblaze_elf_info_to_howto -+#define elf_info_to_howto_rel NULL -+ -+#define bfd_elf64_bfd_reloc_type_lookup microblaze_elf_reloc_type_lookup -+#define bfd_elf64_bfd_is_local_label_name microblaze_elf_is_local_label_name -+#define bfd_elf64_new_section_hook microblaze_elf_new_section_hook -+#define elf_backend_relocate_section microblaze_elf_relocate_section -+#define bfd_elf64_bfd_relax_section microblaze_elf_relax_section -+#define bfd_elf64_bfd_merge_private_bfd_data microblaze_elf_merge_private_bfd_data -+#define bfd_elf64_bfd_reloc_name_lookup microblaze_elf_reloc_name_lookup -+ -+#define elf_backend_gc_mark_hook microblaze_elf_gc_mark_hook -+#define elf_backend_gc_sweep_hook microblaze_elf_gc_sweep_hook -+#define elf_backend_check_relocs microblaze_elf_check_relocs -+#define elf_backend_copy_indirect_symbol microblaze_elf_copy_indirect_symbol -+#define bfd_elf64_bfd_link_hash_table_create microblaze_elf_link_hash_table_create -+#define elf_backend_can_gc_sections 1 -+#define elf_backend_can_refcount 1 -+#define elf_backend_want_got_plt 1 -+#define elf_backend_plt_readonly 1 -+#define elf_backend_got_header_size 12 -+#define elf_backend_want_dynrelro 1 -+#define elf_backend_rela_normal 1 -+#define elf_backend_dtrel_excludes_plt 1 -+ -+#define elf_backend_adjust_dynamic_symbol microblaze_elf_adjust_dynamic_symbol -+#define elf_backend_create_dynamic_sections microblaze_elf_create_dynamic_sections -+#define elf_backend_finish_dynamic_sections microblaze_elf_finish_dynamic_sections -+#define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol -+#define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections -+#define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook -+ -+#include "elf64-target.h" -diff --git a/bfd/libbfd.h b/bfd/libbfd.h -index 6e62e556962..ef5568a78b0 100644 ---- a/bfd/libbfd.h -+++ b/bfd/libbfd.h -@@ -2992,6 +2992,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_MICROBLAZE_32_ROSDA", - "BFD_RELOC_MICROBLAZE_32_RWSDA", - "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", -+ "BFD_RELOC_MICROBLAZE_32_NONE", - "BFD_RELOC_MICROBLAZE_64_NONE", - "BFD_RELOC_MICROBLAZE_64_GOTPC", - "BFD_RELOC_MICROBLAZE_64_GOT", -@@ -2999,6 +3000,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_MICROBLAZE_64_GOTOFF", - "BFD_RELOC_MICROBLAZE_32_GOTOFF", - "BFD_RELOC_MICROBLAZE_COPY", -+ "BFD_RELOC_MICROBLAZE_64", -+ "BFD_RELOC_MICROBLAZE_64_PCREL", - "BFD_RELOC_MICROBLAZE_64_TLS", - "BFD_RELOC_MICROBLAZE_64_TLSGD", - "BFD_RELOC_MICROBLAZE_64_TLSLD", -diff --git a/bfd/reloc.c b/bfd/reloc.c -index 164060361a9..e733e2397f4 100644 ---- a/bfd/reloc.c -+++ b/bfd/reloc.c -@@ -6898,6 +6898,12 @@ ENUM - ENUMDOC - This is a 32 bit reloc for the microblaze to handle - expressions of the form "Symbol Op Symbol" -+ENUM -+ BFD_RELOC_MICROBLAZE_32_NONE -+ENUMDOC -+ This is a 32 bit reloc that stores the 32 bit pc relative -+ value in two words (with an imm instruction). No relocation is -+ done here - only used for relaxing - ENUM - BFD_RELOC_MICROBLAZE_64_NONE - ENUMDOC -@@ -6991,6 +6997,20 @@ ENUMDOC - value in two words (with an imm instruction). The relocation is - relative offset from start of TEXT. - -+ This is a 64 bit reloc that stores 64-bit thread pointer relative offset -+ to two words (uses imml instruction). -+ENUM -+BFD_RELOC_MICROBLAZE_64, -+ENUMDOC -+ This is a 64 bit reloc that stores the 64 bit pc relative -+ value in two words (with an imml instruction). No relocation is -+ done here - only used for relaxing -+ENUM -+BFD_RELOC_MICROBLAZE_64_PCREL, -+ENUMDOC -+ This is a 32 bit reloc that stores the 32 bit pc relative -+ value in two words (with an imml instruction). No relocation is -+ done here - only used for relaxing - ENUM - BFD_RELOC_AARCH64_RELOC_START - ENUMDOC -diff --git a/bfd/targets.c b/bfd/targets.c -index 417743efc0e..333f05c55f4 100644 ---- a/bfd/targets.c -+++ b/bfd/targets.c -@@ -795,6 +795,8 @@ extern const bfd_target mep_elf32_le_vec; - extern const bfd_target metag_elf32_vec; - extern const bfd_target microblaze_elf32_vec; - extern const bfd_target microblaze_elf32_le_vec; -+extern const bfd_target microblaze_elf64_vec; -+extern const bfd_target microblaze_elf64_le_vec; - extern const bfd_target mips_ecoff_be_vec; - extern const bfd_target mips_ecoff_le_vec; - extern const bfd_target mips_ecoff_bele_vec; -@@ -1165,6 +1167,10 @@ static const bfd_target * const _bfd_target_vector[] = - - &metag_elf32_vec, - -+#ifdef BFD64 -+ µblaze_elf64_vec, -+ µblaze_elf64_le_vec, -+#endif - µblaze_elf32_vec, - - &mips_ecoff_be_vec, -diff --git a/gdb/features/Makefile b/gdb/features/Makefile -index fc3196864c9..1bb198abfd3 100644 ---- a/gdb/features/Makefile -+++ b/gdb/features/Makefile -@@ -101,7 +101,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH)) - # to make on the command line. - XMLTOC = \ - microblaze-with-stack-protect.xml \ -+ microblaze64-with-stack-protect.xml \ - microblaze.xml \ -+ microblaze64.xml \ - mips-dsp-linux.xml \ - mips-linux.xml \ - mips64-dsp-linux.xml \ -diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml -index 29fdd6c0a2f..a5c3cce069d 100644 ---- a/gdb/features/microblaze-core.xml -+++ b/gdb/features/microblaze-core.xml -@@ -8,7 +8,7 @@ - - - -- -+ - - - -@@ -39,7 +39,7 @@ - - - -- -+ - - - -@@ -64,4 +64,6 @@ - - - -+ -+ - -diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml -index aac51ea471c..722a51f0df5 100644 ---- a/gdb/features/microblaze-stack-protect.xml -+++ b/gdb/features/microblaze-stack-protect.xml -@@ -7,6 +7,6 @@ - - - -- -- -+ -+ - -diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c -index aa180bf35d5..6a9e74c7a6f 100644 ---- a/gdb/features/microblaze-with-stack-protect.c -+++ b/gdb/features/microblaze-with-stack-protect.c -@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) - - feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); - tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); -- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); -+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); -@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) - tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); -- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); -+ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); -@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void) - tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); - - feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect"); -- tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int"); -- tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); - - tdesc_microblaze_with_stack_protect = result.release (); - } -diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c -index ef2c64c720e..201232dff83 100644 ---- a/gdb/features/microblaze.c -+++ b/gdb/features/microblaze.c -@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void) - - feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); - tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); -- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); -+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); -@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void) - tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); -- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); -+ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); -@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void) - tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); - tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); - - tdesc_microblaze = result.release (); - } -diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml -new file mode 100644 -index 00000000000..96e99e2fb24 ---- /dev/null -+++ b/gdb/features/microblaze64-core.xml -@@ -0,0 +1,69 @@ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml -new file mode 100644 -index 00000000000..1bbf5fc3cea ---- /dev/null -+++ b/gdb/features/microblaze64-stack-protect.xml -@@ -0,0 +1,12 @@ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c -new file mode 100644 -index 00000000000..a4de4666c76 ---- /dev/null -+++ b/gdb/features/microblaze64-with-stack-protect.c -@@ -0,0 +1,79 @@ -+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: -+ Original: microblaze-with-stack-protect.xml */ -+ -+#include "defs.h" -+#include "osabi.h" -+#include "target-descriptions.h" -+ -+struct target_desc *tdesc_microblaze64_with_stack_protect; -+static void -+initialize_tdesc_microblaze64_with_stack_protect (void) -+{ -+ target_desc_up result = allocate_target_description (); -+ struct tdesc_feature *feature; -+ -+ feature = tdesc_create_feature (result.get() , "org.gnu.gdb.microblaze64.core"); -+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int"); -+ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); -+ -+ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.stack-protect"); -+ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); -+ -+ tdesc_microblaze64_with_stack_protect = result.release(); -+} -diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml -new file mode 100644 -index 00000000000..0e9f01611f3 ---- /dev/null -+++ b/gdb/features/microblaze64-with-stack-protect.xml -@@ -0,0 +1,12 @@ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c -new file mode 100644 -index 00000000000..8ab7a90dd95 ---- /dev/null -+++ b/gdb/features/microblaze64.c -@@ -0,0 +1,77 @@ -+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: -+ Original: microblaze.xml */ -+ -+#include "defs.h" -+#include "osabi.h" -+#include "target-descriptions.h" -+ -+struct target_desc *tdesc_microblaze64; -+static void -+initialize_tdesc_microblaze64 (void) -+{ -+ target_desc_up result = allocate_target_description (); -+ struct tdesc_feature *feature; -+ -+ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.core"); -+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); -+ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); -+ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); -+ -+ tdesc_microblaze64 = result.release(); -+} -diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml -new file mode 100644 -index 00000000000..515d18e65cf ---- /dev/null -+++ b/gdb/features/microblaze64.xml -@@ -0,0 +1,11 @@ -+ -+ -+ -+ -+ -+ -+ -diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c -index fc52adffb72..f2db32f0087 100644 ---- a/gdb/microblaze-linux-tdep.c -+++ b/gdb/microblaze-linux-tdep.c -@@ -40,6 +40,7 @@ - #include "features/microblaze-linux.c" - - static int microblaze_debug_flag = 0; -+int MICROBLAZE_REGISTER_SIZE=4; - - static void - microblaze_debug (const char *fmt, ...) -@@ -55,6 +56,7 @@ microblaze_debug (const char *fmt, ...) - } - } - -+#if 0 - static int - microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - struct bp_target_info *bp_tgt) -@@ -86,6 +88,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - return val; - } - -+#endif -+ - static void - microblaze_linux_sigtramp_cache (struct frame_info *next_frame, - struct trad_frame_cache *this_cache, -@@ -147,8 +151,8 @@ microblaze_linux_init_abi (struct gdbarch_info info, - - linux_init_abi (info, gdbarch, 0); - -- set_gdbarch_memory_remove_breakpoint (gdbarch, -- microblaze_linux_memory_remove_breakpoint); -+ // set_gdbarch_memory_remove_breakpoint (gdbarch, -+ // microblaze_linux_memory_remove_breakpoint); - - /* Shared library handling. */ - set_solib_svr4_fetch_link_map_offsets (gdbarch, -@@ -160,10 +164,30 @@ microblaze_linux_init_abi (struct gdbarch_info info, - - /* BFD target for core files. */ - if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) -- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); -+ { -+ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { -+ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze"); -+ MICROBLAZE_REGISTER_SIZE=8; -+ } -+ else -+ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); -+ } - else -- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); -+ { -+ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { -+ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel"); -+ MICROBLAZE_REGISTER_SIZE=8; -+ } -+ else -+ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); -+ } - -+ switch (info.bfd_arch_info->mach) -+ { -+ case bfd_mach_microblaze64: -+ set_gdbarch_ptr_bit (gdbarch, 64); -+ break; -+ } - - /* Shared library handling. */ - set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); -@@ -178,7 +202,9 @@ void _initialize_microblaze_linux_tdep (); - void - _initialize_microblaze_linux_tdep () - { -- gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, -+ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, -+ microblaze_linux_init_abi); -+ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, - microblaze_linux_init_abi); - initialize_tdesc_microblaze_linux (); - } -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index ccb6b730d64..c347bb9516b 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -40,7 +40,9 @@ - #include "remote.h" - - #include "features/microblaze-with-stack-protect.c" -+#include "features/microblaze64-with-stack-protect.c" - #include "features/microblaze.c" -+#include "features/microblaze64.c" - - /* Instruction macros used for analyzing the prologue. */ - /* This set of instruction macros need to be changed whenever the -@@ -75,12 +77,13 @@ static const char * const microblaze_register_names[] = - "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6", - "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11", - "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi", -- "rslr", "rshr" -+ "slr", "shr" - }; - - #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names) - - static unsigned int microblaze_debug_flag = 0; -+int reg_size = 4; - - #define microblaze_debug(fmt, ...) \ - debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \ -@@ -128,6 +131,15 @@ microblaze_fetch_instruction (CORE_ADDR pc) - constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; - - typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; -+static CORE_ADDR -+microblaze_store_arguments (struct regcache *regcache, int nargs, -+ struct value **args, CORE_ADDR sp, -+ int struct_return, CORE_ADDR struct_addr) -+{ -+ error (_("store_arguments not implemented")); -+ return sp; -+} -+#if 0 - static int - microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - struct bp_target_info *bp_tgt) -@@ -146,7 +158,6 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - /* Make sure we see the memory breakpoints. */ - scoped_restore restore_memory - = make_scoped_restore_show_memory_breakpoints (1); -- - val = target_read_memory (addr, old_contents, bplen); - - /* If our breakpoint is no longer at the address, this means that the -@@ -161,6 +172,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - return val; - } - -+#endif - /* Allocate and initialize a frame cache. */ - - static struct microblaze_frame_cache * -@@ -577,17 +589,16 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache, - gdb_byte *valbuf) - { - gdb_byte buf[8]; -- - /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF. */ - switch (TYPE_LENGTH (type)) - { - case 1: /* return last byte in the register. */ - regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); -- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1); -+ memcpy(valbuf, buf + reg_size - 1, 1); - return; - case 2: /* return last 2 bytes in register. */ - regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); -- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2); -+ memcpy(valbuf, buf + reg_size - 2, 2); - return; - case 4: /* for sizes 4 or 8, copy the required length. */ - case 8: -@@ -754,6 +765,12 @@ microblaze_software_single_step (struct regcache *regcache) - } - #endif - -+static void -+microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) -+{ -+ regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc); -+} -+ - static int dwarf2_to_reg_map[78] = - { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ - 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ -@@ -788,13 +805,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) - static void - microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) - { -+ - register_remote_g_packet_guess (gdbarch, - 4 * MICROBLAZE_NUM_CORE_REGS, -- tdesc_microblaze); -+ tdesc_microblaze64); - - register_remote_g_packet_guess (gdbarch, - 4 * MICROBLAZE_NUM_REGS, -- tdesc_microblaze_with_stack_protect); -+ tdesc_microblaze64_with_stack_protect); - } - - void -@@ -802,7 +820,7 @@ microblaze_supply_gregset (const struct regset *regset, - struct regcache *regcache, - int regnum, const void *gregs) - { -- const unsigned int *regs = (const unsigned int *)gregs; -+ const gdb_byte *regs = (const gdb_byte *) gregs; - if (regnum >= 0) - regcache->raw_supply (regnum, regs + regnum); - -@@ -810,7 +828,7 @@ microblaze_supply_gregset (const struct regset *regset, - int i; - - for (i = 0; i < 50; i++) { -- regcache->raw_supply (i, regs + i); -+ regcache->raw_supply (regnum, regs + i); - } - } - } -@@ -833,6 +851,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, - } - - -+static void -+make_regs (struct gdbarch *arch) -+{ -+ struct gdbarch_tdep *tdep = gdbarch_tdep (arch); -+ int mach = gdbarch_bfd_arch_info (arch)->mach; -+ -+ if (mach == bfd_mach_microblaze64) -+ { -+ set_gdbarch_ptr_bit (arch, 64); -+ } -+} - - static struct gdbarch * - microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) -@@ -846,8 +875,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - if (arches != NULL) - return arches->gdbarch; - if (tdesc == NULL) -- tdesc = tdesc_microblaze; -- -+ { -+ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ { -+ tdesc = tdesc_microblaze64; -+ reg_size = 8; -+ } -+ else -+ tdesc = tdesc_microblaze; -+ } - /* Check any target description for validity. */ - if (tdesc_has_registers (tdesc)) - { -@@ -855,31 +891,42 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - int valid_p; - int i; - -- feature = tdesc_find_feature (tdesc, -- "org.gnu.gdb.microblaze.core"); -+ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ feature = tdesc_find_feature (tdesc, -+ "org.gnu.gdb.microblaze64.core"); -+ else -+ feature = tdesc_find_feature (tdesc, -+ "org.gnu.gdb.microblaze.core"); - if (feature == NULL) - return NULL; - tdesc_data = tdesc_data_alloc (); - - valid_p = 1; -- for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++) -- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, -- microblaze_register_names[i]); -- feature = tdesc_find_feature (tdesc, -- "org.gnu.gdb.microblaze.stack-protect"); -+ for (i = 0; i < MICROBLAZE_NUM_REGS; i++) -+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, -+ microblaze_register_names[i]); -+ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ feature = tdesc_find_feature (tdesc, -+ "org.gnu.gdb.microblaze64.stack-protect"); -+ else -+ feature = tdesc_find_feature (tdesc, -+ "org.gnu.gdb.microblaze.stack-protect"); - if (feature != NULL) -- { -- valid_p = 1; -- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), -- MICROBLAZE_SLR_REGNUM, -- "rslr"); -- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), -- MICROBLAZE_SHR_REGNUM, -- "rshr"); -- } -+ { -+ valid_p = 1; -+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), -+ MICROBLAZE_SLR_REGNUM, -+ "slr"); -+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), -+ MICROBLAZE_SHR_REGNUM, -+ "shr"); -+ } - - if (!valid_p) -- return NULL; -+ { -+ // tdesc_data_cleanup (tdesc_data.get ()); -+ return NULL; -+ } - } - - /* Allocate space for the new architecture. */ -@@ -899,7 +946,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - /* Register numbers of various important registers. */ - set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); - set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); -+ -+ /* Register set. -+ make_regs (gdbarch); */ -+ switch (info.bfd_arch_info->mach) -+ { -+ case bfd_mach_microblaze64: -+ set_gdbarch_ptr_bit (gdbarch, 64); -+ break; -+ } - -+ - /* Map Dwarf2 registers to GDB registers. */ - set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); - -@@ -919,7 +976,9 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - microblaze_breakpoint::kind_from_pc); - set_gdbarch_sw_breakpoint_from_kind (gdbarch, - microblaze_breakpoint::bp_from_kind); -- set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); -+// set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); -+ -+// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); - - set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); - -@@ -927,7 +986,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - - set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); - -- microblaze_register_g_packet_guesses (gdbarch); -+ //microblaze_register_g_packet_guesses (gdbarch); - - frame_base_set_default (gdbarch, µblaze_frame_base); - -@@ -942,12 +1001,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); - //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); - -- /* If we have register sets, enable the generic core file support. */ -+ /* If we have register sets, enable the generic core file support. - if (tdep->gregset) { - set_gdbarch_iterate_over_regset_sections (gdbarch, - microblaze_iterate_over_regset_sections); -- } -- -+ }*/ - return gdbarch; - } - -@@ -959,6 +1017,8 @@ _initialize_microblaze_tdep () - - initialize_tdesc_microblaze_with_stack_protect (); - initialize_tdesc_microblaze (); -+ initialize_tdesc_microblaze64_with_stack_protect (); -+ initialize_tdesc_microblaze64 (); - /* Debug this files internals. */ - add_setshow_zuinteger_cmd ("microblaze", class_maintenance, - µblaze_debug_flag, _("\ -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index 2415acfe7b6..f4d810303ca 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -28,7 +28,7 @@ struct microblaze_gregset - microblaze_gregset() {} - unsigned int gregs[32]; - unsigned int fpregs[32]; -- unsigned int pregs[16]; -+ unsigned int pregs[18]; - }; - - struct microblaze_gdbarch_tdep : gdbarch_tdep -@@ -134,7 +134,7 @@ struct microblaze_frame_cache - struct trad_frame_saved_reg *saved_regs; - }; - /* All registers are 32 bits. */ --#define MICROBLAZE_REGISTER_SIZE 4 -+//#define MICROBLAZE_REGISTER_SIZE 8 - - /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. - Only used for native debugging. */ -diff --git a/include/elf/common.h b/include/elf/common.h -index 70d63e3299c..8aa330d6631 100644 ---- a/include/elf/common.h -+++ b/include/elf/common.h -@@ -360,6 +360,7 @@ - #define EM_U16_U8CORE 260 /* LAPIS nX-U16/U8 */ - #define EM_TACHYUM 261 /* Tachyum */ - #define EM_56800EF 262 /* NXP 56800EF Digital Signal Controller (DSC) */ -+#define EM_MB_64 263 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ - - /* If it is necessary to assign new unofficial EM_* values, please pick large - random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision -diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h -index 43ad3ad3904..79799b86a49 100644 ---- a/include/elf/microblaze.h -+++ b/include/elf/microblaze.h -@@ -61,6 +61,10 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type) - RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30) /* PC-relative TEXT offset. */ - RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */ - RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */ -+ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33) -+ RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34) -+ RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35) /* GOT entry offset. */ -+ - END_RELOC_NUMBERS (R_MICROBLAZE_max) - - /* Global base address names. */ -diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c -index b057492ba93..283d87c04a2 100644 ---- a/opcodes/microblaze-dis.c -+++ b/opcodes/microblaze-dis.c -@@ -33,6 +33,7 @@ - #define get_field_r1(buf, instr) get_field (buf, instr, RA_MASK, RA_LOW) - #define get_field_r2(buf, instr) get_field (buf, instr, RB_MASK, RB_LOW) - #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) -+#define get_int_field_imml(instr) ((instr & IMML_MASK) >> IMM_LOW) - #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) - - #define NUM_STRBUFS 3 -@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr) - } - - static char * --get_field_imm5 (struct string_buf *buf, long instr) -+get_field_imml (struct string_buf *buf, long instr) - { - char *p = strbuf (buf); - -- sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); -+ sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW)); -+ return p; -+} -+ -+static char * -+get_field_imms (struct string_buf *buf, long instr) -+{ -+ char *p = strbuf (buf); -+ -+ sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW)); - return p; - } - -@@ -90,6 +100,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr) - return p; - } - -+static char * -+get_field_immw (struct string_buf *buf, long instr) -+{ -+ char *p = strbuf (buf); -+ -+ if (instr & 0x00004000) -+ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ -+ else -+ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */ -+ return p; -+} -+ - static char * - get_field_rfsl (struct string_buf *buf, long instr) - { -@@ -296,9 +318,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) - } - } - break; -- case INST_TYPE_RD_R1_IMM5: -+ case INST_TYPE_RD_R1_IMML: -+ print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), -+ get_field_r1(&buf, inst), get_field_imm (&buf, inst)); -+ /* TODO: Also print symbol */ -+ break; -+ case INST_TYPE_RD_R1_IMMS: - print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), -- get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst)); -+ get_field_r1(&buf, inst), get_field_imms (&buf, inst)); - break; - case INST_TYPE_RD_RFSL: - print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), -@@ -402,9 +429,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) - } - } - break; -- case INST_TYPE_RD_R2: -- print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), -- get_field_r2 (&buf, inst)); -+ case INST_TYPE_IMML: -+ print_func (stream, "\t%s", get_field_imml (&buf, inst)); -+ /* TODO: Also print symbol */ -+ break; -+ case INST_TYPE_RD_R2: -+ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst)); - break; - case INST_TYPE_R2: - print_func (stream, "\t%s", get_field_r2 (&buf, inst)); -@@ -427,7 +457,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) - /* For mbar 16 or sleep insn. */ - case INST_TYPE_NONE: - break; -- /* For tuqula instruction */ -+ /* For bit field insns. */ -+ case INST_TYPE_RD_R1_IMMW_IMMS: -+ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), -+ get_field_immw (&buf, inst), get_field_imms (&buf, inst)); -+ break; -+ /* For tuqula instruction */ - case INST_TYPE_RD: - print_func (stream, "\t%s", get_field_rd (&buf, inst)); - break; -diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h -index ffb0f08c692..5e45df995de 100644 ---- a/opcodes/microblaze-opc.h -+++ b/opcodes/microblaze-opc.h -@@ -40,7 +40,7 @@ - #define INST_TYPE_RD_SPECIAL 11 - #define INST_TYPE_R1 12 - /* New instn type for barrel shift imms. */ --#define INST_TYPE_RD_R1_IMM5 13 -+#define INST_TYPE_RD_R1_IMMS 13 - #define INST_TYPE_RD_RFSL 14 - #define INST_TYPE_R1_RFSL 15 - -@@ -59,6 +59,15 @@ - /* For mbar. */ - #define INST_TYPE_IMM5 20 - -+/* For bsefi and bsifi */ -+#define INST_TYPE_RD_R1_IMMW_IMMS 21 -+ -+/* For 64-bit instructions */ -+#define INST_TYPE_IMML 22 -+#define INST_TYPE_RD_R1_IMML 23 -+#define INST_TYPE_R1_IMML 24 -+#define INST_TYPE_RD_R1_IMMW_IMMS 21 -+ - #define INST_TYPE_NONE 25 - - -@@ -88,10 +97,14 @@ - #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ - #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ - #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ --#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ -+#define OPCODE_MASK_H3 0xFC000700 /* High 6 bits and bits 21, 22, 23. */ -+#define OPCODE_MASK_H3B 0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22. */ - #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ -+#define OPCODE_MASK_H32B 0xFC00E000 /* High 6 bits and bit 16, 17, 18. */ - #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ -+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ - #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ -+#define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ - - /* New Mask for msrset, msrclr insns. */ - #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ -@@ -101,7 +114,7 @@ - #define DELAY_SLOT 1 - #define NO_DELAY_SLOT 0 - --#define MAX_OPCODES 289 -+#define MAX_OPCODES 412 - - const struct op_code_struct - { -@@ -119,6 +132,7 @@ const struct op_code_struct - /* More info about output format here. */ - } microblaze_opcodes[MAX_OPCODES] = - { -+ /* 32-bit instructions */ - {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, - {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, - {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, -@@ -155,9 +169,11 @@ const struct op_code_struct - {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, - {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, - {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, -- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, -- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, -- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, -+ {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, -+ {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, -+ {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, -+ {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, -+ {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, - {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, - {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst }, - {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst }, -@@ -174,9 +190,14 @@ const struct op_code_struct - {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, - {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, - {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, -+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }, - {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, -+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst }, -+ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst }, - {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, -+ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst }, - {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, -+ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst }, - {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, - {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst }, - {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst }, -@@ -226,18 +247,24 @@ const struct op_code_struct - {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst }, - {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst }, - {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst }, -+ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst }, - {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst }, - {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst }, -+ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst }, - {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst }, - {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst }, - {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst }, -+ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst }, - {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst }, - {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst }, -+ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst }, - {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst }, - {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst }, -+ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst }, - {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst }, - {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst }, - {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst }, -+ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst }, - {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst }, - {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst }, - {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst }, -@@ -248,9 +275,7 @@ const struct op_code_struct - {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */ - {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */ - {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */ -- {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ - {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */ -- {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ - {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, - {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, - {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, -@@ -402,8 +427,135 @@ const struct op_code_struct - {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst }, - {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst }, - {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */ -+ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */ -+ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */ - {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst }, - {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, -+ -+ /* 64-bit instructions */ -+ {"addl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst }, -+ {"rsubl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst }, -+ {"addlc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst }, -+ {"rsublc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst }, -+ {"addlk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst }, -+ {"rsublk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst }, -+ {"addlkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst }, -+ {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst }, -+ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, -+ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, -+ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ -+ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, -+ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, -+ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, -+ {"bslrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst }, -+ {"bsllli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst }, -+ {"bslrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst }, -+ {"bslrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst }, -+ {"bslefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst }, -+ {"bslifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst }, -+ {"orl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst }, -+ {"andl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst }, -+ {"xorl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst }, -+ {"andnl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst }, -+ {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst }, -+ {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst }, -+ {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst }, -+ {"srla", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst }, -+ {"srlc", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst }, -+ {"srll", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst }, -+ {"sextl8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst }, -+ {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst }, -+ {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst }, -+ {"brea", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst }, -+ {"bread", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst }, -+ {"breald", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst }, -+ {"beaeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst }, -+ {"bealeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst }, -+ {"beaeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst }, -+ {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst }, -+ {"beane", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst }, -+ {"bealne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst }, -+ {"beaned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst }, -+ {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst }, -+ {"bealt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst }, -+ {"beallt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst }, -+ {"bealtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst }, -+ {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst }, -+ {"beale", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst }, -+ {"bealle", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst }, -+ {"bealed", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst }, -+ {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst }, -+ {"beagt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst }, -+ {"bealgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst }, -+ {"beagtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst }, -+ {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst }, -+ {"beage", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst }, -+ {"bealge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst }, -+ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, -+ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, -+ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ -+ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ -+ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ -+ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ -+ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, -+ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, -+ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, -+ {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst }, -+ {"beaeqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst }, -+ {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */ -+ {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst }, -+ {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqid */ -+ {"beanei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst }, -+ {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */ -+ {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst }, -+ {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaneid */ -+ {"bealti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst }, -+ {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */ -+ {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst }, -+ {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealtid */ -+ {"bealei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst }, -+ {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */ -+ {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst }, -+ {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealeid */ -+ {"beagti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst }, -+ {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */ -+ {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst }, -+ {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagtid */ -+ {"beagei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst }, -+ {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */ -+ {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst }, -+ {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beageid */ -+ {"ll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst }, -+ {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst }, -+ {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst }, -+ {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst }, -+ {"lli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ -+ {"sli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ -+ {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */ -+ {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst }, -+ {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst }, -+ {"dmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst }, -+ {"ddiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst }, -+ {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst }, -+ {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst }, -+ {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst }, -+ {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst }, -+ {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst }, -+ {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst }, -+ {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst }, -+ {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst }, -+ {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst }, -+ {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst }, -+ {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ -+ {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ -+ - {"", 0, 0, 0, 0, 0, 0, 0, 0}, - }; - -@@ -424,5 +576,17 @@ char pvr_register_prefix[] = "rpvr"; - #define MIN_IMM5 ((int) 0x00000000) - #define MAX_IMM5 ((int) 0x0000001f) - -+#define MIN_IMM6 ((int) 0x00000000) -+#define MAX_IMM6 ((int) 0x0000003f) -+ -+#define MIN_IMM_WIDTH ((int) 0x00000001) -+#define MAX_IMM_WIDTH ((int) 0x00000020) -+ -+#define MIN_IMM6_WIDTH ((int) 0x00000001) -+#define MAX_IMM6_WIDTH ((int) 0x00000040) -+ -+#define MIN_IMML ((long) 0xffffff8000000000L) -+#define MAX_IMML ((long) 0x0000007fffffffffL) -+ - #endif /* MICROBLAZE_OPC */ - -diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h -index 8e293465fec..254d9fe911e 100644 ---- a/opcodes/microblaze-opcm.h -+++ b/opcodes/microblaze-opcm.h -@@ -25,22 +25,23 @@ - - enum microblaze_instr - { -+ /* 32-bit instructions */ - add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, - addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, - mulh, mulhu, mulhsu,swapb,swaph, - idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, -- ncget, ncput, muli, bslli, bsrai, bsrli, mului, -+ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului, - /* 'or/and/xor' are C++ keywords. */ - microblaze_or, microblaze_and, microblaze_xor, - andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, -- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd, -- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, -- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, -+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse, -+ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, -+ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, - imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, - brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, -- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, -- shr, sw, swr, swx, lbui, lhui, lwi, -- sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, -+ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, -+ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli, -+ sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, - fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, - /* 'fsqrt' is a glibc:math.h symbol. */ - fint, microblaze_fsqrt, -@@ -59,6 +60,18 @@ enum microblaze_instr - aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, - eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, - eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, -+ -+ /* 64-bit instructions */ -+ addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, -+ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, -+ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, -+ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, -+ bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt, -+ bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid, -+ beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti, -+ beagtid, beagei, beageid, imml, ll, llr, sl, slr, -+ dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge, -+ dcmp_un, dbl, dlong, dsqrt, - invalid_inst - }; - -@@ -130,18 +143,25 @@ enum microblaze_instr_type - #define RB_LOW 11 /* Low bit for RB. */ - #define IMM_LOW 0 /* Low bit for immediate. */ - #define IMM_MBAR 21 /* low bit for mbar instruction. */ -+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */ - - #define RD_MASK 0x03E00000 - #define RA_MASK 0x001F0000 - #define RB_MASK 0x0000F800 - #define IMM_MASK 0x0000FFFF -+#define IMML_MASK 0x00FFFFFF - --/* Imm mask for barrel shifts. */ -+/* Imm masks for barrel shifts. */ - #define IMM5_MASK 0x0000001F -+#define IMM6_MASK 0x0000003F - - /* Imm mask for mbar. */ - #define IMM5_MBAR_MASK 0x03E00000 - -+/* Imm masks for extract/insert width. */ -+#define IMM5_WIDTH_MASK 0x000007C0 -+#define IMM6_WIDTH_MASK 0x00000FC0 -+ - /* FSL imm mask for get, put instructions. */ - #define RFSL_MASK 0x000000F - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch new file mode 100644 index 00000000..3a069fdf --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch @@ -0,0 +1,1891 @@ +From 510b596b8cd25ccb3563555190d5396c7b378522 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 31 Jan 2019 14:36:00 +0530 +Subject: [PATCH 06/54] Adding 64 bit MB support Added new architecture to + Microblaze 64-bit support to GDB Signed-off-by :Nagaraju Mekala + Signed-off-by :Mahesh Bodapati + +Conflicts: + gdb/Makefile.in + +Conflicts: + bfd/cpu-microblaze.c + gdb/microblaze-tdep.c + ld/Makefile.am + ld/Makefile.in + opcodes/microblaze-dis.c + +Conflicts: + bfd/configure + gas/config/tc-microblaze.c + ld/Makefile.in + opcodes/microblaze-opcm.h + +Conflicts: + gdb/microblaze-tdep.c + +Conflicts: + bfd/elf32-microblaze.c + gas/config/tc-microblaze.c + gdb/features/Makefile + gdb/features/microblaze-with-stack-protect.c + gdb/microblaze-tdep.c + gdb/regformats/microblaze-with-stack-protect.dat + gdbserver/linux-microblaze-low.c + include/elf/common.h + +Signed-off-by: Aayush Misra +--- + bfd/Makefile.am | 2 + + bfd/Makefile.in | 3 + + bfd/archures.c | 2 + + bfd/bfd-in2.h | 31 +++- + bfd/config.bfd | 4 + + bfd/configure | 2 + + bfd/cpu-microblaze.c | 55 +++++- + bfd/elf32-microblaze.c | 155 ++++++++++++++-- + bfd/libbfd.h | 3 + + bfd/reloc.c | 20 +++ + bfd/targets.c | 6 + + gdb/features/Makefile | 2 + + gdb/features/microblaze-core.xml | 6 +- + gdb/features/microblaze-stack-protect.xml | 4 +- + gdb/features/microblaze-with-stack-protect.c | 8 +- + gdb/features/microblaze.c | 6 +- + gdb/features/microblaze64-core.xml | 69 ++++++++ + gdb/features/microblaze64-stack-protect.xml | 12 ++ + .../microblaze64-with-stack-protect.c | 79 +++++++++ + .../microblaze64-with-stack-protect.xml | 12 ++ + gdb/features/microblaze64.c | 77 ++++++++ + gdb/features/microblaze64.xml | 11 ++ + gdb/microblaze-linux-tdep.c | 36 +++- + gdb/microblaze-tdep.c | 125 +++++++++---- + gdb/microblaze-tdep.h | 4 +- + include/elf/common.h | 1 + + include/elf/microblaze.h | 4 + + opcodes/microblaze-dis.c | 51 +++++- + opcodes/microblaze-opc.h | 165 +++++++++++++++++- + opcodes/microblaze-opcm.h | 28 ++- + 30 files changed, 896 insertions(+), 87 deletions(-) + create mode 100644 gdb/features/microblaze64-core.xml + create mode 100644 gdb/features/microblaze64-stack-protect.xml + create mode 100644 gdb/features/microblaze64-with-stack-protect.c + create mode 100644 gdb/features/microblaze64-with-stack-protect.xml + create mode 100644 gdb/features/microblaze64.c + create mode 100644 gdb/features/microblaze64.xml + +diff --git a/bfd/Makefile.am b/bfd/Makefile.am +index 378c13198d6..089d86b6191 100644 +--- a/bfd/Makefile.am ++++ b/bfd/Makefile.am +@@ -568,6 +568,7 @@ BFD64_BACKENDS = \ + elf64-ppc.lo \ + elf64-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -615,6 +616,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +diff --git a/bfd/Makefile.in b/bfd/Makefile.in +index 8d09f6fa4af..d9fe20f502b 100644 +--- a/bfd/Makefile.in ++++ b/bfd/Makefile.in +@@ -1025,6 +1025,7 @@ BFD64_BACKENDS = \ + elf64-ppc.lo \ + elf64-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -1072,6 +1073,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +@@ -1646,6 +1648,7 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@ +diff --git a/bfd/archures.c b/bfd/archures.c +index b59979e60ac..2994a09bc37 100644 +--- a/bfd/archures.c ++++ b/bfd/archures.c +@@ -515,6 +515,8 @@ DESCRIPTION + . bfd_arch_lm32, {* Lattice Mico32. *} + .#define bfd_mach_lm32 1 + . bfd_arch_microblaze,{* Xilinx MicroBlaze. *} ++.#define bfd_mach_microblaze 1 ++.#define bfd_mach_microblaze64 2 + . bfd_arch_kvx, {* Kalray VLIW core of the MPPA processor family *} + .#define bfd_mach_kv3_unknown 0 + .#define bfd_mach_kv3_1 1 +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index eddb9902f5e..9db63f254a3 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -1771,6 +1771,8 @@ enum bfd_architecture + bfd_arch_lm32, /* Lattice Mico32. */ + #define bfd_mach_lm32 1 + bfd_arch_microblaze,/* Xilinx MicroBlaze. */ ++#define bfd_mach_microblaze 1 ++#define bfd_mach_microblaze64 2 + bfd_arch_kvx, /* Kalray VLIW core of the MPPA processor family */ + #define bfd_mach_kv3_unknown 0 + #define bfd_mach_kv3_1 1 +@@ -6461,16 +6463,41 @@ value relative to the read-write small data area anchor */ + expressions of the form "Symbol Op Symbol" */ + BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative ++/* This is a 32 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_NONE, ++ BFD_RELOC_MICROBLAZE_32_NONE, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_PCREL, ++ ++/* This is a 64 bit reloc that stores the 32 bit relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ ++/* This is a 64 bit reloc that stores the 32 bit relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_EA64, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imm instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). The relocation is ++PC-relative GOT offset */ ++ BFD_RELOC_MICROBLAZE_64_GPC, ++ + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + GOT offset */ +diff --git a/bfd/config.bfd b/bfd/config.bfd +index 08129e6a8cb..3a7d427778c 100644 +--- a/bfd/config.bfd ++++ b/bfd/config.bfd +@@ -884,11 +884,15 @@ case "${targ}" in + microblazeel*-*) + targ_defvec=microblaze_elf32_le_vec + targ_selvecs=microblaze_elf32_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + microblaze*-*) + targ_defvec=microblaze_elf32_vec + targ_selvecs=microblaze_elf32_le_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + #ifdef BFD64 +diff --git a/bfd/configure b/bfd/configure +index f0a07ff675f..b2afdcf9bec 100755 +--- a/bfd/configure ++++ b/bfd/configure +@@ -14062,6 +14062,8 @@ do + rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; + s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; + score_elf32_be_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;; + score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;; + sh_coff_vec) tb="$tb coff-sh.lo $coff" ;; +diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c +index c14b170f94b..7557b3de7b3 100644 +--- a/bfd/cpu-microblaze.c ++++ b/bfd/cpu-microblaze.c +@@ -23,13 +23,30 @@ + #include "bfd.h" + #include "libbfd.h" + +-const bfd_arch_info_type bfd_microblaze_arch = ++const bfd_arch_info_type bfd_microblaze_arch[] = ++{ ++#if BFD_DEFAULT_TARGET_SIZE == 64 ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze64, /* 64 bit Machine */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ false, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, + { + 32, /* Bits in a word. */ + 32, /* Bits in an address. */ + 8, /* Bits in a byte. */ + bfd_arch_microblaze, /* Architecture number. */ +- 0, /* Machine number - 0 for now. */ ++ bfd_mach_microblaze, /* Machine number - 0 for now. */ + "microblaze", /* Architecture name. */ + "MicroBlaze", /* Printable name. */ + 3, /* Section align power. */ +@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_arch = + bfd_arch_default_fill, /* Default fill. */ + NULL, /* Next in list. */ + 0 /* Maximum offset of a reloc from the start of an insn. */ ++} ++#else ++{ ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze, /* 32 bit Machine */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ true, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ bfd_mach_microblaze64, /* 64 bit Machine */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ false, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ NULL, /* Next in list. */ ++ 0 ++} ++#endif + }; +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 487ddeafc5a..6ba28e757be 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -114,6 +114,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + true), /* PC relative offset? */ + ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ + 0, /* Rightshift. */ +@@ -174,7 +188,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + false), /* PC relative offset? */ + +- /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_32_NONE",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ + HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ + 0, /* Rightshift. */ + 0, /* Size. */ +@@ -264,6 +292,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + true), /* PC relative offset? */ + ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ + /* A 64 bit GOT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ + 0, /* Rightshift. */ +@@ -560,6 +603,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_NONE: + microblaze_reloc = R_MICROBLAZE_NONE; + break; ++ case BFD_RELOC_MICROBLAZE_32_NONE: ++ microblaze_reloc = R_MICROBLAZE_32_NONE; ++ break; + case BFD_RELOC_MICROBLAZE_64_NONE: + microblaze_reloc = R_MICROBLAZE_64_NONE; + break; +@@ -600,9 +646,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; ++ case BFD_RELOC_MICROBLAZE_64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: + microblaze_reloc = R_MICROBLAZE_GOTPC_64; + break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOT: + microblaze_reloc = R_MICROBLAZE_GOT_64; + break; +@@ -1564,7 +1616,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) + { + relocation += addend; +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { +@@ -1969,8 +2021,7 @@ microblaze_elf_relax_section (bfd *abfd, + else + symval += irel->r_addend; + +- if ((symval & 0xffff8000) == 0 +- || (symval & 0xffff8000) == 0xffff8000) ++ if ((symval & 0xffff8000) == 0) + { + /* We can delete this instruction. */ + sdata->relax[sdata->relax_count].addr = irel->r_offset; +@@ -2034,15 +2085,44 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); + } + break; +- case R_MICROBLAZE_NONE: ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ case R_MICROBLAZE_32_NONE: + { + /* This was a PC-relative instruction that was + completely resolved. */ + size_t sfix, efix; ++ unsigned int val; + bfd_vma target_address; + target_address = irel->r_addend + irel->r_offset; + sfix = calc_fixup (irel->r_offset, 0, sec); + efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } + irel->r_addend -= (efix - sfix); + /* Should use HOWTO. */ + microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, +@@ -2059,8 +2139,8 @@ microblaze_elf_relax_section (bfd *abfd, + sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); + efix = calc_fixup (target_address, 0, sec); + irel->r_addend -= (efix - sfix); +- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset +- + INST_WORD_SIZE, irel->r_addend); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); + } + break; + } +@@ -2090,9 +2170,50 @@ microblaze_elf_relax_section (bfd *abfd, + irelscanend = irelocs + o->reloc_count; + for (irelscan = irelocs; irelscan < irelscanend; irelscan++) + { +- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) +- { +- isym = isymbuf + ELF32_R_SYM (irelscan->r_info); ++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) ++ { ++ unsigned int val; ++ ++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); ++ ++ /* hax: We only do the following fixup for debug location lists. */ ++ if (strcmp(".debug_loc", o->name)) ++ continue; ++ ++ /* This was a PC-relative instruction that was completely resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ if (val != irelscan->r_addend) { ++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) ++ { ++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx +@@ -2149,7 +2270,7 @@ microblaze_elf_relax_section (bfd *abfd, + elf_section_data (o)->this_hdr.contents = ocontents; + } + } +- irelscan->r_addend -= calc_fixup (irel->r_addend ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend + + isym->st_value, + 0, + sec); +@@ -3490,6 +3611,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd, + return true; + } + ++ ++static bool ++elf_microblaze_object_p (bfd *abfd) ++{ ++ /* Set the right machine number for an s390 elf32 file. */ ++ return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze); ++} ++ + /* Hook called by the linker routine which adds symbols from an object + file. We use it to put .comm items in .sbss, and not .bss. */ + +@@ -3560,8 +3689,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd, + #define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol + #define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections + #define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook +- +-#define elf_backend_grok_prstatus microblaze_elf_grok_prstatus +-#define elf_backend_grok_psinfo microblaze_elf_grok_psinfo ++#define elf_backend_object_p elf_microblaze_object_p + + #include "elf32-target.h" +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index d5f42f22c08..b0e898bf815 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -3010,6 +3010,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_ROSDA", + "BFD_RELOC_MICROBLAZE_32_RWSDA", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", ++ "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", + "BFD_RELOC_MICROBLAZE_64_GOTPC", + "BFD_RELOC_MICROBLAZE_64_GOT", +@@ -3017,6 +3018,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", + "BFD_RELOC_MICROBLAZE_32_GOTOFF", + "BFD_RELOC_MICROBLAZE_COPY", ++ "BFD_RELOC_MICROBLAZE_64", ++ "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_64_TLS", + "BFD_RELOC_MICROBLAZE_64_TLSGD", + "BFD_RELOC_MICROBLAZE_64_TLSLD", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index 2ac883d0eac..278876e765e 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6694,6 +6694,12 @@ ENUM + ENUMDOC + This is a 32 bit reloc for the microblaze to handle + expressions of the form "Symbol Op Symbol" ++ENUM ++ BFD_RELOC_MICROBLAZE_32_NONE ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imm instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC +@@ -7933,6 +7939,20 @@ ENUMX + ENUMDOC + Tilera TILE-Gx Relocations. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_BPF_64 + ENUMX +diff --git a/bfd/targets.c b/bfd/targets.c +index 63b3abbd287..c48c0929157 100644 +--- a/bfd/targets.c ++++ b/bfd/targets.c +@@ -799,6 +799,8 @@ extern const bfd_target mep_elf32_le_vec; + extern const bfd_target metag_elf32_vec; + extern const bfd_target microblaze_elf32_vec; + extern const bfd_target microblaze_elf32_le_vec; ++extern const bfd_target microblaze_elf64_vec; ++extern const bfd_target microblaze_elf64_le_vec; + extern const bfd_target mips_ecoff_be_vec; + extern const bfd_target mips_ecoff_le_vec; + extern const bfd_target mips_ecoff_bele_vec; +@@ -1166,6 +1168,10 @@ static const bfd_target * const _bfd_target_vector[] = + + &metag_elf32_vec, + ++#ifdef BFD64 ++ µblaze_elf64_vec, ++ µblaze_elf64_le_vec, ++#endif + µblaze_elf32_vec, + + &mips_ecoff_be_vec, +diff --git a/gdb/features/Makefile b/gdb/features/Makefile +index 0af9d67c2f7..ee053b7557c 100644 +--- a/gdb/features/Makefile ++++ b/gdb/features/Makefile +@@ -102,7 +102,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH)) + # to make on the command line. + XMLTOC = \ + microblaze-with-stack-protect.xml \ ++ microblaze64-with-stack-protect.xml \ + microblaze.xml \ ++ microblaze64.xml \ + mips-dsp-linux.xml \ + mips-linux.xml \ + mips64-dsp-linux.xml \ +diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml +index d49aa075bae..ac052365773 100644 +--- a/gdb/features/microblaze-core.xml ++++ b/gdb/features/microblaze-core.xml +@@ -8,7 +8,7 @@ + + + +- ++ + + + +@@ -39,7 +39,7 @@ + + + +- ++ + + + +@@ -64,4 +64,6 @@ + + + ++ ++ + +diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml +index a5ffe2e50b1..b15369e03a4 100644 +--- a/gdb/features/microblaze-stack-protect.xml ++++ b/gdb/features/microblaze-stack-protect.xml +@@ -7,6 +7,6 @@ + + + +- +- ++ ++ + +diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c +index 574dc02db67..8ab9565a047 100644 +--- a/gdb/features/microblaze-with-stack-protect.c ++++ b/gdb/features/microblaze-with-stack-protect.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect"); +- tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); + + tdesc_microblaze_with_stack_protect = result.release (); + } +diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c +index 8f1fb0a142f..ed12e5bcfd2 100644 +--- a/gdb/features/microblaze.c ++++ b/gdb/features/microblaze.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); + + tdesc_microblaze = result.release (); + } +diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml +new file mode 100644 +index 00000000000..96e99e2fb24 +--- /dev/null ++++ b/gdb/features/microblaze64-core.xml +@@ -0,0 +1,69 @@ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml +new file mode 100644 +index 00000000000..1bbf5fc3cea +--- /dev/null ++++ b/gdb/features/microblaze64-stack-protect.xml +@@ -0,0 +1,12 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c +new file mode 100644 +index 00000000000..a4de4666c76 +--- /dev/null ++++ b/gdb/features/microblaze64-with-stack-protect.c +@@ -0,0 +1,79 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze-with-stack-protect.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze64_with_stack_protect; ++static void ++initialize_tdesc_microblaze64_with_stack_protect (void) ++{ ++ target_desc_up result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ ++ feature = tdesc_create_feature (result.get() , "org.gnu.gdb.microblaze64.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ ++ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.stack-protect"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze64_with_stack_protect = result.release(); ++} +diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml +new file mode 100644 +index 00000000000..0e9f01611f3 +--- /dev/null ++++ b/gdb/features/microblaze64-with-stack-protect.xml +@@ -0,0 +1,12 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c +new file mode 100644 +index 00000000000..8ab7a90dd95 +--- /dev/null ++++ b/gdb/features/microblaze64.c +@@ -0,0 +1,77 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze64; ++static void ++initialize_tdesc_microblaze64 (void) ++{ ++ target_desc_up result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ ++ feature = tdesc_create_feature (result.get(), "org.gnu.gdb.microblaze64.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze64 = result.release(); ++} +diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml +new file mode 100644 +index 00000000000..515d18e65cf +--- /dev/null ++++ b/gdb/features/microblaze64.xml +@@ -0,0 +1,11 @@ ++ ++ ++ ++ ++ ++ ++ +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 5b57bb4d3ba..39592a43f7c 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -40,6 +40,7 @@ + #include "features/microblaze-linux.c" + + static int microblaze_debug_flag = 0; ++int MICROBLAZE_REGISTER_SIZE=4; + + static void + microblaze_debug (const char *fmt, ...) +@@ -55,6 +56,7 @@ microblaze_debug (const char *fmt, ...) + } + } + ++#if 0 + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -86,6 +88,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + return val; + } + ++#endif ++ + static void + microblaze_linux_sigtramp_cache (frame_info_ptr next_frame, + struct trad_frame_cache *this_cache, +@@ -147,8 +151,8 @@ microblaze_linux_init_abi (struct gdbarch_info info, + + linux_init_abi (info, gdbarch, 0); + +- set_gdbarch_memory_remove_breakpoint (gdbarch, +- microblaze_linux_memory_remove_breakpoint); ++ // set_gdbarch_memory_remove_breakpoint (gdbarch, ++ // microblaze_linux_memory_remove_breakpoint); + + /* Shared library handling. */ + set_solib_svr4_fetch_link_map_offsets (gdbarch, +@@ -160,10 +164,30 @@ microblaze_linux_init_abi (struct gdbarch_info info, + + /* BFD target for core files. */ + if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) +- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze"); ++ MICROBLAZE_REGISTER_SIZE=8; ++ } ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ } + else +- set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) { ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel"); ++ MICROBLAZE_REGISTER_SIZE=8; ++ } ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ } + ++ switch (info.bfd_arch_info->mach) ++ { ++ case bfd_mach_microblaze64: ++ set_gdbarch_ptr_bit (gdbarch, 64); ++ break; ++ } + + /* Shared library handling. */ + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); +@@ -178,7 +202,9 @@ void _initialize_microblaze_linux_tdep (); + void + _initialize_microblaze_linux_tdep () + { +- gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, ++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, ++ microblaze_linux_init_abi); ++ gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, + microblaze_linux_init_abi); + initialize_tdesc_microblaze_linux (); + } +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 066602b385a..9450882e850 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -40,7 +40,9 @@ + #include "remote.h" + + #include "features/microblaze-with-stack-protect.c" ++#include "features/microblaze64-with-stack-protect.c" + #include "features/microblaze.c" ++#include "features/microblaze64.c" + + /* Instruction macros used for analyzing the prologue. */ + /* This set of instruction macros need to be changed whenever the +@@ -75,12 +77,13 @@ static const char * const microblaze_register_names[] = + "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6", + "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11", + "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi", +- "rslr", "rshr" ++ "slr", "shr" + }; + + #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names) + + static unsigned int microblaze_debug_flag = 0; ++int reg_size = 4; + + #define microblaze_debug(fmt, ...) \ + debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \ +@@ -128,6 +131,15 @@ microblaze_fetch_instruction (CORE_ADDR pc) + constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; + + typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; ++static CORE_ADDR ++microblaze_store_arguments (struct regcache *regcache, int nargs, ++ struct value **args, CORE_ADDR sp, ++ int struct_return, CORE_ADDR struct_addr) ++{ ++ error (_("store_arguments not implemented")); ++ return sp; ++} ++#if 0 + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -146,7 +158,6 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + /* Make sure we see the memory breakpoints. */ + scoped_restore restore_memory + = make_scoped_restore_show_memory_breakpoints (1); +- + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the +@@ -161,6 +172,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + return val; + } + ++#endif + /* Allocate and initialize a frame cache. */ + + static struct microblaze_frame_cache * +@@ -583,11 +595,11 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache, + { + case 1: /* return last byte in the register. */ + regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); +- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1); ++ memcpy(valbuf, buf + reg_size - 1, 1); + return; + case 2: /* return last 2 bytes in register. */ + regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf); +- memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2); ++ memcpy(valbuf, buf + reg_size - 2, 2); + return; + case 4: /* for sizes 4 or 8, copy the required length. */ + case 8: +@@ -753,6 +765,12 @@ microblaze_software_single_step (struct regcache *regcache) + } + #endif + ++static void ++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) ++{ ++ regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc); ++} ++ + static int dwarf2_to_reg_map[78] = + { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ + 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ +@@ -787,13 +805,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) + static void + microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) + { ++ + register_remote_g_packet_guess (gdbarch, + 4 * MICROBLAZE_NUM_CORE_REGS, +- tdesc_microblaze); ++ tdesc_microblaze64); + + register_remote_g_packet_guess (gdbarch, + 4 * MICROBLAZE_NUM_REGS, +- tdesc_microblaze_with_stack_protect); ++ tdesc_microblaze64_with_stack_protect); + } + + void +@@ -801,7 +820,7 @@ microblaze_supply_gregset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *gregs) + { +- const unsigned int *regs = (const unsigned int *)gregs; ++ const gdb_byte *regs = (const gdb_byte *) gregs; + if (regnum >= 0) + regcache->raw_supply (regnum, regs + regnum); + +@@ -809,7 +828,7 @@ microblaze_supply_gregset (const struct regset *regset, + int i; + + for (i = 0; i < 50; i++) { +- regcache->raw_supply (i, regs + i); ++ regcache->raw_supply (regnum, regs + i); + } + } + } +@@ -832,6 +851,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, + } + + ++static void ++make_regs (struct gdbarch *arch) ++{ ++ struct gdbarch_tdep *tdep = gdbarch_tdep (arch); ++ int mach = gdbarch_bfd_arch_info (arch)->mach; ++ ++ if (mach == bfd_mach_microblaze64) ++ { ++ set_gdbarch_ptr_bit (arch, 64); ++ } ++} + + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -844,8 +874,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + if (arches != NULL) + return arches->gdbarch; + if (tdesc == NULL) +- tdesc = tdesc_microblaze; +- ++ { ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } ++ else ++ tdesc = tdesc_microblaze; ++ } + /* Check any target description for validity. */ + if (tdesc_has_registers (tdesc)) + { +@@ -853,31 +890,42 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- feature = tdesc_find_feature (tdesc, +- "org.gnu.gdb.microblaze.core"); ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze64.core"); ++ else ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze.core"); + if (feature == NULL) + return NULL; + tdesc_data = tdesc_data_alloc (); + + valid_p = 1; +- for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++) +- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, +- microblaze_register_names[i]); +- feature = tdesc_find_feature (tdesc, +- "org.gnu.gdb.microblaze.stack-protect"); ++ for (i = 0; i < MICROBLAZE_NUM_REGS; i++) ++ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, ++ microblaze_register_names[i]); ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze64.stack-protect"); ++ else ++ feature = tdesc_find_feature (tdesc, ++ "org.gnu.gdb.microblaze.stack-protect"); + if (feature != NULL) +- { +- valid_p = 1; +- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), +- MICROBLAZE_SLR_REGNUM, +- "rslr"); +- valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), +- MICROBLAZE_SHR_REGNUM, +- "rshr"); +- } ++ { ++ valid_p = 1; ++ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), ++ MICROBLAZE_SLR_REGNUM, ++ "slr"); ++ valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), ++ MICROBLAZE_SHR_REGNUM, ++ "shr"); ++ } + + if (!valid_p) +- return NULL; ++ { ++ // tdesc_data_cleanup (tdesc_data.get ()); ++ return NULL; ++ } + } + + /* Allocate space for the new architecture. */ +@@ -897,7 +945,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + /* Register numbers of various important registers. */ + set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); + set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); ++ ++ /* Register set. ++ make_regs (gdbarch); */ ++ switch (info.bfd_arch_info->mach) ++ { ++ case bfd_mach_microblaze64: ++ set_gdbarch_ptr_bit (gdbarch, 64); ++ break; ++ } + ++ + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); + +@@ -917,7 +975,9 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + microblaze_breakpoint::bp_from_kind); +- set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); ++// set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); ++ ++// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + + set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + +@@ -925,7 +985,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); + +- microblaze_register_g_packet_guesses (gdbarch); ++ //microblaze_register_g_packet_guesses (gdbarch); + + frame_base_set_default (gdbarch, µblaze_frame_base); + +@@ -940,12 +1000,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); + //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); + +- /* If we have register sets, enable the generic core file support. */ ++ /* If we have register sets, enable the generic core file support. + if (tdep->gregset) { + set_gdbarch_iterate_over_regset_sections (gdbarch, + microblaze_iterate_over_regset_sections); +- } +- ++ }*/ + return gdbarch; + } + +@@ -957,6 +1016,8 @@ _initialize_microblaze_tdep () + + initialize_tdesc_microblaze_with_stack_protect (); + initialize_tdesc_microblaze (); ++ initialize_tdesc_microblaze64_with_stack_protect (); ++ initialize_tdesc_microblaze64 (); + /* Debug this files internals. */ + add_setshow_zuinteger_cmd ("microblaze", class_maintenance, + µblaze_debug_flag, _("\ +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 21f206777f0..542cdd82070 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -28,7 +28,7 @@ struct microblaze_gregset + microblaze_gregset() {} + unsigned int gregs[32]; + unsigned int fpregs[32]; +- unsigned int pregs[16]; ++ unsigned int pregs[18]; + }; + + struct microblaze_gdbarch_tdep : gdbarch_tdep_base +@@ -134,7 +134,7 @@ struct microblaze_frame_cache + struct trad_frame_saved_reg *saved_regs; + }; + /* All registers are 32 bits. */ +-#define MICROBLAZE_REGISTER_SIZE 4 ++//#define MICROBLAZE_REGISTER_SIZE 8 + + /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. + Only used for native debugging. */ +diff --git a/include/elf/common.h b/include/elf/common.h +index 244b13361e5..6395f69426f 100644 +--- a/include/elf/common.h ++++ b/include/elf/common.h +@@ -360,6 +360,7 @@ + #define EM_U16_U8CORE 260 /* LAPIS nX-U16/U8 */ + #define EM_TACHYUM 261 /* Tachyum */ + #define EM_56800EF 262 /* NXP 56800EF Digital Signal Controller (DSC) */ ++#define EM_MB_64 263 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ + + /* If it is necessary to assign new unofficial EM_* values, please pick large + random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision +diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h +index fecdd7e4831..3306e3c3ad6 100644 +--- a/include/elf/microblaze.h ++++ b/include/elf/microblaze.h +@@ -61,6 +61,10 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type) + RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30) /* PC-relative TEXT offset. */ + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */ + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */ ++ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33) ++ RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34) ++ RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35) /* GOT entry offset. */ ++ + END_RELOC_NUMBERS (R_MICROBLAZE_max) + + /* Global base address names. */ +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 12981abfea1..c910f2ff210 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -33,6 +33,7 @@ + #define get_field_r1(buf, instr) get_field (buf, instr, RA_MASK, RA_LOW) + #define get_field_r2(buf, instr) get_field (buf, instr, RB_MASK, RB_LOW) + #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) ++#define get_int_field_imml(instr) ((instr & IMML_MASK) >> IMM_LOW) + #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) + + #define NUM_STRBUFS 3 +@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr) + } + + static char * +-get_field_imm5 (struct string_buf *buf, long instr) ++get_field_imml (struct string_buf *buf, long instr) + { + char *p = strbuf (buf); + +- sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); ++ sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW)); ++ return p; ++} ++ ++static char * ++get_field_imms (struct string_buf *buf, long instr) ++{ ++ char *p = strbuf (buf); ++ ++ sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW)); + return p; + } + +@@ -90,6 +100,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr) + return p; + } + ++static char * ++get_field_immw (struct string_buf *buf, long instr) ++{ ++ char *p = strbuf (buf); ++ ++ if (instr & 0x00004000) ++ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ ++ else ++ sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */ ++ return p; ++} ++ + static char * + get_field_rfsl (struct string_buf *buf, long instr) + { +@@ -296,9 +318,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; +- case INST_TYPE_RD_R1_IMM5: ++ case INST_TYPE_RD_R1_IMML: ++ print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), ++ get_field_r1(&buf, inst), get_field_imm (&buf, inst)); ++ /* TODO: Also print symbol */ ++ break; ++ case INST_TYPE_RD_R1_IMMS: + print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), +- get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst)); ++ get_field_r1(&buf, inst), get_field_imms (&buf, inst)); + break; + case INST_TYPE_RD_RFSL: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), +@@ -402,9 +429,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; +- case INST_TYPE_RD_R2: +- print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), +- get_field_r2 (&buf, inst)); ++ case INST_TYPE_IMML: ++ print_func (stream, "\t%s", get_field_imml (&buf, inst)); ++ /* TODO: Also print symbol */ ++ break; ++ case INST_TYPE_RD_R2: ++ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst)); + break; + case INST_TYPE_R2: + print_func (stream, "\t%s", get_field_r2 (&buf, inst)); +@@ -427,7 +457,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + /* For mbar 16 or sleep insn. */ + case INST_TYPE_NONE: + break; +- /* For tuqula instruction */ ++ /* For bit field insns. */ ++ case INST_TYPE_RD_R1_IMMW_IMMS: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), ++ get_field_immw (&buf, inst), get_field_imms (&buf, inst)); ++ break; ++ /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (&buf, inst)); + break; +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 7398e9e246a..dc78712d67b 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -40,7 +40,7 @@ + #define INST_TYPE_RD_SPECIAL 11 + #define INST_TYPE_R1 12 + /* New instn type for barrel shift imms. */ +-#define INST_TYPE_RD_R1_IMM5 13 ++#define INST_TYPE_RD_R1_IMMS 13 + #define INST_TYPE_RD_RFSL 14 + #define INST_TYPE_R1_RFSL 15 + +@@ -59,6 +59,15 @@ + /* For mbar. */ + #define INST_TYPE_IMM5 20 + ++/* For bsefi and bsifi */ ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 ++ ++/* For 64-bit instructions */ ++#define INST_TYPE_IMML 22 ++#define INST_TYPE_RD_R1_IMML 23 ++#define INST_TYPE_R1_IMML 24 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 ++ + #define INST_TYPE_NONE 25 + + +@@ -88,11 +97,14 @@ + #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ + #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ + #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ +-#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ ++#define OPCODE_MASK_H3 0xFC000700 /* High 6 bits and bits 21, 22, 23. */ ++#define OPCODE_MASK_H3B 0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22. */ + #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ ++#define OPCODE_MASK_H32B 0xFC00E000 /* High 6 bits and bit 16, 17, 18. */ + #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ + #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ ++#define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ + + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ +@@ -102,7 +114,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 300 ++#define MAX_OPCODES 412 + + const struct op_code_struct + { +@@ -120,6 +132,7 @@ const struct op_code_struct + /* More info about output format here. */ + } microblaze_opcodes[MAX_OPCODES] = + { ++ /* 32-bit instructions */ + {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, + {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, + {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, +@@ -156,9 +169,11 @@ const struct op_code_struct + {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, + {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, + {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, +- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, +- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, +- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, ++ {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, ++ {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, ++ {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, ++ {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, ++ {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, + {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst }, + {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst }, +@@ -260,9 +275,7 @@ const struct op_code_struct + {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */ + {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */ + {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */ +- {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ + {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */ +- {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, + {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, + {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, +@@ -418,6 +431,130 @@ const struct op_code_struct + {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */ + {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst }, + {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, ++ /* 64-bit instructions */ ++ {"addl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst }, ++ {"rsubl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst }, ++ {"addlc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst }, ++ {"rsublc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst }, ++ {"addlk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst }, ++ {"rsublk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst }, ++ {"addlkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst }, ++ {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst }, ++ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, ++ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, ++ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, ++ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, ++ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, ++ {"bslrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst }, ++ {"bsllli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst }, ++ {"bslrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst }, ++ {"bslrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst }, ++ {"bslefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst }, ++ {"bslifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst }, ++ {"orl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst }, ++ {"andl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst }, ++ {"xorl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst }, ++ {"andnl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst }, ++ {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst }, ++ {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst }, ++ {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst }, ++ {"srla", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst }, ++ {"srlc", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst }, ++ {"srll", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst }, ++ {"sextl8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst }, ++ {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst }, ++ {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst }, ++ {"brea", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst }, ++ {"bread", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst }, ++ {"breald", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst }, ++ {"beaeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst }, ++ {"bealeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst }, ++ {"beaeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst }, ++ {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst }, ++ {"beane", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst }, ++ {"bealne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst }, ++ {"beaned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst }, ++ {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst }, ++ {"bealt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst }, ++ {"beallt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst }, ++ {"bealtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst }, ++ {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst }, ++ {"beale", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst }, ++ {"bealle", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst }, ++ {"bealed", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst }, ++ {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst }, ++ {"beagt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst }, ++ {"bealgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst }, ++ {"beagtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst }, ++ {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst }, ++ {"beage", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst }, ++ {"bealge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst }, ++ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, ++ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, ++ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, ++ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, ++ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, ++ {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst }, ++ {"beaeqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst }, ++ {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */ ++ {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst }, ++ {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqid */ ++ {"beanei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst }, ++ {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */ ++ {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst }, ++ {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaneid */ ++ {"bealti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst }, ++ {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */ ++ {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst }, ++ {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealtid */ ++ {"bealei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst }, ++ {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */ ++ {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst }, ++ {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealeid */ ++ {"beagti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst }, ++ {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */ ++ {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst }, ++ {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagtid */ ++ {"beagei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst }, ++ {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */ ++ {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst }, ++ {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beageid */ ++ {"ll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst }, ++ {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst }, ++ {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst }, ++ {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst }, ++ {"lli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ ++ {"sli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ ++ {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */ ++ {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst }, ++ {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst }, ++ {"dmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst }, ++ {"ddiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst }, ++ {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst }, ++ {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst }, ++ {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst }, ++ {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst }, ++ {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst }, ++ {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst }, ++ {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst }, ++ {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst }, ++ {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst }, ++ {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst }, ++ {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ ++ {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ ++ + {"", 0, 0, 0, 0, 0, 0, 0, 0}, + }; + +@@ -438,5 +575,17 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM5 ((int) 0x00000000) + #define MAX_IMM5 ((int) 0x0000001f) + ++#define MIN_IMM6 ((int) 0x00000000) ++#define MAX_IMM6 ((int) 0x0000003f) ++ ++#define MIN_IMM_WIDTH ((int) 0x00000001) ++#define MAX_IMM_WIDTH ((int) 0x00000020) ++ ++#define MIN_IMM6_WIDTH ((int) 0x00000001) ++#define MAX_IMM6_WIDTH ((int) 0x00000040) ++ ++#define MIN_IMML ((long) 0xffffff8000000000L) ++#define MAX_IMML ((long) 0x0000007fffffffffL) ++ + #endif /* MICROBLAZE_OPC */ + +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index c91b002d951..3923f6258d8 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -25,11 +25,12 @@ + + enum microblaze_instr + { ++ /* 32-bit instructions */ + add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, + addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, + mulh, mulhu, mulhsu, swapb, swaph, + idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, +- ncget, ncput, muli, bslli, bsrai, bsrli, mului, ++ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului, + /* 'or/and/xor' are C++ keywords. */ + microblaze_or, microblaze_and, microblaze_xor, + andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, +@@ -39,8 +40,8 @@ enum microblaze_instr + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, + bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, +- sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, +- sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, ++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli, ++ sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv, + fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, + /* 'fsqrt' is a glibc:math.h symbol. */ + fint, microblaze_fsqrt, +@@ -59,6 +60,18 @@ enum microblaze_instr + aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, + eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, ++ ++ /* 64-bit instructions */ ++ addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, ++ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, ++ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, ++ bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt, ++ bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid, ++ beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti, ++ beagtid, beagei, beageid, imml, ll, llr, sl, slr, ++ dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge, ++ dcmp_un, dbl, dlong, dsqrt, + invalid_inst + }; + +@@ -130,18 +143,25 @@ enum microblaze_instr_type + #define RB_LOW 11 /* Low bit for RB. */ + #define IMM_LOW 0 /* Low bit for immediate. */ + #define IMM_MBAR 21 /* low bit for mbar instruction. */ ++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */ + + #define RD_MASK 0x03E00000 + #define RA_MASK 0x001F0000 + #define RB_MASK 0x0000F800 + #define IMM_MASK 0x0000FFFF ++#define IMML_MASK 0x00FFFFFF + +-/* Imm mask for barrel shifts. */ ++/* Imm masks for barrel shifts. */ + #define IMM5_MASK 0x0000001F ++#define IMM6_MASK 0x0000003F + + /* Imm mask for mbar. */ + #define IMM5_MBAR_MASK 0x03E00000 + ++/* Imm masks for extract/insert width. */ ++#define IMM5_WIDTH_MASK 0x000007C0 ++#define IMM6_WIDTH_MASK 0x00000FC0 ++ + /* FSL imm mask for get, put instructions. */ + #define RFSL_MASK 0x000000F + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch deleted file mode 100644 index 9d12cc53..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch +++ /dev/null @@ -1,38 +0,0 @@ -From ef411b49f3b2c9e4048eb273f43ab4ee96f96b7e Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 19 Apr 2021 14:33:27 +0530 -Subject: [PATCH 6/8] [Patch,MicroBlaze] : these changes will make 64 bit - vectors as default target types when we built gdb with microblaze 64 bit type - targets,for instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64 - -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - ---- - bfd/config.bfd | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/bfd/config.bfd b/bfd/config.bfd -index 5e9ba3d9805..deb3d078439 100644 ---- a/bfd/config.bfd -+++ b/bfd/config.bfd -@@ -856,7 +856,15 @@ case "${targ}" in - targ_defvec=metag_elf32_vec - targ_underscore=yes - ;; -+ microblazeel*-*64) -+ targ_defvec=microblaze_elf64_le_vec -+ targ_selvecs=microblaze_elf64_vec -+ ;; - -+ microblaze*-*64) -+ targ_defvec=microblaze_elf64_vec -+ targ_selvecs=microblaze_elf64_le_vec -+ ;; - microblazeel*-*) - targ_defvec=microblaze_elf32_le_vec - targ_selvecs=microblaze_elf32_vec --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch deleted file mode 100644 index ec11e7be..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch +++ /dev/null @@ -1,300 +0,0 @@ -From d2f145ec8e4e149e055adc74e92016447af91806 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 9 Nov 2021 16:19:17 +0530 -Subject: [PATCH 7/8] [Patch,MicroBlaze] : Added m64 abi for 64 bit target - descriptions. set m64 abi for 64 bit elf. - -Conflicts: - gdb/microblaze-tdep.c - gdb/microblaze-tdep.h -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - ---- - gdb/features/microblaze64.xml | 1 + - gdb/microblaze-tdep.c | 159 ++++++++++++++++++++++++++++++++-- - gdb/microblaze-tdep.h | 13 ++- - 3 files changed, 165 insertions(+), 8 deletions(-) - -diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml -index 515d18e65cf..9c1b7d22003 100644 ---- a/gdb/features/microblaze64.xml -+++ b/gdb/features/microblaze64.xml -@@ -7,5 +7,6 @@ - - - -+ microblaze64 - - -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index c347bb9516b..d83072cdaef 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -65,8 +65,95 @@ - #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \ - ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0) - -+static const char *microblaze_abi_string; -+ -+static const char *const microblaze_abi_strings[] = { -+ "auto", -+ "m64", -+}; -+ -+enum microblaze_abi -+microblaze_abi (struct gdbarch *gdbarch) -+{ -+ microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); -+ return tdep->microblaze_abi; -+} - /* The registers of the Xilinx microblaze processor. */ - -+ static struct cmd_list_element *setmicroblazecmdlist = NULL; -+ static struct cmd_list_element *showmicroblazecmdlist = NULL; -+ -+static void -+microblaze_abi_update (const char *ignore_args, -+ int from_tty, struct cmd_list_element *c) -+{ -+ struct gdbarch_info info; -+ -+ /* Force the architecture to update, and (if it's a microblaze architecture) -+ * microblaze_gdbarch_init will take care of the rest. */ -+// gdbarch_info_init (&info); -+ gdbarch_update_p (info); -+} -+ -+ -+static enum microblaze_abi -+global_microblaze_abi (void) -+{ -+ int i; -+ -+ for (i = 0; microblaze_abi_strings[i] != NULL; i++) -+ if (microblaze_abi_strings[i] == microblaze_abi_string) -+ return (enum microblaze_abi) i; -+ -+// internal_error (__FILE__, __LINE__, _("unknown ABI string")); -+} -+ -+static void -+show_microblaze_abi (struct ui_file *file, -+ int from_tty, -+ struct cmd_list_element *ignored_cmd, -+ const char *ignored_value) -+{ -+ enum microblaze_abi global_abi = global_microblaze_abi (); -+ enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ()); -+ const char *actual_abi_str = microblaze_abi_strings[actual_abi]; -+ -+#if 1 -+ if (global_abi == MICROBLAZE_ABI_AUTO) -+ fprintf_filtered -+ (file, -+ "The microblaze ABI is set automatically (currently \"%s\").\n", -+ actual_abi_str); -+ else if (global_abi == actual_abi) -+ fprintf_filtered -+ (file, -+ "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n", -+ actual_abi_str); -+ else -+ { -+#endif -+ /* Probably shouldn't happen... */ -+ fprintf_filtered (file, -+ "The (auto detected) microblaze ABI \"%s\" is in use " -+ "even though the user setting was \"%s\".\n", -+ actual_abi_str, microblaze_abi_strings[global_abi]); -+ } -+} -+ -+static void -+show_microblaze_command (const char *args, int from_tty) -+{ -+ help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout); -+} -+ -+static void -+set_microblaze_command (const char *args, int from_tty) -+{ -+ printf_unfiltered -+ ("\"set microblaze\" must be followed by an appropriate subcommand.\n"); -+ help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout); -+} -+ - static const char * const microblaze_register_names[] = - { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", -@@ -85,9 +172,21 @@ static const char * const microblaze_register_names[] = - static unsigned int microblaze_debug_flag = 0; - int reg_size = 4; - -+unsigned int -+microblaze_abi_regsize (struct gdbarch *gdbarch) -+{ -+ switch (microblaze_abi (gdbarch)) -+ { -+ case MICROBLAZE_ABI_M64: -+ return 8; -+ default: -+ return 4; -+ } -+} -+ - #define microblaze_debug(fmt, ...) \ - debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \ -- fmt, ## __VA_ARGS__) -+ fmt, ## __VA_ARGS__) - - - /* Return the name of register REGNUM. */ -@@ -868,15 +967,30 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - { - struct gdbarch *gdbarch; - tdesc_arch_data_up tdesc_data; -+ enum microblaze_abi microblaze_abi, found_abi, wanted_abi; - const struct target_desc *tdesc = info.target_desc; - -+ /* What has the user specified from the command line? */ -+ wanted_abi = global_microblaze_abi (); -+ if (gdbarch_debug) -+ fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", -+ wanted_abi); -+ if (wanted_abi != MICROBLAZE_ABI_AUTO) -+ microblaze_abi = wanted_abi; -+ - /* If there is already a candidate, use it. */ - arches = gdbarch_list_lookup_by_info (arches, &info); -- if (arches != NULL) -+ if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) - return arches->gdbarch; -+ -+ if (microblaze_abi == MICROBLAZE_ABI_M64) -+ { -+ tdesc = tdesc_microblaze64; -+ reg_size = 8; -+ } - if (tdesc == NULL) - { -- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) - { - tdesc = tdesc_microblaze64; - reg_size = 8; -@@ -891,7 +1005,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - int valid_p; - int i; - -- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) - feature = tdesc_find_feature (tdesc, - "org.gnu.gdb.microblaze64.core"); - else -@@ -905,7 +1019,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - for (i = 0; i < MICROBLAZE_NUM_REGS; i++) - valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, - microblaze_register_names[i]); -- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) - feature = tdesc_find_feature (tdesc, - "org.gnu.gdb.microblaze64.stack-protect"); - else -@@ -955,7 +1069,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - set_gdbarch_ptr_bit (gdbarch, 64); - break; - } -- -+ if(microblaze_abi == MICROBLAZE_ABI_M64) -+ set_gdbarch_ptr_bit (gdbarch, 64); - - /* Map Dwarf2 registers to GDB registers. */ - set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); -@@ -1014,7 +1129,38 @@ void - _initialize_microblaze_tdep () - { - register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init); -+// static struct cmd_list_element *setmicroblazecmdlist = NULL; -+// static struct cmd_list_element *showmicroblazecmdlist = NULL; -+ -+ /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ - -+ add_setshow_prefix_cmd ("microblaze", no_class, -+ _("Various microblaze specific commands."), -+ _("Various microblaze specific commands."), -+ &setmicroblazecmdlist,&showmicroblazecmdlist, -+ &setlist,&showlist); -+#if 0 -+ add_prefix_cmd ("microblaze", no_class, set_microblaze_command, -+ _("Various microblaze specific commands."), -+ &setmicroblazecmdlist, "set microblaze ", 0, &setlist); -+ -+ add_prefix_cmd ("microblaze", no_class, show_microblaze_command, -+ _("Various microblaze specific commands."), -+ &showmicroblazecmdlist, "show microblaze ", 0, &showlist); -+#endif -+ -+ /* Allow the user to override the ABI. */ -+ add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings, -+ µblaze_abi_string, _("\ -+Set the microblaze ABI used by this program."), _("\ -+Show the microblaze ABI used by this program."), _("\ -+This option can be set to one of:\n\ -+ auto - the default ABI associated with the current binary\n\ -+ m64"), -+ microblaze_abi_update, -+ show_microblaze_abi, -+ &setmicroblazecmdlist, &showmicroblazecmdlist); -+ - initialize_tdesc_microblaze_with_stack_protect (); - initialize_tdesc_microblaze (); - initialize_tdesc_microblaze64_with_stack_protect (); -@@ -1029,5 +1175,4 @@ When non-zero, microblaze specific debugging is enabled."), - NULL, - &setdebuglist, &showdebuglist); - -- - } -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index f4d810303ca..babd6c36926 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -19,9 +19,17 @@ - - #ifndef MICROBLAZE_TDEP_H - #define MICROBLAZE_TDEP_H 1 -- -+#include "objfiles.h" - #include "gdbarch.h" - -+struct gdbarch; -+enum microblaze_abi -+ { -+ MICROBLAZE_ABI_AUTO = 0, -+ MICROBLAZE_ABI_M64, -+ }; -+ -+enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch); - /* Microblaze architecture-specific information. */ - struct microblaze_gregset - { -@@ -35,11 +43,14 @@ struct microblaze_gdbarch_tdep : gdbarch_tdep - { - int dummy; // declare something. - -+ enum microblaze_abi microblaze_abi {}; -+ enum microblaze_abi found_abi {}; - /* Register sets. */ - struct regset *gregset; - size_t sizeof_gregset; - struct regset *fpregset; - size_t sizeof_fpregset; -+ int register_size; - }; - - /* Register numbers. */ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch new file mode 100644 index 00000000..27c04153 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0007-these-changes-will-make-64-bit-vectors-as-default-ta.patch @@ -0,0 +1,35 @@ +From b6735e00ff7c60f8e66527402dd541b4217ce38f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 19 Apr 2021 14:33:27 +0530 +Subject: [PATCH 07/54] these changes will make 64 bit vectors as default + target types when we built gdb with microblaze 64 bit type targets,for + instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64 + +Signed-off-by: Aayush Misra +--- + bfd/config.bfd | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/bfd/config.bfd b/bfd/config.bfd +index 3a7d427778c..9a4b26be8f8 100644 +--- a/bfd/config.bfd ++++ b/bfd/config.bfd +@@ -880,7 +880,15 @@ case "${targ}" in + targ_defvec=metag_elf32_vec + targ_underscore=yes + ;; ++ microblazeel*-*64) ++ targ_defvec=microblaze_elf64_le_vec ++ targ_selvecs=microblaze_elf64_vec ++ ;; + ++ microblaze*-*64) ++ targ_defvec=microblaze_elf64_vec ++ targ_selvecs=microblaze_elf64_le_vec ++ ;; + microblazeel*-*) + targ_defvec=microblaze_elf32_le_vec + targ_selvecs=microblaze_elf32_vec +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch new file mode 100644 index 00000000..54e53f6f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Added-m64-abi-for-64-bit-target-descriptions.-set-m6.patch @@ -0,0 +1,4104 @@ +From 89f7a0c3e8b3bc37a37280bacec724f764503f38 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 9 Nov 2021 16:19:17 +0530 +Subject: [PATCH 08/54] Added m64 abi for 64 bit target descriptions. set m64 + abi for 64 bit elf. + +Conflicts: + gdb/microblaze-tdep.c + gdb/microblaze-tdep.h + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 3810 ++++++++++++++++++++++++++++++++++++++++ + gdb/microblaze-tdep.c | 160 +- + gdb/microblaze-tdep.h | 13 +- + 3 files changed, 3975 insertions(+), 8 deletions(-) + create mode 100755 bfd/elf64-microblaze.c + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +new file mode 100755 +index 00000000000..6cd9753a592 +--- /dev/null ++++ b/bfd/elf64-microblaze.c +@@ -0,0 +1,3810 @@ ++/* Xilinx MicroBlaze-specific support for 32-bit ELF ++ ++ Copyright (C) 2009-2021 Free Software Foundation, Inc. ++ ++ This file is part of BFD, the Binary File Descriptor library. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the ++ Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, ++ Boston, MA 02110-1301, USA. */ ++ ++ ++#include "sysdep.h" ++#include "bfd.h" ++#include "bfdlink.h" ++#include "libbfd.h" ++#include "elf-bfd.h" ++#include "elf/microblaze.h" ++#include ++ ++#define USE_RELA /* Only USE_REL is actually significant, but this is ++ here are a reminder... */ ++#define INST_WORD_SIZE 4 ++ ++static int ro_small_data_pointer = 0; ++static int rw_small_data_pointer = 0; ++ ++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max]; ++ ++static reloc_howto_type microblaze_elf_howto_raw[] = ++{ ++ /* This reloc does nothing. */ ++ HOWTO (R_MICROBLAZE_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 0, /* Size. */ ++ 0, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_NONE", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A standard 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 32, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A standard PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 32, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_PCREL", /* Name. */ ++ true, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit PCREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_64_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64_PCREL", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* The low half of a PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_32_PCREL_LO", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 64, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffffffffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit relocation. Table entry not really used. */ ++ HOWTO (R_MICROBLAZE_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* The low half of a 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_LO", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Read-only small data section relocation. */ ++ HOWTO (R_MICROBLAZE_SRO32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRO32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Read-write small data area relocation. */ ++ HOWTO (R_MICROBLAZE_SRW32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRW32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_32_NONE",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 0, /* Size. */ ++ 0, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_64_NONE",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Symbol Op Symbol relocation. */ ++ HOWTO (R_MICROBLAZE_32_SYM_OP_SYM, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 32, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_SYM_OP_SYM", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable hierarchy. */ ++ HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 0, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTINHERIT", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable member usage. */ ++ HOWTO (R_MICROBLAZE_GNU_VTENTRY, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 0, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ _bfd_elf_rel_vtable_reloc_fn, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTENTRY", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTPC_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit TEXTPCREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_TEXTPCREL_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_TEXTPCREL_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOT_64",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit TEXTREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_TEXTREL_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_TEXTREL_64",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 64 bit PLT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_PLT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_PLT_64",/* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_REL, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_REL", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_JUMP_SLOT", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ true, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GLOB_DAT", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ true), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_64", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* A 32 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_32", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* COPY relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_COPY, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size. */ ++ 16, /* Bitsize. */ ++ false, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_COPY", /* Name. */ ++ false, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ false), /* PC relative offset? */ ++ ++ /* Marker relocs for TLS. */ ++ HOWTO (R_MICROBLAZE_TLS, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLS", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSGD, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGD", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSLD, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSLD", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes the load module index of the load module that contains the ++ definition of its TLS sym. */ ++ HOWTO (R_MICROBLAZE_TLSDTPMOD32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPMOD32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. Used for initializing GOT */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL32, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL64, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL64", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSGOTTPREL32, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGOTTPREL32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSTPREL32, ++ 0, /* rightshift */ ++ 4, /* size */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSTPREL32", /* name */ ++ false, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++ ++}; ++ ++#ifndef NUM_ELEM ++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) ++#endif ++ ++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done. */ ++ ++static void ++microblaze_elf_howto_init (void) ++{ ++ unsigned int i; ++ ++ for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;) ++ { ++ unsigned int type; ++ ++ type = microblaze_elf_howto_raw[i].type; ++ ++ BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table)); ++ ++ microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i]; ++ } ++} ++ ++static reloc_howto_type * ++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, ++ bfd_reloc_code_real_type code) ++{ ++ enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE; ++ ++ switch (code) ++ { ++ case BFD_RELOC_NONE: ++ microblaze_reloc = R_MICROBLAZE_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_NONE: ++ microblaze_reloc = R_MICROBLAZE_32_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_NONE: ++ microblaze_reloc = R_MICROBLAZE_64_NONE; ++ break; ++ case BFD_RELOC_32: ++ microblaze_reloc = R_MICROBLAZE_32; ++ break; ++ /* RVA is treated the same as 64 */ ++ case BFD_RELOC_RVA: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; ++ case BFD_RELOC_32_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL; ++ break; ++ case BFD_RELOC_64_PCREL: ++ microblaze_reloc = R_MICROBLAZE_64_PCREL; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL_LO; ++ break; ++ case BFD_RELOC_64: ++ microblaze_reloc = R_MICROBLAZE_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO: ++ microblaze_reloc = R_MICROBLAZE_32_LO; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_ROSDA: ++ microblaze_reloc = R_MICROBLAZE_SRO32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_RWSDA: ++ microblaze_reloc = R_MICROBLAZE_SRW32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: ++ microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM; ++ break; ++ case BFD_RELOC_VTABLE_INHERIT: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT; ++ break; ++ case BFD_RELOC_VTABLE_ENTRY: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; ++ break; ++ case BFD_RELOC_MICROBLAZE_EA64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ microblaze_reloc = R_MICROBLAZE_GOTPC_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOT: ++ microblaze_reloc = R_MICROBLAZE_GOT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TEXTPCREL: ++ microblaze_reloc = R_MICROBLAZE_TEXTPCREL_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TEXTREL: ++ microblaze_reloc = R_MICROBLAZE_TEXTREL_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_PLT: ++ microblaze_reloc = R_MICROBLAZE_PLT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGD: ++ microblaze_reloc = R_MICROBLAZE_TLSGD; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSLD: ++ microblaze_reloc = R_MICROBLAZE_TLSLD; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_COPY: ++ microblaze_reloc = R_MICROBLAZE_COPY; ++ break; ++ default: ++ return (reloc_howto_type *) NULL; ++ } ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ return microblaze_elf_howto_table [(int) microblaze_reloc]; ++}; ++ ++static reloc_howto_type * ++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, ++ const char *r_name) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++) ++ if (microblaze_elf_howto_raw[i].name != NULL ++ && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0) ++ return µblaze_elf_howto_raw[i]; ++ ++ return NULL; ++} ++ ++/* Set the howto pointer for a RCE ELF reloc. */ ++ ++static bool ++microblaze_elf_info_to_howto (bfd * abfd, ++ arelent * cache_ptr, ++ Elf_Internal_Rela * dst) ++{ ++ unsigned int r_type; ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ r_type = ELF64_R_TYPE (dst->r_info); ++ if (r_type >= R_MICROBLAZE_max) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler (_("%pB: unsupported relocation type %#x"), ++ abfd, r_type); ++ bfd_set_error (bfd_error_bad_value); ++ return false; ++ } ++ ++ cache_ptr->howto = microblaze_elf_howto_table [r_type]; ++ return true; ++} ++ ++struct _microblaze_elf_section_data ++{ ++ struct bfd_elf_section_data elf; ++ /* Count of used relaxation table entries. */ ++ size_t relax_count; ++ /* Relaxation table. */ ++ struct relax_table *relax; ++}; ++ ++#define microblaze_elf_section_data(sec) \ ++ ((struct _microblaze_elf_section_data *) elf_section_data (sec)) ++ ++static bool ++microblaze_elf_new_section_hook (bfd *abfd, asection *sec) ++{ ++ if (!sec->used_by_bfd) ++ { ++ struct _microblaze_elf_section_data *sdata; ++ size_t amt = sizeof (*sdata); ++ ++ sdata = bfd_zalloc (abfd, amt); ++ if (sdata == NULL) ++ return false; ++ sec->used_by_bfd = sdata; ++ } ++ ++ return _bfd_elf_new_section_hook (abfd, sec); ++} ++ ++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */ ++ ++static bool ++microblaze_elf_is_local_label_name (bfd *abfd, const char *name) ++{ ++ if (name[0] == 'L' && name[1] == '.') ++ return true; ++ ++ if (name[0] == '$' && name[1] == 'L') ++ return true; ++ ++ /* With gcc, the labels go back to starting with '.', so we accept ++ the generic ELF local label syntax as well. */ ++ return _bfd_elf_is_local_label_name (abfd, name); ++} ++ ++/* The microblaze linker (like many others) needs to keep track of ++ the number of relocs that it decides to copy as dynamic relocs in ++ check_relocs for each symbol. This is so that it can later discard ++ them if they are found to be unnecessary. We store the information ++ in a field extending the regular ELF linker hash table. */ ++ ++struct elf64_mb_dyn_relocs ++{ ++ struct elf64_mb_dyn_relocs *next; ++ ++ /* The input section of the reloc. */ ++ asection *sec; ++ ++ /* Total number of relocs copied for the input section. */ ++ bfd_size_type count; ++ ++ /* Number of pc-relative relocs copied for the input section. */ ++ bfd_size_type pc_count; ++}; ++ ++/* ELF linker hash entry. */ ++ ++struct elf64_mb_link_hash_entry ++{ ++ struct elf_link_hash_entry elf; ++ ++ /* Track dynamic relocs copied for this symbol. */ ++ struct elf64_mb_dyn_relocs *dyn_relocs; ++ ++ /* TLS Reference Types for the symbol; Updated by check_relocs */ ++#define TLS_GD 1 /* GD reloc. */ ++#define TLS_LD 2 /* LD reloc. */ ++#define TLS_TPREL 4 /* TPREL reloc, => IE. */ ++#define TLS_DTPREL 8 /* DTPREL reloc, => LD. */ ++#define TLS_TLS 16 /* Any TLS reloc. */ ++ unsigned char tls_mask; ++ ++}; ++ ++#define IS_TLS_GD(x) (x == (TLS_TLS | TLS_GD)) ++#define IS_TLS_LD(x) (x == (TLS_TLS | TLS_LD)) ++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL)) ++#define IS_TLS_NONE(x) (x == 0) ++ ++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent)) ++ ++/* ELF linker hash table. */ ++ ++struct elf64_mb_link_hash_table ++{ ++ struct elf_link_hash_table elf; ++ ++ /* Short-cuts to get to dynamic linker sections. */ ++ asection *sgot; ++ asection *sgotplt; ++ asection *srelgot; ++ asection *splt; ++ asection *srelplt; ++ asection *sdynbss; ++ asection *srelbss; ++ ++ /* Small local sym to section mapping cache. */ ++ struct sym_cache sym_sec; ++ ++ /* TLS Local Dynamic GOT Entry */ ++ union { ++ bfd_signed_vma refcount; ++ bfd_vma offset; ++ } tlsld_got; ++}; ++ ++/* Nonzero if this section has TLS related relocations. */ ++#define has_tls_reloc sec_flg0 ++ ++/* Get the ELF linker hash table from a link_info structure. */ ++ ++#define elf64_mb_hash_table(p) \ ++ ((is_elf_hash_table ((p)->hash) \ ++ && elf_hash_table_id (elf_hash_table (p)) == MICROBLAZE_ELF_DATA) \ ++ ? (struct elf64_mb_link_hash_table *) (p)->hash : NULL) ++ ++/* Create an entry in a microblaze ELF linker hash table. */ ++ ++static struct bfd_hash_entry * ++link_hash_newfunc (struct bfd_hash_entry *entry, ++ struct bfd_hash_table *table, ++ const char *string) ++{ ++ /* Allocate the structure if it has not already been allocated by a ++ subclass. */ ++ if (entry == NULL) ++ { ++ entry = bfd_hash_allocate (table, ++ sizeof (struct elf64_mb_link_hash_entry)); ++ if (entry == NULL) ++ return entry; ++ } ++ ++ /* Call the allocation method of the superclass. */ ++ entry = _bfd_elf_link_hash_newfunc (entry, table, string); ++ if (entry != NULL) ++ { ++ struct elf64_mb_link_hash_entry *eh; ++ ++ eh = (struct elf64_mb_link_hash_entry *) entry; ++ eh->tls_mask = 0; ++ } ++ ++ return entry; ++} ++ ++/* Create a mb ELF linker hash table. */ ++ ++static struct bfd_link_hash_table * ++microblaze_elf_link_hash_table_create (bfd *abfd) ++{ ++ struct elf64_mb_link_hash_table *ret; ++ size_t amt = sizeof (struct elf64_mb_link_hash_table); ++ ++ ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt); ++ if (ret == NULL) ++ return NULL; ++ ++ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, ++ sizeof (struct elf64_mb_link_hash_entry), ++ MICROBLAZE_ELF_DATA)) ++ { ++ free (ret); ++ return NULL; ++ } ++ ++ return &ret->elf.root; ++} ++ ++/* Set the values of the small data pointers. */ ++ ++static void ++microblaze_elf_final_sdp (struct bfd_link_info *info) ++{ ++ struct bfd_link_hash_entry *h; ++ ++ h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, false, false, true); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ ro_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++ ++ h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, false, false, true); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ rw_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++} ++ ++static bfd_vma ++dtprel_base (struct bfd_link_info *info) ++{ ++ /* If tls_sec is NULL, we should have signalled an error already. */ ++ if (elf_hash_table (info)->tls_sec == NULL) ++ return 0; ++ return elf_hash_table (info)->tls_sec->vma; ++} ++ ++/* The size of the thread control block. */ ++#define TCB_SIZE 8 ++ ++/* Output a simple dynamic relocation into SRELOC. */ ++ ++static void ++microblaze_elf_output_dynamic_relocation (bfd *output_bfd, ++ asection *sreloc, ++ unsigned long reloc_index, ++ unsigned long indx, ++ int r_type, ++ bfd_vma offset, ++ bfd_vma addend) ++{ ++ ++ Elf_Internal_Rela rel; ++ ++ rel.r_info = ELF64_R_INFO (indx, r_type); ++ rel.r_offset = offset; ++ rel.r_addend = addend; ++ ++ bfd_elf64_swap_reloca_out (output_bfd, &rel, ++ (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela))); ++} ++ ++/* This code is taken from elf64-m32r.c ++ There is some attempt to make this function usable for many architectures, ++ both USE_REL and USE_RELA ['twould be nice if such a critter existed], ++ if only to serve as a learning tool. ++ ++ The RELOCATE_SECTION function is called by the new ELF backend linker ++ to handle the relocations for a section. ++ ++ The relocs are always passed as Rela structures; if the section ++ actually uses Rel structures, the r_addend field will always be ++ zero. ++ ++ This function is responsible for adjust the section contents as ++ necessary, and (if using Rela relocs and generating a ++ relocatable output file) adjusting the reloc addend as ++ necessary. ++ ++ This function does not have to worry about setting the reloc ++ address or the reloc symbol index. ++ ++ LOCAL_SYMS is a pointer to the swapped in local symbols. ++ ++ LOCAL_SECTIONS is an array giving the section in the input file ++ corresponding to the st_shndx field of each local symbol. ++ ++ The global hash table entry for the global symbols can be found ++ via elf_sym_hashes (input_bfd). ++ ++ When generating relocatable output, this function must handle ++ STB_LOCAL/STT_SECTION symbols specially. The output symbol is ++ going to be the section symbol corresponding to the output ++ section, which means that the addend must be adjusted ++ accordingly. */ ++ ++static int ++microblaze_elf_relocate_section (bfd *output_bfd, ++ struct bfd_link_info *info, ++ bfd *input_bfd, ++ asection *input_section, ++ bfd_byte *contents, ++ Elf_Internal_Rela *relocs, ++ Elf_Internal_Sym *local_syms, ++ asection **local_sections) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; ++ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); ++ Elf_Internal_Rela *rel, *relend; ++ int endian = (bfd_little_endian (output_bfd)) ? 0 : 2; ++ /* Assume success. */ ++ bool ret = true; ++ asection *sreloc; ++ bfd_vma *local_got_offsets; ++ unsigned int tls_type; ++ ++ if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1]) ++ microblaze_elf_howto_init (); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ local_got_offsets = elf_local_got_offsets (input_bfd); ++ ++ sreloc = elf_section_data (input_section)->sreloc; ++ ++ rel = relocs; ++ relend = relocs + input_section->reloc_count; ++ for (; rel < relend; rel++) ++ { ++ int r_type; ++ reloc_howto_type *howto; ++ unsigned long r_symndx; ++ bfd_vma addend = rel->r_addend; ++ bfd_vma offset = rel->r_offset; ++ struct elf_link_hash_entry *h; ++ Elf_Internal_Sym *sym; ++ asection *sec; ++ const char *sym_name; ++ bfd_reloc_status_type r = bfd_reloc_ok; ++ const char *errmsg = NULL; ++ bool unresolved_reloc = false; ++ ++ h = NULL; ++ r_type = ELF64_R_TYPE (rel->r_info); ++ tls_type = 0; ++ ++ if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max) ++ { ++ /* xgettext:c-format */ ++ _bfd_error_handler (_("%pB: unsupported relocation type %#x"), ++ input_bfd, (int) r_type); ++ bfd_set_error (bfd_error_bad_value); ++ ret = false; ++ continue; ++ } ++ ++ howto = microblaze_elf_howto_table[r_type]; ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ ++ if (bfd_link_relocatable (info)) ++ { ++ /* This is a relocatable link. We don't have to change ++ anything, unless the reloc is against a section symbol, ++ in which case we have to adjust according to where the ++ section symbol winds up in the output section. */ ++ sec = NULL; ++ if (r_symndx >= symtab_hdr->sh_info) ++ /* External symbol. */ ++ continue; ++ ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sym_name = ""; ++ /* STT_SECTION: symbol is associated with a section. */ ++ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) ++ /* Symbol isn't associated with a section. Nothing to do. */ ++ continue; ++ ++ sec = local_sections[r_symndx]; ++ addend += sec->output_offset + sym->st_value; ++#ifndef USE_REL ++ /* This can't be done for USE_REL because it doesn't mean anything ++ and elf_link_input_bfd asserts this stays zero. */ ++ /* rel->r_addend = addend; */ ++#endif ++ ++#ifndef USE_REL ++ /* Addends are stored with relocs. We're done. */ ++ continue; ++#else /* USE_REL */ ++ /* If partial_inplace, we need to store any additional addend ++ back in the section. */ ++ if (!howto->partial_inplace) ++ continue; ++ /* ??? Here is a nice place to call a special_function like handler. */ ++ r = _bfd_relocate_contents (howto, input_bfd, addend, ++ contents + offset); ++#endif /* USE_REL */ ++ } ++ else ++ { ++ bfd_vma relocation; ++ bool resolved_to_zero; ++ ++ /* This is a final link. */ ++ sym = NULL; ++ sec = NULL; ++ unresolved_reloc = false; ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ { ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sec = local_sections[r_symndx]; ++ if (sec == 0) ++ continue; ++ sym_name = ""; ++ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); ++ /* r_addend may have changed if the reference section was ++ a merge section. */ ++ addend = rel->r_addend; ++ } ++ else ++ { ++ /* External symbol. */ ++ bool warned ATTRIBUTE_UNUSED; ++ bool ignored ATTRIBUTE_UNUSED; ++ ++ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, ++ r_symndx, symtab_hdr, sym_hashes, ++ h, sec, relocation, ++ unresolved_reloc, warned, ignored); ++ sym_name = h->root.root.string; ++ } ++ ++ /* Sanity check the address. */ ++ if (offset > bfd_get_section_limit (input_bfd, input_section)) ++ { ++ r = bfd_reloc_outofrange; ++ goto check_reloc; ++ } ++ ++ resolved_to_zero = (h != NULL ++ && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)); ++ ++ switch ((int) r_type) ++ { ++ case (int) R_MICROBLAZE_SRO32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_section_name (sec); ++ ++ if (strcmp (name, ".sdata2") == 0 ++ || strcmp (name, ".sbss2") == 0) ++ { ++ if (ro_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (ro_small_data_pointer == 0) ++ { ++ ret = false; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= ro_small_data_pointer; ++ /* Now it contains the offset from _SDA2_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ _bfd_error_handler ++ /* xgettext:c-format */ ++ (_("%pB: the target (%s) of an %s relocation" ++ " is in the wrong section (%pA)"), ++ input_bfd, ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ sec); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = false; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_SRW32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_section_name (sec); ++ ++ if (strcmp (name, ".sdata") == 0 ++ || strcmp (name, ".sbss") == 0) ++ { ++ if (rw_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (rw_small_data_pointer == 0) ++ { ++ ret = false; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= rw_small_data_pointer; ++ /* Now it contains the offset from _SDA_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ _bfd_error_handler ++ /* xgettext:c-format */ ++ (_("%pB: the target (%s) of an %s relocation" ++ " is in the wrong section (%pA)"), ++ input_bfd, ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ sec); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = false; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_32_SYM_OP_SYM: ++ break; /* Do nothing. */ ++ ++ case (int) R_MICROBLAZE_GOTPC_64: ++ relocation = (htab->elf.sgotplt->output_section->vma ++ + htab->elf.sgotplt->output_offset); ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ relocation += addend; ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ ++ case (int) R_MICROBLAZE_TEXTPCREL_64: ++ relocation = input_section->output_section->vma; ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ relocation += addend; ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ ++ case (int) R_MICROBLAZE_PLT_64: ++ { ++ bfd_vma immediate; ++ if (htab->elf.splt != NULL && h != NULL ++ && h->plt.offset != (bfd_vma) -1) ++ { ++ relocation = (htab->elf.splt->output_section->vma ++ + htab->elf.splt->output_offset ++ + h->plt.offset); ++ unresolved_reloc = false; ++ immediate = relocation - (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ else ++ { ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ immediate = relocation; ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSGD: ++ tls_type = (TLS_TLS | TLS_GD); ++ goto dogot; ++ case (int) R_MICROBLAZE_TLSLD: ++ tls_type = (TLS_TLS | TLS_LD); ++ /* Fall through. */ ++ dogot: ++ case (int) R_MICROBLAZE_GOT_64: ++ { ++ bfd_vma *offp; ++ bfd_vma off, off2; ++ unsigned long indx; ++ bfd_vma static_value; ++ ++ bool need_relocs = false; ++ if (htab->elf.sgot == NULL) ++ abort (); ++ ++ indx = 0; ++ offp = NULL; ++ ++ /* 1. Identify GOT Offset; ++ 2. Compute Static Values ++ 3. Process Module Id, Process Offset ++ 4. Fixup Relocation with GOT offset value. */ ++ ++ /* 1. Determine GOT Offset to use : TLS_LD, global, local */ ++ if (IS_TLS_LD (tls_type)) ++ offp = &htab->tlsld_got.offset; ++ else if (h != NULL) ++ { ++ if (htab->elf.sgotplt != NULL ++ && h->got.offset != (bfd_vma) -1) ++ offp = &h->got.offset; ++ else ++ abort (); ++ } ++ else ++ { ++ if (local_got_offsets == NULL) ++ abort (); ++ offp = &local_got_offsets[r_symndx]; ++ } ++ ++ if (!offp) ++ abort (); ++ ++ off = (*offp) & ~1; ++ off2 = off; ++ ++ if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type)) ++ off2 = off + 4; ++ ++ /* Symbol index to use for relocs */ ++ if (h != NULL) ++ { ++ bool dyn = ++ elf_hash_table (info)->dynamic_sections_created; ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, ++ bfd_link_pic (info), ++ h) ++ && (!bfd_link_pic (info) ++ || !SYMBOL_REFERENCES_LOCAL (info, h))) ++ indx = h->dynindx; ++ } ++ ++ /* Need to generate relocs ? */ ++ if ((bfd_link_pic (info) || indx != 0) ++ && (h == NULL ++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ || h->root.type != bfd_link_hash_undefweak)) ++ need_relocs = true; ++ ++ /* 2. Compute/Emit Static value of r-expression */ ++ static_value = relocation + addend; ++ ++ /* 3. Process module-id and offset */ ++ if (! ((*offp) & 1) ) ++ { ++ bfd_vma got_offset; ++ ++ got_offset = (htab->elf.sgot->output_section->vma ++ + htab->elf.sgot->output_offset ++ + off); ++ ++ /* Process module-id */ ++ if (IS_TLS_LD(tls_type)) ++ { ++ if (! bfd_link_pic (info)) ++ bfd_put_32 (output_bfd, 1, ++ htab->elf.sgot->contents + off); ++ else ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, 0); ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ if (! need_relocs) ++ bfd_put_32 (output_bfd, 1, ++ htab->elf.sgot->contents + off); ++ else ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, indx ? 0 : static_value); ++ } ++ ++ /* Process Offset */ ++ if (htab->elf.srelgot == NULL) ++ abort (); ++ ++ got_offset = (htab->elf.sgot->output_section->vma ++ + htab->elf.sgot->output_offset ++ + off2); ++ if (IS_TLS_LD(tls_type)) ++ { ++ /* For LD, offset should be 0 */ ++ *offp |= 1; ++ bfd_put_32 (output_bfd, 0, ++ htab->elf.sgot->contents + off2); ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ *offp |= 1; ++ static_value -= dtprel_base(info); ++ if (need_relocs) ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32, ++ got_offset, indx ? 0 : static_value); ++ else ++ bfd_put_32 (output_bfd, static_value, ++ htab->elf.sgot->contents + off2); ++ } ++ else ++ { ++ bfd_put_32 (output_bfd, static_value, ++ htab->elf.sgot->contents + off2); ++ ++ /* Relocs for dyn symbols generated by ++ finish_dynamic_symbols */ ++ if (bfd_link_pic (info) && h == NULL) ++ { ++ *offp |= 1; ++ microblaze_elf_output_dynamic_relocation ++ (output_bfd, ++ htab->elf.srelgot, ++ htab->elf.srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_REL, ++ got_offset, static_value); ++ } ++ } ++ } ++ ++ /* 4. Fixup Relocation with GOT offset value ++ Compute relative address of GOT entry for applying ++ the current relocation */ ++ relocation = htab->elf.sgot->output_section->vma ++ + htab->elf.sgot->output_offset ++ + off ++ - htab->elf.sgotplt->output_section->vma ++ - htab->elf.sgotplt->output_offset; ++ ++ /* Apply Current Relocation */ ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ ++ unresolved_reloc = false; ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_64: ++ { ++ bfd_vma immediate; ++ unsigned short lo, high; ++ relocation += addend; ++ relocation -= (htab->elf.sgotplt->output_section->vma ++ + htab->elf.sgotplt->output_offset); ++ /* Write this value into correct location. */ ++ immediate = relocation; ++ lo = immediate & 0x0000ffff; ++ high = (immediate >> 16) & 0x0000ffff; ++ bfd_put_16 (input_bfd, high, contents + offset + endian); ++ bfd_put_16 (input_bfd, lo, ++ contents + offset + INST_WORD_SIZE + endian); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_32: ++ { ++ relocation += addend; ++ relocation -= (htab->elf.sgotplt->output_section->vma ++ + htab->elf.sgotplt->output_offset); ++ /* Write this value into correct location. */ ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSDTPREL64: ++ relocation += addend; ++ relocation -= dtprel_base(info); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ case (int) R_MICROBLAZE_TEXTREL_64: ++ case (int) R_MICROBLAZE_TEXTREL_32_LO: ++ case (int) R_MICROBLAZE_64_PCREL : ++ case (int) R_MICROBLAZE_64: ++ case (int) R_MICROBLAZE_32: ++ case (int) R_MICROBLAZE_IMML_64: ++ { ++ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols ++ from removed linkonce sections, or sections discarded by ++ a linker script. */ ++ if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ else if (r_type == R_MICROBLAZE_TEXTREL_64 ++ || r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ relocation -= input_section->output_section->vma; ++ ++ if (r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian); ++ ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if ((insn & 0xff000000) == 0xb2000000) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, ++ contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ if ((bfd_link_pic (info) ++ && (h == NULL ++ || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ && !resolved_to_zero) ++ || h->root.type != bfd_link_hash_undefweak) ++ && (!howto->pc_relative ++ || (h != NULL ++ && h->dynindx != -1 ++ && (!info->symbolic ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && h != NULL ++ && h->dynindx != -1 ++ && !h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined))) ++ { ++ Elf_Internal_Rela outrel; ++ bfd_byte *loc; ++ bool skip; ++ ++ /* When generating a shared object, these relocations ++ are copied into the output file to be resolved at run ++ time. */ ++ ++ BFD_ASSERT (sreloc != NULL); ++ ++ skip = false; ++ ++ outrel.r_offset = ++ _bfd_elf_section_offset (output_bfd, info, input_section, ++ rel->r_offset); ++ if (outrel.r_offset == (bfd_vma) -1) ++ skip = true; ++ else if (outrel.r_offset == (bfd_vma) -2) ++ skip = true; ++ outrel.r_offset += (input_section->output_section->vma ++ + input_section->output_offset); ++ ++ if (skip) ++ memset (&outrel, 0, sizeof outrel); ++ /* h->dynindx may be -1 if the symbol was marked to ++ become local. */ ++ else if (h != NULL ++ && ((! info->symbolic && h->dynindx != -1) ++ || !h->def_regular)) ++ { ++ BFD_ASSERT (h->dynindx != -1); ++ outrel.r_info = ELF64_R_INFO (h->dynindx, r_type); ++ outrel.r_addend = addend; ++ } ++ else ++ { ++ if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64) ++ { ++ outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); ++ outrel.r_addend = relocation + addend; ++ } ++ else ++ { ++ BFD_FAIL (); ++ _bfd_error_handler ++ (_("%pB: probably compiled without -fPIC?"), ++ input_bfd); ++ bfd_set_error (bfd_error_bad_value); ++ return false; ++ } ++ } ++ ++ loc = sreloc->contents; ++ loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc); ++ break; ++ } ++ else ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset + endian); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ { ++ if (!input_section->output_section->vma && ++ !input_section->output_offset && !offset) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset); ++ else ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset + offset + INST_WORD_SIZE); ++ } ++ else if (r_type == R_MICROBLAZE_TEXTREL_64 ++ || r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ relocation -= input_section->output_section->vma; ++ ++ if (r_type == R_MICROBLAZE_TEXTREL_32_LO) ++ { ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian); ++ } ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if ((insn & 0xff000000) == 0xb2000000) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, ++ contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ } ++ ++ default : ++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, ++ contents, offset, ++ relocation, addend); ++ break; ++ } ++ } ++ ++ check_reloc: ++ ++ if (r != bfd_reloc_ok) ++ { ++ /* FIXME: This should be generic enough to go in a utility. */ ++ const char *name; ++ ++ if (h != NULL) ++ name = h->root.root.string; ++ else ++ { ++ name = (bfd_elf_string_from_elf_section ++ (input_bfd, symtab_hdr->sh_link, sym->st_name)); ++ if (name == NULL || *name == '\0') ++ name = bfd_section_name (sec); ++ } ++ ++ if (errmsg != NULL) ++ goto common_error; ++ ++ switch (r) ++ { ++ case bfd_reloc_overflow: ++ (*info->callbacks->reloc_overflow) ++ (info, (h ? &h->root : NULL), name, howto->name, ++ (bfd_vma) 0, input_bfd, input_section, offset); ++ break; ++ ++ case bfd_reloc_undefined: ++ (*info->callbacks->undefined_symbol) ++ (info, name, input_bfd, input_section, offset, true); ++ break; ++ ++ case bfd_reloc_outofrange: ++ errmsg = _("internal error: out of range error"); ++ goto common_error; ++ ++ case bfd_reloc_notsupported: ++ errmsg = _("internal error: unsupported relocation error"); ++ goto common_error; ++ ++ case bfd_reloc_dangerous: ++ errmsg = _("internal error: dangerous error"); ++ goto common_error; ++ ++ default: ++ errmsg = _("internal error: unknown error"); ++ /* Fall through. */ ++ common_error: ++ (*info->callbacks->warning) (info, errmsg, name, input_bfd, ++ input_section, offset); ++ break; ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++/* Merge backend specific data from an object file to the output ++ object file when linking. ++ ++ Note: We only use this hook to catch endian mismatches. */ ++static bool ++microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) ++{ ++ /* Check if we have the same endianess. */ ++ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) ++ return false; ++ ++ return true; ++} ++ ++ ++/* Calculate fixup value for reference. */ ++ ++static size_t ++calc_fixup (bfd_vma start, bfd_vma size, asection *sec) ++{ ++ bfd_vma end = start + size; ++ size_t i, fixup = 0; ++ struct _microblaze_elf_section_data *sdata; ++ ++ if (sec == NULL || (sdata = microblaze_elf_section_data (sec)) == NULL) ++ return 0; ++ ++ /* Look for addr in relax table, total fixup value. */ ++ for (i = 0; i < sdata->relax_count; i++) ++ { ++ if (end <= sdata->relax[i].addr) ++ break; ++ if (end != start && start > sdata->relax[i].addr) ++ continue; ++ fixup += sdata->relax[i].size; ++ } ++ return fixup; ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ a 32-bit instruction. */ ++static void ++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr = bfd_get_32 (abfd, bfd_addr); ++ ++ if ((instr & 0xff000000) == 0xb2000000) ++ { ++ instr &= ~0x00ffffff; ++ instr |= (val & 0xffffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } ++ else ++ { ++ instr &= ~0x0000ffff; ++ instr |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ two consecutive 32-bit instructions. */ ++static void ++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr_hi; ++ unsigned long instr_lo; ++ ++ instr_hi = bfd_get_32 (abfd, bfd_addr); ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ { ++ instr_hi &= ~0x00ffffff; ++ instr_hi |= (val >> 16) & 0xffffff; ++ bfd_put_32 (abfd, instr_hi,bfd_addr); ++ } ++ else ++ { ++ instr_hi &= ~0x0000ffff; ++ instr_hi |= ((val >> 16) & 0x0000ffff); ++ bfd_put_32 (abfd, instr_hi, bfd_addr); ++ } ++ instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE); ++ instr_lo &= ~0x0000ffff; ++ instr_lo |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE); ++} ++ ++static bool ++microblaze_elf_relax_section (bfd *abfd, ++ asection *sec, ++ struct bfd_link_info *link_info, ++ bool *again) ++{ ++ Elf_Internal_Shdr *symtab_hdr; ++ Elf_Internal_Rela *internal_relocs; ++ Elf_Internal_Rela *irel, *irelend; ++ bfd_byte *contents = NULL; ++ int rel_count; ++ unsigned int shndx; ++ size_t i, sym_index; ++ asection *o; ++ struct elf_link_hash_entry *sym_hash; ++ Elf_Internal_Sym *isymbuf, *isymend; ++ Elf_Internal_Sym *isym; ++ size_t symcount; ++ size_t offset; ++ bfd_vma src, dest; ++ struct _microblaze_elf_section_data *sdata; ++ ++ /* We only do this once per section. We may be able to delete some code ++ by running multiple passes, but it is not worth it. */ ++ *again = false; ++ ++ /* Only do this for a text section. */ ++ if (bfd_link_relocatable (link_info) ++ || (sec->flags & SEC_RELOC) == 0 ++ || (sec->flags & SEC_CODE) == 0 ++ || sec->reloc_count == 0 ++ || (sdata = microblaze_elf_section_data (sec)) == NULL) ++ return true; ++ ++ BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0)); ++ ++ /* If this is the first time we have been called for this section, ++ initialize the cooked size. */ ++ if (sec->size == 0) ++ sec->size = sec->rawsize; ++ ++ /* Get symbols for this section. */ ++ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; ++ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; ++ symcount = symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (isymbuf == NULL) ++ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount, ++ 0, NULL, NULL, NULL); ++ BFD_ASSERT (isymbuf != NULL); ++ ++ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); ++ if (internal_relocs == NULL) ++ goto error_return; ++ ++ sdata->relax_count = 0; ++ sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) ++ * sizeof (*sdata->relax)); ++ if (sdata->relax == NULL) ++ goto error_return; ++ ++ irelend = internal_relocs + sec->reloc_count; ++ rel_count = 0; ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma symval; ++ if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL) ++ && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ) ++&& (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_TEXTREL_64)) ++ continue; /* Can't delete this reloc. */ ++ ++ /* Get the section contents. */ ++ if (contents == NULL) ++ { ++ if (elf_section_data (sec)->this_hdr.contents != NULL) ++ contents = elf_section_data (sec)->this_hdr.contents; ++ else ++ { ++ contents = (bfd_byte *) bfd_malloc (sec->size); ++ if (contents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, sec, contents, ++ (file_ptr) 0, sec->size)) ++ goto error_return; ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } ++ } ++ ++ /* Get the value of the symbol referred to by the reloc. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ /* A local symbol. */ ++ asection *sym_sec; ++ ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ if (isym->st_shndx == SHN_UNDEF) ++ sym_sec = bfd_und_section_ptr; ++ else if (isym->st_shndx == SHN_ABS) ++ sym_sec = bfd_abs_section_ptr; ++ else if (isym->st_shndx == SHN_COMMON) ++ sym_sec = bfd_com_section_ptr; ++ else ++ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ ++ symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel); ++ } ++ else ++ { ++ unsigned long indx; ++ struct elf_link_hash_entry *h; ++ ++ indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info; ++ h = elf_sym_hashes (abfd)[indx]; ++ BFD_ASSERT (h != NULL); ++ ++ if (h->root.type != bfd_link_hash_defined ++ && h->root.type != bfd_link_hash_defweak) ++ /* This appears to be a reference to an undefined ++ symbol. Just ignore it--it will be caught by the ++ regular reloc processing. */ ++ continue; ++ ++ symval = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ } ++ ++ /* If this is a PC-relative reloc, subtract the instr offset from ++ the symbol value. */ ++ if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ symval = symval + irel->r_addend ++ - (irel->r_offset ++ + sec->output_section->vma ++ + sec->output_offset); ++ } ++ else if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_TEXTREL_64) ++ { ++ symval = symval + irel->r_addend - (sec->output_section->vma); ++ } ++ else ++ symval += irel->r_addend; ++ ++ if ((symval & 0xffff8000) == 0 ++ || (symval & 0xffff8000) == 0xffff8000) ++ { ++ /* We can delete this instruction. */ ++ sdata->relax[sdata->relax_count].addr = irel->r_offset; ++ sdata->relax[sdata->relax_count].size = INST_WORD_SIZE; ++ sdata->relax_count++; ++ ++ /* Rewrite relocation type. */ ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ case R_MICROBLAZE_64_PCREL: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_PCREL_LO); ++ break; ++ case R_MICROBLAZE_64: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_LO); ++ break; ++ case R_MICROBLAZE_TEXTREL_64: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_TEXTREL_32_LO); ++ break; ++ default: ++ /* Cannot happen. */ ++ BFD_ASSERT (false); ++ } ++ } ++ } /* Loop through all relocations. */ ++ ++ /* Loop through the relocs again, and see if anything needs to change. */ ++ if (sdata->relax_count > 0) ++ { ++ shndx = _bfd_elf_section_from_bfd_section (abfd, sec); ++ rel_count = 0; ++ sdata->relax[sdata->relax_count].addr = sec->size; ++ ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma nraddr; ++ ++ /* Get the new reloc address. */ ++ nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec); ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ default: ++ break; ++ case R_MICROBLAZE_64_PCREL: ++ break; ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_32_LO: ++ /* If this reloc is against a symbol defined in this ++ section, we must check the addend to see it will put the value in ++ range to be adjusted, and hence must be changed. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ /* Only handle relocs against .text. */ ++ if (isym->st_shndx == shndx ++ && ELF64_ST_TYPE (isym->st_info) == STT_SECTION) ++ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); ++ } ++ break; ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_64 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ case R_MICROBLAZE_NONE: ++ case R_MICROBLAZE_32_NONE: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ size_t sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ case R_MICROBLAZE_64_NONE: ++ { ++ /* This was a PC-relative 64-bit instruction that was ++ completely resolved. */ ++ size_t sfix, efix; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE; ++ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ irel->r_addend -= (efix - sfix); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ } ++ irel->r_offset = nraddr; ++ } /* Change all relocs in this section. */ ++ ++ /* Look through all other sections. */ ++ for (o = abfd->sections; o != NULL; o = o->next) ++ { ++ Elf_Internal_Rela *irelocs; ++ Elf_Internal_Rela *irelscan, *irelscanend; ++ bfd_byte *ocontents; ++ ++ if (o == sec ++ || (o->flags & SEC_RELOC) == 0 ++ || o->reloc_count == 0) ++ continue; ++ ++ /* We always cache the relocs. Perhaps, if info->keep_memory is ++ false, we should free them, if we are permitted to. */ ++ ++ irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, true); ++ if (irelocs == NULL) ++ goto error_return; ++ ++ ocontents = NULL; ++ irelscanend = irelocs + o->reloc_count; ++ for (irelscan = irelocs; irelscan < irelscanend; irelscan++) ++ { ++ if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) ++ { ++ unsigned int val; ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* hax: We only do the following fixup for debug location lists. */ ++ if (strcmp(".debug_loc", o->name)) ++ continue; ++ ++ /* This was a PC-relative instruction that was completely resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ if (val != irelscan->r_addend) { ++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32 ++ || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend ++ + isym->st_value, ++ 0, ++ sec); ++ } ++ } ++ else if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO) ++ || (ELF32_R_TYPE (irelscan->r_info) ++ == (int) R_MICROBLAZE_32_LO) ++ || (ELF32_R_TYPE (irelscan->r_info) ++ == (int) R_MICROBLAZE_TEXTREL_32_LO)) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ immediate = instr & 0x0000ffff; ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ } ++ ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64 ++ || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_TEXTREL_64)) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ offset = calc_fixup (irelscan->r_addend, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ ++ } ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ if (ELF64_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is false, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_64 (abfd, ocontents ++ + irelscan->r_offset, immediate); ++ } ++ } ++ } ++ } ++ ++ /* Adjust the local symbols defined in this section. */ ++ isymend = isymbuf + symtab_hdr->sh_info; ++ for (isym = isymbuf; isym < isymend; isym++) ++ { ++ if (isym->st_shndx == shndx) ++ { ++ isym->st_value -= calc_fixup (isym->st_value, 0, sec); ++ if (isym->st_size) ++ isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec); ++ } ++ } ++ ++ /* Now adjust the global symbols defined in this section. */ ++ isym = isymbuf + symtab_hdr->sh_info; ++ symcount = (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info; ++ for (sym_index = 0; sym_index < symcount; sym_index++) ++ { ++ sym_hash = elf_sym_hashes (abfd)[sym_index]; ++ if ((sym_hash->root.type == bfd_link_hash_defined ++ || sym_hash->root.type == bfd_link_hash_defweak) ++ && sym_hash->root.u.def.section == sec) ++ { ++ sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value, ++ 0, sec); ++ if (sym_hash->size) ++ sym_hash->size -= calc_fixup (sym_hash->root.u.def.value, ++ sym_hash->size, sec); ++ } ++ } ++ ++ /* Physically move the code and change the cooked size. */ ++ dest = sdata->relax[0].addr; ++ for (i = 0; i < sdata->relax_count; i++) ++ { ++ size_t len; ++ src = sdata->relax[i].addr + sdata->relax[i].size; ++ len = (sdata->relax[i+1].addr - sdata->relax[i].addr ++ - sdata->relax[i].size); ++ ++ memmove (contents + dest, contents + src, len); ++ sec->size -= sdata->relax[i].size; ++ dest += len; ++ } ++ ++ elf_section_data (sec)->relocs = internal_relocs; ++ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ ++ symtab_hdr->contents = (bfd_byte *) isymbuf; ++ } ++ ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); ++ ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ { ++ if (! link_info->keep_memory) ++ free (contents); ++ else ++ { ++ /* Cache the section contents for elf_link_input_bfd. */ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } ++ } ++ ++ if (sdata->relax_count == 0) ++ { ++ *again = false; ++ free (sdata->relax); ++ sdata->relax = NULL; ++ } ++ else ++ *again = true; ++ return true; ++ ++ error_return: ++ if (isymbuf != NULL ++ && symtab_hdr->contents != (unsigned char *) isymbuf) ++ free (isymbuf); ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ free (contents); ++ free (sdata->relax); ++ sdata->relax = NULL; ++ sdata->relax_count = 0; ++ return false; ++} ++ ++/* Return the section that should be marked against GC for a given ++ relocation. */ ++ ++static asection * ++microblaze_elf_gc_mark_hook (asection *sec, ++ struct bfd_link_info * info, ++ Elf_Internal_Rela * rel, ++ struct elf_link_hash_entry * h, ++ Elf_Internal_Sym * sym) ++{ ++ if (h != NULL) ++ switch (ELF64_R_TYPE (rel->r_info)) ++ { ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ case R_MICROBLAZE_GNU_VTENTRY: ++ return NULL; ++ } ++ ++ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); ++} ++ ++/* Update the got entry reference counts for the section being removed. */ ++ ++static bool ++microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info * info ATTRIBUTE_UNUSED, ++ asection * sec ATTRIBUTE_UNUSED, ++ const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) ++{ ++ return true; ++} ++ ++/* PIC support. */ ++ ++#define PLT_ENTRY_SIZE 16 ++ ++#define PLT_ENTRY_WORD_0 0xb0000000 /* "imm 0". */ ++#define PLT_ENTRY_WORD_1 0xe9940000 /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT. */ ++#define PLT_ENTRY_WORD_1_NOPIC 0xe9800000 /* "lwi r12,r0,0" - non-PIC object. */ ++#define PLT_ENTRY_WORD_2 0x98186000 /* "brad r12". */ ++#define PLT_ENTRY_WORD_3 0x80000000 /* "nop". */ ++ ++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up ++ shortcuts to them in our hash table. */ ++ ++static bool ++update_local_sym_info (bfd *abfd, ++ Elf_Internal_Shdr *symtab_hdr, ++ unsigned long r_symndx, ++ unsigned int tls_type) ++{ ++ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd); ++ unsigned char *local_got_tls_masks; ++ ++ if (local_got_refcounts == NULL) ++ { ++ bfd_size_type size = symtab_hdr->sh_info; ++ ++ size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks)); ++ local_got_refcounts = bfd_zalloc (abfd, size); ++ if (local_got_refcounts == NULL) ++ return false; ++ elf_local_got_refcounts (abfd) = local_got_refcounts; ++ } ++ ++ local_got_tls_masks = ++ (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info); ++ local_got_tls_masks[r_symndx] |= tls_type; ++ local_got_refcounts[r_symndx] += 1; ++ ++ return true; ++} ++/* Look through the relocs for a section during the first phase. */ ++ ++static bool ++microblaze_elf_check_relocs (bfd * abfd, ++ struct bfd_link_info * info, ++ asection * sec, ++ const Elf_Internal_Rela * relocs) ++{ ++ Elf_Internal_Shdr * symtab_hdr; ++ struct elf_link_hash_entry ** sym_hashes; ++ struct elf_link_hash_entry ** sym_hashes_end; ++ const Elf_Internal_Rela * rel; ++ const Elf_Internal_Rela * rel_end; ++ struct elf64_mb_link_hash_table *htab; ++ asection *sreloc = NULL; ++ ++ if (bfd_link_relocatable (info)) ++ return true; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ symtab_hdr = & elf_tdata (abfd)->symtab_hdr; ++ sym_hashes = elf_sym_hashes (abfd); ++ sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (!elf_bad_symtab (abfd)) ++ sym_hashes_end -= symtab_hdr->sh_info; ++ ++ rel_end = relocs + sec->reloc_count; ++ ++ for (rel = relocs; rel < rel_end; rel++) ++ { ++ unsigned int r_type; ++ struct elf_link_hash_entry * h; ++ unsigned long r_symndx; ++ unsigned char tls_type = 0; ++ ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ r_type = ELF64_R_TYPE (rel->r_info); ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ h = NULL; ++ else ++ { ++ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; ++ while (h->root.type == bfd_link_hash_indirect ++ || h->root.type == bfd_link_hash_warning) ++ h = (struct elf_link_hash_entry *) h->root.u.i.link; ++ /* PR15323, ref flags aren't set for references in the same ++ object. */ ++ h->root.non_ir_ref_regular = 1; ++ } ++ ++ switch (r_type) ++ { ++ /* This relocation describes the C++ object vtable hierarchy. ++ Reconstruct it for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) ++ return false; ++ break; ++ ++ /* This relocation describes which C++ vtable entries are actually ++ used. Record for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTENTRY: ++ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) ++ return false; ++ break; ++ ++ /* This relocation requires .plt entry. */ ++ case R_MICROBLAZE_PLT_64: ++ if (h != NULL) ++ { ++ h->needs_plt = 1; ++ h->plt.refcount += 1; ++ } ++ break; ++ ++ /* This relocation requires .got entry. */ ++ case R_MICROBLAZE_TLSGD: ++ tls_type |= (TLS_TLS | TLS_GD); ++ goto dogottls; ++ case R_MICROBLAZE_TLSLD: ++ tls_type |= (TLS_TLS | TLS_LD); ++ /* Fall through. */ ++ dogottls: ++ sec->has_tls_reloc = 1; ++ /* Fall through. */ ++ case R_MICROBLAZE_GOT_64: ++ if (htab->elf.sgot == NULL) ++ { ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ if (!_bfd_elf_create_got_section (htab->elf.dynobj, info)) ++ return false; ++ } ++ if (h != NULL) ++ { ++ h->got.refcount += 1; ++ elf64_mb_hash_entry (h)->tls_mask |= tls_type; ++ } ++ else ++ { ++ if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) ) ++ return false; ++ } ++ break; ++ ++ case R_MICROBLAZE_GOTOFF_64: ++ case R_MICROBLAZE_GOTOFF_32: ++ if (htab->elf.sgot == NULL) ++ { ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ if (!_bfd_elf_create_got_section (htab->elf.dynobj, info)) ++ return false; ++ } ++ break; ++ ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_64_PCREL: ++ case R_MICROBLAZE_32: ++ case R_MICROBLAZE_IMML_64: ++ { ++ if (h != NULL && !bfd_link_pic (info)) ++ { ++ /* we may need a copy reloc. */ ++ h->non_got_ref = 1; ++ ++ /* we may also need a .plt entry. */ ++ h->plt.refcount += 1; ++ if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL) ++ h->pointer_equality_needed = 1; ++ } ++ ++ ++ /* If we are creating a shared library, and this is a reloc ++ against a global symbol, or a non PC relative reloc ++ against a local symbol, then we need to copy the reloc ++ into the shared library. However, if we are linking with ++ -Bsymbolic, we do not need to copy a reloc against a ++ global symbol which is defined in an object we are ++ including in the link (i.e., DEF_REGULAR is set). At ++ this point we have not seen all the input files, so it is ++ possible that DEF_REGULAR is not set now but will be set ++ later (it is never cleared). In case of a weak definition, ++ DEF_REGULAR may be cleared later by a strong definition in ++ a shared library. We account for that possibility below by ++ storing information in the relocs_copied field of the hash ++ table entry. A similar situation occurs when creating ++ shared libraries and symbol visibility changes render the ++ symbol local. ++ ++ If on the other hand, we are creating an executable, we ++ may need to keep relocations for symbols satisfied by a ++ dynamic library if we manage to avoid copy relocs for the ++ symbol. */ ++ ++ if ((bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && (r_type != R_MICROBLAZE_64_PCREL ++ || (h != NULL ++ && (! info->symbolic ++ || h->root.type == bfd_link_hash_defweak ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && h != NULL ++ && (h->root.type == bfd_link_hash_defweak ++ || !h->def_regular))) ++ { ++ struct elf64_mb_dyn_relocs *p; ++ struct elf64_mb_dyn_relocs **head; ++ ++ /* When creating a shared object, we must copy these ++ relocs into the output file. We create a reloc ++ section in dynobj and make room for the reloc. */ ++ ++ if (sreloc == NULL) ++ { ++ bfd *dynobj; ++ ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ dynobj = htab->elf.dynobj; ++ ++ sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, ++ 2, abfd, 1); ++ if (sreloc == NULL) ++ return false; ++ } ++ ++ /* If this is a global symbol, we count the number of ++ relocations we need for this symbol. */ ++ if (h != NULL) ++ head = &h->dyn_relocs; ++ else ++ { ++ /* Track dynamic relocs needed for local syms too. ++ We really need local syms available to do this ++ easily. Oh well. */ ++ ++ asection *s; ++ Elf_Internal_Sym *isym; ++ void *vpp; ++ ++ isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, ++ abfd, r_symndx); ++ if (isym == NULL) ++ return false; ++ ++ s = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ if (s == NULL) ++ return false; ++ ++ vpp = &elf_section_data (s)->local_dynrel; ++ head = (struct elf64_mb_dyn_relocs **) vpp; ++ } ++ ++ p = *head; ++ if (p == NULL || p->sec != sec) ++ { ++ size_t amt = sizeof *p; ++ p = ((struct elf64_mb_dyn_relocs *) ++ bfd_alloc (htab->elf.dynobj, amt)); ++ if (p == NULL) ++ return false; ++ p->next = *head; ++ *head = p; ++ p->sec = sec; ++ p->count = 0; ++ p->pc_count = 0; ++ } ++ ++ p->count += 1; ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ p->pc_count += 1; ++ } ++ } ++ break; ++ } ++ } ++ ++ return true; ++} ++ ++static bool ++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ if (!htab->sgot && !_bfd_elf_create_got_section (dynobj, info)) ++ return false; ++ ++ if (!_bfd_elf_create_dynamic_sections (dynobj, info)) ++ return false; ++ ++ htab->splt = bfd_get_linker_section (dynobj, ".plt"); ++ htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt"); ++ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss"); ++ if (!bfd_link_pic (info)) ++ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss"); ++ ++ if (!htab->splt || !htab->srelplt || !htab->sdynbss ++ || (!bfd_link_pic (info) && !htab->srelbss)) ++ abort (); ++ ++ return true; ++} ++ ++/* Copy the extra info we tack onto an elf_link_hash_entry. */ ++ ++static void ++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *dir, ++ struct elf_link_hash_entry *ind) ++{ ++ struct elf64_mb_link_hash_entry *edir, *eind; ++ ++ edir = (struct elf64_mb_link_hash_entry *) dir; ++ eind = (struct elf64_mb_link_hash_entry *) ind; ++ ++ if (eind->dyn_relocs != NULL) ++ { ++ if (edir->dyn_relocs != NULL) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (ind->root.type == bfd_link_hash_indirect) ++ abort (); ++ ++ /* Add reloc counts against the weak sym to the strong sym ++ list. Merge any entries against the same section. */ ++ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ struct elf64_mb_dyn_relocs *q; ++ ++ for (q = edir->dyn_relocs; q != NULL; q = q->next) ++ if (q->sec == p->sec) ++ { ++ q->pc_count += p->pc_count; ++ q->count += p->count; ++ *pp = p->next; ++ break; ++ } ++ if (q == NULL) ++ pp = &p->next; ++ } ++ *pp = edir->dyn_relocs; ++ } ++ ++ edir->dyn_relocs = eind->dyn_relocs; ++ eind->dyn_relocs = NULL; ++ } ++ ++ edir->tls_mask |= eind->tls_mask; ++ ++ _bfd_elf_link_hash_copy_indirect (info, dir, ind); ++} ++ ++static bool ++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *h) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry * eh; ++ struct elf64_mb_dyn_relocs *p; ++ asection *sdynbss; ++ asection *s, *srel; ++ unsigned int power_of_two; ++ bfd *dynobj; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ /* If this is a function, put it in the procedure linkage table. We ++ will fill in the contents of the procedure linkage table later, ++ when we know the address of the .got section. */ ++ if (h->type == STT_FUNC ++ || h->needs_plt) ++ { ++ if (h->plt.refcount <= 0 ++ || SYMBOL_CALLS_LOCAL (info, h) ++ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT ++ && h->root.type == bfd_link_hash_undefweak)) ++ { ++ /* This case can occur if we saw a PLT reloc in an input ++ file, but the symbol was never referred to by a dynamic ++ object, or if all references were garbage collected. In ++ such a case, we don't actually need to build a procedure ++ linkage table, and we can just do a PC32 reloc instead. */ ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ return true; ++ } ++ else ++ /* It's possible that we incorrectly decided a .plt reloc was ++ needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in ++ check_relocs. We can't decide accurately between function and ++ non-function syms in check-relocs; Objects loaded later in ++ the link may change h->type. So fix it now. */ ++ h->plt.offset = (bfd_vma) -1; ++ ++ /* If this is a weak symbol, and there is a real definition, the ++ processor independent code will have arranged for us to see the ++ real definition first, and we can just use the same value. */ ++ if (h->is_weakalias) ++ { ++ struct elf_link_hash_entry *def = weakdef (h); ++ BFD_ASSERT (def->root.type == bfd_link_hash_defined); ++ h->root.u.def.section = def->root.u.def.section; ++ h->root.u.def.value = def->root.u.def.value; ++ return true; ++ } ++ ++ /* This is a reference to a symbol defined by a dynamic object which ++ is not a function. */ ++ ++ /* If we are creating a shared library, we must presume that the ++ only references to the symbol are via the global offset table. ++ For such cases we need not do anything here; the relocations will ++ be handled correctly by relocate_section. */ ++ if (bfd_link_pic (info)) ++ return true; ++ ++ /* If there are no references to this symbol that do not use the ++ GOT, we don't need to generate a copy reloc. */ ++ if (!h->non_got_ref) ++ return true; ++ ++ /* If -z nocopyreloc was given, we won't generate them either. */ ++ if (info->nocopyreloc) ++ { ++ h->non_got_ref = 0; ++ return true; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ for (p = eh->dyn_relocs; p != NULL; p = p->next) ++ { ++ s = p->sec->output_section; ++ if (s != NULL && (s->flags & SEC_READONLY) != 0) ++ break; ++ } ++ ++ /* If we didn't find any dynamic relocs in read-only sections, then ++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ ++ if (p == NULL) ++ { ++ h->non_got_ref = 0; ++ return true; ++ } ++ ++ /* We must allocate the symbol in our .dynbss section, which will ++ become part of the .bss section of the executable. There will be ++ an entry for this symbol in the .dynsym section. The dynamic ++ object will contain position independent code, so all references ++ from the dynamic object to this symbol will go through the global ++ offset table. The dynamic linker will use the .dynsym entry to ++ determine the address it must put in the global offset table, so ++ both the dynamic object and the regular object will refer to the ++ same memory location for the variable. */ ++ ++ /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker ++ to copy the initial value out of the dynamic object and into the ++ runtime process image. */ ++ dynobj = elf_hash_table (info)->dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) ++ { ++ htab->srelbss->size += sizeof (Elf64_External_Rela); ++ h->needs_copy = 1; ++ } ++ ++ /* We need to figure out the alignment required for this symbol. I ++ have no idea how ELF linkers handle this. */ ++ power_of_two = bfd_log2 (h->size); ++ if (power_of_two > 3) ++ power_of_two = 3; ++ ++ sdynbss = htab->sdynbss; ++ /* Apply the required alignment. */ ++ sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two)); ++ if (power_of_two > sdynbss->alignment_power) ++ { ++ if (! bfd_set_section_alignment (sdynbss, power_of_two)) ++ return false; ++ } ++ ++ /* Define the symbol as being at this point in the section. */ ++ h->root.u.def.section = s; ++ h->root.u.def.value = s->size; ++ ++ /* Increment the section size to make room for the symbol. */ ++ s->size += h->size; ++ return true; ++} ++ ++/* Allocate space in .plt, .got and associated reloc sections for ++ dynamic relocs. */ ++ ++static bool ++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat) ++{ ++ struct bfd_link_info *info; ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (h->root.type == bfd_link_hash_indirect) ++ return true; ++ ++ info = (struct bfd_link_info *) dat; ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ if (htab->elf.dynamic_sections_created ++ && h->plt.refcount > 0) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return false; ++ } ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h)) ++ { ++ asection *s = htab->elf.splt; ++ ++ /* The first entry in .plt is reserved. */ ++ if (s->size == 0) ++ s->size = PLT_ENTRY_SIZE; ++ ++ h->plt.offset = s->size; ++ ++ /* If this symbol is not defined in a regular file, and we are ++ not generating a shared library, then set the symbol to this ++ location in the .plt. This is required to make function ++ pointers compare as equal between the normal executable and ++ the shared library. */ ++ if (! bfd_link_pic (info) ++ && !h->def_regular) ++ { ++ h->root.u.def.section = s; ++ h->root.u.def.value = h->plt.offset; ++ } ++ ++ /* Make room for this entry. */ ++ s->size += PLT_ENTRY_SIZE; ++ ++ /* We also need to make an entry in the .got.plt section, which ++ will be placed in the .got section by the linker script. */ ++ htab->elf.sgotplt->size += 4; ++ ++ /* We also need to make an entry in the .rel.plt section. */ ++ htab->elf.srelplt->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ if (h->got.refcount > 0) ++ { ++ unsigned int need; ++ asection *s; ++ ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return false; ++ } ++ ++ need = 0; ++ if ((eh->tls_mask & TLS_TLS) != 0) ++ { ++ /* Handle TLS Symbol */ ++ if ((eh->tls_mask & TLS_LD) != 0) ++ { ++ if (!eh->elf.def_dynamic) ++ /* We'll just use htab->tlsld_got.offset. This should ++ always be the case. It's a little odd if we have ++ a local dynamic reloc against a non-local symbol. */ ++ htab->tlsld_got.refcount += 1; ++ else ++ need += 8; ++ } ++ if ((eh->tls_mask & TLS_GD) != 0) ++ need += 8; ++ } ++ else ++ { ++ /* Regular (non-TLS) symbol */ ++ need += 4; ++ } ++ if (need == 0) ++ { ++ h->got.offset = (bfd_vma) -1; ++ } ++ else ++ { ++ s = htab->elf.sgot; ++ h->got.offset = s->size; ++ s->size += need; ++ htab->elf.srelgot->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ h->got.offset = (bfd_vma) -1; ++ ++ if (eh->dyn_relocs == NULL) ++ return true; ++ ++ /* In the shared -Bsymbolic case, discard space allocated for ++ dynamic pc-relative relocs against symbols which turn out to be ++ defined in regular objects. For the normal shared case, discard ++ space for pc-relative relocs that have become local due to symbol ++ visibility changes. */ ++ ++ if (bfd_link_pic (info)) ++ { ++ if (h->def_regular ++ && (h->forced_local ++ || info->symbolic)) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ ++ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ p->count -= p->pc_count; ++ p->pc_count = 0; ++ if (p->count == 0) ++ *pp = p->next; ++ else ++ pp = &p->next; ++ } ++ } ++ else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) ++ h->dyn_relocs = NULL; ++ } ++ else ++ { ++ /* For the non-shared case, discard space for relocs against ++ symbols which turn out to need copy relocs or are not ++ dynamic. */ ++ ++ if (!h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || (htab->elf.dynamic_sections_created ++ && (h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined)))) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return false; ++ } ++ ++ /* If that succeeded, we know we'll be keeping all the ++ relocs. */ ++ if (h->dynindx != -1) ++ goto keep; ++ } ++ ++ h->dyn_relocs = NULL; ++ ++ keep: ; ++ } ++ ++ /* Finally, allocate space. */ ++ for (p = h->dyn_relocs; p != NULL; p = p->next) ++ { ++ asection *sreloc = elf_section_data (p->sec)->sreloc; ++ sreloc->size += p->count * sizeof (Elf64_External_Rela); ++ } ++ ++ return true; ++} ++ ++/* Set the sizes of the dynamic sections. */ ++ ++static bool ++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ bfd *dynobj; ++ asection *s; ++ bfd *ibfd; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ dynobj = htab->elf.dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ ++ /* Set up .got offsets for local syms, and space for local dynamic ++ relocs. */ ++ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) ++ { ++ bfd_signed_vma *local_got; ++ bfd_signed_vma *end_local_got; ++ bfd_size_type locsymcount; ++ Elf_Internal_Shdr *symtab_hdr; ++ unsigned char *lgot_masks; ++ asection *srel; ++ ++ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) ++ continue; ++ ++ for (s = ibfd->sections; s != NULL; s = s->next) ++ { ++ struct elf_dyn_relocs *p; ++ ++ for (p = ((struct elf64_mb_dyn_relocs *) ++ elf_section_data (s)->local_dynrel); ++ p != NULL; ++ p = p->next) ++ { ++ if (!bfd_is_abs_section (p->sec) ++ && bfd_is_abs_section (p->sec->output_section)) ++ { ++ /* Input section has been discarded, either because ++ it is a copy of a linkonce section or due to ++ linker script /DISCARD/, so we'll be discarding ++ the relocs too. */ ++ } ++ else if (p->count != 0) ++ { ++ srel = elf_section_data (p->sec)->sreloc; ++ srel->size += p->count * sizeof (Elf64_External_Rela); ++ if ((p->sec->output_section->flags & SEC_READONLY) != 0) ++ info->flags |= DF_TEXTREL; ++ } ++ } ++ } ++ ++ local_got = elf_local_got_refcounts (ibfd); ++ if (!local_got) ++ continue; ++ ++ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; ++ locsymcount = symtab_hdr->sh_info; ++ end_local_got = local_got + locsymcount; ++ lgot_masks = (unsigned char *) end_local_got; ++ s = htab->elf.sgot; ++ srel = htab->elf.srelgot; ++ ++ for (; local_got < end_local_got; ++local_got, ++lgot_masks) ++ { ++ if (*local_got > 0) ++ { ++ unsigned int need = 0; ++ if ((*lgot_masks & TLS_TLS) != 0) ++ { ++ if ((*lgot_masks & TLS_GD) != 0) ++ need += 8; ++ if ((*lgot_masks & TLS_LD) != 0) ++ htab->tlsld_got.refcount += 1; ++ } ++ else ++ need += 4; ++ ++ if (need == 0) ++ { ++ *local_got = (bfd_vma) -1; ++ } ++ else ++ { ++ *local_got = s->size; ++ s->size += need; ++ if (bfd_link_pic (info)) ++ srel->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ *local_got = (bfd_vma) -1; ++ } ++ } ++ ++ /* Allocate global sym .plt and .got entries, and space for global ++ sym dynamic relocs. */ ++ elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info); ++ ++ if (htab->tlsld_got.refcount > 0) ++ { ++ htab->tlsld_got.offset = htab->elf.sgot->size; ++ htab->elf.sgot->size += 8; ++ if (bfd_link_pic (info)) ++ htab->elf.srelgot->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ htab->tlsld_got.offset = (bfd_vma) -1; ++ ++ if (elf_hash_table (info)->dynamic_sections_created) ++ { ++ /* Make space for the trailing nop in .plt. */ ++ if (htab->elf.splt->size > 0) ++ htab->elf.splt->size += 4; ++ } ++ ++ /* The check_relocs and adjust_dynamic_symbol entry points have ++ determined the sizes of the various dynamic sections. Allocate ++ memory for them. */ ++ for (s = dynobj->sections; s != NULL; s = s->next) ++ { ++ const char *name; ++ bool strip = false; ++ ++ if ((s->flags & SEC_LINKER_CREATED) == 0) ++ continue; ++ ++ /* It's OK to base decisions on the section name, because none ++ of the dynobj section names depend upon the input files. */ ++ name = bfd_section_name (s); ++ ++ if (startswith (name, ".rela")) ++ { ++ if (s->size == 0) ++ { ++ /* If we don't need this section, strip it from the ++ output file. This is to handle .rela.bss and ++ .rela.plt. We must create it in ++ create_dynamic_sections, because it must be created ++ before the linker maps input sections to output ++ sections. The linker does that before ++ adjust_dynamic_symbol is called, and it is that ++ function which decides whether anything needs to go ++ into these sections. */ ++ strip = true; ++ } ++ else ++ { ++ /* We use the reloc_count field as a counter if we need ++ to copy relocs into the output file. */ ++ s->reloc_count = 0; ++ } ++ } ++ else if (s != htab->elf.splt ++ && s != htab->elf.sgot ++ && s != htab->elf.sgotplt ++ && s != htab->elf.sdynbss ++ && s != htab->elf.sdynrelro) ++ { ++ /* It's not one of our sections, so don't allocate space. */ ++ continue; ++ } ++ ++ if (strip) ++ { ++ s->flags |= SEC_EXCLUDE; ++ continue; ++ } ++ ++ /* Allocate memory for the section contents. */ ++ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. ++ Unused entries should be reclaimed before the section's contents ++ are written out, but at the moment this does not happen. Thus in ++ order to prevent writing out garbage, we initialise the section's ++ contents to zero. */ ++ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); ++ if (s->contents == NULL && s->size != 0) ++ return false; ++ } ++ ++ /* ??? Force DF_BIND_NOW? */ ++ info->flags |= DF_BIND_NOW; ++ return _bfd_elf_add_dynamic_tags (output_bfd, info, true); ++} ++ ++/* Finish up dynamic symbol handling. We set the contents of various ++ dynamic sections here. */ ++ ++static bool ++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd, ++ struct bfd_link_info *info, ++ struct elf_link_hash_entry *h, ++ Elf_Internal_Sym *sym) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ if (h->plt.offset != (bfd_vma) -1) ++ { ++ asection *splt; ++ asection *srela; ++ asection *sgotplt; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ bfd_vma plt_index; ++ bfd_vma got_offset; ++ bfd_vma got_addr; ++ ++ /* This symbol has an entry in the procedure linkage table. Set ++ it up. */ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ splt = htab->elf.splt; ++ srela = htab->elf.srelplt; ++ sgotplt = htab->elf.sgotplt; ++ BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL); ++ ++ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved. */ ++ got_offset = (plt_index + 3) * 4; /* 3 reserved ??? */ ++ got_addr = got_offset; ++ ++ /* For non-PIC objects we need absolute address of the GOT entry. */ ++ if (!bfd_link_pic (info)) ++ got_addr += sgotplt->output_section->vma + sgotplt->output_offset; ++ ++ /* Fill in the entry in the procedure linkage table. */ ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff), ++ splt->contents + h->plt.offset); ++ if (bfd_link_pic (info)) ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ else ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2, ++ splt->contents + h->plt.offset + 8); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3, ++ splt->contents + h->plt.offset + 12); ++ ++ /* Any additions to the .got section??? */ ++ /* bfd_put_32 (output_bfd, ++ splt->output_section->vma + splt->output_offset + h->plt.offset + 4, ++ sgotplt->contents + got_offset); */ ++ ++ /* Fill in the entry in the .rela.plt section. */ ++ rela.r_offset = (sgotplt->output_section->vma ++ + sgotplt->output_offset ++ + got_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT); ++ rela.r_addend = 0; ++ loc = srela->contents; ++ loc += plt_index * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); ++ ++ if (!h->def_regular) ++ { ++ /* Mark the symbol as undefined, rather than as defined in ++ the .plt section. Zero the value. */ ++ sym->st_shndx = SHN_UNDEF; ++ sym->st_value = 0; ++ } ++ } ++ ++ /* h->got.refcount to be checked ? */ ++ if (h->got.offset != (bfd_vma) -1 && ++ ! ((h->got.offset & 1) || ++ IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask))) ++ { ++ asection *sgot; ++ asection *srela; ++ bfd_vma offset; ++ ++ /* This symbol has an entry in the global offset table. Set it ++ up. */ ++ ++ sgot = htab->elf.sgot; ++ srela = htab->elf.srelgot; ++ BFD_ASSERT (sgot != NULL && srela != NULL); ++ ++ offset = (sgot->output_section->vma + sgot->output_offset ++ + (h->got.offset &~ (bfd_vma) 1)); ++ ++ /* If this is a -Bsymbolic link, and the symbol is defined ++ locally, we just want to emit a RELATIVE reloc. Likewise if ++ the symbol was forced to be local because of a version file. ++ The entry in the global offset table will already have been ++ initialized in the relocate_section function. */ ++ if (bfd_link_pic (info) ++ && ((info->symbolic && h->def_regular) ++ || h->dynindx == -1)) ++ { ++ asection *sec = h->root.u.def.section; ++ bfd_vma value; ++ ++ value = h->root.u.def.value; ++ if (sec->output_section != NULL) ++ /* PR 21180: If the output section is NULL, then the symbol is no ++ longer needed, and in theory the GOT entry is redundant. But ++ it is too late to change our minds now... */ ++ value += sec->output_section->vma + sec->output_offset; ++ ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ /* symindex= */ 0, ++ R_MICROBLAZE_REL, offset, ++ value); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ h->dynindx, ++ R_MICROBLAZE_GLOB_DAT, ++ offset, 0); ++ } ++ ++ bfd_put_32 (output_bfd, (bfd_vma) 0, ++ sgot->contents + (h->got.offset &~ (bfd_vma) 1)); ++ } ++ ++ if (h->needs_copy) ++ { ++ asection *s; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ ++ /* This symbols needs a copy reloc. Set it up. */ ++ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ rela.r_offset = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY); ++ rela.r_addend = 0; ++ if (h->root.u.def.section == htab->elf.sdynrelro) ++ s = htab->elf.sreldynrelro; ++ else ++ s = htab->elf.srelbss; ++ loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela); ++ bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); ++ } ++ ++ /* Mark some specially defined symbols as absolute. */ ++ if (h == htab->elf.hdynamic ++ || h == htab->elf.hgot ++ || h == htab->elf.hplt) ++ sym->st_shndx = SHN_ABS; ++ ++ return true; ++} ++ ++ ++/* Finish up the dynamic sections. */ ++ ++static bool ++microblaze_elf_finish_dynamic_sections (bfd *output_bfd, ++ struct bfd_link_info *info) ++{ ++ bfd *dynobj; ++ asection *sdyn, *sgot; ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return false; ++ ++ dynobj = htab->elf.dynobj; ++ ++ sdyn = bfd_get_linker_section (dynobj, ".dynamic"); ++ ++ if (htab->elf.dynamic_sections_created) ++ { ++ asection *splt; ++ Elf64_External_Dyn *dyncon, *dynconend; ++ ++ dyncon = (Elf64_External_Dyn *) sdyn->contents; ++ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size); ++ for (; dyncon < dynconend; dyncon++) ++ { ++ Elf_Internal_Dyn dyn; ++ asection *s; ++ bool size; ++ ++ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn); ++ ++ switch (dyn.d_tag) ++ { ++ case DT_PLTGOT: ++ s = htab->elf.sgotplt; ++ size = false; ++ break; ++ ++ case DT_PLTRELSZ: ++ s = htab->elf.srelplt; ++ size = true; ++ break; ++ ++ case DT_JMPREL: ++ s = htab->elf.srelplt; ++ size = false; ++ break; ++ ++ default: ++ continue; ++ } ++ ++ if (s == NULL) ++ dyn.d_un.d_val = 0; ++ else ++ { ++ if (!size) ++ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; ++ else ++ dyn.d_un.d_val = s->size; ++ } ++ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon); ++ } ++ ++ splt = htab->elf.splt; ++ BFD_ASSERT (splt != NULL && sdyn != NULL); ++ ++ /* Clear the first entry in the procedure linkage table, ++ and put a nop in the last four bytes. */ ++ if (splt->size > 0) ++ { ++ memset (splt->contents, 0, PLT_ENTRY_SIZE); ++ bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop. */, ++ splt->contents + splt->size - 4); ++ ++ if (splt->output_section != bfd_abs_section_ptr) ++ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; ++ } ++ } ++ ++ /* Set the first entry in the global offset table to the address of ++ the dynamic section. */ ++ sgot = htab->elf.sgotplt; ++ if (sgot && sgot->size > 0) ++ { ++ if (sdyn == NULL) ++ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); ++ else ++ bfd_put_32 (output_bfd, ++ sdyn->output_section->vma + sdyn->output_offset, ++ sgot->contents); ++ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; ++ } ++ ++ if (htab->elf.sgot && htab->elf.sgot->size > 0) ++ elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize = 4; ++ ++ return true; ++} ++ ++/* Hook called by the linker routine which adds symbols from an object ++ file. We use it to put .comm items in .sbss, and not .bss. */ ++ ++static bool ++microblaze_elf_add_symbol_hook (bfd *abfd, ++ struct bfd_link_info *info, ++ Elf_Internal_Sym *sym, ++ const char **namep ATTRIBUTE_UNUSED, ++ flagword *flagsp ATTRIBUTE_UNUSED, ++ asection **secp, ++ bfd_vma *valp) ++{ ++ if (sym->st_shndx == SHN_COMMON ++ && !bfd_link_relocatable (info) ++ && sym->st_size <= elf_gp_size (abfd)) ++ { ++ /* Common symbols less than or equal to -G nn bytes are automatically ++ put into .sbss. */ ++ *secp = bfd_make_section_old_way (abfd, ".sbss"); ++ if (*secp == NULL ++ || !bfd_set_section_flags (*secp, SEC_IS_COMMON | SEC_SMALL_DATA)) ++ return false; ++ ++ *valp = sym->st_size; ++ } ++ ++ return true; ++} ++ ++#define TARGET_LITTLE_SYM microblaze_elf64_le_vec ++#define TARGET_LITTLE_NAME "elf64-microblazeel" ++ ++#define TARGET_BIG_SYM microblaze_elf64_vec ++#define TARGET_BIG_NAME "elf64-microblaze" ++ ++#define ELF_ARCH bfd_arch_microblaze ++#define ELF_TARGET_ID MICROBLAZE_ELF_DATA ++#define ELF_MACHINE_CODE EM_MICROBLAZE ++#define ELF_MACHINE_ALT1 EM_MICROBLAZE_OLD ++#define ELF_MAXPAGESIZE 0x1000 ++#define elf_info_to_howto microblaze_elf_info_to_howto ++#define elf_info_to_howto_rel NULL ++ ++#define bfd_elf64_bfd_reloc_type_lookup microblaze_elf_reloc_type_lookup ++#define bfd_elf64_bfd_is_local_label_name microblaze_elf_is_local_label_name ++#define bfd_elf64_new_section_hook microblaze_elf_new_section_hook ++#define elf_backend_relocate_section microblaze_elf_relocate_section ++#define bfd_elf64_bfd_relax_section microblaze_elf_relax_section ++#define bfd_elf64_bfd_merge_private_bfd_data microblaze_elf_merge_private_bfd_data ++#define bfd_elf64_bfd_reloc_name_lookup microblaze_elf_reloc_name_lookup ++ ++#define elf_backend_gc_mark_hook microblaze_elf_gc_mark_hook ++#define elf_backend_gc_sweep_hook microblaze_elf_gc_sweep_hook ++#define elf_backend_check_relocs microblaze_elf_check_relocs ++#define elf_backend_copy_indirect_symbol microblaze_elf_copy_indirect_symbol ++#define bfd_elf64_bfd_link_hash_table_create microblaze_elf_link_hash_table_create ++#define elf_backend_can_gc_sections 1 ++#define elf_backend_can_refcount 1 ++#define elf_backend_want_got_plt 1 ++#define elf_backend_plt_readonly 1 ++#define elf_backend_got_header_size 12 ++#define elf_backend_want_dynrelro 1 ++#define elf_backend_rela_normal 1 ++#define elf_backend_dtrel_excludes_plt 1 ++ ++#define elf_backend_adjust_dynamic_symbol microblaze_elf_adjust_dynamic_symbol ++#define elf_backend_create_dynamic_sections microblaze_elf_create_dynamic_sections ++#define elf_backend_finish_dynamic_sections microblaze_elf_finish_dynamic_sections ++#define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol ++#define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections ++#define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook ++ ++#include "elf64-target.h" +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 9450882e850..f265e8fc608 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -65,8 +65,95 @@ + #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \ + ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0) + ++static const char *microblaze_abi_string; ++ ++static const char *const microblaze_abi_strings[] = { ++ "auto", ++ "m64", ++}; ++ ++enum microblaze_abi ++microblaze_abi (struct gdbarch *gdbarch) ++{ ++ microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ return tdep->microblaze_abi; ++} + /* The registers of the Xilinx microblaze processor. */ + ++ static struct cmd_list_element *setmicroblazecmdlist = NULL; ++ static struct cmd_list_element *showmicroblazecmdlist = NULL; ++ ++static void ++microblaze_abi_update (const char *ignore_args, ++ int from_tty, struct cmd_list_element *c) ++{ ++ struct gdbarch_info info; ++ ++ /* Force the architecture to update, and (if it's a microblaze architecture) ++ * microblaze_gdbarch_init will take care of the rest. */ ++// gdbarch_info_init (&info); ++ gdbarch_update_p (info); ++} ++ ++ ++static enum microblaze_abi ++global_microblaze_abi (void) ++{ ++ int i; ++ ++ for (i = 0; microblaze_abi_strings[i] != NULL; i++) ++ if (microblaze_abi_strings[i] == microblaze_abi_string) ++ return (enum microblaze_abi) i; ++ ++// internal_error (__FILE__, __LINE__, _("unknown ABI string")); ++} ++ ++static void ++show_microblaze_abi (struct ui_file *file, ++ int from_tty, ++ struct cmd_list_element *ignored_cmd, ++ const char *ignored_value) ++{ ++ enum microblaze_abi global_abi = global_microblaze_abi (); ++ enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ()); ++ const char *actual_abi_str = microblaze_abi_strings[actual_abi]; ++ ++#if 1 ++ if (global_abi == MICROBLAZE_ABI_AUTO) ++ fprintf_filtered ++ (file, ++ "The microblaze ABI is set automatically (currently \"%s\").\n", ++ actual_abi_str); ++ else if (global_abi == actual_abi) ++ fprintf_filtered ++ (file, ++ "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n", ++ actual_abi_str); ++ else ++ { ++#endif ++ /* Probably shouldn't happen... */ ++ fprintf_filtered (file, ++ "The (auto detected) microblaze ABI \"%s\" is in use " ++ "even though the user setting was \"%s\".\n", ++ actual_abi_str, microblaze_abi_strings[global_abi]); ++ } ++} ++ ++static void ++show_microblaze_command (const char *args, int from_tty) ++{ ++ help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout); ++} ++ ++static void ++set_microblaze_command (const char *args, int from_tty) ++{ ++ printf_unfiltered ++ ("\"set microblaze\" must be followed by an appropriate subcommand.\n"); ++ help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout); ++} ++ + static const char * const microblaze_register_names[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", +@@ -85,9 +172,21 @@ static const char * const microblaze_register_names[] = + static unsigned int microblaze_debug_flag = 0; + int reg_size = 4; + ++unsigned int ++microblaze_abi_regsize (struct gdbarch *gdbarch) ++{ ++ switch (microblaze_abi (gdbarch)) ++ { ++ case MICROBLAZE_ABI_M64: ++ return 8; ++ default: ++ return 4; ++ } ++} ++ + #define microblaze_debug(fmt, ...) \ + debug_prefixed_printf_cond_nofunc (microblaze_debug_flag, "MICROBLAZE", \ +- fmt, ## __VA_ARGS__) ++ fmt, ## __VA_ARGS__) + + + /* Return the name of register REGNUM. */ +@@ -867,15 +966,30 @@ static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { + tdesc_arch_data_up tdesc_data; ++ enum microblaze_abi microblaze_abi, found_abi, wanted_abi; + const struct target_desc *tdesc = info.target_desc; + ++ /* What has the user specified from the command line? */ ++ wanted_abi = global_microblaze_abi (); ++ if (gdbarch_debug) ++ fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", ++ wanted_abi); ++ if (wanted_abi != MICROBLAZE_ABI_AUTO) ++ microblaze_abi = wanted_abi; ++ + /* If there is already a candidate, use it. */ + arches = gdbarch_list_lookup_by_info (arches, &info); +- if (arches != NULL) ++ if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) + return arches->gdbarch; ++ ++ if (microblaze_abi == MICROBLAZE_ABI_M64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } + if (tdesc == NULL) + { +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + { + tdesc = tdesc_microblaze64; + reg_size = 8; +@@ -890,7 +1004,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.core"); + else +@@ -904,7 +1018,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + for (i = 0; i < MICROBLAZE_NUM_REGS; i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, + microblaze_register_names[i]); +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.stack-protect"); + else +@@ -954,7 +1068,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + set_gdbarch_ptr_bit (gdbarch, 64); + break; + } +- ++ if(microblaze_abi == MICROBLAZE_ABI_M64) ++ set_gdbarch_ptr_bit (gdbarch, 64); + + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); +@@ -1014,6 +1129,38 @@ _initialize_microblaze_tdep () + { + gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init); + ++// static struct cmd_list_element *setmicroblazecmdlist = NULL; ++// static struct cmd_list_element *showmicroblazecmdlist = NULL; ++ ++ /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ ++ ++ add_setshow_prefix_cmd ("microblaze", no_class, ++ _("Various microblaze specific commands."), ++ _("Various microblaze specific commands."), ++ &setmicroblazecmdlist,&showmicroblazecmdlist, ++ &setlist,&showlist); ++#if 0 ++ add_prefix_cmd ("microblaze", no_class, set_microblaze_command, ++ _("Various microblaze specific commands."), ++ &setmicroblazecmdlist, "set microblaze ", 0, &setlist); ++ ++ add_prefix_cmd ("microblaze", no_class, show_microblaze_command, ++ _("Various microblaze specific commands."), ++ &showmicroblazecmdlist, "show microblaze ", 0, &showlist); ++#endif ++ ++ /* Allow the user to override the ABI. */ ++ add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings, ++ µblaze_abi_string, _("\ ++Set the microblaze ABI used by this program."), _("\ ++Show the microblaze ABI used by this program."), _("\ ++This option can be set to one of:\n\ ++ auto - the default ABI associated with the current binary\n\ ++ m64"), ++ microblaze_abi_update, ++ show_microblaze_abi, ++ &setmicroblazecmdlist, &showmicroblazecmdlist); ++ + initialize_tdesc_microblaze_with_stack_protect (); + initialize_tdesc_microblaze (); + initialize_tdesc_microblaze64_with_stack_protect (); +@@ -1028,5 +1175,4 @@ When non-zero, microblaze specific debugging is enabled."), + NULL, + &setdebuglist, &showdebuglist); + +- + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 542cdd82070..17a4bb5190c 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -19,9 +19,17 @@ + + #ifndef MICROBLAZE_TDEP_H + #define MICROBLAZE_TDEP_H 1 +- ++#include "objfiles.h" + #include "gdbarch.h" + ++struct gdbarch; ++enum microblaze_abi ++ { ++ MICROBLAZE_ABI_AUTO = 0, ++ MICROBLAZE_ABI_M64, ++ }; ++ ++enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch); + /* Microblaze architecture-specific information. */ + struct microblaze_gregset + { +@@ -35,11 +43,14 @@ struct microblaze_gdbarch_tdep : gdbarch_tdep_base + { + int dummy; // declare something. + ++ enum microblaze_abi microblaze_abi {}; ++ enum microblaze_abi found_abi {}; + /* Register sets. */ + struct regset *gregset; + size_t sizeof_gregset; + struct regset *fpregset; + size_t sizeof_fpregset; ++ int register_size; + }; + + /* Register numbers. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze.patch deleted file mode 100644 index 941a3b9c..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 0532b1db08b9d8efc670f7288fe2d8168b8ed0d1 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 21 Jul 2022 11:45:01 +0530 -Subject: [PATCH 8/8] =?UTF-8?q?[Patch,MicroBlaze]:=20Depth:=20=20Total=20n?= - =?UTF-8?q?umber=20of=20inline=20functions=20[refer=20inline-frame.c]=20st?= - =?UTF-8?q?ate->skipped=5Fframes=20:=20Number=20of=20inline=20functions=20?= - =?UTF-8?q?skipped.=20the=20current=20unwind=5Fpc=20is=20causing=20an=20is?= - =?UTF-8?q?sue=20when=20we=20try=20to=20step=20into=20inline=20functions[D?= - =?UTF-8?q?epth=20is=20becoming=200].=20It=E2=80=99s=20incrementing=20pc?= - =?UTF-8?q?=20by=208=20even=20with=20si=20instruction.?= -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - ---- - gdb/microblaze-tdep.c | 14 +++----------- - 1 file changed, 3 insertions(+), 11 deletions(-) - -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index d83072cdaef..38ba38e8c7d 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -513,16 +513,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, - static CORE_ADDR - microblaze_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) - { -- gdb_byte buf[4]; - CORE_ADDR pc; -- -- frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf); -- pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); -- /* For sentinel frame, return address is actual PC. For other frames, -- return address is pc+8. This is a workaround because gcc does not -- generate correct return address in CIE. */ -- if (frame_relative_level (next_frame) >= 0) -- pc += 8; -+ pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM); - return pc; - } - -@@ -553,7 +545,6 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) - ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, - &cache); - -- - if (ostart_pc > start_pc) - return ostart_pc; - return start_pc; -@@ -660,7 +651,8 @@ static const struct frame_unwind microblaze_frame_unwind = - microblaze_frame_this_id, - microblaze_frame_prev_register, - NULL, -- default_frame_sniffer -+ default_frame_sniffer, -+ NULL, - }; - - static CORE_ADDR --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch new file mode 100644 index 00000000..6769e1ee --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0009-Depth-Total-number-of-inline-functions-refer-inline-.patch @@ -0,0 +1,74 @@ +From c37f307714121981fa91766c539913f7912643b7 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 21 Jul 2022 11:45:01 +0530 +Subject: [PATCH 09/54] =?UTF-8?q?Depth:=20Total=20number=20of=20inline=20f?= + =?UTF-8?q?unctions=20[refer=20inline-frame.c]=20state->skipped=5Fframes?= + =?UTF-8?q?=20:=20Number=20of=20inline=20functions=20skipped.=20the=20curr?= + =?UTF-8?q?ent=20unwind=5Fpc=20is=20causing=20an=20issue=20when=20we=20try?= + =?UTF-8?q?=20to=20step=20into=20inline=20functions[Depth=20is=20becoming?= + =?UTF-8?q?=200].=20It=E2=80=99s=20incrementing=20pc=20by=208=20even=20wit?= + =?UTF-8?q?h=20si=20instruction.?= +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Aayush Misra +--- + gdb/features/microblaze64.xml | 1 + + gdb/microblaze-tdep.c | 14 +++----------- + 2 files changed, 4 insertions(+), 11 deletions(-) + +diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml +index 515d18e65cf..9c1b7d22003 100644 +--- a/gdb/features/microblaze64.xml ++++ b/gdb/features/microblaze64.xml +@@ -7,5 +7,6 @@ + + + ++ microblaze64 + + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index f265e8fc608..3e541789fac 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -513,16 +513,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, + static CORE_ADDR + microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) + { +- gdb_byte buf[4]; + CORE_ADDR pc; +- +- frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf); +- pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); +- /* For sentinel frame, return address is actual PC. For other frames, +- return address is pc+8. This is a workaround because gcc does not +- generate correct return address in CIE. */ +- if (frame_relative_level (next_frame) >= 0) +- pc += 8; ++ pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM); + return pc; + } + +@@ -553,7 +545,6 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) + ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, + &cache); + +- + if (ostart_pc > start_pc) + return ostart_pc; + return start_pc; +@@ -660,7 +651,8 @@ static const struct frame_unwind microblaze_frame_unwind = + microblaze_frame_this_id, + microblaze_frame_prev_register, + NULL, +- default_frame_sniffer ++ default_frame_sniffer, ++ NULL, + }; + + static CORE_ADDR +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch deleted file mode 100644 index 6a930420..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0009-gdb-gdserver-Fix-ABI-settings-for-gdbserver.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 53b76bb548720367032a51a6d604c975b10bb30e Mon Sep 17 00:00:00 2001 -From: Aayush Misra -Date: Fri, 29 Mar 2024 14:59:16 +0530 -Subject: [PATCH] gdb/gdserver: Fix ABI settings for gdbserver - -Upstream-Status: Pending - ---- - gdb/microblaze-tdep.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index 38ba38e8c7d..35cec286d8f 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -1120,12 +1120,13 @@ void _initialize_microblaze_tdep (); - void - _initialize_microblaze_tdep () - { -+ //Setting abi to auto manually, should be able to modify in 'arch'_gdbarch_init function -+ microblaze_abi_string = microblaze_abi_strings[0]; -+ - register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init); --// static struct cmd_list_element *setmicroblazecmdlist = NULL; --// static struct cmd_list_element *showmicroblazecmdlist = NULL; - -- /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ - -+ /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ - add_setshow_prefix_cmd ("microblaze", no_class, - _("Various microblaze specific commands."), - _("Various microblaze specific commands."), --- -2.34.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch new file mode 100644 index 00000000..e5c88f01 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0010-Fix-gdb-14-build-errors-for-microblaze-xilinx-elf-20.patch @@ -0,0 +1,133 @@ +From 6b6632b730808a012738f9eddf621abd6463e317 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 29 Feb 2024 10:53:04 +0530 +Subject: [PATCH 10/54] Fix gdb-14 build errors for microblaze-xilinx-elf + 2023.2 merge + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 12 ++++++++++++ + gdb/frame.c | 2 +- + gdb/microblaze-tdep.c | 17 +++++++++++------ + 3 files changed, 24 insertions(+), 7 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 6cd9753a592..119d266f95a 100755 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -750,6 +750,18 @@ microblaze_elf_info_to_howto (bfd * abfd, + return true; + } + ++/* Relax table contains information about instructions which can ++ be removed by relaxation -- replacing a long address with a ++ short address. */ ++struct relax_table ++{ ++ /* Address where bytes may be deleted. */ ++ bfd_vma addr; ++ ++ /* Number of bytes to be deleted. */ ++ size_t size; ++}; ++ + struct _microblaze_elf_section_data + { + struct bfd_elf_section_data elf; +diff --git a/gdb/frame.c b/gdb/frame.c +index c4d967e01d5..8be230e0617 100644 +--- a/gdb/frame.c ++++ b/gdb/frame.c +@@ -1315,7 +1315,7 @@ frame_unwind_register_value (frame_info_ptr next_frame, int regnum) + int i; + + const gdb_byte *buf = NULL; +- if (value_entirely_available(value)) { ++ if (value->entirely_available()) { + gdb::array_view buf = value->contents (); + } + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 3e541789fac..f7d9d6419ce 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -75,7 +75,7 @@ static const char *const microblaze_abi_strings[] = { + enum microblaze_abi + microblaze_abi (struct gdbarch *gdbarch) + { +- microblaze_gdbarch_tdep *tdep = (microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + return tdep->microblaze_abi; + } + /* The registers of the Xilinx microblaze processor. */ +@@ -120,12 +120,12 @@ show_microblaze_abi (struct ui_file *file, + + #if 1 + if (global_abi == MICROBLAZE_ABI_AUTO) +- fprintf_filtered ++ gdb_printf + (file, + "The microblaze ABI is set automatically (currently \"%s\").\n", + actual_abi_str); + else if (global_abi == actual_abi) +- fprintf_filtered ++ gdb_printf + (file, + "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n", + actual_abi_str); +@@ -133,7 +133,7 @@ show_microblaze_abi (struct ui_file *file, + { + #endif + /* Probably shouldn't happen... */ +- fprintf_filtered (file, ++ gdb_printf (file, + "The (auto detected) microblaze ABI \"%s\" is in use " + "even though the user setting was \"%s\".\n", + actual_abi_str, microblaze_abi_strings[global_abi]); +@@ -934,7 +934,7 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, + void *cb_data, + const struct regcache *regcache) + { +- struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); + +@@ -942,6 +942,8 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, + } + + ++#if 0 ++// compilation errors - function is not actually used ? + static void + make_regs (struct gdbarch *arch) + { +@@ -953,6 +955,7 @@ make_regs (struct gdbarch *arch) + set_gdbarch_ptr_bit (arch, 64); + } + } ++#endif + + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -964,7 +967,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + /* What has the user specified from the command line? */ + wanted_abi = global_microblaze_abi (); + if (gdbarch_debug) +- fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", ++ gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", + wanted_abi); + if (wanted_abi != MICROBLAZE_ABI_AUTO) + microblaze_abi = wanted_abi; +@@ -1038,6 +1041,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + gdbarch *gdbarch + = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep)); + ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ + tdep->gregset = NULL; + tdep->sizeof_gregset = 0; + tdep->fpregset = NULL; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch new file mode 100644 index 00000000..d7e51502 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0011-fix-gdb-microblaze-xilinx-elf-crash-issue-on-invocat.patch @@ -0,0 +1,28 @@ +From 389711a13933a60323d368d5e5f1f54bd171b16b Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 29 Feb 2024 10:55:16 +0530 +Subject: [PATCH 11/54] fix gdb microblaze-xilinx-elf crash issue on invocation + Regression from merging microblaze 64-bit support + +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index f7d9d6419ce..d4b9ef837e5 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -1124,6 +1124,9 @@ void _initialize_microblaze_tdep (); + void + _initialize_microblaze_tdep () + { ++ //Setting abi to auto manually, should be able to modify in 'arch'_gdbarch_init function ++ microblaze_abi_string = microblaze_abi_strings[0]; ++ + gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init); + + // static struct cmd_list_element *setmicroblazecmdlist = NULL; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0013-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0013-Disable-the-warning-message-for-eh_frame_hdr.patch new file mode 100644 index 00000000..8e966788 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0013-Disable-the-warning-message-for-eh_frame_hdr.patch @@ -0,0 +1,35 @@ +From ee4f6d0c1ea82b531d7481692e499fc0b35c88a8 Mon Sep 17 00:00:00 2001 +From: "Edgar E. Iglesias" +Date: Fri, 22 Jun 2012 01:20:20 +0200 +Subject: [PATCH 13/54] Disable the warning message for eh_frame_hdr + +Signed-off-by: Edgar E. Iglesias + +Conflicts: + bfd/elf-eh-frame.c +Signed-off-by: Aayush Misra +--- + bfd/elf-eh-frame.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c +index bf7a9902355..21029b59632 100644 +--- a/bfd/elf-eh-frame.c ++++ b/bfd/elf-eh-frame.c +@@ -1045,10 +1045,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info, + goto success; + + free_no_table: ++/* FIXME: Remove the microblaze specifics when relaxing gets fixed. */ ++if (bfd_get_arch(abfd) != bfd_arch_microblaze) { + _bfd_error_handler + /* xgettext:c-format */ + (_("error in %pB(%pA); no .eh_frame_hdr table will be created"), + abfd, sec); ++} + hdr_info->u.dwarf.table = false; + free (sec_info); + success: +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch new file mode 100644 index 00000000..41118c1a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0015-upstream-change-to-garbage-collection-sweep-causes-m.patch @@ -0,0 +1,43 @@ +From 6531ec7f986fff48b9efc883526018f494cf88fb Mon Sep 17 00:00:00 2001 +From: David Holsgrove +Date: Wed, 27 Feb 2013 13:56:11 +1000 +Subject: [PATCH 15/54] upstream change to garbage collection sweep causes mb + regression + +Upstream change for PR13177 now clears the def_regular during gc_sweep of a +section. (All other archs in binutils/bfd/elf32-*.c received an update +to a warning about unresolvable relocations - this warning is not present +in binutils/bfd/elf32-microblaze.c, but this warning check would not +prevent the error being seen) + +The visible issue with this change is when running a c++ application +in Petalinux which links libstdc++.so for exception handling it segfaults +on execution. + +This does not occur if static linking libstdc++.a, so its during the +relocations for a shared lib with garbage collection this occurs + +Signed-off-by: David Holsgrove + +Conflicts: + bfd/elflink.c +Signed-off-by: Aayush Misra +--- + bfd/elflink.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/bfd/elflink.c b/bfd/elflink.c +index ca162145f7e..0524019641e 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -6608,7 +6608,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data) + + inf = (struct elf_gc_sweep_symbol_info *) data; + (*inf->hide_symbol) (inf->info, h, true); +- h->def_regular = 0; + h->ref_regular = 0; + h->ref_regular_nonweak = 0; + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0016-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0016-Add-new-bit-field-instructions.patch new file mode 100644 index 00000000..30a7322d --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0016-Add-new-bit-field-instructions.patch @@ -0,0 +1,88 @@ +From 50a52ab3ad64b8525a970744dbb1c5f67dc24886 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Mon, 18 Jul 2016 12:24:28 +0530 +Subject: [PATCH 16/54] Add new bit-field instructions + +This patches adds new bsefi and bsifi instructions. +BSEFI- The instruction shall extract a bit field from a +register and place it right-adjusted in the destination register. +The other bits in the destination register shall be set to zero +BSIFI- The instruction shall insert a right-adjusted bit field +from a register at another position in the destination register. +The rest of the bits in the destination register shall be unchanged + +Signed-off-by :Nagaraju Mekala + +Conflicts: + opcodes/microblaze-dis.c + +Conflicts: + gas/config/tc-microblaze.c + opcodes/microblaze-opc.h + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++- + opcodes/microblaze-dis.c | 18 +++++++++- + opcodes/microblaze-opc.h | 6 ++++ + 3 files changed, 93 insertions(+), 2 deletions(-) + +Index: gdb-14.2/opcodes/microblaze-dis.c +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-dis.c ++++ gdb-14.2/opcodes/microblaze-dis.c +@@ -113,7 +113,19 @@ get_field_immw (struct string_buf *buf, + } + + static char * +-get_field_rfsl (struct string_buf *buf, long instr) ++get_field_imm5width (struct string_buf *buf, long instr) ++{ ++ char *p = strbuf (buf); ++ ++ if (instr & 0x00004000) ++ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ ++ else ++ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */ ++ return p; ++} ++ ++static char * ++get_field_rfsl (struct string_buf *buf,long instr) + { + char *p = strbuf (buf); + +@@ -462,6 +474,10 @@ print_insn_microblaze (bfd_vma memaddr, + print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), + get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; ++ /* For bit field insns. */ ++ case INST_TYPE_RD_R1_IMM5_IMM5: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst)); ++ break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (&buf, inst)); +Index: gdb-14.2/opcodes/microblaze-opc.h +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-opc.h ++++ gdb-14.2/opcodes/microblaze-opc.h +@@ -68,6 +68,9 @@ + #define INST_TYPE_R1_IMML 24 + #define INST_TYPE_RD_R1_IMMW_IMMS 21 + ++/* For bsefi and bsifi */ ++#define INST_TYPE_RD_R1_IMM5_IMM5 21 ++ + #define INST_TYPE_NONE 25 + + +@@ -587,5 +590,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMML ((long) 0xffffff8000000000L) + #define MAX_IMML ((long) 0x0000007fffffffffL) + ++#define MIN_IMM_WIDTH ((int) 0x00000001) ++#define MAX_IMM_WIDTH ((int) 0x00000020) ++ + #endif /* MICROBLAZE_OPC */ + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0019-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0019-initial-support-for-MicroBlaze-64-bit-m64.patch new file mode 100644 index 00000000..dc78da6b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0019-initial-support-for-MicroBlaze-64-bit-m64.patch @@ -0,0 +1,150 @@ +From 45f177e5de751f11c2d084c4d836d7f8ef754cb4 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 1 Nov 2021 19:06:53 +0530 +Subject: [PATCH 19/54] initial support for MicroBlaze 64 bit [-m64] + +Conflicts: + bfd/elf32-microblaze.c + include/elf/common.h + ld/Makefile.am + ld/Makefile.in +signed-off-by:Nagaraju Mekala + Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + bfd/bfd-in2.h | 10 ++++++++++ + bfd/libbfd.h | 2 ++ + bfd/reloc.c | 12 ++++++++++++ + gas/config/tc-microblaze.h | 4 +++- + ld/Makefile.am | 2 ++ + ld/configure.tgt | 3 +++ + opcodes/microblaze-dis.c | 8 ++++++-- + opcodes/microblaze-opc.h | 11 +++++++---- + 8 files changed, 45 insertions(+), 7 deletions(-) + +Index: gdb-14.2/bfd/bfd-in2.h +=================================================================== +--- gdb-14.2.orig/bfd/bfd-in2.h ++++ gdb-14.2/bfd/bfd-in2.h +@@ -6489,12 +6489,22 @@ done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). The relocation is ++PC-relative GOT offset */ ++ BFD_RELOC_MICROBLAZE_64_GPC, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GPC, + +Index: gdb-14.2/bfd/libbfd.h +=================================================================== +--- gdb-14.2.orig/bfd/libbfd.h ++++ gdb-14.2/bfd/libbfd.h +@@ -3012,7 +3012,9 @@ static const char *const bfd_reloc_code_ + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", ++ "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", ++ "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", +Index: gdb-14.2/bfd/reloc.c +=================================================================== +--- gdb-14.2.orig/bfd/reloc.c ++++ gdb-14.2/bfd/reloc.c +@@ -6703,6 +6703,12 @@ ENUMDOC + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64 ++ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing +@@ -6710,6 +6716,12 @@ ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64_GPC ++ENUMDOC ++ This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset + ENUM +Index: gdb-14.2/opcodes/microblaze-dis.c +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-dis.c ++++ gdb-14.2/opcodes/microblaze-dis.c +@@ -457,6 +457,10 @@ print_insn_microblaze (bfd_vma memaddr, + case INST_TYPE_R1_R2_SPECIAL: + print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), + get_field_r2 (&buf, inst)); ++ break; ++ case INST_TYPE_IMML: ++ print_func (stream, "\t%s", get_field_imml (&buf, inst)); ++ /* TODO: Also print symbol */ + break; + case INST_TYPE_RD_IMM15: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), +@@ -475,8 +479,8 @@ print_insn_microblaze (bfd_vma memaddr, + get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; + /* For bit field insns. */ +- case INST_TYPE_RD_R1_IMM5_IMM5: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst)); ++ case INST_TYPE_RD_R1_IMMW_IMMS: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; + /* For tuqula instruction */ + case INST_TYPE_RD: +Index: gdb-14.2/opcodes/microblaze-opc.h +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-opc.h ++++ gdb-14.2/opcodes/microblaze-opc.h +@@ -69,7 +69,13 @@ + #define INST_TYPE_RD_R1_IMMW_IMMS 21 + + /* For bsefi and bsifi */ +-#define INST_TYPE_RD_R1_IMM5_IMM5 21 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 ++ ++/* For 64-bit instructions */ ++#define INST_TYPE_IMML 22 ++#define INST_TYPE_RD_R1_IMML 23 ++#define INST_TYPE_R1_IMML 24 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 + + #define INST_TYPE_NONE 25 + +@@ -590,8 +596,5 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMML ((long) 0xffffff8000000000L) + #define MAX_IMML ((long) 0x0000007fffffffffL) + +-#define MIN_IMM_WIDTH ((int) 0x00000001) +-#define MAX_IMM_WIDTH ((int) 0x00000020) +- + #endif /* MICROBLAZE_OPC */ + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0020-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0020-initial-support-for-MicroBlaze-64-bit-m64.patch new file mode 100644 index 00000000..a1efcf41 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0020-initial-support-for-MicroBlaze-64-bit-m64.patch @@ -0,0 +1,82 @@ +From 8ec9b2fe49c8e1e367213fa0b8d6b6f0fedc3456 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 1 Nov 2021 19:06:53 +0530 +Subject: [PATCH 20/54] initial support for MicroBlaze 64 bit [-m64] + +Conflicts: + bfd/elf32-microblaze.c + include/elf/common.h + ld/Makefile.am + ld/Makefile.in +signed-off-by:Nagaraju Mekala + Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + ld/emulparams/elf64microblaze.sh | 23 +++++++++++++++++++++++ + ld/emulparams/elf64microblazeel.sh | 23 +++++++++++++++++++++++ + 2 files changed, 46 insertions(+) + create mode 100644 ld/emulparams/elf64microblaze.sh + create mode 100644 ld/emulparams/elf64microblazeel.sh + +diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh +new file mode 100644 +index 00000000000..9c7b0eb7080 +--- /dev/null ++++ b/ld/emulparams/elf64microblaze.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh +new file mode 100644 +index 00000000000..9c7b0eb7080 +--- /dev/null ++++ b/ld/emulparams/elf64microblazeel.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0021-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0021-Added-relocations-for-MB-X.patch new file mode 100644 index 00000000..caf24b8d --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0021-Added-relocations-for-MB-X.patch @@ -0,0 +1,69 @@ +From 818a103460da557761aacc0d21b9b087721d2d3e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 11 Sep 2018 17:30:17 +0530 +Subject: [PATCH 21/54] Added relocations for MB-X + +Conflicts: + bfd/bfd-in2.h + gas/config/tc-microblaze.c + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/reloc.c | 26 ++++++++++++++------------ + gas/config/tc-microblaze.c | 11 +++++++++++ + 2 files changed, 25 insertions(+), 12 deletions(-) + +Index: gdb-14.2/bfd/reloc.c +=================================================================== +--- gdb-14.2.orig/bfd/reloc.c ++++ gdb-14.2/bfd/reloc.c +@@ -6703,12 +6703,6 @@ ENUMDOC + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64 +-ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing +@@ -6716,12 +6710,6 @@ ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64_GPC +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset + ENUM +@@ -7976,6 +7964,20 @@ ENUMX + ENUMDOC + Linux eBPF relocations. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_EPIPHANY_SIMM8 + ENUMDOC diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0022-initial-support-for-MicroBlaze-64-bit-m64.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0022-initial-support-for-MicroBlaze-64-bit-m64.patch new file mode 100644 index 00000000..2023287a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0022-initial-support-for-MicroBlaze-64-bit-m64.patch @@ -0,0 +1,113 @@ +From 587d5179ce81a4f67ebec321063f6c3c9b1673cb Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 1 Nov 2021 19:06:53 +0530 +Subject: [PATCH 22/54] initial support for MicroBlaze 64 bit [-m64] + +Conflicts: + bfd/elf32-microblaze.c + include/elf/common.h + ld/Makefile.am + ld/Makefile.in +signed-off-by:Nagaraju Mekala + Mahesh Bodapati + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 8 + + bfd/reloc.c | 42 ++- + gas/config/tc-microblaze.c | 558 ++++++++++++++++++++++++++++++++----- + 3 files changed, 507 insertions(+), 101 deletions(-) + +Index: gdb-14.2/bfd/elf64-microblaze.c +=================================================================== +--- gdb-14.2.orig/bfd/elf64-microblaze.c ++++ gdb-14.2/bfd/elf64-microblaze.c +@@ -1666,6 +1666,14 @@ microblaze_elf_relocate_section (bfd *ou + outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); + outrel.r_addend = relocation + addend; + } ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, ++ contents + offset + endian); ++ } + else + { + BFD_FAIL (); +Index: gdb-14.2/bfd/reloc.c +=================================================================== +--- gdb-14.2.orig/bfd/reloc.c ++++ gdb-14.2/bfd/reloc.c +@@ -6703,13 +6703,31 @@ ENUMDOC + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64 ++ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing + ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64_GPC ++ENUMDOC ++ This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset + ENUM +@@ -7942,18 +7960,6 @@ ENUMDOC + This is a 64 bit reloc that stores 64-bit thread pointer relative offset + to two words (uses imml instruction). + ENUM +-BFD_RELOC_MICROBLAZE_64, +-ENUMDOC +- This is a 64 bit reloc that stores the 64 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, +-ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM + BFD_RELOC_BPF_64 + ENUMX + BFD_RELOC_BPF_DISP32 +@@ -7967,18 +7973,6 @@ ENUMDOC + This is a 64 bit reloc that stores 64-bit thread pointer relative offset + to two words (uses imml instruction). + ENUM +-BFD_RELOC_MICROBLAZE_64, +-ENUMDOC +- This is a 64 bit reloc that stores the 64 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, +-ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM + BFD_RELOC_EPIPHANY_SIMM8 + ENUMDOC + Adapteva EPIPHANY - 8 bit signed pc-relative displacement diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0023-Added-relocations-for-MB-X.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0023-Added-relocations-for-MB-X.patch new file mode 100644 index 00000000..54b0cc45 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0023-Added-relocations-for-MB-X.patch @@ -0,0 +1,84 @@ +From 4992c1383473b2a37551b7391f1eb836d2a447d3 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 11 Sep 2018 17:30:17 +0530 +Subject: [PATCH 23/54] Added relocations for MB-X + +Conflicts: + bfd/bfd-in2.h + gas/config/tc-microblaze.c + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/libbfd.h | 2 -- + bfd/reloc.c | 26 ++++++++------- + gas/config/tc-microblaze.c | 68 ++++++++++++-------------------------- + 3 files changed, 36 insertions(+), 60 deletions(-) + +Index: gdb-14.2/bfd/libbfd.h +=================================================================== +--- gdb-14.2.orig/bfd/libbfd.h ++++ gdb-14.2/bfd/libbfd.h +@@ -3012,9 +3012,7 @@ static const char *const bfd_reloc_code_ + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", +- "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", +- "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", +Index: gdb-14.2/bfd/reloc.c +=================================================================== +--- gdb-14.2.orig/bfd/reloc.c ++++ gdb-14.2/bfd/reloc.c +@@ -6669,6 +6669,20 @@ ENUM + ENUMDOC + Address of a GOT entry. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_MICROBLAZE_32_LO + ENUMDOC +@@ -6707,12 +6721,6 @@ ENUMDOC + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing + ENUM +- BFD_RELOC_MICROBLAZE_64 +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imm instruction). No relocation is +- done here - only used for relaxing +-ENUM + BFD_RELOC_MICROBLAZE_64_PCREL, + ENUMDOC + This is a 32 bit reloc that stores the 32 bit pc relative +@@ -6725,12 +6733,6 @@ ENUMDOC + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing + ENUM +- BFD_RELOC_MICROBLAZE_64_GPC +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imm instruction). The relocation is +- PC-relative GOT offset +-ENUM + BFD_RELOC_MICROBLAZE_64_GOT + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0025-Fixed-address-computation-issues-with-64bit-address-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0025-Fixed-address-computation-issues-with-64bit-address-.patch new file mode 100644 index 00000000..e495e207 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0025-Fixed-address-computation-issues-with-64bit-address-.patch @@ -0,0 +1,35 @@ +From 33e22262c6c43af6e7e075df0665838b5b3859a6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 9 Oct 2018 10:14:22 +0530 +Subject: [PATCH 25/54] - Fixed address computation issues with 64bit address - + Fixed imml dissassamble issue + +Conflicts: + gas/config/tc-microblaze.c + opcodes/microblaze-dis.c + +Conflicts: + bfd/elf64-microblaze.c + +Conflicts: + bfd/elf64-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/elf64-microblaze.c | 2 +- + gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++----- + 2 files changed, 67 insertions(+), 9 deletions(-) + +Index: gdb-14.2/bfd/elf64-microblaze.c +=================================================================== +--- gdb-14.2.orig/bfd/elf64-microblaze.c ++++ gdb-14.2/bfd/elf64-microblaze.c +@@ -2131,7 +2131,7 @@ microblaze_elf_relax_section (bfd *abfd, + efix = calc_fixup (target_address, 0, sec); + + /* Validate the in-band val. */ +- val = bfd_get_32 (abfd, contents + irel->r_offset); ++ val = bfd_get_64 (abfd, contents + irel->r_offset); + if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { + fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); + } diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch new file mode 100644 index 00000000..f6598cee --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0028-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -0,0 +1,26 @@ +From 646b229752b9816b25d2b9ffe79b895b69742745 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 29 Nov 2018 17:59:25 +0530 +Subject: [PATCH 28/54] fixing the long & long long mingw toolchain issue + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 10 +++++----- + opcodes/microblaze-opc.h | 4 ++-- + 2 files changed, 7 insertions(+), 7 deletions(-) + +Index: gdb-14.2/opcodes/microblaze-opc.h +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-opc.h ++++ gdb-14.2/opcodes/microblaze-opc.h +@@ -593,8 +593,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM6_WIDTH ((int) 0x00000001) + #define MAX_IMM6_WIDTH ((int) 0x00000040) + +-#define MIN_IMML ((long) 0xffffff8000000000L) +-#define MAX_IMML ((long) 0x0000007fffffffffL) ++#define MIN_IMML ((long long) 0xffffff8000000000L) ++#define MAX_IMML ((long long) 0x0000007fffffffffL) + + #endif /* MICROBLAZE_OPC */ + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0029-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0029-Added-support-to-new-arithmetic-single-register-inst.patch new file mode 100644 index 00000000..8e9585a0 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0029-Added-support-to-new-arithmetic-single-register-inst.patch @@ -0,0 +1,176 @@ +From 1a9a688939dfbf7cca9685b326c0387672c567b4 Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Fri, 23 Aug 2019 16:18:43 +0530 +Subject: [PATCH 29/54] Added support to new arithmetic single register + instructions + +Conflicts: + opcodes/microblaze-dis.c + +Conflicts: + gas/config/tc-microblaze.c + opcodes/microblaze-dis.c + +Conflicts: + gas/config/tc-microblaze.c +signed-off-by:Nagaraju + Mahesh + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++- + opcodes/microblaze-dis.c | 11 +++ + opcodes/microblaze-opc.h | 43 ++++++++++- + opcodes/microblaze-opcm.h | 5 +- + 4 files changed, 200 insertions(+), 6 deletions(-) + +Index: gdb-14.2/opcodes/microblaze-dis.c +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-dis.c ++++ gdb-14.2/opcodes/microblaze-dis.c +@@ -143,6 +143,14 @@ get_field_imm15 (struct string_buf *buf, + return p; + } + ++get_field_imm16 (struct string_buf *buf, long instr) ++{ ++ char *p = strbuf (buf); ++ ++ sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW)); ++ return p; ++} ++ + static char * + get_field_special (struct string_buf *buf, long instr, + const struct op_code_struct *op) +@@ -473,6 +481,9 @@ print_insn_microblaze (bfd_vma memaddr, + /* For mbar 16 or sleep insn. */ + case INST_TYPE_NONE: + break; ++ case INST_TYPE_RD_IMML: ++ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); ++ break; + /* For bit field insns. */ + case INST_TYPE_RD_R1_IMMW_IMMS: + print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), +Index: gdb-14.2/opcodes/microblaze-opc.h +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-opc.h ++++ gdb-14.2/opcodes/microblaze-opc.h +@@ -78,6 +78,7 @@ + #define INST_TYPE_RD_R1_IMMW_IMMS 21 + + #define INST_TYPE_NONE 25 ++#define INST_TYPE_RD_IMML 26 + + + +@@ -93,6 +94,7 @@ + #define IMMVAL_MASK_MFS 0x0000 + + #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */ ++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */ + #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */ + #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ + #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ +@@ -115,6 +117,33 @@ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ + #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ + ++/*Defines to identify 64-bit single reg instructions */ ++#define ADDLI_ONE_REG_MASK 0x68000000 ++#define ADDLIC_ONE_REG_MASK 0x68020000 ++#define ADDLIK_ONE_REG_MASK 0x68040000 ++#define ADDLIKC_ONE_REG_MASK 0x68060000 ++#define RSUBLI_ONE_REG_MASK 0x68010000 ++#define RSUBLIC_ONE_REG_MASK 0x68030000 ++#define RSUBLIK_ONE_REG_MASK 0x68050000 ++#define RSUBLIKC_ONE_REG_MASK 0x68070000 ++#define ORLI_ONE_REG_MASK 0x68100000 ++#define ANDLI_ONE_REG_MASK 0x68110000 ++#define XORLI_ONE_REG_MASK 0x68120000 ++#define ANDLNI_ONE_REG_MASK 0x68130000 ++#define ADDLI_MASK 0x20000000 ++#define ADDLIC_MASK 0x28000000 ++#define ADDLIK_MASK 0x30000000 ++#define ADDLIKC_MASK 0x38000000 ++#define RSUBLI_MASK 0x24000000 ++#define RSUBLIC_MASK 0x2C000000 ++#define RSUBLIK_MASK 0x34000000 ++#define RSUBLIKC_MASK 0x3C000000 ++#define ANDLI_MASK 0xA4000000 ++#define ANDLNI_MASK 0xAC000000 ++#define ORLI_MASK 0xA0000000 ++#define XORLI_MASK 0xA8000000 ++ ++ + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ + /* Mask for mbar insn. */ +@@ -123,7 +152,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 412 ++#define MAX_OPCODES 424 + + const struct op_code_struct + { +@@ -452,13 +481,21 @@ const struct op_code_struct + {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, + {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, + {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst }, + {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst }, + {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst }, + {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst }, + {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst }, + {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst }, + {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst }, + {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst }, + {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, + {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, + {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, +@@ -509,9 +546,13 @@ const struct op_code_struct + {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, + {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, + {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst }, + {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst }, + {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst }, + {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst }, + {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, + {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, + {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, +Index: gdb-14.2/opcodes/microblaze-opcm.h +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-opcm.h ++++ gdb-14.2/opcodes/microblaze-opcm.h +@@ -62,7 +62,9 @@ enum microblaze_instr + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, + + /* 64-bit instructions */ +- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc, ++ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ andli, andnli, orli, xorli, + bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, + andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, + brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, +@@ -167,5 +169,6 @@ enum microblaze_instr_type + + /* Imm mask for msrset, msrclr instructions. */ + #define IMM15_MASK 0x00007FFF ++#define IMM16_MASK 0x0000FFFF + + #endif /* MICROBLAZE-OPCM */ diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0030-double-imml-generation-for-64-bit-values.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0030-double-imml-generation-for-64-bit-values.patch new file mode 100644 index 00000000..72b9cc9f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0030-double-imml-generation-for-64-bit-values.patch @@ -0,0 +1,29 @@ +From 6967f52fe0ebebb4bdf437cb1e683d9e87a013ff Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 26 Aug 2019 15:29:42 +0530 +Subject: [PATCH 30/54] double imml generation for 64 bit values. + +Conflicts: + gas/config/tc-microblaze.c + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 321 ++++++++++++++++++++++++++++++------- + opcodes/microblaze-opc.h | 4 +- + 2 files changed, 262 insertions(+), 63 deletions(-) + +Index: gdb-14.2/opcodes/microblaze-opc.h +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-opc.h ++++ gdb-14.2/opcodes/microblaze-opc.h +@@ -634,8 +634,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM6_WIDTH ((int) 0x00000001) + #define MAX_IMM6_WIDTH ((int) 0x00000040) + +-#define MIN_IMML ((long long) 0xffffff8000000000L) +-#define MAX_IMML ((long long) 0x0000007fffffffffL) ++#define MIN_IMML ((long long) -9223372036854775808) ++#define MAX_IMML ((long long) 9223372036854775807) + + #endif /* MICROBLAZE_OPC */ + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch new file mode 100644 index 00000000..700ec4c3 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0035-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch @@ -0,0 +1,44 @@ +From 9ff4551a70734606139f3ecd146cf0a1c45e0fb0 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 8 Nov 2021 22:01:23 +0530 +Subject: [PATCH 35/54] ld/emulparams/elf64microblaze: Fix emulation generation + +Compilation fails when building ld-new with: + +ldemul.o:(.data.rel+0x820): undefined reference to `ld_elf64microblazeel_emulation' +ldemul.o:(.data.rel+0x828): undefined reference to `ld_elf64microblaze_emulation' + +The error appears to be that the elf64 files were referencing the elf32 emulation. + +Signed-off-by: Mark Hatle +Signed-off-by: Aayush Misra +--- + ld/emulparams/elf64microblaze.sh | 2 +- + ld/emulparams/elf64microblazeel.sh | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh +index 9c7b0eb7080..7b4c7c411bd 100644 +--- a/ld/emulparams/elf64microblaze.sh ++++ b/ld/emulparams/elf64microblaze.sh +@@ -19,5 +19,5 @@ NOP=0x80000000 + #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} + #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' + +-TEMPLATE_NAME=elf32 ++TEMPLATE_NAME=elf + #GENERATE_SHLIB_SCRIPT=yes +diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh +index 9c7b0eb7080..7b4c7c411bd 100644 +--- a/ld/emulparams/elf64microblazeel.sh ++++ b/ld/emulparams/elf64microblazeel.sh +@@ -19,5 +19,5 @@ NOP=0x80000000 + #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} + #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' + +-TEMPLATE_NAME=elf32 ++TEMPLATE_NAME=elf + #GENERATE_SHLIB_SCRIPT=yes +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch new file mode 100644 index 00000000..88c0dc4e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0036-Invalid-data-offsets-pointer-after-relaxation.-Propo.patch @@ -0,0 +1,79 @@ +From a233cd9a21bc94c47c1d33cc10a9e24a5d5b8126 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 24 Jan 2022 16:04:07 +0530 +Subject: [PATCH 36/54] Invalid data offsets (pointer) after relaxation. + Proposed patch from community member (dednev@rambler.ru) against 2021.1 + [CR-1115232] + +Signed-off-by: Aayush Misra +--- + bfd/elf32-microblaze.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 6ba28e757be..7a4d35493e9 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -2174,6 +2174,9 @@ microblaze_elf_relax_section (bfd *abfd, + { + unsigned int val; + ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* hax: We only do the following fixup for debug location lists. */ +@@ -2213,6 +2216,9 @@ microblaze_elf_relax_section (bfd *abfd, + } + if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2245,6 +2251,9 @@ microblaze_elf_relax_section (bfd *abfd, + } + else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2282,6 +2291,9 @@ microblaze_elf_relax_section (bfd *abfd, + || (ELF32_R_TYPE (irelscan->r_info) + == (int) R_MICROBLAZE_TEXTREL_32_LO)) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2328,6 +2340,9 @@ microblaze_elf_relax_section (bfd *abfd, + || (ELF32_R_TYPE (irelscan->r_info) + == (int) R_MICROBLAZE_TEXTREL_64)) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +@@ -2362,6 +2377,9 @@ microblaze_elf_relax_section (bfd *abfd, + } + else if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) + { ++ if (ELF32_R_SYM (irelscan->r_info) >= symtab_hdr->sh_info) ++ continue; ++ + isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch new file mode 100644 index 00000000..3cae48dc --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0037-Double-free-with-ld-no-keep-memory.-Proposed-patches.patch @@ -0,0 +1,107 @@ +From 2d0e4a0b3a9ce2ffebc5892cf34219ac01a2475e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 24 Jan 2022 16:59:19 +0530 +Subject: [PATCH 37/54] Double free with ld --no-keep-memory. Proposed patches + from the community member (dednev@rambler.ru) for 2021.1. [CR-1115233] + +Conflicts: + bfd/elf32-microblaze.c + bfd/elf64-microblaze.c + +Signed-off-by: Aayush Misra +--- + bfd/elf32-microblaze.c | 40 ++++++++++++++++++++++------------------ + 1 file changed, 22 insertions(+), 18 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 7a4d35493e9..554a80ae0e4 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -1881,10 +1881,8 @@ microblaze_elf_relax_section (bfd *abfd, + { + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *internal_relocs; +- Elf_Internal_Rela *free_relocs = NULL; + Elf_Internal_Rela *irel, *irelend; + bfd_byte *contents = NULL; +- bfd_byte *free_contents = NULL; + int rel_count; + unsigned int shndx; + size_t i, sym_index; +@@ -1928,8 +1926,6 @@ microblaze_elf_relax_section (bfd *abfd, + internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); + if (internal_relocs == NULL) + goto error_return; +- if (! link_info->keep_memory) +- free_relocs = internal_relocs; + + sdata->relax_count = 0; + sdata->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) +@@ -1957,7 +1953,6 @@ microblaze_elf_relax_section (bfd *abfd, + contents = (bfd_byte *) bfd_malloc (sec->size); + if (contents == NULL) + goto error_return; +- free_contents = contents; + + if (!bfd_get_section_contents (abfd, sec, contents, + (file_ptr) 0, sec->size)) +@@ -2473,25 +2468,26 @@ microblaze_elf_relax_section (bfd *abfd, + } + + elf_section_data (sec)->relocs = internal_relocs; +- free_relocs = NULL; + + elf_section_data (sec)->this_hdr.contents = contents; +- free_contents = NULL; + + symtab_hdr->contents = (bfd_byte *) isymbuf; + } + +- free (free_relocs); +- free_relocs = NULL; ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); + +- if (free_contents != NULL) +- { +- if (!link_info->keep_memory) +- free (free_contents); ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ { ++ if (! link_info->keep_memory) ++ free (contents); + else +- /* Cache the section contents for elf_link_input_bfd. */ +- elf_section_data (sec)->this_hdr.contents = contents; +- free_contents = NULL; ++ { ++ /* Cache the section contents for elf_link_input_bfd. */ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } + } + + if (sdata->relax_count == 0) +@@ -2505,8 +2501,16 @@ microblaze_elf_relax_section (bfd *abfd, + return true; + + error_return: +- free (free_relocs); +- free (free_contents); ++ ++ if (isymbuf != NULL ++ && symtab_hdr->contents != (unsigned char *) isymbuf) ++ free (isymbuf); ++ if (internal_relocs != NULL ++ && elf_section_data (sec)->relocs != internal_relocs) ++ free (internal_relocs); ++ if (contents != NULL ++ && elf_section_data (sec)->this_hdr.contents != contents) ++ free (contents); + free (sdata->relax); + sdata->relax = NULL; + sdata->relax_count = 0; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0038-MB-binutils-Upstream-port-issues.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0038-MB-binutils-Upstream-port-issues.patch new file mode 100644 index 00000000..a27a9807 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0038-MB-binutils-Upstream-port-issues.patch @@ -0,0 +1,83 @@ +From 06e678ebb6c136c85f73ba8a4a064f9050ae47ce Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Sun, 28 Nov 2021 17:17:15 +0530 +Subject: [PATCH 38/54] MB binutils Upstream port issues. + +It's resolving the seg faults with ADDLIK +Conflicts: + bfd/elf64-microblaze.c + +Signed-off-by: Aayush Misra +--- + gas/config/tc-microblaze.c | 2 +- + opcodes/microblaze-dis.c | 12 ++++++------ + opcodes/microblaze-opc.h | 2 +- + 3 files changed, 8 insertions(+), 8 deletions(-) + +Index: gdb-14.2/opcodes/microblaze-dis.c +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-dis.c ++++ gdb-14.2/opcodes/microblaze-dis.c +@@ -153,7 +153,7 @@ get_field_imm16 (struct string_buf *buf, + + static char * + get_field_special (struct string_buf *buf, long instr, +- const struct op_code_struct *op) ++ struct op_code_struct *op) + { + char *p = strbuf (buf); + char *spr; +@@ -226,11 +226,11 @@ get_field_special (struct string_buf *bu + static unsigned long + read_insn_microblaze (bfd_vma memaddr, + struct disassemble_info *info, +- const struct op_code_struct **opr) ++ struct op_code_struct **opr) + { + unsigned char ibytes[4]; + int status; +- const struct op_code_struct *op; ++ struct op_code_struct *op; + unsigned long inst; + + status = info->read_memory_func (memaddr, ibytes, 4, info); +@@ -266,7 +266,7 @@ print_insn_microblaze (bfd_vma memaddr, + fprintf_ftype print_func = info->fprintf_func; + void *stream = info->stream; + unsigned long inst, prev_inst; +- const struct op_code_struct *op, *pop; ++ struct op_code_struct *op, *pop; + int immval = 0; + bool immfound = false; + static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */ +@@ -518,7 +518,7 @@ get_insn_microblaze (long inst, + enum microblaze_instr_type *insn_type, + short *delay_slots) + { +- const struct op_code_struct *op; ++ struct op_code_struct *op; + *isunsignedimm = false; + + /* Just a linear search of the table. */ +@@ -560,7 +560,7 @@ microblaze_get_target_address (long inst + bool *targetvalid, + bool *unconditionalbranch) + { +- const struct op_code_struct *op; ++ struct op_code_struct *op; + long targetaddr = 0; + + *unconditionalbranch = false; +Index: gdb-14.2/opcodes/microblaze-opc.h +=================================================================== +--- gdb-14.2.orig/opcodes/microblaze-opc.h ++++ gdb-14.2/opcodes/microblaze-opc.h +@@ -154,7 +154,7 @@ + + #define MAX_OPCODES 424 + +-const struct op_code_struct ++struct op_code_struct + { + const char * name; + short inst_type; /* Registers and immediate values involved. */ diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-port-of-core-reading-support-Added-support-f.patch new file mode 100644 index 00000000..3372de27 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-port-of-core-reading-support-Added-support-f.patch @@ -0,0 +1,89 @@ +From e907440fcfce0828efa7b059ef0c6d61c7736d02 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 10 Oct 2022 16:37:53 +0530 +Subject: [PATCH 39/54] Initial port of core reading support Added support for + reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO + information for rebuilding ".reg" sections of core dumps at run time. + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi +Signed-off-by: Mahesh Bodapati +Signed-off-by: Aayush Misra +--- + gdb/microblaze-linux-tdep.c | 11 +++++++++++ + gdb/microblaze-tdep.c | 37 +++++++++++++++++++++++++++++++++++++ + 2 files changed, 48 insertions(+) + +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 39592a43f7c..20daef2ccd4 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -193,6 +193,17 @@ microblaze_linux_init_abi (struct gdbarch_info info, + set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); + set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); + ++ /* BFD target for core files. */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze"); ++ else ++ set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel"); ++ ++ ++ /* Shared library handling. */ ++ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); ++ set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); ++ + /* Enable TLS support. */ + set_gdbarch_fetch_tls_load_module_address (gdbarch, + svr4_fetch_objfile_link_map); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index d4b9ef837e5..363fee34040 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -957,6 +957,43 @@ make_regs (struct gdbarch *arch) + } + #endif + ++void ++microblaze_supply_gregset (const struct regset *regset, ++ struct regcache *regcache, ++ int regnum, const void *gregs) ++{ ++ const unsigned int *regs = (const unsigned int *)gregs; ++ if (regnum >= 0) ++ regcache->raw_supply (regnum, regs + regnum); ++ ++ if (regnum == -1) { ++ int i; ++ ++ for (i = 0; i < 50; i++) { ++ regcache->raw_supply (i, regs + i); ++ } ++ } ++} ++ ++ ++/* Return the appropriate register set for the core section identified ++ by SECT_NAME and SECT_SIZE. */ ++ ++static void ++microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, ++ iterate_over_regset_sections_cb *cb, ++ void *cb_data, ++ const struct regcache *regcache) ++{ ++ struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ ++ cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); ++ ++ cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); ++} ++ ++ ++ + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch new file mode 100644 index 00000000..3ea09e7e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fix-build-issues-after-Xilinx-2023.2-binutils-merge.patch @@ -0,0 +1,185 @@ +From 73b456c4d8f64ec01b170a49330e6de66716eb1a Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 14 Mar 2024 10:41:33 +0530 +Subject: [PATCH 40/54] Fix build issues after Xilinx 2023.2 binutils merge + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + bfd/bfd-in2.h | 10 ------ + gdb/microblaze-tdep.c | 71 ++++++++++++++-------------------------- + opcodes/microblaze-dis.c | 10 ------ + 3 files changed, 25 insertions(+), 66 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 9dcf233f19f..4b022dbfba1 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -6473,11 +6473,6 @@ done here - only used for relaxing */ + * +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_PCREL, + +-/* This is a 64 bit reloc that stores the 32 bit relative +- * +value in two words (with an imml instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64, +- + /* This is a 64 bit reloc that stores the 32 bit relative + * +value in two words (with an imml instruction). No relocation is + * +done here - only used for relaxing */ +@@ -6503,11 +6498,6 @@ value in two words (with an imml instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GPC, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative +-value in two words (with an imml instruction). The relocation is +-PC-relative GOT offset */ +- BFD_RELOC_MICROBLAZE_64_GPC, +- + /* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + GOT offset */ +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 363fee34040..818306f2197 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -70,6 +70,7 @@ static const char *microblaze_abi_string; + static const char *const microblaze_abi_strings[] = { + "auto", + "m64", ++ NULL + }; + + enum microblaze_abi +@@ -105,7 +106,7 @@ global_microblaze_abi (void) + if (microblaze_abi_strings[i] == microblaze_abi_string) + return (enum microblaze_abi) i; + +-// internal_error (__FILE__, __LINE__, _("unknown ABI string")); ++ internal_error (__FILE__, __LINE__, _("unknown ABI string")); + } + + static void +@@ -894,16 +895,31 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) + } + + static void +-microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) ++microblaze_register_g_packet_guesses (struct gdbarch *gdbarch, enum microblaze_abi abi) + { + +- register_remote_g_packet_guess (gdbarch, +- 4 * MICROBLAZE_NUM_CORE_REGS, +- tdesc_microblaze64); ++ if (abi == MICROBLAZE_ABI_M64) ++ { ++ ++ register_remote_g_packet_guess (gdbarch, ++ 8 * MICROBLAZE_NUM_CORE_REGS, ++ tdesc_microblaze64); ++ ++ register_remote_g_packet_guess (gdbarch, ++ 8 * MICROBLAZE_NUM_REGS, ++ tdesc_microblaze64_with_stack_protect); ++ } ++ else ++ { ++ ++ register_remote_g_packet_guess (gdbarch, ++ 4 * MICROBLAZE_NUM_CORE_REGS, ++ tdesc_microblaze); + +- register_remote_g_packet_guess (gdbarch, +- 4 * MICROBLAZE_NUM_REGS, +- tdesc_microblaze64_with_stack_protect); ++ register_remote_g_packet_guess (gdbarch, ++ 4 * MICROBLAZE_NUM_REGS, ++ tdesc_microblaze_with_stack_protect); ++ } + } + + void +@@ -957,43 +973,6 @@ make_regs (struct gdbarch *arch) + } + #endif + +-void +-microblaze_supply_gregset (const struct regset *regset, +- struct regcache *regcache, +- int regnum, const void *gregs) +-{ +- const unsigned int *regs = (const unsigned int *)gregs; +- if (regnum >= 0) +- regcache->raw_supply (regnum, regs + regnum); +- +- if (regnum == -1) { +- int i; +- +- for (i = 0; i < 50; i++) { +- regcache->raw_supply (i, regs + i); +- } +- } +-} +- +- +-/* Return the appropriate register set for the core section identified +- by SECT_NAME and SECT_SIZE. */ +- +-static void +-microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, +- iterate_over_regset_sections_cb *cb, +- void *cb_data, +- const struct regcache *regcache) +-{ +- struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); +- +- cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); +- +- cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); +-} +- +- +- + static struct gdbarch * + microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + { +@@ -1134,7 +1113,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); + +- //microblaze_register_g_packet_guesses (gdbarch); ++ // microblaze_register_g_packet_guesses (gdbarch, microblaze_abi); + + frame_base_set_default (gdbarch, µblaze_frame_base); + +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 540ddecafd4..00712d5eaf1 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -466,10 +466,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), + get_field_r2 (&buf, inst)); + break; +- case INST_TYPE_IMML: +- print_func (stream, "\t%s", get_field_imml (&buf, inst)); +- /* TODO: Also print symbol */ +- break; + case INST_TYPE_RD_IMM15: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), + get_field_imm15 (&buf, inst)); +@@ -484,12 +480,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_RD_IMML: + print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); + break; +- /* For bit field insns. */ +- case INST_TYPE_RD_R1_IMMW_IMMS: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), +- get_field_immw (&buf, inst), get_field_imms (&buf, inst)); +- break; +- /* For bit field insns. */ + case INST_TYPE_RD_R1_IMMW_IMMS: + print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst)); + break; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0041-disable-truncated-register-warning-gdb-remote.c.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0041-disable-truncated-register-warning-gdb-remote.c.patch new file mode 100644 index 00000000..6f5a5f1e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0041-disable-truncated-register-warning-gdb-remote.c.patch @@ -0,0 +1,26 @@ +From a96aee31c41e4d851531100a0716401c3464f6ef Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 14 Mar 2024 15:44:56 +0530 +Subject: [PATCH 41/54] disable truncated register warning (gdb/remote.c) + +Signed-off-by: Aayush Misra +--- + gdb/remote.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gdb/remote.c b/gdb/remote.c +index ae08c980efc..8055c8f62e6 100644 +--- a/gdb/remote.c ++++ b/gdb/remote.c +@@ -8678,7 +8678,7 @@ remote_target::process_g_packet (struct regcache *regcache) + if (rsa->regs[i].pnum == -1) + continue; + +- if (offset >= sizeof_g_packet) ++ if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet)) + rsa->regs[i].in_g_packet = 0; + else if (offset + reg_size > sizeof_g_packet) + error (_("Truncated register %d in remote 'g' packet"), i); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch new file mode 100644 index 00000000..0b5f27b4 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0042-Fix-unresolved-conflicts-from-binutils_2_42_merge.patch @@ -0,0 +1,42 @@ +From f9ffc37f48bd9213e89c8821cd07fc679e113007 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 10:20:48 +0530 +Subject: [PATCH 42/54] Fix unresolved conflicts from binutils_2_42_merge + +opcodes/microblaze-dis.c + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + opcodes/microblaze-dis.c | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 00712d5eaf1..31dbad46b75 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -478,11 +478,16 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_NONE: + break; + case INST_TYPE_RD_IMML: +- print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); +- break; +- case INST_TYPE_RD_R1_IMMW_IMMS: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst)); +- break; ++ print_func (stream, "\t%s, %s", ++ get_field_rd (&buf, inst), get_field_imm16 (&buf, inst)); ++ break; ++ case INST_TYPE_RD_R1_IMMW_IMMS: ++ print_func (stream, "\t%s, %s, %s, %s", ++ get_field_rd (&buf, inst), ++ get_field_r1(&buf, inst), ++ get_field_immw (&buf, inst), ++ get_field_imms (&buf, inst)); ++ break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (&buf, inst)); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch new file mode 100644 index 00000000..5e1fb44f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0043-microblaze_gdbarch_init-set-microblaze_abi-based-on-.patch @@ -0,0 +1,177 @@ +From 03df31becbc7dc6d35189fec3b4b2c7dfd3a8103 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 10:59:40 +0530 +Subject: [PATCH 43/54] microblaze_gdbarch_init: set microblaze_abi based on + wanted_abi and found_abi + +Earlier found_abi was declared but not set, instead gdbarch_info info +was checked every time. Also, microblaze_abi remained undefined for 32-bit +machines. As a result, gdb would show 64-bit registers when connecting +to 32-bit targets with all register values garbled (r5 ended up in r2). +This defect is fixed. found_abi is set from gdbarch_info, microblaze_abi +is set based on wanted_abi and found_abi. Now upon connecting to a 32-bit +remote target (mb-qemu) registers have the correct 32-bit size. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 73 +++++++++++++++++++------------------------ + 1 file changed, 33 insertions(+), 40 deletions(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 818306f2197..47863819724 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file, + const char *ignored_value) + { + enum microblaze_abi global_abi = global_microblaze_abi (); +- enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ()); ++ enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ()); + const char *actual_abi_str = microblaze_abi_strings[actual_abi]; + + #if 1 +@@ -203,6 +203,13 @@ microblaze_register_name (struct gdbarch *gdbarch, int regnum) + static struct type * + microblaze_register_type (struct gdbarch *gdbarch, int regnum) + { ++ ++ int mb_reg_size = microblaze_abi_regsize(gdbarch); ++ ++ if (gdbarch_debug) ++ gdb_printf (gdb_stdlog, "microblaze_register_type: reg_size = %d\n", ++ mb_reg_size); ++ + if (regnum == MICROBLAZE_SP_REGNUM) + return builtin_type (gdbarch)->builtin_data_ptr; + +@@ -980,34 +987,38 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + enum microblaze_abi microblaze_abi, found_abi, wanted_abi; + const struct target_desc *tdesc = info.target_desc; + ++ /* If there is already a candidate, use it. */ ++ arches = gdbarch_list_lookup_by_info (arches, &info); ++ if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) ++ return arches->gdbarch; ++ + /* What has the user specified from the command line? */ + wanted_abi = global_microblaze_abi (); + if (gdbarch_debug) + gdb_printf (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", + wanted_abi); ++ ++ found_abi = MICROBLAZE_ABI_AUTO; ++ ++ if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ found_abi = MICROBLAZE_ABI_M64; ++ + if (wanted_abi != MICROBLAZE_ABI_AUTO) + microblaze_abi = wanted_abi; +- +- /* If there is already a candidate, use it. */ +- arches = gdbarch_list_lookup_by_info (arches, &info); +- if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) +- return arches->gdbarch; ++ else ++ microblaze_abi = found_abi; + + if (microblaze_abi == MICROBLAZE_ABI_M64) + { +- tdesc = tdesc_microblaze64; +- reg_size = 8; ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; + } +- if (tdesc == NULL) ++ else + { +- if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) +- { +- tdesc = tdesc_microblaze64; +- reg_size = 8; +- } +- else +- tdesc = tdesc_microblaze; ++ tdesc = tdesc_microblaze; ++ reg_size = 4; + } ++ + /* Check any target description for validity. */ + if (tdesc_has_registers (tdesc)) + { +@@ -1015,7 +1026,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) ++ if (microblaze_abi == MICROBLAZE_ABI_M64) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.core"); + else +@@ -1029,7 +1040,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + for (i = 0; i < MICROBLAZE_NUM_REGS; i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data.get(), i, + microblaze_register_names[i]); +- if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) ++ if (microblaze_abi == MICROBLAZE_ABI_M64) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.stack-protect"); + else +@@ -1075,15 +1086,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + + /* Register set. + make_regs (gdbarch); */ +- switch (info.bfd_arch_info->mach) +- { +- case bfd_mach_microblaze64: +- set_gdbarch_ptr_bit (gdbarch, 64); +- break; +- } +- if(microblaze_abi == MICROBLAZE_ABI_M64) ++ if (microblaze_abi == MICROBLAZE_ABI_M64) + set_gdbarch_ptr_bit (gdbarch, 64); +- ++ else ++ set_gdbarch_ptr_bit (gdbarch, 32); ++ + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); + +@@ -1105,8 +1112,6 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::bp_from_kind); + // set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + +-// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); +- + set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + + set_gdbarch_frame_args_skip (gdbarch, 8); +@@ -1145,9 +1150,6 @@ _initialize_microblaze_tdep () + + gdbarch_register (bfd_arch_microblaze, microblaze_gdbarch_init); + +-// static struct cmd_list_element *setmicroblazecmdlist = NULL; +-// static struct cmd_list_element *showmicroblazecmdlist = NULL; +- + /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ + + add_setshow_prefix_cmd ("microblaze", no_class, +@@ -1155,15 +1157,6 @@ _initialize_microblaze_tdep () + _("Various microblaze specific commands."), + &setmicroblazecmdlist,&showmicroblazecmdlist, + &setlist,&showlist); +-#if 0 +- add_prefix_cmd ("microblaze", no_class, set_microblaze_command, +- _("Various microblaze specific commands."), +- &setmicroblazecmdlist, "set microblaze ", 0, &setlist); +- +- add_prefix_cmd ("microblaze", no_class, show_microblaze_command, +- _("Various microblaze specific commands."), +- &showmicroblazecmdlist, "show microblaze ", 0, &showlist); +-#endif + + /* Allow the user to override the ABI. */ + add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings, +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch new file mode 100644 index 00000000..f949a982 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0044-Start-bfd_mach_microblaze-values-from-0-0-1-instead-.patch @@ -0,0 +1,32 @@ +From 254bd83017b21301c73e7501c71b2cf128ac18d9 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 11:36:32 +0530 +Subject: [PATCH 44/54] Start bfd_mach_microblaze values from 0 (0,1) instead + of (1,2) + +Before 64-bit support there was only bfd_mach_microblaze (implicitly set to 0), +setting microblaze_mach_microblaze64 to 1 + +Signed-off-by: Aayush Misra +--- + bfd/archures.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/bfd/archures.c b/bfd/archures.c +index 2994a09bc37..e552349319f 100644 +--- a/bfd/archures.c ++++ b/bfd/archures.c +@@ -515,8 +515,8 @@ DESCRIPTION + . bfd_arch_lm32, {* Lattice Mico32. *} + .#define bfd_mach_lm32 1 + . bfd_arch_microblaze,{* Xilinx MicroBlaze. *} +-.#define bfd_mach_microblaze 1 +-.#define bfd_mach_microblaze64 2 ++.#define bfd_mach_microblaze 0 ++.#define bfd_mach_microblaze64 1 + . bfd_arch_kvx, {* Kalray VLIW core of the MPPA processor family *} + .#define bfd_mach_kv3_unknown 0 + .#define bfd_mach_kv3_1 1 +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch new file mode 100644 index 00000000..6e4137ef --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0045-Fix-build-issues-bfd-reloc.c-add-missing-relocs-used.patch @@ -0,0 +1,61 @@ +From b2377a83918c814fd3b6ee2cd46a5f413f97a08e Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 15:37:11 +0530 +Subject: [PATCH 45/54] Fix build issues - bfd/reloc.c add missing relocs used + elsewhere + + BFD_RELOC_MICROBLAZE_EA64 + BFD_RELOC_MICROBLAZE_64_GPC + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + bfd/reloc.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/bfd/reloc.c b/bfd/reloc.c +index fc28e27662f..5afe1518cd0 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6672,13 +6672,19 @@ ENUMDOC + This is a 64 bit reloc that stores 64-bit thread pointer relative offset + to two words (uses imml instruction). + ENUM +-BFD_RELOC_MICROBLAZE_64, ++BFD_RELOC_MICROBLAZE_64 + ENUMDOC + This is a 64 bit reloc that stores the 64 bit pc relative + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing + ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, ++BFD_RELOC_MICROBLAZE_EA64 ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL + ENUMDOC + This is a 32 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). No relocation is +@@ -6721,13 +6727,13 @@ ENUMDOC + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing + ENUM +-BFD_RELOC_MICROBLAZE_64_PCREL, ++BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative ++ This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). No relocation is + done here - only used for relaxing + ENUM +- BFD_RELOC_MICROBLAZE_64_GOTPC ++ BFD_RELOC_MICROBLAZE_64_GPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imml instruction). No relocation is +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch new file mode 100644 index 00000000..e9383c6f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0046-Regenerate-bfd-bfd-in2.h-bfd-libbfd.h.patch @@ -0,0 +1,125 @@ +From 4d201d0a948ab6160f449d41a50a6794dd3efde7 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 15:47:56 +0530 +Subject: [PATCH 46/54] Regenerate - bfd/bfd-in2.h bfd/libbfd.h + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + bfd/bfd-in2.h | 65 +++++++++++++++++++++++++++++---------------------- + 1 file changed, 37 insertions(+), 28 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 4b022dbfba1..171de10910c 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -1771,8 +1771,8 @@ enum bfd_architecture + bfd_arch_lm32, /* Lattice Mico32. */ + #define bfd_mach_lm32 1 + bfd_arch_microblaze,/* Xilinx MicroBlaze. */ +-#define bfd_mach_microblaze 1 +-#define bfd_mach_microblaze64 2 ++#define bfd_mach_microblaze 0 ++#define bfd_mach_microblaze64 1 + bfd_arch_kvx, /* Kalray VLIW core of the MPPA processor family */ + #define bfd_mach_kv3_unknown 0 + #define bfd_mach_kv3_1 1 +@@ -6440,9 +6440,27 @@ the linker could optimize the movq to a leaq if possible. */ + /* Relative offset within page of GOT slot. */ + BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12, + +-/* Address of a GOT entry. */ ++/* Address of a GOT entry. ++ ++This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++to two words (uses imml instruction). */ + BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT, + ++/* This is a 64 bit reloc that stores the 64 bit pc relative ++value in two words (with an imml instruction). No relocation is ++done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ ++/* This is a 64 bit reloc that stores the 64 bit pc relative ++value in two words (with an imml instruction). No relocation is ++done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_EA64, ++ ++/* This is a 32 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). No relocation is ++done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_PCREL, ++ + /* This is a 32 bit reloc for the microblaze that stores the + low 16 bits of a value */ + BFD_RELOC_MICROBLAZE_32_LO, +@@ -6468,34 +6486,19 @@ value in two words (with an imm instruction). No relocation is + done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_32_NONE, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative +- * +value in two words (with an imml instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_PCREL, +- +-/* This is a 64 bit reloc that stores the 32 bit relative +- * +value in two words (with an imml instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_EA64, +- +-/* This is a 64 bit reloc that stores the 32 bit pc relative +- * +value in two words (with an imm instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_NONE, +- +-/* This is a 64 bit reloc that stores the 32 bit pc relative +- * +value in two words (with an imml instruction). No relocation is +- * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64, ++/* This is a 32 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). No relocation is ++done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative +-value in two words (with an imm instruction). The relocation is +-PC-relative GOT offset */ ++value in two words (with an imml instruction). No relocation is ++done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + + /* This is a 64 bit reloc that stores the 32 bit pc relative +-value in two words (with an imml instruction). The relocation is +-PC-relative GOT offset */ ++value in two words (with an imml instruction). No relocation is ++done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_GPC, + + /* This is a 64 bit reloc that stores the 32 bit pc relative +@@ -7199,7 +7202,10 @@ assembler and not (currently) written to any object files. */ + BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA, + BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA, + +-/* Tilera TILE-Gx Relocations. */ ++/* Tilera TILE-Gx Relocations. ++ ++This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++to two words (uses imml instruction). */ + BFD_RELOC_TILEGX_HW0, + BFD_RELOC_TILEGX_HW1, + BFD_RELOC_TILEGX_HW2, +@@ -7310,7 +7316,10 @@ assembler and not (currently) written to any object files. */ + BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD, + BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD, + +-/* Linux eBPF relocations. */ ++/* Linux eBPF relocations. ++ ++This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++to two words (uses imml instruction). */ + BFD_RELOC_BPF_64, + BFD_RELOC_BPF_DISP32, + BFD_RELOC_BPF_DISPCALL32, +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch new file mode 100644 index 00000000..d31eb8ee --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0047-gdb-remote.c-revert-earlier-change-to-process_g_pack.patch @@ -0,0 +1,32 @@ +From 2a1036ac7639aa3b67b1f1ad7e1a6e7c4c22704b Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 28 Mar 2024 16:32:22 +0530 +Subject: [PATCH 47/54] gdb/remote.c - revert earlier change to + process_g_packet + +When connecting to remote target, gdb (microblaze-xilinx-elf) was +generating Truncated register 29 error when parsing the g packet, +workaround added being reverted. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/remote.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gdb/remote.c b/gdb/remote.c +index 8055c8f62e6..ae08c980efc 100644 +--- a/gdb/remote.c ++++ b/gdb/remote.c +@@ -8678,7 +8678,7 @@ remote_target::process_g_packet (struct regcache *regcache) + if (rsa->regs[i].pnum == -1) + continue; + +- if (offset >= sizeof_g_packet || (offset + reg_size > sizeof_g_packet)) ++ if (offset >= sizeof_g_packet) + rsa->regs[i].in_g_packet = 0; + else if (offset + reg_size > sizeof_g_packet) + error (_("Truncated register %d in remote 'g' packet"), i); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch new file mode 100644 index 00000000..f9cbb4a6 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0048-Fix-build-issues-after-Xilinx-2023.2-binutils-patch-.patch @@ -0,0 +1,46 @@ +From 6a5887919f00da84c973ec61c59efcd7d0fb120e Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Mon, 1 Apr 2024 16:21:28 +0530 +Subject: [PATCH 48/54] Fix build issues after Xilinx 2023.2 binutils patch + merge + +binutils/readelf.c - duplicate case statement +gas/config/tc-microblaze.c - Missing , between array elements +gas/config/tc-microblaze.c - A whole hunk ended up in wrong function/switch + +Signed-off-by: Aayush Misra +--- + bfd/libbfd.h | 6 +- + binutils/readelf.c | 5 - + gas/config/tc-microblaze.c | 375 +++++++++++++++++++------------------ + 3 files changed, 192 insertions(+), 194 deletions(-) + +Index: gdb-14.2/bfd/libbfd.h +=================================================================== +--- gdb-14.2.orig/bfd/libbfd.h ++++ gdb-14.2/bfd/libbfd.h +@@ -3005,6 +3005,9 @@ static const char *const bfd_reloc_code_ + "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21", + "BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12", + "BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT", ++ "BFD_RELOC_MICROBLAZE_64", ++ "BFD_RELOC_MICROBLAZE_EA64", ++ "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_32_LO", + "BFD_RELOC_MICROBLAZE_32_LO_PCREL", + "BFD_RELOC_MICROBLAZE_32_ROSDA", +@@ -3013,13 +3016,12 @@ static const char *const bfd_reloc_code_ + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", + "BFD_RELOC_MICROBLAZE_64_GOTPC", ++ "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", + "BFD_RELOC_MICROBLAZE_32_GOTOFF", + "BFD_RELOC_MICROBLAZE_COPY", +- "BFD_RELOC_MICROBLAZE_64", +- "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_64_TLS", + "BFD_RELOC_MICROBLAZE_64_TLSGD", + "BFD_RELOC_MICROBLAZE_64_TLSLD", diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch new file mode 100644 index 00000000..76fcef7d --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0049-Add-back-R_MICROBLAZE_NONE-for-linker-relaxation-pro.patch @@ -0,0 +1,27 @@ +From bf491bdb2e4d30c14968be096969da700dedfc64 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Wed, 17 Apr 2024 16:14:14 +0530 +Subject: [PATCH 49/54] Add back R_MICROBLAZE_NONE for linker relaxation + processing + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + bfd/elf32-microblaze.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 554a80ae0e4..ec6613b6572 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -2102,6 +2102,7 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend); + } + break; ++ case R_MICROBLAZE_NONE: + case R_MICROBLAZE_32_NONE: + { + /* This was a PC-relative instruction that was +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0050-When-unwinding-pc-value-adjust-return-pc-value.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0050-When-unwinding-pc-value-adjust-return-pc-value.patch new file mode 100644 index 00000000..c9da78c3 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0050-When-unwinding-pc-value-adjust-return-pc-value.patch @@ -0,0 +1,92 @@ +From d8b25fd6d8cac000bb8f5ad65ada949447322fca Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Wed, 1 May 2024 11:12:32 +0530 +Subject: [PATCH 50/54] When unwinding pc value, adjust return pc value + +A call (branch and link) instruction can include a delay slot, the +value of pc stored in the link register for Microblaze architecture +is the pc value corresponding to last executed instruction (call) +in the caller. The return instruction (branch reg) includes an +offset of 8 so that when function returns execution continues from +the address at : link register + 8, as the instruction in delay slot +(link register + 4) is already executed at the time of call. + +Handle this by adjusting pc value during unwind-pc. + +Basically restoring code to do this that seems to have been removed +as part of a gdb patch (gdb patch #8, Xilinx Yocto 2023.2) + +That patch caused hundreds of regressions in gdb testuite, including +gdb.base/advance.exp, which is now fixed. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 24 ++++++++++++++++++------ + 1 file changed, 18 insertions(+), 6 deletions(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 47863819724..f87e406ada0 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -523,6 +523,12 @@ microblaze_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) + { + CORE_ADDR pc; + pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM); ++ /* For sentinel frame, return address is actual PC. For other frames, ++ return address is pc+8. This is a workaround because gcc does not ++ generate correct return address in CIE. */ ++ if (frame_relative_level (next_frame) >= 0) ++ pc = pc + 8; ++ microblaze_debug ("unwind pc = 0x%x\n", (int) pc); + return pc; + } + +@@ -615,6 +621,7 @@ microblaze_frame_prev_register (frame_info_ptr this_frame, + struct microblaze_frame_cache *cache = + microblaze_frame_cache (this_frame, this_cache); + ++#if 1 + if ((regnum == MICROBLAZE_SP_REGNUM && + cache->register_offsets[MICROBLAZE_SP_REGNUM]) + || (regnum == MICROBLAZE_FP_REGNUM && +@@ -625,15 +632,22 @@ if ((regnum == MICROBLAZE_SP_REGNUM && + + if (regnum == MICROBLAZE_PC_REGNUM) + { +- regnum = 15; ++ regnum = MICROBLAZE_PREV_PC_REGNUM; ++ ++ microblaze_debug ("prev pc is r15 @ frame offset 0x%x\n", ++ (int) cache->register_offsets[regnum] ); ++ + return frame_unwind_got_memory (this_frame, regnum, + cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]); +- + } ++ + if (regnum == MICROBLAZE_SP_REGNUM) + regnum = 1; +-#if 0 + ++ return trad_frame_get_prev_register (this_frame, cache->saved_regs, ++ regnum); ++ ++#else + if (cache->frameless_p) + { + if (regnum == MICROBLAZE_PC_REGNUM) +@@ -646,9 +660,7 @@ if (regnum == MICROBLAZE_SP_REGNUM) + else + return trad_frame_get_prev_register (this_frame, cache->saved_regs, + regnum); +-#endif +- return trad_frame_get_prev_register (this_frame, cache->saved_regs, +- regnum); ++#endif + } + + static const struct frame_unwind microblaze_frame_unwind = +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0051-info-reg-pc-does-not-print-symbolic-value.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0051-info-reg-pc-does-not-print-symbolic-value.patch new file mode 100644 index 00000000..887ee56e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0051-info-reg-pc-does-not-print-symbolic-value.patch @@ -0,0 +1,116 @@ +From 66c0cc9a030667111d4b632314502e868e5e8e37 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 9 May 2024 11:30:22 +0530 +Subject: [PATCH 51/54] info reg pc does not print symbolic value + +Problem - Test gdb.base/pc-fp.exp fails +Fix - Change feature/microblaze-core.xml add type=code_ptr for pc + +Files changed + features/microblaze-core.xml + features/microblaze.c (generated) + features/microblaze-with-stack-protect.c (generated) + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/features/microblaze-core.xml | 4 ++-- + gdb/features/microblaze-with-stack-protect.c | 10 ++++++---- + gdb/features/microblaze.c | 8 ++++---- + 3 files changed, 12 insertions(+), 10 deletions(-) + +diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml +index ac052365773..205cdf94a27 100644 +--- a/gdb/features/microblaze-core.xml ++++ b/gdb/features/microblaze-core.xml +@@ -8,7 +8,7 @@ + + + +- ++ + + + +@@ -39,7 +39,7 @@ + + + +- ++ + + + +diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c +index 8ab9565a047..95e3eed1a4e 100644 +--- a/gdb/features/microblaze-with-stack-protect.c ++++ b/gdb/features/microblaze-with-stack-protect.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -70,10 +70,12 @@ initialize_tdesc_microblaze_with_stack_protect (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); +- +- feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect"); + tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); + ++ feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.stack-protect"); ++ tdesc_create_reg (feature, "slr", 59, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "shr", 60, 1, NULL, 32, "int"); ++ + tdesc_microblaze_with_stack_protect = result.release (); + } +diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c +index ed12e5bcfd2..ff4865b2acc 100644 +--- a/gdb/features/microblaze.c ++++ b/gdb/features/microblaze.c +@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void) + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.microblaze.core"); + tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr"); + tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); +@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr"); + tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); +@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void) + tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); +- tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); +- tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int"); + + tdesc_microblaze = result.release (); + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0052-Wrong-target-description-accepted-by-microblaze-arch.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0052-Wrong-target-description-accepted-by-microblaze-arch.patch new file mode 100644 index 00000000..89318eec --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0052-Wrong-target-description-accepted-by-microblaze-arch.patch @@ -0,0 +1,51 @@ +From 0982e0c2733aa773d88876e68320b072e5b2a9ad Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 9 May 2024 11:34:04 +0530 +Subject: [PATCH 52/54] Wrong target description accepted by microblaze + architecture + +Fix - Modify microblaze_gdbarch_init, set tdesc only when it is NULL + +Files changed - gdb/microblaze-tdep.c + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index f87e406ada0..4d8c76bcf4c 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -1020,15 +1020,18 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + else + microblaze_abi = found_abi; + +- if (microblaze_abi == MICROBLAZE_ABI_M64) +- { +- tdesc = tdesc_microblaze64; +- reg_size = 8; +- } +- else +- { +- tdesc = tdesc_microblaze; +- reg_size = 4; ++ if (tdesc == NULL) ++ { ++ if (microblaze_abi == MICROBLAZE_ABI_M64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } ++ else ++ { ++ tdesc = tdesc_microblaze; ++ reg_size = 4; ++ } + } + + /* Check any target description for validity. */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch new file mode 100644 index 00000000..2cb3ff06 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch @@ -0,0 +1,42 @@ +From 31b8744afcb31825083a23bbc08b6e00772ebd07 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Thu, 23 May 2024 16:02:59 +0530 +Subject: [PATCH 53/54] Merge gdb/microblaze-linux-tdep.c to gdb-14 and fix + compilation issues. + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-linux-tdep.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 20daef2ccd4..16d3a0b5196 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -48,10 +48,12 @@ microblaze_debug (const char *fmt, ...) + if (microblaze_debug_flag) + { + va_list args; ++ string_file file (gdb_stdout->can_emit_style_escape ()); + + va_start (args, fmt); + printf_unfiltered ("MICROBLAZE LINUX: "); +- vprintf_unfiltered (fmt, args); ++ file.vprintf (fmt, args); ++ gdb_stdout->puts_unfiltered (file.string ().c_str ()); + va_end (args); + } + } +@@ -145,7 +147,7 @@ static void + microblaze_linux_init_abi (struct gdbarch_info info, + struct gdbarch *gdbarch) + { +- struct microblaze_gdbarch_tdep *tdep =(microblaze_gdbarch_tdep *) gdbarch_tdep (gdbarch); ++ struct microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + tdep->sizeof_gregset = 200; + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch new file mode 100644 index 00000000..eb6bde20 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch @@ -0,0 +1,29 @@ +From 8a7a8b724a87c532096004f43b987c352474a905 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Fri, 19 Jul 2024 12:39:24 +0530 +Subject: [PATCH 54/54] Roll back an improvement which inlines target_gdbarch + () inherited from binutils 2.42 merge that causes compilation issues on gdb + 14.2 + +Signed-off-by: Gopi Kumar Bulusu +Signed-off-by: Aayush Misra +--- + gdb/microblaze-tdep.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 4d8c76bcf4c..cb6697654b0 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -116,7 +116,7 @@ show_microblaze_abi (struct ui_file *file, + const char *ignored_value) + { + enum microblaze_abi global_abi = global_microblaze_abi (); +- enum microblaze_abi actual_abi = microblaze_abi (current_inferior ()->arch ()); ++ enum microblaze_abi actual_abi = microblaze_abi ( target_gdbarch () ); + const char *actual_abi_str = microblaze_abi_strings[actual_abi]; + + #if 1 +-- +2.34.1 + -- cgit v1.2.3-54-g00ecf From fe74892eda4264c1c1839144460a0c41ee88aafe Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 23 Jul 2024 16:56:25 -0600 Subject: meta-microblaze: gdb: Fix target GDB compilation for Linux native Add patch for Linux native issue Add library linkage to libatomic to address: ld: /usr/include/c++/13.3.0/bits/atomic_base.h:1015:(.text+0x16d0c): undefined reference to `__atomic_compare_exchange_1' Also remove extra files no longer required. Signed-off-by: Mark Hatle --- .../recipes-devtools/gdb/gdb-cross-canadian.inc | 44 ---------------------- meta-microblaze/recipes-devtools/gdb/gdb-cross.inc | 31 --------------- .../recipes-devtools/gdb/gdb-microblaze.inc | 3 ++ .../gdb/gdb/0055-fix-microblaze-linux-nat.patch | 26 +++++++++++++ 4 files changed, 29 insertions(+), 75 deletions(-) delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian.inc delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb-cross.inc create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0055-fix-microblaze-linux-nat.patch (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian.inc b/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian.inc deleted file mode 100644 index c463574b..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb-cross-canadian.inc +++ /dev/null @@ -1,44 +0,0 @@ -inherit cross-canadian -inherit python3-dir -inherit pkgconfig - -SUMMARY = "GNU debugger (cross-canadian gdb for ${TARGET_ARCH} target)" -PN = "gdb-cross-canadian-${TRANSLATED_TARGET_ARCH}" -BPN = "gdb" - -DEPENDS = "nativesdk-ncurses nativesdk-expat nativesdk-gettext nativesdk-gmp \ - virtual/${HOST_PREFIX}gcc virtual/${HOST_PREFIX}binutils virtual/nativesdk-libc" - -GDBPROPREFIX = "--program-prefix='${TARGET_PREFIX}'" - -# Overrides PACKAGECONFIG variables in gdb-common.inc -PACKAGECONFIG ??= "readline ${@bb.utils.filter('DISTRO_FEATURES', 'debuginfod', d)}" -PACKAGECONFIG[python] = "--with-python=${WORKDIR}/python,--without-python,nativesdk-python3, \ - nativesdk-python3-core \ - nativesdk-python3-codecs nativesdk-python3-netclient \ - " -PACKAGECONFIG[readline] = "--with-system-readline,--without-system-readline,nativesdk-readline" -PACKAGECONFIG[debuginfod] = "--with-debuginfod, --without-debuginfod, nativesdk-elfutils" - -SSTATE_ALLOW_OVERLAP_FILES += "${STAGING_DATADIR}/gdb" - -do_configure:prepend() { -cat > ${WORKDIR}/python << EOF -#! /bin/sh -case "\$2" in - --includes) echo "-I${STAGING_INCDIR}/${PYTHON_DIR}${PYTHON_ABI}/" ;; - --ldflags) echo "-Wl,-rpath-link,${STAGING_LIBDIR}/.. -Wl,-rpath,${libdir}/.. -lpthread -ldl -lutil -lm -lpython${PYTHON_BASEVERSION}${PYTHON_ABI}" ;; - --exec-prefix) echo "${exec_prefix}" ;; - *) exit 1 ;; -esac -exit 0 -EOF - chmod +x ${WORKDIR}/python -} - -# we don't want gdb to provide bfd/iberty/opcodes, which instead will override the -# right bits installed by binutils. -do_install:append() { - rm -rf ${D}${exec_prefix}/lib - cross_canadian_bindirlinks -} diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-cross.inc b/meta-microblaze/recipes-devtools/gdb/gdb-cross.inc deleted file mode 100644 index b418f3a3..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb-cross.inc +++ /dev/null @@ -1,31 +0,0 @@ -require gdb-common.inc - -DEPENDS = "expat-native gmp-native ncurses-native flex-native bison-native" - -inherit python3native pkgconfig - -# Overrides PACKAGECONFIG variables in gdb-common.inc -PACKAGECONFIG ??= "readline ${@bb.utils.filter('DISTRO_FEATURES', 'debuginfod', d)}" -PACKAGECONFIG[python] = "--with-python=${PYTHON},--without-python,python3-native" -PACKAGECONFIG[readline] = "--with-system-readline,--without-system-readline,readline-native" -PACKAGECONFIG[debuginfod] = "--with-debuginfod, --without-debuginfod, elfutils-native" - -do_compile:prepend() { - export STAGING_LIBDIR="${STAGING_LIBDIR_NATIVE}" - export STAGING_INCDIR="${STAGING_INCDIR_NATIVE}" -} - -#EXTRA_OEMAKE += "LDFLAGS='${BUILD_LDFLAGS}'" - -GDBPROPREFIX = "" - -PN = "gdb-cross-${TARGET_ARCH}" -BPN = "gdb" - -# Ignore how TARGET_ARCH is computed. -TARGET_ARCH[vardepvalue] = "${TARGET_ARCH}" - -inherit cross -inherit gettext - -datadir .= "/gdb-${TARGET_SYS}${TARGET_VENDOR}-${TARGET_OS}" diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc index 151e7c25..4e8993c4 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc +++ b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc @@ -7,6 +7,8 @@ FILESEXTRAPATHS:append := ":${THISDIR}/gdb" # Our changes are all local, no real patch-status ERROR_QA:remove = "patch-status" +LDFLAGS:append:class-target:microblaze = " -latomic" + SRC_URI:append:microblaze = " \ file://0001-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \ file://0002-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \ @@ -51,4 +53,5 @@ SRC_URI:append:microblaze = " \ file://0052-Wrong-target-description-accepted-by-microblaze-arch.patch \ file://0053-Merge-gdb-microblaze-linux-tdep.c-to-gdb-14-and-fix-.patch \ file://0054-Roll-back-an-improvement-which-inlines-target_gdbarc.patch \ + file://0055-fix-microblaze-linux-nat.patch \ " diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0055-fix-microblaze-linux-nat.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0055-fix-microblaze-linux-nat.patch new file mode 100644 index 00000000..a0ac4d39 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0055-fix-microblaze-linux-nat.patch @@ -0,0 +1,26 @@ +Fix compilation error on Linux native GDB + +Signed-off-by: Mark Hatle + +Index: gdb-14.2/gdb/microblaze-linux-nat.c +=================================================================== +--- gdb-14.2.orig/gdb/microblaze-linux-nat.c ++++ gdb-14.2/gdb/microblaze-linux-nat.c +@@ -96,7 +96,7 @@ static int + microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) + { + int u_addr = -1; +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace + * interface, and not the wordsize of the program's ABI. */ + int wordsize = sizeof (long); +@@ -191,7 +192,7 @@ static void + fetch_register (struct regcache *regcache, int tid, int regno) + { + struct gdbarch *gdbarch = regcache->arch (); +- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ microblaze_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + /* This isn't really an address. But ptrace thinks of it as one. */ + CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); + int bytes_transferred; -- cgit v1.2.3-54-g00ecf From 2767482fc80d5178ff4a5c298834855e4b186ac7 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 24 Jul 2024 07:47:31 -0600 Subject: Revert "meta-microblaze: gcc-12.2 fix CVE_STATUS" This reverts commit 93d2836d4d0f7732e51b96250a1bfe2b2f058202. Signed-off-by: Mark Hatle --- meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc b/meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc index 82867489..0dbbecad 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc @@ -111,4 +111,4 @@ EXTRA_OECONF_PATHS = "\ " # Is a binutils 2.26 issue, not gcc -CVE_STATUS[CVE-2021-37322] = "cpe-incorrect: Is a binutils 2.26 issue, not gcc" +CVE_CHECK_IGNORE += "CVE-2021-37322" -- cgit v1.2.3-54-g00ecf From a5ef63d835bc8c12cf7e5a1a82ee547542295738 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 24 Jul 2024 07:50:57 -0600 Subject: Revert "meta-microblaze: Import last version of gcc 12.2" This reverts commit 80dc01609f4cf24329cd71adac4dacd2882f82dc. This effectively reverts back to 2024.1 state, GCC won't work but gives us a clean starting point. Signed-off-by: Mark Hatle --- meta-microblaze/conf/layer.conf | 7 - meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc | 114 ----- ...CAL-Testsuite-builtins-tests-require-fpic.patch | 2 - ...0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch | 2 - ...ejagnu-static-testing-on-qemu-suppress-wa.patch | 2 - ...uite-Add-MicroBlaze-to-target-supports-fo.patch | 2 - ...-testsuite-Update-MicroBlaze-strings-test.patch | 2 - ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch | 2 - ...uite-Add-MicroBlaze-to-check_profiling_av.patch | 2 - ...-Patch-microblaze-Fix-atomic-side-effects.patch | 2 - ...icroblaze-Fix-atomic-boolean-return-value.patch | 2 - ...blaze-Fix-the-Microblaze-crash-with-msmal.patch | 2 - ...ch-microblaze-Added-ashrsi3_with_size_opt.patch | 2 - ...-microblaze-Use-bralid-for-profiler-calls.patch | 2 - ...-Patch-microblaze-Removed-moddi3-routinue.patch | 2 - ...icroblaze-Add-INIT_PRIORITY-support-Added.patch | 4 - ...15-Patch-microblaze-Add-optimized-lshrsi3.patch | 2 - .../0016-Patch-microblaze-Add-cbranchsi4_reg.patch | 2 - ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch | 2 - ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch | 2 - ...-microblaze-Update-ashlsi3-movsf-patterns.patch | 4 - ...icroblaze-8-stage-pipeline-for-microblaze.patch | 4 - ...-Patch-microblaze-Correct-the-const-high-.patch | 4 - ...aze-Fix-internal-compiler-error-with-msma.patch | 4 - ...blaze-Fix-the-calculation-of-high-word-in.patch | 4 - ...roBlaze-this-patch-has-1.Fixed-the-bug-in.patch | 4 - ...5-Fixing-the-issue-with-the-builtin_alloc.patch | 4 - ...blaze-Removed-fsqrt-generation-for-double.patch | 4 - ...oBlaze-Intial-commit-of-64-bit-Microblaze.patch | 4 - .../0028-Intial-commit-for-64bit-MB-sources.patch | 4 - ...Blaze-re-arrangement-of-the-compare-branc.patch | 4 - ...blaze-previous-commit-broke-the-handling-.patch | 4 - ...-Microblaze-Support-of-multilibs-with-m64.patch | 4 - .../0032-Patch-MicroBlaze-Fixed-issues-like.patch | 4 - .../gcc/gcc-12/0033-Patch-MicroBlaze.patch | 4 - .../0034-Added-double-arith-instructions.patch | 4 - ...ssue-in-the-delay-slot-with-swap-instruct.patch | 4 - ...oad-store-issue-with-the-32bit-arith-libr.patch | 4 - ...ing-the-Dwarf-support-to-64bit-Microblaze.patch | 4 - ...38-fixing-the-typo-errors-in-umodsi3-file.patch | 4 - ...xing-the-32bit-LTO-related-issue9-1014024.patch | 4 - ...issing-stack-adjustment-in-prologue-of-mo.patch | 4 - ...blaze-corrected-SPN-for-dlong-instruction.patch | 4 - ...-the-long-long-long-mingw-toolchain-issue.patch | 4 - ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch | 4 - ...blaze-We-will-check-the-possibility-of-pe.patch | 4 - ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch | 4 - ...blaze-MB-64-removal-of-barrel-shift-instr.patch | 4 - ...B-64-single-register-arithmetic-instructi.patch | 4 - ...Blaze-Added-support-for-64-bit-Immediate-.patch | 4 - ...blaze-Fix-Compiler-crash-with-freg-struct.patch | 4 - ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch | 2 - ...oblaze-Reducing-Stack-space-for-arguments.patch | 4 - .../gcc/gcc-12/0052-Patch-MicroBlaze.patch | 4 - ...croblaze64-Add-Zero_extended-instructions.patch | 2 - .../gcc/gcc-12/microblaze-mulitlib-hack.patch | 2 +- .../recipes-devtools/gcc/gcc-common.inc | 118 ----- .../recipes-devtools/gcc/gcc-configure-common.inc | 123 ----- .../recipes-devtools/gcc/gcc-cross-canadian.inc | 187 -------- .../gcc/gcc-cross-canadian_12.2.bb | 5 - .../gcc/gcc-cross-canadian_13.%.bbappend | 1 - meta-microblaze/recipes-devtools/gcc/gcc-cross.inc | 163 ------- .../recipes-devtools/gcc/gcc-cross_12.2.bb | 3 - .../recipes-devtools/gcc/gcc-cross_13.%.bbappend | 1 - .../recipes-devtools/gcc/gcc-crosssdk.inc | 12 - .../recipes-devtools/gcc/gcc-crosssdk_12.2.bb | 2 - .../gcc/gcc-crosssdk_13.%.bbappend | 1 - .../recipes-devtools/gcc/gcc-multilib-config.inc | 249 ---------- .../recipes-devtools/gcc/gcc-runtime.inc | 310 ------------- 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| 39 -- ...4-pass-fix-v4bx-to-linker-to-support-EABI.patch | 40 -- ...tilib-config-files-from-B-instead-of-usin.patch | 99 ---- ...-libdir-from-.la-which-usually-points-to-.patch | 28 -- .../0011-aarch64-Fix-include-paths-when-S-B.patch | 55 --- ...-libdir-from-.la-which-usually-points-to-.patch | 28 -- ...Ensure-target-gcc-headers-can-be-included.patch | 113 ----- ...h-host-directory-during-relink-if-inst_pr.patch | 35 -- ...ibcc1-fix-libcc1-s-install-path-and-rpath.patch | 51 --- ...-handle-sysroot-support-for-nativesdk-gcc.patch | 510 --------------------- ...et-sysroot-gcc-version-specific-dirs-with.patch | 99 ---- ...shared-to-link-commandline-for-musl-targe.patch | 84 ---- ...0019-Re-introduce-spe-commandline-options.patch | 39 -- ...e-alias-for-__cpu_indicator_init-instead-.patch | 83 ---- ...nmodes-Do-not-use-__LINE__-for-maintainin.patch | 182 -------- ...libatomic-Do-not-enforce-march-on-aarch64.patch | 42 -- .../gcc/0023-Fix-install-path-of-linux64.h.patch | 31 -- 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meta-microblaze/recipes-devtools/gcc/gcc/0024-Avoid-hardcoded-build-paths-into-ppc-libgcc.patch delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc/0024-Fix-install-path-of-linux64.h.patch delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc/0026-rust-recursion-limit.patch delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc/hardcoded-paths.patch delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc/prefix-map-realpath.patch delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc_12.2.bb delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc_13.%.bbappend delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgcc-common.inc delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgcc-initial.inc delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgcc-initial_12.2.bb delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgcc-initial_13.%.bbappend delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgcc.inc delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgcc_12.2.bb delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgcc_13.%.bbappend delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgfortran.inc delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgfortran_12.2.bb delete mode 100644 meta-microblaze/recipes-devtools/gcc/libgfortran_13.%.bbappend delete mode 100644 meta-microblaze/recipes-devtools/gcc/microblaze-block.inc (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/conf/layer.conf b/meta-microblaze/conf/layer.conf index dbb83aed..ea8a1e4b 100644 --- a/meta-microblaze/conf/layer.conf +++ b/meta-microblaze/conf/layer.conf @@ -20,13 +20,6 @@ OLDEST_KERNEL:microblaze = "3.15" INHERIT += "rust_microblaze" -# We want to use gcc 12.x for the microblaze stuff, and 13.x for any host tooling -GCCVERSION:microblaze = "12.2.%" -SDKGCCVERSION:microblaze = "13.%" - -# canon-prefix-map doesn't exist in gcc 12.x -DEBUG_PREFIX_MAP:remove:microblaze = "-fcanon-prefix-map" - MICROBLAZE_SKIP_MSG = "" MICROBLAZE_SKIP_MSG:microblaze = "This recipe does not currently work on microblaze." diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc b/meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc deleted file mode 100644 index 0dbbecad..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12.2.inc +++ /dev/null @@ -1,114 +0,0 @@ -require gcc-common.inc - -# Third digit in PV should be incremented after a minor release - -PV = "12.2.0" - -# BINV should be incremented to a revision after a minor gcc release - -BINV = "12.2.0" - -FILESEXTRAPATHS =. "${FILE_DIRNAME}/gcc:${FILE_DIRNAME}/gcc/backport:" - -DEPENDS =+ "mpfr gmp libmpc zlib flex-native" -NATIVEDEPS = "mpfr-native gmp-native libmpc-native zlib-native flex-native zstd-native" - -LICENSE = "GPL-3.0-with-GCC-exception & GPL-3.0-only" - -LIC_FILES_CHKSUM = "\ - file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \ - file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \ - file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \ - file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \ - file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8 \ -" -# from git -#RELEASE ?= "7092b7aea122a91824d048aeb23834cf1d19b1a1" -#BASEURI ?= "https://repo.or.cz/official-gcc.git/snapshot/${RELEASE}.tar.gz;downloadfilename=gcc-${PV}-${RELEASE}.tar.gz" -#SOURCEDIR ?= "official-gcc-${@'${RELEASE}'[0:7]}" - -# from snapshot -#RELEASE ?= "12.1.0-RC-20220429" -#SOURCEDIR ?= "gcc-${RELEASE}" -#BASEURI ?= "https://gcc.gnu.org/pub/gcc/snapshots/${RELEASE}/gcc-${RELEASE}.tar.xz" - -# official release -RELEASE ?= "${PV}" -BASEURI ?= "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.xz" -SOURCEDIR ?= "gcc-${PV}" - -SRC_URI = "${BASEURI} \ - file://0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \ - file://0002-gcc-poison-system-directories.patch \ - file://0003-64-bit-multilib-hack.patch \ - file://0004-Pass-CXXFLAGS_FOR_BUILD-in-a-couple-of-places-to-avo.patch \ - file://0005-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch \ - file://0006-cpp-honor-sysroot.patch \ - file://0007-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch \ - file://0008-libtool.patch \ - file://0009-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch \ - file://0010-Use-the-multilib-config-files-from-B-instead-of-usin.patch \ - file://0011-Avoid-using-libdir-from-.la-which-usually-points-to-.patch \ - file://0013-Ensure-target-gcc-headers-can-be-included.patch \ - file://0014-Don-t-search-host-directory-during-relink-if-inst_pr.patch \ - file://0015-libcc1-fix-libcc1-s-install-path-and-rpath.patch \ - file://0016-handle-sysroot-support-for-nativesdk-gcc.patch \ - file://0017-Search-target-sysroot-gcc-version-specific-dirs-with.patch \ - file://0018-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch \ - file://0019-Re-introduce-spe-commandline-options.patch \ - file://0020-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch \ - file://0021-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch \ - file://0023-libatomic-Do-not-enforce-march-on-aarch64.patch \ - file://0024-Fix-install-path-of-linux64.h.patch \ - file://0026-rust-recursion-limit.patch \ - file://prefix-map-realpath.patch \ - file://hardcoded-paths.patch \ -" -SRC_URI[sha256sum] = "e549cf9cf3594a00e27b6589d4322d70e0720cdd213f39beb4181e06926230ff" - -S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/${SOURCEDIR}" -B = "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}" - -# Language Overrides -FORTRAN = "" -JAVA = "" - -SSP ?= "--disable-libssp" -SSP:mingw32 = "--enable-libssp" - -EXTRA_OECONF_BASE = "\ - ${SSP} \ - --enable-libitm \ - --enable-lto \ - --disable-bootstrap \ - --with-system-zlib \ - ${@'--with-linker-hash-style=${LINKER_HASH_STYLE}' if '${LINKER_HASH_STYLE}' else ''} \ - --enable-linker-build-id \ - --with-ppl=no \ - --with-cloog=no \ - --enable-checking=release \ - --enable-cheaders=c_global \ - --without-isl \ -" - -EXTRA_OECONF_INITIAL = "\ - --disable-libgomp \ - --disable-libitm \ - --disable-libquadmath \ - --with-system-zlib \ - --disable-lto \ - --disable-plugin \ - --enable-linker-build-id \ - --enable-decimal-float=no \ - --without-isl \ - --disable-libssp \ -" - -EXTRA_OECONF_PATHS = "\ - --with-gxx-include-dir=/not/exist{target_includedir}/c++/${BINV} \ - --with-sysroot=/not/exist \ - --with-build-sysroot=${STAGING_DIR_TARGET} \ -" - -# Is a binutils 2.26 issue, not gcc -CVE_CHECK_IGNORE += "CVE-2021-37322" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch index f8985752..1099a0e8 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch @@ -2,8 +2,6 @@ From 376b0ee790231a99fe50b50e20070c104bbba0d8 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati Date: Wed, 11 Jan 2017 13:13:57 +0530 Subject: [PATCH 01/53] LOCAL]: Testsuite - builtins tests require fpic -Upstream-Status: Pending - Signed-off-by: David Holsgrove Conflicts: diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch index 5302b942..061dfc86 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch @@ -6,8 +6,6 @@ Subject: [PATCH 02/53] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This for microblaze. This speeds up the testsuite without removing it from the FAIL reports. -Upstream-Status: Pending - Signed-off-by: Edgar E. Iglesias --- gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch index 89fe0ff6..1b5d428e 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch @@ -6,8 +6,6 @@ Subject: [PATCH 03/53] [LOCAL]: For dejagnu static testing on qemu, suppress with method used by powerpc. Dynamic linking and using a qemu binary which understands sysroot resolves all test failures with builtins -Upstream-Status: Pending - Signed-off-by: David Holsgrove --- gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ---- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch index 39c9c17e..8db33100 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch @@ -13,8 +13,6 @@ Changelog/testsuite * gcc/testsuite/lib/target-supports.exp: Add microblaze to check_effective_target_sync_int_long. -Upstream-Status: Pending - Signed-off-by: David Holsgrove --- gcc/testsuite/lib/target-supports.exp | 1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch index d127a03e..0fb32850 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch @@ -11,8 +11,6 @@ ChangeLog/testsuite * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update to include $LC label. -Upstream-Status: Pending - Signed-off-by: David Holsgrove --- gcc/testsuite/gcc.target/microblaze/others/strings1.c | 4 ++++ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch index 3c412471..a82f11cc 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch @@ -13,8 +13,6 @@ ChangeLog/testsuite pattern to take optional ext after .weak. * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. -Upstream-Status: Pending - Signed-off-by: David Holsgrove Conflicts: diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch index 89d3b75a..736f5cd1 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch @@ -6,8 +6,6 @@ Subject: [PATCH 07/53] [Patch, testsuite]: Add MicroBlaze to check_profiling_available inline with other archs setting profiling_available_saved to 0 -Upstream-Status: Pending - Signed-off-by: David Holsgrove --- gcc/testsuite/lib/target-supports.exp | 1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch index 21747726..451070c0 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch @@ -7,8 +7,6 @@ Subject: [PATCH 08/53] [Patch, microblaze]: Fix atomic side effects. In generated assembly code with undefined side effects after invocation of the atomic. -Upstream-Status: Pending - Signed-off-by: Kirk Meyer Signed-off-by: David Holsgrove diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch index 97f35569..c7efbb07 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch @@ -5,8 +5,6 @@ Subject: [PATCH 09/53] [Patch, microblaze]: Fix atomic boolean return value. In atomic_compare_and_swapsi, fix boolean return value. Previously, it contained zero if successful and non-zero if unsuccessful. -Upstream-Status: Pending - Signed-off-by: Kirk Meyer Signed-off-by: David Holsgrove --- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch index 62bb02a9..1bffafa9 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch @@ -9,8 +9,6 @@ Subject: [PATCH 10/53] [Patch, microblaze]: Fix the Microblaze crash with have subreg register due to this compiler was crashing. Changed the logic to avoid sub_reg call -Upstream-Status: Pending - Signed-off-by:Nagaraju Mekala Conflicts: diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch index 09ebfca6..1bd73b8a 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch @@ -6,8 +6,6 @@ Subject: [PATCH 11/53] [Patch, microblaze]: Added ashrsi3_with_size_opt Added optimization is used. lshrsi3_with_size_opt is being removed as it has conflicts with unsigned int variables -Upstream-Status: Pending - Signed-off-by:Nagaraju Mekala --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch index c26d46d4..f40fff9a 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch @@ -2,8 +2,6 @@ From 12d7e086376916ef61e2c48639671fd0f7c8fbbf Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati Date: Tue, 17 Jan 2017 10:57:19 +0530 Subject: [PATCH 12/53] [Patch, microblaze]: Use bralid for profiler calls -Upstream-Status: Pending - Signed-off-by: Edgar E. Iglesias --- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch index 8739e6ea..5c927264 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch @@ -4,8 +4,6 @@ Date: Thu, 12 Jan 2017 17:36:16 +0530 Subject: [PATCH 13/53] [Patch, microblaze]: Removed moddi3 routinue Using the default moddi3 function as the existing implementation has many bugs -Upstream-Status: Pending - Signed-off-by:Nagaraju Conflicts: diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch index 472c543c..f8bcabe3 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch @@ -10,10 +10,6 @@ attribute by specifying a relative priority, a constant integral expression currently bounded between 101 and 65535 inclusive. Lower numbers indicate a higher priority. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 53 +++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch index 7ce5ebc0..0f7d356f 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch @@ -17,8 +17,6 @@ ChangeLog/testsuite * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. -Upstream-Status: Pending - Signed-off-by:Nagaraju Signed-off-by: David Holsgrove --- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch index dc645c30..19ae324d 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch @@ -6,8 +6,6 @@ Subject: [PATCH 16/53] [Patch, microblaze]: Add cbranchsi4_reg This patch instruction has no immediate values.For the immediate values the xor instruction is generated -Upstream-Status: Pending - Signed-off-by: Nagaraju Mekala Signed-off-by: Ajit Agarwal diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch index b0d33516..e3a98a08 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch @@ -22,8 +22,6 @@ ChangeLog: * config/microblaze/microblaze.md (sqrtdf2): New pattern. -Upstream-Status: Pending - Signed-off-by:Ajit Agarwal ajitkum@xilinx.com Nagaraju Mekala nmekala@xilinx.com --- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch index 94235be6..831b8f22 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch @@ -17,8 +17,6 @@ implement purely with instructions as microblaze does not provide an instruction to perform a forward arithmetic subtraction (it only provides reverse 'rD = IMM - rA'). -Upstream-Status: Pending - Signed-off-by: Nathan Rossi --- gcc/config/microblaze/microblaze.md | 13 ++++++------- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch index e955938e..ab3fa535 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch @@ -24,10 +24,6 @@ ChangeLog: Conflicts: gcc/config/microblaze/microblaze.c -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 2 +- gcc/config/microblaze/microblaze.md | 10 ++++++++-- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch index 2d384b78..67eb0893 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch @@ -6,10 +6,6 @@ Subject: [PATCH 20/53] [Patch, microblaze]: 8-stage pipeline for microblaze pipeline reduces the latencies of float & integer division drastically Signed-off-by :Nagaraju Mekala -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 11 ++++ gcc/config/microblaze/microblaze.h | 3 +- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch index 1b8d924c..96fe4f73 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch @@ -9,10 +9,6 @@ Subject: [PATCH 21/53] [PATCH 21/53] [Patch, microblaze]: Correct the const Signed-off-by :Nagaraju Mekala Ajit Agarwal -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 6 ++++-- gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch index a5917947..332db5d3 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch @@ -9,10 +9,6 @@ Subject: [PATCH 22/53] [Fix, microblaze]: Fix internal compiler error with Signed-off-by :Nagaraju Mekala Ajit Agarwal -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch index ae05e791..47e13fa6 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch @@ -14,10 +14,6 @@ Subject: [PATCH 23/53] [patch,microblaze]: Fix the calculation of high word in Signed-off-by :Nagaraju Mekala Ajit Agarwal -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch index 444c9397..8ed5ae83 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch @@ -5,10 +5,6 @@ Subject: [PATCH 24/53] [Patch,MicroBlaze] : this patch has 1.Fixed the bug in version calculation. 2.Add new bitfield instructions. Signed-off-by :Mahesh Bodapati -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 154 ++++++++++++++-------------- gcc/config/microblaze/microblaze.h | 2 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch index 2800dee7..109e0686 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch @@ -6,10 +6,6 @@ Subject: [PATCH 25/53] Fixing the issue with the builtin_alloc. register r18 available register signed-off-by:nagaraju mekala -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch index a1e4fb36..4f101b96 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch @@ -4,10 +4,6 @@ Date: Mon, 4 Jun 2018 10:10:18 +0530 Subject: [PATCH 26/53] [Patch,Microblaze] : Removed fsqrt generation for double values. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch index a9222e54..2e7106d6 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch @@ -5,10 +5,6 @@ Subject: [PATCH 27/53] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze Conflicts: gcc/config/microblaze/microblaze.md -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/constraints.md | 6 + gcc/config/microblaze/microblaze-protos.h | 1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch index c36e246a..1ffa79cb 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch @@ -4,10 +4,6 @@ Date: Tue, 13 Sep 2022 14:38:48 +0530 Subject: [PATCH 28/53] Intial commit for 64bit-MB sources. Need to cleanup the code later. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/constraints.md | 2 +- gcc/config/microblaze/microblaze-c.cc | 6 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch index 0a275c0b..26cdfca2 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch @@ -4,10 +4,6 @@ Date: Tue, 13 Sep 2022 14:45:15 +0530 Subject: [PATCH 29/53] [Patch,MicroBlaze] : re-arrangement of the compare branches -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 28 ++---- gcc/config/microblaze/microblaze.md | 141 +++++++++++++--------------- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch index bda4e7da..83d047cb 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch @@ -4,10 +4,6 @@ Date: Wed, 8 Aug 2018 17:37:26 +0530 Subject: [PATCH 30/53] [Patch,Microblaze] : previous commit broke the handling of SI Branch compare for Microblaze 32-bit.. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch index a9a7a03d..c230049c 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch @@ -7,10 +7,6 @@ Conflicts: gcc/config/microblaze/microblaze-c.c signed-off-by : Mahesh Bodapati -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze-c.cc | 1 + gcc/config/microblaze/t-microblaze | 15 ++++++--------- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Patch-MicroBlaze-Fixed-issues-like.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Patch-MicroBlaze-Fixed-issues-like.patch index cb62c5a7..36a20450 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Patch-MicroBlaze-Fixed-issues-like.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Patch-MicroBlaze-Fixed-issues-like.patch @@ -4,10 +4,6 @@ Date: Tue, 13 Sep 2022 15:24:25 +0530 Subject: [PATCH 32/53] [Patch,MicroBlaze]: Fixed issues like: 1 Interrupt alignment issue 2 Sign extension issue -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 16 ++++++++++------ gcc/config/microblaze/microblaze.md | 2 +- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Patch-MicroBlaze.patch index 9760695c..9c9e4dd2 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Patch-MicroBlaze.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Patch-MicroBlaze.patch @@ -7,10 +7,6 @@ Subject: [PATCH 33/53] [Patch,MicroBlaze]: fixed below issues: - Floating Conflicts: gcc/config/microblaze/microblaze.md -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 12 +++- gcc/config/microblaze/microblaze.h | 7 +++ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch index 3f07dfa1..7bd3001d 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch @@ -4,10 +4,6 @@ Date: Tue, 9 Oct 2018 10:07:08 +0530 Subject: [PATCH 34/53] -Added double arith instructions -Fixed prologue stack pointer decrement issue -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++---- gcc/config/microblaze/t-microblaze | 7 +++ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch index 3ff6a2d0..89018aae 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch @@ -4,10 +4,6 @@ Date: Fri, 12 Oct 2018 16:07:36 +0530 Subject: [PATCH 35/53] Fixed the issue in the delay slot with swap instructions -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch index 90ddf3eb..0c27d69f 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch @@ -4,10 +4,6 @@ Date: Sat, 13 Oct 2018 21:12:43 +0530 Subject: [PATCH 36/53] Fixed the load store issue with the 32bit arith libraries -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++- libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch index 191c7627..2eab03ec 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch @@ -3,10 +3,6 @@ From: Nagaraju Mekala Date: Mon, 15 Oct 2018 12:00:10 +0530 Subject: [PATCH 37/53] extending the Dwarf support to 64bit Microblaze -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch index 8697be58..4d6be758 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch @@ -3,10 +3,6 @@ From: Nagaraju Mekala Date: Tue, 16 Oct 2018 07:55:46 +0530 Subject: [PATCH 38/53] fixing the typo errors in umodsi3 file -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- libgcc/config/microblaze/umodsi3.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch index 032cab4d..1a5a0ef7 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch @@ -3,10 +3,6 @@ From: Nagaraju Mekala Date: Wed, 17 Oct 2018 16:56:14 +0530 Subject: [PATCH 39/53] fixing the 32bit LTO related issue9(1014024) -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch index 1ed53957..7c6f9008 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch @@ -4,10 +4,6 @@ Date: Fri, 19 Oct 2018 14:26:25 +0530 Subject: [PATCH 40/53] Fixed the missing stack adjustment in prologue of modsi3 function -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- libgcc/config/microblaze/modsi3.S | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch index e6335e8e..9cec7be9 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch @@ -4,10 +4,6 @@ Date: Wed, 24 Oct 2018 18:31:04 +0530 Subject: [PATCH 41/53] [Patch,Microblaze] : corrected SPN for dlong instruction mapping. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch index f4013b9e..8836d0e7 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -3,10 +3,6 @@ From: Nagaraju Mekala Date: Thu, 29 Nov 2018 17:55:08 +0530 Subject: [PATCH 42/53] fixing the long & long long mingw toolchain issue -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/constraints.md | 2 +- gcc/config/microblaze/microblaze.md | 8 ++++---- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch index 7f3c8373..c8caff29 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch @@ -3,10 +3,6 @@ From: Nagaraju Date: Thu, 14 Mar 2019 18:11:04 +0530 Subject: [PATCH 43/53] Fix the MB-64 bug of handling QI objects -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch index 14eb812a..e0d7df3d 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch @@ -4,10 +4,6 @@ Date: Fri, 29 Mar 2019 12:08:39 +0530 Subject: [PATCH 44/53] [Patch,Microblaze] : We will check the possibility of peephole2 optimization,if we can then we will fix the compiler issue. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------ 1 file changed, 38 insertions(+), 25 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch index 54135b0f..770d0f70 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch @@ -4,10 +4,6 @@ Date: Wed, 17 Apr 2019 12:36:16 +0530 Subject: [PATCH 45/53] [Patch,MicroBlaze]: fixed typos in mul,div and mod assembly files. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++---- libgcc/config/microblaze/modsi3.S | 40 ++++++++++++++++++--- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch index def10321..29a7b4eb 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch @@ -8,10 +8,6 @@ Subject: [PATCH 46/53] [Patch, microblaze]: MB-64 removal of barrel-shift enabled. Similarly to double instructions as well. Signed-off-by :Nagaraju Mekala -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 2 +- gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++-- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch index 318abe7b..774fad5a 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch @@ -3,10 +3,6 @@ From: Nagaraju Date: Fri, 23 Aug 2019 16:16:53 +0530 Subject: [PATCH 47/53] Added new MB-64 single register arithmetic instructions -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch index 09514a7d..a442bf0f 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch @@ -4,10 +4,6 @@ Date: Mon, 26 Aug 2019 15:55:22 +0530 Subject: [PATCH 48/53] [Patch,MicroBlaze] : Added support for 64 bit Immediate values. -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/constraints.md | 4 ++-- gcc/config/microblaze/microblaze.md | 3 +-- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch index 6258e799..5732000d 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch @@ -7,10 +7,6 @@ Subject: [PATCH 49/53] [Patch, microblaze]: Fix Compiler crash with With this patch all other modes are handled properly Signed-off-by :Nagaraju Mekala -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 11 ++++++++++- gcc/config/microblaze/microblaze.h | 19 ------------------- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch index 8d99c93d..ed48daf7 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch @@ -9,8 +9,6 @@ Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. * gcc/common/config/microblaze/microblaze-common.c (microblaze_option_optimization_table): Disable fivopts by default. -Upstream-Status: Pending - Signed-off-by: Nagaraju Mekala Mahesh Bodapati Conflicts: diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch index 64069e3c..b9575eac 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch @@ -9,10 +9,6 @@ Subject: [PATCH 51/53] [Patch, microblaze]: Reducing Stack space for arguments Signed-off-by :Nagaraju Mekala :Ajit Agarwal -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze-protos.h | 1 + gcc/config/microblaze/microblaze.cc | 130 ++++++++++++++++++++++ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch index 63feff79..d504a092 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch @@ -8,10 +8,6 @@ Subject: [PATCH 52/53] [Patch,MicroBlaze] : If we use break_handler break_handler attribute. signed-off-by : Mahesh Bodapati -Upstream-Status: Pending - -Signed-off-by: Mark Hatle - --- gcc/config/microblaze/microblaze.cc | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch index 1552a5e9..6b3f4ddd 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch @@ -9,8 +9,6 @@ Subject: [PATCH 53/53] [patch, microblaze64]: Add Zero_extended instructions [CR/TSR]: TSR-974519 -Upstream-Status: Pending - Signed-off-by: Nagaraju Mekala Mahesh Bodapati --- diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch index 56d8c223..af8ebf3b 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch @@ -27,7 +27,7 @@ Do same for riscv64 and aarch64 RP 15/8/11 -Upstream-Status: Inappropriate [OE-Specific] +Upstream-Status: Inappropriate[OE-Specific] Signed-off-by: Khem Raj Signed-off-by: Elvis Dowson diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-common.inc b/meta-microblaze/recipes-devtools/gcc/gcc-common.inc deleted file mode 100644 index 5ac82b1b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-common.inc +++ /dev/null @@ -1,118 +0,0 @@ -SUMMARY = "GNU cc and gcc C compilers" -HOMEPAGE = "http://www.gnu.org/software/gcc/" -DESCRIPTION = "The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Ada, Go, and D, as well as libraries for these languages (libstdc++,...). GCC was originally written as the compiler for the GNU operating system." -SECTION = "devel" -LICENSE = "GPL" - -NATIVEDEPS = "" - -CVE_PRODUCT = "gcc" - -inherit autotools gettext texinfo - -BPN = "gcc" -COMPILERDEP = "virtual/${TARGET_PREFIX}gcc:do_gcc_stash_builddir" - -python extract_stashed_builddir () { - src = d.expand("${COMPONENTS_DIR}/${BUILD_ARCH}/gcc-stashed-builddir-${TARGET_SYS}") - dest = d.getVar("B") - oe.path.copyhardlinktree(src, dest) - staging_processfixme([src + "/fixmepath"], dest, d.getVar("RECIPE_SYSROOT"), d.getVar("RECIPE_SYSROOT_NATIVE"), d) -} - -def get_gcc_float_setting(bb, d): - if d.getVar('ARMPKGSFX_EABI') == "hf" and d.getVar('TRANSLATED_TARGET_ARCH') == "arm": - return "--with-float=hard" - if d.getVar('TARGET_FPU') in [ 'soft' ]: - return "--with-float=soft" - if d.getVar('TARGET_FPU') in [ 'ppc-efd' ]: - return "--enable-e500_double" - return "" - -get_gcc_float_setting[vardepvalue] = "${@get_gcc_float_setting(bb, d)}" - -def get_gcc_x86_64_arch_setting(bb, d): - import re - march = re.match(r'^.*-march=([^\s]*)', d.getVar('TUNE_CCARGS')) - if march: - return "--with-arch=%s " % march.group(1) - # The earliest supported x86-64 CPU - return "--with-arch=core2" - -get_gcc_x86_64_arch_setting[vardepvalue] = "${@get_gcc_x86_64_arch_setting(bb, d)}" - -def get_gcc_mips_plt_setting(bb, d): - if d.getVar('TRANSLATED_TARGET_ARCH') in [ 'mips', 'mipsel' ] and bb.utils.contains('DISTRO_FEATURES', 'mplt', True, False, d): - return "--with-mips-plt" - return "" - -def get_gcc_ppc_plt_settings(bb, d): - if d.getVar('TRANSLATED_TARGET_ARCH') in [ 'powerpc', 'powerpc64' ] and not bb.utils.contains('DISTRO_FEATURES', 'bssplt', True, False, d): - return "--enable-secureplt" - return "" - -def get_gcc_multiarch_setting(bb, d): - target_arch = d.getVar('TRANSLATED_TARGET_ARCH') - multiarch_options = { - "i586": "--enable-targets=all", - "i686": "--enable-targets=all", - "powerpc": "--enable-targets=powerpc64", - "powerpc64le": "--enable-targets=powerpcle", - "mips": "--enable-targets=all", - "sparc": "--enable-targets=all", - } - - if bb.utils.contains('DISTRO_FEATURES', 'multiarch', True, False, d): - if target_arch in multiarch_options : - return multiarch_options[target_arch] - return "" - -# this is used by the multilib setup of gcc -def get_tune_parameters(tune, d): - availtunes = d.getVar('AVAILTUNES') - if tune not in availtunes.split(): - bb.error('The tune: %s is not one of the available tunes: %s' % (tune or None, availtunes)) - - localdata = bb.data.createCopy(d) - override = ':tune-' + tune - localdata.setVar('OVERRIDES', localdata.getVar('OVERRIDES', False) + override) - - retdict = {} - retdict['tune'] = tune - retdict['ccargs'] = localdata.getVar('TUNE_CCARGS') - retdict['features'] = localdata.getVar('TUNE_FEATURES') - # BASELIB is used by the multilib code to change library paths - retdict['baselib'] = localdata.getVar('BASE_LIB') or localdata.getVar('BASELIB') - retdict['arch'] = localdata.getVar('TUNE_ARCH') - retdict['abiextension'] = localdata.getVar('ABIEXTENSION') - retdict['target_fpu'] = localdata.getVar('TARGET_FPU') - retdict['pkgarch'] = localdata.getVar('TUNE_PKGARCH') - retdict['package_extra_archs'] = localdata.getVar('PACKAGE_EXTRA_ARCHS') - return retdict - -get_tune_parameters[vardepsexclude] = "AVAILTUNES TUNE_CCARGS OVERRIDES TUNE_FEATURES BASE_LIB BASELIB TUNE_ARCH ABIEXTENSION TARGET_FPU TUNE_PKGARCH PACKAGE_EXTRA_ARCHS" - -DEBIANNAME:${MLPREFIX}libgcc = "libgcc1" - -MIRRORS =+ "\ - ${GNU_MIRROR}/gcc https://gcc.gnu.org/pub/gcc/releases/ \ -" -# -# Set some default values -# -gcclibdir = "${libdir}/gcc" -BINV = "${PV}" -#S = "${WORKDIR}/gcc-${PV}" -S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}" - -B ?= "${WORKDIR}/gcc-${PV}/build.${HOST_SYS}.${TARGET_SYS}" - -target_includedir ?= "${includedir}" -target_libdir ?= "${libdir}" -target_base_libdir ?= "${base_libdir}" -target_prefix ?= "${prefix}" - -# We need to ensure that for the shared work directory, the do_patch signatures match -# The real WORKDIR location isn't a dependency for the shared workdir. -src_patches[vardepsexclude] = "WORKDIR" -should_apply[vardepsexclude] += "PN" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-configure-common.inc b/meta-microblaze/recipes-devtools/gcc/gcc-configure-common.inc deleted file mode 100644 index e4cdb73f..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-configure-common.inc +++ /dev/null @@ -1,123 +0,0 @@ -require gcc-multilib-config.inc -require gcc-shared-source.inc -# -# Build the list of lanaguages to build. -# -# These can be overridden by the version specific .inc file. - -# gcc 3.x expects 'f77', 4.0 expects 'f95', 4.1 and 4.2 expect 'fortran' -FORTRAN ?= ",f77" -LANGUAGES ?= "c,c++${FORTRAN}" - -EXTRA_OECONF_BASE ?= "" -EXTRA_OECONF_PATHS ?= "" - -GCCMULTILIB ?= "--disable-multilib" -GCCTHREADS ?= "posix" - -GCCPIE ??= "" - -SYMVERS_CONF ?= "--enable-symvers=gnu" - -EXTRA_OECONF = "\ - ${@['--enable-clocale=generic', ''][d.getVar('USE_NLS') != 'no']} \ - --with-gnu-ld \ - --enable-shared \ - --enable-languages=${LANGUAGES} \ - --enable-threads=${GCCTHREADS} \ - ${GCCMULTILIB} \ - ${GCCPIE} \ - --enable-c99 \ - --enable-long-long \ - ${SYMVERS_CONF} \ - --enable-libstdcxx-pch \ - --program-prefix=${TARGET_PREFIX} \ - --without-local-prefix \ - --disable-install-libiberty \ - ${EXTRA_OECONF_BASE} \ - ${EXTRA_OECONF_GCC_FLOAT} \ - ${EXTRA_OECONF_PATHS} \ - ${@get_gcc_mips_plt_setting(bb, d)} \ - ${@get_gcc_ppc_plt_settings(bb, d)} \ - ${@get_gcc_multiarch_setting(bb, d)} \ - --enable-standard-branch-protection \ -" - -# glibc version is a minimum controlling whether features are enabled. -# Doesn't need to track glibc exactly -EXTRA_OECONF:append:libc-glibc = " --with-glibc-version=2.28 " - -# Set this here since GCC configure won't auto-detect and enable -# initfini-arry when cross compiling. -EXTRA_OECONF:append = " --enable-initfini-array" - -export gcc_cv_collect2_libs = 'none required' -# We need to set gcc_cv_collect2_libs else there is cross-compilation badness -# in the config.log files (which might not get generated until do_compile -# hence being missed by the insane do_configure check). - -EXTRA_OECONF:append:linux = " --enable-__cxa_atexit" - -EXTRA_OECONF:append:mips64 = " --with-abi=64 --with-arch-64=mips64 --with-tune-64=mips64" -EXTRA_OECONF:append:mips64el = " --with-abi=64 --with-arch-64=mips64 --with-tune-64=mips64" -EXTRA_OECONF:append:mips64n32 = " --with-abi=64 --with-arch-64=mips64 --with-tune-64=mips64" -EXTRA_OECONF:append:mips64eln32 = " --with-abi=64 --with-arch-64=mips64 --with-tune-64=mips64" -EXTRA_OECONF:append:mipsisa32r6el = " --with-abi=32 --with-arch=mips32r6" -EXTRA_OECONF:append:mipsisa32r6 = " --with-abi=32 --with-arch=mips32r6" -EXTRA_OECONF:append:mipsisa64r6el = " --with-abi=64 --with-arch-64=mips64r6" -EXTRA_OECONF:append:mipsisa64r6 = " --with-abi=64 --with-arch-64=mips64r6" - -EXTRA_OECONF_GCC_FLOAT ??= "" -CPPFLAGS = "" - -SYSTEMHEADERS = "${target_includedir}" -SYSTEMLIBS = "${target_base_libdir}/" -SYSTEMLIBS1 = "${target_libdir}/" - -do_configure:prepend () { - # teach gcc to find correct target includedir when checking libc ssp support - mkdir -p ${B}/gcc - echo "NATIVE_SYSTEM_HEADER_DIR = ${SYSTEMHEADERS}" > ${B}/gcc/t-oe - cat ${S}/gcc/defaults.h | grep -v "\#endif.*GCC_DEFAULTS_H" > ${B}/gcc/defaults.h.new - cat >>${B}/gcc/defaults.h.new <<_EOF -#define NATIVE_SYSTEM_HEADER_DIR "${SYSTEMHEADERS}" -#define STANDARD_STARTFILE_PREFIX_1 "${SYSTEMLIBS}" -#define STANDARD_STARTFILE_PREFIX_2 "${SYSTEMLIBS1}" -#define SYSTEMLIBS_DIR "${SYSTEMLIBS}" -#endif /* ! GCC_DEFAULTS_H */ -_EOF - mv ${B}/gcc/defaults.h.new ${B}/gcc/defaults.h -} - -do_configure () { - # Setup these vars for cross building only - # ... because foo_FOR_TARGET apparently gets misinterpreted inside the - # gcc build stuff when the build is producing a cross compiler - i.e. - # when the 'current' target is the 'host' system, and the host is not - # the target (because the build is actually making a cross compiler!) - if [ "${BUILD_SYS}" != "${HOST_SYS}" ]; then - export CC_FOR_TARGET="${CC}" - export GCC_FOR_TARGET="${CC}" - export CXX_FOR_TARGET="${CXX}" - export AS_FOR_TARGET="${HOST_PREFIX}as" - export LD_FOR_TARGET="${HOST_PREFIX}ld" - export NM_FOR_TARGET="${HOST_PREFIX}nm" - export AR_FOR_TARGET="${HOST_PREFIX}ar" - export GFORTRAN_FOR_TARGET="gfortran" - export RANLIB_FOR_TARGET="${HOST_PREFIX}ranlib" - fi - export CC_FOR_BUILD="${BUILD_CC}" - export CXX_FOR_BUILD="${BUILD_CXX}" - export CFLAGS_FOR_BUILD="${BUILD_CFLAGS}" - export CPPFLAGS_FOR_BUILD="${BUILD_CPPFLAGS}" - export CXXFLAGS_FOR_BUILD="${BUILD_CXXFLAGS}" - export LDFLAGS_FOR_BUILD="${BUILD_LDFLAGS}" - export CFLAGS_FOR_TARGET="${TARGET_CFLAGS}" - export CPPFLAGS_FOR_TARGET="${TARGET_CPPFLAGS}" - export CXXFLAGS_FOR_TARGET="${TARGET_CXXFLAGS}" - export LDFLAGS_FOR_TARGET="${TARGET_LDFLAGS}" - - - oe_runconf -} - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian.inc b/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian.inc deleted file mode 100644 index ec87b462..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian.inc +++ /dev/null @@ -1,187 +0,0 @@ -inherit cross-canadian - -SUMMARY = "GNU cc and gcc C compilers (cross-canadian for ${TARGET_ARCH} target)" -PN = "gcc-cross-canadian-${TRANSLATED_TARGET_ARCH}" - -DEPENDS = "virtual/${TARGET_PREFIX}gcc virtual/${HOST_PREFIX}gcc virtual/${HOST_PREFIX}binutils virtual/nativesdk-libc nativesdk-gettext flex-native virtual/libc" - -GCCMULTILIB = "--enable-multilib" - -require gcc-configure-common.inc - -EXTRA_OECONF += "--with-plugin-ld=ld" -EXTRA_OECONF_PATHS = "\ - --with-gxx-include-dir=/not/exist${target_includedir}/c++/${BINV} \ - --with-build-time-tools=${STAGING_DIR_NATIVE}${prefix_native}/${TARGET_SYS}/bin \ - --with-sysroot=/not/exist \ - --with-build-sysroot=${STAGING_DIR_TARGET} \ -" -# We have to point gcc at a sysroot but we don't need to rebuild if this changes -# e.g. we switch between different machines with different tunes. -EXTRA_OECONF_PATHS[vardepsexclude] = "TUNE_PKGARCH" -TARGET_ARCH[vardepsexclude] = "TUNE_ARCH" -get_gcc_float_setting[vardepvalue] = "" - -# -# gcc-cross looks and finds these in ${exec_prefix} but we're not so lucky -# for the sdk. Hardcoding the paths ensures the build doesn't go canadian or worse. -# -export AR_FOR_TARGET = "${TARGET_PREFIX}ar" -export AS_FOR_TARGET = "${TARGET_PREFIX}as" -export DLLTOOL_FOR_TARGET = "${TARGET_PREFIX}dlltool" -export CC_FOR_TARGET = "${TARGET_PREFIX}gcc" -export CXX_FOR_TARGET = "${TARGET_PREFIX}g++" -export GCC_FOR_TARGET = "${TARGET_PREFIX}gcc" -export LD_FOR_TARGET = "${TARGET_PREFIX}ld" -export LIPO_FOR_TARGET = "${TARGET_PREFIX}lipo" -export NM_FOR_TARGET = "${TARGET_PREFIX}nm" -export OBJDUMP_FOR_TARGET = "${TARGET_PREFIX}objdump" -export RANLIB_FOR_TARGET = "${TARGET_PREFIX}ranlib" -export STRIP_FOR_TARGET = "${TARGET_PREFIX}strip" -export WINDRES_FOR_TARGET = "${TARGET_PREFIX}windres" - -# -# We need to override this and make sure the compiler can find staging -# -export ARCH_FLAGS_FOR_TARGET = "--sysroot=${STAGING_DIR_TARGET}" - -do_configure () { - if [ ! -d ${RECIPE_SYSROOT}/${target_includedir} ]; then - mkdir -p ${RECIPE_SYSROOT}/${target_includedir} - fi - export CC_FOR_BUILD="${BUILD_CC}" - export CXX_FOR_BUILD="${BUILD_CXX}" - export CFLAGS_FOR_BUILD="${BUILD_CFLAGS}" - export CPPFLAGS_FOR_BUILD="${BUILD_CPPFLAGS}" - export CXXFLAGS_FOR_BUILD="${BUILD_CXXFLAGS}" - export LDFLAGS_FOR_BUILD="${BUILD_LDFLAGS}" - export CFLAGS_FOR_TARGET="${TARGET_CFLAGS}" - export CPPFLAGS_FOR_TARGET="${TARGET_CPPFLAGS}" - export CXXFLAGS_FOR_TARGET="${TARGET_CXXFLAGS}" - export LDFLAGS_FOR_TARGET="${TARGET_LDFLAGS}" - oe_runconf -} - -do_compile () { - oe_runmake all-host configure-target-libgcc - (cd ${B}/${TARGET_SYS}/libgcc; oe_runmake enable-execute-stack.c unwind.h md-unwind-support.h sfp-machine.h gthr-default.h) -} - -PACKAGES = "${PN}-dbg ${PN} ${PN}-doc" - -FILES:${PN} = "\ - ${exec_prefix}/bin/* \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/* \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/*.o \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/specs \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/lib* \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/include \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/include-fixed \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/plugin/include/ \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/plugin/gtype.* \ - ${libdir}/bfd-plugins/*.so \ - ${includedir}/c++/${BINV} \ - ${prefix}/${TARGET_SYS}/bin/* \ - ${prefix}/${TARGET_SYS}/lib/* \ - ${prefix}/${TARGET_SYS}${target_includedir}/* \ -" -INSANE_SKIP:${PN} += "dev-so" - -FILES:${PN}-doc = "\ - ${infodir} \ - ${mandir} \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/include/README \ -" - -EXEEXT = "" - -# Compute how to get from libexecdir to bindir in python (easier than shell) -BINRELPATH = "${@os.path.relpath(d.expand("${bindir}"), d.expand("${libexecdir}/gcc/${TARGET_SYS}/${BINV}"))}" -# linker plugin path -LIBRELPATH = "${@os.path.relpath(d.expand("${libexecdir}/gcc/${TARGET_SYS}/${BINV}"), d.expand("${libdir}/bfd-plugins"))}" - -do_install () { - ( cd ${B}/${TARGET_SYS}/libgcc; oe_runmake 'DESTDIR=${D}' install-unwind_h-forbuild install-unwind_h ) - oe_runmake 'DESTDIR=${D}' install-host - - # Cleanup some of the ${libdir}{,exec}/gcc stuff ... - rm -r ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/install-tools - rm -r ${D}${libexecdir}/gcc/${TARGET_SYS}/${BINV}/install-tools - rm -rf ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/finclude - - # We care about g++ not c++ - rm -f ${D}${bindir}/*c++ - - # We don't care about the gcc- copies - rm -f ${D}${bindir}/*gcc-${BINV}* - - # Cleanup empty directories which are not shipped - # we use rmdir instead of 'rm -f' to ensure the non empty directories are not deleted - # ${D}${libdir}/../lib only seems to appear with SDKMACHINE=i686 - local empty_dirs="${D}${libdir}/../lib ${D}${prefix}/${TARGET_SYS}/lib ${D}${prefix}/${TARGET_SYS} ${D}${includedir}" - for i in $empty_dirs; do - [ -d $i ] && rmdir --ignore-fail-on-non-empty $i - done - - # Insert symlinks into libexec so when tools without a prefix are searched for, the correct ones are - # found. - dest=${D}${libexecdir}/gcc/${TARGET_SYS}/${BINV}/ - install -d $dest - suffix=${EXEEXT} - for t in ar as ld ld.bfd ld.gold nm objcopy objdump ranlib strip g77 gcc cpp gfortran; do - if [ "$t" = "g77" -o "$t" = "gfortran" ] && [ ! -e ${D}${bindir}/${TARGET_PREFIX}$t$suffix ]; then - continue - fi - - ln -sf ${BINRELPATH}/${TARGET_PREFIX}$t$suffix $dest$t$suffix - done - - # libquadmath headers need to be available in the gcc libexec dir - install -d ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ - cp ${S}/libquadmath/quadmath.h ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ - cp ${S}/libquadmath/quadmath_weak.h ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ - - # install LTO linker plugins where binutils tools can find it - install -d ${D}${libdir}/bfd-plugins - ln -sf ${LIBRELPATH}/liblto_plugin.so ${D}${libdir}/bfd-plugins/liblto_plugin.so - - chown -R root:root ${D} - - cross_canadian_bindirlinks - - for i in linux ${CANADIANEXTRAOS} - do - for v in ${CANADIANEXTRAVENDOR} - do - d=${D}${bindir}/../${TARGET_ARCH}$v-$i - install -d $d - for j in ${TARGET_PREFIX}gcc${EXEEXT} ${TARGET_PREFIX}g++${EXEEXT} - do - p=${TARGET_ARCH}$v-$i-`echo $j | sed -e s,${TARGET_PREFIX},,` - case $i in - *musl*) - rm -rf $d/$p - echo "#!/usr/bin/env sh" > $d/$p - echo "exec \`dirname \$0\`/../${TARGET_SYS}/$j -mmusl \$@" >> $d/$p - chmod 0755 $d/$p - ;; - *) - ;; - esac - done - done - done -} - -ELFUTILS = "nativesdk-elfutils" -DEPENDS += "nativesdk-gmp nativesdk-mpfr nativesdk-libmpc ${ELFUTILS} nativesdk-zlib nativesdk-zstd" -RDEPENDS:${PN} += "nativesdk-mpfr nativesdk-libmpc ${ELFUTILS}" - -SYSTEMHEADERS = "${target_includedir}/" -SYSTEMLIBS = "${target_base_libdir}/" -SYSTEMLIBS1 = "${target_libdir}/" - -EXTRA_OECONF += "--enable-poison-system-directories" - -# gcc 4.7 needs -isystem -export ARCH_FLAGS_FOR_TARGET = "--sysroot=${STAGING_DIR_TARGET} -isystem=${target_includedir}" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian_12.2.bb b/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian_12.2.bb deleted file mode 100644 index bf53c5cd..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian_12.2.bb +++ /dev/null @@ -1,5 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require gcc-cross-canadian.inc - - - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-cross-canadian_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-cross.inc b/meta-microblaze/recipes-devtools/gcc/gcc-cross.inc deleted file mode 100644 index a540fb24..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-cross.inc +++ /dev/null @@ -1,163 +0,0 @@ -inherit cross - -INHIBIT_DEFAULT_DEPS = "1" -EXTRADEPENDS = "" -DEPENDS = "virtual/${TARGET_PREFIX}binutils ${EXTRADEPENDS} ${NATIVEDEPS}" -PROVIDES = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++" -python () { - if d.getVar("TARGET_OS").startswith("linux"): - d.setVar("EXTRADEPENDS", "linux-libc-headers") -} - -PN = "gcc-cross-${TARGET_ARCH}" - -# Ignore how TARGET_ARCH is computed. -TARGET_ARCH[vardepvalue] = "${TARGET_ARCH}" - -require gcc-configure-common.inc - -# While we want the 'gnu' hash style, we explicitly set it to sysv here to -# ensure that any recipe which doesn't obey our LDFLAGS (which also set it to -# gnu) will hit a QA failure. -LINKER_HASH_STYLE ?= "sysv" - -EXTRA_OECONF += "--enable-poison-system-directories=error" -EXTRA_OECONF:append:sh4 = " \ - --with-multilib-list= \ - --enable-incomplete-targets \ -" - -EXTRA_OECONF += "\ - --with-system-zlib \ -" - -EXTRA_OECONF:append:libc-baremetal = " --without-headers" -EXTRA_OECONF:remove:libc-baremetal = "--enable-threads=posix" -EXTRA_OECONF:remove:libc-newlib = "--enable-threads=posix" - -EXTRA_OECONF_PATHS = "\ - --with-gxx-include-dir=/not/exist${target_includedir}/c++/${BINV} \ - --with-sysroot=/not/exist \ - --with-build-sysroot=${STAGING_DIR_TARGET} \ -" - -ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_DIR_TARGET}${target_includedir}" - - -do_configure:prepend () { - install -d ${RECIPE_SYSROOT}${target_includedir} - touch ${RECIPE_SYSROOT}${target_includedir}/limits.h -} - -do_compile () { - export CC="${BUILD_CC}" - export AR_FOR_TARGET="${TARGET_SYS}-ar" - export RANLIB_FOR_TARGET="${TARGET_SYS}-ranlib" - export LD_FOR_TARGET="${TARGET_SYS}-ld" - export NM_FOR_TARGET="${TARGET_SYS}-nm" - export CC_FOR_TARGET="${CCACHE} ${TARGET_SYS}-gcc" - export CFLAGS_FOR_TARGET="${TARGET_CFLAGS}" - export CPPFLAGS_FOR_TARGET="${TARGET_CPPFLAGS}" - export CXXFLAGS_FOR_TARGET="${TARGET_CXXFLAGS}" - export LDFLAGS_FOR_TARGET="${TARGET_LDFLAGS}" - - # Prevent native/host sysroot path from being used in configargs.h header, - # as it will be rewritten when used by other sysroots preventing support - # for gcc plugins - oe_runmake configure-gcc - sed -i 's@${STAGING_DIR_TARGET}@/host@g' ${B}/gcc/configargs.h - sed -i 's@${STAGING_DIR_HOST}@/host@g' ${B}/gcc/configargs.h - - # Prevent sysroot/workdir paths from being used in checksum-options. - # checksum-options is used to generate a checksum which is embedded into - # the output binary. - oe_runmake TARGET-gcc=checksum-options all-gcc - sed -i 's@${DEBUG_PREFIX_MAP}@@g' ${B}/gcc/checksum-options - sed -i 's@${STAGING_DIR_HOST}@/host@g' ${B}/gcc/checksum-options - - oe_runmake all-host configure-target-libgcc - (cd ${B}/${TARGET_SYS}/libgcc; oe_runmake enable-execute-stack.c unwind.h md-unwind-support.h sfp-machine.h gthr-default.h) -} - -INHIBIT_PACKAGE_STRIP = "1" - -# Compute how to get from libexecdir to bindir in python (easier than shell) -BINRELPATH = "${@os.path.relpath(d.expand("${STAGING_DIR_NATIVE}${prefix_native}/bin/${TARGET_SYS}"), d.expand("${libexecdir}/gcc/${TARGET_SYS}/${BINV}"))}" -# linker plugin path -LIBRELPATH = "${@os.path.relpath(d.expand("${libexecdir}/gcc/${TARGET_SYS}/${BINV}"), d.expand("${STAGING_LIBDIR_NATIVE}/${TARGET_SYS}/bfd-plugins"))}" - -do_install () { - ( cd ${B}/${TARGET_SYS}/libgcc; oe_runmake 'DESTDIR=${D}' install-unwind_h-forbuild install-unwind_h ) - oe_runmake 'DESTDIR=${D}' install-host - - install -d ${D}${target_base_libdir} - install -d ${D}${target_libdir} - - # Link gfortran to g77 to satisfy not-so-smart configure or hard coded g77 - # gfortran is fully backwards compatible. This is a safe and practical solution. - if [ -n "${@d.getVar('FORTRAN')}" ]; then - ln -sf ${STAGING_DIR_NATIVE}${prefix_native}/bin/${TARGET_PREFIX}gfortran ${STAGING_DIR_NATIVE}${prefix_native}/bin/${TARGET_PREFIX}g77 || true - fortsymlinks="g77 gfortran" - fi - - # Insert symlinks into libexec so when tools without a prefix are searched for, the correct ones are - # found. These need to be relative paths so they work in different locations. - dest=${D}${libexecdir}/gcc/${TARGET_SYS}/${BINV}/ - install -d $dest - for t in ar as ld ld.bfd ld.gold nm objcopy objdump ranlib strip gcc cpp $fortsymlinks; do - ln -sf ${BINRELPATH}/${TARGET_PREFIX}$t $dest$t - ln -sf ${BINRELPATH}/${TARGET_PREFIX}$t ${dest}${TARGET_PREFIX}$t - done - - # Remove things we don't need but keep share/java - for d in info man share/doc share/locale share/man share/info; do - rm -rf ${D}${STAGING_DIR_NATIVE}${prefix_native}/$d - done - - # libquadmath headers need to be available in the gcc libexec dir - install -d ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ - cp ${S}/libquadmath/quadmath.h ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ - cp ${S}/libquadmath/quadmath_weak.h ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ - - find ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include-fixed -type f -not -name "README" -not -name limits.h -not -name syslimits.h | xargs rm -f - - # install LTO linker plugins where binutils tools can find it - install -d ${D}${libdir}/bfd-plugins - ln -sf ${LIBRELPATH}/liblto_plugin.so ${D}${libdir}/bfd-plugins/liblto_plugin.so -} - -do_package[noexec] = "1" -do_packagedata[noexec] = "1" -do_package_write_ipk[noexec] = "1" -do_package_write_rpm[noexec] = "1" -do_package_write_deb[noexec] = "1" - -inherit chrpath - -python gcc_stash_builddir_fixrpaths() { - # rewrite rpaths, breaking hardlinks as required - process_dir("/", d.getVar("BUILDDIRSTASH"), d, break_hardlinks = True) -} - -BUILDDIRSTASH = "${WORKDIR}/stashed-builddir/build" -do_gcc_stash_builddir[dirs] = "${B}" -do_gcc_stash_builddir[cleandirs] = "${BUILDDIRSTASH}" -do_gcc_stash_builddir[postfuncs] += "gcc_stash_builddir_fixrpaths" -do_gcc_stash_builddir () { - dest=${BUILDDIRSTASH} - hardlinkdir . $dest - # Makefile does move-if-change which can end up with 'timestamp' as file contents so break links to those files - rm $dest/gcc/include/*.h - cp gcc/include/*.h $dest/gcc/include/ - sysroot-relativelinks.py $dest -} -addtask do_gcc_stash_builddir after do_compile before do_install -SSTATETASKS += "do_gcc_stash_builddir" -do_gcc_stash_builddir[sstate-inputdirs] = "${BUILDDIRSTASH}" -do_gcc_stash_builddir[sstate-outputdirs] = "${COMPONENTS_DIR}/${BUILD_ARCH}/gcc-stashed-builddir-${TARGET_SYS}" -do_gcc_stash_builddir[sstate-fixmedir] = "${COMPONENTS_DIR}/${BUILD_ARCH}/gcc-stashed-builddir-${TARGET_SYS}" - -python do_gcc_stash_builddir_setscene () { - sstate_setscene(d) -} -addtask do_gcc_stash_builddir_setscene diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-cross_12.2.bb b/meta-microblaze/recipes-devtools/gcc/gcc-cross_12.2.bb deleted file mode 100644 index b43cca0c..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-cross_12.2.bb +++ /dev/null @@ -1,3 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require gcc-cross.inc - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-cross_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-cross_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-cross_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk.inc b/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk.inc deleted file mode 100644 index bd65b1fe..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk.inc +++ /dev/null @@ -1,12 +0,0 @@ -inherit crosssdk - -PN = "gcc-crosssdk-${SDK_SYS}" - -SYSTEMHEADERS = "${SDKPATHNATIVE}${prefix_nativesdk}/include" -SYSTEMLIBS = "${SDKPATHNATIVE}${base_libdir_nativesdk}/" -SYSTEMLIBS1 = "${SDKPATHNATIVE}${libdir_nativesdk}/" - -GCCMULTILIB = "--disable-multilib" - -DEPENDS = "virtual/${TARGET_PREFIX}binutils gettext-native ${NATIVEDEPS}" -PROVIDES = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk_12.2.bb b/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk_12.2.bb deleted file mode 100644 index 40a6c4fe..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk_12.2.bb +++ /dev/null @@ -1,2 +0,0 @@ -require recipes-devtools/gcc/gcc-cross_${PV}.bb -require gcc-crosssdk.inc diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-crosssdk_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-multilib-config.inc b/meta-microblaze/recipes-devtools/gcc/gcc-multilib-config.inc deleted file mode 100644 index 2dbbc23c..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-multilib-config.inc +++ /dev/null @@ -1,249 +0,0 @@ -# following code modifies these definitions in the gcc config -# MULTILIB_OPTIONS -# MULTILIB_DIRNAMES -# MULTILIB_OSDIRNAMES -# GLIBC_DYNAMIC_LINKER32 -# GLIBC_DYNAMIC_LINKER64 -# GLIBC_DYNAMIC_LINKERX32 -# GLIBC_DYNAMIC_LINKERN32 -# For more information on use of these variables look at these files in the gcc source code -# gcc/config/i386/t-linux64 -# gcc/config/mips/t-linux64 -# gcc/config/rs6000/t-linux64 -# gcc/config/i386/linux64.h -# gcc/config/mips/linux64.h -# gcc/config/rs6000/linux64.h - -MULTILIB_OPTION_WHITELIST ??= "-m32 -m64 -mx32 -mabi=n32 -mabi=32 -mabi=64" - -python gcc_multilib_setup() { - import re - import shutil - import glob - - srcdir = d.getVar('S') - builddir = d.getVar('B') - src_conf_dir = '%s/gcc/config' % srcdir - build_conf_dir = '%s/gcc/config' % builddir - - bb.utils.remove(build_conf_dir, True) - ml_globs = ('%s/*/t-linux64' % src_conf_dir, - '%s/*/linux64.h' % src_conf_dir, - '%s/aarch64/t-aarch64' % src_conf_dir, - '%s/aarch64/aarch64.h' % src_conf_dir, - '%s/aarch64/aarch64-linux.h' % src_conf_dir, - '%s/aarch64/aarch64-cores.def' % src_conf_dir, - '%s/arm/linux-eabi.h' % src_conf_dir, - '%s/*/linux.h' % src_conf_dir, - '%s/linux.h' % src_conf_dir) - - # copy the target multilib config files to ${B} - for ml_glob in ml_globs: - for fn in glob.glob(ml_glob): - rel_path = os.path.relpath(fn, src_conf_dir) - parent_dir = os.path.dirname(rel_path) - bb.utils.mkdirhier('%s/%s' % (build_conf_dir, parent_dir)) - bb.utils.copyfile(fn, '%s/%s' % (build_conf_dir, rel_path)) - - pn = d.getVar('PN') - multilibs = (d.getVar('MULTILIB_VARIANTS') or '').split() - if not multilibs and pn != "nativesdk-gcc": - return - - mlprefix = d.getVar('MLPREFIX') - - if ('%sgcc' % mlprefix) != pn and (not pn.startswith('gcc-cross-canadian')) and pn != "nativesdk-gcc": - return - - - def write_config(root, files, options, dirnames, osdirnames): - for ml_conf_file in files: - with open(root + '/' + ml_conf_file, 'r') as f: - filelines = f.readlines() - # recreate multilib configuration variables - substs = [ - (r'^(\s*(MULTILIB_OPTIONS\s*=).*)$', r'\2 %s' % '/'.join(options)), - (r'^(\s*MULTILIB_OPTIONS\s*\+=.*)$', ''), - (r'^(\s*(MULTILIB_DIRNAMES\s*=).*)$', r'\2 %s' % ' '.join(dirnames)), - (r'^(\s*MULTILIB_DIRNAMES\s*\+=.*)$', ''), - (r'^(\s*(MULTILIB_OSDIRNAMES\s*=).*)$', r'\2 %s' % ' '.join(osdirnames)), - (r'^(\s*MULTILIB_OSDIRNAMES\s*\+=.*)$', ''), - ] - - for (i, line) in enumerate(filelines): - for subst in substs: - line = re.sub(subst[0], subst[1], line) - filelines[i] = line - - with open(root + '/' + ml_conf_file, 'w') as f: - f.write(''.join(filelines)) - - def write_headers(root, files, libdir32, libdir64, libdirx32, libdirn32): - def wrap_libdir(libdir): - if libdir.find('SYSTEMLIBS_DIR') != -1: - return '"%r"' - else: - return '"/%s/"' % libdir - - for ml_conf_file in files: - fn = root + '/' + ml_conf_file - if not os.path.exists(fn): - continue - with open(fn, 'r') as f: - filelines = f.readlines() - - # replace lines like - # #define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-linux.so.2" - # by - # #define GLIBC_DYNAMIC_LINKER32 "/lib/" "ld-linux.so.2" - # this is needed to put the correct dynamic loader path in the generated binaries - substs = [ - (r'^(#define\s*GLIBC_DYNAMIC_LINKER32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir32) + r'\3'), - (r'^(#define\s*GLIBC_DYNAMIC_LINKER64\s*)(\S+)(\s*\"\S+\")$', - r'\1' + wrap_libdir(libdir64) + r'\3'), - (r'^(#define\s*GLIBC_DYNAMIC_LINKER64\s*\"\S+\"\s*)(\S+)(\s*\"\S+\"\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir64) + r'\3' + wrap_libdir(libdir64) + r'\5'), - (r'^(#define\s*GLIBC_DYNAMIC_LINKER\b\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir32) + r'\3'), - (r'^(#define\s*GLIBC_DYNAMIC_LINKERX32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdirx32) + r'\3'), - (r'^(#define\s*GLIBC_DYNAMIC_LINKERN32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdirn32) + r'\3'), - (r'^(#define\s*UCLIBC_DYNAMIC_LINKER32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir32) + r'\3'), - (r'^(#define\s*UCLIBC_DYNAMIC_LINKER64\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir64) + r'\3'), - (r'^(#define\s*UCLIBC_DYNAMIC_LINKERN32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdirn32) + r'\3'), - (r'^(#define\s*UCLIBC_DYNAMIC_LINKERX32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdirx32) + r'\3'), - (r'^(#define\s*UCLIBC_DYNAMIC_LINKER\b\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir32) + r'\3'), - (r'^(#define\s*MUSL_DYNAMIC_LINKER32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir32) + r'\3'), - (r'^(#define\s*MUSL_DYNAMIC_LINKER64\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir64) + r'\3'), - (r'^(#define\s*MUSL_DYNAMIC_LINKERX32\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdirx32) + r'\3'), - (r'^(#define\s*MUSL_DYNAMIC_LINKER\b\s*)(\S+)(\s*\".*\")$', - r'\1' + wrap_libdir(libdir32) + r'\3'), - ] - - for (i, line) in enumerate(filelines): - for subst in substs: - line = re.sub(subst[0], subst[1], line) - filelines[i] = line - - with open(root + '/' + ml_conf_file, 'w') as f: - f.write(''.join(filelines)) - - - gcc_target_config_files = { - 'x86_64' : ['gcc/config/i386/t-linux64'], - 'i586' : ['gcc/config/i386/t-linux64'], - 'i686' : ['gcc/config/i386/t-linux64'], - 'mips' : ['gcc/config/mips/t-linux64'], - 'mips64' : ['gcc/config/mips/t-linux64'], - 'powerpc' : ['gcc/config/rs6000/t-linux64'], - 'powerpc64' : ['gcc/config/rs6000/t-linux64'], - 'aarch64' : ['gcc/config/aarch64/t-aarch64'], - 'arm' : ['gcc/config/aarch64/t-aarch64'], - } - - gcc_header_config_files = { - 'x86_64' : ['gcc/config/linux.h', 'gcc/config/i386/linux.h', 'gcc/config/i386/linux64.h'], - 'i586' : ['gcc/config/linux.h', 'gcc/config/i386/linux.h', 'gcc/config/i386/linux64.h'], - 'i686' : ['gcc/config/linux.h', 'gcc/config/i386/linux.h', 'gcc/config/i386/linux64.h'], - 'mips' : ['gcc/config/linux.h', 'gcc/config/mips/linux.h', 'gcc/config/mips/linux64.h'], - 'mips64' : ['gcc/config/linux.h', 'gcc/config/mips/linux.h', 'gcc/config/mips/linux64.h'], - 'powerpc' : ['gcc/config/linux.h', 'gcc/config/rs6000/linux64.h'], - 'powerpc64' : ['gcc/config/linux.h', 'gcc/config/rs6000/linux64.h'], - 'aarch64' : ['gcc/config/linux.h', 'gcc/config/aarch64/aarch64-linux.h', 'gcc/config/arm/linux-eabi.h'], - 'arm' : ['gcc/config/linux.h', 'gcc/config/aarch64/aarch64-linux.h', 'gcc/config/arm/linux-eabi.h'], - } - - libdir32 = 'SYSTEMLIBS_DIR' - libdir64 = 'SYSTEMLIBS_DIR' - libdirx32 = 'SYSTEMLIBS_DIR' - libdirn32 = 'SYSTEMLIBS_DIR' - - - target_arch = (d.getVar('TARGET_ARCH_MULTILIB_ORIGINAL') if mlprefix - else d.getVar('TARGET_ARCH')) - if pn == "nativesdk-gcc": - header_config_files = gcc_header_config_files[d.getVar("SDK_ARCH")] - write_headers(builddir, header_config_files, libdir32, libdir64, libdirx32, libdirn32) - return - - if target_arch not in gcc_target_config_files: - bb.warn('gcc multilib setup is not supported for TARGET_ARCH=' + target_arch) - return - - target_config_files = gcc_target_config_files[target_arch] - header_config_files = gcc_header_config_files[target_arch] - - ml_list = ['DEFAULTTUNE_MULTILIB_ORIGINAL' if mlprefix else 'DEFAULTTUNE'] - mltunes = [('DEFAULTTUNE:virtclass-multilib-%s' % ml) for ml in multilibs] - if mlprefix: - mlindex = 0 - for ml in multilibs: - if mlprefix == ml + '-': - break - mlindex += 1 - - ml_list.extend(mltunes[:mlindex] + ['DEFAULTTUNE'] + mltunes[(mlindex + 1):]) - else: - ml_list.extend(mltunes) - - options = [] - dirnames = [] - osdirnames = [] - optsets = [] - - for ml in ml_list: - tune = d.getVar(ml) - if not tune: - bb.warn("%s doesn't have a corresponding tune. Skipping..." % ml) - continue - tune_parameters = get_tune_parameters(tune, d) - - tune_baselib = tune_parameters['baselib'] - if not tune_baselib: - bb.warn("Tune %s doesn't have a baselib set. Skipping..." % tune) - continue - - if tune_baselib == 'lib64': - libdir64 = tune_baselib - elif tune_baselib == 'libx32': - libdirx32 = tune_baselib - elif tune_baselib == 'lib32': - libdirn32 = tune_baselib - elif tune_baselib == 'lib': - libdir32 = tune_baselib - else: - bb.error('Unknown libdir (%s) of the tune : %s' % (tune_baselib, tune)) - - # take out '-' mcpu='s and march='s from parameters - opts = [] - whitelist = (d.getVar("MULTILIB_OPTION_WHITELIST") or "").split() - for i in d.expand(tune_parameters['ccargs']).split(): - if i in whitelist: - # Need to strip '-' from option - opts.append(i[1:]) - options.append(" ".join(opts)) - - if tune_baselib == 'lib': - dirnames.append('32') # /lib => 32bit lib - else: - dirnames.append(tune_baselib.replace('lib', '')) - osdirnames.append('../' + tune_baselib) - - write_config(builddir, target_config_files, options, dirnames, osdirnames) - write_headers(builddir, header_config_files, libdir32, libdir64, libdirx32, libdirn32) -} - -gcc_multilib_setup[cleandirs] = "${B}/gcc/config" -gcc_multilib_setup[vardepsexclude] = "SDK_ARCH" - -EXTRACONFFUNCS += "gcc_multilib_setup" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-runtime.inc b/meta-microblaze/recipes-devtools/gcc/gcc-runtime.inc deleted file mode 100644 index 8bb58631..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-runtime.inc +++ /dev/null @@ -1,310 +0,0 @@ -require gcc-configure-common.inc - -SUMMARY = "Runtime libraries from GCC" - -# Over-ride the LICENSE set by gcc-${PV}.inc to remove "& GPLv3" -# All gcc-runtime packages are now covered by the runtime exception. -LICENSE = "GPL-3.0-with-GCC-exception" - -CXXFLAGS:remove = "-fvisibility-inlines-hidden" - -EXTRA_OECONF_PATHS = "\ - --with-gxx-include-dir=${includedir}/c++/${BINV} \ - --with-sysroot=/not/exist \ - --with-build-sysroot=${STAGING_DIR_TARGET} \ -" - -EXTRA_OECONF:append:linuxstdbase = " --enable-clocale=gnu" -EXTRA_OECONF:append = " --cache-file=${B}/config.cache" -EXTRA_OECONF:append:libc-newlib = " --with-newlib --with-target-subdir" -EXTRA_OECONF:append:libc-baremetal = " --with-target-subdir" - -# Disable ifuncs for libatomic on arm conflicts -march/-mcpu -EXTRA_OECONF:append:arm = " libat_cv_have_ifunc=no " -EXTRA_OECONF:append:armeb = " libat_cv_have_ifunc=no " - -DISABLE_STATIC:class-nativesdk ?= "" - -# Newlib does not support symbol versioning on libsdtcc++ -SYMVERS_CONF:libc-newlib = "" - -# Building with thumb enabled on armv6t fails -ARM_INSTRUCTION_SET:armv6 = "arm" - -RUNTIMELIBITM = "libitm" -RUNTIMELIBITM:arc = "" -RUNTIMELIBITM:mipsarch = "" -RUNTIMELIBITM:nios2 = "" -RUNTIMELIBITM:microblaze = "" -RUNTIMELIBITM:riscv32 = "" -RUNTIMELIBITM:riscv64 = "" -RUNTIMELIBITM:loongarch64 = "" -RUNTIMELIBSSP ?= "" -RUNTIMELIBSSP:mingw32 ?= "libssp" - -RUNTIMETARGET = "${RUNTIMELIBSSP} libstdc++-v3 libgomp libatomic ${RUNTIMELIBITM} \ - ${@bb.utils.contains_any('FORTRAN', [',fortran',',f77'], 'libquadmath', '', d)} \ -" -# Only build libstdc++ for newlib -RUNTIMETARGET:libc-newlib = "libstdc++-v3" - -# libiberty -# libgfortran needs separate recipe due to libquadmath dependency - -do_configure () { - export CXX="${CXX} -nostdinc++ -L${WORKDIR}/dummylib" - # libstdc++ isn't built yet so CXX would error not able to find it which breaks stdc++'s configure - # tests. Create a dummy empty lib for the purposes of configure. - mkdir -p ${WORKDIR}/dummylib - ${CC} -x c /dev/null -c -o ${WORKDIR}/dummylib/dummylib.o - ${AR} rcs ${WORKDIR}/dummylib/libstdc++.a ${WORKDIR}/dummylib/dummylib.o - for d in libgcc ${RUNTIMETARGET}; do - echo "Configuring $d" - rm -rf ${B}/${TARGET_SYS}/$d/ - mkdir -p ${B}/${TARGET_SYS}/$d/ - cd ${B}/${TARGET_SYS}/$d/ - chmod a+x ${S}/$d/configure - ${S}/$d/configure ${CONFIGUREOPTS} ${EXTRA_OECONF} - if [ "$d" = "libgcc" ]; then - (cd ${B}/${TARGET_SYS}/libgcc; oe_runmake enable-execute-stack.c unwind.h md-unwind-support.h sfp-machine.h gthr-default.h) - fi - done -} -EXTRACONFFUNCS += "extract_stashed_builddir" -do_configure[depends] += "${COMPILERDEP}" - -do_compile () { - for d in libgcc ${RUNTIMETARGET}; do - cd ${B}/${TARGET_SYS}/$d/ - oe_runmake MULTIBUILDTOP=${B}/${TARGET_SYS}/$d/ - done -} - -do_install () { - for d in ${RUNTIMETARGET}; do - cd ${B}/${TARGET_SYS}/$d/ - oe_runmake 'DESTDIR=${D}' MULTIBUILDTOP=${B}/${TARGET_SYS}/$d/ install - done - if [ -d ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include ]; then - install -d ${D}${libdir}/${TARGET_SYS}/${BINV}/include - mv ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/* ${D}${libdir}/${TARGET_SYS}/${BINV}/include - rmdir --ignore-fail-on-non-empty -p ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include - fi - rm -rf ${D}${infodir}/libgomp.info ${D}${infodir}/dir - rm -rf ${D}${infodir}/libitm.info ${D}${infodir}/dir - rm -rf ${D}${infodir}/libquadmath.info ${D}${infodir}/dir - if [ -d ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/finclude ]; then - rmdir --ignore-fail-on-non-empty -p ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/finclude - fi - if [ -d ${D}${infodir} ]; then - rmdir --ignore-fail-on-non-empty -p ${D}${infodir} - fi -} - -do_install:append:class-target () { - if [ "${TARGET_OS}" = "linux-gnuspe" ]; then - ln -s ${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-linux - fi - - if [ "${TARGET_OS}" = "linux-gnun32" ]; then - if [ "${TARGET_VENDOR_MULTILIB_ORIGINAL}" != "" -a "${TARGET_VENDOR}" != "${TARGET_VENDOR_MULTILIB_ORIGINAL}" ]; then - mkdir ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR_MULTILIB_ORIGINAL}-linux - ln -s ../${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR_MULTILIB_ORIGINAL}-linux/32 - elif [ "${MULTILIB_VARIANTS}" != "" ]; then - mkdir ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-linux - ln -s ../${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-linux/32 - else - ln -s ${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-linux - fi - elif [ "${TARGET_OS}" = "linux-gnux32" ]; then - if [ "${TARGET_VENDOR_MULTILIB_ORIGINAL}" != "" -a "${TARGET_VENDOR}" != "${TARGET_VENDOR_MULTILIB_ORIGINAL}" ]; then - mkdir ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR_MULTILIB_ORIGINAL}-linux - ln -s ../${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR_MULTILIB_ORIGINAL}-linux/x32 - elif [ "${MULTILIB_VARIANTS}" != "" ]; then - mkdir ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-linux - ln -s ../${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-linux/32 - else - ln -s ${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-linux - fi - elif [ "${TARGET_VENDOR_MULTILIB_ORIGINAL}" != "" -a "${TARGET_VENDOR}" != "${TARGET_VENDOR_MULTILIB_ORIGINAL}" ]; then - mkdir ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR_MULTILIB_ORIGINAL}-${TARGET_OS} - ln -s ../${TARGET_SYS}/bits ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR_MULTILIB_ORIGINAL}-${TARGET_OS}/bits - ln -s ../${TARGET_SYS}/ext ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR_MULTILIB_ORIGINAL}-${TARGET_OS}/ext - fi - - if [ "${TARGET_ARCH}" == "x86_64" -a "${MULTILIB_VARIANTS}" != "" ];then - ln -sf ../${X86ARCH32}${TARGET_VENDOR}-${TARGET_OS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-${TARGET_OS}/32 - fi - - if [ "${TCLIBC}" != "glibc" ]; then - case "${TARGET_OS}" in - "linux-musl" | "linux-*spe") extra_target_os="linux";; - "linux-musleabi") extra_target_os="linux-gnueabi";; - *) extra_target_os="linux";; - esac - ln -s ${TARGET_SYS} ${D}${includedir}/c++/${BINV}/${TARGET_ARCH}${TARGET_VENDOR}-$extra_target_os - fi - chown -R root:root ${D} -} - -INHIBIT_DEFAULT_DEPS = "1" -DEPENDS = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++ libgcc virtual/${MLPREFIX}libc" -PROVIDES = "virtual/${TARGET_PREFIX}compilerlibs" - -#BBCLASSEXTEND = "nativesdk" - -PACKAGES = "\ - ${PN}-dbg \ - libstdc++ \ - libstdc++-precompile-dev \ - libstdc++-dev \ - libstdc++-staticdev \ - libg2c \ - libg2c-dev \ - libssp \ - libssp-dev \ - libssp-staticdev \ - libquadmath \ - libquadmath-dev \ - libquadmath-staticdev \ - libgomp \ - libgomp-dev \ - libgomp-staticdev \ - libatomic \ - libatomic-dev \ - libatomic-staticdev \ - libitm \ - libitm-dev \ - libitm-staticdev \ -" -# The base package doesn't exist, so we clear the recommends. -RRECOMMENDS:${PN}-dbg = "" - -# include python debugging scripts -FILES:${PN}-dbg += "\ - ${libdir}/libstdc++.*-gdb.py \ - ${datadir}/gcc-${BINV}/python/libstdcxx \ -" - -FILES:libg2c = "${target_libdir}/libg2c.so.*" -SUMMARY:libg2c = "Companion runtime library for g77" -FILES:libg2c-dev = "\ - ${libdir}/libg2c.so \ - ${libdir}/libg2c.a \ - ${libdir}/libfrtbegin.a \ -" -SUMMARY:libg2c-dev = "Companion runtime library for g77 - development files" - -FILES:libstdc++ = "${libdir}/libstdc++.so.*" -SUMMARY:libstdc++ = "GNU standard C++ library" -FILES:libstdc++-dev = "\ - ${includedir}/c++/ \ - ${libdir}/libstdc++.so \ - ${libdir}/libstdc++*.la \ - ${libdir}/libsupc++.la \ -" -SUMMARY:libstdc++-dev = "GNU standard C++ library - development files" -FILES:libstdc++-staticdev = "\ - ${libdir}/libstdc++*.a \ - ${libdir}/libsupc++.a \ -" -SUMMARY:libstdc++-staticdev = "GNU standard C++ library - static development files" - -FILES:libstdc++-precompile-dev = "${includedir}/c++/${TARGET_SYS}/bits/*.gch" -SUMMARY:libstdc++-precompile-dev = "GNU standard C++ library - precompiled header files" - -FILES:libssp = "${libdir}/libssp.so.*" -SUMMARY:libssp = "GNU stack smashing protection library" -FILES:libssp-dev = "\ - ${libdir}/libssp*.so \ - ${libdir}/libssp*_nonshared.a \ - ${libdir}/libssp*.la \ - ${libdir}/${TARGET_SYS}/${BINV}/include/ssp \ -" -SUMMARY:libssp-dev = "GNU stack smashing protection library - development files" -FILES:libssp-staticdev = "${libdir}/libssp*.a" -SUMMARY:libssp-staticdev = "GNU stack smashing protection library - static development files" - -FILES:libquadmath = "${libdir}/libquadmath*.so.*" -SUMMARY:libquadmath = "GNU quad-precision math library" -FILES:libquadmath-dev = "\ - ${libdir}/${TARGET_SYS}/${BINV}/include/quadmath* \ - ${libdir}/libquadmath*.so \ - ${libdir}/libquadmath.la \ -" -SUMMARY:libquadmath-dev = "GNU quad-precision math library - development files" -FILES:libquadmath-staticdev = "${libdir}/libquadmath.a" -SUMMARY:libquadmath-staticdev = "GNU quad-precision math library - static development files" - -FILES:libgomp = "${libdir}/libgomp*${SOLIBS}" -SUMMARY:libgomp = "GNU OpenMP parallel programming library" -FILES:libgomp-dev = "\ - ${libdir}/libgomp*${SOLIBSDEV} \ - ${libdir}/libgomp*.la \ - ${libdir}/libgomp.spec \ - ${libdir}/${TARGET_SYS}/${BINV}/include/acc_prof.h \ - ${libdir}/${TARGET_SYS}/${BINV}/include/omp.h \ - ${libdir}/${TARGET_SYS}/${BINV}/include/openacc.h \ -" -SUMMARY:libgomp-dev = "GNU OpenMP parallel programming library - development files" -FILES:libgomp-staticdev = "${libdir}/libgomp*.a" -SUMMARY:libgomp-staticdev = "GNU OpenMP parallel programming library - static development files" - -FILES:libatomic = "${libdir}/libatomic.so.*" -SUMMARY:libatomic = "GNU C++11 atomics support library" -FILES:libatomic-dev = "\ - ${libdir}/libatomic.so \ - ${libdir}/libatomic.la \ -" -SUMMARY:libatomic-dev = "GNU C++11 atomics support library - development files" -FILES:libatomic-staticdev = "${libdir}/libatomic.a" -SUMMARY:libatomic-staticdev = "GNU C++11 atomics support library - static development files" - -FILES:libitm = "${libdir}/libitm.so.*" -SUMMARY:libitm = "GNU transactional memory support library" -FILES:libitm-dev = "\ - ${libdir}/libitm.so \ - ${libdir}/libitm.la \ - ${libdir}/libitm.spec \ -" -SUMMARY:libitm-dev = "GNU transactional memory support library - development files" -FILES:libitm-staticdev = "${libdir}/libitm.a" -SUMMARY:libitm-staticdev = "GNU transactional memory support library - static development files" - -require gcc-testsuite.inc - -EXTRA_OEMAKE:prepend:task-check = "${PARALLEL_MAKE} " - -MAKE_CHECK_TARGETS ??= "check-gcc ${@" ".join("check-target-" + i for i in d.getVar("RUNTIMETARGET").split())}" -# prettyprinters and xmethods require gdb tooling -MAKE_CHECK_IGNORE ??= "prettyprinters.exp xmethods.exp" -MAKE_CHECK_RUNTESTFLAGS ??= "${MAKE_CHECK_BOARDARGS} --ignore '${MAKE_CHECK_IGNORE}'" - -# specific host and target dependencies required for test suite running -do_check[depends] += "dejagnu-native:do_populate_sysroot expect-native:do_populate_sysroot" -do_check[depends] += "virtual/libc:do_populate_sysroot" -# only depend on qemu if targeting linux user execution -do_check[depends] += "${@'qemu-native:do_populate_sysroot' if "user" in d.getVar('TOOLCHAIN_TEST_TARGET') else ''}" -# extend the recipe sysroot to include the built libraries (for qemu usermode) -do_check[prefuncs] += "extend_recipe_sysroot" -do_check[prefuncs] += "check_prepare" -do_check[dirs] = "${WORKDIR}/dejagnu ${B}" -do_check[nostamp] = "1" -do_check() { - export DEJAGNU="${WORKDIR}/dejagnu/site.exp" - - # HACK: this works around the configure setting CXX with -nostd* args - sed -i 's#-nostdinc++ -L${WORKDIR}/dummylib##g' $(find ${B} -name testsuite_flags | head -1) - - if [ "${TOOLCHAIN_TEST_TARGET}" = "user" ]; then - # qemu user has issues allocating large amounts of memory - export G_SLICE=always-malloc - # no test should need more that 10G of memory, this prevents tests like pthread7-rope from leaking memory - ulimit -m 4194304 - ulimit -v 10485760 - fi - - oe_runmake -i ${MAKE_CHECK_TARGETS} RUNTESTFLAGS="${MAKE_CHECK_RUNTESTFLAGS}" -} -addtask check after do_compile do_populate_sysroot - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-runtime_12.2.bb b/meta-microblaze/recipes-devtools/gcc/gcc-runtime_12.2.bb deleted file mode 100644 index dd430b57..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-runtime_12.2.bb +++ /dev/null @@ -1,2 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require gcc-runtime.inc diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-runtime_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-runtime_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-runtime_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers.inc b/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers.inc deleted file mode 100644 index f6aa9c99..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers.inc +++ /dev/null @@ -1,120 +0,0 @@ -require gcc-configure-common.inc - -LICENSE = "NCSA | MIT" - -LIC_FILES_CHKSUM = "\ - file://libsanitizer/LICENSE.TXT;md5=0249c37748936faf5b1efd5789587909 \ -" - -EXTRA_OECONF_PATHS = "\ - --with-sysroot=/not/exist \ - --with-build-sysroot=${STAGING_DIR_TARGET} \ -" - -do_configure () { - rm -rf ${B}/${TARGET_SYS}/libsanitizer/ - mkdir -p ${B}/${TARGET_SYS}/libsanitizer/ - cd ${B}/${TARGET_SYS}/libsanitizer/ - chmod a+x ${S}/libsanitizer/configure - relpath=${@os.path.relpath("${S}/libsanitizer", "${B}/${TARGET_SYS}/libsanitizer")} - $relpath/configure ${CONFIGUREOPTS} ${EXTRA_OECONF} - # Easiest way to stop bad RPATHs getting into the library since we have a - # broken libtool here - sed -i -e 's/hardcode_into_libs=yes/hardcode_into_libs=no/' ${B}/${TARGET_SYS}/libsanitizer/libtool - # Link to the sysroot's libstdc++ instead of one gcc thinks it just built - sed -i -e '/LIBSTDCXX_RAW_CXX_\(CXXFLAGS\|LDFLAGS\)\s*=/d' ${B}/${TARGET_SYS}/libsanitizer/*/Makefile -} -EXTRACONFFUNCS += "extract_stashed_builddir" -do_configure[depends] += "${COMPILERDEP}" - -do_compile () { - cd ${B}/${TARGET_SYS}/libsanitizer/ - oe_runmake MULTIBUILDTOP=${B}/${TARGET_SYS}/libsanitizer/ -} - -do_install () { - cd ${B}/${TARGET_SYS}/libsanitizer/ - oe_runmake 'DESTDIR=${D}' MULTIBUILDTOP=${B}/${TARGET_SYS}/libsanitizer/ install - if [ -d ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include ]; then - install -d ${D}${libdir}/${TARGET_SYS}/${BINV}/include - mv ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/* ${D}${libdir}/${TARGET_SYS}/${BINV}/include - rmdir --ignore-fail-on-non-empty -p ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include - fi - if [ -d ${D}${infodir} ]; then - rmdir --ignore-fail-on-non-empty -p ${D}${infodir} - fi - chown -R root:root ${D} -} - -INHIBIT_DEFAULT_DEPS = "1" -ALLOW_EMPTY:${PN} = "1" -DEPENDS = "virtual/crypt gcc-runtime virtual/${TARGET_PREFIX}gcc" - -# used to fix ../../../../../../../../../work-shared/gcc-8.3.0-r0/gcc-8.3.0/libsanitizer/libbacktrace/../../libbacktrace/elf.c:772:21: error: 'st.st_mode' may be used uninitialized in this function [-Werror=maybe-uninitialized] -DEBUG_OPTIMIZATION:append = " -Wno-error" - -#BBCLASSEXTEND = "nativesdk" - -PACKAGES = "${PN} ${PN}-dbg" -PACKAGES += "libasan libubsan liblsan libtsan" -PACKAGES += "libasan-dev libubsan-dev liblsan-dev libtsan-dev" -PACKAGES += "libasan-staticdev libubsan-staticdev liblsan-staticdev libtsan-staticdev" - -RDEPENDS:libasan += "libstdc++" -RDEPENDS:libubsan += "libstdc++" -RDEPENDS:liblsan += "libstdc++" -RDEPENDS:libtsan += "libstdc++" -RDEPENDS:libasan-dev += "${PN}" -RDEPENDS:libubsan-dev += "${PN}" -RDEPENDS:liblsan-dev += "${PN}" -RDEPENDS:libtsan-dev += "${PN}" -RRECOMMENDS:${PN} += "libasan libubsan" -RRECOMMENDS:${PN}:append:x86 = " liblsan" -RRECOMMENDS:${PN}:append:x86-64 = " liblsan libtsan" -RRECOMMENDS:${PN}:append:powerpc64 = " liblsan libtsan" -RRECOMMENDS:${PN}:append:aarch64 = " liblsan libtsan" - -do_package_write_ipk[depends] += "virtual/${MLPREFIX}${TARGET_PREFIX}compilerlibs:do_packagedata" -do_package_write_deb[depends] += "virtual/${MLPREFIX}${TARGET_PREFIX}compilerlibs:do_packagedata" -do_package_write_rpm[depends] += "virtual/${MLPREFIX}${TARGET_PREFIX}compilerlibs:do_packagedata" - -# Only x86, powerpc, sparc, s390, arm, and aarch64 are supported -COMPATIBLE_HOST = '(x86_64|i.86|powerpc|sparc|s390|arm|aarch64).*-linux' -# musl is currently broken entirely -COMPATIBLE_HOST:libc-musl = 'null' - -FILES:libasan += "${libdir}/libasan.so.* ${libdir}/libhwasan.so.*" -FILES:libasan-dev += "\ - ${libdir}/libasan_preinit.o \ - ${libdir}/libasan.so \ - ${libdir}/libhwasan.so \ - ${libdir}/libasan.la \ -" -FILES:libasan-staticdev += "${libdir}/libasan.a \ - ${libdir}/libhwasan.a \ -" - -FILES:libubsan += "${libdir}/libubsan.so.*" -FILES:libubsan-dev += "\ - ${libdir}/libubsan.so \ - ${libdir}/libubsan.la \ -" -FILES:libubsan-staticdev += "${libdir}/libubsan.a" - -FILES:liblsan += "${libdir}/liblsan.so.*" -FILES:liblsan-dev += "\ - ${libdir}/liblsan.so \ - ${libdir}/liblsan.la \ - ${libdir}/liblsan_preinit.o \ -" -FILES:liblsan-staticdev += "${libdir}/liblsan.a" - -FILES:libtsan += "${libdir}/libtsan.so.*" -FILES:libtsan-dev += "\ - ${libdir}/libtsan.so \ - ${libdir}/libtsan.la \ - ${libdir}/libtsan_*.o \ -" -FILES:libtsan-staticdev += "${libdir}/libtsan.a" - -FILES:${PN} = "${libdir}/*.spec ${libdir}/${TARGET_SYS}/${BINV}/include/sanitizer/*.h" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers_12.2.bb b/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers_12.2.bb deleted file mode 100644 index 8bda2cca..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers_12.2.bb +++ /dev/null @@ -1,7 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require gcc-sanitizers.inc - -# Building with thumb enabled on armv4t armv5t fails with -# sanitizer_linux.s:5749: Error: lo register required -- `ldr ip,[sp],#8' -ARM_INSTRUCTION_SET:armv4 = "arm" -ARM_INSTRUCTION_SET:armv5 = "arm" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-sanitizers_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-shared-source.inc b/meta-microblaze/recipes-devtools/gcc/gcc-shared-source.inc deleted file mode 100644 index 03f520b0..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-shared-source.inc +++ /dev/null @@ -1,21 +0,0 @@ -do_fetch() { - : -} -do_fetch[noexec] = "1" -deltask do_unpack -deltask do_patch - -SRC_URI = "" - -do_configure[depends] += "gcc-source-${PV}:do_preconfigure" -do_populate_lic[depends] += "gcc-source-${PV}:do_unpack" -do_deploy_source_date_epoch[depends] += "gcc-source-${PV}:do_deploy_source_date_epoch" - -# Copy the SDE from the shared workdir to the recipe workdir -do_deploy_source_date_epoch () { - sde_file=${SDE_FILE} - sde_file=${sde_file#${WORKDIR}/} - mkdir -p ${SDE_DEPLOYDIR} $(dirname ${SDE_FILE}) - cp -p $(dirname ${S})/$sde_file ${SDE_DEPLOYDIR} - cp -p $(dirname ${S})/$sde_file ${SDE_FILE} -} diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source.inc b/meta-microblaze/recipes-devtools/gcc/gcc-source.inc deleted file mode 100644 index 265bcf4b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-source.inc +++ /dev/null @@ -1,45 +0,0 @@ -deltask do_configure -deltask do_compile -deltask do_install -deltask do_populate_sysroot -deltask do_populate_lic -RM_WORK_EXCLUDE += "${PN}" - -inherit nopackages - -PN = "gcc-source-${PV}" -WORKDIR = "${TMPDIR}/work-shared/gcc-${PV}-${PR}" -SSTATE_SWSPEC = "sstate:gcc::${PV}:${PR}::${SSTATE_VERSION}:" - -STAMP = "${STAMPS_DIR}/work-shared/gcc-${PV}-${PR}" -STAMPCLEAN = "${STAMPS_DIR}/work-shared/gcc-${PV}-*" - -INHIBIT_DEFAULT_DEPS = "1" -DEPENDS = "" -PACKAGES = "" -TARGET_ARCH = "allarch" -TARGET_AS_ARCH = "none" -TARGET_CC_ARCH = "none" -TARGET_LD_ARCH = "none" -TARGET_OS = "linux" -baselib = "lib" -PACKAGE_ARCH = "all" - -B = "${WORKDIR}/build" - -# This needs to be Python to avoid lots of shell variables becoming dependencies. -python do_preconfigure () { - import subprocess - cmd = d.expand('cd ${S} && PATH=${PATH} gnu-configize') - subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=True) - cmd = d.expand("sed -i 's/BUILD_INFO=info/BUILD_INFO=/' ${S}/gcc/configure") - subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=True) - - # Easiest way to stop bad RPATHs getting into the library since we have a - # broken libtool here (breaks cross-canadian and target at least) - cmd = d.expand("sed -i -e 's/hardcode_into_libs=yes/hardcode_into_libs=no/' ${S}/libcc1/configure") - subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=True) -} -addtask do_preconfigure after do_patch -do_preconfigure[depends] += "gnu-config-native:do_populate_sysroot autoconf-native:do_populate_sysroot" - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_12.2.bb b/meta-microblaze/recipes-devtools/gcc/gcc-source_12.2.bb deleted file mode 100644 index b890fa33..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-source_12.2.bb +++ /dev/null @@ -1,4 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require recipes-devtools/gcc/gcc-source.inc - -EXCLUDE_FROM_WORLD = "1" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-target.inc b/meta-microblaze/recipes-devtools/gcc/gcc-target.inc deleted file mode 100644 index 7dac3ef4..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-target.inc +++ /dev/null @@ -1,259 +0,0 @@ -GCCMULTILIB = "--enable-multilib" -require gcc-configure-common.inc - -EXTRA_OECONF_PATHS = "\ - --with-build-sysroot=${STAGING_DIR_TARGET} \ -" - -EXTRA_OECONF:append:linuxstdbase = " --enable-clocale=gnu" - -# Configure gcc running on the target to default to an architecture which will -# be compatible with that of gcc-runtime (which is cross compiled to be target -# specific). For example, for ARM, ARMv6+ adds atomic instructions that may -# affect the ABI in the gcc-runtime libs. Since we can't rely on gcc on the -# target to always be passed -march etc, its built-in default needs to be safe. - -ARMFPARCHEXT ?= "" - -EXTRA_OECONF:append:armv6:class-target = " --with-arch=armv6${ARMFPARCHEXT}" -EXTRA_OECONF:append:armv7a:class-target = " --with-arch=armv7-a${ARMFPARCHEXT}" -EXTRA_OECONF:append:armv7ve:class-target = " --with-arch=armv7ve${ARMFPARCHEXT}" -EXTRA_OECONF:append:arc:class-target = " --with-cpu=${TUNE_PKGARCH}" -EXTRA_OECONF:append:x86-64:class-target = " ${@get_gcc_x86_64_arch_setting(bb, d)}" - -# libcc1 requres gcc_cv_objdump when cross build, but gcc_cv_objdump is -# set in subdir gcc, so subdir libcc1 can't use it, export it here to -# fix the problem. -export gcc_cv_objdump = "${TARGET_PREFIX}objdump" - -EXTRA_OECONF_GCC_FLOAT = "${@get_gcc_float_setting(bb, d)}" - -PACKAGES = "\ - ${PN} ${PN}-plugins ${PN}-symlinks \ - g++ g++-symlinks \ - cpp cpp-symlinks \ - g77 g77-symlinks \ - gfortran gfortran-symlinks \ - gcov gcov-symlinks \ - ${PN}-doc \ - ${PN}-dev \ - ${PN}-dbg \ -" - -FILES:${PN} = "\ - ${bindir}/${TARGET_PREFIX}gcc* \ - ${bindir}/${TARGET_PREFIX}lto* \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/collect2* \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/g++-mapper-server \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/lto* \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/lib*${SOLIBS} \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/liblto*${SOLIBSDEV} \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/*.o \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/specs \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/lib*${SOLIBS} \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/include \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/include-fixed \ - ${libdir}/bfd-plugins/*.so \ -" -INSANE_SKIP:${PN} += "dev-so" -RRECOMMENDS:${PN} += "\ - libssp \ - libssp-dev \ -" -RDEPENDS:${PN} += "cpp" - -FILES:${PN}-dev = "\ - ${gcclibdir}/${TARGET_SYS}/${BINV}/lib*${SOLIBSDEV} \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/lib*${SOLIBSDEV} \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/plugin/include/ \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/plugin/gengtype \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/plugin/gtype.state \ -" -FILES:${PN}-symlinks = "\ - ${bindir}/cc \ - ${bindir}/gcc \ - ${bindir}/gccbug \ -" - -FILES:${PN}-plugins = "\ - ${gcclibdir}/${TARGET_SYS}/${BINV}/plugin \ -" -ALLOW_EMPTY:${PN}-plugins = "1" - -FILES:g77 = "\ - ${bindir}/${TARGET_PREFIX}g77 \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/f771 \ -" -FILES:g77-symlinks = "\ - ${bindir}/g77 \ - ${bindir}/f77 \ -" -RRECOMMENDS:g77 = "\ - libg2c \ - libg2c-dev \ -" - -FILES:gfortran = "\ - ${bindir}/${TARGET_PREFIX}gfortran \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/f951 \ -" -RRECOMMENDS:gfortran = "\ - libquadmath \ - libquadmath-dev \ -" -FILES:gfortran-symlinks = "\ - ${bindir}/gfortran \ - ${bindir}/f95" - -FILES:cpp = "\ - ${bindir}/${TARGET_PREFIX}cpp* \ - ${base_libdir}/cpp \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/cc1" -FILES:cpp-symlinks = "${bindir}/cpp" - -FILES:gcov = "${bindir}/${TARGET_PREFIX}gcov* \ - ${bindir}/${TARGET_PREFIX}gcov-tool* \ -" -FILES:gcov-symlinks = "${bindir}/gcov \ - ${bindir}/gcov-tool \ -" - -FILES:g++ = "\ - ${bindir}/${TARGET_PREFIX}g++* \ - ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/cc1plus \ -" -FILES:g++-symlinks = "\ - ${bindir}/c++ \ - ${bindir}/g++ \ -" -RRECOMMENDS:g++ = "\ - libstdc++ \ - libstdc++-dev \ - libatomic \ - libatomic-dev \ -" - -FILES:${PN}-doc = "\ - ${infodir} \ - ${mandir} \ - ${gcclibdir}/${TARGET_SYS}/${BINV}/include/README \ -" - -do_compile () { - # Prevent full target sysroot path from being used in configargs.h header, - # as it will be rewritten when used by other sysroots preventing support - # for gcc plugins. Additionally the path is embeddeded into the output - # binary, this prevents building a reproducible binary. - oe_runmake configure-gcc - sed -i 's@${STAGING_DIR_TARGET}@/@g' ${B}/gcc/configargs.h - sed -i 's@${STAGING_DIR_HOST}@/@g' ${B}/gcc/configargs.h - - # Prevent sysroot/workdir paths from being used in checksum-options. - # checksum-options is used to generate a checksum which is embedded into - # the output binary. - oe_runmake TARGET-gcc=checksum-options all-gcc - sed -i 's@${DEBUG_PREFIX_MAP}@@g' ${B}/gcc/checksum-options - sed -i 's@${STAGING_DIR_TARGET}@/@g' ${B}/gcc/checksum-options - - oe_runmake all-host -} - -do_install () { - oe_runmake 'DESTDIR=${D}' install-host - - # Add unwind.h, it comes from libgcc which we don't want to build again - install ${STAGING_LIBDIR_NATIVE}/${TARGET_SYS}/gcc/${TARGET_SYS}/${BINV}/include/unwind.h ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ - - # Info dir listing isn't interesting at this point so remove it if it exists. - if [ -e "${D}${infodir}/dir" ]; then - rm -f ${D}${infodir}/dir - fi - - # Cleanup some of the ${libdir}{,exec}/gcc stuff ... - rm -r ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/install-tools - rm -r ${D}${libexecdir}/gcc/${TARGET_SYS}/${BINV}/install-tools - rm -rf ${D}${libexecdir}/gcc/${TARGET_SYS}/${BINV}/*.la - rmdir ${D}${includedir} - rm -rf ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/finclude - - # Hack around specs file assumptions - test -f ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/specs && sed -i -e '/^*cross_compile:$/ { n; s/1/0/; }' ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/specs - - # Cleanup manpages.. - rm -rf ${D}${mandir}/man7 - - # Don't package details about the build host - rm -f ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/plugin/include/auto-build.h - rm -f ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/plugin/include/bconfig.h - - cd ${D}${bindir} - - # We care about g++ not c++ - rm -f *c++* - - # We don't care about the gcc- ones for this - rm -f *gcc-?*.?* - - # Not sure why we end up with these but we don't want them... - rm -f ${TARGET_PREFIX}${TARGET_PREFIX}* - - # Symlinks so we can use these trivially on the target - if [ -e ${TARGET_PREFIX}g77 ]; then - ln -sf ${TARGET_PREFIX}g77 g77 || true - ln -sf g77 f77 || true - fi - if [ -e ${TARGET_PREFIX}gfortran ]; then - ln -sf ${TARGET_PREFIX}gfortran gfortran || true - ln -sf gfortran f95 || true - fi - ln -sf ${TARGET_PREFIX}g++ g++ - ln -sf ${TARGET_PREFIX}gcc gcc - ln -sf ${TARGET_PREFIX}cpp cpp - ln -sf ${TARGET_PREFIX}gcov gcov - ln -sf ${TARGET_PREFIX}gcov-tool gcov-tool - install -d ${D}${base_libdir} - ln -sf ${bindir}/${TARGET_PREFIX}cpp ${D}${base_libdir}/cpp - ln -sf g++ c++ - ln -sf gcc cc - install -d ${D}${libdir}/bfd-plugins - ln -sf ${libexecdir}/gcc/${TARGET_SYS}/${BINV}/liblto_plugin.so ${D}${libdir}/bfd-plugins/liblto_plugin.so - chown -R root:root ${D} -} - -do_install:append () { - # - # Thefixinc.sh script, run on the gcc's compile phase, looks into sysroot header - # files and places the modified files into - # {D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include-fixed folder. This makes the - # build not deterministic. The following code prunes all those headers - # except those under include-fixed/linux, *limits.h and README, yielding - # the same include-fixed folders no matter what sysroot - - include_fixed="${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/include-fixed" - for f in $(find ${include_fixed} -type f); do - case $f in - */include-fixed/linux/*) - continue - ;; - */include-fixed/*limits.h) - continue - ;; - */include-fixed/README) - continue - ;; - *) - # remove file and directory if empty - bbdebug 2 "Pruning $f" - rm $f - find $(dirname $f) -maxdepth 0 -empty -exec rmdir {} \; - ;; - esac - done -} - -# Installing /usr/lib/gcc/* means we'd have two copies, one from gcc-cross -# and one from here. These can confuse gcc cross where includes use #include_next -# and builds track file dependencies (e.g. perl and its makedepends code). -# For determinism we don't install this ever and rely on the copy from gcc-cross. -# [YOCTO #7287] -SYSROOT_DIRS_IGNORE += "${libdir}/gcc" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-testsuite.inc b/meta-microblaze/recipes-devtools/gcc/gcc-testsuite.inc deleted file mode 100644 index f68fec58..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-testsuite.inc +++ /dev/null @@ -1,107 +0,0 @@ -inherit qemu - -TOOLCHAIN_TEST_TARGET ??= "user" -TOOLCHAIN_TEST_HOST ??= "localhost" -TOOLCHAIN_TEST_HOST_USER ??= "root" -TOOLCHAIN_TEST_HOST_PORT ??= "2222" - -MAKE_CHECK_BOARDFLAGS ??= "" -MAKE_CHECK_BOARDARGS ??= "--target_board=${TOOLCHAIN_TEST_TARGET}${MAKE_CHECK_BOARDFLAGS}" - -python () { - # Provide the targets compiler args via targets options. This allows dejagnu to - # correctly mark incompatible tests as UNSUPPORTED (e.g. needs soft-float - # but running on hard-float target). - # - # These options are called "multilib_flags" within the gcc test suite. Most - # architectures handle these options in a sensible way such that tests that - # are incompatible with the provided multilib are marked as UNSUPPORTED. - # - # Note: multilib flags are added to the compile command after the args - # provided by any test (through dg-options), CFLAGS_FOR_TARGET is always - # added to the compile command before any other args but is not interpted - # as options like multilib flags. - # - # i686, x86-64 and aarch64 are special, since most toolchains built for - # these targets don't do multilib the tests do not get correctly marked as - # UNSUPPORTED. More importantly the test suite itself does not handle - # overriding the multilib flags where it could (like other archs do). As - # such do not pass the target compiler args for these targets. - args = d.getVar("TUNE_CCARGS").split() - if d.getVar("TUNE_ARCH") in ["i686", "x86_64", "aarch64"]: - args = [] - d.setVar("MAKE_CHECK_BOARDFLAGS", ("/" + "/".join(args)) if len(args) != 0 else "") -} - -python check_prepare() { - def generate_qemu_linux_user_config(d): - content = [] - content.append('load_generic_config "sim"') - content.append('load_base_board_description "basic-sim"') - content.append('process_multilib_options ""') - - # qemu args - qemu_binary = qemu_target_binary(d) - if not qemu_binary: - bb.fatal("Missing target qemu linux-user binary") - - args = [] - # QEMU_OPTIONS is not always valid due to -cross recipe - args += ["-r", d.getVar("OLDEST_KERNEL")] - # enable all valid instructions, since the test suite itself does not - # limit itself to the target cpu options. - # - valid for x86*, powerpc, arm, arm64 - if qemu_binary.lstrip("qemu-") in ["x86_64", "i386", "ppc", "arm", "aarch64"]: - args += ["-cpu", "max"] - - sysroot = d.getVar("RECIPE_SYSROOT") - args += ["-L", sysroot] - # lib paths are static here instead of using $libdir since this is used by a -cross recipe - libpaths = [sysroot + "/usr/lib", sysroot + "/lib"] - args += ["-E", "LD_LIBRARY_PATH={0}".format(":".join(libpaths))] - - content.append('set_board_info is_simulator 1') - content.append('set_board_info sim "{0}"'.format(qemu_binary)) - content.append('set_board_info sim,options "{0}"'.format(" ".join(args))) - - # target build/test config - content.append('set_board_info target_install {%s}' % d.getVar("TARGET_SYS")) - content.append('set_board_info ldscript ""') - #content.append('set_board_info needs_status_wrapper 1') # qemu-linux-user return codes work, and abort works fine - content.append('set_board_info gcc,stack_size 16834') - content.append('set_board_info gdb,nosignals 1') - content.append('set_board_info gcc,timeout 60') - - return "\n".join(content) - - def generate_remote_ssh_linux_config(d): - content = [] - content.append('load_generic_config "unix"') - content.append('process_multilib_options ""') - content.append("set_board_info hostname {0}".format(d.getVar("TOOLCHAIN_TEST_HOST"))) - content.append("set_board_info username {0}".format(d.getVar("TOOLCHAIN_TEST_HOST_USER"))) - - port = d.getVar("TOOLCHAIN_TEST_HOST_PORT") - content.append("set_board_info rsh_prog \"/usr/bin/ssh -p {0} -o UserKnownHostsFile=/dev/null -o StrictHostKeyChecking=no\"".format(port)) - content.append("set_board_info rcp_prog \"/usr/bin/scp -P {0} -o UserKnownHostsFile=/dev/null -o StrictHostKeyChecking=no\"".format(port)) - - return "\n".join(content) - - dejagnudir = d.expand("${WORKDIR}/dejagnu") - if not os.path.isdir(dejagnudir): - os.makedirs(dejagnudir) - - # write out target qemu board config - with open(os.path.join(dejagnudir, "user.exp"), "w") as f: - f.write(generate_qemu_linux_user_config(d)) - - # write out target ssh board config - with open(os.path.join(dejagnudir, "ssh.exp"), "w") as f: - f.write(generate_remote_ssh_linux_config(d)) - - # generate site.exp to provide boards - with open(os.path.join(dejagnudir, "site.exp"), "w") as f: - f.write("lappend boards_dir {0}\n".format(dejagnudir)) - f.write("set CFLAGS_FOR_TARGET \"{0}\"\n".format(d.getVar("TOOLCHAIN_OPTIONS"))) -} - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch deleted file mode 100644 index 66e582ca..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0001-gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 31f94ef5b43a984a98f0eebd2dcf1b53aa1d7bce Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 08:37:11 +0400 -Subject: [PATCH] gcc-4.3.1: ARCH_FLAGS_FOR_TARGET - -Signed-off-by: Khem Raj - -Upstream-Status: Inappropriate [embedded specific] ---- - configure | 2 +- - configure.ac | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/configure b/configure -index 5dcaab14ae9..f76310a36bb 100755 ---- a/configure -+++ b/configure -@@ -10165,7 +10165,7 @@ fi - # for target_alias and gcc doesn't manage it consistently. - target_configargs="--cache-file=./config.cache ${target_configargs}" - --FLAGS_FOR_TARGET= -+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET" - case " $target_configdirs " in - *" newlib "*) - case " $target_configargs " in -diff --git a/configure.ac b/configure.ac -index 85977482aee..8b9097c7a45 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -3346,7 +3346,7 @@ fi - # for target_alias and gcc doesn't manage it consistently. - target_configargs="--cache-file=./config.cache ${target_configargs}" - --FLAGS_FOR_TARGET= -+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET" - case " $target_configdirs " in - *" newlib "*) - case " $target_configargs " in diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0002-gcc-poison-system-directories.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0002-gcc-poison-system-directories.patch deleted file mode 100644 index 5aa635b3..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0002-gcc-poison-system-directories.patch +++ /dev/null @@ -1,239 +0,0 @@ -From 99f1e61b2957226254a116fde7fd73bf07034012 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Mon, 8 Mar 2021 16:04:20 -0800 -Subject: [PATCH] gcc: poison-system-directories - -Add /sw/include and /opt/include based on the original -zecke-no-host-includes.patch patch. The original patch checked for -/usr/include, /sw/include and /opt/include and then triggered a failure and -aborted. - -Instead, we add the two missing items to the current scan. If the user -wants this to be a failure, they can add "-Werror=poison-system-directories". - -Upstream-Status: Pending -Signed-off-by: Mark Hatle -Signed-off-by: Khem Raj ---- - gcc/common.opt | 4 ++++ - gcc/config.in | 10 ++++++++++ - gcc/configure | 19 +++++++++++++++++++ - gcc/configure.ac | 16 ++++++++++++++++ - gcc/doc/invoke.texi | 9 +++++++++ - gcc/gcc.cc | 15 ++++++++++++--- - gcc/incpath.cc | 21 +++++++++++++++++++++ - 7 files changed, 91 insertions(+), 3 deletions(-) - -diff --git a/gcc/common.opt b/gcc/common.opt -index 8a0dafc52..0357868e2 100644 ---- a/gcc/common.opt -+++ b/gcc/common.opt -@@ -710,6 +710,10 @@ Wreturn-local-addr - Common Var(warn_return_local_addr) Init(1) Warning - Warn about returning a pointer/reference to a local or temporary variable. - -+Wpoison-system-directories -+Common Var(flag_poison_system_directories) Init(1) Warning -+Warn for -I and -L options using system directories if cross compiling -+ - Wshadow - Common Var(warn_shadow) Warning - Warn when one variable shadows another. Same as -Wshadow=global. -diff --git a/gcc/config.in b/gcc/config.in -index 64c27c9cf..a693cb8a8 100644 ---- a/gcc/config.in -+++ b/gcc/config.in -@@ -230,6 +230,16 @@ - #endif - - -+/* Define to warn for use of native system header directories */ -+#ifndef USED_FOR_TARGET -+#undef ENABLE_POISON_SYSTEM_DIRECTORIES -+#endif -+/* Define to warn for use of native system header directories */ -+#ifndef USED_FOR_TARGET -+#undef POISON_BY_DEFAULT -+#endif -+ -+ - /* Define if you want all operations on RTL (the basic data structure of the - optimizer and back end) to be checked for dynamic type safety at runtime. - This is quite expensive. */ -diff --git a/gcc/configure b/gcc/configure -index 2b83acfb0..8bb97578c 100755 ---- a/gcc/configure -+++ b/gcc/configure -@@ -1023,6 +1023,7 @@ enable_maintainer_mode - enable_link_mutex - enable_link_serialization - enable_version_specific_runtime_libs -+enable_poison_system_directories - enable_plugin - enable_host_shared - enable_libquadmath_support -@@ -1785,6 +1786,8 @@ Optional Features: - --enable-version-specific-runtime-libs - specify that runtime libraries should be installed - in a compiler-specific directory -+ --enable-poison-system-directories -+ warn for use of native system header directories - --enable-plugin enable plugin support - --enable-host-shared build host code as shared libraries - --disable-libquadmath-support -@@ -31996,6 +31999,22 @@ if test "${enable_version_specific_runtime_libs+set}" = set; then : - fi - - -+# Check whether --enable-poison-system-directories was given. -+if test "${enable_poison_system_directories+set}" = set; then : -+ enableval=$enable_poison_system_directories; -+else -+ enable_poison_system_directories=no -+fi -+ -+if test "x${enable_poison_system_directories}" != "xno"; then -+ -+$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h -+if test "$enable_poison_system_directories" = "error"; then -+$as_echo "#define POISON_BY_DEFAULT 1" >>confdefs.h -+fi -+ -+fi -+ - # Substitute configuration variables - - -diff --git a/gcc/configure.ac b/gcc/configure.ac -index daf2a708c..6155b83a7 100644 ---- a/gcc/configure.ac -+++ b/gcc/configure.ac -@@ -7435,6 +7435,22 @@ AC_ARG_ENABLE(version-specific-runtime-libs, - [specify that runtime libraries should be - installed in a compiler-specific directory])]) - -+AC_ARG_ENABLE([poison-system-directories], -+ AS_HELP_STRING([--enable-poison-system-directories], -+ [warn for use of native system header directories (no/yes/error)]),, -+ [enable_poison_system_directories=no]) -+AC_MSG_NOTICE([poisoned directories $enable_poison_system_directories]) -+if test "x${enable_poison_system_directories}" != "xno"; then -+ AC_MSG_NOTICE([poisoned directories enabled]) -+ AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES], -+ [1], -+ [Define to warn for use of native system header directories]) -+ if test $enable_poison_system_directories = "error"; then -+ AC_MSG_NOTICE([poisoned directories are fatal]) -+ AC_DEFINE([POISON_BY_DEFAULT], [1], [Define to make poison warnings errors]) -+ fi -+fi -+ - # Substitute configuration variables - AC_SUBST(subdirs) - AC_SUBST(srcdir) -diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi -index ff6c338be..a8ebfa59a 100644 ---- a/gcc/doc/invoke.texi -+++ b/gcc/doc/invoke.texi -@@ -379,6 +379,7 @@ Objective-C and Objective-C++ Dialects}. - -Wpacked -Wno-packed-bitfield-compat -Wpacked-not-aligned -Wpadded @gol - -Wparentheses -Wno-pedantic-ms-format @gol - -Wpointer-arith -Wno-pointer-compare -Wno-pointer-to-int-cast @gol -+-Wno-poison-system-directories @gol - -Wno-pragmas -Wno-prio-ctor-dtor -Wredundant-decls @gol - -Wrestrict -Wno-return-local-addr -Wreturn-type @gol - -Wno-scalar-storage-order -Wsequence-point @gol -@@ -8029,6 +8030,14 @@ made up of data only and thus requires no special treatment. But, for - most targets, it is made up of code and thus requires the stack to be - made executable in order for the program to work properly. - -+@item -Wno-poison-system-directories -+@opindex Wno-poison-system-directories -+Do not warn for @option{-I} or @option{-L} options using system -+directories such as @file{/usr/include} when cross compiling. This -+option is intended for use in chroot environments when such -+directories contain the correct headers and libraries for the target -+system rather than the host. -+ - @item -Wfloat-equal - @opindex Wfloat-equal - @opindex Wno-float-equal -diff --git a/gcc/gcc.cc b/gcc/gcc.cc -index beefde7f6..4e6557b3c 100644 ---- a/gcc/gcc.cc -+++ b/gcc/gcc.cc -@@ -1162,6 +1162,8 @@ proper position among the other output files. */ - "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \ - "%X %{o*} %{e*} %{N} %{n} %{r}\ - %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \ -+ %{Wno-poison-system-directories:--no-poison-system-directories} \ -+ %{Werror=poison-system-directories:--error-poison-system-directories} \ - %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \ - VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \ - %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\ -@@ -1257,8 +1259,11 @@ static const char *cpp_unique_options = - static const char *cpp_options = - "%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w}\ - %{f*} %{g*:%{%:debug-level-gt(0):%{g*}\ -- %{!fno-working-directory:-fworking-directory}}} %{O*}\ -- %{undef} %{save-temps*:-fpch-preprocess}"; -+ %{!fno-working-directory:-fworking-directory}}} %{O*}" -+#ifdef POISON_BY_DEFAULT -+ " %{!Wno-error=poison-system-directories:-Werror=poison-system-directories}" -+#endif -+ " %{undef} %{save-temps*:-fpch-preprocess}"; - - /* Pass -d* flags, possibly modifying -dumpdir, -dumpbase et al. - -@@ -1287,7 +1292,11 @@ static const char *cc1_options = - %{coverage:-fprofile-arcs -ftest-coverage}\ - %{fprofile-arcs|fprofile-generate*|coverage:\ - %{!fprofile-update=single:\ -- %{pthread:-fprofile-update=prefer-atomic}}}"; -+ %{pthread:-fprofile-update=prefer-atomic}}}" -+#ifdef POISON_BY_DEFAULT -+ " %{!Wno-error=poison-system-directories:-Werror=poison-system-directories}" -+#endif -+ ; - - static const char *asm_options = - "%{-target-help:%:print-asm-header()} " -diff --git a/gcc/incpath.cc b/gcc/incpath.cc -index 622204a38..5ac03c086 100644 ---- a/gcc/incpath.cc -+++ b/gcc/incpath.cc -@@ -26,6 +26,7 @@ - #include "intl.h" - #include "incpath.h" - #include "cppdefault.h" -+#include "diagnostic-core.h" - - /* Microsoft Windows does not natively support inodes. - VMS has non-numeric inodes. */ -@@ -399,6 +400,26 @@ merge_include_chains (const char *sysroot, cpp_reader *pfile, int verbose) - } - fprintf (stderr, _("End of search list.\n")); - } -+ -+#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES -+ if (flag_poison_system_directories) -+ { -+ struct cpp_dir *p; -+ -+ for (p = heads[INC_QUOTE]; p; p = p->next) -+ { -+ if ((!strncmp (p->name, "/usr/include", 12)) -+ || (!strncmp (p->name, "/usr/local/include", 18)) -+ || (!strncmp (p->name, "/usr/X11R6/include", 18)) -+ || (!strncmp (p->name, "/sw/include", 11)) -+ || (!strncmp (p->name, "/opt/include", 12))) -+ warning (OPT_Wpoison_system_directories, -+ "include location \"%s\" is unsafe for " -+ "cross-compilation", -+ p->name); -+ } -+ } -+#endif - } - - /* Use given -I paths for #include "..." but not #include <...>, and diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0003-64-bit-multilib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0003-64-bit-multilib-hack.patch deleted file mode 100644 index e83f05b8..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0003-64-bit-multilib-hack.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 34b861e7a4cfd7b1f0d2c0f8cf9bb0b0b81eb61a Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:10:06 +0400 -Subject: [PATCH] 64-bit multilib hack. - -GCC has internal multilib handling code but it assumes a very specific rigid directory -layout. The build system implementation of multilib layout is very generic and allows -complete customisation of the library directories. - -This patch is a partial solution to allow any custom directories to be passed into gcc -and handled correctly. It forces gcc to use the base_libdir (which is the current -directory, "."). We need to do this for each multilib that is configured as we don't -know which compiler options may be being passed into the compiler. Since we have a compiler -per mulitlib at this point that isn't an issue. - -The one problem is the target compiler is only going to work for the default multlilib at -this point. Ideally we'd figure out which multilibs were being enabled with which paths -and be able to patch these entries with a complete set of correct paths but this we -don't have such code at this point. This is something the target gcc recipe should do -and override these platform defaults in its build config. - -Do same for riscv64, aarch64 & arc - -RP 15/8/11 - -Upstream-Status: Inappropriate [OE-Specific] - -Signed-off-by: Khem Raj -Signed-off-by: Elvis Dowson -Signed-off-by: Mark Hatle -Signed-off-by: Khem Raj ---- - gcc/config/aarch64/t-aarch64-linux | 8 ++++---- - gcc/config/arc/t-multilib-linux | 4 ++-- - gcc/config/i386/t-linux64 | 6 ++---- - gcc/config/mips/t-linux64 | 10 +++------- - gcc/config/riscv/t-linux | 6 ++++-- - gcc/config/rs6000/t-linux64 | 5 ++--- - 6 files changed, 17 insertions(+), 22 deletions(-) - -diff --git a/gcc/config/aarch64/t-aarch64-linux b/gcc/config/aarch64/t-aarch64-linux -index d0cd546002a..f4056d68372 100644 ---- a/gcc/config/aarch64/t-aarch64-linux -+++ b/gcc/config/aarch64/t-aarch64-linux -@@ -21,8 +21,8 @@ - LIB1ASMSRC = aarch64/lib1funcs.asm - LIB1ASMFUNCS = _aarch64_sync_cache_range - --AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be) --MULTILIB_OSDIRNAMES = mabi.lp64=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu) --MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu) -+#AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be) -+#MULTILIB_OSDIRNAMES = mabi.lp64=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu) -+#MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu) - --MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu_ilp32) -+#MULTILIB_OSDIRNAMES += mabi.ilp32=../libilp32$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu_ilp32) -diff --git a/gcc/config/arc/t-multilib-linux b/gcc/config/arc/t-multilib-linux -index ecb9ae6859f..12a164028d4 100644 ---- a/gcc/config/arc/t-multilib-linux -+++ b/gcc/config/arc/t-multilib-linux -@@ -16,9 +16,9 @@ - # along with GCC; see the file COPYING3. If not see - # . - --MULTILIB_OPTIONS = mcpu=hs/mcpu=archs/mcpu=hs38/mcpu=hs38_linux/mcpu=arc700/mcpu=nps400 -+#MULTILIB_OPTIONS = mcpu=hs/mcpu=archs/mcpu=hs38/mcpu=hs38_linux/mcpu=arc700/mcpu=nps400 - --MULTILIB_DIRNAMES = hs archs hs38 hs38_linux arc700 nps400 -+#MULTILIB_DIRNAMES = hs archs hs38 hs38_linux arc700 nps400 - - # Aliases: - MULTILIB_MATCHES += mcpu?arc700=mA7 -diff --git a/gcc/config/i386/t-linux64 b/gcc/config/i386/t-linux64 -index 5526ad0e6cc..fa51c88912b 100644 ---- a/gcc/config/i386/t-linux64 -+++ b/gcc/config/i386/t-linux64 -@@ -32,7 +32,5 @@ - # - comma=, - MULTILIB_OPTIONS = $(subst $(comma),/,$(TM_MULTILIB_CONFIG)) --MULTILIB_DIRNAMES = $(patsubst m%, %, $(subst /, ,$(MULTILIB_OPTIONS))) --MULTILIB_OSDIRNAMES = m64=../lib64$(call if_multiarch,:x86_64-linux-gnu) --MULTILIB_OSDIRNAMES+= m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:i386-linux-gnu) --MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-linux-gnux32) -+MULTILIB_DIRNAMES = . . -+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) -diff --git a/gcc/config/mips/t-linux64 b/gcc/config/mips/t-linux64 -index 2fdd8e00407..04f2099250f 100644 ---- a/gcc/config/mips/t-linux64 -+++ b/gcc/config/mips/t-linux64 -@@ -17,10 +17,6 @@ - # . - - MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64 --MULTILIB_DIRNAMES = n32 32 64 --MIPS_EL = $(if $(filter %el, $(firstword $(subst -, ,$(target)))),el) --MIPS_SOFT = $(if $(strip $(filter MASK_SOFT_FLOAT_ABI, $(target_cpu_default)) $(filter soft, $(with_float))),soft) --MULTILIB_OSDIRNAMES = \ -- ../lib32$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabin32$(MIPS_SOFT)) \ -- ../lib$(call if_multiarch,:mips$(MIPS_EL)-linux-gnu$(MIPS_SOFT)) \ -- ../lib64$(call if_multiarch,:mips64$(MIPS_EL)-linux-gnuabi64$(MIPS_SOFT)) -+MULTILIB_DIRNAMES = . . . -+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) -+ -diff --git a/gcc/config/riscv/t-linux b/gcc/config/riscv/t-linux -index 216d2776a18..e4d817621fc 100644 ---- a/gcc/config/riscv/t-linux -+++ b/gcc/config/riscv/t-linux -@@ -1,3 +1,5 @@ - # Only XLEN and ABI affect Linux multilib dir names, e.g. /lib32/ilp32d/ --MULTILIB_DIRNAMES := $(patsubst rv32%,lib32,$(patsubst rv64%,lib64,$(MULTILIB_DIRNAMES))) --MULTILIB_OSDIRNAMES := $(patsubst lib%,../lib%,$(MULTILIB_DIRNAMES)) -+#MULTILIB_DIRNAMES := $(patsubst rv32%,lib32,$(patsubst rv64%,lib64,$(MULTILIB_DIRNAMES))) -+MULTILIB_DIRNAMES := . . -+#MULTILIB_OSDIRNAMES := $(patsubst lib%,../lib%,$(MULTILIB_DIRNAMES)) -+MULTILIB_OSDIRNAMES := ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) -diff --git a/gcc/config/rs6000/t-linux64 b/gcc/config/rs6000/t-linux64 -index 47e0efd5764..05f5a3f188e 100644 ---- a/gcc/config/rs6000/t-linux64 -+++ b/gcc/config/rs6000/t-linux64 -@@ -26,10 +26,9 @@ - # MULTILIB_OSDIRNAMES according to what is found on the target. - - MULTILIB_OPTIONS := m64/m32 --MULTILIB_DIRNAMES := 64 32 -+MULTILIB_DIRNAMES := . . - MULTILIB_EXTRA_OPTS := --MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu) --MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu) -+MULTILIB_OSDIRNAMES := ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) - - rs6000-linux.o: $(srcdir)/config/rs6000/rs6000-linux.cc - $(COMPILE) $< diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0004-Pass-CXXFLAGS_FOR_BUILD-in-a-couple-of-places-to-avo.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0004-Pass-CXXFLAGS_FOR_BUILD-in-a-couple-of-places-to-avo.patch deleted file mode 100644 index e8f21634..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0004-Pass-CXXFLAGS_FOR_BUILD-in-a-couple-of-places-to-avo.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 7f40f8321fb999e9b34d948724517d3fb0d26820 Mon Sep 17 00:00:00 2001 -From: Richard Purdie -Date: Thu, 28 Oct 2021 11:33:40 +0100 -Subject: [PATCH] Pass CXXFLAGS_FOR_BUILD in a couple of places to avoid these - errors. - -If CXXFLAGS contains something unsupported by the build CXX, we see build failures (e.g. using -fmacro-prefix-map for the target). - -2021-10-28 Richard Purdie - -ChangeLog: - - * Makefile.in: Regenerate. - * Makefile.tpl: Add missing CXXFLAGS_FOR_BUILD overrides - -Upstream-Status: Pending [should be submittable] - -Signed-off-by: Richard Purdie -Signed-off-by: Khem Raj ---- - Makefile.in | 2 ++ - Makefile.tpl | 2 ++ - 2 files changed, 4 insertions(+) - -diff --git a/Makefile.in b/Makefile.in -index 593495e1650..1d9c83cc566 100644 ---- a/Makefile.in -+++ b/Makefile.in -@@ -176,6 +176,7 @@ BUILD_EXPORTS = \ - # built for the build system to override those in BASE_FLAGS_TO_PASS. - EXTRA_BUILD_FLAGS = \ - CFLAGS="$(CFLAGS_FOR_BUILD)" \ -+ CXXFLAGS="$(CXXFLAGS_FOR_BUILD)" \ - LDFLAGS="$(LDFLAGS_FOR_BUILD)" - - # This is the list of directories to built for the host system. -@@ -207,6 +208,7 @@ HOST_EXPORTS = \ - CPP_FOR_BUILD="$(CPP_FOR_BUILD)"; export CPP_FOR_BUILD; \ - CPPFLAGS_FOR_BUILD="$(CPPFLAGS_FOR_BUILD)"; export CPPFLAGS_FOR_BUILD; \ - CXX_FOR_BUILD="$(CXX_FOR_BUILD)"; export CXX_FOR_BUILD; \ -+ CXXFLAGS_FOR_BUILD="$(CXXFLAGS_FOR_BUILD)"; export CXXFLAGS_FOR_BUILD; \ - DLLTOOL="$(DLLTOOL)"; export DLLTOOL; \ - DSYMUTIL="$(DSYMUTIL)"; export DSYMUTIL; \ - LD="$(LD)"; export LD; \ -diff --git a/Makefile.tpl b/Makefile.tpl -index ef58fac2b9a..bab04f335c2 100644 ---- a/Makefile.tpl -+++ b/Makefile.tpl -@@ -179,6 +179,7 @@ BUILD_EXPORTS = \ - # built for the build system to override those in BASE_FLAGS_TO_PASS. - EXTRA_BUILD_FLAGS = \ - CFLAGS="$(CFLAGS_FOR_BUILD)" \ -+ CXXFLAGS="$(CXXFLAGS_FOR_BUILD)" \ - LDFLAGS="$(LDFLAGS_FOR_BUILD)" - - # This is the list of directories to built for the host system. -@@ -210,6 +211,7 @@ HOST_EXPORTS = \ - CPP_FOR_BUILD="$(CPP_FOR_BUILD)"; export CPP_FOR_BUILD; \ - CPPFLAGS_FOR_BUILD="$(CPPFLAGS_FOR_BUILD)"; export CPPFLAGS_FOR_BUILD; \ - CXX_FOR_BUILD="$(CXX_FOR_BUILD)"; export CXX_FOR_BUILD; \ -+ CXXFLAGS_FOR_BUILD="$(CXXFLAGS_FOR_BUILD)"; export CXXFLAGS_FOR_BUILD; \ - DLLTOOL="$(DLLTOOL)"; export DLLTOOL; \ - DSYMUTIL="$(DSYMUTIL)"; export DSYMUTIL; \ - LD="$(LD)"; export LD; \ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0005-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0005-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch deleted file mode 100644 index e34eb2cf..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0005-Use-the-defaults.h-in-B-instead-of-S-and-t-oe-in-B.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 5455fc1de74897a27c1199dc5611ec02243e24af Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:17:25 +0400 -Subject: [PATCH] Use the defaults.h in ${B} instead of ${S}, and t-oe in ${B} - -Use the defaults.h in ${B} instead of ${S}, and t-oe in ${B}, so that -the source can be shared between gcc-cross-initial, -gcc-cross-intermediate, gcc-cross, gcc-runtime, and also the sdk build. - -Signed-off-by: Khem Raj - -Upstream-Status: Pending - -While compiling gcc-crosssdk-initial-x86_64 on some host, there is -occasionally failure that test the existance of default.h doesn't -work, the reason is tm_include_list='** defaults.h' rather than -tm_include_list='** ./defaults.h' - -So we add the test condition for this situation. -Signed-off-by: Hongxu Jia ---- - gcc/Makefile.in | 2 +- - gcc/configure | 4 ++-- - gcc/configure.ac | 4 ++-- - gcc/mkconfig.sh | 4 ++-- - 4 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/gcc/Makefile.in b/gcc/Makefile.in -index 31ff95500c9..a8277254696 100644 ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -553,7 +553,7 @@ TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT@ - TARGET_SYSTEM_ROOT_DEFINE = @TARGET_SYSTEM_ROOT_DEFINE@ - - xmake_file=@xmake_file@ --tmake_file=@tmake_file@ -+tmake_file=@tmake_file@ ./t-oe - TM_ENDIAN_CONFIG=@TM_ENDIAN_CONFIG@ - TM_MULTILIB_CONFIG=@TM_MULTILIB_CONFIG@ - TM_MULTILIB_EXCEPTIONS_CONFIG=@TM_MULTILIB_EXCEPTIONS_CONFIG@ -diff --git a/gcc/configure b/gcc/configure -index dc2d59701ad..3fc0e2f5813 100755 ---- a/gcc/configure -+++ b/gcc/configure -@@ -13381,8 +13381,8 @@ for f in $tm_file; do - tm_include_list="${tm_include_list} $f" - ;; - defaults.h ) -- tm_file_list="${tm_file_list} \$(srcdir)/$f" -- tm_include_list="${tm_include_list} $f" -+ tm_file_list="${tm_file_list} ./$f" -+ tm_include_list="${tm_include_list} ./$f" - ;; - * ) - tm_file_list="${tm_file_list} \$(srcdir)/config/$f" -diff --git a/gcc/configure.ac b/gcc/configure.ac -index 36ce78924de..46de496b256 100644 ---- a/gcc/configure.ac -+++ b/gcc/configure.ac -@@ -2332,8 +2332,8 @@ for f in $tm_file; do - tm_include_list="${tm_include_list} $f" - ;; - defaults.h ) -- tm_file_list="${tm_file_list} \$(srcdir)/$f" -- tm_include_list="${tm_include_list} $f" -+ tm_file_list="${tm_file_list} ./$f" -+ tm_include_list="${tm_include_list} ./$f" - ;; - * ) - tm_file_list="${tm_file_list} \$(srcdir)/config/$f" -diff --git a/gcc/mkconfig.sh b/gcc/mkconfig.sh -index 91cc43f69ff..8de33713cd8 100644 ---- a/gcc/mkconfig.sh -+++ b/gcc/mkconfig.sh -@@ -77,7 +77,7 @@ if [ -n "$HEADERS" ]; then - if [ $# -ge 1 ]; then - echo '#ifdef IN_GCC' >> ${output}T - for file in "$@"; do -- if test x"$file" = x"defaults.h"; then -+ if test x"$file" = x"./defaults.h" -o x"$file" = x"defaults.h"; then - postpone_defaults_h="yes" - else - echo "# include \"$file\"" >> ${output}T -@@ -106,7 +106,7 @@ esac - - # If we postponed including defaults.h, add the #include now. - if test x"$postpone_defaults_h" = x"yes"; then -- echo "# include \"defaults.h\"" >> ${output}T -+ echo "# include \"./defaults.h\"" >> ${output}T - fi - - # Add multiple inclusion protection guard, part two. diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0006-cpp-honor-sysroot.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0006-cpp-honor-sysroot.patch deleted file mode 100644 index b08aecc7..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0006-cpp-honor-sysroot.patch +++ /dev/null @@ -1,53 +0,0 @@ -From abc3b82ab24169277f2090e9df1ceac3573142be Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:22:00 +0400 -Subject: [PATCH] cpp: honor sysroot. - -Currently, if the gcc toolchain is relocated and installed from sstate, then you try and compile -preprocessed source (.i or .ii files), the compiler will try and access the builtin sysroot location -rather than the --sysroot option specified on the commandline. If access to that directory is -permission denied (unreadable), gcc will error. - -This happens when ccache is in use due to the fact it uses preprocessed source files. - -The fix below adds %I to the cpp-output spec macro so the default substitutions for -iprefix, --isystem, -isysroot happen and the correct sysroot is used. - -[YOCTO #2074] - -RP 2012/04/13 - -Signed-off-by: Khem Raj - -Upstream-Status: Pending ---- - gcc/cp/lang-specs.h | 2 +- - gcc/gcc.cc | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/cp/lang-specs.h b/gcc/cp/lang-specs.h -index f35c9fab76b..19ddc98ce7f 100644 ---- a/gcc/cp/lang-specs.h -+++ b/gcc/cp/lang-specs.h -@@ -116,7 +116,7 @@ along with GCC; see the file COPYING3. If not see - {".ii", "@c++-cpp-output", 0, 0, 0}, - {"@c++-cpp-output", - "%{!E:%{!M:%{!MM:" -- " cc1plus -fpreprocessed %i %(cc1_options) %2" -+ " cc1plus -fpreprocessed %i %I %(cc1_options) %2" - " %{!fsyntax-only:" - " %{fmodule-only:%{!S:-o %g.s%V}}" - " %{!fmodule-only:%{!fmodule-header*:%(invoke_as)}}}" -diff --git a/gcc/gcc.cc b/gcc/gcc.cc -index ce161d3c853..aa4cf92fb78 100644 ---- a/gcc/gcc.cc -+++ b/gcc/gcc.cc -@@ -1476,7 +1476,7 @@ static const struct compiler default_compilers[] = - %W{o*:--output-pch=%*}}%V}}}}}}}", 0, 0, 0}, - {".i", "@cpp-output", 0, 0, 0}, - {"@cpp-output", -- "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, -+ "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %I %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, - {".s", "@assembler", 0, 0, 0}, - {"@assembler", - "%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 0, 0}, diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0007-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0007-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch deleted file mode 100644 index b59eed57..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0007-Define-GLIBC_DYNAMIC_LINKER-and-UCLIBC_DYNAMIC_LINKE.patch +++ /dev/null @@ -1,403 +0,0 @@ -From 4de00af67b57b5440bdf61ab364ad959ad0aeee7 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:24:50 +0400 -Subject: [PATCH] Define GLIBC_DYNAMIC_LINKER and UCLIBC_DYNAMIC_LINKER - relative to SYSTEMLIBS_DIR - -This patch defines GLIBC_DYNAMIC_LINKER and UCLIBC_DYNAMIC_LINKER -relative to SYSTEMLIBS_DIR which can be set in generated headers -This breaks the assumption of hardcoded multilib in gcc -Change is only for the supported architectures in OE including -SH, sparc, alpha for possible future support (if any) - -Removes the do_headerfix task in metadata - -Signed-off-by: Khem Raj - -Upstream-Status: Inappropriate [OE configuration] -Signed-off-by: Khem Raj ---- - gcc/config/aarch64/aarch64-linux.h | 4 ++-- - gcc/config/alpha/linux-elf.h | 4 ++-- - gcc/config/arm/linux-eabi.h | 6 +++--- - gcc/config/arm/linux-elf.h | 2 +- - gcc/config/i386/linux.h | 4 ++-- - gcc/config/i386/linux64.h | 12 ++++++------ - gcc/config/linux.h | 8 ++++---- - gcc/config/loongarch/gnu-user.h | 4 ++-- - gcc/config/microblaze/linux.h | 4 ++-- - gcc/config/mips/linux.h | 18 +++++++++--------- - gcc/config/nios2/linux.h | 4 ++-- - gcc/config/riscv/linux.h | 4 ++-- - gcc/config/rs6000/linux64.h | 15 +++++---------- - gcc/config/rs6000/sysv4.h | 4 ++-- - gcc/config/s390/linux.h | 8 ++++---- - gcc/config/sh/linux.h | 4 ++-- - gcc/config/sparc/linux.h | 2 +- - gcc/config/sparc/linux64.h | 4 ++-- - 18 files changed, 53 insertions(+), 58 deletions(-) - -diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h -index 5e4553d79f5..877e8841eb2 100644 ---- a/gcc/config/aarch64/aarch64-linux.h -+++ b/gcc/config/aarch64/aarch64-linux.h -@@ -21,10 +21,10 @@ - #ifndef GCC_AARCH64_LINUX_H - #define GCC_AARCH64_LINUX_H - --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1" - - #undef MUSL_DYNAMIC_LINKER --#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1" -+#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1" - - #undef ASAN_CC1_SPEC - #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}" -diff --git a/gcc/config/alpha/linux-elf.h b/gcc/config/alpha/linux-elf.h -index 17f16a55910..0a7be38fa63 100644 ---- a/gcc/config/alpha/linux-elf.h -+++ b/gcc/config/alpha/linux-elf.h -@@ -23,8 +23,8 @@ along with GCC; see the file COPYING3. If not see - #define EXTRA_SPECS \ - { "elf_dynamic_linker", ELF_DYNAMIC_LINKER }, - --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" --#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux.so.2" -+#define UCLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-uClibc.so.0" - #if DEFAULT_LIBC == LIBC_UCLIBC - #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" - #elif DEFAULT_LIBC == LIBC_GLIBC -diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h -index 50cc0bc6d08..17c18b27145 100644 ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -65,8 +65,8 @@ - GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */ - - #undef GLIBC_DYNAMIC_LINKER --#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/lib/ld-linux.so.3" --#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3" -+#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT SYSTEMLIBS_DIR "ld-linux.so.3" -+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT SYSTEMLIBS_DIR "ld-linux-armhf.so.3" - #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT - - #define GLIBC_DYNAMIC_LINKER \ -@@ -89,7 +89,7 @@ - #define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}" - #endif - #define MUSL_DYNAMIC_LINKER \ -- "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1" -+ SYSTEMLIBS_DIR "ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1" - - /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to - use the GNU/Linux version, not the generic BPABI version. */ -diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h -index df3da67c4f0..37456e9d5a4 100644 ---- a/gcc/config/arm/linux-elf.h -+++ b/gcc/config/arm/linux-elf.h -@@ -60,7 +60,7 @@ - - #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc" - --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux.so.2" - - #define LINUX_TARGET_LINK_SPEC "%{h*} \ - %{static:-Bstatic} \ -diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h -index 5d99ee56d5b..a76022c9ccc 100644 ---- a/gcc/config/i386/linux.h -+++ b/gcc/config/i386/linux.h -@@ -20,7 +20,7 @@ along with GCC; see the file COPYING3. If not see - . */ - - #define GNU_USER_LINK_EMULATION "elf_i386" --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux.so.2" - - #undef MUSL_DYNAMIC_LINKER --#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1" -+#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-i386.so.1" -diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h -index 8681e36f10d..ddce49b6b60 100644 ---- a/gcc/config/i386/linux64.h -+++ b/gcc/config/i386/linux64.h -@@ -27,13 +27,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - #define GNU_USER_LINK_EMULATION64 "elf_x86_64" - #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64" - --#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2" --#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2" --#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2" -+#define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-linux.so.2" -+#define GLIBC_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld-linux-x86-64.so.2" -+#define GLIBC_DYNAMIC_LINKERX32 SYSTEMLIBS_DIR "ld-linux-x32.so.2" - - #undef MUSL_DYNAMIC_LINKER32 --#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1" -+#define MUSL_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-musl-i386.so.1" - #undef MUSL_DYNAMIC_LINKER64 --#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1" -+#define MUSL_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld-musl-x86_64.so.1" - #undef MUSL_DYNAMIC_LINKERX32 --#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1" -+#define MUSL_DYNAMIC_LINKERX32 SYSTEMLIBS_DIR "ld-musl-x32.so.1" -diff --git a/gcc/config/linux.h b/gcc/config/linux.h -index 74f70793d90..4ce173384ef 100644 ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -99,10 +99,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - GLIBC_DYNAMIC_LINKER must be defined for each target using them, or - GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets - supporting both 32-bit and 64-bit compilation. */ --#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" --#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" --#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" --#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0" -+#define UCLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-uClibc.so.0" -+#define UCLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-uClibc.so.0" -+#define UCLIBC_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld64-uClibc.so.0" -+#define UCLIBC_DYNAMIC_LINKERX32 SYSTEMLIBS_DIR "ldx32-uClibc.so.0" - #define BIONIC_DYNAMIC_LINKER "/system/bin/linker" - #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker" - #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64" -diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h -index 664dc9206ad..082bd7cfc6f 100644 ---- a/gcc/config/loongarch/gnu-user.h -+++ b/gcc/config/loongarch/gnu-user.h -@@ -31,11 +31,11 @@ along with GCC; see the file COPYING3. If not see - - #undef GLIBC_DYNAMIC_LINKER - #define GLIBC_DYNAMIC_LINKER \ -- "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" -+ SYSTEMLIBS_DIR "ld-linux-loongarch-" ABI_SPEC ".so.1" - - #undef MUSL_DYNAMIC_LINKER - #define MUSL_DYNAMIC_LINKER \ -- "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1" -+ SYSTEMLIBS_DIR "ld-musl-loongarch-" ABI_SPEC ".so.1" - - #undef GNU_USER_TARGET_LINK_SPEC - #define GNU_USER_TARGET_LINK_SPEC \ -diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h -index 5b1a365eda4..2e63df1ae9c 100644 ---- a/gcc/config/microblaze/linux.h -+++ b/gcc/config/microblaze/linux.h -@@ -28,7 +28,7 @@ - #undef TLS_NEEDS_GOT - #define TLS_NEEDS_GOT 1 - --#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "/ld.so.1" - #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" - - #if TARGET_BIG_ENDIAN_DEFAULT == 0 /* LE */ -@@ -38,7 +38,7 @@ - #endif - - #undef MUSL_DYNAMIC_LINKER --#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1" -+#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1" - - #undef SUBTARGET_EXTRA_SPECS - #define SUBTARGET_EXTRA_SPECS \ -diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h -index 230b7789bb8..d96d134bfcf 100644 ---- a/gcc/config/mips/linux.h -+++ b/gcc/config/mips/linux.h -@@ -22,29 +22,29 @@ along with GCC; see the file COPYING3. If not see - #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32" - - #define GLIBC_DYNAMIC_LINKER32 \ -- "%{mnan=2008:/lib/ld-linux-mipsn8.so.1;:/lib/ld.so.1}" -+ "%{mnan=2008:" SYSTEMLIBS_DIR "ld-linux-mipsn8.so.1;:" SYSTEMLIBS_DIR "ld.so.1}" - #define GLIBC_DYNAMIC_LINKER64 \ -- "%{mnan=2008:/lib64/ld-linux-mipsn8.so.1;:/lib64/ld.so.1}" -+ "%{mnan=2008:" SYSTEMLIBS_DIR "ld-linux-mipsn8.so.1;:" SYSTEMLIBS_DIR "ld.so.1}" - #define GLIBC_DYNAMIC_LINKERN32 \ -- "%{mnan=2008:/lib32/ld-linux-mipsn8.so.1;:/lib32/ld.so.1}" -+ "%{mnan=2008:" SYSTEMLIBS_DIR "ld-linux-mipsn8.so.1;:" SYSTEMLIBS_DIR "ld.so.1}" - - #undef UCLIBC_DYNAMIC_LINKER32 - #define UCLIBC_DYNAMIC_LINKER32 \ -- "%{mnan=2008:/lib/ld-uClibc-mipsn8.so.0;:/lib/ld-uClibc.so.0}" -+ "%{mnan=2008:" SYSTEMLIBS_DIR "ld-uClibc-mipsn8.so.0;:" SYSTEMLIBS_DIR "ld-uClibc.so.0}" - #undef UCLIBC_DYNAMIC_LINKER64 - #define UCLIBC_DYNAMIC_LINKER64 \ -- "%{mnan=2008:/lib/ld64-uClibc-mipsn8.so.0;:/lib/ld64-uClibc.so.0}" -+ "%{mnan=2008:" SYSTEMLIBS_DIR "ld64-uClibc-mipsn8.so.0;:" SYSTEMLIBS_DIR "ld64-uClibc.so.0}" - #define UCLIBC_DYNAMIC_LINKERN32 \ -- "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}" -+ "%{mnan=2008:" SYSTEMLIBS_DIR "ld-uClibc-mipsn8.so.0;:" SYSTEMLIBS_DIR "ld-uClibc.so.0}" - - #undef MUSL_DYNAMIC_LINKER32 - #define MUSL_DYNAMIC_LINKER32 \ -- "/lib/ld-musl-mips%{mips32r6|mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1" -+ SYSTEMLIBS_DIR "ld-musl-mips%{mips32r6|mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1" - #undef MUSL_DYNAMIC_LINKER64 - #define MUSL_DYNAMIC_LINKER64 \ -- "/lib/ld-musl-mips64%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1" -+ SYSTEMLIBS_DIR "ld-musl-mips64%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1" - #define MUSL_DYNAMIC_LINKERN32 \ -- "/lib/ld-musl-mipsn32%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1" -+ SYSTEMLIBS_DIR "ld-musl-mipsn32%{mips64r6:r6}%{EL:el}%{msoft-float:-sf}.so.1" - - #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32" - #define GNU_USER_DYNAMIC_LINKERN32 \ -diff --git a/gcc/config/nios2/linux.h b/gcc/config/nios2/linux.h -index f5dd813acad..7a13e1c9799 100644 ---- a/gcc/config/nios2/linux.h -+++ b/gcc/config/nios2/linux.h -@@ -29,8 +29,8 @@ - #undef CPP_SPEC - #define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" - --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-nios2.so.1" --#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-nios2.so.1" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux-nios2.so.1" -+#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-nios2.so.1" - - #undef LINK_SPEC - #define LINK_SPEC LINK_SPEC_ENDIAN \ -diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h -index 38803723ba9..d5ef8a96a19 100644 ---- a/gcc/config/riscv/linux.h -+++ b/gcc/config/riscv/linux.h -@@ -22,7 +22,7 @@ along with GCC; see the file COPYING3. If not see - GNU_USER_TARGET_OS_CPP_BUILTINS(); \ - } while (0) - --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-riscv" XLEN_SPEC "-" ABI_SPEC ".so.1" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux-riscv" XLEN_SPEC "-" ABI_SPEC ".so.1" - - #define MUSL_ABI_SUFFIX \ - "%{mabi=ilp32:-sf}" \ -@@ -33,7 +33,7 @@ along with GCC; see the file COPYING3. If not see - "%{mabi=lp64d:}" - - #undef MUSL_DYNAMIC_LINKER --#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX ".so.1" -+#define MUSL_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX ".so.1" - - /* Because RISC-V only has word-sized atomics, it requries libatomic where - others do not. So link libatomic by default, as needed. */ -diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h -index b2a7afabc73..364c1a5b155 100644 ---- a/gcc/config/rs6000/linux64.h -+++ b/gcc/config/rs6000/linux64.h -@@ -339,24 +339,19 @@ extern int dot_symbols; - #undef LINK_OS_DEFAULT_SPEC - #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" - --#define GLIBC_DYNAMIC_LINKER32 "%(dynamic_linker_prefix)/lib/ld.so.1" -- -+#define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld.so.1" - #ifdef LINUX64_DEFAULT_ABI_ELFv2 --#define GLIBC_DYNAMIC_LINKER64 \ --"%{mabi=elfv1:%(dynamic_linker_prefix)/lib64/ld64.so.1;" \ --":%(dynamic_linker_prefix)/lib64/ld64.so.2}" -+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:" SYSTEMLIBS_DIR "ld64.so.1;:" SYSTEMLIBS_DIR "ld64.so.2}" - #else --#define GLIBC_DYNAMIC_LINKER64 \ --"%{mabi=elfv2:%(dynamic_linker_prefix)/lib64/ld64.so.2;" \ --":%(dynamic_linker_prefix)/lib64/ld64.so.1}" -+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:" SYSTEMLIBS_DIR "ld64.so.2;:" SYSTEMLIBS_DIR "ld64.so.1}" - #endif - - #undef MUSL_DYNAMIC_LINKER32 - #define MUSL_DYNAMIC_LINKER32 \ -- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" -+ SYSTEMLIBS_DIR "ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" - #undef MUSL_DYNAMIC_LINKER64 - #define MUSL_DYNAMIC_LINKER64 \ -- "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" -+ SYSTEMLIBS_DIR "ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" - - #undef DEFAULT_ASM_ENDIAN - #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) -diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h -index 7e2519de5d4..a73954d9de5 100644 ---- a/gcc/config/rs6000/sysv4.h -+++ b/gcc/config/rs6000/sysv4.h -@@ -779,10 +779,10 @@ GNU_USER_TARGET_CC1_SPEC - - #define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","") - --#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld.so.1" - #undef MUSL_DYNAMIC_LINKER - #define MUSL_DYNAMIC_LINKER \ -- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" -+ SYSTEMLIBS_DIR "ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" - - #ifndef GNU_USER_DYNAMIC_LINKER - #define GNU_USER_DYNAMIC_LINKER GLIBC_DYNAMIC_LINKER -diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h -index d7b7e7a7b02..0139b4d06ca 100644 ---- a/gcc/config/s390/linux.h -+++ b/gcc/config/s390/linux.h -@@ -72,13 +72,13 @@ along with GCC; see the file COPYING3. If not see - #define MULTILIB_DEFAULTS { "m31" } - #endif - --#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" --#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" -+#define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld.so.1" -+#define GLIBC_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld64.so.1" - - #undef MUSL_DYNAMIC_LINKER32 --#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" -+#define MUSL_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-musl-s390.so.1" - #undef MUSL_DYNAMIC_LINKER64 --#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" -+#define MUSL_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld-musl-s390x.so.1" - - #undef LINK_SPEC - #define LINK_SPEC \ -diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h -index d96d077c99e..7d27f9893ee 100644 ---- a/gcc/config/sh/linux.h -+++ b/gcc/config/sh/linux.h -@@ -61,10 +61,10 @@ along with GCC; see the file COPYING3. If not see - - #undef MUSL_DYNAMIC_LINKER - #define MUSL_DYNAMIC_LINKER \ -- "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \ -+ SYSTEMLIBS_DIR "ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \ - "%{mfdpic:-fdpic}.so.1" - --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux.so.2" - - #undef SUBTARGET_LINK_EMUL_SUFFIX - #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd;:_linux}" -diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h -index 6a809e9092d..60603765ad6 100644 ---- a/gcc/config/sparc/linux.h -+++ b/gcc/config/sparc/linux.h -@@ -78,7 +78,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); - When the -shared link option is used a final link is not being - done. */ - --#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" -+#define GLIBC_DYNAMIC_LINKER SYSTEMLIBS_DIR "ld-linux.so.2" - - #undef LINK_SPEC - #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \ -diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h -index d08a2ef96fe..e6955da0a5b 100644 ---- a/gcc/config/sparc/linux64.h -+++ b/gcc/config/sparc/linux64.h -@@ -78,8 +78,8 @@ along with GCC; see the file COPYING3. If not see - When the -shared link option is used a final link is not being - done. */ - --#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2" --#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2" -+#define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld-linux.so.2" -+#define GLIBC_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld-linux.so.2" - - #ifdef SPARC_BI_ARCH - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0008-libtool.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0008-libtool.patch deleted file mode 100644 index c9bc38cc..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0008-libtool.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 5117519c1897a49b09fe7fff213b9c2ea15d37f5 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:29:11 +0400 -Subject: [PATCH] libtool - -libstdc++ from gcc-runtime gets created with -rpath=/usr/lib/../lib for qemux86-64 -when running on am x86_64 build host. - -This patch stops this speading to libdir in the libstdc++.la file within libtool. -Arguably, it shouldn't be passing this into libtool in the first place but -for now this resolves the nastiest problems this causes. - -func_normal_abspath would resolve an empty path to `pwd` so we need -to filter the zero case. - -RP 2012/8/24 - -Signed-off-by: Khem Raj - -Upstream-Status: Pending ---- - ltmain.sh | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/ltmain.sh b/ltmain.sh -index 70990740b6c..ee938056bef 100644 ---- a/ltmain.sh -+++ b/ltmain.sh -@@ -6359,6 +6359,10 @@ func_mode_link () - func_warning "ignoring multiple \`-rpath's for a libtool library" - - install_libdir="$1" -+ if test -n "$install_libdir"; then -+ func_normal_abspath "$install_libdir" -+ install_libdir=$func_normal_abspath_result -+ fi - - oldlibs= - if test -z "$rpath"; then diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0009-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0009-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch deleted file mode 100644 index dd67b115..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0009-gcc-armv4-pass-fix-v4bx-to-linker-to-support-EABI.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 32129f9682d0d27fc67af10f077ad2768935cbe6 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:30:32 +0400 -Subject: [PATCH] gcc: armv4: pass fix-v4bx to linker to support EABI. - -The LINK_SPEC for linux gets overwritten by linux-eabi.h which -means the value of TARGET_FIX_V4BX_SPEC gets lost and as a result -the option is not passed to linker when chosing march=armv4 -This patch redefines this in linux-eabi.h and reinserts it -for eabi defaulting toolchains. - -We might want to send it upstream. - -Signed-off-by: Khem Raj - -Upstream-Status: Pending ---- - gcc/config/arm/linux-eabi.h | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h -index 17c18b27145..8eacb099317 100644 ---- a/gcc/config/arm/linux-eabi.h -+++ b/gcc/config/arm/linux-eabi.h -@@ -91,10 +91,14 @@ - #define MUSL_DYNAMIC_LINKER \ - SYSTEMLIBS_DIR "ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1" - -+/* For armv4 we pass --fix-v4bx to linker to support EABI */ -+#undef TARGET_FIX_V4BX_SPEC -+#define TARGET_FIX_V4BX_SPEC "%{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4: --fix-v4bx}" -+ - /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to - use the GNU/Linux version, not the generic BPABI version. */ - #undef LINK_SPEC --#define LINK_SPEC EABI_LINK_SPEC \ -+#define LINK_SPEC TARGET_FIX_V4BX_SPEC EABI_LINK_SPEC \ - LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ - LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0010-Use-the-multilib-config-files-from-B-instead-of-usin.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0010-Use-the-multilib-config-files-from-B-instead-of-usin.patch deleted file mode 100644 index 45edc62e..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0010-Use-the-multilib-config-files-from-B-instead-of-usin.patch +++ /dev/null @@ -1,99 +0,0 @@ -From bf85b8bbcb4b77725d4c22c1bb25a29f6ff21038 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:33:04 +0400 -Subject: [PATCH] Use the multilib config files from ${B} instead of using the - ones from ${S} - -Use the multilib config files from ${B} instead of using the ones from ${S} -so that the source can be shared between gcc-cross-initial, -gcc-cross-intermediate, gcc-cross, gcc-runtime, and also the sdk build. - -Signed-off-by: Khem Raj -Signed-off-by: Constantin Musca - -Upstream-Status: Inappropriate [configuration] ---- - gcc/configure | 22 ++++++++++++++++++---- - gcc/configure.ac | 22 ++++++++++++++++++---- - 2 files changed, 36 insertions(+), 8 deletions(-) - -diff --git a/gcc/configure b/gcc/configure -index 3fc0e2f5813..2f0f0e057a9 100755 ---- a/gcc/configure -+++ b/gcc/configure -@@ -13361,10 +13361,20 @@ done - tmake_file_= - for f in ${tmake_file} - do -- if test -f ${srcdir}/config/$f -- then -- tmake_file_="${tmake_file_} \$(srcdir)/config/$f" -- fi -+ case $f in -+ */t-linux64 ) -+ if test -f ./config/$f -+ then -+ tmake_file_="${tmake_file_} ./config/$f" -+ fi -+ ;; -+ * ) -+ if test -f ${srcdir}/config/$f -+ then -+ tmake_file_="${tmake_file_} \$(srcdir)/config/$f" -+ fi -+ ;; -+ esac - done - tmake_file="${tmake_file_}${omp_device_property_tmake_file}" - -@@ -13375,6 +13385,10 @@ tm_file_list="options.h" - tm_include_list="options.h insn-constants.h" - for f in $tm_file; do - case $f in -+ */linux64.h ) -+ tm_file_list="${tm_file_list} ./config/$f" -+ tm_include_list="${tm_include_list} ./config/$f" -+ ;; - ./* ) - f=`echo $f | sed 's/^..//'` - tm_file_list="${tm_file_list} $f" -diff --git a/gcc/configure.ac b/gcc/configure.ac -index 46de496b256..6155b83a732 100644 ---- a/gcc/configure.ac -+++ b/gcc/configure.ac -@@ -2312,10 +2312,20 @@ done - tmake_file_= - for f in ${tmake_file} - do -- if test -f ${srcdir}/config/$f -- then -- tmake_file_="${tmake_file_} \$(srcdir)/config/$f" -- fi -+ case $f in -+ */t-linux64 ) -+ if test -f ./config/$f -+ then -+ tmake_file_="${tmake_file_} ./config/$f" -+ fi -+ ;; -+ * ) -+ if test -f ${srcdir}/config/$f -+ then -+ tmake_file_="${tmake_file_} \$(srcdir)/config/$f" -+ fi -+ ;; -+ esac - done - tmake_file="${tmake_file_}${omp_device_property_tmake_file}" - -@@ -2326,6 +2336,10 @@ tm_file_list="options.h" - tm_include_list="options.h insn-constants.h" - for f in $tm_file; do - case $f in -+ */linux64.h ) -+ tm_file_list="${tm_file_list} ./config/$f" -+ tm_include_list="${tm_include_list} ./config/$f" -+ ;; - ./* ) - f=`echo $f | sed 's/^..//'` - tm_file_list="${tm_file_list} $f" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0011-Avoid-using-libdir-from-.la-which-usually-points-to-.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0011-Avoid-using-libdir-from-.la-which-usually-points-to-.patch deleted file mode 100644 index 352c6eec..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0011-Avoid-using-libdir-from-.la-which-usually-points-to-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From e5463727ff028cee5e452da38f5b4c44d52e412e Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 20 Feb 2015 09:39:38 +0000 -Subject: [PATCH] Avoid using libdir from .la which usually points to a host - path - -Upstream-Status: Inappropriate [embedded specific] - -Signed-off-by: Jonathan Liu -Signed-off-by: Khem Raj ---- - ltmain.sh | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/ltmain.sh b/ltmain.sh -index ee938056bef..9ebc7e3d1e0 100644 ---- a/ltmain.sh -+++ b/ltmain.sh -@@ -5628,6 +5628,9 @@ func_mode_link () - absdir="$abs_ladir" - libdir="$abs_ladir" - else -+ # Instead of using libdir from .la which usually points to a host path, -+ # use the path the .la is contained in. -+ libdir="$abs_ladir" - dir="$libdir" - absdir="$libdir" - fi diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0011-aarch64-Fix-include-paths-when-S-B.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0011-aarch64-Fix-include-paths-when-S-B.patch deleted file mode 100644 index f52e21ed..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0011-aarch64-Fix-include-paths-when-S-B.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 710d1325474e708e6b34eebe09f3f130420af293 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Tue, 31 Jan 2023 22:03:38 -0800 -Subject: [PATCH] aarch64: Fix include paths when S != B - -aarch64.h gets copied into build directory when built out of tree, in -this case build uses this file but does not find the includes inside it -since they are not found in any of include paths specified in compiler -cmdline. - -Fixes build errors like - -% g++ -c -isystem/mnt/b/yoe/master/build/tmp/work/x86_64-linux/gcc-cross-aarch64/13.0.1-r0/recipe-sysroot-native/usr/include -O2 -pipe -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -Wconditionally-supported -Woverloaded-virtual -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -DHAVE_CONFIG_H -DGENERATOR_FILE -I. -Ibuild -I../../../../../../../work-shared/gcc-13.0.1-r0/gcc-b2ec2504af77b35e748067eeb846821d12a6b6b4/gcc -I../../../../../../../work-shared/gcc-13.0.1-r0/gcc-b2ec2504af77b35e748067eeb846821d12a6b6b4/gcc/build -I../../../../../../../work-shared/gcc-13.0.1-r0/gcc-b2ec2504af77b35e748067eeb846821d12a6b6b4/gcc/../include -I../../../../../../../work-shared/gcc-13.0.1-r0/gcc-b2ec2504af77b35e748067eeb846821d12a6b6b4/gcc/../libcpp/include -o build/gencheck.o ../../../../../../../work-shared/gcc-13.0.1-r0/gcc-b2ec2504af77b35e748067eeb846821d12a6b6b4/gcc/gencheck.cc -In file included from ./tm.h:34, - from ../../../../../../../work-shared/gcc-13.0.1-r0/gcc-b2ec2504af77b35e748067eeb846821d12a6b6b4/gcc/gencheck.cc:23: -./config/aarch64/aarch64.h:164:10: fatal error: aarch64-option-extensions.def: No such file or directory - 164 | #include "aarch64-option-extensions.def" - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -compilation terminated. - -See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105144 - -Upstream-Status: Pending - -Signed-off-by: Khem Raj ---- - gcc/config/aarch64/aarch64.h | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h -index 155cace6afe..07d68958908 100644 ---- a/gcc/config/aarch64/aarch64.h -+++ b/gcc/config/aarch64/aarch64.h -@@ -161,8 +161,8 @@ - enum class aarch64_feature : unsigned char { - #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) IDENT, - #define AARCH64_ARCH(A, B, IDENT, D, E) IDENT, --#include "aarch64-option-extensions.def" --#include "aarch64-arches.def" -+#include "config/aarch64/aarch64-option-extensions.def" -+#include "config/aarch64/aarch64-arches.def" - }; - - /* Define unique flags for each of the above. */ -@@ -171,8 +171,8 @@ enum class aarch64_feature : unsigned char { - = aarch64_feature_flags (1) << int (aarch64_feature::IDENT); - #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) HANDLE (IDENT) - #define AARCH64_ARCH(A, B, IDENT, D, E) HANDLE (IDENT) --#include "aarch64-option-extensions.def" --#include "aarch64-arches.def" -+#include "config/aarch64/aarch64-option-extensions.def" -+#include "config/aarch64/aarch64-arches.def" - #undef HANDLE - - #endif diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0012-Avoid-using-libdir-from-.la-which-usually-points-to-.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0012-Avoid-using-libdir-from-.la-which-usually-points-to-.patch deleted file mode 100644 index b05be59c..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0012-Avoid-using-libdir-from-.la-which-usually-points-to-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From e8e8a0ab572cfceb9758f99599c0db4c962e49c0 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 20 Feb 2015 09:39:38 +0000 -Subject: [PATCH] Avoid using libdir from .la which usually points to a host - path - -Upstream-Status: Inappropriate [embedded specific] - -Signed-off-by: Jonathan Liu -Signed-off-by: Khem Raj ---- - ltmain.sh | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/ltmain.sh b/ltmain.sh -index ee938056bef..9ebc7e3d1e0 100644 ---- a/ltmain.sh -+++ b/ltmain.sh -@@ -5628,6 +5628,9 @@ func_mode_link () - absdir="$abs_ladir" - libdir="$abs_ladir" - else -+ # Instead of using libdir from .la which usually points to a host path, -+ # use the path the .la is contained in. -+ libdir="$abs_ladir" - dir="$libdir" - absdir="$libdir" - fi diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0013-Ensure-target-gcc-headers-can-be-included.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0013-Ensure-target-gcc-headers-can-be-included.patch deleted file mode 100644 index 61e61ecc..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0013-Ensure-target-gcc-headers-can-be-included.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 612801d426e75ff997cfabda380dbe52c2cbc532 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 20 Feb 2015 10:25:11 +0000 -Subject: [PATCH] Ensure target gcc headers can be included - -There are a few headers installed as part of the OpenEmbedded -gcc-runtime target (omp.h, ssp/*.h). Being installed from a recipe -built for the target architecture, these are within the target -sysroot and not cross/nativesdk; thus they weren't able to be -found by gcc with the existing search paths. Add support for -picking up these headers under the sysroot supplied on the gcc -command line in order to resolve this. - -Extend target gcc headers search to musl too - -Upstream-Status: Pending - -Signed-off-by: Paul Eggleton -Signed-off-by: Khem Raj ---- - gcc/Makefile.in | 2 ++ - gcc/config/linux.h | 8 ++++++++ - gcc/config/rs6000/sysv4.h | 8 ++++++++ - gcc/cppdefault.cc | 4 ++++ - 4 files changed, 22 insertions(+) - -diff --git a/gcc/Makefile.in b/gcc/Makefile.in -index a8277254696..07fa63b6640 100644 ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -632,6 +632,7 @@ libexecdir = @libexecdir@ - - # Directory in which the compiler finds libraries etc. - libsubdir = $(libdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix) -+libsubdir_target = $(target_noncanonical)/$(version) - # Directory in which the compiler finds executables - libexecsubdir = $(libexecdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix) - # Directory in which all plugin resources are installed -@@ -3024,6 +3025,7 @@ CFLAGS-intl.o += -DLOCALEDIR=\"$(localedir)\" - - PREPROCESSOR_DEFINES = \ - -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ -+ -DGCC_INCLUDE_SUBDIR_TARGET=\"$(libsubdir_target)/include\" \ - -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \ - -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \ - -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \ -diff --git a/gcc/config/linux.h b/gcc/config/linux.h -index 4ce173384ef..8a3cd4f2d34 100644 ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -170,6 +170,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - #define INCLUDE_DEFAULTS_MUSL_TOOL - #endif - -+#ifdef GCC_INCLUDE_SUBDIR_TARGET -+#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ -+ { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0}, -+#else -+#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET -+#endif -+ - #ifdef NATIVE_SYSTEM_HEADER_DIR - #define INCLUDE_DEFAULTS_MUSL_NATIVE \ - { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \ -@@ -196,6 +203,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - INCLUDE_DEFAULTS_MUSL_PREFIX \ - INCLUDE_DEFAULTS_MUSL_CROSS \ - INCLUDE_DEFAULTS_MUSL_TOOL \ -+ INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ - INCLUDE_DEFAULTS_MUSL_NATIVE \ - { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \ - { 0, 0, 0, 0, 0, 0 } \ -diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h -index a73954d9de5..e5dd6538358 100644 ---- a/gcc/config/rs6000/sysv4.h -+++ b/gcc/config/rs6000/sysv4.h -@@ -994,6 +994,13 @@ ncrtn.o%s" - #define INCLUDE_DEFAULTS_MUSL_TOOL - #endif - -+#ifdef GCC_INCLUDE_SUBDIR_TARGET -+#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ -+ { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0}, -+#else -+#define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET -+#endif -+ - #ifdef NATIVE_SYSTEM_HEADER_DIR - #define INCLUDE_DEFAULTS_MUSL_NATIVE \ - { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \ -@@ -1020,6 +1027,7 @@ ncrtn.o%s" - INCLUDE_DEFAULTS_MUSL_PREFIX \ - INCLUDE_DEFAULTS_MUSL_CROSS \ - INCLUDE_DEFAULTS_MUSL_TOOL \ -+ INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ - INCLUDE_DEFAULTS_MUSL_NATIVE \ - { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \ - { 0, 0, 0, 0, 0, 0 } \ -diff --git a/gcc/cppdefault.cc b/gcc/cppdefault.cc -index 7888300f277..52cf14e92f8 100644 ---- a/gcc/cppdefault.cc -+++ b/gcc/cppdefault.cc -@@ -64,6 +64,10 @@ const struct default_include cpp_include_defaults[] - /* This is the dir for gcc's private headers. */ - { GCC_INCLUDE_DIR, "GCC", 0, 0, 0, 0 }, - #endif -+#ifdef GCC_INCLUDE_SUBDIR_TARGET -+ /* This is the dir for gcc's private headers under the specified sysroot. */ -+ { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0 }, -+#endif - #ifdef LOCAL_INCLUDE_DIR - /* /usr/local/include comes before the fixincluded header files. */ - { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0014-Don-t-search-host-directory-during-relink-if-inst_pr.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0014-Don-t-search-host-directory-during-relink-if-inst_pr.patch deleted file mode 100644 index 94308b2a..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0014-Don-t-search-host-directory-during-relink-if-inst_pr.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9ae49e7b88c208ab79ec9c2fc4a2fa8a3f1e85bb Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Tue, 3 Mar 2015 08:21:19 +0000 -Subject: [PATCH] Don't search host directory during "relink" if $inst_prefix - is provided - -http://lists.gnu.org/archive/html/libtool-patches/2011-01/msg00026.html - -Upstream-Status: Submitted - -Signed-off-by: Khem Raj ---- - ltmain.sh | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/ltmain.sh b/ltmain.sh -index 9ebc7e3d1e0..7ea79fa8be6 100644 ---- a/ltmain.sh -+++ b/ltmain.sh -@@ -6004,12 +6004,13 @@ func_mode_link () - fi - else - # We cannot seem to hardcode it, guess we'll fake it. -+ # Default if $libdir is not relative to the prefix: - add_dir="-L$libdir" -- # Try looking first in the location we're being installed to. -+ - if test -n "$inst_prefix_dir"; then - case $libdir in - [\\/]*) -- add_dir="$add_dir -L$inst_prefix_dir$libdir" -+ add_dir="-L$inst_prefix_dir$libdir" - ;; - esac - fi diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0015-libcc1-fix-libcc1-s-install-path-and-rpath.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0015-libcc1-fix-libcc1-s-install-path-and-rpath.patch deleted file mode 100644 index ce9635ce..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0015-libcc1-fix-libcc1-s-install-path-and-rpath.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bf918db7117f41d3c04162095641165ca241707d Mon Sep 17 00:00:00 2001 -From: Robert Yang -Date: Sun, 5 Jul 2015 20:25:18 -0700 -Subject: [PATCH] libcc1: fix libcc1's install path and rpath - -* Install libcc1.so and libcc1plugin.so into - $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version), as what we - had done to lto-plugin. -* Fix bad RPATH iussue: - gcc-5.2.0: package gcc-plugins contains bad RPATH /patht/to/tmp/sysroots/qemux86-64/usr/lib64/../lib64 in file - /path/to/gcc/5.2.0-r0/packages-split/gcc-plugins/usr/lib64/gcc/x86_64-poky-linux/5.2.0/plugin/libcc1plugin.so.0.0.0 - [rpaths] - -Upstream-Status: Inappropriate [OE configuration] - -Signed-off-by: Robert Yang ---- - libcc1/Makefile.am | 4 ++-- - libcc1/Makefile.in | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/libcc1/Makefile.am b/libcc1/Makefile.am -index 6e3a34ff7e2..3f3f6391aba 100644 ---- a/libcc1/Makefile.am -+++ b/libcc1/Makefile.am -@@ -40,8 +40,8 @@ libiberty = $(if $(wildcard $(libiberty_noasan)),$(Wc)$(libiberty_noasan), \ - $(Wc)$(libiberty_normal))) - libiberty_dep = $(patsubst $(Wc)%,%,$(libiberty)) - --plugindir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/plugin --cc1libdir = $(libdir)/$(libsuffix) -+cc1libdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) -+plugindir = $(cc1libdir) - - if ENABLE_PLUGIN - plugin_LTLIBRARIES = libcc1plugin.la libcp1plugin.la -diff --git a/libcc1/Makefile.in b/libcc1/Makefile.in -index f8f590d71e9..56462492045 100644 ---- a/libcc1/Makefile.in -+++ b/libcc1/Makefile.in -@@ -396,8 +396,8 @@ libiberty = $(if $(wildcard $(libiberty_noasan)),$(Wc)$(libiberty_noasan), \ - $(Wc)$(libiberty_normal))) - - libiberty_dep = $(patsubst $(Wc)%,%,$(libiberty)) --plugindir = $(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/plugin --cc1libdir = $(libdir)/$(libsuffix) -+cc1libdir = $(libexecdir)/gcc/$(target_noncanonical)/$(gcc_version) -+plugindir = $(cc1libdir) - @ENABLE_PLUGIN_TRUE@plugin_LTLIBRARIES = libcc1plugin.la libcp1plugin.la - @ENABLE_PLUGIN_TRUE@cc1lib_LTLIBRARIES = libcc1.la - shared_source = callbacks.cc callbacks.hh connection.cc connection.hh \ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0016-handle-sysroot-support-for-nativesdk-gcc.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0016-handle-sysroot-support-for-nativesdk-gcc.patch deleted file mode 100644 index 3b547195..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0016-handle-sysroot-support-for-nativesdk-gcc.patch +++ /dev/null @@ -1,510 +0,0 @@ -From 4fbbd40d7db89cdbeaf93df1e1da692b1f80a5bc Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Mon, 7 Dec 2015 23:39:54 +0000 -Subject: [PATCH] handle sysroot support for nativesdk-gcc - -Being able to build a nativesdk gcc is useful, particularly in cases -where the host compiler may be of an incompatible version (or a 32 -bit compiler is needed). - -Sadly, building nativesdk-gcc is not straight forward. We install -nativesdk-gcc into a relocatable location and this means that its -library locations can change. "Normal" sysroot support doesn't help -in this case since the values of paths like "libdir" change, not just -base root directory of the system. - -In order to handle this we do two things: - -a) Add %r into spec file markup which can be used for injected paths - such as SYSTEMLIBS_DIR (see gcc_multilib_setup()). -b) Add other paths which need relocation into a .gccrelocprefix section - which the relocation code will notice and adjust automatically. - -Upstream-Status: Inappropriate -RP 2015/7/28 - -Extend the gccrelocprefix support to musl config too, this ensures -that gcc will get right bits in SDK installations - -Signed-off-by: Khem Raj - -Added PREFIXVAR and EXEC_PREFIXVAR to support runtime relocation. Without -these as part of the gccrelocprefix the system can't do runtime relocation -if the executable is moved. (These paths were missed in the original -implementation.) - -Signed-off-by: Mark Hatle ---- - gcc/c-family/c-opts.cc | 4 +-- - gcc/config/linux.h | 24 +++++++-------- - gcc/config/rs6000/sysv4.h | 24 +++++++-------- - gcc/cppdefault.cc | 63 ++++++++++++++++++++++++--------------- - gcc/cppdefault.h | 13 ++++---- - gcc/gcc.cc | 20 +++++++++---- - gcc/incpath.cc | 12 ++++---- - gcc/prefix.cc | 6 ++-- - 8 files changed, 94 insertions(+), 72 deletions(-) - -diff --git a/gcc/c-family/c-opts.cc b/gcc/c-family/c-opts.cc -index a341a061758..83b0bef4dbb 100644 ---- a/gcc/c-family/c-opts.cc -+++ b/gcc/c-family/c-opts.cc -@@ -1458,8 +1458,8 @@ add_prefixed_path (const char *suffix, incpath_kind chain) - size_t prefix_len, suffix_len; - - suffix_len = strlen (suffix); -- prefix = iprefix ? iprefix : cpp_GCC_INCLUDE_DIR; -- prefix_len = iprefix ? strlen (iprefix) : cpp_GCC_INCLUDE_DIR_len; -+ prefix = iprefix ? iprefix : GCC_INCLUDE_DIRVAR; -+ prefix_len = iprefix ? strlen (iprefix) : strlen(GCC_INCLUDE_DIRVAR) - 7; - - path = (char *) xmalloc (prefix_len + suffix_len + 1); - memcpy (path, prefix, prefix_len); -diff --git a/gcc/config/linux.h b/gcc/config/linux.h -index 8a3cd4f2d34..58143dff731 100644 ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -134,53 +134,53 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - * Unfortunately, this is mostly duplicated from cppdefault.cc */ - #if DEFAULT_LIBC == LIBC_MUSL - #define INCLUDE_DEFAULTS_MUSL_GPP \ -- { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \ -+ { GPLUSPLUS_INCLUDE_DIRVAR, "G++", 1, 1, \ - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \ -- { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \ -+ { GPLUSPLUS_TOOL_INCLUDE_DIRVAR, "G++", 1, 1, \ - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \ -- { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \ -+ { GPLUSPLUS_BACKWARD_INCLUDE_DIRVAR, "G++", 1, 1, \ - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, - - #ifdef LOCAL_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_LOCAL \ -- { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \ -- { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, -+ { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 2 }, \ -+ { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 0 }, - #else - #define INCLUDE_DEFAULTS_MUSL_LOCAL - #endif - - #ifdef PREFIX_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_PREFIX \ -- { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0}, -+ { PREFIX_INCLUDE_DIRVAR, 0, 0, 1, 0, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_PREFIX - #endif - - #ifdef CROSS_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_CROSS \ -- { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0}, -+ { CROSS_INCLUDE_DIRVAR, "GCC", 0, 0, 0, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_CROSS - #endif - - #ifdef TOOL_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_TOOL \ -- { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0}, -+ { TOOL_INCLUDE_DIRVAR, "BINUTILS", 0, 1, 0, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_TOOL - #endif - - #ifdef GCC_INCLUDE_SUBDIR_TARGET - #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ -- { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0}, -+ { STANDARD_STARTFILE_PREFIX_2VAR, "GCC", 0, 0, 1, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET - #endif - - #ifdef NATIVE_SYSTEM_HEADER_DIR - #define INCLUDE_DEFAULTS_MUSL_NATIVE \ -- { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \ -- { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 }, -+ { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 2 }, \ -+ { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 0 }, - #else - #define INCLUDE_DEFAULTS_MUSL_NATIVE - #endif -@@ -205,7 +205,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - INCLUDE_DEFAULTS_MUSL_TOOL \ - INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ - INCLUDE_DEFAULTS_MUSL_NATIVE \ -- { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \ -+ { GCC_INCLUDE_DIRVAR, "GCC", 0, 1, 0, 0 }, \ - { 0, 0, 0, 0, 0, 0 } \ - } - #endif -diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h -index e5dd6538358..b496849b792 100644 ---- a/gcc/config/rs6000/sysv4.h -+++ b/gcc/config/rs6000/sysv4.h -@@ -958,53 +958,53 @@ ncrtn.o%s" - /* Include order changes for musl, same as in generic linux.h. */ - #if DEFAULT_LIBC == LIBC_MUSL - #define INCLUDE_DEFAULTS_MUSL_GPP \ -- { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \ -+ { GPLUSPLUS_INCLUDE_DIRVAR, "G++", 1, 1, \ - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \ -- { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \ -+ { GPLUSPLUS_TOOL_INCLUDE_DIRVAR, "G++", 1, 1, \ - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \ -- { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \ -+ { GPLUSPLUS_BACKWARD_INCLUDE_DIRVAR, "G++", 1, 1, \ - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, - - #ifdef LOCAL_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_LOCAL \ -- { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \ -- { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, -+ { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 2 }, \ -+ { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 0 }, - #else - #define INCLUDE_DEFAULTS_MUSL_LOCAL - #endif - - #ifdef PREFIX_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_PREFIX \ -- { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0}, -+ { PREFIX_INCLUDE_DIRVAR, 0, 0, 1, 0, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_PREFIX - #endif - - #ifdef CROSS_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_CROSS \ -- { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0}, -+ { CROSS_INCLUDE_DIRVAR, "GCC", 0, 0, 0, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_CROSS - #endif - - #ifdef TOOL_INCLUDE_DIR - #define INCLUDE_DEFAULTS_MUSL_TOOL \ -- { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0}, -+ { TOOL_INCLUDE_DIRVAR, "BINUTILS", 0, 1, 0, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_TOOL - #endif - - #ifdef GCC_INCLUDE_SUBDIR_TARGET - #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ -- { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0}, -+ { STANDARD_STARTFILE_PREFIX_2VAR, "GCC", 0, 0, 1, 0}, - #else - #define INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET - #endif - - #ifdef NATIVE_SYSTEM_HEADER_DIR - #define INCLUDE_DEFAULTS_MUSL_NATIVE \ -- { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \ -- { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 }, -+ { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 2 }, \ -+ { NATIVE_SYSTEM_HEADER_DIRVAR, 0, 0, 0, 1, 0 }, - #else - #define INCLUDE_DEFAULTS_MUSL_NATIVE - #endif -@@ -1029,7 +1029,7 @@ ncrtn.o%s" - INCLUDE_DEFAULTS_MUSL_TOOL \ - INCLUDE_DEFAULTS_MUSL_SUBDIR_TARGET \ - INCLUDE_DEFAULTS_MUSL_NATIVE \ -- { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \ -+ { GCC_INCLUDE_DIRVAR, "GCC", 0, 1, 0, 0 }, \ - { 0, 0, 0, 0, 0, 0 } \ - } - #endif -diff --git a/gcc/cppdefault.cc b/gcc/cppdefault.cc -index 52cf14e92f8..d8977afc05e 100644 ---- a/gcc/cppdefault.cc -+++ b/gcc/cppdefault.cc -@@ -35,6 +35,30 @@ - # undef CROSS_INCLUDE_DIR - #endif - -+static char GPLUSPLUS_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = GPLUSPLUS_INCLUDE_DIR; -+char GCC_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = GCC_INCLUDE_DIR; -+static char GPLUSPLUS_TOOL_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = GPLUSPLUS_TOOL_INCLUDE_DIR; -+static char GPLUSPLUS_BACKWARD_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = GPLUSPLUS_BACKWARD_INCLUDE_DIR; -+static char STANDARD_STARTFILE_PREFIX_2VAR[4096] __attribute__ ((section (".gccrelocprefix"))) = STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET; -+#ifdef LOCAL_INCLUDE_DIR -+static char LOCAL_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = LOCAL_INCLUDE_DIR; -+#endif -+#ifdef PREFIX_INCLUDE_DIR -+static char PREFIX_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = PREFIX_INCLUDE_DIR; -+#endif -+#ifdef FIXED_INCLUDE_DIR -+static char FIXED_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = FIXED_INCLUDE_DIR; -+#endif -+#ifdef CROSS_INCLUDE_DIR -+static char CROSS_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = CROSS_INCLUDE_DIR; -+#endif -+#ifdef TOOL_INCLUDE_DIR -+static char TOOL_INCLUDE_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = TOOL_INCLUDE_DIR; -+#endif -+#ifdef NATIVE_SYSTEM_HEADER_DIR -+static char NATIVE_SYSTEM_HEADER_DIRVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = NATIVE_SYSTEM_HEADER_DIR; -+#endif -+ - const struct default_include cpp_include_defaults[] - #ifdef INCLUDE_DEFAULTS - = INCLUDE_DEFAULTS; -@@ -42,17 +66,17 @@ const struct default_include cpp_include_defaults[] - = { - #ifdef GPLUSPLUS_INCLUDE_DIR - /* Pick up GNU C++ generic include files. */ -- { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, -+ { GPLUSPLUS_INCLUDE_DIRVAR, "G++", 1, 1, - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, - #endif - #ifdef GPLUSPLUS_TOOL_INCLUDE_DIR - /* Pick up GNU C++ target-dependent include files. */ -- { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, -+ { GPLUSPLUS_TOOL_INCLUDE_DIRVAR, "G++", 1, 1, - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, - #endif - #ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR - /* Pick up GNU C++ backward and deprecated include files. */ -- { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, -+ { GPLUSPLUS_BACKWARD_INCLUDE_DIRVAR, "G++", 1, 1, - GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, - #endif - #ifdef GPLUSPLUS_LIBCXX_INCLUDE_DIR -@@ -62,23 +86,23 @@ const struct default_include cpp_include_defaults[] - #endif - #ifdef GCC_INCLUDE_DIR - /* This is the dir for gcc's private headers. */ -- { GCC_INCLUDE_DIR, "GCC", 0, 0, 0, 0 }, -+ { GCC_INCLUDE_DIRVAR, "GCC", 0, 0, 0, 0 }, - #endif - #ifdef GCC_INCLUDE_SUBDIR_TARGET - /* This is the dir for gcc's private headers under the specified sysroot. */ -- { STANDARD_STARTFILE_PREFIX_2 GCC_INCLUDE_SUBDIR_TARGET, "GCC", 0, 0, 1, 0 }, -+ { STANDARD_STARTFILE_PREFIX_2VAR, "GCC", 0, 0, 1, 0 }, - #endif - #ifdef LOCAL_INCLUDE_DIR - /* /usr/local/include comes before the fixincluded header files. */ -- { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, -- { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, -+ { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 2 }, -+ { LOCAL_INCLUDE_DIRVAR, 0, 0, 1, 1, 0 }, - #endif - #ifdef PREFIX_INCLUDE_DIR -- { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0 }, -+ { PREFIX_INCLUDE_DIRVAR, 0, 0, 1, 0, 0 }, - #endif - #ifdef FIXED_INCLUDE_DIR - /* This is the dir for fixincludes. */ -- { FIXED_INCLUDE_DIR, "GCC", 0, 0, 0, -+ { FIXED_INCLUDE_DIRVAR, "GCC", 0, 0, 0, - /* A multilib suffix needs adding if different multilibs use - different headers. */ - #ifdef SYSROOT_HEADERS_SUFFIX_SPEC -@@ -90,33 +114,24 @@ const struct default_include cpp_include_defaults[] - #endif - #ifdef CROSS_INCLUDE_DIR - /* One place the target system's headers might be. */ -- { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0 }, -+ { CROSS_INCLUDE_DIRVAR, "GCC", 0, 0, 0, 0 }, - #endif - #ifdef TOOL_INCLUDE_DIR - /* Another place the target system's headers might be. */ -- { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0 }, -+ { TOOL_INCLUDE_DIRVAR, "BINUTILS", 0, 1, 0, 0 }, - #endif - #ifdef NATIVE_SYSTEM_HEADER_DIR - /* /usr/include comes dead last. */ -- { NATIVE_SYSTEM_HEADER_DIR, NATIVE_SYSTEM_HEADER_COMPONENT, 0, 0, 1, 2 }, -- { NATIVE_SYSTEM_HEADER_DIR, NATIVE_SYSTEM_HEADER_COMPONENT, 0, 0, 1, 0 }, -+ { NATIVE_SYSTEM_HEADER_DIRVAR, NATIVE_SYSTEM_HEADER_COMPONENT, 0, 0, 1, 2 }, -+ { NATIVE_SYSTEM_HEADER_DIRVAR, NATIVE_SYSTEM_HEADER_COMPONENT, 0, 0, 1, 0 }, - #endif - { 0, 0, 0, 0, 0, 0 } - }; - #endif /* no INCLUDE_DEFAULTS */ - --#ifdef GCC_INCLUDE_DIR --const char cpp_GCC_INCLUDE_DIR[] = GCC_INCLUDE_DIR; --const size_t cpp_GCC_INCLUDE_DIR_len = sizeof GCC_INCLUDE_DIR - 8; --#else --const char cpp_GCC_INCLUDE_DIR[] = ""; --const size_t cpp_GCC_INCLUDE_DIR_len = 0; --#endif -- - /* The configured prefix. */ --const char cpp_PREFIX[] = PREFIX; --const size_t cpp_PREFIX_len = sizeof PREFIX - 1; --const char cpp_EXEC_PREFIX[] = STANDARD_EXEC_PREFIX; -+char PREFIXVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = PREFIX; -+char EXEC_PREFIXVAR[4096] __attribute__ ((section (".gccrelocprefix"))) = STANDARD_EXEC_PREFIX; - - /* This value is set by cpp_relocated at runtime */ - const char *gcc_exec_prefix; -diff --git a/gcc/cppdefault.h b/gcc/cppdefault.h -index fb97c0b5814..6267150facc 100644 ---- a/gcc/cppdefault.h -+++ b/gcc/cppdefault.h -@@ -33,7 +33,8 @@ - - struct default_include - { -- const char *const fname; /* The name of the directory. */ -+ const char *fname; /* The name of the directory. */ -+ - const char *const component; /* The component containing the directory - (see update_path in prefix.cc) */ - const char cplusplus; /* When this is non-zero, we should only -@@ -55,17 +56,13 @@ struct default_include - }; - - extern const struct default_include cpp_include_defaults[]; --extern const char cpp_GCC_INCLUDE_DIR[]; --extern const size_t cpp_GCC_INCLUDE_DIR_len; -+extern char GCC_INCLUDE_DIRVAR[] __attribute__ ((section (".gccrelocprefix"))); - - /* The configure-time prefix, i.e., the value supplied as the argument - to --prefix=. */ --extern const char cpp_PREFIX[]; -+extern char PREFIXVAR[] __attribute__ ((section (".gccrelocprefix"))); - /* The length of the configure-time prefix. */ --extern const size_t cpp_PREFIX_len; --/* The configure-time execution prefix. This is typically the lib/gcc -- subdirectory of cpp_PREFIX. */ --extern const char cpp_EXEC_PREFIX[]; -+extern char EXEC_PREFIXVAR[] __attribute__ ((section (".gccrelocprefix"))); - /* The run-time execution prefix. This is typically the lib/gcc - subdirectory of the actual installation. */ - extern const char *gcc_exec_prefix; -diff --git a/gcc/gcc.cc b/gcc/gcc.cc -index aa4cf92fb78..5569a39a14a 100644 ---- a/gcc/gcc.cc -+++ b/gcc/gcc.cc -@@ -252,6 +252,8 @@ FILE *report_times_to_file = NULL; - #endif - static const char *target_system_root = DEFAULT_TARGET_SYSTEM_ROOT; - -+static char target_relocatable_prefix[4096] __attribute__ ((section (".gccrelocprefix"))) = SYSTEMLIBS_DIR; -+ - /* Nonzero means pass the updated target_system_root to the compiler. */ - - static int target_system_root_changed; -@@ -575,6 +577,7 @@ or with constant text in a single argument. - %G process LIBGCC_SPEC as a spec. - %R Output the concatenation of target_system_root and - target_sysroot_suffix. -+ %r Output the base path target_relocatable_prefix - %S process STARTFILE_SPEC as a spec. A capital S is actually used here. - %E process ENDFILE_SPEC as a spec. A capital E is actually used here. - %C process CPP_SPEC as a spec. -@@ -1627,10 +1630,10 @@ static const char *gcc_libexec_prefix; - gcc_exec_prefix is set because, in that case, we know where the - compiler has been installed, and use paths relative to that - location instead. */ --static const char *const standard_exec_prefix = STANDARD_EXEC_PREFIX; --static const char *const standard_libexec_prefix = STANDARD_LIBEXEC_PREFIX; --static const char *const standard_bindir_prefix = STANDARD_BINDIR_PREFIX; --static const char *const standard_startfile_prefix = STANDARD_STARTFILE_PREFIX; -+static char standard_exec_prefix[4096] __attribute__ ((section (".gccrelocprefix"))) = STANDARD_EXEC_PREFIX; -+static char standard_libexec_prefix[4096] __attribute__ ((section (".gccrelocprefix"))) = STANDARD_LIBEXEC_PREFIX; -+static char standard_bindir_prefix[4096] __attribute__ ((section (".gccrelocprefix"))) = STANDARD_BINDIR_PREFIX; -+static char *const standard_startfile_prefix = STANDARD_STARTFILE_PREFIX; - - /* For native compilers, these are well-known paths containing - components that may be provided by the system. For cross -@@ -1638,9 +1641,9 @@ static const char *const standard_startfile_prefix = STANDARD_STARTFILE_PREFIX; - static const char *md_exec_prefix = MD_EXEC_PREFIX; - static const char *md_startfile_prefix = MD_STARTFILE_PREFIX; - static const char *md_startfile_prefix_1 = MD_STARTFILE_PREFIX_1; --static const char *const standard_startfile_prefix_1 -+static char standard_startfile_prefix_1[4096] __attribute__ ((section (".gccrelocprefix"))) - = STANDARD_STARTFILE_PREFIX_1; --static const char *const standard_startfile_prefix_2 -+static char standard_startfile_prefix_2[4096] __attribute__ ((section (".gccrelocprefix"))) - = STANDARD_STARTFILE_PREFIX_2; - - /* A relative path to be used in finding the location of tools -@@ -6676,6 +6679,11 @@ do_spec_1 (const char *spec, int inswitch, const char *soft_matched_part) - } - break; - -+ case 'r': -+ obstack_grow (&obstack, target_relocatable_prefix, -+ strlen (target_relocatable_prefix)); -+ break; -+ - case 'S': - value = do_spec_1 (startfile_spec, 0, NULL); - if (value != 0) -diff --git a/gcc/incpath.cc b/gcc/incpath.cc -index c80f100f476..5ac03c08693 100644 ---- a/gcc/incpath.cc -+++ b/gcc/incpath.cc -@@ -135,7 +135,7 @@ add_standard_paths (const char *sysroot, const char *iprefix, - int relocated = cpp_relocated (); - size_t len; - -- if (iprefix && (len = cpp_GCC_INCLUDE_DIR_len) != 0) -+ if (iprefix && (len = strlen(GCC_INCLUDE_DIRVAR) - 7) != 0) - { - /* Look for directories that start with the standard prefix. - "Translate" them, i.e. replace /usr/local/lib/gcc... with -@@ -150,7 +150,7 @@ add_standard_paths (const char *sysroot, const char *iprefix, - now. */ - if (sysroot && p->add_sysroot) - continue; -- if (!filename_ncmp (p->fname, cpp_GCC_INCLUDE_DIR, len)) -+ if (!filename_ncmp (p->fname, GCC_INCLUDE_DIRVAR, len)) - { - char *str = concat (iprefix, p->fname + len, NULL); - if (p->multilib == 1 && imultilib) -@@ -191,7 +191,7 @@ add_standard_paths (const char *sysroot, const char *iprefix, - free (sysroot_no_trailing_dir_separator); - } - else if (!p->add_sysroot && relocated -- && !filename_ncmp (p->fname, cpp_PREFIX, cpp_PREFIX_len)) -+ && !filename_ncmp (p->fname, PREFIXVAR, strlen(PREFIXVAR))) - { - static const char *relocated_prefix; - char *ostr; -@@ -208,12 +208,12 @@ add_standard_paths (const char *sysroot, const char *iprefix, - dummy = concat (gcc_exec_prefix, "dummy", NULL); - relocated_prefix - = make_relative_prefix (dummy, -- cpp_EXEC_PREFIX, -- cpp_PREFIX); -+ EXEC_PREFIXVAR, -+ PREFIXVAR); - free (dummy); - } - ostr = concat (relocated_prefix, -- p->fname + cpp_PREFIX_len, -+ p->fname + strlen(PREFIXVAR), - NULL); - str = update_path (ostr, p->component); - free (ostr); -diff --git a/gcc/prefix.cc b/gcc/prefix.cc -index 096ed5afa3d..2526f0ecc39 100644 ---- a/gcc/prefix.cc -+++ b/gcc/prefix.cc -@@ -72,7 +72,9 @@ License along with GCC; see the file COPYING3. If not see - #include "prefix.h" - #include "common/common-target.h" - --static const char *std_prefix = PREFIX; -+char PREFIXVAR1[4096] __attribute__ ((section (".gccrelocprefix"))) = PREFIX; -+ -+static const char *std_prefix = PREFIXVAR1; - - static const char *get_key_value (char *); - static char *translate_name (char *); -@@ -212,7 +214,7 @@ translate_name (char *name) - prefix = getenv (key); - - if (prefix == 0) -- prefix = PREFIX; -+ prefix = PREFIXVAR1; - - /* We used to strip trailing DIR_SEPARATORs here, but that can - sometimes yield a result with no separator when one was coded diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0017-Search-target-sysroot-gcc-version-specific-dirs-with.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0017-Search-target-sysroot-gcc-version-specific-dirs-with.patch deleted file mode 100644 index 9b05da64..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0017-Search-target-sysroot-gcc-version-specific-dirs-with.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 33a1f07a4417247dc24819d4e583ca09f56d5a7b Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Mon, 7 Dec 2015 23:41:45 +0000 -Subject: [PATCH] Search target sysroot gcc version specific dirs with - multilib. - -We install the gcc libraries (such as crtbegin.p) into -//5.2.0/ -which is a default search path for GCC (aka multi_suffix in the -code below). is 'machine' in gcc's terminology. We use -these directories so that multiple gcc versions could in theory -co-exist on target. - -We only want to build one gcc-cross-canadian per arch and have this work -for all multilibs. can be handled by mapping the multilib - to the one used by gcc-cross-canadian, e.g. -mips64-polkmllib32-linux -is symlinked to by mips64-poky-linux. - -The default gcc search path in the target sysroot for a "lib64" mutlilib -is: - -/lib32/mips64-poky-linux/5.2.0/ -/lib32/../lib64/ -/usr/lib32/mips64-poky-linux/5.2.0/ -/usr/lib32/../lib64/ -/lib32/ -/usr/lib32/ - -which means that the lib32 crtbegin.o will be found and the lib64 ones -will not which leads to compiler failures. - -This patch injects a multilib version of that path first so the lib64 -binaries can be found first. With this change the search path becomes: - -/lib32/../lib64/mips64-poky-linux/5.2.0/ -/lib32/mips64-poky-linux/5.2.0/ -/lib32/../lib64/ -/usr/lib32/../lib64/mips64-poky-linux/5.2.0/ -/usr/lib32/mips64-poky-linux/5.2.0/ -/usr/lib32/../lib64/ -/lib32/ -/usr/lib32/ - -Upstream-Status: Pending -RP 2015/7/31 - -Signed-off-by: Khem Raj ---- - gcc/gcc.cc | 29 ++++++++++++++++++++++++++++- - 1 file changed, 28 insertions(+), 1 deletion(-) - -diff --git a/gcc/gcc.cc b/gcc/gcc.cc -index 5569a39a14a..4598f6cd7c9 100644 ---- a/gcc/gcc.cc -+++ b/gcc/gcc.cc -@@ -2817,7 +2817,7 @@ for_each_path (const struct path_prefix *paths, - if (path == NULL) - { - len = paths->max_len + extra_space + 1; -- len += MAX (MAX (suffix_len, multi_os_dir_len), multiarch_len); -+ len += MAX ((suffix_len + multi_os_dir_len), multiarch_len); - path = XNEWVEC (char, len); - } - -@@ -2829,6 +2829,33 @@ for_each_path (const struct path_prefix *paths, - /* Look first in MACHINE/VERSION subdirectory. */ - if (!skip_multi_dir) - { -+ if (!(pl->os_multilib ? skip_multi_os_dir : skip_multi_dir)) -+ { -+ const char *this_multi; -+ size_t this_multi_len; -+ -+ if (pl->os_multilib) -+ { -+ this_multi = multi_os_dir; -+ this_multi_len = multi_os_dir_len; -+ } -+ else -+ { -+ this_multi = multi_dir; -+ this_multi_len = multi_dir_len; -+ } -+ -+ /* Look in multilib MACHINE/VERSION subdirectory first */ -+ if (this_multi_len) -+ { -+ memcpy (path + len, this_multi, this_multi_len + 1); -+ memcpy (path + len + this_multi_len, multi_suffix, suffix_len + 1); -+ ret = callback (path, callback_info); -+ if (ret) -+ break; -+ } -+ } -+ - memcpy (path + len, multi_suffix, suffix_len + 1); - ret = callback (path, callback_info); - if (ret) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0018-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0018-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch deleted file mode 100644 index 56793e03..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0018-Add-ssp_nonshared-to-link-commandline-for-musl-targe.patch +++ /dev/null @@ -1,84 +0,0 @@ -From d7dc2861840e88a4592817a398a054a886c3f3ee Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Tue, 27 Jun 2017 18:10:54 -0700 -Subject: [PATCH] Add ssp_nonshared to link commandline for musl targets - -when -fstack-protector options are enabled we need to -link with ssp_shared on musl since it does not provide -the __stack_chk_fail_local() so essentially it provides -libssp but not libssp_nonshared something like -TARGET_LIBC_PROVIDES_SSP_BUT_NOT_SSP_NONSHARED - where-as for glibc the needed symbols -are already present in libc_nonshared library therefore -we do not need any library helper on glibc based systems -but musl needs the libssp_noshared from gcc - -Upstream-Status: Pending - -Signed-off-by: Khem Raj ---- - gcc/config/linux.h | 7 +++++++ - gcc/config/rs6000/linux.h | 10 ++++++++++ - gcc/config/rs6000/linux64.h | 10 ++++++++++ - 3 files changed, 27 insertions(+) - -diff --git a/gcc/config/linux.h b/gcc/config/linux.h -index 58143dff731..d2409ccac26 100644 ---- a/gcc/config/linux.h -+++ b/gcc/config/linux.h -@@ -208,6 +208,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - { GCC_INCLUDE_DIRVAR, "GCC", 0, 1, 0, 0 }, \ - { 0, 0, 0, 0, 0, 0 } \ - } -+#ifdef TARGET_LIBC_PROVIDES_SSP -+#undef LINK_SSP_SPEC -+#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ -+ "|fstack-protector-strong|fstack-protector-explicit" \ -+ ":-lssp_nonshared}" -+#endif -+ - #endif - - #if (DEFAULT_LIBC == LIBC_UCLIBC) && defined (SINGLE_LIBC) /* uClinux */ -diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h -index 8c9039ac1e5..259cd485973 100644 ---- a/gcc/config/rs6000/linux.h -+++ b/gcc/config/rs6000/linux.h -@@ -99,6 +99,16 @@ - " -m elf32ppclinux") - #endif - -+/* link libssp_nonshared.a with musl */ -+#if DEFAULT_LIBC == LIBC_MUSL -+#ifdef TARGET_LIBC_PROVIDES_SSP -+#undef LINK_SSP_SPEC -+#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ -+ "|fstack-protector-strong|fstack-protector-explicit" \ -+ ":-lssp_nonshared}" -+#endif -+#endif -+ - #undef LINK_OS_LINUX_SPEC - #define LINK_OS_LINUX_SPEC LINK_OS_LINUX_EMUL " %{!shared: %{!static: \ - %{!static-pie: \ -diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h -index 364c1a5b155..e33d9ae98e0 100644 ---- a/gcc/config/rs6000/linux64.h -+++ b/gcc/config/rs6000/linux64.h -@@ -372,6 +372,16 @@ extern int dot_symbols; - " -m elf64ppc") - #endif - -+/* link libssp_nonshared.a with musl */ -+#if DEFAULT_LIBC == LIBC_MUSL -+#ifdef TARGET_LIBC_PROVIDES_SSP -+#undef LINK_SSP_SPEC -+#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ -+ "|fstack-protector-strong|fstack-protector-explicit" \ -+ ":-lssp_nonshared}" -+#endif -+#endif -+ - #define LINK_OS_LINUX_SPEC32 LINK_OS_LINUX_EMUL32 " %{!shared: %{!static: \ - %{!static-pie: \ - %{rdynamic:-export-dynamic} \ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0019-Re-introduce-spe-commandline-options.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0019-Re-introduce-spe-commandline-options.patch deleted file mode 100644 index bb1699be..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0019-Re-introduce-spe-commandline-options.patch +++ /dev/null @@ -1,39 +0,0 @@ -From bf0d7c463e1fab62804556099b56319fe94be1eb Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Wed, 6 Jun 2018 12:10:22 -0700 -Subject: [PATCH] Re-introduce spe commandline options - -This should ensure that we keep accepting -spe options - -Upstream-Status: Inappropriate [SPE port is removed from rs600 port] - -Signed-off-by: Khem Raj ---- - gcc/config/rs6000/rs6000.opt | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt -index 4931d781c4e..3fb87b6f7d5 100644 ---- a/gcc/config/rs6000/rs6000.opt -+++ b/gcc/config/rs6000/rs6000.opt -@@ -348,6 +348,19 @@ mdebug= - Target RejectNegative Joined - -mdebug= Enable debug output. - -+; PPC SPE ABI -+mspe -+Target Var(rs6000_spe) Save -+Generate SPE SIMD instructions on E500. -+ -+mabi=spe -+Target RejectNegative Var(rs6000_spe_abi) Save -+Use the SPE ABI extensions. -+ -+mabi=no-spe -+Target RejectNegative Var(rs6000_spe_abi, 0) -+Do not use the SPE ABI extensions. -+ - ; Altivec ABI - mabi=altivec - Target RejectNegative Var(rs6000_altivec_abi) Save diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0020-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0020-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch deleted file mode 100644 index f3709208..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0020-libgcc_s-Use-alias-for-__cpu_indicator_init-instead-.patch +++ /dev/null @@ -1,83 +0,0 @@ -From a32c75b37209d6836eaaa943dc6b1207acba5d27 Mon Sep 17 00:00:00 2001 -From: Szabolcs Nagy -Date: Sat, 24 Oct 2015 20:09:53 +0000 -Subject: [PATCH] libgcc_s: Use alias for __cpu_indicator_init instead of - symver - -Adapter from - -https://gcc.gnu.org/ml/gcc-patches/2015-05/msg00899.html - -This fix was debated but hasnt been applied gcc upstream since -they expect musl to support '@' in symbol versioning which is -a sun/gnu versioning extention. This patch however avoids the -need for the '@' symbols at all - -libgcc/Changelog: - -2015-05-11 Szabolcs Nagy - - * config/i386/cpuinfo.c (__cpu_indicator_init_local): Add. - (__cpu_indicator_init@GCC_4.8.0, __cpu_model@GCC_4.8.0): Remove. - - * config/i386/t-linux (HOST_LIBGCC2_CFLAGS): Remove -DUSE_ELF_SYMVER. - -gcc/Changelog: - -2015-05-11 Szabolcs Nagy - - * config/i386/i386-expand.c (ix86_expand_builtin): Make __builtin_cpu_init - call __cpu_indicator_init_local instead of __cpu_indicator_init. - -Upstream-Status: Pending - -Signed-off-by: Khem Raj ---- - gcc/config/i386/i386-expand.cc | 4 ++-- - libgcc/config/i386/cpuinfo.c | 6 +++--- - libgcc/config/i386/t-linux | 2 +- - 3 files changed, 6 insertions(+), 6 deletions(-) - -diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc -index 68978ef8dc2..0c71f36b572 100644 ---- a/gcc/config/i386/i386-expand.cc -+++ b/gcc/config/i386/i386-expand.cc -@@ -12321,10 +12321,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, - { - case IX86_BUILTIN_CPU_INIT: - { -- /* Make it call __cpu_indicator_init in libgcc. */ -+ /* Make it call __cpu_indicator_init_local in libgcc.a. */ - tree call_expr, fndecl, type; - type = build_function_type_list (integer_type_node, NULL_TREE); -- fndecl = build_fn_decl ("__cpu_indicator_init", type); -+ fndecl = build_fn_decl ("__cpu_indicator_init_local", type); - call_expr = build_call_expr (fndecl, 0); - return expand_expr (call_expr, target, mode, EXPAND_NORMAL); - } -diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c -index dab1d98060f..cf824b4114a 100644 ---- a/libgcc/config/i386/cpuinfo.c -+++ b/libgcc/config/i386/cpuinfo.c -@@ -63,7 +63,7 @@ __cpu_indicator_init (void) - __cpu_features2); - } - --#if defined SHARED && defined USE_ELF_SYMVER --__asm__ (".symver __cpu_indicator_init, __cpu_indicator_init@GCC_4.8.0"); --__asm__ (".symver __cpu_model, __cpu_model@GCC_4.8.0"); -+#ifndef SHARED -+int __cpu_indicator_init_local (void) -+ __attribute__ ((weak, alias ("__cpu_indicator_init"))); - #endif -diff --git a/libgcc/config/i386/t-linux b/libgcc/config/i386/t-linux -index 8506a635790..564296f788e 100644 ---- a/libgcc/config/i386/t-linux -+++ b/libgcc/config/i386/t-linux -@@ -3,5 +3,5 @@ - # t-slibgcc-elf-ver and t-linux - SHLIB_MAPFILES = libgcc-std.ver $(srcdir)/config/i386/libgcc-glibc.ver - --HOST_LIBGCC2_CFLAGS += -mlong-double-80 -DUSE_ELF_SYMVER $(CET_FLAGS) -+HOST_LIBGCC2_CFLAGS += -mlong-double-80 $(CET_FLAGS) - CRTSTUFF_T_CFLAGS += $(CET_FLAGS) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0021-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0021-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch deleted file mode 100644 index f5f04ae3..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0021-gentypes-genmodes-Do-not-use-__LINE__-for-maintainin.patch +++ /dev/null @@ -1,182 +0,0 @@ -From 4efc42b99c96b026f560b0918de7e237ac3dc8d1 Mon Sep 17 00:00:00 2001 -From: Richard Purdie -Date: Tue, 10 Mar 2020 08:26:53 -0700 -Subject: [PATCH] gentypes/genmodes: Do not use __LINE__ for maintaining - reproducibility - -Inserting line numbers into generated code means its not always reproducible wth -differing versions of host gcc. Void the issue by not adding these. - -Upstream-Status: Inappropriate [OE Reproducibility specific] - -Signed-off-by: Richard Purdie -Signed-off-by: Khem Raj ---- - gcc/gengtype.cc | 6 +++--- - gcc/genmodes.cc | 32 ++++++++++++++++---------------- - 2 files changed, 19 insertions(+), 19 deletions(-) - -diff --git a/gcc/gengtype.cc b/gcc/gengtype.cc -index 386ae1b0506..9762e914296 100644 ---- a/gcc/gengtype.cc -+++ b/gcc/gengtype.cc -@@ -1006,7 +1006,7 @@ create_field_at (pair_p next, type_p type, const char *name, options_p opt, - /* Create a fake field with the given type and name. NEXT is the next - field in the chain. */ - #define create_field(next,type,name) \ -- create_field_all (next,type,name, 0, this_file, __LINE__) -+ create_field_all (next,type,name, 0, this_file, 0) - - /* Like create_field, but the field is only valid when condition COND - is true. */ -@@ -1039,7 +1039,7 @@ create_optional_field_ (pair_p next, type_p type, const char *name, - } - - #define create_optional_field(next,type,name,cond) \ -- create_optional_field_(next,type,name,cond,__LINE__) -+ create_optional_field_(next,type,name,cond,0) - - /* Reverse a linked list of 'struct pair's in place. */ - pair_p -@@ -5238,7 +5238,7 @@ main (int argc, char **argv) - /* These types are set up with #define or else outside of where - we can see them. We should initialize them before calling - read_input_list. */ --#define POS_HERE(Call) do { pos.file = this_file; pos.line = __LINE__; \ -+#define POS_HERE(Call) do { pos.file = this_file; pos.line = 0; \ - Call;} while (0) - POS_HERE (do_scalar_typedef ("CUMULATIVE_ARGS", &pos)); - POS_HERE (do_scalar_typedef ("REAL_VALUE_TYPE", &pos)); -diff --git a/gcc/genmodes.cc b/gcc/genmodes.cc -index 59850bb070a..e187f8542a1 100644 ---- a/gcc/genmodes.cc -+++ b/gcc/genmodes.cc -@@ -440,7 +440,7 @@ complete_all_modes (void) - } - - /* For each mode in class CLASS, construct a corresponding complex mode. */ --#define COMPLEX_MODES(C) make_complex_modes (MODE_##C, __FILE__, __LINE__) -+#define COMPLEX_MODES(C) make_complex_modes (MODE_##C, __FILE__, 0) - static void - make_complex_modes (enum mode_class cl, - const char *file, unsigned int line) -@@ -499,7 +499,7 @@ make_complex_modes (enum mode_class cl, - having as many components as necessary. ORDER is the sorting order - of the mode, with smaller numbers indicating a higher priority. */ - #define VECTOR_MODES_WITH_PREFIX(PREFIX, C, W, ORDER) \ -- make_vector_modes (MODE_##C, #PREFIX, W, ORDER, __FILE__, __LINE__) -+ make_vector_modes (MODE_##C, #PREFIX, W, ORDER, __FILE__, 0) - #define VECTOR_MODES(C, W) VECTOR_MODES_WITH_PREFIX (V, C, W, 0) - static void ATTRIBUTE_UNUSED - make_vector_modes (enum mode_class cl, const char *prefix, unsigned int width, -@@ -552,7 +552,7 @@ make_vector_modes (enum mode_class cl, const char *prefix, unsigned int width, - BYTESIZE bytes in total. */ - #define VECTOR_BOOL_MODE(NAME, COUNT, COMPONENT, BYTESIZE) \ - make_vector_bool_mode (#NAME, COUNT, #COMPONENT, BYTESIZE, \ -- __FILE__, __LINE__) -+ __FILE__, 0) - static void ATTRIBUTE_UNUSED - make_vector_bool_mode (const char *name, unsigned int count, - const char *component, unsigned int bytesize, -@@ -574,7 +574,7 @@ make_vector_bool_mode (const char *name, unsigned int count, - /* Input. */ - - #define _SPECIAL_MODE(C, N) \ -- make_special_mode (MODE_##C, #N, __FILE__, __LINE__) -+ make_special_mode (MODE_##C, #N, __FILE__, 0) - #define RANDOM_MODE(N) _SPECIAL_MODE (RANDOM, N) - #define CC_MODE(N) _SPECIAL_MODE (CC, N) - -@@ -587,7 +587,7 @@ make_special_mode (enum mode_class cl, const char *name, - - #define INT_MODE(N, Y) FRACTIONAL_INT_MODE (N, -1U, Y) - #define FRACTIONAL_INT_MODE(N, B, Y) \ -- make_int_mode (#N, B, Y, __FILE__, __LINE__) -+ make_int_mode (#N, B, Y, __FILE__, 0) - - static void - make_int_mode (const char *name, -@@ -628,16 +628,16 @@ make_opaque_mode (const char *name, - } - - #define FRACT_MODE(N, Y, F) \ -- make_fixed_point_mode (MODE_FRACT, #N, Y, 0, F, __FILE__, __LINE__) -+ make_fixed_point_mode (MODE_FRACT, #N, Y, 0, F, __FILE__, 0) - - #define UFRACT_MODE(N, Y, F) \ -- make_fixed_point_mode (MODE_UFRACT, #N, Y, 0, F, __FILE__, __LINE__) -+ make_fixed_point_mode (MODE_UFRACT, #N, Y, 0, F, __FILE__, 0) - - #define ACCUM_MODE(N, Y, I, F) \ -- make_fixed_point_mode (MODE_ACCUM, #N, Y, I, F, __FILE__, __LINE__) -+ make_fixed_point_mode (MODE_ACCUM, #N, Y, I, F, __FILE__, 0) - - #define UACCUM_MODE(N, Y, I, F) \ -- make_fixed_point_mode (MODE_UACCUM, #N, Y, I, F, __FILE__, __LINE__) -+ make_fixed_point_mode (MODE_UACCUM, #N, Y, I, F, __FILE__, 0) - - /* Create a fixed-point mode by setting CL, NAME, BYTESIZE, IBIT, FBIT, - FILE, and LINE. */ -@@ -658,7 +658,7 @@ make_fixed_point_mode (enum mode_class cl, - - #define FLOAT_MODE(N, Y, F) FRACTIONAL_FLOAT_MODE (N, -1U, Y, F) - #define FRACTIONAL_FLOAT_MODE(N, B, Y, F) \ -- make_float_mode (#N, B, Y, #F, __FILE__, __LINE__) -+ make_float_mode (#N, B, Y, #F, __FILE__, 0) - - static void - make_float_mode (const char *name, -@@ -675,7 +675,7 @@ make_float_mode (const char *name, - #define DECIMAL_FLOAT_MODE(N, Y, F) \ - FRACTIONAL_DECIMAL_FLOAT_MODE (N, -1U, Y, F) - #define FRACTIONAL_DECIMAL_FLOAT_MODE(N, B, Y, F) \ -- make_decimal_float_mode (#N, B, Y, #F, __FILE__, __LINE__) -+ make_decimal_float_mode (#N, B, Y, #F, __FILE__, 0) - - static void - make_decimal_float_mode (const char *name, -@@ -690,7 +690,7 @@ make_decimal_float_mode (const char *name, - } - - #define RESET_FLOAT_FORMAT(N, F) \ -- reset_float_format (#N, #F, __FILE__, __LINE__) -+ reset_float_format (#N, #F, __FILE__, 0) - static void ATTRIBUTE_UNUSED - reset_float_format (const char *name, const char *format, - const char *file, unsigned int line) -@@ -711,7 +711,7 @@ reset_float_format (const char *name, const char *format, - - /* __intN support. */ - #define INT_N(M,PREC) \ -- make_int_n (#M, PREC, __FILE__, __LINE__) -+ make_int_n (#M, PREC, __FILE__, 0) - static void ATTRIBUTE_UNUSED - make_int_n (const char *m, int bitsize, - const char *file, unsigned int line) -@@ -740,7 +740,7 @@ make_int_n (const char *m, int bitsize, - /* Partial integer modes are specified by relation to a full integer - mode. */ - #define PARTIAL_INT_MODE(M,PREC,NAME) \ -- make_partial_integer_mode (#M, #NAME, PREC, __FILE__, __LINE__) -+ make_partial_integer_mode (#M, #NAME, PREC, __FILE__, 0) - static void ATTRIBUTE_UNUSED - make_partial_integer_mode (const char *base, const char *name, - unsigned int precision, -@@ -767,7 +767,7 @@ make_partial_integer_mode (const char *base, const char *name, - /* A single vector mode can be specified by naming its component - mode and the number of components. */ - #define VECTOR_MODE_WITH_PREFIX(PREFIX, C, M, N, ORDER) \ -- make_vector_mode (MODE_##C, #PREFIX, #M, N, ORDER, __FILE__, __LINE__); -+ make_vector_mode (MODE_##C, #PREFIX, #M, N, ORDER, __FILE__, 0); - #define VECTOR_MODE(C, M, N) VECTOR_MODE_WITH_PREFIX(V, C, M, N, 0); - static void ATTRIBUTE_UNUSED - make_vector_mode (enum mode_class bclass, -@@ -814,7 +814,7 @@ make_vector_mode (enum mode_class bclass, - - /* Adjustability. */ - #define _ADD_ADJUST(A, M, X, C1, C2) \ -- new_adjust (#M, &adj_##A, #A, #X, MODE_##C1, MODE_##C2, __FILE__, __LINE__) -+ new_adjust (#M, &adj_##A, #A, #X, MODE_##C1, MODE_##C2, __FILE__, 0) - - #define ADJUST_NUNITS(M, X) _ADD_ADJUST (nunits, M, X, RANDOM, RANDOM) - #define ADJUST_BYTESIZE(M, X) _ADD_ADJUST (bytesize, M, X, RANDOM, RANDOM) diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0022-libatomic-Do-not-enforce-march-on-aarch64.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0022-libatomic-Do-not-enforce-march-on-aarch64.patch deleted file mode 100644 index cb8969b1..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0022-libatomic-Do-not-enforce-march-on-aarch64.patch +++ /dev/null @@ -1,42 +0,0 @@ -From c3870d073eb9e5d82f9d3067d0fa15038b69713a Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Wed, 13 May 2020 15:10:38 -0700 -Subject: [PATCH] libatomic: Do not enforce march on aarch64 - -OE passes the right options via gcc compiler cmdline via TUNE_CCARGS -this can conflict between -mcpu settings and -march setting here, since --mcpu will translate into an appropriate -march, lets depend on that -instead of setting it explicitly - -Upstream-Status: Inappropriate [OE-Specific] - -Signed-off-by: Khem Raj ---- - libatomic/Makefile.am | 1 - - libatomic/Makefile.in | 1 - - 2 files changed, 2 deletions(-) - -diff --git a/libatomic/Makefile.am b/libatomic/Makefile.am -index c6c8d81c56a..d959a5d040e 100644 ---- a/libatomic/Makefile.am -+++ b/libatomic/Makefile.am -@@ -125,7 +125,6 @@ libatomic_la_LIBADD = $(foreach s,$(SIZES),$(addsuffix _$(s)_.lo,$(SIZEOBJS))) - ## On a target-specific basis, include alternates to be selected by IFUNC. - if HAVE_IFUNC - if ARCH_AARCH64_LINUX --IFUNC_OPTIONS = -march=armv8-a+lse - libatomic_la_LIBADD += $(foreach s,$(SIZES),$(addsuffix _$(s)_1_.lo,$(SIZEOBJS))) - libatomic_la_SOURCES += atomic_16.S - -diff --git a/libatomic/Makefile.in b/libatomic/Makefile.in -index a0fa3dfc8cc..e70d389874a 100644 ---- a/libatomic/Makefile.in -+++ b/libatomic/Makefile.in -@@ -447,7 +447,6 @@ M_SRC = $(firstword $(filter %/$(M_FILE), $(all_c_files))) - libatomic_la_LIBADD = $(foreach s,$(SIZES),$(addsuffix \ - _$(s)_.lo,$(SIZEOBJS))) $(am__append_1) $(am__append_3) \ - $(am__append_4) $(am__append_5) --@ARCH_AARCH64_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv8-a+lse - @ARCH_ARM_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv7-a+fp -DHAVE_KERNEL64 - @ARCH_I386_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=i586 - @ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -mcx16 -mcx16 diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0023-Fix-install-path-of-linux64.h.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0023-Fix-install-path-of-linux64.h.patch deleted file mode 100644 index 11f42c59..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0023-Fix-install-path-of-linux64.h.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 7bd6e631e4a5273f5ecc41a5a48830a1342e5926 Mon Sep 17 00:00:00 2001 -From: Andrei Gherzan -Date: Wed, 22 Dec 2021 12:49:25 +0100 -Subject: [PATCH] Fix install path of linux64.h - -We add linux64.h to tm includes[1] as a relative path to B. This patch -adapts the install path of linux64.h to match the include in tm.h. - -[1] 0016-Use-the-multilib-config-files-from-B-instead-of-usin.patch - -Signed-off-by: Andrei Gherzan - -Upstream-Status: Inappropriate [configuration] -Signed-off-by: Khem Raj ---- - gcc/Makefile.in | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/gcc/Makefile.in b/gcc/Makefile.in -index 065ce7e9a5b..d4c723968aa 100644 ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -3738,6 +3738,8 @@ install-plugin: installdirs lang.install-plugin s-header-vars install-gengtype - "$(srcdir)"/config/* | "$(srcdir)"/common/config/* \ - | "$(srcdir)"/c-family/* | "$(srcdir)"/*.def ) \ - base=`echo "$$path" | sed -e "s|$$srcdirstrip/||"`;; \ -+ */linux64.h ) \ -+ base=`dirname $$path`;;\ - *) base=`basename $$path` ;; \ - esac; \ - dest=$(plugin_includedir)/$$base; \ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0023-libatomic-Do-not-enforce-march-on-aarch64.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0023-libatomic-Do-not-enforce-march-on-aarch64.patch deleted file mode 100644 index 2f016598..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0023-libatomic-Do-not-enforce-march-on-aarch64.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 52931ec7a708b58d68e69ce9eb99001ae9f099dd Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Wed, 13 May 2020 15:10:38 -0700 -Subject: [PATCH] libatomic: Do not enforce march on aarch64 - -OE passes the right options via gcc compiler cmdline via TUNE_CCARGS -this can conflict between -mcpu settings and -march setting here, since --mcpu will translate into an appropriate -march, lets depend on that -instead of setting it explicitly - -Upstream-Status: Inappropriate [OE-Specific] - -Signed-off-by: Khem Raj ---- - libatomic/Makefile.am | 1 - - libatomic/Makefile.in | 1 - - 2 files changed, 2 deletions(-) - -diff --git a/libatomic/Makefile.am b/libatomic/Makefile.am -index d88515e4a03..e0e2f8b442a 100644 ---- a/libatomic/Makefile.am -+++ b/libatomic/Makefile.am -@@ -125,7 +125,6 @@ libatomic_la_LIBADD = $(foreach s,$(SIZES),$(addsuffix _$(s)_.lo,$(SIZEOBJS))) - ## On a target-specific basis, include alternates to be selected by IFUNC. - if HAVE_IFUNC - if ARCH_AARCH64_LINUX --IFUNC_OPTIONS = -march=armv8-a+lse - libatomic_la_LIBADD += $(foreach s,$(SIZES),$(addsuffix _$(s)_1_.lo,$(SIZEOBJS))) - endif - if ARCH_ARM_LINUX -diff --git a/libatomic/Makefile.in b/libatomic/Makefile.in -index 80d25653dc7..7377689ab34 100644 ---- a/libatomic/Makefile.in -+++ b/libatomic/Makefile.in -@@ -434,7 +434,6 @@ M_SRC = $(firstword $(filter %/$(M_FILE), $(all_c_files))) - libatomic_la_LIBADD = $(foreach s,$(SIZES),$(addsuffix \ - _$(s)_.lo,$(SIZEOBJS))) $(am__append_1) $(am__append_2) \ - $(am__append_3) $(am__append_4) --@ARCH_AARCH64_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv8-a+lse - @ARCH_ARM_LINUX_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=armv7-a+fp -DHAVE_KERNEL64 - @ARCH_I386_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -march=i586 - @ARCH_X86_64_TRUE@@HAVE_IFUNC_TRUE@IFUNC_OPTIONS = -mcx16 -mcx16 diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0024-Avoid-hardcoded-build-paths-into-ppc-libgcc.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0024-Avoid-hardcoded-build-paths-into-ppc-libgcc.patch deleted file mode 100644 index ad826901..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0024-Avoid-hardcoded-build-paths-into-ppc-libgcc.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 4623d87d779853a2862ee92a15a41fded81eddb8 Mon Sep 17 00:00:00 2001 -From: Richard Purdie -Date: Sat, 20 Aug 2022 09:04:14 -0700 -Subject: [PATCH] Avoid hardcoded build paths into ppc libgcc - -Avoid encoding build paths into sources used for floating point on powerpc. -(MACHINE=qemuppc bitbake libgcc). - -Upstream-Status: Submitted [https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599882.html] -Signed-off-by: Richard Purdie -Signed-off-by: Khem Raj ---- - libgcc/config/rs6000/t-float128 | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128 -index b09b5664af0..513e63748f1 100644 ---- a/libgcc/config/rs6000/t-float128 -+++ b/libgcc/config/rs6000/t-float128 -@@ -103,7 +103,7 @@ $(ibm128_dec_objs) : INTERNAL_CFLAGS += $(IBM128_CFLAGS_DECIMAL) - $(fp128_softfp_src) : $(srcdir)/soft-fp/$(subst -sw,,$(subst kf,tf,$@)) $(fp128_dep) - @src="$(srcdir)/soft-fp/$(subst -sw,,$(subst kf,tf,$@))"; \ - echo "Create $@"; \ -- (echo "/* file created from $$src */"; \ -+ (echo "/* file created from `basename $$src` */"; \ - echo; \ - sed -f $(fp128_sed) < $$src) > $@ - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0024-Fix-install-path-of-linux64.h.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0024-Fix-install-path-of-linux64.h.patch deleted file mode 100644 index 555be623..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0024-Fix-install-path-of-linux64.h.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 3e67c9c77e46132c252911bf1e5e4222dfd3aa34 Mon Sep 17 00:00:00 2001 -From: Andrei Gherzan -Date: Wed, 22 Dec 2021 12:49:25 +0100 -Subject: [PATCH] Fix install path of linux64.h - -We add linux64.h to tm includes[1] as a relative path to B. This patch -adapts the install path of linux64.h to match the include in tm.h. - -[1] 0016-Use-the-multilib-config-files-from-B-instead-of-usin.patch - -Signed-off-by: Andrei Gherzan - -Upstream-Status: Inappropriate [configuration] -Signed-off-by: Khem Raj ---- - gcc/Makefile.in | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/gcc/Makefile.in b/gcc/Makefile.in -index 07fa63b6640..0def7394454 100644 ---- a/gcc/Makefile.in -+++ b/gcc/Makefile.in -@@ -3706,6 +3706,8 @@ install-plugin: installdirs lang.install-plugin s-header-vars install-gengtype - "$(srcdir)"/config/* | "$(srcdir)"/common/config/* \ - | "$(srcdir)"/c-family/* | "$(srcdir)"/*.def ) \ - base=`echo "$$path" | sed -e "s|$$srcdirstrip/||"`;; \ -+ */linux64.h ) \ -+ base=`dirname $$path`;;\ - *) base=`basename $$path` ;; \ - esac; \ - dest=$(plugin_includedir)/$$base; \ diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0026-rust-recursion-limit.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0026-rust-recursion-limit.patch deleted file mode 100644 index bbe2f18f..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/0026-rust-recursion-limit.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 9234cdca6ee88badfc00297e72f13dac4e540c79 Mon Sep 17 00:00:00 2001 -From: Nick Clifton -Date: Fri, 1 Jul 2022 15:58:52 +0100 -Subject: [PATCH] Add a recursion limit to the demangle_const function in the - Rust demangler. - -libiberty/ - PR demangler/105039 - * rust-demangle.c (demangle_const): Add recursion limit. - -Upstream-Status: Backport [https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=9234cdca6ee88badfc00297e72f13dac4e540c79] ---- - libiberty/rust-demangle.c | 29 ++++++++++++++++++++--------- - 1 file changed, 20 insertions(+), 9 deletions(-) - -diff --git a/libiberty/rust-demangle.c b/libiberty/rust-demangle.c -index bb58d900e27..36afcfae278 100644 ---- a/libiberty/rust-demangle.c -+++ b/libiberty/rust-demangle.c -@@ -126,7 +126,7 @@ parse_integer_62 (struct rust_demangler *rdm) - return 0; - - x = 0; -- while (!eat (rdm, '_')) -+ while (!eat (rdm, '_') && !rdm->errored) - { - c = next (rdm); - x *= 62; -@@ -1148,6 +1148,15 @@ demangle_const (struct rust_demangler *rdm) - if (rdm->errored) - return; - -+ if (rdm->recursion != RUST_NO_RECURSION_LIMIT) -+ { -+ ++ rdm->recursion; -+ if (rdm->recursion > RUST_MAX_RECURSION_COUNT) -+ /* FIXME: There ought to be a way to report -+ that the recursion limit has been reached. */ -+ goto fail_return; -+ } -+ - if (eat (rdm, 'B')) - { - backref = parse_integer_62 (rdm); -@@ -1158,7 +1167,7 @@ demangle_const (struct rust_demangler *rdm) - demangle_const (rdm); - rdm->next = old_next; - } -- return; -+ goto pass_return; - } - - ty_tag = next (rdm); -@@ -1167,7 +1176,7 @@ demangle_const (struct rust_demangler *rdm) - /* Placeholder. */ - case 'p': - PRINT ("_"); -- return; -+ goto pass_return; - - /* Unsigned integer types. */ - case 'h': -@@ -1200,18 +1209,20 @@ demangle_const (struct rust_demangler *rdm) - break; - - default: -- rdm->errored = 1; -- return; -+ goto fail_return; - } - -- if (rdm->errored) -- return; -- -- if (rdm->verbose) -+ if (!rdm->errored && rdm->verbose) - { - PRINT (": "); - PRINT (basic_type (ty_tag)); - } -+ -+ fail_return: -+ rdm->errored = 1; -+ pass_return: -+ if (rdm->recursion != RUST_NO_RECURSION_LIMIT) -+ -- rdm->recursion; - } - - static void --- -2.31.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/hardcoded-paths.patch b/meta-microblaze/recipes-devtools/gcc/gcc/hardcoded-paths.patch deleted file mode 100644 index f3485858..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/hardcoded-paths.patch +++ /dev/null @@ -1,19 +0,0 @@ -Avoid encoding build paths into sources used for floating point on powerpc. -(MACHINE=qemuppc bitbake libgcc). - -Upstream-Status: Submitted [https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599882.html] -Signed-off-by: Richard Purdie - -Index: gcc-12.1.0/libgcc/config/rs6000/t-float128 -=================================================================== ---- gcc-12.1.0.orig/libgcc/config/rs6000/t-float128 -+++ gcc-12.1.0/libgcc/config/rs6000/t-float128 -@@ -103,7 +103,7 @@ $(ibm128_dec_objs) : INTERNAL_CFLAGS += - $(fp128_softfp_src) : $(srcdir)/soft-fp/$(subst -sw,,$(subst kf,tf,$@)) $(fp128_dep) - @src="$(srcdir)/soft-fp/$(subst -sw,,$(subst kf,tf,$@))"; \ - echo "Create $@"; \ -- (echo "/* file created from $$src */"; \ -+ (echo "/* file created from `basename $$src` */"; \ - echo; \ - sed -f $(fp128_sed) < $$src) > $@ - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/prefix-map-realpath.patch b/meta-microblaze/recipes-devtools/gcc/gcc/prefix-map-realpath.patch deleted file mode 100644 index 7f1a2dee..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc/prefix-map-realpath.patch +++ /dev/null @@ -1,63 +0,0 @@ -Relative paths don't work with -fdebug-prefix-map and friends. This -can lead to paths which the user wanted to be remapped being missed. -Setting -fdebug-prefix-map to work with a relative path isn't practical -either. - -Instead, call gcc's realpath function on the incomming path name before -comparing it with the remapping. This means other issues like symlinks -are also accounted for and leads to a more consistent remapping experience. - -Upstream-Status: Submitted [https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599885.html] -[Also https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599884.html] -Signed-off-by: Richard Purdie - - -Index: gcc-12.1.0/gcc/file-prefix-map.cc -=================================================================== ---- gcc-12.1.0.orig/gcc/file-prefix-map.cc -+++ gcc-12.1.0/gcc/file-prefix-map.cc -@@ -70,19 +70,28 @@ remap_filename (file_prefix_map *maps, c - file_prefix_map *map; - char *s; - const char *name; -+ char *realname; - size_t name_len; - -+ if (lbasename (filename) == filename) -+ return filename; -+ -+ realname = lrealpath (filename); -+ - for (map = maps; map; map = map->next) -- if (filename_ncmp (filename, map->old_prefix, map->old_len) == 0) -+ if (filename_ncmp (realname, map->old_prefix, map->old_len) == 0) - break; -- if (!map) -+ if (!map) { -+ free (realname); - return filename; -- name = filename + map->old_len; -+ } -+ name = realname + map->old_len; - name_len = strlen (name) + 1; - - s = (char *) ggc_alloc_atomic (name_len + map->new_len); - memcpy (s, map->new_prefix, map->new_len); - memcpy (s + map->new_len, name, name_len); -+ free (realname); - return s; - } - -Index: gcc-12.1.0/libcpp/macro.cc -=================================================================== ---- gcc-12.1.0.orig/libcpp/macro.cc -+++ gcc-12.1.0/libcpp/macro.cc -@@ -563,7 +563,7 @@ _cpp_builtin_macro_text (cpp_reader *pfi - if (!name) - abort (); - } -- if (pfile->cb.remap_filename) -+ if (pfile->cb.remap_filename && !pfile->state.in_directive) - name = pfile->cb.remap_filename (name); - len = strlen (name); - buf = _cpp_unaligned_alloc (pfile, len * 2 + 3); diff --git a/meta-microblaze/recipes-devtools/gcc/gcc_12.2.bb b/meta-microblaze/recipes-devtools/gcc/gcc_12.2.bb deleted file mode 100644 index c1996ab1..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc_12.2.bb +++ /dev/null @@ -1,14 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require gcc-target.inc - -# Building with thumb enabled on armv4t armv5t fails with -# | gcc-4.8.1-r0/gcc-4.8.1/gcc/cp/decl.c:7438:(.text.unlikely+0x2fa): relocation truncated to fit: R_ARM_THM_CALL against symbol `fancy_abort(char const*, int, char const*)' defined in .glue_7 section in linker stubs -# | gcc-4.8.1-r0/gcc-4.8.1/gcc/cp/decl.c:7442:(.text.unlikely+0x318): additional relocation overflows omitted from the output -ARM_INSTRUCTION_SET:armv4 = "arm" -ARM_INSTRUCTION_SET:armv5 = "arm" - -ARMFPARCHEXT:armv6 = "${@'+fp' if d.getVar('TARGET_FPU') == 'hard' else ''}" -ARMFPARCHEXT:armv7a = "${@'+fp' if d.getVar('TARGET_FPU') == 'hard' else ''}" -ARMFPARCHEXT:armv7ve = "${@'+fp' if d.getVar('TARGET_FPU') == 'hard' else ''}" - -#BBCLASSEXTEND = "nativesdk" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/libgcc-common.inc b/meta-microblaze/recipes-devtools/gcc/libgcc-common.inc deleted file mode 100644 index ac0a5a7b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgcc-common.inc +++ /dev/null @@ -1,163 +0,0 @@ -BPN = "libgcc" - -require gcc-configure-common.inc - -INHIBIT_DEFAULT_DEPS = "1" - -do_configure () { - install -d ${D}${base_libdir} ${D}${libdir} - mkdir -p ${B}/${BPN} - mkdir -p ${B}/${TARGET_SYS}/${BPN}/ - cd ${B}/${BPN} - chmod a+x ${S}/${BPN}/configure - ${S}/${BPN}/configure ${CONFIGUREOPTS} ${EXTRA_OECONF} -} -EXTRACONFFUNCS += "extract_stashed_builddir" -do_configure[depends] += "${COMPILERDEP}" - -do_compile () { - cd ${B}/${BPN} - oe_runmake MULTIBUILDTOP=${B}/${TARGET_SYS}/${BPN}/ -} - -do_install () { - cd ${B}/${BPN} - oe_runmake 'DESTDIR=${D}' MULTIBUILDTOP=${B}/${TARGET_SYS}/${BPN}/ install - - # Move libgcc_s into /lib - mkdir -p ${D}${base_libdir} - if [ -f ${D}${libdir}/nof/libgcc_s.so ]; then - mv ${D}${libdir}/nof/libgcc* ${D}${base_libdir} - else - mv ${D}${libdir}/libgcc* ${D}${base_libdir} || true - fi - - # install the runtime in /usr/lib/ not in /usr/lib/gcc on target - # so that cross-gcc can find it in the sysroot - - mv ${D}${libdir}/gcc/* ${D}${libdir} - rm -rf ${D}${libdir}/gcc/ - # unwind.h is installed here which is shipped in gcc-cross - # as well as target gcc and they are identical so we dont - # ship one with libgcc here - rm -rf ${D}${libdir}/${TARGET_SYS}/${BINV}/include -} - -do_install:append:libc-baremetal () { - if [ "${base_libdir}" != "${libdir}" ]; then - rmdir ${D}${base_libdir} - fi -} -do_install:append:libc-newlib () { - if [ "${base_libdir}" != "${libdir}" ]; then - rmdir ${D}${base_libdir} - fi -} - -# No rpm package is actually created but -dev depends on it, avoid dnf error -DEV_PKG_DEPENDENCY:libc-baremetal = "" -DEV_PKG_DEPENDENCY:libc-newlib = "" - -#BBCLASSEXTEND = "nativesdk" - -addtask multilib_install after do_install before do_package do_populate_sysroot -# this makes multilib gcc files findable for target gcc -# e.g. -# /usr/lib/i586-pokymllib32-linux/4.7/ -# by creating this symlink to it -# /usr/lib64/x86_64-poky-linux/4.7/32 - -fakeroot python do_multilib_install() { - import re - - multilibs = d.getVar('MULTILIB_VARIANTS') - if not multilibs or bb.data.inherits_class('nativesdk', d): - return - - binv = d.getVar('BINV') - - mlprefix = d.getVar('MLPREFIX') - if ('%slibgcc' % mlprefix) != d.getVar('PN'): - return - - if mlprefix: - orig_tune = d.getVar('DEFAULTTUNE_MULTILIB_ORIGINAL') - orig_tune_params = get_tune_parameters(orig_tune, d) - orig_tune_baselib = orig_tune_params['baselib'] - orig_tune_bitness = orig_tune_baselib.replace('lib', '') - if not orig_tune_bitness: - orig_tune_bitness = '32' - - src = '../../../' + orig_tune_baselib + '/' + \ - d.getVar('TARGET_SYS_MULTILIB_ORIGINAL') + '/' + binv + '/' - - dest = d.getVar('D') + d.getVar('libdir') + '/' + \ - d.getVar('TARGET_SYS') + '/' + binv + '/' + orig_tune_bitness - - if os.path.lexists(dest): - os.unlink(dest) - os.symlink(src, dest) - return - - - for ml in multilibs.split(): - tune = d.getVar('DEFAULTTUNE:virtclass-multilib-' + ml) - if not tune: - bb.warn('DEFAULTTUNE:virtclass-multilib-%s is not defined. Skipping...' % ml) - continue - - tune_parameters = get_tune_parameters(tune, d) - tune_baselib = tune_parameters['baselib'] - if not tune_baselib: - bb.warn("Tune %s doesn't have a baselib set. Skipping..." % tune) - continue - - tune_arch = tune_parameters['arch'] - tune_bitness = tune_baselib.replace('lib', '') - if not tune_bitness: - tune_bitness = '32' # /lib => 32bit lib - - tune_abiextension = tune_parameters['abiextension'] - if tune_abiextension: - libcextension = '-gnu' + tune_abiextension - else: - libcextension = '' - - src = '../../../' + tune_baselib + '/' + \ - tune_arch + d.getVar('TARGET_VENDOR') + 'ml' + ml + \ - '-' + d.getVar('TARGET_OS') + libcextension + '/' + binv + '/' - - dest = d.getVar('D') + d.getVar('libdir') + '/' + \ - d.getVar('TARGET_SYS') + '/' + binv + '/' + tune_bitness - - if os.path.lexists(dest): - os.unlink(dest) - os.symlink(src, dest) -} - -def get_original_os(d): - vendoros = d.expand('${TARGET_ARCH}${ORIG_TARGET_VENDOR}-${TARGET_OS}') - for suffix in [d.getVar('ABIEXTENSION'), d.getVar('LIBCEXTENSION')]: - if suffix and vendoros.endswith(suffix): - vendoros = vendoros[:-len(suffix)] - # Arm must use linux-gnueabi not linux as only the former is accepted by gcc - if vendoros.startswith("arm-") and not vendoros.endswith("-gnueabi"): - vendoros = vendoros + "-gnueabi" - return vendoros - -ORIG_TARGET_VENDOR := "${TARGET_VENDOR}" -BASETARGET_SYS = "${@get_original_os(d)}" - -addtask extra_symlinks after do_multilib_install before do_package do_populate_sysroot -fakeroot python do_extra_symlinks() { - if bb.data.inherits_class('nativesdk', d): - return - - targetsys = d.getVar('BASETARGET_SYS') - - if targetsys != d.getVar('TARGET_SYS'): - dest = d.getVar('D') + d.getVar('libdir') + '/' + targetsys - src = d.getVar('TARGET_SYS') - if not os.path.lexists(dest) and os.path.lexists(d.getVar('D') + d.getVar('libdir')): - os.symlink(src, dest) -} diff --git a/meta-microblaze/recipes-devtools/gcc/libgcc-initial.inc b/meta-microblaze/recipes-devtools/gcc/libgcc-initial.inc deleted file mode 100644 index 8251e3c2..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgcc-initial.inc +++ /dev/null @@ -1,58 +0,0 @@ -# -# Notes on the way the OE cross toolchain now works -# -# We need a libgcc to build glibc. Tranditionally we therefore built -# a non-threaded and non-shared compiler (gcc-cross-initial), then use -# that to build libgcc-initial which is used to build glibc which we can -# then build gcc-cross and libgcc against. -# -# We were able to drop the glibc dependency from gcc-cross, with two tweaks: - -# a) specify the minimum glibc version to support in a configure option -# b) create a dummy limits.h file so that later when glibc creates one, -# the headers structure has support for it. We can do this with a simple -# empty file -# -# Once gcc-cross is libc independent, we can use it to build both -# libgcc-initial and then later libgcc. -# -# libgcc-initial is tricky as we need to imitate the non-threaded and -# non-shared case. We can do that by hacking the threading mode back to -# "single" even if gcc reports "posix" and disable libc presence for the -# libgcc-intial build. We have to create the dummy limits.h to avoid -# compiler errors from a missing header. -# -# glibc will fail to link with libgcc-initial due to a missing "exception -# handler" capable libgcc (libgcc_eh.a). Since we know glibc doesn't need -# any exception handler, we can safely symlink to libgcc.a. -# - -require libgcc-common.inc - -DEPENDS = "virtual/${TARGET_PREFIX}gcc" - -LICENSE = "GPL-3.0-with-GCC-exception" - -PACKAGES = "" - -EXTRA_OECONF += "--disable-shared" - -inherit nopackages - -# We really only want this built by things that need it, not any recrdeptask -deltask do_build - -do_configure:prepend () { - install -d ${STAGING_INCDIR} - touch ${STAGING_INCDIR}/limits.h - sed -i -e 's#INHIBIT_LIBC_CFLAGS =.*#INHIBIT_LIBC_CFLAGS = -Dinhibit_libc#' ${B}/gcc/libgcc.mvars - sed -i -e 's#inhibit_libc = false#inhibit_libc = true#' ${B}/gcc/Makefile -} - -do_configure:append () { - sed -i -e 's#thread_header = .*#thread_header = gthr-single.h#' ${B}/${BPN}/Makefile -} - -do_install:append () { - ln -s libgcc.a ${D}${libdir}/${TARGET_SYS}/${BINV}/libgcc_eh.a -} diff --git a/meta-microblaze/recipes-devtools/gcc/libgcc-initial_12.2.bb b/meta-microblaze/recipes-devtools/gcc/libgcc-initial_12.2.bb deleted file mode 100644 index a259082b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgcc-initial_12.2.bb +++ /dev/null @@ -1,5 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require libgcc-initial.inc - -# Building with thumb enabled on armv6t fails -ARM_INSTRUCTION_SET:armv6 = "arm" diff --git a/meta-microblaze/recipes-devtools/gcc/libgcc-initial_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/libgcc-initial_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgcc-initial_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/libgcc.inc b/meta-microblaze/recipes-devtools/gcc/libgcc.inc deleted file mode 100644 index 84a2d930..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgcc.inc +++ /dev/null @@ -1,53 +0,0 @@ -require libgcc-common.inc - -DEPENDS = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++ virtual/${MLPREFIX}libc" - -do_install:append:class-target () { - if [ "${TCLIBC}" != "glibc" ]; then - case "${TARGET_OS}" in - "linux-musl" | "linux-*spe") extra_target_os="linux";; - "linux-musleabi") extra_target_os="linux-gnueabi";; - *) extra_target_os="linux";; - esac - if [ ! -e ${D}${libdir}/${TARGET_ARCH}${TARGET_VENDOR}-$extra_target_os ]; then - ln -s ${TARGET_SYS} ${D}${libdir}/${TARGET_ARCH}${TARGET_VENDOR}-$extra_target_os - fi - fi - if [ -n "${@ bb.utils.contains('TUNE_CCARGS_MFLOAT', 'hard', 'hf', '', d)}" ]; then - case "${TARGET_OS}" in - "linux-musleabi") extra_target_os="linux-musleabihf";; - "linux-gnueabi") extra_target_os="linux-gnueabihf";; - esac - if [ ! -e ${D}${libdir}/${TARGET_ARCH}${TARGET_VENDOR}-$extra_target_os ]; then - ln -s ${TARGET_SYS} ${D}${libdir}/${TARGET_ARCH}${TARGET_VENDOR}-$extra_target_os - fi - fi -} - -PACKAGES = "\ - ${PN} \ - ${PN}-dev \ - ${PN}-dbg \ -" - -# All libgcc source is marked with the exception. -# -LICENSE:${PN} = "GPL-3.0-with-GCC-exception" -LICENSE:${PN}-dev = "GPL-3.0-with-GCC-exception" -LICENSE:${PN}-dbg = "GPL-3.0-with-GCC-exception" - - -FILES:${PN}-dev = "\ - ${base_libdir}/libgcc*.so \ - ${@oe.utils.conditional('BASETARGET_SYS', '${TARGET_SYS}', '', '${libdir}/${BASETARGET_SYS}', d)} \ - ${libdir}/${TARGET_SYS}/${BINV}* \ - ${libdir}/${TARGET_ARCH}${TARGET_VENDOR}* \ -" - -do_package[depends] += "virtual/${MLPREFIX}libc:do_packagedata" -do_package_write_ipk[depends] += "virtual/${MLPREFIX}libc:do_packagedata" -do_package_write_deb[depends] += "virtual/${MLPREFIX}libc:do_packagedata" -do_package_write_rpm[depends] += "virtual/${MLPREFIX}libc:do_packagedata" - -INSANE_SKIP:${PN}-dev = "staticdev" - diff --git a/meta-microblaze/recipes-devtools/gcc/libgcc_12.2.bb b/meta-microblaze/recipes-devtools/gcc/libgcc_12.2.bb deleted file mode 100644 index f88963b0..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgcc_12.2.bb +++ /dev/null @@ -1,5 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require libgcc.inc - -# Building with thumb enabled on armv6t fails -ARM_INSTRUCTION_SET:armv6 = "arm" diff --git a/meta-microblaze/recipes-devtools/gcc/libgcc_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/libgcc_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgcc_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/libgfortran.inc b/meta-microblaze/recipes-devtools/gcc/libgfortran.inc deleted file mode 100644 index 99fdd89c..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgfortran.inc +++ /dev/null @@ -1,88 +0,0 @@ -require gcc-configure-common.inc - -EXTRA_OECONF_PATHS = "\ - --with-sysroot=/not/exist \ - --with-build-sysroot=${STAGING_DIR_TARGET} \ -" - -# An arm hard float target like raspberrypi4 won't build -# as CFLAGS don't make it to the fortran compiler otherwise -# (the configure script sets FC to $GFORTRAN unconditionally) -export GFORTRAN = "${FC}" - -do_configure () { - for target in libbacktrace libgfortran - do - rm -rf ${B}/${TARGET_SYS}/$target/ - mkdir -p ${B}/${TARGET_SYS}/$target/ - cd ${B}/${TARGET_SYS}/$target/ - chmod a+x ${S}/$target/configure - relpath=${@os.path.relpath("${S}", "${B}/${TARGET_SYS}")} - ../$relpath/$target/configure ${CONFIGUREOPTS} ${EXTRA_OECONF} - # Easiest way to stop bad RPATHs getting into the library since we have a - # broken libtool here - sed -i -e 's/hardcode_into_libs=yes/hardcode_into_libs=no/' ${B}/${TARGET_SYS}/$target/libtool - done -} -EXTRACONFFUNCS += "extract_stashed_builddir" -do_configure[depends] += "${COMPILERDEP}" - -do_compile () { - for target in libbacktrace libgfortran - do - cd ${B}/${TARGET_SYS}/$target/ - oe_runmake MULTIBUILDTOP=${B}/${TARGET_SYS}/$target/ - done -} - -do_install () { - cd ${B}/${TARGET_SYS}/libgfortran/ - oe_runmake 'DESTDIR=${D}' MULTIBUILDTOP=${B}/${TARGET_SYS}/libgfortran/ install - if [ -d ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/finclude ]; then - rmdir --ignore-fail-on-non-empty -p ${D}${libdir}/gcc/${TARGET_SYS}/${BINV}/finclude - fi - if [ -d ${D}${infodir} ]; then - rmdir --ignore-fail-on-non-empty -p ${D}${infodir} - fi - chown -R root:root ${D} -} - -INHIBIT_DEFAULT_DEPS = "1" -DEPENDS = "gcc-runtime gcc-cross-${TARGET_ARCH}" - -#BBCLASSEXTEND = "nativesdk" - -PACKAGES = "\ - ${PN}-dbg \ - libgfortran \ - libgfortran-dev \ - libgfortran-staticdev \ -" - -LICENSE:${PN} = "GPL-3.0-with-GCC-exception" -LICENSE:${PN}-dev = "GPL-3.0-with-GCC-exception" -LICENSE:${PN}-dbg = "GPL-3.0-with-GCC-exception" - -FILES:${PN} = "${libdir}/libgfortran.so.*" -FILES:${PN}-dev = "\ - ${libdir}/libgfortran*.so \ - ${libdir}/libgfortran.spec \ - ${libdir}/libgfortran.la \ - ${libdir}/gcc/${TARGET_SYS}/${BINV}/libgfortranbegin.* \ - ${libdir}/gcc/${TARGET_SYS}/${BINV}/libcaf_single* \ - ${libdir}/gcc/${TARGET_SYS}/${BINV}/finclude/ \ - ${libdir}/gcc/${TARGET_SYS}/${BINV}/include/ \ -" -FILES:${PN}-staticdev = "${libdir}/libgfortran.a" - -INSANE_SKIP:${MLPREFIX}libgfortran-dev = "staticdev" - -do_package_write_ipk[depends] += "virtual/${MLPREFIX}libc:do_packagedata" -do_package_write_deb[depends] += "virtual/${MLPREFIX}libc:do_packagedata" -do_package_write_rpm[depends] += "virtual/${MLPREFIX}libc:do_packagedata" - -python __anonymous () { - f = d.getVar("FORTRAN") - if "fortran" not in f: - raise bb.parse.SkipRecipe("libgfortran needs fortran support to be enabled in the compiler") -} diff --git a/meta-microblaze/recipes-devtools/gcc/libgfortran_12.2.bb b/meta-microblaze/recipes-devtools/gcc/libgfortran_12.2.bb deleted file mode 100644 index 71dd8b4b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgfortran_12.2.bb +++ /dev/null @@ -1,3 +0,0 @@ -require recipes-devtools/gcc/gcc-${PV}.inc -require libgfortran.inc - diff --git a/meta-microblaze/recipes-devtools/gcc/libgfortran_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/libgfortran_13.%.bbappend deleted file mode 100644 index d1df2061..00000000 --- a/meta-microblaze/recipes-devtools/gcc/libgfortran_13.%.bbappend +++ /dev/null @@ -1 +0,0 @@ -require microblaze-block.inc diff --git a/meta-microblaze/recipes-devtools/gcc/microblaze-block.inc b/meta-microblaze/recipes-devtools/gcc/microblaze-block.inc deleted file mode 100644 index 67c40845..00000000 --- a/meta-microblaze/recipes-devtools/gcc/microblaze-block.inc +++ /dev/null @@ -1 +0,0 @@ -COMPATIBLE_HOST:microblaze = "^$" -- cgit v1.2.3-54-g00ecf From 76896af103e13176e7bcbc5e57d5357249c6a0f6 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 24 Jul 2024 11:41:48 -0600 Subject: meta-microblaze: Update to gcc 13 Signed-off-by: Mark Hatle --- ...CAL-Testsuite-builtins-tests-require-fpic.patch | 35 - ...0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch | 31 - ...ejagnu-static-testing-on-qemu-suppress-wa.patch | 35 - ...uite-Add-MicroBlaze-to-target-supports-fo.patch | 35 - ...-testsuite-Update-MicroBlaze-strings-test.patch | 36 - ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch | 67 - ...uite-Add-MicroBlaze-to-check_profiling_av.patch | 28 - ...-Patch-microblaze-Fix-atomic-side-effects.patch | 68 - ...icroblaze-Fix-atomic-boolean-return-value.patch | 40 - ...blaze-Fix-the-Microblaze-crash-with-msmal.patch | 36 - ...ch-microblaze-Added-ashrsi3_with_size_opt.patch | 48 - ...-microblaze-Use-bralid-for-profiler-calls.patch | 26 - ...-Patch-microblaze-Removed-moddi3-routinue.patch | 160 -- ...icroblaze-Add-INIT_PRIORITY-support-Added.patch | 90 - ...15-Patch-microblaze-Add-optimized-lshrsi3.patch | 81 - .../0016-Patch-microblaze-Add-cbranchsi4_reg.patch | 147 -- ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch | 58 - ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch | 63 - ...-microblaze-Update-ashlsi3-movsf-patterns.patch | 75 - ...icroblaze-8-stage-pipeline-for-microblaze.patch | 177 -- ...-Patch-microblaze-Correct-the-const-high-.patch | 58 - ...aze-Fix-internal-compiler-error-with-msma.patch | 31 - ...blaze-Fix-the-calculation-of-high-word-in.patch | 37 - ...roBlaze-this-patch-has-1.Fixed-the-bug-in.patch | 373 --- ...5-Fixing-the-issue-with-the-builtin_alloc.patch | 44 - ...blaze-Removed-fsqrt-generation-for-double.patch | 38 - ...oBlaze-Intial-commit-of-64-bit-Microblaze.patch | 784 ------- .../0028-Intial-commit-for-64bit-MB-sources.patch | 2442 -------------------- ...Blaze-re-arrangement-of-the-compare-branc.patch | 269 --- ...blaze-previous-commit-broke-the-handling-.patch | 28 - ...-Microblaze-Support-of-multilibs-with-m64.patch | 77 - .../0032-Patch-MicroBlaze-Fixed-issues-like.patch | 70 - .../gcc/gcc-12/0033-Patch-MicroBlaze.patch | 305 --- .../0034-Added-double-arith-instructions.patch | 135 -- ...ssue-in-the-delay-slot-with-swap-instruct.patch | 37 - ...oad-store-issue-with-the-32bit-arith-libr.patch | 256 -- ...ing-the-Dwarf-support-to-64bit-Microblaze.patch | 25 - ...38-fixing-the-typo-errors-in-umodsi3-file.patch | 29 - ...xing-the-32bit-LTO-related-issue9-1014024.patch | 68 - ...issing-stack-adjustment-in-prologue-of-mo.patch | 25 - ...blaze-corrected-SPN-for-dlong-instruction.patch | 29 - ...-the-long-long-long-mingw-toolchain-issue.patch | 59 - ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch | 47 - ...blaze-We-will-check-the-possibility-of-pe.patch | 87 - ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch | 466 ---- ...blaze-MB-64-removal-of-barrel-shift-instr.patch | 477 ---- ...B-64-single-register-arithmetic-instructi.patch | 107 - ...Blaze-Added-support-for-64-bit-Immediate-.patch | 44 - ...blaze-Fix-Compiler-crash-with-freg-struct.patch | 76 - ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch | 50 - ...oblaze-Reducing-Stack-space-for-arguments.patch | 189 -- .../gcc/gcc-12/0052-Patch-MicroBlaze.patch | 73 - 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meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-source_13.%.bbappend delete mode 100644 meta-vitis-tc/recipes-devtools/gcc/gcc-12/additional-microblaze-multilibs.patch delete mode 100644 meta-vitis-tc/recipes-devtools/gcc/gcc-12/riscv-multilib-generator-python.patch create mode 100644 meta-vitis-tc/recipes-devtools/gcc/gcc-13/additional-microblaze-multilibs.patch delete mode 100644 meta-vitis-tc/recipes-devtools/gcc/gcc-source_12.%.bbappend (limited to 'meta-microblaze/recipes-devtools') diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch deleted file mode 100644 index 1099a0e8..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 376b0ee790231a99fe50b50e20070c104bbba0d8 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 13:13:57 +0530 -Subject: [PATCH 01/53] LOCAL]: Testsuite - builtins tests require fpic - Signed-off-by: David Holsgrove - -Conflicts: - - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ---- - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -index fb47f51f90c..d9ecf045554 100644 ---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] - lappend additional_flags "-Wl,--allow-multiple-definition" - } - -+<<<<<<< HEAD -+======= -+if [istarget "microblaze*-*-linux*"] { -+ lappend additional_flags "-Wl,-zmuldefs" -+ lappend additional_flags "-fPIC" -+} -+ -+>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic - foreach src [lsort [find $srcdir/$subdir *.c]] { - if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { - c-torture-execute [list $src \ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch deleted file mode 100644 index 061dfc86..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch +++ /dev/null @@ -1,31 +0,0 @@ -From b1aea8e71692065497ee3e9be5a9f1fccecf5685 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 14:31:10 +0530 -Subject: [PATCH 02/53] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This - particular testcase fails with a timeout. Instead, fail it at compile-time - for microblaze. This speeds up the testsuite without removing it from the - FAIL reports. - -Signed-off-by: Edgar E. Iglesias ---- - gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C -index 3862756083d..db9f990f781 100644 ---- a/gcc/testsuite/g++.dg/opt/memcpy1.C -+++ b/gcc/testsuite/g++.dg/opt/memcpy1.C -@@ -4,6 +4,10 @@ - // { dg-do compile } - // { dg-options "-O" } - -+#if defined (__MICROBLAZE__) -+#error "too slow on mb. Investigate." -+#endif -+ - typedef unsigned char uint8_t; - typedef uint8_t uint8; - __extension__ typedef __SIZE_TYPE__ size_t; --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch deleted file mode 100644 index 1b5d428e..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch +++ /dev/null @@ -1,35 +0,0 @@ -From af78edb2cb91c55f54ac2d720cee9871da13b845 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 15:46:28 +0530 -Subject: [PATCH 03/53] [LOCAL]: For dejagnu static testing on qemu, suppress - warnings about multiple definitions from the test function and libc in line - with method used by powerpc. Dynamic linking and using a qemu binary which - understands sysroot resolves all test failures with builtins - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ---- - 1 file changed, 4 deletions(-) - -diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -index d9ecf045554..d6c2b04f286 100644 ---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] - lappend additional_flags "-Wl,--allow-multiple-definition" - } - --<<<<<<< HEAD --======= - if [istarget "microblaze*-*-linux*"] { - lappend additional_flags "-Wl,-zmuldefs" -- lappend additional_flags "-fPIC" - } - -->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic - foreach src [lsort [find $srcdir/$subdir *.c]] { - if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { - c-torture-execute [list $src \ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch deleted file mode 100644 index 8db33100..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 34b7dd28e3fe40f55ec7f6df3f000dd797d6c1cc Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 15:50:35 +0530 -Subject: [PATCH 04/53] [Patch, testsuite]: Add MicroBlaze to target-supports - for atomic buil. .tin tests - -MicroBlaze added to supported targets for atomic builtin tests. - -Changelog/testsuite - -2014-02-14 David Holsgrove - - * gcc/testsuite/lib/target-supports.exp: Add microblaze to - check_effective_target_sync_int_long. - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/lib/target-supports.exp | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index 244fe2306f4..c19f251f0d2 100644 ---- a/gcc/testsuite/lib/target-supports.exp -+++ b/gcc/testsuite/lib/target-supports.exp -@@ -8639,6 +8639,7 @@ proc check_effective_target_sync_int_long { } { - && [check_effective_target_arm_acq_rel]) - || [istarget bfin*-*linux*] - || [istarget hppa*-*linux*] -+ || [istarget microblaze*-*linux*] - || [istarget s390*-*-*] - || [istarget powerpc*-*-*] - || [istarget cris-*-*] --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch deleted file mode 100644 index 0fb32850..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 2d0b5d68aff95a95dfb4ed0b207849658502bd53 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 16:20:01 +0530 -Subject: [PATCH 05/53] [Patch, testsuite]: Update MicroBlaze strings test for - new scan-assembly output resulting in use of $LC label - -ChangeLog/testsuite - -2014-02-14 David Holsgrove - - * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update - to include $LC label. - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/gcc.target/microblaze/others/strings1.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c -index efaf3c660ea..347872360d3 100644 ---- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c -+++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c -@@ -3,6 +3,10 @@ - /* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ - /* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ - -+/* { dg-final { scan-assembler "\.rodata*" } } */ -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ -+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ -+ - #include - - extern void somefunc (char *); --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch deleted file mode 100644 index a82f11cc..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 20b6479f240bfebb46daad06839286a7abcff56c Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:14:15 +0530 -Subject: [PATCH 06/53] [Patch, testsuite]: Allow MicroBlaze .weakext pattern - in regex match Extend regex pattern to include optional ext at the end of - .weak to match the MicroBlaze weak label .weakext - -ChangeLog/testsuite - -2014-02-14 David Holsgrove - - * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler - pattern to take optional ext after .weak. - * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. - -Signed-off-by: David Holsgrove - -Conflicts: - - gcc/testsuite/g++.dg/abi/rtti3.C ---- - gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++-- - gcc/testsuite/g++.dg/abi/thunk3.C | 2 +- - gcc/testsuite/g++.dg/abi/thunk4.C | 2 +- - 3 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C -index 0cc7d3e79d0..f284cd9255c 100644 ---- a/gcc/testsuite/g++.dg/abi/rtti3.C -+++ b/gcc/testsuite/g++.dg/abi/rtti3.C -@@ -3,8 +3,8 @@ - - // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } --// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } } --// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } - // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } } - // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } } - -diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C -index f2347f79ecd..dcec8a771a1 100644 ---- a/gcc/testsuite/g++.dg/abi/thunk3.C -+++ b/gcc/testsuite/g++.dg/abi/thunk3.C -@@ -1,5 +1,5 @@ - // { dg-require-weak "" } --// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } - // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } - - struct Base -diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C -index 6e8f124bc5e..d1d34fe1e4a 100644 ---- a/gcc/testsuite/g++.dg/abi/thunk4.C -+++ b/gcc/testsuite/g++.dg/abi/thunk4.C -@@ -1,6 +1,6 @@ - // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } --// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } - // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } - - struct Base --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch deleted file mode 100644 index 736f5cd1..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0efefd8ac71dd084c745402afdf07319de9774c6 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:34:27 +0530 -Subject: [PATCH 07/53] [Patch, testsuite]: Add MicroBlaze to - check_profiling_available Testsuite, add microblaze*-*-* target in - check_profiling_available inline with other archs setting - profiling_available_saved to 0 - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/lib/target-supports.exp | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index c19f251f0d2..c136c93e673 100644 ---- a/gcc/testsuite/lib/target-supports.exp -+++ b/gcc/testsuite/lib/target-supports.exp -@@ -729,6 +729,7 @@ proc check_profiling_available { test_what } { - || [istarget m68k-*-elf] - || [istarget m68k-*-uclinux*] - || [istarget mips*-*-elf*] -+ || [istarget microblaze*-*-*] - || [istarget mmix-*-*] - || [istarget mn10300-*-elf*] - || [istarget moxie-*-elf*] --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch deleted file mode 100644 index 451070c0..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 42ab0f7a2e6834feed456d00b3e2ec0ae2532a41 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:41:43 +0530 -Subject: [PATCH 08/53] [Patch, microblaze]: Fix atomic side effects. In - atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions - during optimization. Previously, the outputs were considered unused; this - generated assembly code with undefined side effects after invocation of the - atomic. - -Signed-off-by: Kirk Meyer -Signed-off-by: David Holsgrove - -Conflicts: - gcc/config/microblaze/microblaze.md ---- - gcc/config/microblaze/microblaze.md | 3 +++ - gcc/config/microblaze/sync.md | 21 +++++++++++++-------- - 2 files changed, 16 insertions(+), 8 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 0765ff930c6..ea7f74f1dff 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -43,6 +43,9 @@ - (UNSPEC_TLS 106) ;; jump table - (UNSPEC_SET_TEXT 107) ;; set text start - (UNSPEC_TEXT 108) ;; data text relative -+ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool) -+ (UNSPECV_CAS_VAL 202) ;; compare and swap (val) -+ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem) - ]) - - (define_c_enum "unspec" [ -diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index ae8955ce691..77c3ce8ff27 100644 ---- a/gcc/config/microblaze/sync.md -+++ b/gcc/config/microblaze/sync.md -@@ -18,14 +18,19 @@ - ;; . - - (define_insn "atomic_compare_and_swapsi" -- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output -- (match_operand:SI 1 "register_operand" "=&d") ;; val output -- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory -- (match_operand:SI 3 "register_operand" "d") ;; expected value -- (match_operand:SI 4 "register_operand" "d") ;; desired value -- (match_operand:SI 5 "const_int_operand" "") ;; is_weak -- (match_operand:SI 6 "const_int_operand" "") ;; mod_s -- (match_operand:SI 7 "const_int_operand" "") ;; mod_f -+ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output -+ (unspec_volatile:SI -+ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory -+ (match_operand:SI 3 "register_operand" "d") ;; expected value -+ (match_operand:SI 4 "register_operand" "d")] ;; desired value -+ UNSPECV_CAS_BOOL)) -+ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output -+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL)) -+ (set (match_dup 2) -+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM)) -+ (match_operand:SI 5 "const_int_operand" "") ;; is_weak -+ (match_operand:SI 6 "const_int_operand" "") ;; mod_s -+ (match_operand:SI 7 "const_int_operand" "") ;; mod_f - (clobber (match_scratch:SI 8 "=&d"))] - "" - { --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch deleted file mode 100644 index c7efbb07..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch +++ /dev/null @@ -1,40 +0,0 @@ -From a1b8136a157c549f0f65c14d628e694310ca0d23 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:45:45 +0530 -Subject: [PATCH 09/53] [Patch, microblaze]: Fix atomic boolean return value. - In atomic_compare_and_swapsi, fix boolean return value. Previously, it - contained zero if successful and non-zero if unsuccessful. - -Signed-off-by: Kirk Meyer -Signed-off-by: David Holsgrove ---- - gcc/config/microblaze/sync.md | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index 77c3ce8ff27..573ce4765a0 100644 ---- a/gcc/config/microblaze/sync.md -+++ b/gcc/config/microblaze/sync.md -@@ -34,15 +34,16 @@ - (clobber (match_scratch:SI 8 "=&d"))] - "" - { -- output_asm_insn ("addc \tr0,r0,r0", operands); -+ output_asm_insn ("add \t%0,r0,r0", operands); - output_asm_insn ("lwx \t%1,%y2,r0", operands); - output_asm_insn ("addic\t%8,r0,0", operands); - output_asm_insn ("bnei \t%8,.-8", operands); -- output_asm_insn ("cmp \t%0,%1,%3", operands); -- output_asm_insn ("bnei \t%0,.+16", operands); -+ output_asm_insn ("cmp \t%8,%1,%3", operands); -+ output_asm_insn ("bnei \t%8,.+20", operands); - output_asm_insn ("swx \t%4,%y2,r0", operands); - output_asm_insn ("addic\t%8,r0,0", operands); - output_asm_insn ("bnei \t%8,.-28", operands); -+ output_asm_insn ("addi \t%0,r0,1", operands); - return ""; - } - ) --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch deleted file mode 100644 index 1bffafa9..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 1ab5b8af098d100a1d7af05cca680b3c7181549d Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:50:17 +0530 -Subject: [PATCH 10/53] [Patch, microblaze]: Fix the Microblaze crash with - msmall-divides flag Compiler is crashing when we use msmall-divides and - mxl-barrel-shift flag. This is because when use above flags - microblaze_expand_divide function will be called for division operation. In - microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't - have subreg register due to this compiler was crashing. Changed the logic to - avoid sub_reg call - -Signed-off-by:Nagaraju Mekala - -Conflicts: - gcc/config/microblaze/microblaze.c ---- - gcc/config/microblaze/microblaze.cc | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index f32effecfb6..6922dd94af7 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -3710,8 +3710,7 @@ microblaze_expand_divide (rtx operands[]) - mem_rtx = gen_rtx_MEM (QImode, - gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); - -- insn = emit_insn (gen_movqi (regqi, mem_rtx)); -- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); -+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); - JUMP_LABEL (jump) = div_end_label; - LABEL_NUSES (div_end_label) = 1; --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch deleted file mode 100644 index 1bd73b8a..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 7dd4ae2ad891094aa85a907b168cbdce744789e9 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:52:56 +0530 -Subject: [PATCH 11/53] [Patch, microblaze]: Added ashrsi3_with_size_opt Added - ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os - optimization is used. lshrsi3_with_size_opt is being removed as it has - conflicts with unsigned int variables - -Signed-off-by:Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index ea7f74f1dff..9fbb3113f3c 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1508,6 +1508,27 @@ - (set_attr "length" "4,4")] - ) - -+(define_insn "*ashrsi3_with_size_opt" -+ [(set (match_operand:SI 0 "register_operand" "=&d") -+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "immediate_operand" "I")))] -+ "(INTVAL (operands[2]) > 5 && optimize_size)" -+ { -+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("ori\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addik\t%3,%3,-1", operands); -+ output_asm_insn ("bneid\t%3,.-4", operands); -+ return "sra\t%0,%0"; -+ } -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "20")] -+) -+ - (define_insn "*ashrsi_inline" - [(set (match_operand:SI 0 "register_operand" "=&d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch deleted file mode 100644 index f40fff9a..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 12d7e086376916ef61e2c48639671fd0f7c8fbbf Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 10:57:19 +0530 -Subject: [PATCH 12/53] [Patch, microblaze]: Use bralid for profiler calls - Signed-off-by: Edgar E. Iglesias - ---- - gcc/config/microblaze/microblaze.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index d28bc766de8..cd544f2030e 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -486,7 +486,7 @@ typedef struct microblaze_args - - #define FUNCTION_PROFILER(FILE, LABELNO) { \ - { \ -- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \ -+ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \ - } \ - } - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch deleted file mode 100644 index 5c927264..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch +++ /dev/null @@ -1,160 +0,0 @@ -From cd8c9f3c43b266628d1585b74fc78f3e34a33c44 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 17:36:16 +0530 -Subject: [PATCH 13/53] [Patch, microblaze]: Removed moddi3 routinue Using the - default moddi3 function as the existing implementation has many bugs - -Signed-off-by:Nagaraju - -Conflicts: - libgcc/config/microblaze/moddi3.S ---- - libgcc/config/microblaze/moddi3.S | 121 -------------------------- - libgcc/config/microblaze/t-microblaze | 3 +- - 2 files changed, 1 insertion(+), 123 deletions(-) - delete mode 100644 libgcc/config/microblaze/moddi3.S - -diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S -deleted file mode 100644 -index 9b77865df38..00000000000 ---- a/libgcc/config/microblaze/moddi3.S -+++ /dev/null -@@ -1,121 +0,0 @@ --################################### --# --# Copyright (C) 2009-2022 Free Software Foundation, Inc. --# --# Contributed by Michael Eager . --# --# This file is free software; you can redistribute it and/or modify it --# under the terms of the GNU General Public License as published by the --# Free Software Foundation; either version 3, or (at your option) any --# later version. --# --# GCC is distributed in the hope that it will be useful, but WITHOUT --# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public --# License for more details. --# --# Under Section 7 of GPL version 3, you are granted additional --# permissions described in the GCC Runtime Library Exception, version --# 3.1, as published by the Free Software Foundation. --# --# You should have received a copy of the GNU General Public License and --# a copy of the GCC Runtime Library Exception along with this program; --# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --# . --# --# modsi3.S --# --# modulo operation for 64 bit integers. --# --####################################### -- -- --/* An executable stack is *not* required for these functions. */ --#ifdef __linux__ --.section .note.GNU-stack,"",%progbits --.previous --#endif -- -- .globl __moddi3 -- .ent __moddi3 --__moddi3: -- .frame r1,0,r15 -- --#Change the stack pointer value and Save callee saved regs -- addik r1,r1,-24 -- swi r25,r1,0 -- swi r26,r1,4 -- swi r27,r1,8 # used for sign -- swi r28,r1,12 # used for loop count -- swi r29,r1,16 # Used for div value High -- swi r30,r1,20 # Used for div value Low -- --#Check for Zero Value in the divisor/dividend -- OR r9,r5,r6 # Check for the op1 being zero -- BEQID r9,$LaResult_Is_Zero # Result is zero -- OR r9,r7,r8 # Check for the dividend being zero -- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error -- BGEId r5,$La1_Pos -- XOR r27,r5,r7 # Get the sign of the result -- RSUBI r6,r6,0 # Make dividend positive -- RSUBIC r5,r5,0 # Make dividend positive --$La1_Pos: -- BGEI r7,$La2_Pos -- RSUBI r8,r8,0 # Make Divisor Positive -- RSUBIC r9,r9,0 # Make Divisor Positive --$La2_Pos: -- ADDIK r4,r0,0 # Clear mod low -- ADDIK r3,r0,0 # Clear mod high -- ADDIK r29,r0,0 # clear div high -- ADDIK r30,r0,0 # clear div low -- ADDIK r28,r0,64 # Initialize the loop count -- # First part try to find the first '1' in the r5/r6 --$LaDIV1: -- ADD r6,r6,r6 -- ADDC r5,r5,r5 # left shift logical r5 -- BGEID r5,$LaDIV1 -- ADDIK r28,r28,-1 --$LaDIV2: -- ADD r6,r6,r6 -- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry -- ADDC r4,r4,r4 # Move that bit into the Mod register -- ADDC r3,r3,r3 # Move carry into high mod register -- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor -- bnei r18,$L_High_EQ -- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h] --$L_High_EQ: -- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L] -- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H] -- BLTi r25,$LaMOD_TOO_SMALL -- OR r3,r0,r25 # move r25 to mod [h] -- OR r4,r0,r26 # move r26 to mod [l] -- ADDI r30,r30,1 -- ADDC r29,r29,r0 --$LaMOD_TOO_SMALL: -- ADDIK r28,r28,-1 -- BEQi r28,$LaLOOP_END -- ADD r30,r30,r30 # Shift in the '1' into div [low] -- ADDC r29,r29,r29 # Move the carry generated into high -- BRI $LaDIV2 # Div2 --$LaLOOP_END: -- BGEI r27,$LaRETURN_HERE -- rsubi r30,r30,0 -- rsubc r29,r29,r0 -- BRI $LaRETURN_HERE --$LaDiv_By_Zero: --$LaResult_Is_Zero: -- or r29,r0,r0 # set result to 0 [High] -- or r30,r0,r0 # set result to 0 [Low] --$LaRETURN_HERE: --# Restore values of CSRs and that of r29 and the divisor and the dividend -- -- lwi r25,r1,0 -- lwi r26,r1,4 -- lwi r27,r1,8 -- lwi r28,r1,12 -- lwi r29,r1,16 -- lwi r30,r1,20 -- rtsd r15,8 -- addik r1,r1,24 -- .end __moddi3 -- -diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 96959f0292b..8d954a49575 100644 ---- a/libgcc/config/microblaze/t-microblaze -+++ b/libgcc/config/microblaze/t-microblaze -@@ -1,8 +1,7 @@ --LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3 -+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 - - LIB2ADD += \ - $(srcdir)/config/microblaze/divsi3.S \ -- $(srcdir)/config/microblaze/moddi3.S \ - $(srcdir)/config/microblaze/modsi3.S \ - $(srcdir)/config/microblaze/muldi3_hard.S \ - $(srcdir)/config/microblaze/mulsi3.S \ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch deleted file mode 100644 index f8bcabe3..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 30aa7cef2dd076637155384fba539838ddaf0163 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 12 Sep 2022 20:20:00 +0530 -Subject: [PATCH 14/53] [Patch, microblaze]: Add INIT_PRIORITY support Added - TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. - -These macros allows users to control the order of initialization -of objects defined at namespace scope with the init_priority -attribute by specifying a relative priority, a constant integral -expression currently bounded between 101 and 65535 inclusive. - -Lower numbers indicate a higher priority. ---- - gcc/config/microblaze/microblaze.cc | 53 +++++++++++++++++++++++++++++ - 1 file changed, 53 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 6922dd94af7..4b0621db168 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2635,6 +2635,53 @@ print_operand_address (FILE * file, rtx addr) - } - } - -+/* Output an element in the table of global constructors. */ -+void -+microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) -+{ -+ const char *section = ".ctors"; -+ char buf[16]; -+ -+ if (priority != DEFAULT_INIT_PRIORITY) -+ { -+ sprintf (buf, ".ctors.%.5u", -+ /* Invert the numbering so the linker puts us in the proper -+ order; constructors are run from right to left, and the -+ linker sorts in increasing order. */ -+ MAX_INIT_PRIORITY - priority); -+ section = buf; -+ } -+ -+ switch_to_section (get_section (section, 0, NULL)); -+ assemble_align (POINTER_SIZE); -+ fputs ("\t.word\t", asm_out_file); -+ output_addr_const (asm_out_file, symbol); -+ fputs ("\n", asm_out_file); -+} -+ -+/* Output an element in the table of global destructors. */ -+void -+microblaze_asm_destructor (rtx symbol, int priority) -+{ -+ const char *section = ".dtors"; -+ char buf[16]; -+ if (priority != DEFAULT_INIT_PRIORITY) -+ { -+ sprintf (buf, ".dtors.%.5u", -+ /* Invert the numbering so the linker puts us in the proper -+ order; constructors are run from right to left, and the -+ linker sorts in increasing order. */ -+ MAX_INIT_PRIORITY - priority); -+ section = buf; -+ } -+ -+ switch_to_section (get_section (section, 0, NULL)); -+ assemble_align (POINTER_SIZE); -+ fputs ("\t.word\t", asm_out_file); -+ output_addr_const (asm_out_file, symbol); -+ fputs ("\n", asm_out_file); -+} -+ - /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol - is used, so that we don't emit an .extern for it in - microblaze_asm_file_end. */ -@@ -3976,6 +4023,12 @@ microblaze_starting_frame_offset (void) - #undef TARGET_ATTRIBUTE_TABLE - #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table - -+#undef TARGET_ASM_CONSTRUCTOR -+#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor -+ -+#undef TARGET_ASM_DESTRUCTOR -+#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor -+ - #undef TARGET_IN_SMALL_DATA_P - #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch deleted file mode 100644 index 0f7d356f..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch +++ /dev/null @@ -1,81 +0,0 @@ -From b9bb669d9404bd04676f09c793310e1b7f228674 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 15:23:57 +0530 -Subject: [PATCH 15/53] [Patch, microblaze]: Add optimized lshrsi3 When barrel - shifter is not present, the immediate value is greater than #5 and - optimization is -OS, the compiler will generate shift operation using loop. - -Changelog - -2013-11-26 David Holsgrove - - * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn - -ChangeLog/testsuite - -2014-02-12 David Holsgrove - - * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. - -Signed-off-by:Nagaraju -Signed-off-by: David Holsgrove ---- - gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++ - .../microblaze/others/lshrsi_Os_1.c | 13 ++++++++++++ - 2 files changed, 34 insertions(+) - create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 9fbb3113f3c..52308cce0cb 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1618,6 +1618,27 @@ - (set_attr "length" "4,4")] - ) - -+(define_insn "*lshrsi3_with_size_opt" -+ [(set (match_operand:SI 0 "register_operand" "=&d") -+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "immediate_operand" "I")))] -+ "(INTVAL (operands[2]) > 5 && optimize_size)" -+ { -+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("ori\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addik\t%3,%3,-1", operands); -+ output_asm_insn ("bneid\t%3,.-4", operands); -+ return "srl\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "SI") -+ (set_attr "length" "20")] -+) -+ - (define_insn "*lshrsi_inline" - [(set (match_operand:SI 0 "register_operand" "=&d") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") -diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c -new file mode 100644 -index 00000000000..32a3be7c76a ---- /dev/null -+++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c -@@ -0,0 +1,13 @@ -+/* { dg-options "-Os -mno-xl-barrel-shift" } */ -+ -+void testfunc(void) -+{ -+ unsigned volatile int z = 8192; -+ z >>= 8; -+} -+/* { dg-final { scan-assembler-not "\bsrli" } } */ -+/* { dg-final { scan-assembler "\ori\tr18,r0" } } */ -+/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */ -+/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */ -+/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ -+/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch deleted file mode 100644 index 19ae324d..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch +++ /dev/null @@ -1,147 +0,0 @@ -From 08d7bb4062024f3e34fbb17d695f8fa2c9e1b305 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 17:04:37 +0530 -Subject: [PATCH 16/53] [Patch, microblaze]: Add cbranchsi4_reg This patch - optimizes the generation of pcmpne/pcmpeq instruction if the compare - instruction has no immediate values.For the immediate values the xor - instruction is generated - -Signed-off-by: Nagaraju Mekala -Signed-off-by: Ajit Agarwal - -ChangeLog: -2015-01-13 Nagaraju Mekala - Ajit Agarwal - - *microblaze.md (cbranchsi4_reg): New - *microblaze.c (microblaze_expand_conditional_branch_reg): New - -Conflicts: - - gcc/config/microblaze/microblaze-protos.h ---- - gcc/config/microblaze/microblaze-protos.h | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++------- - gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------ - 7 files changed, 18 insertions(+), 18 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index d67355697b5..848cd509003 100644 ---- a/gcc/config/microblaze/microblaze-protos.h -+++ b/gcc/config/microblaze/microblaze-protos.h -@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *); - extern bool microblaze_expand_move (machine_mode, rtx *); - extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); - extern void microblaze_expand_divide (rtx *); --extern void microblaze_expand_conditional_branch (machine_mode, rtx *); -+extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_sf (rtx *); - extern int microblaze_can_use_return_insn (void); -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c -index 4041a241391..ccc6a461cd9 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c -@@ -6,5 +6,5 @@ void float_func () - { - /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if (f2 <= f3) -- print ("le"); -+ f2 = f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c -index 3902b839db9..1dd5fe6c539 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c -@@ -6,5 +6,5 @@ void float_func () - { - /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if (f2 < f3) -- print ("lt"); -+ f2 = f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c -index 8555974dda5..d6f80fb0ec3 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c -@@ -6,5 +6,5 @@ void float_func () - { - /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if (f2 == f3) -- print ("eq"); -+ f1 = f2 + f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c -index 79cc5f9dd8e..d1177249552 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c -@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3) - /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if(f1==f2 && f1<=f3) -- print ("f1 eq f2 && f1 le f3"); -+ f2 = f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c -index ebfb170ecee..75822977ef8 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c -@@ -5,17 +5,17 @@ volatile float f1, f2, f3; - void float_func () - { - /* { dg-final { scan-assembler-not "fcmp" } } */ -- if (f2 <= f3) -- print ("le"); -+ if (f2 <= f3) -+ f1 = f3; - else if (f2 == f3) -- print ("eq"); -+ f1 = f3; - else if (f2 < f3) -- print ("lt"); -+ f1 = f3; - else if (f2 > f3) -- print ("gt"); -+ f1 = f3; - else if (f2 >= f3) -- print ("ge"); -+ f1 = f3; - else if (f2 != f3) -- print ("ne"); -+ f1 = f3; - - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c -index 1d6ba807b12..532c035adfd 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c -@@ -74,16 +74,16 @@ void float_cmp_func () - { - /* { dg-final { scan-assembler-not "fcmp" } } */ - if (f2 <= f3) -- print ("le"); -+ f1 = f3; - else if (f2 == f3) -- print ("eq"); -+ f1 = f3; - else if (f2 < f3) -- print ("lt"); -+ f1 = f3; - else if (f2 > f3) -- print ("gt"); -+ f1 = f3; - else if (f2 >= f3) -- print ("ge"); -+ f1 = f3; - else if (f2 != f3) -- print ("ne"); -+ f1 = f3; - - } --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch deleted file mode 100644 index e3a98a08..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 1593e5a9839b7cade95e9f55ba3cff66d64d0e84 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 17:11:04 +0530 -Subject: [PATCH 17/53] [Patch,microblaze]: Inline Expansion of fsqrt builtin. - The changes are made in the patch for the inline expansion of the fsqrt - builtin with fqrt instruction. The sqrt math function takes double as - argument and return double as argument. The pattern is selected while - expanding the unary op through expand_unop which passes DFmode and the DFmode - pattern was not there returning zero. Thus the sqrt math function is not - inlined and expanded. The pattern with DFmode argument is added. Also the - source and destination argument is not same the DF through two different - consecutive registers with lower 32 bit is the argument passed to sqrt and - the higher 32 bit is zero. If the source and destinations are different the - DFmode 64 bits registers is not set properly giving the problem in runtime. - Such changes are taken care in the implementation of the pattern for DFmode - for inline expansion of the sqrt. - -ChangeLog: -2015-06-16 Ajit Agarwal - Nagaraju Mekala - - * config/microblaze/microblaze.md (sqrtdf2): New - pattern. - -Signed-off-by:Ajit Agarwal ajitkum@xilinx.com - Nagaraju Mekala nmekala@xilinx.com ---- - gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 52308cce0cb..0e5ef4d7649 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -451,6 +451,20 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "sqrtdf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] -+ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" -+ { -+ if (REGNO (operands[0]) == REGNO (operands[1])) -+ return "fsqrt\t%0,%1"; -+ else -+ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; -+ } -+ [(set_attr "type" "fsqrt") -+ (set_attr "mode" "SF") -+ (set_attr "length" "4")]) -+ - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch deleted file mode 100644 index 831b8f22..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 9002b7d4c295bef95a3fc28c05f86dde5087dde1 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 18:07:24 +0530 -Subject: [PATCH 18/53] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' - insn definitions Change adddi3 to handle DI immediates as the second operand, - this requires modification to the output template however reduces the need to - specify seperate templates for 16-bit positive/negative immediate operands. - The use of 32-bit immediates for the addi and addic instructions is handled - by the assembler, which will emit the imm instructions when required. This - conveniently handles the optimizable cases where the immediate constant value - does not need the higher half words of the operands upper/lower words. - -Change the constraints of the subdi3 instruction definition such that it -does not match the second operand as an immediate value. This is because -there is no definition to handle this case nor is it possible to -implement purely with instructions as microblaze does not provide an -instruction to perform a forward arithmetic subtraction (it only -provides reverse 'rD = IMM - rA'). - -Signed-off-by: Nathan Rossi ---- - gcc/config/microblaze/microblaze.md | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 0e5ef4d7649..effb9774c32 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -502,17 +502,16 @@ - ;; Adding 2 DI operands in register or reg/imm - - (define_insn "adddi3" -- [(set (match_operand:DI 0 "register_operand" "=d,d,d") -- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d") -- (match_operand:DI 2 "arith_operand32" "d,P,N")))] -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") -+ (match_operand:DI 2 "arith_operand" "d,i")))] - "" - "@ - add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 -- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0 -- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1" -+ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" - [(set_attr "type" "darith") - (set_attr "mode" "DI") -- (set_attr "length" "8,8,12")]) -+ (set_attr "length" "8,8")]) - - ;;---------------------------------------------------------------- - ;; Subtraction -@@ -549,7 +548,7 @@ - (define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "d") -- (match_operand:DI 2 "arith_operand32" "d")))] -+ (match_operand:DI 2 "register_operand" "d")))] - "" - "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" - [(set_attr "type" "darith") --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch deleted file mode 100644 index ab3fa535..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch +++ /dev/null @@ -1,75 +0,0 @@ -From ef94a8b2110f5a3becefb00c1f7c0c3adac6fcac Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 18:18:41 +0530 -Subject: [PATCH 19/53] [Patch, microblaze]: Update ashlsi3 & movsf patterns - This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand - of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal - patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our - instruction doesn't support so using gen_int_mode function - -Signed-off-by :Nagaraju Mekala - :Ajit Agarwal - -ChangeLog: -2016-01-07 Nagaraju Mekala - Ajit Agarwal - - *microblaze.md (ashlsi3_with_mul_nodelay, - ashlsi3_with_mul_delay, - movsf_internal): - Updated the patterns to use gen_int_mode function - *microblaze.cc (print_operand): - updated the 'F' case to use "unsinged int" instead - of HOST_WIDE_INT_PRINT_HEX - -Conflicts: - gcc/config/microblaze/microblaze.c ---- - gcc/config/microblaze/microblaze.cc | 2 +- - gcc/config/microblaze/microblaze.md | 10 ++++++++-- - 2 files changed, 9 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 4b0621db168..c23061c4e4a 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2469,7 +2469,7 @@ print_operand (FILE * file, rtx op, int letter) - unsigned long value_long; - REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), - value_long); -- fprintf (file, "0x%lx", value_long); -+ fprintf (file, "0x%08x", (unsigned int) value_long); - } - else - { -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index effb9774c32..a4d7ea29219 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1368,7 +1368,10 @@ - (match_operand:SI 2 "immediate_operand" "I")))] - "!TARGET_SOFT_MUL - && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)" -- "muli\t%0,%1,%m2" -+ { -+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); -+ return "muli\t%0,%1,%2"; -+ } - ;; This MUL will not generate an imm. Can go into a delay slot. - [(set_attr "type" "arith") - (set_attr "mode" "SI") -@@ -1380,7 +1383,10 @@ - (ashift:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "immediate_operand" "I")))] - "!TARGET_SOFT_MUL" -- "muli\t%0,%1,%m2" -+ { -+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); -+ return "muli\t%0,%1,%2"; -+ } - ;; This MUL will generate an IMM. Cannot go into a delay slot - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "SI") --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch deleted file mode 100644 index 67eb0893..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch +++ /dev/null @@ -1,177 +0,0 @@ -From 65574bdca9006fda7654e33a0081eeecfcd9976b Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 12 Sep 2022 21:05:51 +0530 -Subject: [PATCH 20/53] [Patch, microblaze]: 8-stage pipeline for microblaze - This patch adds the support for the 8-stage pipeline. The new 8-stage - pipeline reduces the latencies of float & integer division drastically - -Signed-off-by :Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.cc | 11 ++++ - gcc/config/microblaze/microblaze.h | 3 +- - gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++- - gcc/config/microblaze/microblaze.opt | 4 ++ - 4 files changed, 94 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index c23061c4e4a..bd394c411b8 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -1841,6 +1841,17 @@ microblaze_option_override (void) - "%<-mcpu=v8.30.a%>"); - TARGET_REORDER = 0; - } -+ ver = microblaze_version_to_int("v10.0"); -+ if (ver < 0) -+ { -+ if (TARGET_AREA_OPTIMIZED_2) -+ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater"); -+ } -+ else -+ { -+ if (TARGET_AREA_OPTIMIZED_2) -+ microblaze_pipe = MICROBLAZE_PIPE_8; -+ } - - if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) - error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>"); -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index cd544f2030e..640ae6ea9a3 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -27,7 +27,8 @@ - enum pipeline_type - { - MICROBLAZE_PIPE_3 = 0, -- MICROBLAZE_PIPE_5 = 1 -+ MICROBLAZE_PIPE_5 = 1, -+ MICROBLAZE_PIPE_8 = 2 - }; - - #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index a4d7ea29219..9e9dfb1ccb0 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -35,6 +35,7 @@ - (R_GOT 20) ;; GOT ptr reg - (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline - (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline -+ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline - (UNSPEC_SET_GOT 101) ;; - (UNSPEC_GOTOFF 102) ;; GOT offset - (UNSPEC_PLT 103) ;; jump table -@@ -82,7 +83,7 @@ - ;; bshift Shift operations - - (define_attr "type" -- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap" -+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap" - (const_string "unknown")) - - ;; Main data type used by the insn -@@ -224,6 +225,80 @@ - ;;----------------------------------------------------------------- - - -+ -+;;---------------------------------------------------------------- -+;; Microblaze 8-stage pipeline description (v10.0 and later) -+;;---------------------------------------------------------------- -+ -+(define_automaton "mbpipe_8") -+(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8") -+ -+(define_insn_reservation "mb8-integer" 1 -+ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu,mb8_wb") -+ -+(define_insn_reservation "mb8-special-move" 2 -+ (and (eq_attr "type" "move") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu*2,mb8_wb") -+ -+(define_insn_reservation "mb8-mem-load" 3 -+ (and (eq_attr "type" "load,no_delay_load") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu,mb8_wb") -+ -+(define_insn_reservation "mb8-mem-store" 1 -+ (and (eq_attr "type" "store,no_delay_store") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu,mb8_wb") -+ -+(define_insn_reservation "mb8-mul" 3 -+ (and (eq_attr "type" "imul,no_delay_imul") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb") -+ -+(define_insn_reservation "mb8-div" 30 -+ (and (eq_attr "type" "idiv") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb") -+ -+(define_insn_reservation "mb8-bs" 2 -+ (and (eq_attr "type" "bshift") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-add-sub-mul" 1 -+ (and (eq_attr "type" "fadd,frsub,fmul") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-fcmp" 3 -+ (and (eq_attr "type" "fcmp") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-div" 24 -+ (and (eq_attr "type" "fdiv") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-sqrt" 23 -+ (and (eq_attr "type" "fsqrt") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-fcvt" 1 -+ (and (eq_attr "type" "fcvt") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-fint" 2 -+ (and (eq_attr "type" "fint") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_wb") -+ -+ - ;;---------------------------------------------------------------- - ;; Microblaze 5-stage pipeline description (v5.00.a and later) - ;;---------------------------------------------------------------- -@@ -470,7 +545,7 @@ - (fix:SI (match_operand:SF 1 "register_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "fint\t%0,%1" -- [(set_attr "type" "fcvt") -+ [(set_attr "type" "fint") - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt -index 9f47e67cf2a..cc009363f87 100644 ---- a/gcc/config/microblaze/microblaze.opt -+++ b/gcc/config/microblaze/microblaze.opt -@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE). - - mxl-mode-xilkernel - Target -+ -+mxl-frequency -+Target Mask(AREA_OPTIMIZED_2) -+Use 8 stage pipeline (frequency optimization) --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch deleted file mode 100644 index 96fe4f73..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 1d56bfb436b008422b4a7d4d4e3180667130c840 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 11:49:11 +0530 -Subject: [PATCH 21/53] [PATCH 21/53] [Patch, microblaze]: Correct the const - high double immediate value with this patch the loading of the DI mode - immediate values will be using REAL_VALUE_FROM_CONST_DOUBLE and - REAL_VALUE_TO_TARGET_DOUBLE functions, as CONST_DOUBLE_HIGH was returning - the sign extension value even of the unsigned long long constants also - -Signed-off-by :Nagaraju Mekala - Ajit Agarwal ---- - gcc/config/microblaze/microblaze.cc | 6 ++++-- - gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++ - 2 files changed, 13 insertions(+), 2 deletions(-) - create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index bd394c411b8..7c648cda1b2 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2453,14 +2453,16 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -+ long l[2]; - if (code == CONST_DOUBLE) - { - if (GET_MODE (op) == DFmode) - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); - else - { -- val[0] = CONST_DOUBLE_HIGH (op); -- val[1] = CONST_DOUBLE_LOW (op); -+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); -+ val[1] = l[WORDS_BIG_ENDIAN == 0]; -+ val[0] = l[WORDS_BIG_ENDIAN != 0]; - } - } - else if (code == CONST_INT) -diff --git a/gcc/testsuite/gcc.target/microblaze/others/long.c b/gcc/testsuite/gcc.target/microblaze/others/long.c -new file mode 100644 -index 00000000000..b6b55d5ad65 ---- /dev/null -+++ b/gcc/testsuite/gcc.target/microblaze/others/long.c -@@ -0,0 +1,9 @@ -+#define BASEADDR 0xF0000000ULL -+int main () -+{ -+ unsigned long long start; -+ start = (unsigned long long) BASEADDR; -+ return 0; -+} -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch deleted file mode 100644 index 332db5d3..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch +++ /dev/null @@ -1,31 +0,0 @@ -From cd60ea1bd88ac47856ac66266a0771478ac73bad Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 11:58:14 +0530 -Subject: [PATCH 22/53] [Fix, microblaze]: Fix internal compiler error with - msmall-divides This patch will fix the internal error - microblaze_expand_divide function which come of rtx PLUS where the - mem_rtx is of type SI and the operand is of type QImode. This patch - modifies the mem_rtx as QImode and Plus as QImode to fix the error. - - Signed-off-by :Nagaraju Mekala - Ajit Agarwal ---- - gcc/config/microblaze/microblaze.cc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 7c648cda1b2..907c0afa9b8 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -3768,7 +3768,7 @@ microblaze_expand_divide (rtx operands[]) - emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); - emit_insn (gen_addsi3 (regt1, regt1, operands[2])); - mem_rtx = gen_rtx_MEM (QImode, -- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); -+ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - - insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch deleted file mode 100644 index 47e13fa6..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b98cddb206ce84994425ede4b116365977768e37 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 12:03:08 +0530 -Subject: [PATCH 23/53] [patch,microblaze]: Fix the calculation of high word in - a long long 64-bit - - This patch will change the calculation of high word in a long long 64-bit. - Earlier to this patch the high word of long long word (0xF0000000ULL) is - coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word - should be 0x00000000 and the low word should be 0xF0000000. This patch - removes the condition of checking high word = 0 & low word < 0. - This check is not required for the correctness of calculating 32-bit high - and low words in a 64-bit long long. - - Signed-off-by :Nagaraju Mekala - Ajit Agarwal ---- - gcc/config/microblaze/microblaze.cc | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 907c0afa9b8..f75eaff4b49 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2469,9 +2469,6 @@ print_operand (FILE * file, rtx op, int letter) - { - val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; - val[1] = INTVAL (op) & 0x00000000ffffffffLL; -- if (val[0] == 0 && val[1] < 0) -- val[0] = -1; -- - } - fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); - } --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch deleted file mode 100644 index 8ed5ae83..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch +++ /dev/null @@ -1,373 +0,0 @@ -From 89269c9b8d2047ebbc13e98c45e94746edc63de6 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 12:23:54 +0530 -Subject: [PATCH 24/53] [Patch,MicroBlaze] : this patch has 1.Fixed the bug in - version calculation. 2.Add new bitfield instructions. - -Signed-off-by :Mahesh Bodapati ---- - gcc/config/microblaze/microblaze.cc | 154 ++++++++++++++-------------- - gcc/config/microblaze/microblaze.h | 2 + - gcc/config/microblaze/microblaze.md | 69 +++++++++++++ - 3 files changed, 147 insertions(+), 78 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index f75eaff4b49..3abfc834ff2 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -165,6 +165,9 @@ int microblaze_no_unsafe_delay; - /* Set to one if the targeted core has the CLZ insn. */ - int microblaze_has_clz = 0; - -+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */ -+int microblaze_has_bitfield = 0; -+ - /* Which CPU pipeline do we use. We haven't really standardized on a CPU - version having only a particular type of pipeline. There can still be - options on the CPU to scale pipeline features up or down. :( -@@ -240,6 +243,63 @@ section *sdata2_section; - #define TARGET_HAVE_TLS true - #endif - -+/* Convert a version number of the form "vX.YY.Z" to an integer encoding -+ for easier range comparison. */ -+static int -+microblaze_version_to_int (const char *version) -+{ -+ const char *p, *v; -+ const char *tmpl = "vXX.YY.Z"; -+ int iver1 =0, iver2 =0, iver3 =0; -+ -+ p = version; -+ v = tmpl; -+ -+ while (*p) -+ { -+ if (*v == 'X') -+ { /* Looking for major */ -+ if (*p == '.') -+ { -+ *v++; -+ } -+ else -+ { -+ if (!(*p >= '0' && *p <= '9')) -+ return -1; -+ iver1 += (int) (*p - '0'); -+ iver1 *= 1000; -+ } -+ } -+ else if (*v == 'Y') -+ { /* Looking for minor */ -+ if (!(*p >= '0' && *p <= '9')) -+ return -1; -+ iver2 += (int) (*p - '0'); -+ iver2 *= 10; -+ } -+ else if (*v == 'Z') -+ { /* Looking for compat */ -+ if (!(*p >= 'a' && *p <= 'z')) -+ return -1; -+ iver3 = ((int) (*p)) - 96; -+ } -+ else -+ { -+ if (*p != *v) -+ return -1; -+ } -+ -+ v++; -+ p++; -+ } -+ -+ if (*p) -+ return -1; -+ -+ return iver1 + iver2 + iver3; -+} -+ - /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ - static bool - microblaze_const_double_ok (rtx op, machine_mode mode) -@@ -1339,8 +1399,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, - { - if (TARGET_BARREL_SHIFT) - { -- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") -- >= 0) -+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) - *total = COSTS_N_INSNS (1); - else - *total = COSTS_N_INSNS (2); -@@ -1401,8 +1460,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, - } - else if (!TARGET_SOFT_MUL) - { -- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") -- >= 0) -+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) - *total = COSTS_N_INSNS (1); - else - *total = COSTS_N_INSNS (3); -@@ -1675,72 +1733,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, - return 0; - } - --/* Convert a version number of the form "vX.YY.Z" to an integer encoding -- for easier range comparison. */ --static int --microblaze_version_to_int (const char *version) --{ -- const char *p, *v; -- const char *tmpl = "vXX.YY.Z"; -- int iver = 0; -- -- p = version; -- v = tmpl; -- -- while (*p) -- { -- if (*v == 'X') -- { /* Looking for major */ -- if (*p == '.') -- { -- v++; -- } -- else -- { -- if (!(*p >= '0' && *p <= '9')) -- return -1; -- iver += (int) (*p - '0'); -- iver *= 10; -- } -- } -- else if (*v == 'Y') -- { /* Looking for minor */ -- if (!(*p >= '0' && *p <= '9')) -- return -1; -- iver += (int) (*p - '0'); -- iver *= 10; -- } -- else if (*v == 'Z') -- { /* Looking for compat */ -- if (!(*p >= 'a' && *p <= 'z')) -- return -1; -- iver *= 10; -- iver += (int) (*p - 'a'); -- } -- else -- { -- if (*p != *v) -- return -1; -- } -- -- v++; -- p++; -- } -- -- if (*p) -- return -1; -- -- return iver; --} -- -- - static void - microblaze_option_override (void) - { - int i, start; - int regno; - machine_mode mode; -- int ver; -+ int ver,ver_int; - - microblaze_section_threshold = (OPTION_SET_P (g_switch_value) - ? g_switch_value -@@ -1761,13 +1760,13 @@ microblaze_option_override (void) - /* Check the MicroBlaze CPU version for any special action to be done. */ - if (microblaze_select_cpu == NULL) - microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; -- ver = microblaze_version_to_int (microblaze_select_cpu); -- if (ver == -1) -+ ver_int = microblaze_version_to_int (microblaze_select_cpu); -+ if (ver_int == -1) - { - error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu); - } - -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a"); -+ ver = ver_int - microblaze_version_to_int("v3.00.a"); - if (ver < 0) - { - /* No hardware exceptions in earlier versions. So no worries. */ -@@ -1778,8 +1777,7 @@ microblaze_option_override (void) - microblaze_pipe = MICROBLAZE_PIPE_3; - } - else if (ver == 0 -- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b") -- == 0)) -+ || (ver_int == microblaze_version_to_int("v4.00.b"))) - { - #if 0 - microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); -@@ -1796,11 +1794,9 @@ microblaze_option_override (void) - #endif - microblaze_no_unsafe_delay = 0; - microblaze_pipe = MICROBLAZE_PIPE_5; -- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0 -- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, -- "v5.00.b") == 0 -- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, -- "v5.00.c") == 0) -+ if ((ver_int == microblaze_version_to_int("v5.00.a")) -+ || (ver_int == microblaze_version_to_int("v5.00.b")) -+ || (ver_int == microblaze_version_to_int("v5.00.c"))) - { - /* Pattern compares are to be turned on by default only when - compiling for MB v5.00.'z'. */ -@@ -1808,7 +1804,7 @@ microblaze_option_override (void) - } - } - -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a"); -+ ver = ver_int - microblaze_version_to_int("v6.00.a"); - if (ver < 0) - { - if (TARGET_MULTIPLY_HIGH) -@@ -1817,7 +1813,7 @@ microblaze_option_override (void) - "%<-mcpu=v6.00.a%> or greater"); - } - -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a"); -+ ver = ver_int - microblaze_version_to_int("v8.10.a"); - microblaze_has_clz = 1; - if (ver < 0) - { -@@ -1826,7 +1822,7 @@ microblaze_option_override (void) - } - - /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a"); -+ ver = ver_int - microblaze_version_to_int("v8.30.a"); - if (ver < 0) - { - if (TARGET_REORDER == 1) -@@ -1841,7 +1837,7 @@ microblaze_option_override (void) - "%<-mcpu=v8.30.a%>"); - TARGET_REORDER = 0; - } -- ver = microblaze_version_to_int("v10.0"); -+ ver = ver_int - microblaze_version_to_int("v10.0"); - if (ver < 0) - { - if (TARGET_AREA_OPTIMIZED_2) -@@ -1851,6 +1847,8 @@ microblaze_option_override (void) - { - if (TARGET_AREA_OPTIMIZED_2) - microblaze_pipe = MICROBLAZE_PIPE_8; -+ if (TARGET_BARREL_SHIFT) -+ microblaze_has_bitfield = 1; - } - - if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 640ae6ea9a3..67015058198 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; - - extern int microblaze_no_unsafe_delay; - extern int microblaze_has_clz; -+extern int microblaze_has_bitfield; - extern enum pipeline_type microblaze_pipe; - - #define OBJECT_FORMAT_ELF -@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe; - /* Do we have CLZ? */ - #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz) - -+#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield) - /* The default is to support PIC. */ - #define TARGET_SUPPORTS_PIC 1 - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 9e9dfb1ccb0..dede4d068d3 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2491,4 +2491,73 @@ - DONE; - }") - -+(define_expand "extvsi" -+ [(set (match_operand:SI 0 "register_operand" "r") -+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "I") -+ (match_operand:SI 3 "immediate_operand" "I")))] -+"TARGET_HAS_BITFIELD" -+" -+{ -+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); -+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); -+ -+ if ((len == 0) || (pos + len > 32) ) -+ FAIL; -+ -+ ;;if (!register_operand (operands[1], VOIDmode)) -+ ;; FAIL; -+ if (operands[0] == operands[1]) -+ FAIL; -+ if (GET_CODE (operands[1]) == ASHIFT) -+ FAIL; -+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); -+ emit_insn (gen_extv_32 (operands[0], operands[1], -+ operands[2], operands[3])); -+ DONE; -+}") -+ -+(define_insn "extv_32" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "I") -+ (match_operand:SI 3 "immediate_operand" "I")))] -+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0) -+ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" -+ "bsefi %0,%1,%2,%3" -+ [(set_attr "type" "bshift") -+ (set_attr "length" "4")]) -+ -+(define_expand "insvsi" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (match_operand:SI 1 "immediate_operand" "I") -+ (match_operand:SI 2 "immediate_operand" "I")) -+ (match_operand:SI 3 "register_operand" "r"))] -+ "TARGET_HAS_BITFIELD" -+ " -+{ -+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); -+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); -+ -+ if (len <= 0 || pos + len > 32) -+ FAIL; -+ -+ ;;if (!register_operand (operands[0], VOIDmode)) -+ ;; FAIL; -+ emit_insn (gen_insv_32 (operands[0], operands[1], -+ operands[2], operands[3])); -+ DONE; -+}") -+ -+(define_insn "insv_32" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (match_operand:SI 1 "immediate_operand" "I") -+ (match_operand:SI 2 "immediate_operand" "I")) -+ (match_operand:SI 3 "register_operand" "r"))] -+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0 -+ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" -+ "bsifi %0, %3, %1, %2" -+ [(set_attr "type" "bshift") -+ (set_attr "length" "4")]) -+ - (include "sync.md") --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch deleted file mode 100644 index 109e0686..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 101f47dedd82fc09bcefd5db986e6d6b0a1761ad Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Thu, 23 Feb 2017 17:09:04 +0530 -Subject: [PATCH 25/53] Fixing the issue with the builtin_alloc. register r18 - was not properly handling the stack pattern which was resolved by using free - available register - -signed-off-by:nagaraju mekala ---- - gcc/config/microblaze/microblaze.md | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index dede4d068d3..c6d8a87e9d1 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2075,10 +2075,10 @@ - "" - { - rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); -- rtx rtmp = gen_rtx_REG (SImode, R_TMP); -+ rtx reg = gen_reg_rtx (Pmode); - rtx neg_op0; - -- emit_move_insn (rtmp, retaddr); -+ emit_move_insn (reg, retaddr); - if (GET_CODE (operands[1]) != CONST_INT) - { - neg_op0 = gen_reg_rtx (Pmode); -@@ -2087,9 +2087,9 @@ - neg_op0 = GEN_INT (- INTVAL (operands[1])); - - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); -- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp); -+ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg); - emit_move_insn (operands[0], virtual_stack_dynamic_rtx); -- emit_insn (gen_rtx_CLOBBER (SImode, rtmp)); -+ emit_insn (gen_rtx_CLOBBER (SImode, reg)); - DONE; - } - ) --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch deleted file mode 100644 index 4f101b96..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch +++ /dev/null @@ -1,38 +0,0 @@ -From b3e51ca34dc4048445b178253051ad4bbdfc5ec4 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 4 Jun 2018 10:10:18 +0530 -Subject: [PATCH 26/53] [Patch,Microblaze] : Removed fsqrt generation for - double values. - ---- - gcc/config/microblaze/microblaze.md | 14 -------------- - 1 file changed, 14 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index c6d8a87e9d1..f23a85c7ac7 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -526,20 +526,6 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - --(define_insn "sqrtdf2" -- [(set (match_operand:DF 0 "register_operand" "=d") -- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] -- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" -- { -- if (REGNO (operands[0]) == REGNO (operands[1])) -- return "fsqrt\t%0,%1"; -- else -- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; -- } -- [(set_attr "type" "fsqrt") -- (set_attr "mode" "SF") -- (set_attr "length" "4")]) -- - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch deleted file mode 100644 index 2e7106d6..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch +++ /dev/null @@ -1,784 +0,0 @@ -From cf9ab9693d02212e1a49465e55d759a01acc507a Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 13:56:52 +0530 -Subject: [PATCH 27/53] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze - - Conflicts: - gcc/config/microblaze/microblaze.md ---- - gcc/config/microblaze/constraints.md | 6 + - gcc/config/microblaze/microblaze-protos.h | 1 + - gcc/config/microblaze/microblaze.cc | 109 +++++-- - gcc/config/microblaze/microblaze.h | 4 +- - gcc/config/microblaze/microblaze.md | 352 +++++++++++++++++++++- - gcc/config/microblaze/microblaze.opt | 7 +- - gcc/config/microblaze/t-microblaze | 7 +- - 7 files changed, 456 insertions(+), 30 deletions(-) - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index a8934d305ee..2133650147e 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -52,6 +52,12 @@ - (and (match_code "const_int") - (match_test "ival > 0 && ival < 0x10000"))) - -+(define_constraint "K" -+ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." -+ (and (match_code "const_int") -+ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) -+ -+ - ;; Define floating point constraints - - (define_constraint "G" -diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index 848cd509003..7f575c2adec 100644 ---- a/gcc/config/microblaze/microblaze-protos.h -+++ b/gcc/config/microblaze/microblaze-protos.h -@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *); - extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_sf (rtx *); -+extern void microblaze_expand_conditional_branch_df (rtx *); - extern int microblaze_can_use_return_insn (void); - extern void print_operand (FILE *, rtx, int); - extern void print_operand_address (FILE *, rtx); -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 3abfc834ff2..1ac889041b8 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -3433,11 +3433,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) - op0 = operands[0]; - op1 = operands[1]; - -- if (!register_operand (op0, SImode) -- && !register_operand (op1, SImode) -+ if (!register_operand (op0, mode) -+ && !register_operand (op1, mode) - && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0)) - { -- rtx temp = force_reg (SImode, op1); -+ rtx temp = force_reg (mode, op1); - emit_move_insn (op0, temp); - return true; - } -@@ -3502,12 +3502,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) - && (flag_pic == 2 || microblaze_tls_symbol_p (p0) - || !SMALL_INT (p1))))) - { -- rtx temp = force_reg (SImode, p0); -+ rtx temp = force_reg (mode, p0); - rtx temp2 = p1; - - if (flag_pic && reload_in_progress) - df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); -- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2)); -+ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2)); - return true; - } - } -@@ -3638,7 +3638,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - rtx cmp_op0 = operands[1]; - rtx cmp_op1 = operands[2]; - rtx label1 = operands[3]; -- rtx comp_reg = gen_reg_rtx (SImode); -+ rtx comp_reg = gen_reg_rtx (mode); - rtx condition; - - gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); -@@ -3647,23 +3647,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - if (cmp_op1 == const0_rtx) - { - comp_reg = cmp_op0; -- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); -+ - } - - else if (code == EQ || code == NE) - { - /* Use xor for equal/not-equal comparison. */ -- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); -- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ if (mode == SImode) -+ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); -+ else -+ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); -+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); - } - else - { - /* Generate compare and branch in single instruction. */ - cmp_op1 = force_reg (mode, cmp_op1); - condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); -- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); -+ if (mode == SImode) -+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); -+ else -+ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1)); - } - } - -@@ -3674,7 +3687,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - rtx cmp_op0 = operands[1]; - rtx cmp_op1 = operands[2]; - rtx label1 = operands[3]; -- rtx comp_reg = gen_reg_rtx (SImode); -+ rtx comp_reg = gen_reg_rtx (mode); - rtx condition; - - gcc_assert ((GET_CODE (cmp_op0) == REG) -@@ -3685,30 +3698,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - { - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), -- SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); - } - else if (code == EQ) - { -- emit_insn (gen_seq_internal_pat (comp_reg, -- cmp_op0, cmp_op1)); -- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ if (mode == SImode) -+ { -+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ else -+ { -+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); -+ - } - else if (code == NE) - { -- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, -- cmp_op1)); -- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ if (mode == SImode) -+ { -+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ else -+ { -+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ condition = gen_rtx_NE (mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); - } - else - { - /* Generate compare and branch in single instruction. */ - cmp_op1 = force_reg (mode, cmp_op1); - condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); -- emit_jump_insn (gen_branch_compare (condition, cmp_op0, -- cmp_op1, label1)); -+ if (mode == SImode) -+ emit_jump_insn (gen_branch_compare (condition, cmp_op0, -+ cmp_op1, label1)); -+ else -+ { -+ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0, -+ cmp_op1, label1)); -+ } -+ - } - } - -@@ -3725,6 +3771,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) - emit_jump_insn (gen_condjump (condition, operands[3])); - } - -+void -+microblaze_expand_conditional_branch_df (rtx operands[]) -+{ -+ rtx condition; -+ rtx cmp_op0 = XEXP (operands[0], 0); -+ rtx cmp_op1 = XEXP (operands[0], 1); -+ rtx comp_reg = gen_reg_rtx (DImode); -+ -+ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); -+ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); -+ emit_jump_insn (gen_long_condjump (condition, operands[3])); -+} -+ - /* Implement TARGET_FRAME_POINTER_REQUIRED. */ - - static bool -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 67015058198..885abc6e5a1 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; - #define ASM_SPEC "\ - %(target_asm_spec) \ - %{mbig-endian:-EB} \ -+%{m64:-m64} \ - %{mlittle-endian:-EL}" - - /* Extra switches sometimes passed to the linker. */ -@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe; - #define LINK_SPEC "%{shared:-shared} -N -relax \ - %{mbig-endian:-EB --oformat=elf32-microblaze} \ - %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ -+ %{m64:-EL --oformat=elf64-microblazeel} \ - %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ - %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ - %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ -@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe; - #define MIN_UNITS_PER_WORD 4 - #define INT_TYPE_SIZE 32 - #define SHORT_TYPE_SIZE 16 --#define LONG_TYPE_SIZE 32 -+#define LONG_TYPE_SIZE 64 - #define LONG_LONG_TYPE_SIZE 64 - #define FLOAT_TYPE_SIZE 32 - #define DOUBLE_TYPE_SIZE 64 -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index f23a85c7ac7..40711fe224b 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -497,7 +497,6 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -- - (define_insn "divsf3" - [(set (match_operand:SF 0 "register_operand" "=d") - (div:SF (match_operand:SF 1 "register_operand" "d") -@@ -508,6 +507,7 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+ - (define_insn "sqrtsf2" - [(set (match_operand:SF 0 "register_operand" "=d") - (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] -@@ -562,6 +562,18 @@ - - ;; Adding 2 DI operands in register or reg/imm - -+(define_insn "adddi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") -+ (match_operand:DI 2 "arith_plus_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ addlk\t%0,%z1,%2 -+ addlik\t%0,%z1,%2" -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "adddi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (match_operand:DI 1 "register_operand" "%d,d") -@@ -606,6 +618,18 @@ - ;; Double Precision Subtraction - ;;---------------------------------------------------------------- - -+(define_insn "subdi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (minus:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "register_operand" "d,n")))] -+ "TARGET_MB_64" -+ "@ -+ rsubl\t%0,%2,%1 -+ addlik\t%0,%z1,-%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "d") -@@ -795,6 +819,15 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "negdi2_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (neg:DI (match_operand:DI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "rsubl\t%0,%1,r0" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "negdi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d")))] -@@ -814,6 +847,15 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "one_cmpldi2_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (not:DI (match_operand:DI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "xorli\t%0,%1,-1" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "*one_cmpldi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (not:DI (match_operand:DI 1 "register_operand" "d")))] -@@ -840,6 +882,20 @@ - ;; Logical - ;;---------------------------------------------------------------- - -+(define_insn "anddi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (and:DI (match_operand:DI 1 "arith_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ andl\t%0,%1,%2 -+ andli\t%0,%1,%2 #andl1" -+ ;; andli\t%0,%1,%2 #andl3 -+ ;; andli\t%0,%1,%2 #andl2 -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "andsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") - (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") -@@ -855,6 +911,18 @@ - (set_attr "length" "4,8,8,8")]) - - -+(define_insn "iordi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (ior:DI (match_operand:DI 1 "arith_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ orl\t%0,%1,%2 -+ orli\t%0,%1,%2 #andl1" -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "iorsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") - (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") -@@ -869,6 +937,19 @@ - (set_attr "mode" "SI,SI,SI,SI") - (set_attr "length" "4,8,8,8")]) - -+(define_insn "xordi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") -+ (match_operand:DI 2 "arith_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ xorl\t%0,%1,%2 -+ xorli\t%0,%1,%2 #andl1" -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ -+ - (define_insn "xorsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d") - (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") -@@ -937,6 +1018,26 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+;;(define_expand "extendqidi2" -+;; [(set (match_operand:DI 0 "register_operand" "=d") -+;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] -+;; "TARGET_MB_64" -+;; { -+;; if (GET_CODE (operands[1]) != REG) -+;; FAIL; -+;; } -+;;) -+ -+ -+;;(define_insn "extendqidi2" -+;; [(set (match_operand:DI 0 "register_operand" "=d") -+;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] -+;; "TARGET_MB_64" -+;; "sextl8\t%0,%1" -+;; [(set_attr "type" "arith") -+;; (set_attr "mode" "DI") -+;; (set_attr "length" "4")]) -+ - (define_insn "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] -@@ -946,6 +1047,16 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "sextl16\t%0,%1" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ -+ - ;; Those for integer source operand are ordered - ;; widest source type first. - -@@ -1009,6 +1120,32 @@ - ) - - -+(define_insn "*movdi_internal_64" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") -+ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] -+ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1"; -+ case 1: -+ return "addlik\t%0,r0,%1"; -+ case 2: -+ return "addlk\t%0,r0,r0"; -+ case 3: -+ case 4: -+ return "lli\t%0,%1"; -+ case 5: -+ case 6: -+ return "sli\t%1,%0"; -+ } -+ return "unreachable"; -+ } -+ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8,8,8,8,12,8,12")]) -+ - - (define_insn "*movdi_internal" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") -@@ -1421,6 +1558,36 @@ - (set_attr "length" "4,4")] - ) - -+;; Barrel shift left -+(define_expand "ashldi3" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "")))] -+"TARGET_MB_64" -+{ -+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+ { -+ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else -+ FAIL; -+} -+) -+ -+(define_insn "ashldi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "I,d")))] -+ "TARGET_MB_64" -+ "@ -+ bsllli\t%0,%1,%2 -+ bslll\t%0,%1,%2" -+ [(set_attr "type" "bshift,bshift") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")] -+) - ;; The following patterns apply when there is no barrel shifter present - - (define_insn "*ashlsi3_with_mul_delay" -@@ -1546,6 +1713,36 @@ - ;;---------------------------------------------------------------- - ;; 32-bit right shifts - ;;---------------------------------------------------------------- -+;; Barrel shift left -+(define_expand "ashrdi3" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "")))] -+"TARGET_MB_64" -+{ -+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+ { -+ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else -+ FAIL; -+} -+) -+ -+(define_insn "ashrdi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "I,d")))] -+ "TARGET_MB_64" -+ "@ -+ bslrai\t%0,%1,%2 -+ bslra\t%0,%1,%2" -+ [(set_attr "type" "bshift,bshift") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")] -+ ) - (define_expand "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -@@ -1655,6 +1852,36 @@ - ;;---------------------------------------------------------------- - ;; 32-bit right shifts (logical) - ;;---------------------------------------------------------------- -+;; Barrel shift left -+(define_expand "lshrdi3" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "")))] -+"TARGET_MB_64" -+{ -+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+ { -+ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else -+ FAIL; -+} -+) -+ -+(define_insn "lshrdi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "I,d")))] -+ "TARGET_MB_64" -+ "@ -+ bslrli\t%0,%1,%2 -+ bslrl\t%0,%1,%2" -+ [(set_attr "type" "bshift,bshift") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")] -+ ) - - (define_expand "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") -@@ -1800,6 +2027,8 @@ - (set_attr "length" "4")] - ) - -+ -+ - ;;---------------------------------------------------------------- - ;; Setting a register from an floating point comparison. - ;;---------------------------------------------------------------- -@@ -1815,6 +2044,18 @@ - (set_attr "length" "4")] - ) - -+(define_insn "cstoredf4" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (match_operator:DI 1 "ordered_comparison_operator" -+ [(match_operand:DF 2 "register_operand" "r") -+ (match_operand:DF 3 "register_operand" "r")]))] -+ "TARGET_MB_64" -+ "dcmp.%C1\t%0,%3,%2" -+ [(set_attr "type" "fcmp") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")] -+) -+ - ;;---------------------------------------------------------------- - ;; Conditional branches - ;;---------------------------------------------------------------- -@@ -1927,6 +2168,115 @@ - (set_attr "length" "12")] - ) - -+ -+(define_expand "cbranchdi4" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand") -+ (match_operand:DI 2 "arith_operand" "I,i")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "TARGET_MB_64" -+{ -+ microblaze_expand_conditional_branch (DImode, operands); -+ DONE; -+}) -+ -+(define_expand "cbranchdi4_reg" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand") -+ (match_operand:DI 2 "register_operand")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "TARGET_MB_64" -+{ -+ microblaze_expand_conditional_branch_reg (DImode, operands); -+ DONE; -+}) -+ -+(define_expand "cbranchdf4" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand:DF 1 "register_operand") -+ (match_operand:DF 2 "register_operand")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "TARGET_MB_64" -+{ -+ microblaze_expand_conditional_branch_df (operands); -+ DONE; -+ -+}) -+ -+;; Used to implement comparison instructions -+(define_expand "long_condjump" -+ [(set (pc) -+ (if_then_else (match_operand 0) -+ (label_ref (match_operand 1)) -+ (pc)))]) -+ -+(define_insn "long_branch_zero" -+ [(set (pc) -+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand" "d") -+ (const_int 0)]) -+ (match_operand:DI 2 "pc_or_label_operand" "") -+ (match_operand:DI 3 "pc_or_label_operand" ""))) -+ ] -+ "TARGET_MB_64" -+ { -+ if (operands[3] == pc_rtx) -+ return "beal%C0i%?\t%z1,%2"; -+ else -+ return "beal%N0i%?\t%z1,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "long_branch_compare" -+ [(set (pc) -+ (if_then_else (match_operator:DI 0 "cmp_op" -+ [(match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d") -+ ]) -+ (label_ref (match_operand 3)) -+ (pc))) -+ (clobber(reg:DI R_TMP))] -+ "TARGET_MB_64" -+ { -+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ enum rtx_code code = GET_CODE (operands[0]); -+ -+ if (code == GT || code == LE) -+ { -+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GTU || code == LEU) -+ { -+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GE || code == LT) -+ { -+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); -+ } -+ else if (code == GEU || code == LTU) -+ { -+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); -+ } -+ -+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); -+ return "beal%C0i%?\tr18,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "12")] -+) -+ - ;;---------------------------------------------------------------- - ;; Unconditional branches - ;;---------------------------------------------------------------- -diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt -index cc009363f87..10910dbb83f 100644 ---- a/gcc/config/microblaze/microblaze.opt -+++ b/gcc/config/microblaze/microblaze.opt -@@ -136,4 +136,9 @@ Target - - mxl-frequency - Target Mask(AREA_OPTIMIZED_2) --Use 8 stage pipeline (frequency optimization) -+Use 8 stage pipeline (frequency optimization). -+ -+m64 -+Target Mask(MB_64) -+MicroBlaze 64-bit mode. -+ -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index 7e2fc5dcef8..4c25cfe15e7 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -1,8 +1,11 @@ --MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian --MULTILIB_DIRNAMES = bs m mh le -+MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 -+MULTILIB_DIRNAMES = bs m mh le m64 - MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 - MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian -+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 -+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 - - # Extra files - microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch deleted file mode 100644 index 1ffa79cb..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch +++ /dev/null @@ -1,2442 +0,0 @@ -From da40b160857d0b6a56b6f6c9c81d61dabb5255db Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 14:38:48 +0530 -Subject: [PATCH 28/53] Intial commit for 64bit-MB sources. Need to cleanup - the code later. - ---- - gcc/config/microblaze/constraints.md | 2 +- - gcc/config/microblaze/microblaze-c.cc | 6 + - gcc/config/microblaze/microblaze.cc | 216 ++++++--- - gcc/config/microblaze/microblaze.h | 63 ++- - gcc/config/microblaze/microblaze.md | 605 ++++++++++++++++++------ - gcc/config/microblaze/t-microblaze | 3 +- - libgcc/config/microblaze/crti.S | 4 +- - libgcc/config/microblaze/crtn.S | 4 +- - libgcc/config/microblaze/divdi3.S | 98 ++++ - libgcc/config/microblaze/divdi3_table.c | 62 +++ - libgcc/config/microblaze/moddi3.S | 97 ++++ - libgcc/config/microblaze/muldi3.S | 73 +++ - libgcc/config/microblaze/t-microblaze | 11 +- - libgcc/config/microblaze/udivdi3.S | 107 +++++ - libgcc/config/microblaze/umoddi3.S | 110 +++++ - 15 files changed, 1229 insertions(+), 232 deletions(-) - create mode 100644 libgcc/config/microblaze/divdi3.S - create mode 100644 libgcc/config/microblaze/divdi3_table.c - create mode 100644 libgcc/config/microblaze/moddi3.S - create mode 100644 libgcc/config/microblaze/muldi3.S - create mode 100644 libgcc/config/microblaze/udivdi3.S - create mode 100644 libgcc/config/microblaze/umoddi3.S - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index 2133650147e..0ced155340d 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -55,7 +55,7 @@ - (define_constraint "K" - "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." - (and (match_code "const_int") -- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) -+ (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) - - - ;; Define floating point constraints -diff --git a/gcc/config/microblaze/microblaze-c.cc b/gcc/config/microblaze/microblaze-c.cc -index caabe99b993..ef8d2430565 100644 ---- a/gcc/config/microblaze/microblaze-c.cc -+++ b/gcc/config/microblaze/microblaze-c.cc -@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) - builtin_define ("HAVE_HW_FPU_SQRT"); - builtin_define ("__HAVE_HW_FPU_SQRT__"); - } -+ if (TARGET_MB_64) -+ { -+ builtin_define ("__arch64__"); -+ builtin_define ("__microblaze64__"); -+ builtin_define ("__MICROBLAZE64__"); -+ } - } -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 1ac889041b8..9d3628c6816 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -384,10 +384,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) - { - return 1; - } -- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) -+ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) - { - return 1; -- } -+ }*/ - else - return 0; - -@@ -435,7 +435,7 @@ double_memory_operand (rtx op, machine_mode mode) - return 1; - - return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT -- ? E_SImode : E_SFmode), -+ ? Pmode : E_SFmode), - plus_constant (Pmode, addr, 4)); - } - -@@ -682,7 +682,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) - /* Load the addend. */ - addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), - UNSPEC_TLS); -- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); -+ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend)); - dest = gen_rtx_PLUS (Pmode, dest, addend); - break; - -@@ -700,7 +700,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) - - if (XINT (x, 1) == UNSPEC_GOTOFF) - { -- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM); -+ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); - info->type = ADDRESS_GOTOFF; - } - else if (XINT (x, 1) == UNSPEC_PLT) -@@ -1303,8 +1303,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) - emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); - - /* Emit the test & branch. */ -- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src), -+ -+ if (TARGET_MB_64) { -+ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src), -+ src_reg, final_src, label)); -+ } -+ else { -+ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src), - src_reg, final_src, label)); -+ -+ } - - /* Mop up any left-over bytes. */ - if (leftover) -@@ -1634,14 +1642,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, - break; - - case E_DFmode: -- cum->arg_words += 2; -+ if (TARGET_MB_64) -+ cum->arg_words++; -+ else -+ cum->arg_words += 2; - if (!cum->gp_reg_found && cum->arg_number <= 2) - cum->fp_code += 2 << ((cum->arg_number - 1) * 2); - break; - - case E_DImode: - cum->gp_reg_found = 1; -- cum->arg_words += 2; -+ if (TARGET_MB_64) -+ cum->arg_words++; -+ else -+ cum->arg_words += 2; - break; - - case E_QImode: -@@ -2156,7 +2170,7 @@ compute_frame_size (HOST_WIDE_INT size) - - if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) - /* Don't account for link register. It is accounted specially below. */ -- gp_reg_size += GET_MODE_SIZE (SImode); -+ gp_reg_size += GET_MODE_SIZE (Pmode); - - mask |= (1L << (regno - GP_REG_FIRST)); - } -@@ -2425,7 +2439,7 @@ print_operand (FILE * file, rtx op, int letter) - - if ((letter == 'M' && !WORDS_BIG_ENDIAN) - || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') -- regnum++; -+ regnum++; - - fprintf (file, "%s", reg_names[regnum]); - } -@@ -2451,6 +2465,7 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -+ int val1[2]; - long l[2]; - if (code == CONST_DOUBLE) - { -@@ -2463,12 +2478,12 @@ print_operand (FILE * file, rtx op, int letter) - val[0] = l[WORDS_BIG_ENDIAN != 0]; - } - } -- else if (code == CONST_INT) -+ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) - { -- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -- val[1] = INTVAL (op) & 0x00000000ffffffffLL; -+ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -+ val1[1] = INTVAL (op) & 0x00000000ffffffffLL; - } -- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); -+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); - } - else if (code == CONST_DOUBLE) - { -@@ -2662,7 +2677,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) - - switch_to_section (get_section (section, 0, NULL)); - assemble_align (POINTER_SIZE); -- fputs ("\t.word\t", asm_out_file); -+ if (TARGET_MB_64) -+ fputs ("\t.dword\t", asm_out_file); -+ else -+ fputs ("\t.word\t", asm_out_file); - output_addr_const (asm_out_file, symbol); - fputs ("\n", asm_out_file); - } -@@ -2685,7 +2703,10 @@ microblaze_asm_destructor (rtx symbol, int priority) - - switch_to_section (get_section (section, 0, NULL)); - assemble_align (POINTER_SIZE); -- fputs ("\t.word\t", asm_out_file); -+ if (TARGET_MB_64) -+ fputs ("\t.dword\t", asm_out_file); -+ else -+ fputs ("\t.word\t", asm_out_file); - output_addr_const (asm_out_file, symbol); - fputs ("\n", asm_out_file); - } -@@ -2751,7 +2772,7 @@ save_restore_insns (int prologue) - /* For interrupt_handlers, need to save/restore the MSR. */ - if (microblaze_is_interrupt_variant ()) - { -- isr_mem_rtx = gen_rtx_MEM (SImode, -+ isr_mem_rtx = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, base_reg_rtx, - GEN_INT (current_frame_info. - gp_offset - -@@ -2759,8 +2780,8 @@ save_restore_insns (int prologue) - - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (isr_mem_rtx) = 1; -- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG); -- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG); -+ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG); -+ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG); - } - - if (microblaze_is_interrupt_variant () && !prologue) -@@ -2768,8 +2789,8 @@ save_restore_insns (int prologue) - emit_move_insn (isr_reg_rtx, isr_mem_rtx); - emit_move_insn (isr_msr_rtx, isr_reg_rtx); - /* Do not optimize in flow analysis. */ -- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); -- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); - } - - for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) -@@ -2780,9 +2801,9 @@ save_restore_insns (int prologue) - /* Don't handle here. Already handled as the first register. */ - continue; - -- reg_rtx = gen_rtx_REG (SImode, regno); -+ reg_rtx = gen_rtx_REG (Pmode, regno); - insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset)); -- mem_rtx = gen_rtx_MEM (SImode, insn); -+ mem_rtx = gen_rtx_MEM (Pmode, insn); - if (microblaze_is_interrupt_variant () || save_volatiles) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; -@@ -2797,7 +2818,7 @@ save_restore_insns (int prologue) - insn = emit_move_insn (reg_rtx, mem_rtx); - } - -- gp_offset += GET_MODE_SIZE (SImode); -+ gp_offset += GET_MODE_SIZE (Pmode); - } - } - -@@ -2807,8 +2828,8 @@ save_restore_insns (int prologue) - emit_move_insn (isr_mem_rtx, isr_reg_rtx); - - /* Do not optimize in flow analysis. */ -- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); -- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); - } - - /* Done saving and restoring */ -@@ -2898,7 +2919,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) - - switch_to_section (s); - assemble_align (POINTER_SIZE); -- fputs ("\t.word\t", asm_out_file); -+ if (TARGET_MB_64) -+ fputs ("\t.dword\t", asm_out_file); -+ else -+ fputs ("\t.word\t", asm_out_file); - output_addr_const (asm_out_file, symbol); - fputs ("\n", asm_out_file); - } -@@ -3042,10 +3066,10 @@ microblaze_expand_prologue (void) - { - if (offset != 0) - ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); -- emit_move_insn (gen_rtx_MEM (SImode, ptr), -- gen_rtx_REG (SImode, regno)); -+ emit_move_insn (gen_rtx_MEM (Pmode, ptr), -+ gen_rtx_REG (Pmode, regno)); - -- offset += GET_MODE_SIZE (SImode); -+ offset += GET_MODE_SIZE (Pmode); - } - } - -@@ -3054,15 +3078,23 @@ microblaze_expand_prologue (void) - rtx fsiz_rtx = GEN_INT (fsiz); - - rtx_insn *insn = NULL; -- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ if (TARGET_MB_64) -+ { -+ -+ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, - fsiz_rtx)); -+ } -+ else { -+ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ fsiz_rtx)); -+ } - if (insn) - RTX_FRAME_RELATED_P (insn) = 1; - - /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */ - if (!crtl->is_leaf || interrupt_handler) - { -- mem_rtx = gen_rtx_MEM (SImode, -+ mem_rtx = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, stack_pointer_rtx, - const0_rtx)); - -@@ -3070,7 +3102,7 @@ microblaze_expand_prologue (void) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; - -- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); - insn = emit_move_insn (mem_rtx, reg_rtx); - RTX_FRAME_RELATED_P (insn) = 1; - } -@@ -3180,12 +3212,12 @@ microblaze_expand_epilogue (void) - if (!crtl->is_leaf || interrupt_handler) - { - mem_rtx = -- gen_rtx_MEM (SImode, -+ gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); - if (interrupt_handler) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; -- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); - emit_move_insn (reg_rtx, mem_rtx); - } - -@@ -3201,15 +3233,25 @@ microblaze_expand_epilogue (void) - /* _restore_ registers for epilogue. */ - save_restore_insns (0); - emit_insn (gen_blockage ()); -- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); -+ if (TARGET_MB_64) -+ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); -+ else -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); - } - - if (crtl->calls_eh_return) -- emit_insn (gen_addsi3 (stack_pointer_rtx, -+ if (TARGET_MB_64) { -+ emit_insn (gen_adddi3 (stack_pointer_rtx, - stack_pointer_rtx, -- gen_raw_REG (SImode, -+ gen_raw_REG (Pmode, - MB_EH_STACKADJ_REGNUM))); -- -+ } -+ else { -+ emit_insn (gen_addsi3 (stack_pointer_rtx, -+ stack_pointer_rtx, -+ gen_raw_REG (Pmode, -+ MB_EH_STACKADJ_REGNUM))); -+ } - emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + - MB_ABI_SUB_RETURN_ADDR_REGNUM))); - } -@@ -3376,9 +3418,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, - else - this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); - -- /* Apply the constant offset, if required. */ -+ /* Apply the constant offset, if required. */ - if (delta) -- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); -+ { -+ if (TARGET_MB_64) -+ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); -+ else -+ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); -+ } - - /* Apply the offset from the vtable, if required. */ - if (vcall_offset) -@@ -3391,7 +3438,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, - rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); - emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); - -- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); -+ if (TARGET_MB_64) -+ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1)); -+ else -+ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); - } - - /* Generate a tail call to the target function. */ -@@ -3622,9 +3672,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) - emit_block_move (m_tramp, assemble_trampoline_template (), - GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); - -- mem = adjust_address (m_tramp, SImode, 16); -+ mem = adjust_address (m_tramp, Pmode, 16); - emit_move_insn (mem, chain_value); -- mem = adjust_address (m_tramp, SImode, 20); -+ mem = adjust_address (m_tramp, Pmode, 20); - emit_move_insn (mem, fnaddr); - } - -@@ -3648,7 +3698,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - { - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -- if (mode == SImode) -+ if (mode == Pmode) - emit_jump_insn (gen_condjump (condition, label1)); - else - emit_jump_insn (gen_long_condjump (condition, label1)); -@@ -3767,7 +3817,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) - rtx comp_reg = gen_reg_rtx (SImode); - - emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); -- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); - emit_jump_insn (gen_condjump (condition, operands[3])); - } - -@@ -3777,10 +3827,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) - rtx condition; - rtx cmp_op0 = XEXP (operands[0], 0); - rtx cmp_op1 = XEXP (operands[0], 1); -- rtx comp_reg = gen_reg_rtx (DImode); -+ rtx comp_reg = gen_reg_rtx (Pmode); - - emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); -- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); -+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); - emit_jump_insn (gen_long_condjump (condition, operands[3])); - } - -@@ -3801,8 +3851,8 @@ microblaze_expand_divide (rtx operands[]) - { - /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ - -- rtx regt1 = gen_reg_rtx (SImode); -- rtx reg18 = gen_rtx_REG (SImode, R_TMP); -+ rtx regt1 = gen_reg_rtx (Pmode); -+ rtx reg18 = gen_rtx_REG (Pmode, R_TMP); - rtx regqi = gen_reg_rtx (QImode); - rtx_code_label *div_label = gen_label_rtx (); - rtx_code_label *div_end_label = gen_label_rtx (); -@@ -3810,17 +3860,31 @@ microblaze_expand_divide (rtx operands[]) - rtx mem_rtx; - rtx ret; - rtx_insn *jump, *cjump, *insn; -- -- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); -- cjump = emit_jump_insn_after (gen_cbranchsi4 ( -- gen_rtx_GTU (SImode, regt1, GEN_INT (15)), -+ -+ if (TARGET_MB_64) { -+ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2])); -+ cjump = emit_jump_insn_after (gen_cbranchdi4 ( -+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), -+ regt1, GEN_INT (15), div_label), insn); -+ } -+ else { -+ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); -+ cjump = emit_jump_insn_after (gen_cbranchsi4 ( -+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), - regt1, GEN_INT (15), div_label), insn); -+ } - LABEL_NUSES (div_label) = 1; - JUMP_LABEL (cjump) = div_label; -- emit_insn (gen_rtx_CLOBBER (SImode, reg18)); -+ emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); - -- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); -- emit_insn (gen_addsi3 (regt1, regt1, operands[2])); -+ if (TARGET_MB_64) { -+ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); -+ emit_insn (gen_adddi3 (regt1, regt1, operands[2])); -+ } -+ else { -+ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); -+ emit_insn (gen_addsi3 (regt1, regt1, operands[2])); -+ } - mem_rtx = gen_rtx_MEM (QImode, - gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - -@@ -3967,7 +4031,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) - { - insn = - emit_insn_before (gen_iprefetch -- (gen_int_mode (addr_offset, SImode)), -+ (gen_int_mode (addr_offset, Pmode)), - before_4); - recog_memoized (insn); - INSN_LOCATION (insn) = INSN_LOCATION (before_4); -@@ -3977,7 +4041,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) - } - } - } -- -+ -+/* Set the names for various arithmetic operations according to the -+ * MICROBLAZE ABI. */ -+static void -+microblaze_init_libfuncs (void) -+{ -+ set_optab_libfunc (smod_optab, SImode, "__modsi3"); -+ set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); -+ set_optab_libfunc (smul_optab, SImode, "__mulsi3"); -+ set_optab_libfunc (umod_optab, SImode, "__umodsi3"); -+ set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); -+ -+ if (TARGET_MB_64) -+ { -+ set_optab_libfunc (smod_optab, DImode, "__moddi3"); -+ set_optab_libfunc (sdiv_optab, DImode, "__divdi3"); -+ set_optab_libfunc (smul_optab, DImode, "__muldi3"); -+ set_optab_libfunc (umod_optab, DImode, "__umoddi3"); -+ set_optab_libfunc (udiv_optab, DImode, "__udivdi3"); -+ } -+} - /* Insert instruction prefetch instruction at the fall - through path of the function call. */ - -@@ -4130,6 +4214,17 @@ microblaze_starting_frame_offset (void) - #undef TARGET_LRA_P - #define TARGET_LRA_P hook_bool_void_false - -+#ifdef TARGET_MB_64 -+#undef TARGET_ASM_ALIGNED_DI_OP -+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" -+ -+#undef TARGET_ASM_ALIGNED_HI_OP -+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" -+ -+#undef TARGET_ASM_ALIGNED_SI_OP -+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" -+#endif -+ - #undef TARGET_FRAME_POINTER_REQUIRED - #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required - -@@ -4139,6 +4234,9 @@ microblaze_starting_frame_offset (void) - #undef TARGET_TRAMPOLINE_INIT - #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init - -+#undef TARGET_INIT_LIBFUNCS -+#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs -+ - #undef TARGET_PROMOTE_FUNCTION_MODE - #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 885abc6e5a1..5f30b8ac195 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; - - /* Generate DWARF exception handling info. */ - #define DWARF2_UNWIND_INFO 1 -- - /* Don't generate .loc operations. */ - #define DWARF2_ASM_LINE_DEBUG_INFO 0 - -@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe; - ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr) - - /* Use DWARF 2 debugging information by default. */ --#define DWARF2_DEBUGGING_INFO -+#define DWARF2_DEBUGGING_INFO 1 - #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+#define DWARF2_ADDR_SIZE 4 - - /* Target machine storage layout */ - - #define BITS_BIG_ENDIAN 0 - #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) - #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) --#define BITS_PER_WORD 32 --#define UNITS_PER_WORD 4 -+//#define BITS_PER_WORD 64 -+//Revisit -+#define MAX_BITS_PER_WORD 64 -+#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) -+//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) -+//#define UNITS_PER_WORD 4 - #define MIN_UNITS_PER_WORD 4 - #define INT_TYPE_SIZE 32 - #define SHORT_TYPE_SIZE 16 --#define LONG_TYPE_SIZE 64 -+#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32) - #define LONG_LONG_TYPE_SIZE 64 - #define FLOAT_TYPE_SIZE 32 - #define DOUBLE_TYPE_SIZE 64 - #define LONG_DOUBLE_TYPE_SIZE 64 --#define POINTER_SIZE 32 --#define PARM_BOUNDARY 32 --#define FUNCTION_BOUNDARY 32 --#define EMPTY_FIELD_BOUNDARY 32 -+#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32) -+//#define WIDEST_HARDWARE_FP_SIZE 64 -+//#define POINTERS_EXTEND_UNSIGNED 1 -+#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32) -+#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32) -+#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32) - #define STRUCTURE_SIZE_BOUNDARY 8 --#define BIGGEST_ALIGNMENT 32 -+#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32) - #define STRICT_ALIGNMENT 1 - #define PCC_BITFIELD_TYPE_MATTERS 1 - -+//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode) - #undef SIZE_TYPE --#define SIZE_TYPE "unsigned int" -+#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") - - #undef PTRDIFF_TYPE --#define PTRDIFF_TYPE "int" -+#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int") -+ -+/*#undef INTPTR_TYPE -+#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/ -+#undef UINTPTR_TYPE -+#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") - - #define DATA_ALIGNMENT(TYPE, ALIGN) \ - ((((ALIGN) < BITS_PER_WORD) \ -@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe; - #define WORD_REGISTER_OPERATIONS 1 - - #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND -- -+/* - #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ - if (GET_MODE_CLASS (MODE) == MODE_INT \ -- && GET_MODE_SIZE (MODE) < 4) \ -- (MODE) = SImode; -- -+ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ -+ (MODE) = TARGET_MB_64 ? DImode : SImode; -+*/ - /* Standard register usage. */ - - /* On the MicroBlaze, we have 32 integer registers */ -@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info; - #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) - - #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 -+#define DWARF_CIE_DATA_ALIGNMENT -1 - - #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - - #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 - --#define STACK_BOUNDARY 32 -+#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) - -+#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) -+ - #define NUM_OF_ARGS 6 - - #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) -@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info; - #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS - - #define LIBCALL_VALUE(MODE) \ -+ gen_rtx_REG (MODE,GP_RETURN) -+ -+/*#define LIBCALL_VALUE(MODE) \ - gen_rtx_REG ( \ - ((GET_MODE_CLASS (MODE) != MODE_INT \ - || GET_MODE_SIZE (MODE) >= 4) \ - ? (MODE) \ - : SImode), GP_RETURN) -- -+*/ - /* 1 if N is a possible register number for a function value. - On the MicroBlaze, R2 R3 are the only register thus used. - Currently, R2 are only implemented here (C has no complex type) */ -@@ -500,7 +518,7 @@ typedef struct microblaze_args - /* 4 insns + 2 words of data. */ - #define TRAMPOLINE_SIZE (6 * 4) - --#define TRAMPOLINE_ALIGNMENT 32 -+#define TRAMPOLINE_ALIGNMENT 64 - - #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) - -@@ -529,13 +547,13 @@ typedef struct microblaze_args - addresses which require two reload registers. */ - #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) - --#define CASE_VECTOR_MODE (SImode) -+#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode) - - #ifndef DEFAULT_SIGNED_CHAR - #define DEFAULT_SIGNED_CHAR 1 - #endif - --#define MOVE_MAX 4 -+#define MOVE_MAX (TARGET_MB_64 ? 8 : 4) - #define MAX_MOVE_MAX 8 - - #define SLOW_BYTE_ACCESS 1 -@@ -545,7 +563,7 @@ typedef struct microblaze_args - - #define SHIFT_COUNT_TRUNCATED 1 - --#define Pmode SImode -+#define Pmode (TARGET_MB_64? DImode:SImode) - - #define FUNCTION_MODE SImode - -@@ -707,6 +725,7 @@ do { \ - - #undef TARGET_ASM_OUTPUT_IDENT - #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident -+//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive - - /* Default to -G 8 */ - #ifndef MICROBLAZE_DEFAULT_GVALUE -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 40711fe224b..c99150ff0da 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -26,6 +26,7 @@ - ;; Constants - ;;---------------------------------------------------- - (define_constants [ -+ (R_Z 0) ;; For reg r0 - (R_SP 1) ;; Stack pointer reg - (R_SR 15) ;; Sub-routine return addr reg - (R_IR 14) ;; Interrupt return addr reg -@@ -541,6 +542,7 @@ - - ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] - ;; Leave carry as is -+ - (define_insn "addsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d") - (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") -@@ -562,23 +564,38 @@ - - ;; Adding 2 DI operands in register or reg/imm - --(define_insn "adddi3_long" -+(define_expand "adddi3" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (plus:DI (match_operand:DI 1 "register_operand" "") -+ (match_operand:DI 2 "arith_plus_operand" "")))] -+"" -+{ -+ if (TARGET_MB_64) -+ { -+ if (GET_CODE (operands[2]) == CONST_INT && -+ INTVAL(operands[2]) < (long)-549755813888 && -+ INTVAL(operands[2]) > (long)549755813887) -+ FAIL; -+ } -+}) -+ -+(define_insn "*adddi3_long" - [(set (match_operand:DI 0 "register_operand" "=d,d") -- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") -+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") - (match_operand:DI 2 "arith_plus_operand" "d,K")))] - "TARGET_MB_64" - "@ -- addlk\t%0,%z1,%2 -- addlik\t%0,%z1,%2" -- [(set_attr "type" "arith,arith") -- (set_attr "mode" "DI,DI") -+ addlk\t%0,%1,%2 -+ addlik\t%0,%1,%2 #N10" -+ [(set_attr "type" "darith,no_delay_arith") -+ (set_attr "mode" "DI") - (set_attr "length" "4,4")]) - --(define_insn "adddi3" -+(define_insn "*adddi3_all" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (match_operand:DI 1 "register_operand" "%d,d") - (match_operand:DI 2 "arith_operand" "d,i")))] -- "" -+ "!TARGET_MB_64" - "@ - add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 - addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" -@@ -605,7 +622,7 @@ - (define_insn "iprefetch" - [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) - (clobber (mem:BLK (scratch)))] -- "TARGET_PREFETCH" -+ "TARGET_PREFETCH && !TARGET_MB_64" - { - operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); - return "mfs\t%2,rpc\n\twic\t%2,r0"; -@@ -618,23 +635,33 @@ - ;; Double Precision Subtraction - ;;---------------------------------------------------------------- - --(define_insn "subdi3_long" -- [(set (match_operand:DI 0 "register_operand" "=d,d") -- (minus:DI (match_operand:DI 1 "register_operand" "d,d") -- (match_operand:DI 2 "register_operand" "d,n")))] -+(define_expand "subdi3" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (minus:DI (match_operand:DI 1 "register_operand" "") -+ (match_operand:DI 2 "arith_operand" "")))] -+"" -+" -+{ -+}") -+ -+(define_insn "subsidi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d,d") -+ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") -+ (match_operand:DI 2 "arith_operand" "d,K,n")))] - "TARGET_MB_64" - "@ - rsubl\t%0,%2,%1 -- addlik\t%0,%z1,-%2" -- [(set_attr "type" "darith") -- (set_attr "mode" "DI,DI") -- (set_attr "length" "4,4")]) -+ addik\t%0,%z1,-%2 -+ addik\t%0,%z1,-%2" -+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4,4,4")]) - --(define_insn "subdi3" -+(define_insn "subdi3_small" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] -- "" -+ "!TARGET_MB_64" - "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" - [(set_attr "type" "darith") - (set_attr "mode" "DI") -@@ -663,7 +690,7 @@ - (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] -- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" -+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" - "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -674,7 +701,7 @@ - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] -- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" -+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" - "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -685,7 +712,7 @@ - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] -- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" -+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" - "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -789,7 +816,7 @@ - (match_operand:SI 4 "arith_operand")]) - (label_ref (match_operand 5)) - (pc)))] -- "TARGET_HARD_FLOAT" -+ "TARGET_HARD_FLOAT && !TARGET_MB_64" - [(set (match_dup 1) (match_dup 3))] - - { -@@ -819,6 +846,15 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "negsi_long" -+ [(set (match_operand:SI 0 "register_operand" "=d") -+ (neg:SI (match_operand:DI 1 "register_operand" "d")))] -+ "" -+ "rsubk\t%0,%1,r0" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "4")]) -+ - (define_insn "negdi2_long" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d")))] -@@ -847,16 +883,24 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - --(define_insn "one_cmpldi2_long" -+(define_expand "one_cmpldi2" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (not:DI (match_operand:DI 1 "register_operand" "")))] -+ "" -+ " -+{ -+}") -+ -+(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=d") -- (not:DI (match_operand:DI 1 "register_operand" "d")))] -+ (not:DI (match_operand:DI 1 "arith_operand" "d")))] - "TARGET_MB_64" - "xorli\t%0,%1,-1" -- [(set_attr "type" "arith") -+ [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") - (set_attr "length" "4")]) - --(define_insn "*one_cmpldi2" -+(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=d") - (not:DI (match_operand:DI 1 "register_operand" "d")))] - "" -@@ -871,7 +915,8 @@ - (not:DI (match_operand:DI 1 "register_operand" "")))] - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) -- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" -+ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -+ && !TARGET_MB_64" - - [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) - (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] -@@ -883,18 +928,17 @@ - ;;---------------------------------------------------------------- - - (define_insn "anddi3" -- [(set (match_operand:DI 0 "register_operand" "=d,d") -- (and:DI (match_operand:DI 1 "arith_operand" "d,d") -- (match_operand:DI 2 "arith_operand" "d,K")))] -+ [(set (match_operand:DI 0 "register_operand" "=d,d,d") -+ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") -+ (match_operand:DI 2 "arith_operand" "d,K,I")))] - "TARGET_MB_64" - "@ - andl\t%0,%1,%2 -- andli\t%0,%1,%2 #andl1" -- ;; andli\t%0,%1,%2 #andl3 -- ;; andli\t%0,%1,%2 #andl2 -- [(set_attr "type" "arith,arith") -- (set_attr "mode" "DI,DI") -- (set_attr "length" "4,4")]) -+ andli\t%0,%1,%2 #andl2 -+ andli\t%0,%1,%2 #andl3" -+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") -+ (set_attr "mode" "DI,DI,DI") -+ (set_attr "length" "4,4,4")]) - - (define_insn "andsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") -@@ -919,7 +963,7 @@ - "@ - orl\t%0,%1,%2 - orli\t%0,%1,%2 #andl1" -- [(set_attr "type" "arith,arith") -+ [(set_attr "type" "arith,no_delay_arith") - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")]) - -@@ -945,7 +989,7 @@ - "@ - xorl\t%0,%1,%2 - xorli\t%0,%1,%2 #andl1" -- [(set_attr "type" "arith,arith") -+ [(set_attr "type" "arith,no_delay_arith") - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")]) - -@@ -1018,26 +1062,6 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - --;;(define_expand "extendqidi2" --;; [(set (match_operand:DI 0 "register_operand" "=d") --;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] --;; "TARGET_MB_64" --;; { --;; if (GET_CODE (operands[1]) != REG) --;; FAIL; --;; } --;;) -- -- --;;(define_insn "extendqidi2" --;; [(set (match_operand:DI 0 "register_operand" "=d") --;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] --;; "TARGET_MB_64" --;; "sextl8\t%0,%1" --;; [(set_attr "type" "arith") --;; (set_attr "mode" "DI") --;; (set_attr "length" "4")]) -- - (define_insn "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] -@@ -1060,6 +1084,27 @@ - ;; Those for integer source operand are ordered - ;; widest source type first. - -+(define_insn "extendsidi2_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d,d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] -+ "TARGET_MB_64" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "sextl32\t%0,%1"; -+ case 1: -+ case 2: -+ { -+ output_asm_insn ("ll%i1\t%0,%1", operands); -+ return "sextl32\t%0,%0"; -+ } -+ } -+ } -+ [(set_attr "type" "multi,multi,multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4,8,8")]) -+ - (define_insn "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] -@@ -1088,69 +1133,118 @@ - ;; Unlike most other insns, the move insns can't be split with - ;; different predicates, because register spilling and other parts of - ;; the compiler, have memoized the insn number already. -+;; //} - - (define_expand "movdi" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "" - { -- /* If operands[1] is a constant address illegal for pic, then we need to -- handle it just like microblaze_legitimize_address does. */ -- if (flag_pic && pic_address_needs_scratch (operands[1])) -+ if (TARGET_MB_64) - { -+ if (microblaze_expand_move (DImode, operands)) DONE; -+ } -+ else -+ { -+ /* If operands[1] is a constant address illegal for pic, then we need to -+ handle it just like microblaze_legitimize_address does. */ -+ if (flag_pic && pic_address_needs_scratch (operands[1])) -+ { - rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); - rtx temp2 = XEXP (XEXP (operands[1], 0), 1); - emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2)); - DONE; -- } -- -- -- if ((reload_in_progress | reload_completed) == 0 -- && !register_operand (operands[0], DImode) -- && !register_operand (operands[1], DImode) -- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) -- && operands[1] != CONST0_RTX (DImode)))) -- { -+ } - -- rtx temp = force_reg (DImode, operands[1]); -- emit_move_insn (operands[0], temp); -- DONE; -+ if ((reload_in_progress | reload_completed) == 0 -+ && !register_operand (operands[0], DImode) -+ && !register_operand (operands[1], DImode) -+ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) -+ && operands[1] != CONST0_RTX (DImode)))) -+ { -+ rtx temp = force_reg (DImode, operands[1]); -+ emit_move_insn (operands[0], temp); -+ DONE; -+ } - } - } - ) - -+;; Added for status registers -+(define_insn "movdi_status" -+ [(set (match_operand:DI 0 "register_operand" "=d,d,z") -+ (match_operand:DI 1 "register_operand" "z,d,d"))] -+ "microblaze_is_interrupt_variant () && TARGET_MB_64" -+ "@ -+ mfs\t%0,%1 #mfs -+ addlk\t%0,%1,r0 #add movdi -+ mts\t%0,%1 #mts" -+ [(set_attr "type" "move") -+ (set_attr "mode" "DI") -+ (set_attr "length" "12")]) -+ -+;; This move will be not be moved to delay slot. -+(define_insn "*movdi_internal3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") -+ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] -+ "TARGET_MB_64 && (register_operand (operands[0], DImode) && -+ (GET_CODE (operands[1]) == CONST_INT && -+ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" -+ "@ -+ addlk\t%0,r0,r0\t -+ addlik\t%0,r0,%1\t #N1 %X1 -+ addlik\t%0,r0,%1\t #N2 %X1" -+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) - --(define_insn "*movdi_internal_64" -- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") -- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] -- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" -+;; This move may be used for PLT label operand -+(define_insn "*movdi_internal5_pltop" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (match_operand:DI 1 "call_insn_operand" ""))] -+ "TARGET_MB_64 && (register_operand (operands[0], Pmode) && -+ PLT_ADDR_P (operands[1]))" -+ { -+ gcc_unreachable (); -+ } -+ [(set_attr "type" "load") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ -+(define_insn "*movdi_internal2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") -+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] -+ "TARGET_MB_64" - { - switch (which_alternative) - { - case 0: -- return "addlk\t%0,%1"; -- case 1: -- return "addlik\t%0,r0,%1"; -- case 2: -- return "addlk\t%0,r0,r0"; -- case 3: -- case 4: -- return "lli\t%0,%1"; -- case 5: -- case 6: -- return "sli\t%1,%0"; -- } -- return "unreachable"; -- } -- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ case 2: -+ if (GET_CODE (operands[1]) == CONST_INT && -+ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) -+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ else -+ return "addlik\t%0,r0,%1"; -+ case 3: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 5: -+ case 6: -+ return "sl%i0\t%z1,%0"; -+ } -+ } -+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") - (set_attr "mode" "DI") -- (set_attr "length" "8,8,8,8,12,8,12")]) -+ (set_attr "length" "4,4,12,4,8,4,8")]) -+ - - - (define_insn "*movdi_internal" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") - (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] -- "" -+ "!TARGET_MB_64" - { - switch (which_alternative) - { -@@ -1182,7 +1276,8 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))" -+ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1)) -+ && !(TARGET_MB_64)" - - [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) - (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] -@@ -1194,12 +1289,22 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" -+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) -+ && !(TARGET_MB_64)" - - [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) - (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] - "") - -+(define_insn "movdi_long_int" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (match_operand:DI 1 "general_operand" "i"))] -+ "" -+ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "12")]) -+ - ;; Unlike most other insns, the move insns can't be split with - ;; different predicates, because register spilling and other parts of - ;; the compiler, have memoized the insn number already. -@@ -1271,6 +1376,8 @@ - (set_attr "length" "4,4,8,4,8,4,8")]) - - -+ -+ - ;; 16-bit Integer moves - - ;; Unlike most other insns, the move insns can't be split with -@@ -1303,8 +1410,8 @@ - "@ - addik\t%0,r0,%1\t# %X1 - addk\t%0,%1,r0 -- lhui\t%0,%1 -- lhui\t%0,%1 -+ lhu%i1\t%0,%1 -+ lhu%i1\t%0,%1 - sh%i0\t%z1,%0 - sh%i0\t%z1,%0" - [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") -@@ -1347,7 +1454,7 @@ - lbu%i1\t%0,%1 - lbu%i1\t%0,%1 - sb%i0\t%z1,%0 -- sbi\t%z1,%0" -+ sb%i0\t%z1,%0" - [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") - (set_attr "mode" "QI") - (set_attr "length" "4,4,8,4,8,4,8")]) -@@ -1420,7 +1527,7 @@ - addik\t%0,r0,%F1 - lw%i1\t%0,%1 - sw%i0\t%z1,%0 -- swi\t%z1,%0" -+ sw%i0\t%z1,%0" - [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") - (set_attr "mode" "SF") - (set_attr "length" "4,4,4,4,4,4,4")]) -@@ -1459,6 +1566,33 @@ - ;; movdf_internal - ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT - ;; -+(define_insn "*movdf_internal_64" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") -+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] -+ "TARGET_MB_64" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ return "addlk\t%0,r0,r0"; -+ case 2: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 3: -+ { -+ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; -+ } -+ case 5: -+ return "sl%i0\t%1,%0"; -+ } -+ gcc_unreachable (); -+ } -+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4,4,4,16,4,4")]) -+ - (define_insn "*movdf_internal" - [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") - (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] -@@ -1493,7 +1627,8 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))" -+ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1)) -+ && !TARGET_MB_64" - [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) - (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] - "") -@@ -1504,7 +1639,8 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" -+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) -+ && !TARGET_MB_64" - [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) - (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] - "") -@@ -2003,6 +2139,31 @@ else - " - ) - -+ -+(define_insn "seq_internal_pat_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (eq:DI -+ (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "pcmpleq\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "sne_internal_pat_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (ne:DI -+ (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "pcmplne\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")] -+) -+ - (define_insn "seq_internal_pat" - [(set (match_operand:SI 0 "register_operand" "=d") - (eq:SI -@@ -2063,8 +2224,8 @@ else - (define_expand "cbranchsi4" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand:SI 1 "register_operand") -- (match_operand:SI 2 "arith_operand" "I,i")]) -+ [(match_operand 1 "register_operand") -+ (match_operand 2 "arith_operand" "I,i")]) - (label_ref (match_operand 3 "")) - (pc)))] - "" -@@ -2076,13 +2237,13 @@ else - (define_expand "cbranchsi4_reg" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand:SI 1 "register_operand") -- (match_operand:SI 2 "register_operand")]) -+ [(match_operand 1 "register_operand") -+ (match_operand 2 "register_operand")]) - (label_ref (match_operand 3 "")) - (pc)))] - "" - { -- microblaze_expand_conditional_branch_reg (SImode, operands); -+ microblaze_expand_conditional_branch_reg (Pmode, operands); - DONE; - }) - -@@ -2107,6 +2268,26 @@ else - (label_ref (match_operand 1)) - (pc)))]) - -+(define_insn "branch_zero64" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand 1 "register_operand" "d") -+ (const_int 0)]) -+ (match_operand 2 "pc_or_label_operand" "") -+ (match_operand 3 "pc_or_label_operand" ""))) -+ ] -+ "TARGET_MB_64" -+ { -+ if (operands[3] == pc_rtx) -+ return "bea%C0i%?\t%z1,%2"; -+ else -+ return "bea%N0i%?\t%z1,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")] -+) -+ - (define_insn "branch_zero" - [(set (pc) - (if_then_else (match_operator:SI 0 "ordered_comparison_operator" -@@ -2127,6 +2308,47 @@ else - (set_attr "length" "4")] - ) - -+(define_insn "branch_compare64" -+ [(set (pc) -+ (if_then_else (match_operator 0 "cmp_op" -+ [(match_operand 1 "register_operand" "d") -+ (match_operand 2 "register_operand" "d") -+ ]) -+ (label_ref (match_operand 3)) -+ (pc))) -+ (clobber(reg:SI R_TMP))] -+ "TARGET_MB_64" -+ { -+ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+ enum rtx_code code = GET_CODE (operands[0]); -+ -+ if (code == GT || code == LE) -+ { -+ output_asm_insn ("cmp\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GTU || code == LEU) -+ { -+ output_asm_insn ("cmpu\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GE || code == LT) -+ { -+ output_asm_insn ("cmp\tr18,%z2,%z1", operands); -+ } -+ else if (code == GEU || code == LTU) -+ { -+ output_asm_insn ("cmpu\tr18,%z2,%z1", operands); -+ } -+ -+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); -+ return "bea%C0i%?\tr18,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "12")] -+) -+ - (define_insn "branch_compare" - [(set (pc) - (if_then_else (match_operator:SI 0 "cmp_op" -@@ -2310,7 +2532,7 @@ else - ;; Indirect jumps. Jump to register values. Assuming absolute jumps - - (define_insn "indirect_jump_internal1" -- [(set (pc) (match_operand:SI 0 "register_operand" "d"))] -+ [(set (pc) (match_operand 0 "register_operand" "d"))] - "" - "bra%?\t%0" - [(set_attr "type" "jump") -@@ -2323,7 +2545,7 @@ else - (use (label_ref (match_operand 1 "" "")))] - "" - { -- gcc_assert (GET_MODE (operands[0]) == Pmode); -+ //gcc_assert (GET_MODE (operands[0]) == Pmode); - - if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) - emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); -@@ -2335,7 +2557,7 @@ else - - (define_insn "tablejump_internal1" - [(set (pc) -- (match_operand:SI 0 "register_operand" "d")) -+ (match_operand 0 "register_operand" "d")) - (use (label_ref (match_operand 1 "" "")))] - "" - "bra%?\t%0 " -@@ -2345,9 +2567,9 @@ else - - (define_expand "tablejump_internal3" - [(parallel [(set (pc) -- (plus:SI (match_operand:SI 0 "register_operand" "d") -- (label_ref:SI (match_operand:SI 1 "" "")))) -- (use (label_ref:SI (match_dup 1)))])] -+ (plus (match_operand 0 "register_operand" "d") -+ (label_ref (match_operand:SI 1 "" "")))) -+ (use (label_ref (match_dup 1)))])] - "" - "" - ) -@@ -2408,7 +2630,7 @@ else - (minus (reg 1) (match_operand 1 "register_operand" ""))) - (set (reg 1) - (minus (reg 1) (match_dup 1)))] -- "" -+ "!TARGET_MB_64" - { - rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); - rtx reg = gen_reg_rtx (Pmode); -@@ -2433,7 +2655,7 @@ else - (define_expand "save_stack_block" - [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "")] -- "" -+ "!TARGET_MB_64" - { - emit_move_insn (operands[0], operands[1]); - DONE; -@@ -2443,7 +2665,7 @@ else - (define_expand "restore_stack_block" - [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "")] -- "" -+ "!TARGET_MB_64" - { - rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); - rtx rtmp = gen_rtx_REG (SImode, R_TMP); -@@ -2490,7 +2712,7 @@ else - - (define_insn "_internal" - [(any_return) -- (use (match_operand:SI 0 "register_operand" ""))] -+ (use (match_operand 0 "register_operand" ""))] - "" - { - if (microblaze_is_break_handler ()) -@@ -2523,7 +2745,7 @@ else - (define_expand "call" - [(parallel [(call (match_operand 0 "memory_operand" "m") - (match_operand 1 "" "i")) -- (clobber (reg:SI R_SR)) -+ (clobber (reg R_SR)) - (use (match_operand 2 "" "")) - (use (match_operand 3 "" ""))])] - "" -@@ -2544,12 +2766,12 @@ else - - if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) - emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), - pic_offset_table_rtx)); - else - emit_call_insn (gen_call_internal0 (operands[0], operands[1], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); - - DONE; -@@ -2559,7 +2781,7 @@ else - (define_expand "call_internal0" - [(parallel [(call (match_operand 0 "" "") - (match_operand 1 "" "")) -- (clobber (match_operand:SI 2 "" ""))])] -+ (clobber (match_operand 2 "" ""))])] - "" - { - } -@@ -2568,18 +2790,34 @@ else - (define_expand "call_internal_plt0" - [(parallel [(call (match_operand 0 "" "") - (match_operand 1 "" "")) -- (clobber (match_operand:SI 2 "" "")) -- (use (match_operand:SI 3 "" ""))])] -+ (clobber (match_operand 2 "" "")) -+ (use (match_operand 3 "" ""))])] - "" - { - } - ) - -+(define_insn "call_internal_plt_64" -+ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR)) -+ (use (reg R_GOT))] -+ "flag_pic && TARGET_MB_64" -+ { -+ register rtx target2 = gen_rtx_REG (Pmode, -+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ gen_rtx_CLOBBER (VOIDmode, target2); -+ return "brealid\tr15,%0\;%#"; -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_internal_plt" -- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" "")) -- (match_operand:SI 1 "" "i")) -- (clobber (reg:SI R_SR)) -- (use (reg:SI R_GOT))] -+ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR)) -+ (use (reg R_GOT))] - "flag_pic" - { - rtx target2 -@@ -2591,10 +2829,41 @@ else - (set_attr "mode" "none") - (set_attr "length" "4")]) - -+(define_insn "call_internal1_64" -+ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR))] -+ "TARGET_MB_64" -+ { -+ register rtx target = operands[0]; -+ register rtx target2 = gen_rtx_REG (Pmode, -+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ if (GET_CODE (target) == SYMBOL_REF) { -+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) { -+ gen_rtx_CLOBBER (VOIDmode, target2); -+ return "breaki\tr16,%0\;%#"; -+ } -+ else { -+ gen_rtx_CLOBBER (VOIDmode, target2); -+ return "brealid\tr15,%0\;%#"; -+ } -+ } else if (GET_CODE (target) == CONST_INT) -+ return "la\t%@,r0,%0\;brald\tr15,%@\;%#"; -+ else if (GET_CODE (target) == REG) -+ return "brald\tr15,%0\;%#"; -+ else { -+ fprintf (stderr,"Unsupported call insn\n"); -+ return NULL; -+ } -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_internal1" - [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) -- (match_operand:SI 1 "" "i")) -- (clobber (reg:SI R_SR))] -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR))] - "" - { - rtx target = operands[0]; -@@ -2628,7 +2897,7 @@ else - [(parallel [(set (match_operand 0 "register_operand" "=d") - (call (match_operand 1 "memory_operand" "m") - (match_operand 2 "" "i"))) -- (clobber (reg:SI R_SR)) -+ (clobber (reg R_SR)) - (use (match_operand 3 "" ""))])] ;; next_arg_reg - "" - { -@@ -2649,13 +2918,13 @@ else - if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) - emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], - operands[2], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), - pic_offset_table_rtx)); - else - emit_call_insn (gen_call_value_internal (operands[0], operands[1], - operands[2], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); - - DONE; -@@ -2667,7 +2936,7 @@ else - [(parallel [(set (match_operand 0 "" "") - (call (match_operand 1 "" "") - (match_operand 2 "" ""))) -- (clobber (match_operand:SI 3 "" "")) -+ (clobber (match_operand 3 "" "")) - ])] - "" - {} -@@ -2677,18 +2946,35 @@ else - [(parallel[(set (match_operand 0 "" "") - (call (match_operand 1 "" "") - (match_operand 2 "" ""))) -- (clobber (match_operand:SI 3 "" "")) -- (use (match_operand:SI 4 "" ""))])] -+ (clobber (match_operand 3 "" "")) -+ (use (match_operand 4 "" ""))])] - "flag_pic" - {} - ) - -+(define_insn "call_value_intern_plt_64" -+ [(set (match_operand:VOID 0 "register_operand" "=d") -+ (call (mem (match_operand 1 "call_insn_plt_operand" "")) -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d")) -+ (use (match_operand 4 "register_operand"))] -+ "flag_pic && TARGET_MB_64" -+ { -+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ -+ gen_rtx_CLOBBER (VOIDmode,target2); -+ return "brealid\tr15,%1\;%#"; -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_value_intern_plt" - [(set (match_operand:VOID 0 "register_operand" "=d") -- (call (mem (match_operand:SI 1 "call_insn_plt_operand" "")) -- (match_operand:SI 2 "" "i"))) -- (clobber (match_operand:SI 3 "register_operand" "=d")) -- (use (match_operand:SI 4 "register_operand"))] -+ (call (mem (match_operand 1 "call_insn_plt_operand" "")) -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d")) -+ (use (match_operand 4 "register_operand"))] - "flag_pic" - { - rtx target2 -@@ -2701,11 +2987,46 @@ else - (set_attr "mode" "none") - (set_attr "length" "4")]) - -+(define_insn "call_value_intern_64" -+ [(set (match_operand:VOID 0 "register_operand" "=d") -+ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d"))] -+ "TARGET_MB_64" -+ { -+ register rtx target = operands[1]; -+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ -+ if (GET_CODE (target) == SYMBOL_REF) -+ { -+ gen_rtx_CLOBBER (VOIDmode,target2); -+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) -+ return "breaki\tr16,%1\;%#"; -+ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION) -+ { -+ return "brealid\tr15,%1\;%#"; -+ } -+ else -+ { -+ return "bralid\tr15,%1\;%#"; -+ } -+ } -+ else if (GET_CODE (target) == CONST_INT) -+ return "la\t%@,r0,%1\;brald\tr15,%@\;%#"; -+ else if (GET_CODE (target) == REG) -+ return "brald\tr15,%1\;%#"; -+ else -+ return "Unsupported call insn\n"; -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_value_intern" - [(set (match_operand:VOID 0 "register_operand" "=d") - (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) -- (match_operand:SI 2 "" "i"))) -- (clobber (match_operand:SI 3 "register_operand" "=d"))] -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d"))] - "" - { - rtx target = operands[1]; -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index 4c25cfe15e7..965132b3513 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -2,7 +2,8 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en - MULTILIB_DIRNAMES = bs m mh le m64 - MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high - MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian - MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 - MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 -diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S -index cbbe32d5f6a..ec797e1bf17 100644 ---- a/libgcc/config/microblaze/crti.S -+++ b/libgcc/config/microblaze/crti.S -@@ -40,7 +40,7 @@ - - .align 2 - __init: -- addik r1, r1, -8 -+ addik r1, r1, -16 - sw r15, r0, r1 - la r11, r0, _stack - mts rshr, r11 -@@ -51,5 +51,5 @@ __init: - .global __fini - .align 2 - __fini: -- addik r1, r1, -8 -+ addik r1, r1, -16 - sw r15, r0, r1 -diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S -index cb8d8ef2bfa..977b43b9436 100644 ---- a/libgcc/config/microblaze/crtn.S -+++ b/libgcc/config/microblaze/crtn.S -@@ -33,9 +33,9 @@ - .section .init, "ax" - lw r15, r0, r1 - rtsd r15, 8 -- addik r1, r1, 8 -+ addik r1, r1, 16 - - .section .fini, "ax" - lw r15, r0, r1 - rtsd r15, 8 -- addik r1, r1, 8 -+ addik r1, r1, 16 -diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S -new file mode 100644 -index 00000000000..d37bf5165c6 ---- /dev/null -+++ b/libgcc/config/microblaze/divdi3.S -@@ -0,0 +1,98 @@ -+###################################- -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# divdi3.S -+# -+# Divide operation for 32 bit integers. -+# Input : Dividend in Reg r5 -+# Divisor in Reg r6 -+# Output: Result in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __divdi3 -+ .ent __divdi3 -+ .type __divdi3,@function -+__divdi3: -+ .frame r1,0,r15 -+ -+ ADDLIK r1,r1,-32 -+ SLI r28,r1,0 -+ SLI r29,r1,8 -+ SLI r30,r1,16 -+ SLI r31,r1,24 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ XORL r28,r5,r6 # Get the sign of the result -+ BEALGEI r5,$LaR5_Pos -+ RSUBLI r5,r5,0 # Make r5 positive -+$LaR5_Pos: -+ BEALGEI r6,$LaR6_Pos -+ RSUBLI r6,r6,0 # Make r6 positive -+$LaR6_Pos: -+ ADDLIK r30,r0,0 # Clear mod -+ ADDLIK r3,r0,0 # clear div -+ ADDLIK r29,r0,64 # Initialize the loop count -+ -+ # First part try to find the first '1' in the r5 -+$LaDIV0: -+ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGTI r5,$LaDIV1 -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r30,r30,r30 # Move that bit into the Mod register -+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) -+ BEALLTI r31,$LaMOD_TOO_SMALL -+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r3,r3,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r3,r3,r3 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BEALGEI r28,$LaRETURN_HERE -+ RSUBLI r3,r3,0 # Negate the result -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ ORL r3,r0,r0 # set result to 0 -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r28,r1,0 -+ LLI r29,r1,8 -+ LLI r30,r1,16 -+ LLI r31,r1,24 -+ ADDLIK r1,r1,32 -+ RTSD r15,8 -+ nop -+.end __divdi3 -+ .size __divdi3, . - __divdi3 -+#endif -diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c -new file mode 100644 -index 00000000000..80962597ea5 ---- /dev/null -+++ b/libgcc/config/microblaze/divdi3_table.c -@@ -0,0 +1,62 @@ -+/* Table for software lookup divide for Xilinx MicroBlaze. -+ -+ Copyright (C) 2009-2017 Free Software Foundation, Inc. -+ -+ Contributed by Michael Eager . -+ -+ This file is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by the -+ Free Software Foundation; either version 3, or (at your option) any -+ later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+ -+unsigned char _divdi3_table[] = -+{ -+ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7, -+ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15, -+ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, -+ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15, -+ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7, -+ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15, -+ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7, -+ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15, -+ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7, -+ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15, -+ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7, -+ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15, -+ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7, -+ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15, -+ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7, -+ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15, -+ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7, -+ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15, -+ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7, -+ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15, -+ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7, -+ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15, -+ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7, -+ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15, -+ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7, -+ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15, -+ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7, -+ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15, -+ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7, -+ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15, -+ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7, -+ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15, -+}; -+ -diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S -new file mode 100644 -index 00000000000..5d3f7c03fc8 ---- /dev/null -+++ b/libgcc/config/microblaze/moddi3.S -@@ -0,0 +1,97 @@ -+################################### -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# moddi3.S -+# -+# modulo operation for 32 bit integers. -+# Input : op1 in Reg r5 -+# op2 in Reg r6 -+# Output: op1 mod op2 in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __moddi3 -+ .ent __moddi3 -+ .type __moddi3,@function -+__moddi3: -+ .frame r1,0,r15 -+ -+ addlik r1,r1,-32 -+ sli r28,r1,0 -+ sli r29,r1,8 -+ sli r30,r1,16 -+ sli r31,r1,32 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] -+ BEALGEI r5,$LaR5_Pos -+ RSUBLI r5,r5,0 # Make r5 positive -+$LaR5_Pos: -+ BEALGEI r6,$LaR6_Pos -+ RSUBLI r6,r6,0 # Make r6 positive -+$LaR6_Pos: -+ ADDLIK r3,r0,0 # Clear mod -+ ADDLIK r30,r0,0 # clear div -+ ADDLIK r29,r0,64 # Initialize the loop count -+ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip -+ # the first bit search. -+ # First part try to find the first '1' in the r5 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGEI r5,$LaDIV1 # -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r3,r3,r3 # Move that bit into the Mod register -+ rSUBL r31,r6,r3 # Try to subtract (r30 a r6) -+ BEALLTi r31,$LaMOD_TOO_SMALL -+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r30,r30,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BEALGEI r28,$LaRETURN_HERE -+ rsubli r3,r3,0 # Negate the result -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0] -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r28,r1,0 -+ lli r29,r1,8 -+ lli r30,r1,16 -+ lli r31,r1,24 -+ addlik r1,r1,32 -+ rtsd r15,8 -+ nop -+ .end __moddi3 -+ .size __moddi3, . - __moddi3 -+#endif -diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S -new file mode 100644 -index 00000000000..567784197d3 ---- /dev/null -+++ b/libgcc/config/microblaze/muldi3.S -@@ -0,0 +1,73 @@ -+/*###################################-*-asm*- -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# muldi3.S -+# -+# Multiply operation for 32 bit integers. -+# Input : Operand1 in Reg r5 -+# Operand2 in Reg r6 -+# Output: Result [op1 * op2] in Reg r3 -+# -+#######################################*/ -+ -+#ifdef __arch64__ -+ .globl __muldi3 -+ .ent __muldi3 -+ .type __muldi3,@function -+__muldi3: -+ .frame r1,0,r15 -+ addl r3,r0,r0 -+ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero -+ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero -+ XORL r4,r5,r6 # Get the sign of the result -+ BEALGEI r5,$L_R5_Pos -+ RSUBLI r5,r5,0 # Make r5 positive -+$L_R5_Pos: -+ BEALGEI r6,$L_R6_Pos -+ RSUBLI r6,r6,0 # Make r6 positive -+$L_R6_Pos: -+ breai $L1 -+$L2: -+ addl r5,r5,r5 -+$L1: -+ srll r6,r6 -+ addlc r7,r0,r0 -+ bealeqi r7,$L2 -+ addl r3,r3,r5 -+ bealnei r6,$L2 -+ beallti r4,$L_NegateResult -+ rtsd r15,8 -+ nop -+$L_NegateResult: -+ rsubl r3,r3,r0 -+ rtsd r15,8 -+ nop -+$L_Result_Is_Zero: -+ addli r3,r0,0 -+ rtsd r15,8 -+ nop -+ .end __muldi3 -+ .size __muldi3, . - __muldi3 -+#endif -diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 8d954a49575..35021b24b7d 100644 ---- a/libgcc/config/microblaze/t-microblaze -+++ b/libgcc/config/microblaze/t-microblaze -@@ -1,11 +1,16 @@ --LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 -+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ -+ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 - - LIB2ADD += \ - $(srcdir)/config/microblaze/divsi3.S \ -+ $(srcdir)/config/microblaze/divdi3.S \ - $(srcdir)/config/microblaze/modsi3.S \ -- $(srcdir)/config/microblaze/muldi3_hard.S \ -+ $(srcdir)/config/microblaze/moddi3.S \ - $(srcdir)/config/microblaze/mulsi3.S \ -+ $(srcdir)/config/microblaze/muldi3.S \ - $(srcdir)/config/microblaze/stack_overflow_exit.S \ - $(srcdir)/config/microblaze/udivsi3.S \ -+ $(srcdir)/config/microblaze/udivdi3.S \ - $(srcdir)/config/microblaze/umodsi3.S \ -- $(srcdir)/config/microblaze/divsi3_table.c -+ $(srcdir)/config/microblaze/umoddi3.S \ -+ $(srcdir)/config/microblaze/divsi3_table.c \ -diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S -new file mode 100644 -index 00000000000..c210fbc7128 ---- /dev/null -+++ b/libgcc/config/microblaze/udivdi3.S -@@ -0,0 +1,107 @@ -+###################################- -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# udivdi3.S -+# -+# Unsigned divide operation. -+# Input : Divisor in Reg r5 -+# Dividend in Reg r6 -+# Output: Result in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __udivdi3 -+ .ent __udivdi3 -+ .type __udivdi3,@function -+__udivdi3: -+ .frame r1,0,r15 -+ -+ ADDlIK r1,r1,-24 -+ SLI r29,r1,0 -+ SLI r30,r1,8 -+ SLI r31,r1,16 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ ADDLIK r30,r0,0 # Clear mod -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ ADDLIK r29,r0,64 # Initialize the loop count -+ -+ # Check if r6 and r5 are equal # if yes, return 1 -+ RSUBL r18,r5,r6 -+ ADDLIK r3,r0,1 -+ BEALEQI r18,$LaRETURN_HERE -+ -+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 -+ XORL r18,r5,r6 -+ ADDL r3,r0,r0 # We would anyways clear r3 -+ BEALGEI r18,$LRSUBL -+ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater -+ BREAI $LCheckr6 -+$LRSUBL: -+ RSUBL r18,r6,r5 # MICROBLAZEcmp -+ BEALLTI r18,$LaRETURN_HERE -+ -+ # If r6 [bit 31] is set, then return result as 1 -+$LCheckr6: -+ BEALGTI r6,$LaDIV0 -+ ADDLIK r3,r0,1 -+ BREAI $LaRETURN_HERE -+ -+ # First part try to find the first '1' in the r5 -+$LaDIV0: -+ BEALLTI r5,$LaDIV2 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGTI r5,$LaDIV1 -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r30,r30,r30 # Move that bit into the Mod register -+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) -+ BEALLTI r31,$LaMOD_TOO_SMALL -+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r3,r3,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r3,r3,r3 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ ORL r3,r0,r0 # set result to 0 -+$LaRETURN_HERE: -+ # Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r29,r1,0 -+ LLI r30,r1,8 -+ LLI r31,r1,16 -+ ADDLIK r1,r1,24 -+ RTSD r15,8 -+ NOP -+ .end __udivdi3 -+ .size __udivdi3, . - __udivdi3 -+#endif -diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S -new file mode 100644 -index 00000000000..7f5cd23f9a1 ---- /dev/null -+++ b/libgcc/config/microblaze/umoddi3.S -@@ -0,0 +1,110 @@ -+################################### -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# umoddi3.S -+# -+# Unsigned modulo operation for 32 bit integers. -+# Input : op1 in Reg r5 -+# op2 in Reg r6 -+# Output: op1 mod op2 in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __umoddi3 -+ .ent __umoddi3 -+ .type __umoddi3,@function -+__umoddi3: -+ .frame r1,0,r15 -+ -+ addlik r1,r1,-24 -+ sli r29,r1,0 -+ sli r30,r1,8 -+ sli r31,r1,16 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ ADDLIK r3,r0,0 # Clear div -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ ADDLIK r30,r0,0 # clear mod -+ ADDLIK r29,r0,64 # Initialize the loop count -+ -+# Check if r6 and r5 are equal # if yes, return 0 -+ rsubl r18,r5,r6 -+ bealeqi r18,$LaRETURN_HERE -+ -+# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 -+ xorl r18,r5,r6 -+ addlik r3,r5,0 -+ bealgei r18,$LRSUB -+ beallti r6,$LaRETURN_HERE -+ breai $LCheckr6 -+$LRSUB: -+ rsubl r18,r5,r6 # MICROBLAZEcmp -+ bealgti r18,$LaRETURN_HERE -+ -+# If r6 [bit 31] is set, then return result as r5-r6 -+$LCheckr6: -+ addlik r3,r0,0 -+ bealgti r6,$LaDIV0 -+ addlik r18,r0,0x7fffffff -+ andl r5,r5,r18 -+ andl r6,r6,r18 -+ breaid $LaRETURN_HERE -+ rsubl r3,r6,r5 -+# First part: try to find the first '1' in the r5 -+$LaDIV0: -+ BEALLTI r5,$LaDIV2 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGEI r5,$LaDIV1 # -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r3,r3,r3 # Move that bit into the Mod register -+ rSUBL r31,r6,r3 # Try to subtract (r3 a r6) -+ BEALLTi r31,$LaMOD_TOO_SMALL -+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r30,r30,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ orl r3,r0,r0 # set result to 0 -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r29,r1,0 -+ lli r30,r1,8 -+ lli r31,r1,16 -+ addlik r1,r1,24 -+ rtsd r15,8 -+ nop -+.end __umoddi3 -+ .size __umoddi3, . - __umoddi3 -+#endif --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch deleted file mode 100644 index 26cdfca2..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch +++ /dev/null @@ -1,269 +0,0 @@ -From 10d5e7d6cad5e7349b88b7469eb5ae20d87eb908 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 14:45:15 +0530 -Subject: [PATCH 29/53] [Patch,MicroBlaze] : re-arrangement of the compare - branches - ---- - gcc/config/microblaze/microblaze.cc | 28 ++---- - gcc/config/microblaze/microblaze.md | 141 +++++++++++++--------------- - 2 files changed, 73 insertions(+), 96 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 9d3628c6816..4792e3ba370 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -3698,11 +3698,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - { - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -- if (mode == Pmode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -- -+ emit_jump_insn (gen_condjump (condition, label1)); - } - - else if (code == EQ || code == NE) -@@ -3713,10 +3709,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - else - emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); - condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - } - else - { -@@ -3749,10 +3742,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), - mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - } - else if (code == EQ) - { -@@ -3767,10 +3757,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - cmp_op1)); - } - condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - - } - else if (code == NE) -@@ -3786,10 +3773,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - cmp_op1)); - } - condition = gen_rtx_NE (mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - } - else - { -@@ -3831,7 +3815,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) - - emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); - condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); -- emit_jump_insn (gen_long_condjump (condition, operands[3])); -+ emit_jump_insn (gen_condjump (condition, operands[3])); - } - - /* Implement TARGET_FRAME_POINTER_REQUIRED. */ -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index c99150ff0da..566c53ba228 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2268,7 +2268,27 @@ else - (label_ref (match_operand 1)) - (pc)))]) - --(define_insn "branch_zero64" -+(define_insn "branch_zero_64" -+ [(set (pc) -+ (if_then_else (match_operator:SI 0 "ordered_comparison_operator" -+ [(match_operand:SI 1 "register_operand" "d") -+ (const_int 0)]) -+ (match_operand:SI 2 "pc_or_label_operand" "") -+ (match_operand:SI 3 "pc_or_label_operand" ""))) -+ ] -+ "TARGET_MB_64" -+ { -+ if (operands[3] == pc_rtx) -+ return "bea%C0i%?\t%z1,%2"; -+ else -+ return "bea%N0i%?\t%z1,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "long_branch_zero" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" - [(match_operand 1 "register_operand" "d") -@@ -2279,9 +2299,9 @@ else - "TARGET_MB_64" - { - if (operands[3] == pc_rtx) -- return "bea%C0i%?\t%z1,%2"; -+ return "beal%C0i%?\t%z1,%2"; - else -- return "bea%N0i%?\t%z1,%3"; -+ return "beal%N0i%?\t%z1,%3"; - } - [(set_attr "type" "branch") - (set_attr "mode" "none") -@@ -2310,9 +2330,9 @@ else - - (define_insn "branch_compare64" - [(set (pc) -- (if_then_else (match_operator 0 "cmp_op" -- [(match_operand 1 "register_operand" "d") -- (match_operand 2 "register_operand" "d") -+ (if_then_else (match_operator:SI 0 "cmp_op" -+ [(match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "register_operand" "d") - ]) - (label_ref (match_operand 3)) - (pc))) -@@ -2349,6 +2369,47 @@ else - (set_attr "length" "12")] - ) - -+(define_insn "long_branch_compare" -+ [(set (pc) -+ (if_then_else (match_operator 0 "cmp_op" -+ [(match_operand 1 "register_operand" "d") -+ (match_operand 2 "register_operand" "d") -+ ]) -+ (label_ref (match_operand 3)) -+ (pc))) -+ (clobber(reg:DI R_TMP))] -+ "TARGET_MB_64" -+ { -+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ enum rtx_code code = GET_CODE (operands[0]); -+ -+ if (code == GT || code == LE) -+ { -+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GTU || code == LEU) -+ { -+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GE || code == LT) -+ { -+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); -+ } -+ else if (code == GEU || code == LTU) -+ { -+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); -+ } -+ -+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); -+ return "beal%C0i%?\tr18,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "12")] -+) -+ - (define_insn "branch_compare" - [(set (pc) - (if_then_else (match_operator:SI 0 "cmp_op" -@@ -2431,74 +2492,6 @@ else - - }) - --;; Used to implement comparison instructions --(define_expand "long_condjump" -- [(set (pc) -- (if_then_else (match_operand 0) -- (label_ref (match_operand 1)) -- (pc)))]) -- --(define_insn "long_branch_zero" -- [(set (pc) -- (if_then_else (match_operator:DI 0 "ordered_comparison_operator" -- [(match_operand:DI 1 "register_operand" "d") -- (const_int 0)]) -- (match_operand:DI 2 "pc_or_label_operand" "") -- (match_operand:DI 3 "pc_or_label_operand" ""))) -- ] -- "TARGET_MB_64" -- { -- if (operands[3] == pc_rtx) -- return "beal%C0i%?\t%z1,%2"; -- else -- return "beal%N0i%?\t%z1,%3"; -- } -- [(set_attr "type" "branch") -- (set_attr "mode" "none") -- (set_attr "length" "4")] --) -- --(define_insn "long_branch_compare" -- [(set (pc) -- (if_then_else (match_operator:DI 0 "cmp_op" -- [(match_operand:DI 1 "register_operand" "d") -- (match_operand:DI 2 "register_operand" "d") -- ]) -- (label_ref (match_operand 3)) -- (pc))) -- (clobber(reg:DI R_TMP))] -- "TARGET_MB_64" -- { -- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -- enum rtx_code code = GET_CODE (operands[0]); -- -- if (code == GT || code == LE) -- { -- output_asm_insn ("cmpl\tr18,%z1,%z2", operands); -- code = swap_condition (code); -- } -- else if (code == GTU || code == LEU) -- { -- output_asm_insn ("cmplu\tr18,%z1,%z2", operands); -- code = swap_condition (code); -- } -- else if (code == GE || code == LT) -- { -- output_asm_insn ("cmpl\tr18,%z2,%z1", operands); -- } -- else if (code == GEU || code == LTU) -- { -- output_asm_insn ("cmplu\tr18,%z2,%z1", operands); -- } -- -- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); -- return "beal%C0i%?\tr18,%3"; -- } -- [(set_attr "type" "branch") -- (set_attr "mode" "none") -- (set_attr "length" "12")] --) -- - ;;---------------------------------------------------------------- - ;; Unconditional branches - ;;---------------------------------------------------------------- --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch deleted file mode 100644 index 83d047cb..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From af910dd71faec99838e421dd76fd5231e34bee3e Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 8 Aug 2018 17:37:26 +0530 -Subject: [PATCH 30/53] [Patch,Microblaze] : previous commit broke the - handling of SI Branch compare for Microblaze 32-bit.. - ---- - gcc/config/microblaze/microblaze.md | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 566c53ba228..e54888550f6 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2224,8 +2224,8 @@ else - (define_expand "cbranchsi4" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand 1 "register_operand") -- (match_operand 2 "arith_operand" "I,i")]) -+ [(match_operand:SI 1 "register_operand") -+ (match_operand:SI 2 "arith_operand" "I,i")]) - (label_ref (match_operand 3 "")) - (pc)))] - "" --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch deleted file mode 100644 index c230049c..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 6921698fc0acf40cb036cf71649762e7a21bf604 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 11 Sep 2018 13:43:48 +0530 -Subject: [PATCH 31/53] [Patch, Microblaze] : Support of multilibs with m64 ... - -Conflicts: - gcc/config/microblaze/microblaze-c.c - -signed-off-by : Mahesh Bodapati ---- - gcc/config/microblaze/microblaze-c.cc | 1 + - gcc/config/microblaze/t-microblaze | 15 ++++++--------- - libgcc/config/microblaze/t-microblaze | 11 +++-------- - 3 files changed, 10 insertions(+), 17 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze-c.cc b/gcc/config/microblaze/microblaze-c.cc -index ef8d2430565..4e83a84b112 100644 ---- a/gcc/config/microblaze/microblaze-c.cc -+++ b/gcc/config/microblaze/microblaze-c.cc -@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) - } - if (TARGET_MB_64) - { -+ builtin_define ("__microblaze64"); - builtin_define ("__arch64__"); - builtin_define ("__microblaze64__"); - builtin_define ("__MICROBLAZE64__"); -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index 965132b3513..47b869b9303 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -1,12 +1,9 @@ --MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 --MULTILIB_DIRNAMES = bs m mh le m64 --MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high --MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian --MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 --MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 -+MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high -+MULTILIB_DIRNAMES = m64 bs le m mh -+MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high - - # Extra files - microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \ -diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 35021b24b7d..8d954a49575 100644 ---- a/libgcc/config/microblaze/t-microblaze -+++ b/libgcc/config/microblaze/t-microblaze -@@ -1,16 +1,11 @@ --LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ -- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 -+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 - - LIB2ADD += \ - $(srcdir)/config/microblaze/divsi3.S \ -- $(srcdir)/config/microblaze/divdi3.S \ - $(srcdir)/config/microblaze/modsi3.S \ -- $(srcdir)/config/microblaze/moddi3.S \ -+ $(srcdir)/config/microblaze/muldi3_hard.S \ - $(srcdir)/config/microblaze/mulsi3.S \ -- $(srcdir)/config/microblaze/muldi3.S \ - $(srcdir)/config/microblaze/stack_overflow_exit.S \ - $(srcdir)/config/microblaze/udivsi3.S \ -- $(srcdir)/config/microblaze/udivdi3.S \ - $(srcdir)/config/microblaze/umodsi3.S \ -- $(srcdir)/config/microblaze/umoddi3.S \ -- $(srcdir)/config/microblaze/divsi3_table.c \ -+ $(srcdir)/config/microblaze/divsi3_table.c --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Patch-MicroBlaze-Fixed-issues-like.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Patch-MicroBlaze-Fixed-issues-like.patch deleted file mode 100644 index 36a20450..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Patch-MicroBlaze-Fixed-issues-like.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 7f827e73dff27c764e5f475613e3e06ae546103f Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 15:24:25 +0530 -Subject: [PATCH 32/53] [Patch,MicroBlaze]: Fixed issues like: 1 Interrupt - alignment issue 2 Sign extension issue - ---- - gcc/config/microblaze/microblaze.cc | 16 ++++++++++------ - gcc/config/microblaze/microblaze.md | 2 +- - 2 files changed, 11 insertions(+), 7 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 4792e3ba370..f1da145232a 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2178,9 +2178,14 @@ compute_frame_size (HOST_WIDE_INT size) - - total_size += gp_reg_size; - -- /* Add 4 bytes for MSR. */ -+ /* Add 4/8 bytes for MSR. */ - if (microblaze_is_interrupt_variant ()) -- total_size += 4; -+ { -+ if (TARGET_MB_64) -+ total_size += 8; -+ else -+ total_size += 4; -+ } - - /* No space to be allocated for link register in leaf functions with no other - stack requirements. */ -@@ -2465,7 +2470,6 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -- int val1[2]; - long l[2]; - if (code == CONST_DOUBLE) - { -@@ -2480,10 +2484,10 @@ print_operand (FILE * file, rtx op, int letter) - } - else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) - { -- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -- val1[1] = INTVAL (op) & 0x00000000ffffffffLL; -+ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -+ val[1] = INTVAL (op) & 0x00000000ffffffffLL; - } -- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); -+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); - } - else if (code == CONST_DOUBLE) - { -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index e54888550f6..4e5d21a1f4c 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1096,7 +1096,7 @@ - case 1: - case 2: - { -- output_asm_insn ("ll%i1\t%0,%1", operands); -+ output_asm_insn ("lw%i1\t%0,%1", operands); - return "sextl32\t%0,%0"; - } - } --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Patch-MicroBlaze.patch deleted file mode 100644 index 9c9e4dd2..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Patch-MicroBlaze.patch +++ /dev/null @@ -1,305 +0,0 @@ -From 0a86428a345ed359f788a72a0e185053b598e908 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 15:28:58 +0530 -Subject: [PATCH 33/53] [Patch,MicroBlaze]: fixed below issues: - Floating - point print issues in 64bit mode - Dejagnu Jump related issues - - Added dbl instruction - - Conflicts: - gcc/config/microblaze/microblaze.md ---- - gcc/config/microblaze/microblaze.cc | 12 +++- - gcc/config/microblaze/microblaze.h | 7 +++ - gcc/config/microblaze/microblaze.md | 86 ++++++++++++++++++++++++----- - libgcc/config/microblaze/crti.S | 24 +++++++- - libgcc/config/microblaze/crtn.S | 13 +++++ - 5 files changed, 125 insertions(+), 17 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index f1da145232a..7a08390a027 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2474,7 +2474,12 @@ print_operand (FILE * file, rtx op, int letter) - if (code == CONST_DOUBLE) - { - if (GET_MODE (op) == DFmode) -- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); -+ { -+ if (TARGET_MB_64) -+ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); -+ else -+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); -+ } - else - { - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); -@@ -3877,7 +3882,10 @@ microblaze_expand_divide (rtx operands[]) - gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - - insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); -- jump = emit_jump_insn_after (gen_jump (div_end_label), insn); -+ if (TARGET_MB_64) -+ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn); -+ else -+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn); - JUMP_LABEL (jump) = div_end_label; - LABEL_NUSES (div_end_label) = 1; - emit_barrier (); -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 5f30b8ac195..ac4ea43a706 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -888,10 +888,17 @@ do { \ - /* We do this to save a few 10s of code space that would be taken up - by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION - definition in crtstuff.c. */ -+#ifdef __arch64__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm ( SECTION_OP "\n" \ -+ "\tbrealid r15, " #FUNC "\n\t nop\n" \ -+ TEXT_SECTION_ASM_OP); -+#else - #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ - asm ( SECTION_OP "\n" \ - "\tbrlid r15, " #FUNC "\n\t nop\n" \ - TEXT_SECTION_ASM_OP); -+#endif - - /* We need to group -lm as well, since some Newlib math functions - reference __errno! */ -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 4e5d21a1f4c..5a950b49591 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -527,6 +527,15 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "floatdidf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (float:DF (match_operand:DI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dbl\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] -@@ -1299,7 +1308,7 @@ - (define_insn "movdi_long_int" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d") - (match_operand:DI 1 "general_operand" "i"))] -- "" -+ "TARGET_MB_64" - "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -1582,7 +1591,7 @@ - return "ll%i1\t%0,%1"; - case 3: - { -- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; -+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; - } - case 5: - return "sl%i0\t%1,%0"; -@@ -2371,9 +2380,9 @@ else - - (define_insn "long_branch_compare" - [(set (pc) -- (if_then_else (match_operator 0 "cmp_op" -- [(match_operand 1 "register_operand" "d") -- (match_operand 2 "register_operand" "d") -+ (if_then_else (match_operator:DI 0 "cmp_op" -+ [(match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d") - ]) - (label_ref (match_operand 3)) - (pc))) -@@ -2495,6 +2504,20 @@ else - ;;---------------------------------------------------------------- - ;; Unconditional branches - ;;---------------------------------------------------------------- -+(define_insn "jump_64" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "TARGET_MB_64" -+ { -+ if (GET_CODE (operands[0]) == REG) -+ return "brea%?\t%0"; -+ else -+ return "breai%?\t%l0"; -+ } -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "jump" - [(set (pc) - (label_ref (match_operand 0 "" "")))] -@@ -2540,17 +2563,25 @@ else - { - //gcc_assert (GET_MODE (operands[0]) == Pmode); - -- if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) -- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); -- else -- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); -+ if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) { -+ if (!TARGET_MB_64) -+ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); -+ else -+ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); -+ } -+ else { -+ if (!TARGET_MB_64) -+ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); -+ else -+ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); -+ } - DONE; - } - ) - - (define_insn "tablejump_internal1" - [(set (pc) -- (match_operand 0 "register_operand" "d")) -+ (match_operand:SI 0 "register_operand" "d")) - (use (label_ref (match_operand 1 "" "")))] - "" - "bra%?\t%0 " -@@ -2558,11 +2589,21 @@ else - (set_attr "mode" "none") - (set_attr "length" "4")]) - -+(define_insn "tablejump_internal2" -+ [(set (pc) -+ (match_operand:DI 0 "register_operand" "d")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "TARGET_MB_64" -+ "bra%?\t%0 " -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_expand "tablejump_internal3" - [(parallel [(set (pc) -- (plus (match_operand 0 "register_operand" "d") -- (label_ref (match_operand:SI 1 "" "")))) -- (use (label_ref (match_dup 1)))])] -+ (plus:SI (match_operand:SI 0 "register_operand" "d") -+ (label_ref:SI (match_operand:SI 1 "" "")))) -+ (use (label_ref:SI (match_dup 1)))])] - "" - "" - ) -@@ -2593,6 +2634,23 @@ else - "" - ) - -+(define_insn "" -+ [(set (pc) -+ (plus:DI (match_operand:DI 0 "register_operand" "d") -+ (label_ref:DI (match_operand 1 "" "")))) -+ (use (label_ref:DI (match_dup 1)))] -+ "TARGET_MB_64 && NEXT_INSN (as_a (operands[1])) != 0 -+ && GET_CODE (PATTERN (NEXT_INSN (as_a (operands[1])))) == ADDR_DIFF_VEC -+ && flag_pic" -+ { -+ output_asm_insn ("addlk\t%0,%0,r20",operands); -+ return "bra%?\t%0"; -+} -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ -+ - ;;---------------------------------------------------------------- - ;; Function prologue/epilogue and stack allocation - ;;---------------------------------------------------------------- -@@ -3101,7 +3159,7 @@ else - ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference - ;; between "mfs" and "addik" instructions. - (define_insn "set_got" -- [(set (match_operand:SI 0 "register_operand" "=r") -+ [(set (match_operand 0 "register_operand" "=r") - (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))] - "" - "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" -diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S -index ec797e1bf17..15ebe68c277 100644 ---- a/libgcc/config/microblaze/crti.S -+++ b/libgcc/config/microblaze/crti.S -@@ -33,11 +33,32 @@ - .section .init, "ax" - .global __init - -+#ifdef __arch64__ - .weak _stack -- .set _stack, 0xffffffff -+ .set _stack, 0xffffffffffffffff - .weak _stack_end - .set _stack_end, 0 - -+ .align 3 -+__init: -+ addlik r1, r1, -32 -+ sl r15, r0, r1 -+ addlik r11, r0, _stack -+ mts rshr, r11 -+ addlik r11, r0, _stack_end -+ mts rslr, r11 -+ -+ .section .fini, "ax" -+ .global __fini -+ .align 3 -+__fini: -+ addlik r1, r1, -32 -+ sl r15, r0, r1 -+#else -+ .weak _stack -+ .set _stack, 0xffffffff -+ .weak _stack_end -+ .set _stack_end, 0 - .align 2 - __init: - addik r1, r1, -16 -@@ -53,3 +74,4 @@ __init: - __fini: - addik r1, r1, -16 - sw r15, r0, r1 -+#endif -diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S -index 977b43b9436..9de3d4de13c 100644 ---- a/libgcc/config/microblaze/crtn.S -+++ b/libgcc/config/microblaze/crtn.S -@@ -29,7 +29,19 @@ - .section .note.GNU-stack,"",%progbits - .previous - #endif -+#ifdef __arch64__ -+ .section .init, "ax" -+ ll r15, r0, r1 -+ addlik r1, r1, 32 -+ rtsd r15, 8 -+ nop - -+ .section .fini, "ax" -+ ll r15, r0, r1 -+ addlik r1, r1, 32 -+ rtsd r15, 8 -+ nop -+#else - .section .init, "ax" - lw r15, r0, r1 - rtsd r15, 8 -@@ -39,3 +51,4 @@ - lw r15, r0, r1 - rtsd r15, 8 - addik r1, r1, 16 -+#endif --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch deleted file mode 100644 index 7bd3001d..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 80c16e39bdf8643184c353e34f146dc8601c2c1e Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Tue, 9 Oct 2018 10:07:08 +0530 -Subject: [PATCH 34/53] -Added double arith instructions -Fixed prologue stack - pointer decrement issue - ---- - gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++---- - gcc/config/microblaze/t-microblaze | 7 +++ - 2 files changed, 76 insertions(+), 9 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 5a950b49591..5506aee7be5 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -527,6 +527,66 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "fix_truncsfsi2" -+ [(set (match_operand:SI 0 "register_operand" "=d") -+ (fix:SI (match_operand:SF 1 "register_operand" "d")))] -+ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" -+ "fint\t%0,%1" -+ [(set_attr "type" "fint") -+ (set_attr "mode" "SF") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "adddf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (plus:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dadd\t%0,%1,%2" -+ [(set_attr "type" "fadd") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+(define_insn "subdf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (minus:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "drsub\t%0,%2,%1" -+ [(set_attr "type" "frsub") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+(define_insn "muldf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (mult:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dmul\t%0,%1,%2" -+ [(set_attr "type" "fmul") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+(define_insn "divdf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (div:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "ddiv\t%0,%2,%1" -+ [(set_attr "type" "fdiv") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "sqrtdf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dsqrt\t%0,%1" -+ [(set_attr "type" "fsqrt") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "register_operand" "=d") - (float:DF (match_operand:DI 1 "register_operand" "d")))] -@@ -536,13 +596,13 @@ - (set_attr "mode" "DF") - (set_attr "length" "4")]) - --(define_insn "fix_truncsfsi2" -- [(set (match_operand:SI 0 "register_operand" "=d") -- (fix:SI (match_operand:SF 1 "register_operand" "d")))] -- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" -- "fint\t%0,%1" -- [(set_attr "type" "fint") -- (set_attr "mode" "SF") -+(define_insn "floatdfdi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (float:DI (match_operand:DF 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dlong\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DI") - (set_attr "length" "4")]) - - ;;---------------------------------------------------------------- -@@ -660,8 +720,8 @@ - "TARGET_MB_64" - "@ - rsubl\t%0,%2,%1 -- addik\t%0,%z1,-%2 -- addik\t%0,%z1,-%2" -+ addlik\t%0,%z1,-%2 -+ addlik\t%0,%z1,-%2" - [(set_attr "type" "arith,no_delay_arith,no_delay_arith") - (set_attr "mode" "DI") - (set_attr "length" "4,4,4")]) -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index 47b869b9303..3522afd4831 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -1,6 +1,13 @@ - MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high - MULTILIB_DIRNAMES = m64 bs le m mh - MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *m64 -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift -+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul -+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high -+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high - MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch deleted file mode 100644 index 89018aae..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 455216291580ca22767433eec11941c5f2471892 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Fri, 12 Oct 2018 16:07:36 +0530 -Subject: [PATCH 35/53] Fixed the issue in the delay slot with swap - instructions - ---- - gcc/config/microblaze/microblaze.md | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 5506aee7be5..4a372f8fd3f 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -443,6 +443,9 @@ - (bswap:SI (match_operand:SI 1 "register_operand" "r")))] - "TARGET_REORDER" - "swapb %0, %1" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "4")] - ) - - (define_insn "bswaphi2" -@@ -451,6 +454,9 @@ - "TARGET_REORDER" - "swapb %0, %1 - swaph %0, %0" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "8")] - ) - - ;;---------------------------------------------------------------- --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch deleted file mode 100644 index 0c27d69f..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch +++ /dev/null @@ -1,256 +0,0 @@ -From b8c468f1bd467213083b59b54af100ee0c6dea9e Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Sat, 13 Oct 2018 21:12:43 +0530 -Subject: [PATCH 36/53] Fixed the load store issue with the 32bit arith - libraries - ---- - libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++- - libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++- - libgcc/config/microblaze/mulsi3.S | 3 +++ - libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++- - libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++- - 5 files changed, 98 insertions(+), 4 deletions(-) - -diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S -index 14829ec6701..b464deed481 100644 ---- a/libgcc/config/microblaze/divsi3.S -+++ b/libgcc/config/microblaze/divsi3.S -@@ -41,6 +41,17 @@ - .globl __divsi3 - .ent __divsi3 - .type __divsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__divsi3: -+ .frame r1,0,r15 -+ -+ ADDIK r1,r1,-32 -+ SLI r28,r1,0 -+ SLI r29,r1,8 -+ SLI r30,r1,16 -+ SLI r31,r1,24 -+#else - __divsi3: - .frame r1,0,r15 - -@@ -49,7 +60,7 @@ __divsi3: - SWI r29,r1,4 - SWI r30,r1,8 - SWI r31,r1,12 -- -+#endif - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQI r5,$LaResult_Is_Zero # Result is Zero - BGEID r5,$LaR5_Pos -@@ -89,6 +100,17 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - OR r3,r0,r0 # set result to 0 -+#ifdef __arch64__ -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r28,r1,0 -+ LLI r29,r1,8 -+ LLI r30,r1,16 -+ LLI r31,r1,24 -+ ADDLIK r1,r1,32 -+ RTSD r15,8 -+ NOP -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - LWI r28,r1,0 -@@ -97,6 +119,7 @@ $LaRETURN_HERE: - LWI r31,r1,12 - RTSD r15,8 - ADDIK r1,r1,16 -+#endif - .end __divsi3 - .size __divsi3, . - __divsi3 - -diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S -index b8f2e37809d..e0fbd91e766 100644 ---- a/libgcc/config/microblaze/modsi3.S -+++ b/libgcc/config/microblaze/modsi3.S -@@ -41,6 +41,17 @@ - .globl __modsi3 - .ent __modsi3 - .type __modsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__modsi3: -+ .frame r1,0,r15 -+ -+ addlik r1,r1,-32 -+ sli r28,r1,0 -+ sli r29,r1,8 -+ sli r30,r1,16 -+ sli r31,r1,24 -+#else - __modsi3: - .frame r1,0,r15 - -@@ -49,6 +60,7 @@ __modsi3: - swi r29,r1,4 - swi r30,r1,8 - swi r31,r1,12 -+#endif - - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQI r5,$LaResult_Is_Zero # Result is Zero -@@ -88,6 +100,18 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - or r3,r0,r0 # set result to 0 [Both mod as well as div are 0] -+ -+#ifdef __arch64__ -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r28,r1,0 -+ lli r29,r1,8 -+ lli r30,r1,16 -+ lli r31,r1,24 -+ addik r1,r1,32 -+ rtsd r15,8 -+ nop -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - lwi r28,r1,0 -@@ -95,7 +119,7 @@ $LaRETURN_HERE: - lwi r30,r1,8 - lwi r31,r1,12 - rtsd r15,8 -- addik r1,r1,16 -+#endif - .end __modsi3 - .size __modsi3, . - __modsi3 - -diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S -index f48fcf8270c..657668ef826 100644 ---- a/libgcc/config/microblaze/mulsi3.S -+++ b/libgcc/config/microblaze/mulsi3.S -@@ -41,6 +41,9 @@ - .globl __mulsi3 - .ent __mulsi3 - .type __mulsi3,@function -+#ifdef __arch64__ -+ .align 3 -+#endif - __mulsi3: - .frame r1,0,r15 - add r3,r0,r0 -diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S -index 2c321f94b09..fc6a4b5a248 100644 ---- a/libgcc/config/microblaze/udivsi3.S -+++ b/libgcc/config/microblaze/udivsi3.S -@@ -41,6 +41,16 @@ - .globl __udivsi3 - .ent __udivsi3 - .type __udivsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__udivsi3: -+ .frame r1,0,r15 -+ -+ ADDLIK r1,r1,-24 -+ SLI r29,r1,0 -+ SLI r30,r1,8 -+ SLI r31,r1,16 -+#else - __udivsi3: - .frame r1,0,r15 - -@@ -48,7 +58,7 @@ __udivsi3: - SWI r29,r1,0 - SWI r30,r1,4 - SWI r31,r1,8 -- -+#endif - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQID r5,$LaResult_Is_Zero # Result is Zero - ADDIK r30,r0,0 # Clear mod -@@ -98,6 +108,17 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - OR r3,r0,r0 # set result to 0 -+ -+#ifdef __arch64__ -+$LaRETURN_HERE: -+ # Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r29,r1,0 -+ LLI r30,r1,8 -+ LLI r31,r1,16 -+ ADDIK r1,r1,24 -+ RTSD r15,8 -+ NOP -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - LWI r29,r1,0 -@@ -105,5 +126,6 @@ $LaRETURN_HERE: - LWI r31,r1,8 - RTSD r15,8 - ADDIK r1,r1,12 -+#endif - .end __udivsi3 - .size __udivsi3, . - __udivsi3 -diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S -index fbe942dc5f2..b68ba7a5ea6 100644 ---- a/libgcc/config/microblaze/umodsi3.S -+++ b/libgcc/config/microblaze/umodsi3.S -@@ -41,6 +41,16 @@ - .globl __umodsi3 - .ent __umodsi3 - .type __umodsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__umodsi3: -+ .frame r1,0,r15 -+ -+ addik r1,r1,-24 -+ swi r29,r1,0 -+ swi r30,r1,8 -+ swi r31,r1,16 -+#else - __umodsi3: - .frame r1,0,r15 - -@@ -48,7 +58,7 @@ __umodsi3: - swi r29,r1,0 - swi r30,r1,4 - swi r31,r1,8 -- -+#endif - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQId r5,$LaResult_Is_Zero # Result is Zero - ADDIK r3,r0,0 # Clear div -@@ -101,6 +111,17 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - or r3,r0,r0 # set result to 0 -+ -+#ifdef __arch64__ -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r29,r1,0 -+ lli r30,r1,8 -+ lli r31,r1,16 -+ addlik r1,r1,24 -+ rtsd r15,8 -+ nop -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - lwi r29,r1,0 -@@ -108,5 +129,6 @@ $LaRETURN_HERE: - lwi r31,r1,8 - rtsd r15,8 - addik r1,r1,12 -+#endif - .end __umodsi3 - .size __umodsi3, . - __umodsi3 --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch deleted file mode 100644 index 2eab03ec..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 2bc476e64f1bacc27874c152340c004c17bfd942 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Mon, 15 Oct 2018 12:00:10 +0530 -Subject: [PATCH 37/53] extending the Dwarf support to 64bit Microblaze - ---- - gcc/config/microblaze/microblaze.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index ac4ea43a706..56dfc2a3824 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; - /* Use DWARF 2 debugging information by default. */ - #define DWARF2_DEBUGGING_INFO 1 - #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG --#define DWARF2_ADDR_SIZE 4 -+#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4) - - /* Target machine storage layout */ - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch deleted file mode 100644 index 4d6be758..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 1e0eaa1330f24d4989af6326ce1af4f613ea0d89 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Tue, 16 Oct 2018 07:55:46 +0530 -Subject: [PATCH 38/53] fixing the typo errors in umodsi3 file - ---- - libgcc/config/microblaze/umodsi3.S | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S -index b68ba7a5ea6..03be6df1fc6 100644 ---- a/libgcc/config/microblaze/umodsi3.S -+++ b/libgcc/config/microblaze/umodsi3.S -@@ -47,9 +47,9 @@ __umodsi3: - .frame r1,0,r15 - - addik r1,r1,-24 -- swi r29,r1,0 -- swi r30,r1,8 -- swi r31,r1,16 -+ sli r29,r1,0 -+ sli r30,r1,8 -+ sli r31,r1,16 - #else - __umodsi3: - .frame r1,0,r15 --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch deleted file mode 100644 index 1a5a0ef7..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 7dbdc5ba78c9237b0a367ca61f448cf3a0277ea6 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Wed, 17 Oct 2018 16:56:14 +0530 -Subject: [PATCH 39/53] fixing the 32bit LTO related issue9(1014024) - ---- - gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- - 1 file changed, 14 insertions(+), 10 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 56dfc2a3824..c48b6de0d58 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; - #define WORD_REGISTER_OPERATIONS 1 - - #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND --/* --#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -- if (GET_MODE_CLASS (MODE) == MODE_INT \ -- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ -- (MODE) = TARGET_MB_64 ? DImode : SImode; --*/ -+ -+#ifndef __arch64__ -+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -+ if (GET_MODE_CLASS (MODE) == MODE_INT \ -+ && GET_MODE_SIZE (MODE) < 4) \ -+ (MODE) = SImode; -+#endif -+ - /* Standard register usage. */ - - /* On the MicroBlaze, we have 32 integer registers */ -@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info; - - #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS - -+#ifdef __aarch64__ - #define LIBCALL_VALUE(MODE) \ - gen_rtx_REG (MODE,GP_RETURN) -- --/*#define LIBCALL_VALUE(MODE) \ -+#else -+#define LIBCALL_VALUE(MODE) \ - gen_rtx_REG ( \ - ((GET_MODE_CLASS (MODE) != MODE_INT \ - || GET_MODE_SIZE (MODE) >= 4) \ - ? (MODE) \ - : SImode), GP_RETURN) --*/ -+#endif -+ - /* 1 if N is a possible register number for a function value. - On the MicroBlaze, R2 R3 are the only register thus used. - Currently, R2 are only implemented here (C has no complex type) */ -@@ -518,7 +522,7 @@ typedef struct microblaze_args - /* 4 insns + 2 words of data. */ - #define TRAMPOLINE_SIZE (6 * 4) - --#define TRAMPOLINE_ALIGNMENT 64 -+#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32) - - #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch deleted file mode 100644 index 7c6f9008..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch +++ /dev/null @@ -1,25 +0,0 @@ -From a21a41a0c574b807c7e7edaa7051a0f7395d8142 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Fri, 19 Oct 2018 14:26:25 +0530 -Subject: [PATCH 40/53] Fixed the missing stack adjustment in prologue of - modsi3 function - ---- - libgcc/config/microblaze/modsi3.S | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S -index e0fbd91e766..3ec17685e51 100644 ---- a/libgcc/config/microblaze/modsi3.S -+++ b/libgcc/config/microblaze/modsi3.S -@@ -119,6 +119,7 @@ $LaRETURN_HERE: - lwi r30,r1,8 - lwi r31,r1,12 - rtsd r15,8 -+ addik r1,r1,16 - #endif - .end __modsi3 - .size __modsi3, . - __modsi3 --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch deleted file mode 100644 index 9cec7be9..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 5f799ea01bae0573a44f3fefa825861e99f4e30a Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 24 Oct 2018 18:31:04 +0530 -Subject: [PATCH 41/53] [Patch,Microblaze] : corrected SPN for dlong - instruction mapping. - ---- - gcc/config/microblaze/microblaze.md | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 4a372f8fd3f..5a964e70d1f 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -602,9 +602,9 @@ - (set_attr "mode" "DF") - (set_attr "length" "4")]) - --(define_insn "floatdfdi2" -+(define_insn "fix_truncdfdi2" - [(set (match_operand:DI 0 "register_operand" "=d") -- (float:DI (match_operand:DF 1 "register_operand" "d")))] -+ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] - "TARGET_MB_64" - "dlong\t%0,%1" - [(set_attr "type" "fcvt") --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch deleted file mode 100644 index 8836d0e7..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 9c37b9690ec2c6290095209c039725f235537379 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Thu, 29 Nov 2018 17:55:08 +0530 -Subject: [PATCH 42/53] fixing the long & long long mingw toolchain issue - ---- - gcc/config/microblaze/constraints.md | 2 +- - gcc/config/microblaze/microblaze.md | 8 ++++---- - 2 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index 0ced155340d..3f9805dfe0a 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -55,7 +55,7 @@ - (define_constraint "K" - "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." - (and (match_code "const_int") -- (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) -+ (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) - - - ;; Define floating point constraints -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 5a964e70d1f..f509bd5e665 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -648,8 +648,8 @@ - if (TARGET_MB_64) - { - if (GET_CODE (operands[2]) == CONST_INT && -- INTVAL(operands[2]) < (long)-549755813888 && -- INTVAL(operands[2]) > (long)549755813887) -+ INTVAL(operands[2]) < (long long)-549755813888 && -+ INTVAL(operands[2]) > (long long)549755813887) - FAIL; - } - }) -@@ -1264,7 +1264,7 @@ - (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] - "TARGET_MB_64 && (register_operand (operands[0], DImode) && - (GET_CODE (operands[1]) == CONST_INT && -- (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" -+ (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" - "@ - addlk\t%0,r0,r0\t - addlik\t%0,r0,%1\t #N1 %X1 -@@ -1298,7 +1298,7 @@ - case 1: - case 2: - if (GET_CODE (operands[1]) == CONST_INT && -- (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) -+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) - return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; - else - return "addlik\t%0,r0,%1"; --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch deleted file mode 100644 index c8caff29..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 0ed24f5a2e6e47f5d13896793ab2c6ea89e8c8e6 Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Thu, 14 Mar 2019 18:11:04 +0530 -Subject: [PATCH 43/53] Fix the MB-64 bug of handling QI objects - ---- - gcc/config/microblaze/microblaze.md | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index f509bd5e665..27436c0f660 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2345,11 +2345,11 @@ else - - (define_insn "branch_zero_64" - [(set (pc) -- (if_then_else (match_operator:SI 0 "ordered_comparison_operator" -+ (if_then_else (match_operator 0 "ordered_comparison_operator" - [(match_operand:SI 1 "register_operand" "d") - (const_int 0)]) -- (match_operand:SI 2 "pc_or_label_operand" "") -- (match_operand:SI 3 "pc_or_label_operand" ""))) -+ (match_operand 2 "pc_or_label_operand" "") -+ (match_operand 3 "pc_or_label_operand" ""))) - ] - "TARGET_MB_64" - { -@@ -2365,11 +2365,11 @@ else - - (define_insn "long_branch_zero" - [(set (pc) -- (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand 1 "register_operand" "d") -+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand" "d") - (const_int 0)]) -- (match_operand 2 "pc_or_label_operand" "") -- (match_operand 3 "pc_or_label_operand" ""))) -+ (match_operand:DI 2 "pc_or_label_operand" "") -+ (match_operand:DI 3 "pc_or_label_operand" ""))) - ] - "TARGET_MB_64" - { --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch deleted file mode 100644 index e0d7df3d..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch +++ /dev/null @@ -1,87 +0,0 @@ -From e8286e00f939486dde52e9475bc9cca0aa025a42 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Fri, 29 Mar 2019 12:08:39 +0530 -Subject: [PATCH 44/53] [Patch,Microblaze] : We will check the possibility of - peephole2 optimization,if we can then we will fix the compiler issue. - ---- - gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------ - 1 file changed, 38 insertions(+), 25 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 27436c0f660..4b9acddb1f1 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -882,31 +882,44 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - --(define_peephole2 -- [(set (match_operand:SI 0 "register_operand") -- (fix:SI (match_operand:SF 1 "register_operand"))) -- (set (pc) -- (if_then_else (match_operator 2 "ordered_comparison_operator" -- [(match_operand:SI 3 "register_operand") -- (match_operand:SI 4 "arith_operand")]) -- (label_ref (match_operand 5)) -- (pc)))] -- "TARGET_HARD_FLOAT && !TARGET_MB_64" -- [(set (match_dup 1) (match_dup 3))] -- -- { -- rtx condition; -- rtx cmp_op0 = operands[3]; -- rtx cmp_op1 = operands[4]; -- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -- -- emit_insn (gen_cstoresf4 (comp_reg, operands[2], -- gen_rtx_REG (SFmode, REGNO (cmp_op0)), -- gen_rtx_REG (SFmode, REGNO (cmp_op1)))); -- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, operands[5])); -- } --) -+;; peephole2 optimization will be done only if fint and if-then-else -+;; are dependent.added condition for the same. -+;; if they are dependent then gcc is giving "flow control insn inside a basic block" -+;; testcase: -+;; volatile float vec = 1.0; -+;; volatile int ci = 2; -+;; register int cj = (int)(vec); -+;;// ci=cj; -+;;// if (ci <0) { -+;; if (cj < 0) { -+;; ci = 0; -+;; } -+;; commenting for now.we will check the possibility of this optimization later -+ -+;;(define_peephole2 -+;; [(set (match_operand:SI 0 "register_operand") -+;; (fix:SI (match_operand:SF 1 "register_operand"))) -+;; (set (pc) -+;; (if_then_else (match_operator 2 "ordered_comparison_operator" -+;; [(match_operand:SI 3 "register_operand") -+;; (match_operand:SI 4 "arith_operand")]) -+;; (label_ref (match_operand 5)) -+;; (pc)))] -+;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" -+;; [(set (match_dup 1) (match_dup 3))] -+;; { -+;; rtx condition; -+;; rtx cmp_op0 = operands[3]; -+;; rtx cmp_op1 = operands[4]; -+;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+;; -+;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], -+;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), -+;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); -+;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -+;; emit_jump_insn (gen_condjump (condition, operands[5])); -+;; } -+;;) - - ;;---------------------------------------------------------------- - ;; Negation and one's complement --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch deleted file mode 100644 index 770d0f70..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch +++ /dev/null @@ -1,466 +0,0 @@ -From 29c33e35373d7dc52e43162dce38a3ec0e350db3 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 17 Apr 2019 12:36:16 +0530 -Subject: [PATCH 45/53] [Patch,MicroBlaze]: fixed typos in mul,div and mod - assembly files. - ---- - libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++---- - libgcc/config/microblaze/modsi3.S | 40 ++++++++++++++++++--- - libgcc/config/microblaze/mulsi3.S | 33 ++++++++++++++++- - libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++--- - libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++--- - 5 files changed, 212 insertions(+), 20 deletions(-) - -diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S -index b464deed481..ceeed6be1f4 100644 ---- a/libgcc/config/microblaze/divsi3.S -+++ b/libgcc/config/microblaze/divsi3.S -@@ -46,7 +46,7 @@ - __divsi3: - .frame r1,0,r15 - -- ADDIK r1,r1,-32 -+ ADDLIK r1,r1,-32 - SLI r28,r1,0 - SLI r29,r1,8 - SLI r30,r1,16 -@@ -61,13 +61,23 @@ __divsi3: - SWI r30,r1,8 - SWI r31,r1,12 - #endif -- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -- BEQI r5,$LaResult_Is_Zero # Result is Zero -- BGEID r5,$LaR5_Pos -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero -+ BEAGEID r5,$LaR5_Pos -+#else -+ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEQI r5,$LaResult_Is_Zero # Result is Zero -+ BGEID r5,$LaR5_Pos -+#endif - XOR r28,r5,r6 # Get the sign of the result - RSUBI r5,r5,0 # Make r5 positive - $LaR5_Pos: -- BGEI r6,$LaR6_Pos -+#ifdef __arch64__ -+ BEAGEI r6,$LaR6_Pos -+#else -+ BGEI r6,$LaR6_Pos -+#endif - RSUBI r6,r6,0 # Make r6 positive - $LaR6_Pos: - ADDIK r30,r0,0 # Clear mod -@@ -76,26 +86,51 @@ $LaR6_Pos: - - # First part try to find the first '1' in the r5 - $LaDIV0: -- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+#ifdef __arch64__ -+ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+#else -+ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+#endif - $LaDIV1: - ADD r5,r5,r5 # left shift logical r5 -+#ifdef __arch64__ -+ BEAGTID r5,$LaDIV1 -+#else - BGTID r5,$LaDIV1 -+#endif - ADDIK r29,r29,-1 - $LaDIV2: - ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry - ADDC r30,r30,r30 # Move that bit into the Mod register - RSUB r31,r6,r30 # Try to subtract (r30 a r6) -+#ifdef __arch64__ -+ BEALTI r31,$LaMOD_TOO_SMALL -+#else - BLTI r31,$LaMOD_TOO_SMALL -+#endif - OR r30,r0,r31 # Move the r31 to mod since the result was positive - ADDIK r3,r3,1 - $LaMOD_TOO_SMALL: - ADDIK r29,r29,-1 -+#ifdef __arch64__ -+ BEAEQi r29,$LaLOOP_END -+#else - BEQi r29,$LaLOOP_END -+#endif - ADD r3,r3,r3 # Shift in the '1' into div -+#ifdef __arch64__ -+ BREAI $LaDIV2 # Div2 -+#else - BRI $LaDIV2 # Div2 -+#endif - $LaLOOP_END: -+#ifdef __arch64__ -+ BEAGEI r28,$LaRETURN_HERE -+ BREAID $LaRETURN_HERE -+#else - BGEI r28,$LaRETURN_HERE - BRID $LaRETURN_HERE -+#endif - RSUBI r3,r3,0 # Negate the result - $LaDiv_By_Zero: - $LaResult_Is_Zero: -diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S -index 3ec17685e51..637b06c09a3 100644 ---- a/libgcc/config/microblaze/modsi3.S -+++ b/libgcc/config/microblaze/modsi3.S -@@ -62,40 +62,72 @@ __modsi3: - swi r31,r1,12 - #endif - -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero -+ BEAGEId r5,$LaR5_Pos -+#else - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQI r5,$LaResult_Is_Zero # Result is Zero - BGEId r5,$LaR5_Pos -+#endif - ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] - RSUBI r5,r5,0 # Make r5 positive - $LaR5_Pos: -- BGEI r6,$LaR6_Pos -+#ifdef __arch64__ -+ BEAGEI r6,$LaR6_Pos -+#else -+ BGEI r6,$LaR6_Pos -+#endif - RSUBI r6,r6,0 # Make r6 positive - $LaR6_Pos: - ADDIK r3,r0,0 # Clear mod - ADDIK r30,r0,0 # clear div -- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip -+#ifdef __arch64__ -+ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip - # the first bit search. -+#else -+ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip -+ # the first bit search. -+#endif - ADDIK r29,r0,32 # Initialize the loop count - # First part try to find the first '1' in the r5 - $LaDIV1: - ADD r5,r5,r5 # left shift logical r5 -- BGEID r5,$LaDIV1 # -+#ifdef __arch64__ -+ BEAGEID r5,$LaDIV1 # -+#else -+ BGEID r5,$LaDIV1 # -+#endif - ADDIK r29,r29,-1 - $LaDIV2: - ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry - ADDC r3,r3,r3 # Move that bit into the Mod register - rSUB r31,r6,r3 # Try to subtract (r30 a r6) -+#ifdef __arch64__ -+ BEALTi r31,$LaMOD_TOO_SMALL -+#else - BLTi r31,$LaMOD_TOO_SMALL -+#endif - OR r3,r0,r31 # Move the r31 to mod since the result was positive - ADDIK r30,r30,1 - $LaMOD_TOO_SMALL: - ADDIK r29,r29,-1 -+#ifdef __arch64__ -+ BEAEQi r29,$LaLOOP_END -+ ADD r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BEAGEI r28,$LaRETURN_HERE -+ BREAId $LaRETURN_HERE -+#else - BEQi r29,$LaLOOP_END - ADD r30,r30,r30 # Shift in the '1' into div - BRI $LaDIV2 # Div2 - $LaLOOP_END: - BGEI r28,$LaRETURN_HERE - BRId $LaRETURN_HERE -+#endif - rsubi r3,r3,0 # Negate the result - $LaDiv_By_Zero: - $LaResult_Is_Zero: -@@ -108,7 +140,7 @@ $LaRETURN_HERE: - lli r29,r1,8 - lli r30,r1,16 - lli r31,r1,24 -- addik r1,r1,32 -+ addlik r1,r1,32 - rtsd r15,8 - nop - #else -diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S -index 657668ef826..6be75dc95e8 100644 ---- a/libgcc/config/microblaze/mulsi3.S -+++ b/libgcc/config/microblaze/mulsi3.S -@@ -43,7 +43,37 @@ - .type __mulsi3,@function - #ifdef __arch64__ - .align 3 --#endif -+__mulsi3: -+ .frame r1,0,r15 -+ add r3,r0,r0 -+ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero -+ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero -+ BEAGEId r5,$L_R5_Pos -+ XOR r4,r5,r6 # Get the sign of the result -+ RSUBI r5,r5,0 # Make r5 positive -+$L_R5_Pos: -+ BEAGEI r6,$L_R6_Pos -+ RSUBI r6,r6,0 # Make r6 positive -+$L_R6_Pos: -+ breai $L1 -+$L2: -+ add r5,r5,r5 -+$L1: -+ srl r6,r6 -+ addc r7,r0,r0 -+ beaeqi r7,$L2 -+ beaneid r6,$L2 -+ add r3,r3,r5 -+ bealti r4,$L_NegateResult -+ rtsd r15,8 -+ nop -+$L_NegateResult: -+ rtsd r15,8 -+ rsub r3,r3,r0 -+$L_Result_Is_Zero: -+ rtsd r15,8 -+ addi r3,r0,0 -+#else - __mulsi3: - .frame r1,0,r15 - add r3,r0,r0 -@@ -74,5 +104,6 @@ $L_NegateResult: - $L_Result_Is_Zero: - rtsd r15,8 - addi r3,r0,0 -+#endif - .end __mulsi3 - .size __mulsi3, . - __mulsi3 -diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S -index fc6a4b5a248..f8ce88bd8b7 100644 ---- a/libgcc/config/microblaze/udivsi3.S -+++ b/libgcc/config/microblaze/udivsi3.S -@@ -59,52 +59,96 @@ __udivsi3: - SWI r30,r1,4 - SWI r31,r1,8 - #endif -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQID r5,$LaResult_Is_Zero # Result is Zero -+#else - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQID r5,$LaResult_Is_Zero # Result is Zero -+#endif - ADDIK r30,r0,0 # Clear mod - ADDIK r29,r0,32 # Initialize the loop count - - # Check if r6 and r5 are equal # if yes, return 1 - RSUB r18,r5,r6 -+#ifdef __arch64__ -+ BEAEQID r18,$LaRETURN_HERE -+#else - BEQID r18,$LaRETURN_HERE -+#endif - ADDIK r3,r0,1 - - # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 - XOR r18,r5,r6 -- BGEID r18,16 -+#ifdef __arch64__ -+ BEAGEID r18,16 -+#else -+ BGEID r18,16 -+#endif - ADD r3,r0,r0 # We would anyways clear r3 -+#ifdef __arch64__ -+ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater -+ BREAI $LCheckr6 -+ RSUB r18,r6,r5 # MICROBLAZEcmp -+ BEALTI r18,$LaRETURN_HERE -+#else - BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater - BRI $LCheckr6 - RSUB r18,r6,r5 # MICROBLAZEcmp - BLTI r18,$LaRETURN_HERE -- -+#endif - # If r6 [bit 31] is set, then return result as 1 - $LCheckr6: -- BGTI r6,$LaDIV0 -- BRID $LaRETURN_HERE -+#ifdef __arch64__ -+ BEAGTI r6,$LaDIV0 -+ BREAID $LaRETURN_HERE -+#else -+ BGTI r6,$LaDIV0 -+ BRID $LaRETURN_HERE -+#endif - ADDIK r3,r0,1 - - # First part try to find the first '1' in the r5 - $LaDIV0: -+#ifdef __arch64__ -+ BEALTI r5,$LaDIV2 -+#else - BLTI r5,$LaDIV2 -+#endif - $LaDIV1: - ADD r5,r5,r5 # left shift logical r5 -+#ifdef __arch64__ -+ BEAGTID r5,$LaDIV1 -+#else - BGTID r5,$LaDIV1 -+#endif - ADDIK r29,r29,-1 - $LaDIV2: - ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry - ADDC r30,r30,r30 # Move that bit into the Mod register - RSUB r31,r6,r30 # Try to subtract (r30 a r6) -+#ifdef __arch64__ -+ BEALTI r31,$LaMOD_TOO_SMALL -+#else - BLTI r31,$LaMOD_TOO_SMALL -+#endif - OR r30,r0,r31 # Move the r31 to mod since the result was positive - ADDIK r3,r3,1 - $LaMOD_TOO_SMALL: - ADDIK r29,r29,-1 -+#ifdef __arch64__ -+ BEAEQi r29,$LaLOOP_END -+ ADD r3,r3,r3 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+#else - BEQi r29,$LaLOOP_END - ADD r3,r3,r3 # Shift in the '1' into div - BRI $LaDIV2 # Div2 - $LaLOOP_END: - BRI $LaRETURN_HERE -+#endif - $LaDiv_By_Zero: - $LaResult_Is_Zero: - OR r3,r0,r0 # set result to 0 -@@ -115,7 +159,7 @@ $LaRETURN_HERE: - LLI r29,r1,0 - LLI r30,r1,8 - LLI r31,r1,16 -- ADDIK r1,r1,24 -+ ADDLIK r1,r1,24 - RTSD r15,8 - NOP - #else -diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S -index 03be6df1fc6..3be3658f7a2 100644 ---- a/libgcc/config/microblaze/umodsi3.S -+++ b/libgcc/config/microblaze/umodsi3.S -@@ -46,7 +46,7 @@ - __umodsi3: - .frame r1,0,r15 - -- addik r1,r1,-24 -+ addlik r1,r1,-24 - sli r29,r1,0 - sli r30,r1,8 - sli r31,r1,16 -@@ -59,27 +59,77 @@ __umodsi3: - swi r30,r1,4 - swi r31,r1,8 - #endif -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQId r5,$LaResult_Is_Zero # Result is Zero -+#else - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQId r5,$LaResult_Is_Zero # Result is Zero -+#endif - ADDIK r3,r0,0 # Clear div - ADDIK r30,r0,0 # clear mod - ADDIK r29,r0,32 # Initialize the loop count - - # Check if r6 and r5 are equal # if yes, return 0 - rsub r18,r5,r6 -- beqi r18,$LaRETURN_HERE - -+#ifdef __arch64__ -+ beaeqi r18,$LaRETURN_HERE -+#else -+ beqi r18,$LaRETURN_HERE -+#endif - # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 - xor r18,r5,r6 -+#ifdef __arch64__ -+ beageid r18,16 -+ addik r3,r5,0 -+ bealti r6,$LaRETURN_HERE -+ breai $LCheckr6 -+ rsub r18,r5,r6 # MICROBLAZEcmp -+ beagti r18,$LaRETURN_HERE -+#else - bgeid r18,16 - addik r3,r5,0 - blti r6,$LaRETURN_HERE - bri $LCheckr6 - rsub r18,r5,r6 # MICROBLAZEcmp - bgti r18,$LaRETURN_HERE -- -+#endif - # If r6 [bit 31] is set, then return result as r5-r6 - $LCheckr6: -+#ifdef __arch64__ -+ beagtid r6,$LaDIV0 -+ addik r3,r0,0 -+ addik r18,r0,0x7fffffff -+ and r5,r5,r18 -+ and r6,r6,r18 -+ breaid $LaRETURN_HERE -+ rsub r3,r6,r5 -+# First part: try to find the first '1' in the r5 -+$LaDIV0: -+ BEALTI r5,$LaDIV2 -+$LaDIV1: -+ ADD r5,r5,r5 # left shift logical r5 -+ BEAGEID r5,$LaDIV1 # -+ ADDIK r29,r29,-1 -+$LaDIV2: -+ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDC r3,r3,r3 # Move that bit into the Mod register -+ rSUB r31,r6,r3 # Try to subtract (r3 a r6) -+ BEALTi r31,$LaMOD_TOO_SMALL -+ OR r3,r0,r31 # Move the r31 to mod since the result was positive -+ ADDIK r30,r30,1 -+$LaMOD_TOO_SMALL: -+ ADDIK r29,r29,-1 -+ BEAEQi r29,$LaLOOP_END -+ ADD r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ or r3,r0,r0 # set result to 0 -+#else - bgtid r6,$LaDIV0 - addik r3,r0,0 - addik r18,r0,0x7fffffff -@@ -111,7 +161,7 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - or r3,r0,r0 # set result to 0 -- -+#endif - #ifdef __arch64__ - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch deleted file mode 100644 index 29a7b4eb..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch +++ /dev/null @@ -1,477 +0,0 @@ -From 39589348962a2e0453ad49118b6bc3dd8a7b1bb5 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 15:59:12 +0530 -Subject: [PATCH 46/53] [Patch, microblaze]: MB-64 removal of barrel-shift - instructions from default By default MB-64 is generatting - barrel-shift instructions. It has been removed from default. - Barrel-shift instructions will be generated only if barrel-shifter is - enabled. Similarly to double instructions as well. - - Signed-off-by :Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.cc | 2 +- - gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++-- - 2 files changed, 252 insertions(+), 19 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 7a08390a027..3ee3996a38d 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -3871,7 +3871,7 @@ microblaze_expand_divide (rtx operands[]) - emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); - - if (TARGET_MB_64) { -- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); -+ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); - emit_insn (gen_adddi3 (regt1, regt1, operands[2])); - } - else { -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 4b9acddb1f1..3695e9e101d 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -547,7 +547,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (plus:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dadd\t%0,%1,%2" - [(set_attr "type" "fadd") - (set_attr "mode" "DF") -@@ -557,7 +557,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (minus:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "drsub\t%0,%2,%1" - [(set_attr "type" "frsub") - (set_attr "mode" "DF") -@@ -567,7 +567,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (mult:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dmul\t%0,%1,%2" - [(set_attr "type" "fmul") - (set_attr "mode" "DF") -@@ -577,7 +577,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (div:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "ddiv\t%0,%2,%1" - [(set_attr "type" "fdiv") - (set_attr "mode" "DF") -@@ -587,7 +587,7 @@ - (define_insn "sqrtdf2" - [(set (match_operand:DF 0 "register_operand" "=d") - (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dsqrt\t%0,%1" - [(set_attr "type" "fsqrt") - (set_attr "mode" "DF") -@@ -596,7 +596,7 @@ - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "register_operand" "=d") - (float:DF (match_operand:DI 1 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dbl\t%0,%1" - [(set_attr "type" "fcvt") - (set_attr "mode" "DF") -@@ -605,7 +605,7 @@ - (define_insn "fix_truncdfdi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dlong\t%0,%1" - [(set_attr "type" "fcvt") - (set_attr "mode" "DI") -@@ -1299,6 +1299,34 @@ - (set_attr "mode" "DI") - (set_attr "length" "4")]) - -+(define_insn "*movdi_internal2_bshift" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") -+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ case 2: -+ if (GET_CODE (operands[1]) == CONST_INT && -+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) -+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ else -+ return "addlik\t%0,r0,%1"; -+ case 3: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 5: -+ case 6: -+ return "sl%i0\t%z1,%0"; -+ } -+ } -+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4,4,12,4,8,4,8")]) -+ - (define_insn "*movdi_internal2" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") - (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] -@@ -1312,7 +1340,15 @@ - case 2: - if (GET_CODE (operands[1]) == CONST_INT && - (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) -- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ { -+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("addlik\t%0,r0,%h1", operands); -+ output_asm_insn ("addlik\t%2,r0,32", operands); -+ output_asm_insn ("addlik\t%2,%2,-1", operands); -+ output_asm_insn ("beaneid\t%2,.-8", operands); -+ output_asm_insn ("addlk\t%0,%0,%0", operands); -+ return "addlik\t%0,%0,%j1 #li => la"; -+ } - else - return "addlik\t%0,r0,%1"; - case 3: -@@ -1387,7 +1423,7 @@ - (define_insn "movdi_long_int" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d") - (match_operand:DI 1 "general_operand" "i"))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -1654,6 +1690,33 @@ - ;; movdf_internal - ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT - ;; -+(define_insn "*movdf_internal_64_bshift" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") -+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ return "addlk\t%0,r0,r0"; -+ case 2: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 3: -+ { -+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; -+ } -+ case 5: -+ return "sl%i0\t%1,%0"; -+ } -+ gcc_unreachable (); -+ } -+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4,4,4,16,4,4")]) -+ - (define_insn "*movdf_internal_64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") - (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] -@@ -1670,7 +1733,13 @@ - return "ll%i1\t%0,%1"; - case 3: - { -- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; -+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("addlik\t%0,r0,%h1", operands); -+ output_asm_insn ("addlik\t%2,r0,32", operands); -+ output_asm_insn ("addlik\t%2,%2,-1", operands); -+ output_asm_insn ("beaneid\t%2,.-8", operands); -+ output_asm_insn ("addlk\t%0,%0,%0", operands); -+ return "addlik\t%0,%0,%j1 #li => la"; - } - case 5: - return "sl%i0\t%1,%0"; -@@ -1790,11 +1859,21 @@ - "TARGET_MB_64" - { - ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) --if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) - { - emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); - DONE; - } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) -+ { -+ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) -+ { -+ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); -+ DONE; -+ } - else - FAIL; - } -@@ -1804,7 +1883,7 @@ else - [(set (match_operand:DI 0 "register_operand" "=d,d") - (ashift:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:DI 2 "arith_operand" "I,d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "@ - bsllli\t%0,%1,%2 - bslll\t%0,%1,%2" -@@ -1812,6 +1891,51 @@ else - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")] - ) -+ -+(define_insn "ashldi3_const" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("orli\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "addlk\t%0,%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "20")] -+) -+ -+(define_insn "ashldi3_reg" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("andli\t%3,%2,31", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,r0,%1", operands); -+ /* Exit the loop if zero shift. */ -+ output_asm_insn ("beaeqid\t%3,.+24", operands); -+ /* Emit the loop. */ -+ output_asm_insn ("addlk\t%0,%0,r0", operands); -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "addlk\t%0,%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "28")] -+) -+ - ;; The following patterns apply when there is no barrel shifter present - - (define_insn "*ashlsi3_with_mul_delay" -@@ -1945,11 +2069,21 @@ else - "TARGET_MB_64" - { - ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) --if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) - { - emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); - DONE; - } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) -+ { -+ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) -+ { -+ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); -+ DONE; -+ } - else - FAIL; - } -@@ -1959,7 +2093,7 @@ else - [(set (match_operand:DI 0 "register_operand" "=d,d") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:DI 2 "arith_operand" "I,d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "@ - bslrai\t%0,%1,%2 - bslra\t%0,%1,%2" -@@ -1967,6 +2101,51 @@ else - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")] - ) -+ -+(define_insn "ashrdi3_const" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("orli\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srla\t%0,%0"; -+ } -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "20")] -+) -+ -+(define_insn "ashrdi3_reg" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("andli\t%3,%2,31", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,r0,%1", operands); -+ /* Exit the loop if zero shift. */ -+ output_asm_insn ("beaeqid\t%3,.+24", operands); -+ /* Emit the loop. */ -+ output_asm_insn ("addlk\t%0,%0,r0", operands); -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srla\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "28")] -+) -+ - (define_expand "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -@@ -2084,11 +2263,21 @@ else - "TARGET_MB_64" - { - ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) --if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) - { - emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); - DONE; - } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) -+ { -+ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) -+ { -+ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); -+ DONE; -+ } - else - FAIL; - } -@@ -2098,7 +2287,7 @@ else - [(set (match_operand:DI 0 "register_operand" "=d,d") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:DI 2 "arith_operand" "I,d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "@ - bslrli\t%0,%1,%2 - bslrl\t%0,%1,%2" -@@ -2107,6 +2296,50 @@ else - (set_attr "length" "4,4")] - ) - -+(define_insn "lshrdi3_const" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("orli\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srll\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "20")] -+) -+ -+(define_insn "lshrdi3_reg" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("andli\t%3,%2,31", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,r0,%1", operands); -+ /* Exit the loop if zero shift. */ -+ output_asm_insn ("beaeqid\t%3,.+24", operands); -+ /* Emit the loop. */ -+ output_asm_insn ("addlk\t%0,%0,r0", operands); -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srll\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "SI") -+ (set_attr "length" "28")] -+) -+ - (define_expand "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") -@@ -2233,7 +2466,7 @@ else - (eq:DI - (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" - "pcmpleq\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "DI") -@@ -2245,7 +2478,7 @@ else - (ne:DI - (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" - "pcmplne\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "DI") --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch deleted file mode 100644 index 774fad5a..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch +++ /dev/null @@ -1,107 +0,0 @@ -From e32334b0f8a4c9532975001ffab33e86469ea4e1 Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Fri, 23 Aug 2019 16:16:53 +0530 -Subject: [PATCH 47/53] Added new MB-64 single register arithmetic instructions - ---- - gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 3695e9e101d..85c1ab45994 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -654,6 +654,18 @@ - } - }) - -+(define_insn "adddi3_int" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (plus:DI (match_operand:DI 1 "register_operand" "%0") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ addlik\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")] -+) -+ - (define_insn "*adddi3_long" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (match_operand:DI 1 "register_operand" "%d,d") -@@ -719,6 +731,18 @@ - { - }") - -+(define_insn "subdi316imm" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (minus:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))" -+ "@ -+ addlik\t%0,-%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ -+ - (define_insn "subsidi3" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") -@@ -1015,6 +1039,17 @@ - ;; Logical - ;;---------------------------------------------------------------- - -+(define_insn "anddi3imm16" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (and:DI (match_operand:DI 1 "arith_operand" "%0") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ andli\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "anddi3" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") -@@ -1042,6 +1077,16 @@ - (set_attr "mode" "SI,SI,SI,SI") - (set_attr "length" "4,8,8,8")]) - -+(define_insn "iordi3imm16" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (ior:DI (match_operand:DI 1 "arith_operand" "%0") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ orli\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) - - (define_insn "iordi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") -@@ -1069,6 +1114,17 @@ - (set_attr "mode" "SI,SI,SI,SI") - (set_attr "length" "4,8,8,8")]) - -+(define_insn "xordi3imm16" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (xor:DI (match_operand:DI 1 "arith_operand" "%0") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ xorli\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "xordi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch deleted file mode 100644 index a442bf0f..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From f5f262b196de197b7e9ece8cc08c8715f953857f Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 26 Aug 2019 15:55:22 +0530 -Subject: [PATCH 48/53] [Patch,MicroBlaze] : Added support for 64 bit Immediate - values. - ---- - gcc/config/microblaze/constraints.md | 4 ++-- - gcc/config/microblaze/microblaze.md | 3 +-- - 2 files changed, 3 insertions(+), 4 deletions(-) - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index 3f9805dfe0a..91653f36f52 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -53,9 +53,9 @@ - (match_test "ival > 0 && ival < 0x10000"))) - - (define_constraint "K" -- "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." -+ "A constant in the range -9223372036854775808 to 9223372036854775807 (inclusive)." - (and (match_code "const_int") -- (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) -+ (match_test "ival > (long long)-9223372036854775808 && ival < (long long)9223372036854775807"))) - - - ;; Define floating point constraints -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 85c1ab45994..0ac6e1480e6 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1332,8 +1332,7 @@ - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") - (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] - "TARGET_MB_64 && (register_operand (operands[0], DImode) && -- (GET_CODE (operands[1]) == CONST_INT && -- (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" -+ (GET_CODE (operands[1]) == CONST_INT))" - "@ - addlk\t%0,r0,r0\t - addlik\t%0,r0,%1\t #N1 %X1 --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch deleted file mode 100644 index 5732000d..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch +++ /dev/null @@ -1,76 +0,0 @@ -From d45405d05a1f9079f7db86ba60dcd30d358613d4 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 16:06:10 +0530 -Subject: [PATCH 49/53] [Patch, microblaze]: Fix Compiler crash with - -freg-struct-return This patch fixes a bug in MB GCC regarding the - passing struct values in registers. Currently we are only handling SImode - With this patch all other modes are handled properly - - Signed-off-by :Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.cc | 11 ++++++++++- - gcc/config/microblaze/microblaze.h | 19 ------------------- - 2 files changed, 10 insertions(+), 20 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 3ee3996a38d..4668a81d060 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -3909,7 +3909,16 @@ microblaze_function_value (const_tree valtype, - const_tree func ATTRIBUTE_UNUSED, - bool outgoing ATTRIBUTE_UNUSED) - { -- return LIBCALL_VALUE (TYPE_MODE (valtype)); -+ return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN); -+} -+ -+#undef TARGET_LIBCALL_VALUE -+#define TARGET_LIBCALL_VALUE microblaze_libcall_value -+ -+rtx -+microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) -+{ -+ return gen_rtx_REG (mode, GP_RETURN); - } - - /* Implement TARGET_SCHED_ADJUST_COST. */ -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index c48b6de0d58..730ad87b13b 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe; - - #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND - --#ifndef __arch64__ --#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -- if (GET_MODE_CLASS (MODE) == MODE_INT \ -- && GET_MODE_SIZE (MODE) < 4) \ -- (MODE) = SImode; --#endif -- - /* Standard register usage. */ - - /* On the MicroBlaze, we have 32 integer registers */ -@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info; - - #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS - --#ifdef __aarch64__ --#define LIBCALL_VALUE(MODE) \ -- gen_rtx_REG (MODE,GP_RETURN) --#else --#define LIBCALL_VALUE(MODE) \ -- gen_rtx_REG ( \ -- ((GET_MODE_CLASS (MODE) != MODE_INT \ -- || GET_MODE_SIZE (MODE) >= 4) \ -- ? (MODE) \ -- : SImode), GP_RETURN) --#endif -- - /* 1 if N is a possible register number for a function value. - On the MicroBlaze, R2 R3 are the only register thus used. - Currently, R2 are only implemented here (C has no complex type) */ --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch deleted file mode 100644 index ed48daf7..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch +++ /dev/null @@ -1,50 +0,0 @@ -From a64afc59e82703f40d04d4d7126038811a195467 Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Wed, 8 May 2019 14:12:03 +0530 -Subject: [PATCH 50/53] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and - disable fivopts by default - -Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. - - * gcc/common/config/microblaze/microblaze-common.c - (microblaze_option_optimization_table): Disable fivopts by default. - -Signed-off-by: Nagaraju Mekala - Mahesh Bodapati -Conflicts: - gcc/common/config/microblaze/microblaze-common.c - -Conflicts: - gcc/common/config/microblaze/microblaze-common.c ---- - gcc/common/config/microblaze/microblaze-common.cc | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/gcc/common/config/microblaze/microblaze-common.cc b/gcc/common/config/microblaze/microblaze-common.cc -index 21b35f55b92..137332ded25 100644 ---- a/gcc/common/config/microblaze/microblaze-common.cc -+++ b/gcc/common/config/microblaze/microblaze-common.cc -@@ -24,7 +24,20 @@ - #include "common/common-target.h" - #include "common/common-target-def.h" - -+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ -+static const struct default_options microblaze_option_optimization_table[] = -+ { -+ /* Turn off ivopts by default. It messes up cse. -+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */ -+ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, -+ { OPT_LEVELS_NONE, 0, NULL, 0 } -+ }; -+ -+ - #undef TARGET_DEFAULT_TARGET_FLAGS - #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT - -+#undef TARGET_OPTION_OPTIMIZATION_TABLE -+#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table -+ - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch deleted file mode 100644 index b9575eac..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 09e10c513f8970f4d2402244b7ac69ecd33b4c04 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 16:35:00 +0530 -Subject: [PATCH 51/53] [Patch, microblaze]: Reducing Stack space for arguments - - Currently in Microblaze target stack space for arguments in register is being - allocated even if there are no arguments in the function. - This patch will optimize the extra 24 bytes that are being allocated. - - Signed-off-by :Nagaraju Mekala - :Ajit Agarwal ---- - gcc/config/microblaze/microblaze-protos.h | 1 + - gcc/config/microblaze/microblaze.cc | 130 ++++++++++++++++++++++ - gcc/config/microblaze/microblaze.h | 4 +- - 3 files changed, 133 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index 7f575c2adec..bd594699940 100644 ---- a/gcc/config/microblaze/microblaze-protos.h -+++ b/gcc/config/microblaze/microblaze-protos.h -@@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx); - extern int label_mentioned_p (rtx); - extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); - extern void microblaze_eh_return (rtx op0); -+int microblaze_reg_parm_stack_space(tree fun); - #endif /* RTX_CODE */ - - /* Declare functions in microblaze-c.cc. */ -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 4668a81d060..24ac215b6d5 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2081,6 +2081,136 @@ microblaze_must_save_register (int regno) - return 0; - } - -+static bool -+microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type) -+{ -+ int unsignedp; -+ rtx entry_parm; -+ -+ /* Catch errors. */ -+ if (type == NULL || type == error_mark_node) -+ return true; -+ -+ if (TREE_CODE (type) == POINTER_TYPE) -+ return true; -+ -+ /* Handle types with no storage requirement. */ -+ if (TYPE_MODE (type) == VOIDmode) -+ return false; -+ -+ /* Handle complex types. */ -+ if (TREE_CODE (type) == COMPLEX_TYPE) -+ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)) -+ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))); -+ -+ /* Handle transparent aggregates. */ -+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE) -+ && TYPE_TRANSPARENT_AGGR (type)) -+ type = TREE_TYPE (first_field (type)); -+ -+ /* See if this arg was passed by invisible reference. */ -+ function_arg_info arg (type, /*named=*/true); -+ apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg); -+ -+ /* Find mode as it is passed by the ABI. */ -+ unsignedp = TYPE_UNSIGNED (type); -+ arg.mode = promote_mode (arg.type, arg.mode, &unsignedp); -+ -+ /* If there is no incoming register, we need a stack. */ -+ entry_parm = microblaze_function_arg (args_so_far, arg); -+ if (entry_parm == NULL) -+ return true; -+ -+ /* Likewise if we need to pass both in registers and on the stack. */ -+ if (GET_CODE (entry_parm) == PARALLEL -+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX) -+ return true; -+ -+ /* Also true if we're partially in registers and partially not. */ -+ if (function_arg_partial_bytes (args_so_far, arg) != 0) -+ return true; -+ -+ /* Update info on where next arg arrives in registers. */ -+ microblaze_function_arg_advance (args_so_far, arg); -+ return false; -+} -+ -+static bool -+microblaze_function_parms_need_stack (tree fun, bool incoming) -+{ -+ tree fntype, result; -+ CUMULATIVE_ARGS args_so_far_v; -+ cumulative_args_t args_so_far; -+ int num_of_args = 0; -+ -+ /* Must be a libcall, all of which only use reg parms. */ -+ if (!fun) -+ return true; -+ -+ fntype = fun; -+ if (!TYPE_P (fun)) -+ fntype = TREE_TYPE (fun); -+ -+ /* Varargs functions need the parameter save area. */ -+ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype)) -+ return true; -+ -+ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0); -+ args_so_far = pack_cumulative_args (&args_so_far_v); -+ -+ /* When incoming, we will have been passed the function decl. -+ * * It is necessary to use the decl to handle K&R style functions, -+ * * where TYPE_ARG_TYPES may not be available. */ -+ if (incoming) -+ { -+ gcc_assert (DECL_P (fun)); -+ result = DECL_RESULT (fun); -+ } -+ else -+ result = TREE_TYPE (fntype); -+ -+ if (result && aggregate_value_p (result, fntype)) -+ { -+ if (!TYPE_P (result)) -+ result = build_pointer_type (result); -+ microblaze_parm_needs_stack (args_so_far, result); -+ } -+ -+ if (incoming) -+ { -+ tree parm; -+ for (parm = DECL_ARGUMENTS (fun); -+ parm && parm != void_list_node; -+ parm = TREE_CHAIN (parm)) -+ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm))) -+ return true; -+ } -+ else -+ { -+ function_args_iterator args_iter; -+ tree arg_type; -+ -+ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter) -+ { -+ num_of_args; -+ if (microblaze_parm_needs_stack (args_so_far, arg_type)) -+ return true; -+ } -+ } -+ -+ if (num_of_args > 3) return true; -+ -+ return false; -+} -+ -+int microblaze_reg_parm_stack_space(tree fun) -+{ -+ if (microblaze_function_parms_need_stack (fun,false)) -+ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD; -+ else -+ return 0; -+} -+ - /* Return the bytes needed to compute the frame pointer from the current - stack pointer. - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 730ad87b13b..dfacd080b6d 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info; - #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 - #define DWARF_CIE_DATA_ALIGNMENT -1 - --#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) -+#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL) - --#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 -+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 - - #define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) - --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch deleted file mode 100644 index d504a092..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch +++ /dev/null @@ -1,73 +0,0 @@ -From fe2781d189493dc82a3714b48bbc12c6bd5cdfd0 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 16:38:43 +0530 -Subject: [PATCH 52/53] [Patch,MicroBlaze] : If we use break_handler - attribute then interrupt vector call happened to break_handler instead of - interrupt_handler. this fix will resolve the issue CR-1081780. This - fix will not change the behavior of compiler unless there is a usage of - break_handler attribute. signed-off-by : Mahesh Bodapati - - ---- - gcc/config/microblaze/microblaze.cc | 13 +++++-------- - 1 file changed, 5 insertions(+), 8 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc -index 24ac215b6d5..66d62f6f909 100644 ---- a/gcc/config/microblaze/microblaze.cc -+++ b/gcc/config/microblaze/microblaze.cc -@@ -2020,7 +2020,7 @@ microblaze_save_volatiles (tree func) - int - microblaze_is_interrupt_variant (void) - { -- return (interrupt_handler || fast_interrupt); -+ return (interrupt_handler || fast_interrupt || break_handler); - } - int - microblaze_is_break_handler (void) -@@ -2059,7 +2059,7 @@ microblaze_must_save_register (int regno) - { - if (df_regs_ever_live_p (regno) - || regno == MB_ABI_MSR_SAVE_REG -- || ((interrupt_handler || fast_interrupt) -+ || ((interrupt_handler || fast_interrupt || break_handler) - && (regno == MB_ABI_ASM_TEMP_REGNUM - || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM))) - return 1; -@@ -2275,9 +2275,6 @@ compute_frame_size (HOST_WIDE_INT size) - fast_interrupt = - microblaze_fast_interrupt_function_p (current_function_decl); - save_volatiles = microblaze_save_volatiles (current_function_decl); -- if (break_handler) -- interrupt_handler = break_handler; -- - gp_reg_size = 0; - mask = 0; - var_size = size; -@@ -3237,7 +3234,7 @@ microblaze_expand_prologue (void) - gen_rtx_PLUS (Pmode, stack_pointer_rtx, - const0_rtx)); - -- if (interrupt_handler) -+ if (interrupt_handler || break_handler) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; - -@@ -3348,12 +3345,12 @@ microblaze_expand_epilogue (void) - a load-use stall cycle :) This is also important to handle alloca. - (See comments for if (frame_pointer_needed) below. */ - -- if (!crtl->is_leaf || interrupt_handler) -+ if (!crtl->is_leaf || interrupt_handler || break_handler) - { - mem_rtx = - gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); -- if (interrupt_handler) -+ if (interrupt_handler || break_handler) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; - reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch deleted file mode 100644 index 6b3f4ddd..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 6c2e67237a12cecfd8c0575fd17314d3024943fc Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 13 Sep 2022 16:45:41 +0530 -Subject: [PATCH 53/53] [patch, microblaze64]: Add Zero_extended instructions - - Due to latest changes in GCC-10.2 MB64 perforamance has reduced - We have added zero_extended instructions to get rid of left shift - and right shift loops - - [CR/TSR]: TSR-974519 - - Signed-off-by: Nagaraju Mekala - Mahesh Bodapati ---- - gcc/config/microblaze/microblaze.md | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 0ac6e1480e6..7a7c70d607b 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1191,6 +1191,33 @@ - (set_attr "mode" "SI,SI,SI") - (set_attr "length" "4,4,8")]) - -+(define_insn "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0xffff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ -+(define_insn "zero_extendsidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0xffffffff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ -+(define_insn "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0x00ff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ - ;;---------------------------------------------------------------- - ;; Sign extension - ;;---------------------------------------------------------------- --- -2.37.1 (Apple Git-137.1) - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch deleted file mode 100644 index af8ebf3b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch +++ /dev/null @@ -1,58 +0,0 @@ -Microblaze Mulitlib hack - -Based on the patch: - -From c2081c51db589471ea713870c72f13999abda815 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:10:06 +0400 -Subject: [PATCH 04/36] 64-bit multilib hack. - -GCC has internal multilib handling code but it assumes a very specific rigid directory -layout. The build system implementation of multilib layout is very generic and allows -complete customisation of the library directories. - -This patch is a partial solution to allow any custom directories to be passed into gcc -and handled correctly. It forces gcc to use the base_libdir (which is the current -directory, "."). We need to do this for each multilib that is configured as we don't -know which compiler options may be being passed into the compiler. Since we have a compiler -per mulitlib at this point that isn't an issue. - -The one problem is the target compiler is only going to work for the default multlilib at -this point. Ideally we'd figure out which multilibs were being enabled with which paths -and be able to patch these entries with a complete set of correct paths but this we -don't have such code at this point. This is something the target gcc recipe should do -and override these platform defaults in its build config. - -Do same for riscv64 and aarch64 - -RP 15/8/11 - -Upstream-Status: Inappropriate[OE-Specific] - -Signed-off-by: Khem Raj -Signed-off-by: Elvis Dowson -Signed-off-by: Mark Hatle -Signed-off-by: Mark Hatle - -Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze -=================================================================== ---- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze -+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze -@@ -1,5 +1,6 @@ - MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high --MULTILIB_DIRNAMES = m64 bs le m mh -+#MULTILIB_DIRNAMES = m64 bs le m mh -+MULTILIB_DIRNAMES = . . . . . - MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *m64 - MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift -Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux -=================================================================== ---- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze-linux -+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux -@@ -1,3 +1,4 @@ - MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high --MULTILIB_DIRNAMES = bs m mh -+#MULTILIB_DIRNAMES = bs m mh -+MULTILIB_DIRNAMES = . . . - MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch new file mode 100644 index 00000000..8b9c6177 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch @@ -0,0 +1,35 @@ +From 8beb2e85436c77db197ce22626c7b7037d41d595 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 13:13:57 +0530 +Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic + Signed-off-by: David Holsgrove + +Conflicts: + + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index fa762d33232..ce8545fc460 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + ++<<<<<<< HEAD ++======= ++if [istarget "microblaze*-*-linux*"] { ++ lappend additional_flags "-Wl,-zmuldefs" ++ lappend additional_flags "-fPIC" ++} ++ ++>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch new file mode 100644 index 00000000..94970e7b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch @@ -0,0 +1,31 @@ +From 4a2d958fe0d54c78b7a131b9cde1c74165533aaf Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 14:31:10 +0530 +Subject: [PATCH 02/54] Quick fail g++.dg/opt/memcpy1.C This particular + testcase fails with a timeout. Instead, fail it at compile-time for + microblaze. This speeds up the testsuite without removing it from the FAIL + reports. + +Signed-off-by: Edgar E. Iglesias +--- + gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C +index 3862756083d..db9f990f781 100644 +--- a/gcc/testsuite/g++.dg/opt/memcpy1.C ++++ b/gcc/testsuite/g++.dg/opt/memcpy1.C +@@ -4,6 +4,10 @@ + // { dg-do compile } + // { dg-options "-O" } + ++#if defined (__MICROBLAZE__) ++#error "too slow on mb. Investigate." ++#endif ++ + typedef unsigned char uint8_t; + typedef uint8_t uint8; + __extension__ typedef __SIZE_TYPE__ size_t; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch new file mode 100644 index 00000000..5b4466d8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch @@ -0,0 +1,35 @@ +From 0b4ec0cbfc13f5a40a20663da9c074ac81c5ec3f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 15:46:28 +0530 +Subject: [PATCH 03/54] For dejagnu static testing on qemu, suppress warnings + about multiple definitions from the test function and libc in line with + method used by powerpc. Dynamic linking and using a qemu binary which + understands sysroot resolves all test failures with builtins + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index ce8545fc460..72fd697d855 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + +-<<<<<<< HEAD +-======= + if [istarget "microblaze*-*-linux*"] { + lappend additional_flags "-Wl,-zmuldefs" +- lappend additional_flags "-fPIC" + } + +->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch new file mode 100644 index 00000000..87adeaf4 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch @@ -0,0 +1,35 @@ +From dcb106f7cb2fb68f3117677b12df2b01f3929f7b Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 15:50:35 +0530 +Subject: [PATCH 04/54] Add MicroBlaze to target-supports for atomic buil. .tin + tests + +MicroBlaze added to supported targets for atomic builtin tests. + +Changelog/testsuite + +2014-02-14 David Holsgrove + + * gcc/testsuite/lib/target-supports.exp: Add microblaze to + check_effective_target_sync_int_long. + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/lib/target-supports.exp | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 40f71e9ed8b..32e29706fcd 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -8947,6 +8947,7 @@ proc check_effective_target_sync_int_long { } { + && [check_effective_target_arm_acq_rel]) + || [istarget bfin*-*linux*] + || [istarget hppa*-*linux*] ++ || [istarget microblaze*-*linux*] + || [istarget s390*-*-*] + || [istarget powerpc*-*-*] + || [istarget cris-*-*] +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch new file mode 100644 index 00000000..9a8d0a86 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch @@ -0,0 +1,36 @@ +From 68bc05ae258334f591c336dbed6dc907969e90fc Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 16:20:01 +0530 +Subject: [PATCH 05/54] Update MicroBlaze strings test for new scan-assembly + output resulting in use of $LC label + +ChangeLog/testsuite + +2014-02-14 David Holsgrove + + * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update + to include $LC label. + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/gcc.target/microblaze/others/strings1.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c +index efaf3c660ea..347872360d3 100644 +--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c ++++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c +@@ -3,6 +3,10 @@ + /* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ + /* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ + ++/* { dg-final { scan-assembler "\.rodata*" } } */ ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ ++/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ ++ + #include + + extern void somefunc (char *); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch new file mode 100644 index 00000000..c32a8bab --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch @@ -0,0 +1,67 @@ +From 7b07ae9c8086973b7baa031b09889146057de8ab Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:14:15 +0530 +Subject: [PATCH 06/54] Allow MicroBlaze .weakext pattern in regex match Extend + regex pattern to include optional ext at the end of .weak to match the + MicroBlaze weak label .weakext + +ChangeLog/testsuite + +2014-02-14 David Holsgrove + + * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler + pattern to take optional ext after .weak. + * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. + +Signed-off-by: David Holsgrove + +Conflicts: + + gcc/testsuite/g++.dg/abi/rtti3.C +--- + gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++-- + gcc/testsuite/g++.dg/abi/thunk3.C | 2 +- + gcc/testsuite/g++.dg/abi/thunk4.C | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C +index 0cc7d3e79d0..f284cd9255c 100644 +--- a/gcc/testsuite/g++.dg/abi/rtti3.C ++++ b/gcc/testsuite/g++.dg/abi/rtti3.C +@@ -3,8 +3,8 @@ + + // { dg-require-weak "" } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } +-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } } +-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } + // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } } + // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } } + +diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C +index f2347f79ecd..dcec8a771a1 100644 +--- a/gcc/testsuite/g++.dg/abi/thunk3.C ++++ b/gcc/testsuite/g++.dg/abi/thunk3.C +@@ -1,5 +1,5 @@ + // { dg-require-weak "" } +-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } + // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } + + struct Base +diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C +index 6e8f124bc5e..d1d34fe1e4a 100644 +--- a/gcc/testsuite/g++.dg/abi/thunk4.C ++++ b/gcc/testsuite/g++.dg/abi/thunk4.C +@@ -1,6 +1,6 @@ + // { dg-require-weak "" } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } +-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } + // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } + + struct Base +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch new file mode 100644 index 00000000..5de0bfd8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch @@ -0,0 +1,27 @@ +From 6de628ecccf3739891052a2fbaf97048384c6190 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:34:27 +0530 +Subject: [PATCH 07/54] Add MicroBlaze to check_profiling_available Testsuite, + add microblaze*-*-* target in check_profiling_available inline with other + archs setting profiling_available_saved to 0 + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/lib/target-supports.exp | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 32e29706fcd..47233563339 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -804,6 +804,7 @@ proc check_profiling_available { test_what } { + || [istarget m68k-*-elf] + || [istarget m68k-*-uclinux*] + || [istarget mips*-*-elf*] ++ || [istarget microblaze*-*-*] + || [istarget mmix-*-*] + || [istarget mn10300-*-elf*] + || [istarget moxie-*-elf*] +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch new file mode 100644 index 00000000..e554e660 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch @@ -0,0 +1,67 @@ +From cd3db73d253df229054863e5f920e59e60b84c45 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:41:43 +0530 +Subject: [PATCH 08/54] Fix atomic side effects. In atomic_compare_and_swapsi, + add side effects to prevent incorrect assumptions during optimization. + Previously, the outputs were considered unused; this generated assembly code + with undefined side effects after invocation of the atomic. + +Signed-off-by: Kirk Meyer +Signed-off-by: David Holsgrove + +Conflicts: + gcc/config/microblaze/microblaze.md +--- + gcc/config/microblaze/microblaze.md | 3 +++ + gcc/config/microblaze/sync.md | 21 +++++++++++++-------- + 2 files changed, 16 insertions(+), 8 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 671667b537c..dfd7395432b 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -43,6 +43,9 @@ + (UNSPEC_TLS 106) ;; jump table + (UNSPEC_SET_TEXT 107) ;; set text start + (UNSPEC_TEXT 108) ;; data text relative ++ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool) ++ (UNSPECV_CAS_VAL 202) ;; compare and swap (val) ++ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem) + ]) + + (define_c_enum "unspec" [ +diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md +index c84bac94101..587f852b3a0 100644 +--- a/gcc/config/microblaze/sync.md ++++ b/gcc/config/microblaze/sync.md +@@ -18,14 +18,19 @@ + ;; . + + (define_insn "atomic_compare_and_swapsi" +- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output +- (match_operand:SI 1 "register_operand" "=&d") ;; val output +- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory +- (match_operand:SI 3 "register_operand" "d") ;; expected value +- (match_operand:SI 4 "register_operand" "d") ;; desired value +- (match_operand:SI 5 "const_int_operand" "") ;; is_weak +- (match_operand:SI 6 "const_int_operand" "") ;; mod_s +- (match_operand:SI 7 "const_int_operand" "") ;; mod_f ++ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output ++ (unspec_volatile:SI ++ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory ++ (match_operand:SI 3 "register_operand" "d") ;; expected value ++ (match_operand:SI 4 "register_operand" "d")] ;; desired value ++ UNSPECV_CAS_BOOL)) ++ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL)) ++ (set (match_dup 2) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM)) ++ (match_operand:SI 5 "const_int_operand" "") ;; is_weak ++ (match_operand:SI 6 "const_int_operand" "") ;; mod_s ++ (match_operand:SI 7 "const_int_operand" "") ;; mod_f + (clobber (match_scratch:SI 8 "=&d"))] + "" + { +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch new file mode 100644 index 00000000..617b10f3 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch @@ -0,0 +1,40 @@ +From 7eca0d5cf7bc603c5a359b70521861c11faf6038 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:45:45 +0530 +Subject: [PATCH 09/54] Fix atomic boolean return value. In + atomic_compare_and_swapsi, fix boolean return value. Previously, it contained + zero if successful and non-zero if unsuccessful. + +Signed-off-by: Kirk Meyer +Signed-off-by: David Holsgrove +--- + gcc/config/microblaze/sync.md | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md +index 587f852b3a0..230699bf280 100644 +--- a/gcc/config/microblaze/sync.md ++++ b/gcc/config/microblaze/sync.md +@@ -34,15 +34,16 @@ + (clobber (match_scratch:SI 8 "=&d"))] + "" + { +- output_asm_insn ("addc \tr0,r0,r0", operands); ++ output_asm_insn ("add \t%0,r0,r0", operands); + output_asm_insn ("lwx \t%1,%y2,r0", operands); + output_asm_insn ("addic\t%8,r0,0", operands); + output_asm_insn ("bnei \t%8,.-8", operands); +- output_asm_insn ("cmp \t%0,%1,%3", operands); +- output_asm_insn ("bnei \t%0,.+16", operands); ++ output_asm_insn ("cmp \t%8,%1,%3", operands); ++ output_asm_insn ("bnei \t%8,.+20", operands); + output_asm_insn ("swx \t%4,%y2,r0", operands); + output_asm_insn ("addic\t%8,r0,0", operands); + output_asm_insn ("bnei \t%8,.-28", operands); ++ output_asm_insn ("addi \t%0,r0,1", operands); + return ""; + } + ) +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch new file mode 100644 index 00000000..42b9d575 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch @@ -0,0 +1,35 @@ +From 72cdba90d70131c092918c5d5c18eb800f0f9dfb Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:50:17 +0530 +Subject: [PATCH 10/54] Fix the Microblaze crash with msmall-divides flag + Compiler is crashing when we use msmall-divides and mxl-barrel-shift flag. + This is because when use above flags microblaze_expand_divide function will + be called for division operation. In microblaze_expand_divide function we are + using sub_reg but MicroBlaze doesn't have subreg register due to this + compiler was crashing. Changed the logic to avoid sub_reg call + +Signed-off-by:Nagaraju Mekala + +Conflicts: + gcc/config/microblaze/microblaze.c +--- + gcc/config/microblaze/microblaze.cc | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 6df2c712cab..11e34b3fdae 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -3719,8 +3719,7 @@ microblaze_expand_divide (rtx operands[]) + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); + +- insn = emit_insn (gen_movqi (regqi, mem_rtx)); +- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); ++ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch new file mode 100644 index 00000000..8988e23b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch @@ -0,0 +1,48 @@ +From 41d8b3677d64bf9408925667c103a04b176050d5 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:52:56 +0530 +Subject: [PATCH 11/54] Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt + pattern to optimize the sra instructions when the -Os optimization is used. + lshrsi3_with_size_opt is being removed as it has conflicts with unsigned int + variables + +Signed-off-by:Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index dfd7395432b..4f20b8efe33 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1508,6 +1508,27 @@ + (set_attr "length" "4,4")] + ) + ++(define_insn "*ashrsi3_with_size_opt" ++ [(set (match_operand:SI 0 "register_operand" "=&d") ++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "immediate_operand" "I")))] ++ "(INTVAL (operands[2]) > 5 && optimize_size)" ++ { ++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("ori\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addik\t%3,%3,-1", operands); ++ output_asm_insn ("bneid\t%3,.-4", operands); ++ return "sra\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "20")] ++) ++ + (define_insn "*ashrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch new file mode 100644 index 00000000..46a8699a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch @@ -0,0 +1,26 @@ +From 9dc1f7291c4c7abfe254ca4e86a6ba0975a74960 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 10:57:19 +0530 +Subject: [PATCH 12/54] Use bralid for profiler calls Signed-off-by: Edgar E. + Iglesias + +--- + gcc/config/microblaze/microblaze.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 0398902362b..49e7fbedd5a 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -486,7 +486,7 @@ typedef struct microblaze_args + + #define FUNCTION_PROFILER(FILE, LABELNO) { \ + { \ +- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \ ++ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \ + } \ + } + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch new file mode 100644 index 00000000..26c24a49 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch @@ -0,0 +1,160 @@ +From a2dbb662c573d2bf1a6a9192eb0d7f453ad20c59 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 17:36:16 +0530 +Subject: [PATCH 13/54] Removed moddi3 routinue Using the default moddi3 + function as the existing implementation has many bugs + +Signed-off-by:Nagaraju + +Conflicts: + libgcc/config/microblaze/moddi3.S +--- + libgcc/config/microblaze/moddi3.S | 121 -------------------------- + libgcc/config/microblaze/t-microblaze | 3 +- + 2 files changed, 1 insertion(+), 123 deletions(-) + delete mode 100644 libgcc/config/microblaze/moddi3.S + +diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S +deleted file mode 100644 +index b3e4bf6182e..00000000000 +--- a/libgcc/config/microblaze/moddi3.S ++++ /dev/null +@@ -1,121 +0,0 @@ +-################################### +-# +-# Copyright (C) 2009-2023 Free Software Foundation, Inc. +-# +-# Contributed by Michael Eager . +-# +-# This file is free software; you can redistribute it and/or modify it +-# under the terms of the GNU General Public License as published by the +-# Free Software Foundation; either version 3, or (at your option) any +-# later version. +-# +-# GCC is distributed in the hope that it will be useful, but WITHOUT +-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-# License for more details. +-# +-# Under Section 7 of GPL version 3, you are granted additional +-# permissions described in the GCC Runtime Library Exception, version +-# 3.1, as published by the Free Software Foundation. +-# +-# You should have received a copy of the GNU General Public License and +-# a copy of the GCC Runtime Library Exception along with this program; +-# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +-# . +-# +-# modsi3.S +-# +-# modulo operation for 64 bit integers. +-# +-####################################### +- +- +-/* An executable stack is *not* required for these functions. */ +-#ifdef __linux__ +-.section .note.GNU-stack,"",%progbits +-.previous +-#endif +- +- .globl __moddi3 +- .ent __moddi3 +-__moddi3: +- .frame r1,0,r15 +- +-#Change the stack pointer value and Save callee saved regs +- addik r1,r1,-24 +- swi r25,r1,0 +- swi r26,r1,4 +- swi r27,r1,8 # used for sign +- swi r28,r1,12 # used for loop count +- swi r29,r1,16 # Used for div value High +- swi r30,r1,20 # Used for div value Low +- +-#Check for Zero Value in the divisor/dividend +- OR r9,r5,r6 # Check for the op1 being zero +- BEQID r9,$LaResult_Is_Zero # Result is zero +- OR r9,r7,r8 # Check for the dividend being zero +- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error +- BGEId r5,$La1_Pos +- XOR r27,r5,r7 # Get the sign of the result +- RSUBI r6,r6,0 # Make dividend positive +- RSUBIC r5,r5,0 # Make dividend positive +-$La1_Pos: +- BGEI r7,$La2_Pos +- RSUBI r8,r8,0 # Make Divisor Positive +- RSUBIC r9,r9,0 # Make Divisor Positive +-$La2_Pos: +- ADDIK r4,r0,0 # Clear mod low +- ADDIK r3,r0,0 # Clear mod high +- ADDIK r29,r0,0 # clear div high +- ADDIK r30,r0,0 # clear div low +- ADDIK r28,r0,64 # Initialize the loop count +- # First part try to find the first '1' in the r5/r6 +-$LaDIV1: +- ADD r6,r6,r6 +- ADDC r5,r5,r5 # left shift logical r5 +- BGEID r5,$LaDIV1 +- ADDIK r28,r28,-1 +-$LaDIV2: +- ADD r6,r6,r6 +- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry +- ADDC r4,r4,r4 # Move that bit into the Mod register +- ADDC r3,r3,r3 # Move carry into high mod register +- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor +- bnei r18,$L_High_EQ +- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h] +-$L_High_EQ: +- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L] +- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H] +- BLTi r25,$LaMOD_TOO_SMALL +- OR r3,r0,r25 # move r25 to mod [h] +- OR r4,r0,r26 # move r26 to mod [l] +- ADDI r30,r30,1 +- ADDC r29,r29,r0 +-$LaMOD_TOO_SMALL: +- ADDIK r28,r28,-1 +- BEQi r28,$LaLOOP_END +- ADD r30,r30,r30 # Shift in the '1' into div [low] +- ADDC r29,r29,r29 # Move the carry generated into high +- BRI $LaDIV2 # Div2 +-$LaLOOP_END: +- BGEI r27,$LaRETURN_HERE +- rsubi r30,r30,0 +- rsubc r29,r29,r0 +- BRI $LaRETURN_HERE +-$LaDiv_By_Zero: +-$LaResult_Is_Zero: +- or r29,r0,r0 # set result to 0 [High] +- or r30,r0,r0 # set result to 0 [Low] +-$LaRETURN_HERE: +-# Restore values of CSRs and that of r29 and the divisor and the dividend +- +- lwi r25,r1,0 +- lwi r26,r1,4 +- lwi r27,r1,8 +- lwi r28,r1,12 +- lwi r29,r1,16 +- lwi r30,r1,20 +- rtsd r15,8 +- addik r1,r1,24 +- .end __moddi3 +- +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 96959f0292b..8d954a49575 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,8 +1,7 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ +- $(srcdir)/config/microblaze/moddi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ + $(srcdir)/config/microblaze/muldi3_hard.S \ + $(srcdir)/config/microblaze/mulsi3.S \ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch new file mode 100644 index 00000000..9e4348ad --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch @@ -0,0 +1,90 @@ +From 40dd974a6cd608567f1746a934c9743b80ca1e3f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 12 Sep 2022 20:20:00 +0530 +Subject: [PATCH 14/54] Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR + and TARGET_ASM_DESTRUCTOR macros. + +These macros allows users to control the order of initialization +of objects defined at namespace scope with the init_priority +attribute by specifying a relative priority, a constant integral +expression currently bounded between 101 and 65535 inclusive. + +Lower numbers indicate a higher priority. +--- + gcc/config/microblaze/microblaze.cc | 53 +++++++++++++++++++++++++++++ + 1 file changed, 53 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 11e34b3fdae..3fb402b87d4 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2640,6 +2640,53 @@ print_operand_address (FILE * file, rtx addr) + } + } + ++/* Output an element in the table of global constructors. */ ++void ++microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) ++{ ++ const char *section = ".ctors"; ++ char buf[16]; ++ ++ if (priority != DEFAULT_INIT_PRIORITY) ++ { ++ sprintf (buf, ".ctors.%.5u", ++ /* Invert the numbering so the linker puts us in the proper ++ order; constructors are run from right to left, and the ++ linker sorts in increasing order. */ ++ MAX_INIT_PRIORITY - priority); ++ section = buf; ++ } ++ ++ switch_to_section (get_section (section, 0, NULL)); ++ assemble_align (POINTER_SIZE); ++ fputs ("\t.word\t", asm_out_file); ++ output_addr_const (asm_out_file, symbol); ++ fputs ("\n", asm_out_file); ++} ++ ++/* Output an element in the table of global destructors. */ ++void ++microblaze_asm_destructor (rtx symbol, int priority) ++{ ++ const char *section = ".dtors"; ++ char buf[16]; ++ if (priority != DEFAULT_INIT_PRIORITY) ++ { ++ sprintf (buf, ".dtors.%.5u", ++ /* Invert the numbering so the linker puts us in the proper ++ order; constructors are run from right to left, and the ++ linker sorts in increasing order. */ ++ MAX_INIT_PRIORITY - priority); ++ section = buf; ++ } ++ ++ switch_to_section (get_section (section, 0, NULL)); ++ assemble_align (POINTER_SIZE); ++ fputs ("\t.word\t", asm_out_file); ++ output_addr_const (asm_out_file, symbol); ++ fputs ("\n", asm_out_file); ++} ++ + /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol + is used, so that we don't emit an .extern for it in + microblaze_asm_file_end. */ +@@ -3985,6 +4032,12 @@ microblaze_starting_frame_offset (void) + #undef TARGET_ATTRIBUTE_TABLE + #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table + ++#undef TARGET_ASM_CONSTRUCTOR ++#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor ++ ++#undef TARGET_ASM_DESTRUCTOR ++#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor ++ + #undef TARGET_IN_SMALL_DATA_P + #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch new file mode 100644 index 00000000..fac95b7b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch @@ -0,0 +1,81 @@ +From d0f1a493d130e06816df4d11f31421a8691761e0 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 15:23:57 +0530 +Subject: [PATCH 15/54] Add optimized lshrsi3 When barrel shifter is not + present, the immediate value is greater than #5 and optimization is -OS, the + compiler will generate shift operation using loop. + +Changelog + +2013-11-26 David Holsgrove + + * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn + +ChangeLog/testsuite + +2014-02-12 David Holsgrove + + * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. + +Signed-off-by:Nagaraju +Signed-off-by: David Holsgrove +--- + gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++ + .../microblaze/others/lshrsi_Os_1.c | 13 ++++++++++++ + 2 files changed, 34 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 4f20b8efe33..5d65ad84449 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1618,6 +1618,27 @@ + (set_attr "length" "4,4")] + ) + ++(define_insn "*lshrsi3_with_size_opt" ++ [(set (match_operand:SI 0 "register_operand" "=&d") ++ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "immediate_operand" "I")))] ++ "(INTVAL (operands[2]) > 5 && optimize_size)" ++ { ++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("ori\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addik\t%3,%3,-1", operands); ++ output_asm_insn ("bneid\t%3,.-4", operands); ++ return "srl\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "SI") ++ (set_attr "length" "20")] ++) ++ + (define_insn "*lshrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") +diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c +new file mode 100644 +index 00000000000..32a3be7c76a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c +@@ -0,0 +1,13 @@ ++/* { dg-options "-Os -mno-xl-barrel-shift" } */ ++ ++void testfunc(void) ++{ ++ unsigned volatile int z = 8192; ++ z >>= 8; ++} ++/* { dg-final { scan-assembler-not "\bsrli" } } */ ++/* { dg-final { scan-assembler "\ori\tr18,r0" } } */ ++/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */ ++/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */ ++/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ ++/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch new file mode 100644 index 00000000..298765dc --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch @@ -0,0 +1,146 @@ +From e94d406c9fa0d7b99532bd8cf4b2a4580cdb02b7 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 17:04:37 +0530 +Subject: [PATCH 16/54] Add cbranchsi4_reg This patch optimizes the generation + of pcmpne/pcmpeq instruction if the compare instruction has no immediate + values.For the immediate values the xor instruction is generated + +Signed-off-by: Nagaraju Mekala +Signed-off-by: Ajit Agarwal + +ChangeLog: +2015-01-13 Nagaraju Mekala + Ajit Agarwal + + *microblaze.md (cbranchsi4_reg): New + *microblaze.c (microblaze_expand_conditional_branch_reg): New + +Conflicts: + + gcc/config/microblaze/microblaze-protos.h +--- + gcc/config/microblaze/microblaze-protos.h | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++------- + gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------ + 7 files changed, 18 insertions(+), 18 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index 31a6515176b..41557af0f3c 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *); + extern bool microblaze_expand_move (machine_mode, rtx *); + extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); + extern void microblaze_expand_divide (rtx *); +-extern void microblaze_expand_conditional_branch (machine_mode, rtx *); ++extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); + extern int microblaze_can_use_return_insn (void); +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +index 4041a241391..ccc6a461cd9 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 <= f3) +- print ("le"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +index 3902b839db9..1dd5fe6c539 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 < f3) +- print ("lt"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +index 8555974dda5..d6f80fb0ec3 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 == f3) +- print ("eq"); ++ f1 = f2 + f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +index 79cc5f9dd8e..d1177249552 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3) + /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if(f1==f2 && f1<=f3) +- print ("f1 eq f2 && f1 le f3"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +index ebfb170ecee..75822977ef8 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +@@ -5,17 +5,17 @@ volatile float f1, f2, f3; + void float_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ +- if (f2 <= f3) +- print ("le"); ++ if (f2 <= f3) ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +index 1d6ba807b12..532c035adfd 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +@@ -74,16 +74,16 @@ void float_cmp_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ + if (f2 <= f3) +- print ("le"); ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch new file mode 100644 index 00000000..91ca87fc --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch @@ -0,0 +1,58 @@ +From 0760cd661f6c09cda8327288f79314319a0b9b14 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 17:11:04 +0530 +Subject: [PATCH 17/54] Inline Expansion of fsqrt builtin. The changes are made + in the patch for the inline expansion of the fsqrt builtin with fqrt + instruction. The sqrt math function takes double as argument and return + double as argument. The pattern is selected while expanding the unary op + through expand_unop which passes DFmode and the DFmode pattern was not there + returning zero. Thus the sqrt math function is not inlined and expanded. The + pattern with DFmode argument is added. Also the source and destination + argument is not same the DF through two different consecutive registers with + lower 32 bit is the argument passed to sqrt and the higher 32 bit is zero. If + the source and destinations are different the DFmode 64 bits registers is not + set properly giving the problem in runtime. Such changes are taken care in + the implementation of the pattern for DFmode for inline expansion of the + sqrt. + +ChangeLog: +2015-06-16 Ajit Agarwal + Nagaraju Mekala + + * config/microblaze/microblaze.md (sqrtdf2): New + pattern. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com + Nagaraju Mekala nmekala@xilinx.com +--- + gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 5d65ad84449..0597ed8d75a 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -451,6 +451,20 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" ++ { ++ if (REGNO (operands[0]) == REGNO (operands[1])) ++ return "fsqrt\t%0,%1"; ++ else ++ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; ++ } ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch new file mode 100644 index 00000000..f388e9b5 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch @@ -0,0 +1,63 @@ +From 0a7299e82a8f463e9e7cd6297c5bdc0aac3a0ec4 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 18:07:24 +0530 +Subject: [PATCH 18/54] microblaze.md: Improve 'adddi3' and 'subdi3' insn + definitions Change adddi3 to handle DI immediates as the second operand, this + requires modification to the output template however reduces the need to + specify seperate templates for 16-bit positive/negative immediate operands. + The use of 32-bit immediates for the addi and addic instructions is handled + by the assembler, which will emit the imm instructions when required. This + conveniently handles the optimizable cases where the immediate constant value + does not need the higher half words of the operands upper/lower words. + +Change the constraints of the subdi3 instruction definition such that it +does not match the second operand as an immediate value. This is because +there is no definition to handle this case nor is it possible to +implement purely with instructions as microblaze does not provide an +instruction to perform a forward arithmetic subtraction (it only +provides reverse 'rD = IMM - rA'). + +Signed-off-by: Nathan Rossi +--- + gcc/config/microblaze/microblaze.md | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0597ed8d75a..498926a4a75 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -502,17 +502,16 @@ + ;; Adding 2 DI operands in register or reg/imm + + (define_insn "adddi3" +- [(set (match_operand:DI 0 "register_operand" "=d,d,d") +- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d") +- (match_operand:DI 2 "arith_operand32" "d,P,N")))] ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") ++ (match_operand:DI 2 "arith_operand" "d,i")))] + "" + "@ + add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 +- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0 +- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1" ++ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" + [(set_attr "type" "darith") + (set_attr "mode" "DI") +- (set_attr "length" "8,8,12")]) ++ (set_attr "length" "8,8")]) + + ;;---------------------------------------------------------------- + ;; Subtraction +@@ -549,7 +548,7 @@ + (define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") +- (match_operand:DI 2 "arith_operand32" "d")))] ++ (match_operand:DI 2 "register_operand" "d")))] + "" + "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" + [(set_attr "type" "darith") +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch new file mode 100644 index 00000000..0f388f70 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch @@ -0,0 +1,75 @@ +From a969ab3f04de077eca6d928dd651e3c6b042367d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 18:18:41 +0530 +Subject: [PATCH 19/54] Update ashlsi3 & movsf patterns This patch removes the + use of HOST_WIDE_INT_PRINT_HEX macro in print_operand of + ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal patterns + beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our + instruction doesn't support so using gen_int_mode function + +Signed-off-by :Nagaraju Mekala + :Ajit Agarwal + +ChangeLog: +2016-01-07 Nagaraju Mekala + Ajit Agarwal + + *microblaze.md (ashlsi3_with_mul_nodelay, + ashlsi3_with_mul_delay, + movsf_internal): + Updated the patterns to use gen_int_mode function + *microblaze.cc (print_operand): + updated the 'F' case to use "unsinged int" instead + of HOST_WIDE_INT_PRINT_HEX + +Conflicts: + gcc/config/microblaze/microblaze.c +--- + gcc/config/microblaze/microblaze.cc | 2 +- + gcc/config/microblaze/microblaze.md | 10 ++++++++-- + 2 files changed, 9 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 3fb402b87d4..ff64e0ca342 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2474,7 +2474,7 @@ print_operand (FILE * file, rtx op, int letter) + unsigned long value_long; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), + value_long); +- fprintf (file, "0x%lx", value_long); ++ fprintf (file, "0x%08x", (unsigned int) value_long); + } + else + { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 498926a4a75..0448101de8a 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1368,7 +1368,10 @@ + (match_operand:SI 2 "immediate_operand" "I")))] + "!TARGET_SOFT_MUL + && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)" +- "muli\t%0,%1,%m2" ++ { ++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); ++ return "muli\t%0,%1,%2"; ++ } + ;; This MUL will not generate an imm. Can go into a delay slot. + [(set_attr "type" "arith") + (set_attr "mode" "SI") +@@ -1380,7 +1383,10 @@ + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "!TARGET_SOFT_MUL" +- "muli\t%0,%1,%m2" ++ { ++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); ++ return "muli\t%0,%1,%2"; ++ } + ;; This MUL will generate an IMM. Cannot go into a delay slot + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "SI") +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch new file mode 100644 index 00000000..002e60be --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch @@ -0,0 +1,177 @@ +From 21daca8e01515b2e73463adbf9488b63bb0ccf54 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 12 Sep 2022 21:05:51 +0530 +Subject: [PATCH 20/54] 8-stage pipeline for microblaze This patch adds the + support for the 8-stage pipeline. The new 8-stage pipeline reduces the + latencies of float & integer division drastically + +Signed-off-by :Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.cc | 11 ++++ + gcc/config/microblaze/microblaze.h | 3 +- + gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++- + gcc/config/microblaze/microblaze.opt | 4 ++ + 4 files changed, 94 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index ff64e0ca342..a58a5b2a1b0 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -1846,6 +1846,17 @@ microblaze_option_override (void) + "%<-mcpu=v8.30.a%>"); + TARGET_REORDER = 0; + } ++ ver = microblaze_version_to_int("v10.0"); ++ if (ver < 0) ++ { ++ if (TARGET_AREA_OPTIMIZED_2) ++ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater"); ++ } ++ else ++ { ++ if (TARGET_AREA_OPTIMIZED_2) ++ microblaze_pipe = MICROBLAZE_PIPE_8; ++ } + + if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) + error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>"); +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 49e7fbedd5a..e4faa9c681f 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -27,7 +27,8 @@ + enum pipeline_type + { + MICROBLAZE_PIPE_3 = 0, +- MICROBLAZE_PIPE_5 = 1 ++ MICROBLAZE_PIPE_5 = 1, ++ MICROBLAZE_PIPE_8 = 2 + }; + + #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0448101de8a..7a01b28d8f0 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -35,6 +35,7 @@ + (R_GOT 20) ;; GOT ptr reg + (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline + (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline ++ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline + (UNSPEC_SET_GOT 101) ;; + (UNSPEC_GOTOFF 102) ;; GOT offset + (UNSPEC_PLT 103) ;; jump table +@@ -82,7 +83,7 @@ + ;; bshift Shift operations + + (define_attr "type" +- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap" ++ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap" + (const_string "unknown")) + + ;; Main data type used by the insn +@@ -224,6 +225,80 @@ + ;;----------------------------------------------------------------- + + ++ ++;;---------------------------------------------------------------- ++;; Microblaze 8-stage pipeline description (v10.0 and later) ++;;---------------------------------------------------------------- ++ ++(define_automaton "mbpipe_8") ++(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8") ++ ++(define_insn_reservation "mb8-integer" 1 ++ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu,mb8_wb") ++ ++(define_insn_reservation "mb8-special-move" 2 ++ (and (eq_attr "type" "move") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu*2,mb8_wb") ++ ++(define_insn_reservation "mb8-mem-load" 3 ++ (and (eq_attr "type" "load,no_delay_load") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu,mb8_wb") ++ ++(define_insn_reservation "mb8-mem-store" 1 ++ (and (eq_attr "type" "store,no_delay_store") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu,mb8_wb") ++ ++(define_insn_reservation "mb8-mul" 3 ++ (and (eq_attr "type" "imul,no_delay_imul") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb") ++ ++(define_insn_reservation "mb8-div" 30 ++ (and (eq_attr "type" "idiv") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb") ++ ++(define_insn_reservation "mb8-bs" 2 ++ (and (eq_attr "type" "bshift") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-add-sub-mul" 1 ++ (and (eq_attr "type" "fadd,frsub,fmul") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-fcmp" 3 ++ (and (eq_attr "type" "fcmp") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-div" 24 ++ (and (eq_attr "type" "fdiv") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-sqrt" 23 ++ (and (eq_attr "type" "fsqrt") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-fcvt" 1 ++ (and (eq_attr "type" "fcvt") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-fint" 2 ++ (and (eq_attr "type" "fint") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_wb") ++ ++ + ;;---------------------------------------------------------------- + ;; Microblaze 5-stage pipeline description (v5.00.a and later) + ;;---------------------------------------------------------------- +@@ -470,7 +545,7 @@ + (fix:SI (match_operand:SF 1 "register_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "fint\t%0,%1" +- [(set_attr "type" "fcvt") ++ [(set_attr "type" "fint") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt +index dbf6390ef4b..37aaaf9ffda 100644 +--- a/gcc/config/microblaze/microblaze.opt ++++ b/gcc/config/microblaze/microblaze.opt +@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE). + + mxl-mode-xilkernel + Target ++ ++mxl-frequency ++Target Mask(AREA_OPTIMIZED_2) ++Use 8 stage pipeline (frequency optimization) +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch new file mode 100644 index 00000000..2e8182d1 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch @@ -0,0 +1,58 @@ +From 1cda2f5772650aa65853e6a3e9d8162498c2f469 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 11:49:11 +0530 +Subject: [PATCH 21/54] Correct the const high double immediate value with this + patch the loading of the DI mode immediate values will be using + REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE functions, as + CONST_DOUBLE_HIGH was returning the sign extension value even of the unsigned + long long constants also + +Signed-off-by :Nagaraju Mekala + Ajit Agarwal +--- + gcc/config/microblaze/microblaze.cc | 6 ++++-- + gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++ + 2 files changed, 13 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index a58a5b2a1b0..af5c2371740 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2458,14 +2458,16 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ long l[2]; + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); + else + { +- val[0] = CONST_DOUBLE_HIGH (op); +- val[1] = CONST_DOUBLE_LOW (op); ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); ++ val[1] = l[WORDS_BIG_ENDIAN == 0]; ++ val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } + else if (code == CONST_INT) +diff --git a/gcc/testsuite/gcc.target/microblaze/others/long.c b/gcc/testsuite/gcc.target/microblaze/others/long.c +new file mode 100644 +index 00000000000..b6b55d5ad65 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/microblaze/others/long.c +@@ -0,0 +1,9 @@ ++#define BASEADDR 0xF0000000ULL ++int main () ++{ ++ unsigned long long start; ++ start = (unsigned long long) BASEADDR; ++ return 0; ++} ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch new file mode 100644 index 00000000..599bd71e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch @@ -0,0 +1,31 @@ +From a88796930d8ef1b97056217ffdcc9f86326cdc98 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 11:58:14 +0530 +Subject: [PATCH 22/54] Fix internal compiler error with msmall-divides This + patch will fix the internal error microblaze_expand_divide function which + come of rtx PLUS where the mem_rtx is of type SI and the operand is of type + QImode. This patch modifies the mem_rtx as QImode and Plus as QImode to fix + the error. + + Signed-off-by :Nagaraju Mekala + Ajit Agarwal +--- + gcc/config/microblaze/microblaze.cc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index af5c2371740..4967d6a0133 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -3777,7 +3777,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_addsi3 (regt1, regt1, operands[2])); + mem_rtx = gen_rtx_MEM (QImode, +- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); ++ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch new file mode 100644 index 00000000..65f283ad --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch @@ -0,0 +1,36 @@ +From f9871617fe69a105ebc4aa4838c682bfe40e4f2c Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 12:03:08 +0530 +Subject: [PATCH 23/54] Fix the calculation of high word in a long long 64-bit + + This patch will change the calculation of high word in a long long 64-bit. + Earlier to this patch the high word of long long word (0xF0000000ULL) is + coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word + should be 0x00000000 and the low word should be 0xF0000000. This patch + removes the condition of checking high word = 0 & low word < 0. + This check is not required for the correctness of calculating 32-bit high + and low words in a 64-bit long long. + + Signed-off-by :Nagaraju Mekala + Ajit Agarwal +--- + gcc/config/microblaze/microblaze.cc | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 4967d6a0133..2d516724acc 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2474,9 +2474,6 @@ print_operand (FILE * file, rtx op, int letter) + { + val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; + val[1] = INTVAL (op) & 0x00000000ffffffffLL; +- if (val[0] == 0 && val[1] < 0) +- val[0] = -1; +- + } + fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch new file mode 100644 index 00000000..0356657b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch @@ -0,0 +1,373 @@ +From a8991be91d79cf0bd17b7d303a10ec5edd7408c6 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 12:23:54 +0530 +Subject: [PATCH 24/54] this patch has 1.Fixed the bug in version calculation. + 2.Add new bitfield instructions. + +Signed-off-by :Mahesh Bodapati +--- + gcc/config/microblaze/microblaze.cc | 154 ++++++++++++++-------------- + gcc/config/microblaze/microblaze.h | 2 + + gcc/config/microblaze/microblaze.md | 69 +++++++++++++ + 3 files changed, 147 insertions(+), 78 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 2d516724acc..e28ab593c3e 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -165,6 +165,9 @@ int microblaze_no_unsafe_delay; + /* Set to one if the targeted core has the CLZ insn. */ + int microblaze_has_clz = 0; + ++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */ ++int microblaze_has_bitfield = 0; ++ + /* Which CPU pipeline do we use. We haven't really standardized on a CPU + version having only a particular type of pipeline. There can still be + options on the CPU to scale pipeline features up or down. :( +@@ -240,6 +243,63 @@ section *sdata2_section; + #define TARGET_HAVE_TLS true + #endif + ++/* Convert a version number of the form "vX.YY.Z" to an integer encoding ++ for easier range comparison. */ ++static int ++microblaze_version_to_int (const char *version) ++{ ++ const char *p, *v; ++ const char *tmpl = "vXX.YY.Z"; ++ int iver1 =0, iver2 =0, iver3 =0; ++ ++ p = version; ++ v = tmpl; ++ ++ while (*p) ++ { ++ if (*v == 'X') ++ { /* Looking for major */ ++ if (*p == '.') ++ { ++ *v++; ++ } ++ else ++ { ++ if (!(*p >= '0' && *p <= '9')) ++ return -1; ++ iver1 += (int) (*p - '0'); ++ iver1 *= 1000; ++ } ++ } ++ else if (*v == 'Y') ++ { /* Looking for minor */ ++ if (!(*p >= '0' && *p <= '9')) ++ return -1; ++ iver2 += (int) (*p - '0'); ++ iver2 *= 10; ++ } ++ else if (*v == 'Z') ++ { /* Looking for compat */ ++ if (!(*p >= 'a' && *p <= 'z')) ++ return -1; ++ iver3 = ((int) (*p)) - 96; ++ } ++ else ++ { ++ if (*p != *v) ++ return -1; ++ } ++ ++ v++; ++ p++; ++ } ++ ++ if (*p) ++ return -1; ++ ++ return iver1 + iver2 + iver3; ++} ++ + /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ + static bool + microblaze_const_double_ok (rtx op, machine_mode mode) +@@ -1344,8 +1404,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, + { + if (TARGET_BARREL_SHIFT) + { +- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") +- >= 0) ++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (2); +@@ -1406,8 +1465,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, + } + else if (!TARGET_SOFT_MUL) + { +- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") +- >= 0) ++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (3); +@@ -1680,72 +1738,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, + return 0; + } + +-/* Convert a version number of the form "vX.YY.Z" to an integer encoding +- for easier range comparison. */ +-static int +-microblaze_version_to_int (const char *version) +-{ +- const char *p, *v; +- const char *tmpl = "vXX.YY.Z"; +- int iver = 0; +- +- p = version; +- v = tmpl; +- +- while (*p) +- { +- if (*v == 'X') +- { /* Looking for major */ +- if (*p == '.') +- { +- v++; +- } +- else +- { +- if (!(*p >= '0' && *p <= '9')) +- return -1; +- iver += (int) (*p - '0'); +- iver *= 10; +- } +- } +- else if (*v == 'Y') +- { /* Looking for minor */ +- if (!(*p >= '0' && *p <= '9')) +- return -1; +- iver += (int) (*p - '0'); +- iver *= 10; +- } +- else if (*v == 'Z') +- { /* Looking for compat */ +- if (!(*p >= 'a' && *p <= 'z')) +- return -1; +- iver *= 10; +- iver += (int) (*p - 'a'); +- } +- else +- { +- if (*p != *v) +- return -1; +- } +- +- v++; +- p++; +- } +- +- if (*p) +- return -1; +- +- return iver; +-} +- +- + static void + microblaze_option_override (void) + { + int i, start; + int regno; + machine_mode mode; +- int ver; ++ int ver,ver_int; + + microblaze_section_threshold = (OPTION_SET_P (g_switch_value) + ? g_switch_value +@@ -1766,13 +1765,13 @@ microblaze_option_override (void) + /* Check the MicroBlaze CPU version for any special action to be done. */ + if (microblaze_select_cpu == NULL) + microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; +- ver = microblaze_version_to_int (microblaze_select_cpu); +- if (ver == -1) ++ ver_int = microblaze_version_to_int (microblaze_select_cpu); ++ if (ver_int == -1) + { + error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu); + } + +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a"); ++ ver = ver_int - microblaze_version_to_int("v3.00.a"); + if (ver < 0) + { + /* No hardware exceptions in earlier versions. So no worries. */ +@@ -1783,8 +1782,7 @@ microblaze_option_override (void) + microblaze_pipe = MICROBLAZE_PIPE_3; + } + else if (ver == 0 +- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b") +- == 0)) ++ || (ver_int == microblaze_version_to_int("v4.00.b"))) + { + #if 0 + microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); +@@ -1801,11 +1799,9 @@ microblaze_option_override (void) + #endif + microblaze_no_unsafe_delay = 0; + microblaze_pipe = MICROBLAZE_PIPE_5; +- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0 +- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, +- "v5.00.b") == 0 +- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, +- "v5.00.c") == 0) ++ if ((ver_int == microblaze_version_to_int("v5.00.a")) ++ || (ver_int == microblaze_version_to_int("v5.00.b")) ++ || (ver_int == microblaze_version_to_int("v5.00.c"))) + { + /* Pattern compares are to be turned on by default only when + compiling for MB v5.00.'z'. */ +@@ -1813,7 +1809,7 @@ microblaze_option_override (void) + } + } + +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a"); ++ ver = ver_int - microblaze_version_to_int("v6.00.a"); + if (ver < 0) + { + if (TARGET_MULTIPLY_HIGH) +@@ -1822,7 +1818,7 @@ microblaze_option_override (void) + "%<-mcpu=v6.00.a%> or greater"); + } + +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a"); ++ ver = ver_int - microblaze_version_to_int("v8.10.a"); + microblaze_has_clz = 1; + if (ver < 0) + { +@@ -1831,7 +1827,7 @@ microblaze_option_override (void) + } + + /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a"); ++ ver = ver_int - microblaze_version_to_int("v8.30.a"); + if (ver < 0) + { + if (TARGET_REORDER == 1) +@@ -1846,7 +1842,7 @@ microblaze_option_override (void) + "%<-mcpu=v8.30.a%>"); + TARGET_REORDER = 0; + } +- ver = microblaze_version_to_int("v10.0"); ++ ver = ver_int - microblaze_version_to_int("v10.0"); + if (ver < 0) + { + if (TARGET_AREA_OPTIMIZED_2) +@@ -1856,6 +1852,8 @@ microblaze_option_override (void) + { + if (TARGET_AREA_OPTIMIZED_2) + microblaze_pipe = MICROBLAZE_PIPE_8; ++ if (TARGET_BARREL_SHIFT) ++ microblaze_has_bitfield = 1; + } + + if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index e4faa9c681f..94d96bf6b5d 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -44,6 +44,7 @@ extern int microblaze_debugger_regno[]; + + extern int microblaze_no_unsafe_delay; + extern int microblaze_has_clz; ++extern int microblaze_has_bitfield; + extern enum pipeline_type microblaze_pipe; + + #define OBJECT_FORMAT_ELF +@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe; + /* Do we have CLZ? */ + #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz) + ++#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield) + /* The default is to support PIC. */ + #define TARGET_SUPPORTS_PIC 1 + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 7a01b28d8f0..a76287ab4fd 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2491,4 +2491,73 @@ + DONE; + }") + ++(define_expand "extvsi" ++ [(set (match_operand:SI 0 "register_operand" "r") ++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "immediate_operand" "I") ++ (match_operand:SI 3 "immediate_operand" "I")))] ++"TARGET_HAS_BITFIELD" ++" ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); ++ ++ if ((len == 0) || (pos + len > 32) ) ++ FAIL; ++ ++ ;;if (!register_operand (operands[1], VOIDmode)) ++ ;; FAIL; ++ if (operands[0] == operands[1]) ++ FAIL; ++ if (GET_CODE (operands[1]) == ASHIFT) ++ FAIL; ++;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); ++ emit_insn (gen_extv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") ++ ++(define_insn "extv_32" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "immediate_operand" "I") ++ (match_operand:SI 3 "immediate_operand" "I")))] ++ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0) ++ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" ++ "bsefi %0,%1,%2,%3" ++ [(set_attr "type" "bshift") ++ (set_attr "length" "4")]) ++ ++(define_expand "insvsi" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (match_operand:SI 1 "immediate_operand" "I") ++ (match_operand:SI 2 "immediate_operand" "I")) ++ (match_operand:SI 3 "register_operand" "r"))] ++ "TARGET_HAS_BITFIELD" ++ " ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); ++ ++ if (len <= 0 || pos + len > 32) ++ FAIL; ++ ++ ;;if (!register_operand (operands[0], VOIDmode)) ++ ;; FAIL; ++ emit_insn (gen_insv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") ++ ++(define_insn "insv_32" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (match_operand:SI 1 "immediate_operand" "I") ++ (match_operand:SI 2 "immediate_operand" "I")) ++ (match_operand:SI 3 "register_operand" "r"))] ++ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0 ++ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" ++ "bsifi %0, %3, %1, %2" ++ [(set_attr "type" "bshift") ++ (set_attr "length" "4")]) ++ + (include "sync.md") +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch new file mode 100644 index 00000000..cd286818 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch @@ -0,0 +1,44 @@ +From 85273a514d0ab3b243b947633ab46705a0d946bc Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 23 Feb 2017 17:09:04 +0530 +Subject: [PATCH 25/54] Fixing the issue with the builtin_alloc. register r18 + was not properly handling the stack pattern which was resolved by using free + available register + +signed-off-by:nagaraju mekala +--- + gcc/config/microblaze/microblaze.md | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index a76287ab4fd..12270f135cf 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2075,10 +2075,10 @@ + "" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); +- rtx rtmp = gen_rtx_REG (SImode, R_TMP); ++ rtx reg = gen_reg_rtx (Pmode); + rtx neg_op0; + +- emit_move_insn (rtmp, retaddr); ++ emit_move_insn (reg, retaddr); + if (GET_CODE (operands[1]) != CONST_INT) + { + neg_op0 = gen_reg_rtx (Pmode); +@@ -2087,9 +2087,9 @@ + neg_op0 = GEN_INT (- INTVAL (operands[1])); + + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); +- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp); ++ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg); + emit_move_insn (operands[0], virtual_stack_dynamic_rtx); +- emit_insn (gen_rtx_CLOBBER (SImode, rtmp)); ++ emit_insn (gen_rtx_CLOBBER (SImode, reg)); + DONE; + } + ) +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch new file mode 100644 index 00000000..02cc5a1e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch @@ -0,0 +1,37 @@ +From aba85eba7bc5cc19edafe54379fb1f1794dc3844 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 4 Jun 2018 10:10:18 +0530 +Subject: [PATCH 26/54] Removed fsqrt generation for double values. + +--- + gcc/config/microblaze/microblaze.md | 14 -------------- + 1 file changed, 14 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 12270f135cf..b05f7da30b4 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -526,20 +526,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +-(define_insn "sqrtdf2" +- [(set (match_operand:DF 0 "register_operand" "=d") +- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" +- { +- if (REGNO (operands[0]) == REGNO (operands[1])) +- return "fsqrt\t%0,%1"; +- else +- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; +- } +- [(set_attr "type" "fsqrt") +- (set_attr "mode" "SF") +- (set_attr "length" "4")]) +- + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch new file mode 100644 index 00000000..c998d5eb --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch @@ -0,0 +1,784 @@ +From dd3eee641d2bf28216bf02f324cf8b81d4a61e43 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 13:56:52 +0530 +Subject: [PATCH 27/54] Intial commit of 64-bit Microblaze + + Conflicts: + gcc/config/microblaze/microblaze.md +--- + gcc/config/microblaze/constraints.md | 6 + + gcc/config/microblaze/microblaze-protos.h | 1 + + gcc/config/microblaze/microblaze.cc | 109 +++++-- + gcc/config/microblaze/microblaze.h | 4 +- + gcc/config/microblaze/microblaze.md | 352 +++++++++++++++++++++- + gcc/config/microblaze/microblaze.opt | 7 +- + gcc/config/microblaze/t-microblaze | 7 +- + 7 files changed, 456 insertions(+), 30 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index aae4be73ae3..26742d34980 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -52,6 +52,12 @@ + (and (match_code "const_int") + (match_test "ival > 0 && ival < 0x10000"))) + ++(define_constraint "K" ++ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." ++ (and (match_code "const_int") ++ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ ++ + ;; Define floating point constraints + + (define_constraint "G" +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index 41557af0f3c..0e9f783c4a4 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *); + extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); ++extern void microblaze_expand_conditional_branch_df (rtx *); + extern int microblaze_can_use_return_insn (void); + extern void print_operand (FILE *, rtx, int); + extern void print_operand_address (FILE *, rtx); +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index e28ab593c3e..7975bc182f2 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -3438,11 +3438,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + op0 = operands[0]; + op1 = operands[1]; + +- if (!register_operand (op0, SImode) +- && !register_operand (op1, SImode) ++ if (!register_operand (op0, mode) ++ && !register_operand (op1, mode) + && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0)) + { +- rtx temp = force_reg (SImode, op1); ++ rtx temp = force_reg (mode, op1); + emit_move_insn (op0, temp); + return true; + } +@@ -3511,12 +3511,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + && (flag_pic == 2 || microblaze_tls_symbol_p (p0) + || !SMALL_INT (p1))))) + { +- rtx temp = force_reg (SImode, p0); ++ rtx temp = force_reg (mode, p0); + rtx temp2 = p1; + + if (flag_pic && reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); +- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2)); ++ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2)); + return true; + } + } +@@ -3647,7 +3647,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); +@@ -3656,23 +3656,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + if (cmp_op1 == const0_rtx) + { + comp_reg = cmp_op0; +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + + else if (code == EQ || code == NE) + { + /* Use xor for equal/not-equal comparison. */ +- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); ++ else ++ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ else ++ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1)); + } + } + +@@ -3683,7 +3696,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) +@@ -3694,30 +3707,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), +- SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else if (code == EQ) + { +- emit_insn (gen_seq_internal_pat (comp_reg, +- cmp_op0, cmp_op1)); +- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + else if (code == NE) + { +- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, +- cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_NE (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare (condition, cmp_op0, +- cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ else ++ { ++ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ } ++ + } + } + +@@ -3734,6 +3780,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + emit_jump_insn (gen_condjump (condition, operands[3])); + } + ++void ++microblaze_expand_conditional_branch_df (rtx operands[]) ++{ ++ rtx condition; ++ rtx cmp_op0 = XEXP (operands[0], 0); ++ rtx cmp_op1 = XEXP (operands[0], 1); ++ rtx comp_reg = gen_reg_rtx (DImode); ++ ++ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); ++ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ emit_jump_insn (gen_long_condjump (condition, operands[3])); ++} ++ + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ + + static bool +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 94d96bf6b5d..f35f7075ce3 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; + #define ASM_SPEC "\ + %(target_asm_spec) \ + %{mbig-endian:-EB} \ ++%{m64:-m64} \ + %{mlittle-endian:-EL}" + + /* Extra switches sometimes passed to the linker. */ +@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe; + #define LINK_SPEC "%{shared:-shared} -N -relax \ + %{mbig-endian:-EB --oformat=elf32-microblaze} \ + %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ ++ %{m64:-EL --oformat=elf64-microblazeel} \ + %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ +@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe; + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 32 ++#define LONG_TYPE_SIZE 64 + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index b05f7da30b4..3f572fe2351 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -497,7 +497,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +- + (define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (div:SF (match_operand:SF 1 "register_operand" "d") +@@ -508,6 +507,7 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++ + (define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] +@@ -562,6 +562,18 @@ + + ;; Adding 2 DI operands in register or reg/imm + ++(define_insn "adddi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (match_operand:DI 2 "arith_plus_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ addlk\t%0,%z1,%2 ++ addlik\t%0,%z1,%2" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "adddi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") +@@ -606,6 +618,18 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + ++(define_insn "subdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "register_operand" "d,n")))] ++ "TARGET_MB_64" ++ "@ ++ rsubl\t%0,%2,%1 ++ addlik\t%0,%z1,-%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") +@@ -795,6 +819,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negdi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (neg:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "rsubl\t%0,%1,r0" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -814,6 +847,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "one_cmpldi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "xorli\t%0,%1,-1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "*one_cmpldi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -840,6 +882,20 @@ + ;; Logical + ;;---------------------------------------------------------------- + ++(define_insn "anddi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ andl\t%0,%1,%2 ++ andli\t%0,%1,%2 #andl1" ++ ;; andli\t%0,%1,%2 #andl3 ++ ;; andli\t%0,%1,%2 #andl2 ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -855,6 +911,18 @@ + (set_attr "length" "4,8,8,8")]) + + ++(define_insn "iordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ior:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ orl\t%0,%1,%2 ++ orli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -869,6 +937,19 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "xordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ xorl\t%0,%1,%2 ++ xorli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ ++ + (define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") +@@ -937,6 +1018,26 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++;;(define_expand "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] ++;; "TARGET_MB_64" ++;; { ++;; if (GET_CODE (operands[1]) != REG) ++;; FAIL; ++;; } ++;;) ++ ++ ++;;(define_insn "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] ++;; "TARGET_MB_64" ++;; "sextl8\t%0,%1" ++;; [(set_attr "type" "arith") ++;; (set_attr "mode" "DI") ++;; (set_attr "length" "4")]) ++ + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -946,6 +1047,16 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "sextl16\t%0,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++ + ;; Those for integer source operand are ordered + ;; widest source type first. + +@@ -1009,6 +1120,32 @@ + ) + + ++(define_insn "*movdi_internal_64" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") ++ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] ++ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1"; ++ case 1: ++ return "addlik\t%0,r0,%1"; ++ case 2: ++ return "addlk\t%0,r0,r0"; ++ case 3: ++ case 4: ++ return "lli\t%0,%1"; ++ case 5: ++ case 6: ++ return "sli\t%1,%0"; ++ } ++ return "unreachable"; ++ } ++ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8,8,8,8,12,8,12")]) ++ + + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") +@@ -1421,6 +1558,36 @@ + (set_attr "length" "4,4")] + ) + ++;; Barrel shift left ++(define_expand "ashldi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashldi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bsllli\t%0,%1,%2 ++ bslll\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++) + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1546,6 +1713,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "ashrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrai\t%0,%1,%2 ++ bslra\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -1655,6 +1852,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts (logical) + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "lshrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "lshrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrli\t%0,%1,%2 ++ bslrl\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") +@@ -1800,6 +2027,8 @@ + (set_attr "length" "4")] + ) + ++ ++ + ;;---------------------------------------------------------------- + ;; Setting a register from an floating point comparison. + ;;---------------------------------------------------------------- +@@ -1815,6 +2044,18 @@ + (set_attr "length" "4")] + ) + ++(define_insn "cstoredf4" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (match_operator:DI 1 "ordered_comparison_operator" ++ [(match_operand:DF 2 "register_operand" "r") ++ (match_operand:DF 3 "register_operand" "r")]))] ++ "TARGET_MB_64" ++ "dcmp.%C1\t%0,%3,%2" ++ [(set_attr "type" "fcmp") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")] ++) ++ + ;;---------------------------------------------------------------- + ;; Conditional branches + ;;---------------------------------------------------------------- +@@ -1927,6 +2168,115 @@ + (set_attr "length" "12")] + ) + ++ ++(define_expand "cbranchdi4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "arith_operand" "I,i")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdi4_reg" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_reg (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdf4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DF 1 "register_operand") ++ (match_operand:DF 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_df (operands); ++ DONE; ++ ++}) ++ ++;; Used to implement comparison instructions ++(define_expand "long_condjump" ++ [(set (pc) ++ (if_then_else (match_operand 0) ++ (label_ref (match_operand 1)) ++ (pc)))]) ++ ++(define_insn "long_branch_zero" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:DI 2 "pc_or_label_operand" "") ++ (match_operand:DI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "beal%C0i%?\t%z1,%2"; ++ else ++ return "beal%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt +index 37aaaf9ffda..96615a6d2c4 100644 +--- a/gcc/config/microblaze/microblaze.opt ++++ b/gcc/config/microblaze/microblaze.opt +@@ -136,4 +136,9 @@ Target + + mxl-frequency + Target Mask(AREA_OPTIMIZED_2) +-Use 8 stage pipeline (frequency optimization) ++Use 8 stage pipeline (frequency optimization). ++ ++m64 ++Target Mask(MB_64) ++MicroBlaze 64-bit mode. ++ +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 7e2fc5dcef8..4c25cfe15e7 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,8 +1,11 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian +-MULTILIB_DIRNAMES = bs m mh le ++MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 ++MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch new file mode 100644 index 00000000..58bb6fd8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch @@ -0,0 +1,2442 @@ +From fcec4be11de1c646bdcd6dcfc3844b7deb42898e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 14:38:48 +0530 +Subject: [PATCH 28/54] Intial commit for 64bit-MB sources. Need to cleanup the + code later. + +--- + gcc/config/microblaze/constraints.md | 2 +- + gcc/config/microblaze/microblaze-c.cc | 6 + + gcc/config/microblaze/microblaze.cc | 216 ++++++--- + gcc/config/microblaze/microblaze.h | 63 ++- + gcc/config/microblaze/microblaze.md | 605 ++++++++++++++++++------ + gcc/config/microblaze/t-microblaze | 3 +- + libgcc/config/microblaze/crti.S | 4 +- + libgcc/config/microblaze/crtn.S | 4 +- + libgcc/config/microblaze/divdi3.S | 98 ++++ + libgcc/config/microblaze/divdi3_table.c | 62 +++ + libgcc/config/microblaze/moddi3.S | 97 ++++ + libgcc/config/microblaze/muldi3.S | 73 +++ + libgcc/config/microblaze/t-microblaze | 11 +- + libgcc/config/microblaze/udivdi3.S | 107 +++++ + libgcc/config/microblaze/umoddi3.S | 110 +++++ + 15 files changed, 1229 insertions(+), 232 deletions(-) + create mode 100644 libgcc/config/microblaze/divdi3.S + create mode 100644 libgcc/config/microblaze/divdi3_table.c + create mode 100644 libgcc/config/microblaze/moddi3.S + create mode 100644 libgcc/config/microblaze/muldi3.S + create mode 100644 libgcc/config/microblaze/udivdi3.S + create mode 100644 libgcc/config/microblaze/umoddi3.S + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index 26742d34980..7bb1e0b4c8d 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -55,7 +55,7 @@ + (define_constraint "K" + "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) + + + ;; Define floating point constraints +diff --git a/gcc/config/microblaze/microblaze-c.cc b/gcc/config/microblaze/microblaze-c.cc +index 065351ad218..af73de0709c 100644 +--- a/gcc/config/microblaze/microblaze-c.cc ++++ b/gcc/config/microblaze/microblaze-c.cc +@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) + builtin_define ("HAVE_HW_FPU_SQRT"); + builtin_define ("__HAVE_HW_FPU_SQRT__"); + } ++ if (TARGET_MB_64) ++ { ++ builtin_define ("__arch64__"); ++ builtin_define ("__microblaze64__"); ++ builtin_define ("__MICROBLAZE64__"); ++ } + } +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 7975bc182f2..46bbf8a21e7 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -384,10 +384,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) + { + return 1; + } +- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) ++ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) + { + return 1; +- } ++ }*/ + else + return 0; + +@@ -435,7 +435,7 @@ double_memory_operand (rtx op, machine_mode mode) + return 1; + + return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT +- ? E_SImode : E_SFmode), ++ ? Pmode : E_SFmode), + plus_constant (Pmode, addr, 4)); + } + +@@ -682,7 +682,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) + /* Load the addend. */ + addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), + UNSPEC_TLS); +- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); ++ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend)); + dest = gen_rtx_PLUS (Pmode, dest, addend); + break; + +@@ -700,7 +700,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) + + if (XINT (x, 1) == UNSPEC_GOTOFF) + { +- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM); ++ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); + info->type = ADDRESS_GOTOFF; + } + else if (XINT (x, 1) == UNSPEC_PLT) +@@ -1308,8 +1308,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) + emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); + + /* Emit the test & branch. */ +- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src), ++ ++ if (TARGET_MB_64) { ++ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src), ++ src_reg, final_src, label)); ++ } ++ else { ++ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src), + src_reg, final_src, label)); ++ ++ } + + /* Mop up any left-over bytes. */ + if (leftover) +@@ -1639,14 +1647,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, + break; + + case E_DFmode: +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + if (!cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 2 << ((cum->arg_number - 1) * 2); + break; + + case E_DImode: + cum->gp_reg_found = 1; +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + break; + + case E_QImode: +@@ -2161,7 +2175,7 @@ compute_frame_size (HOST_WIDE_INT size) + + if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) + /* Don't account for link register. It is accounted specially below. */ +- gp_reg_size += GET_MODE_SIZE (SImode); ++ gp_reg_size += GET_MODE_SIZE (Pmode); + + mask |= (1L << (regno - GP_REG_FIRST)); + } +@@ -2430,7 +2444,7 @@ print_operand (FILE * file, rtx op, int letter) + + if ((letter == 'M' && !WORDS_BIG_ENDIAN) + || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') +- regnum++; ++ regnum++; + + fprintf (file, "%s", reg_names[regnum]); + } +@@ -2456,6 +2470,7 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2468,12 +2483,12 @@ print_operand (FILE * file, rtx op, int letter) + val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } +- else if (code == CONST_INT) ++ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val1[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); + } + else if (code == CONST_DOUBLE) + { +@@ -2667,7 +2682,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2690,7 +2708,10 @@ microblaze_asm_destructor (rtx symbol, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2756,7 +2777,7 @@ save_restore_insns (int prologue) + /* For interrupt_handlers, need to save/restore the MSR. */ + if (microblaze_is_interrupt_variant ()) + { +- isr_mem_rtx = gen_rtx_MEM (SImode, ++ isr_mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, base_reg_rtx, + GEN_INT (current_frame_info. + gp_offset - +@@ -2764,8 +2785,8 @@ save_restore_insns (int prologue) + + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (isr_mem_rtx) = 1; +- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG); +- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG); ++ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG); ++ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG); + } + + if (microblaze_is_interrupt_variant () && !prologue) +@@ -2773,8 +2794,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_reg_rtx, isr_mem_rtx); + emit_move_insn (isr_msr_rtx, isr_reg_rtx); + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) +@@ -2785,9 +2806,9 @@ save_restore_insns (int prologue) + /* Don't handle here. Already handled as the first register. */ + continue; + +- reg_rtx = gen_rtx_REG (SImode, regno); ++ reg_rtx = gen_rtx_REG (Pmode, regno); + insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset)); +- mem_rtx = gen_rtx_MEM (SImode, insn); ++ mem_rtx = gen_rtx_MEM (Pmode, insn); + if (microblaze_is_interrupt_variant () || save_volatiles) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +@@ -2802,7 +2823,7 @@ save_restore_insns (int prologue) + insn = emit_move_insn (reg_rtx, mem_rtx); + } + +- gp_offset += GET_MODE_SIZE (SImode); ++ gp_offset += GET_MODE_SIZE (Pmode); + } + } + +@@ -2812,8 +2833,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_mem_rtx, isr_reg_rtx); + + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + /* Done saving and restoring */ +@@ -2903,7 +2924,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) + + switch_to_section (s); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -3047,10 +3071,10 @@ microblaze_expand_prologue (void) + { + if (offset != 0) + ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); +- emit_move_insn (gen_rtx_MEM (SImode, ptr), +- gen_rtx_REG (SImode, regno)); ++ emit_move_insn (gen_rtx_MEM (Pmode, ptr), ++ gen_rtx_REG (Pmode, regno)); + +- offset += GET_MODE_SIZE (SImode); ++ offset += GET_MODE_SIZE (Pmode); + } + } + +@@ -3059,15 +3083,23 @@ microblaze_expand_prologue (void) + rtx fsiz_rtx = GEN_INT (fsiz); + + rtx_insn *insn = NULL; +- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ if (TARGET_MB_64) ++ { ++ ++ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, + fsiz_rtx)); ++ } ++ else { ++ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ fsiz_rtx)); ++ } + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + + /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */ + if (!crtl->is_leaf || interrupt_handler) + { +- mem_rtx = gen_rtx_MEM (SImode, ++ mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + const0_rtx)); + +@@ -3075,7 +3107,7 @@ microblaze_expand_prologue (void) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } +@@ -3185,12 +3217,12 @@ microblaze_expand_epilogue (void) + if (!crtl->is_leaf || interrupt_handler) + { + mem_rtx = +- gen_rtx_MEM (SImode, ++ gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); + if (interrupt_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + emit_move_insn (reg_rtx, mem_rtx); + } + +@@ -3206,15 +3238,25 @@ microblaze_expand_epilogue (void) + /* _restore_ registers for epilogue. */ + save_restore_insns (0); + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ else ++ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); + } + + if (crtl->calls_eh_return) +- emit_insn (gen_addsi3 (stack_pointer_rtx, ++ if (TARGET_MB_64) { ++ emit_insn (gen_adddi3 (stack_pointer_rtx, + stack_pointer_rtx, +- gen_raw_REG (SImode, ++ gen_raw_REG (Pmode, + MB_EH_STACKADJ_REGNUM))); +- ++ } ++ else { ++ emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ gen_raw_REG (Pmode, ++ MB_EH_STACKADJ_REGNUM))); ++ } + emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + } +@@ -3381,9 +3423,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + else + this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); + +- /* Apply the constant offset, if required. */ ++ /* Apply the constant offset, if required. */ + if (delta) +- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ { ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ } + + /* Apply the offset from the vtable, if required. */ + if (vcall_offset) +@@ -3396,7 +3443,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); + emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); + +- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1)); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); + } + + /* Generate a tail call to the target function. */ +@@ -3631,9 +3681,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + emit_block_move (m_tramp, assemble_trampoline_template (), + GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); + +- mem = adjust_address (m_tramp, SImode, 16); ++ mem = adjust_address (m_tramp, Pmode, 16); + emit_move_insn (mem, chain_value); +- mem = adjust_address (m_tramp, SImode, 20); ++ mem = adjust_address (m_tramp, Pmode, 20); + emit_move_insn (mem, fnaddr); + } + +@@ -3657,7 +3707,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) ++ if (mode == Pmode) + emit_jump_insn (gen_condjump (condition, label1)); + else + emit_jump_insn (gen_long_condjump (condition, label1)); +@@ -3776,7 +3826,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + rtx comp_reg = gen_reg_rtx (SImode); + + emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, operands[3])); + } + +@@ -3786,10 +3836,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + rtx condition; + rtx cmp_op0 = XEXP (operands[0], 0); + rtx cmp_op1 = XEXP (operands[0], 1); +- rtx comp_reg = gen_reg_rtx (DImode); ++ rtx comp_reg = gen_reg_rtx (Pmode); + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_long_condjump (condition, operands[3])); + } + +@@ -3810,8 +3860,8 @@ microblaze_expand_divide (rtx operands[]) + { + /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ + +- rtx regt1 = gen_reg_rtx (SImode); +- rtx reg18 = gen_rtx_REG (SImode, R_TMP); ++ rtx regt1 = gen_reg_rtx (Pmode); ++ rtx reg18 = gen_rtx_REG (Pmode, R_TMP); + rtx regqi = gen_reg_rtx (QImode); + rtx_code_label *div_label = gen_label_rtx (); + rtx_code_label *div_end_label = gen_label_rtx (); +@@ -3819,17 +3869,31 @@ microblaze_expand_divide (rtx operands[]) + rtx mem_rtx; + rtx ret; + rtx_insn *jump, *cjump, *insn; +- +- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); +- cjump = emit_jump_insn_after (gen_cbranchsi4 ( +- gen_rtx_GTU (SImode, regt1, GEN_INT (15)), ++ ++ if (TARGET_MB_64) { ++ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchdi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), ++ regt1, GEN_INT (15), div_label), insn); ++ } ++ else { ++ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchsi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), + regt1, GEN_INT (15), div_label), insn); ++ } + LABEL_NUSES (div_label) = 1; + JUMP_LABEL (cjump) = div_label; +- emit_insn (gen_rtx_CLOBBER (SImode, reg18)); ++ emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + +- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); +- emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ if (TARGET_MB_64) { ++ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_adddi3 (regt1, regt1, operands[2])); ++ } ++ else { ++ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ } + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + +@@ -3976,7 +4040,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) + { + insn = + emit_insn_before (gen_iprefetch +- (gen_int_mode (addr_offset, SImode)), ++ (gen_int_mode (addr_offset, Pmode)), + before_4); + recog_memoized (insn); + INSN_LOCATION (insn) = INSN_LOCATION (before_4); +@@ -3986,7 +4050,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) + } + } + } +- ++ ++/* Set the names for various arithmetic operations according to the ++ * MICROBLAZE ABI. */ ++static void ++microblaze_init_libfuncs (void) ++{ ++ set_optab_libfunc (smod_optab, SImode, "__modsi3"); ++ set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); ++ set_optab_libfunc (smul_optab, SImode, "__mulsi3"); ++ set_optab_libfunc (umod_optab, SImode, "__umodsi3"); ++ set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); ++ ++ if (TARGET_MB_64) ++ { ++ set_optab_libfunc (smod_optab, DImode, "__moddi3"); ++ set_optab_libfunc (sdiv_optab, DImode, "__divdi3"); ++ set_optab_libfunc (smul_optab, DImode, "__muldi3"); ++ set_optab_libfunc (umod_optab, DImode, "__umoddi3"); ++ set_optab_libfunc (udiv_optab, DImode, "__udivdi3"); ++ } ++} + /* Insert instruction prefetch instruction at the fall + through path of the function call. */ + +@@ -4139,6 +4223,17 @@ microblaze_starting_frame_offset (void) + #undef TARGET_LRA_P + #define TARGET_LRA_P hook_bool_void_false + ++#ifdef TARGET_MB_64 ++#undef TARGET_ASM_ALIGNED_DI_OP ++#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" ++ ++#undef TARGET_ASM_ALIGNED_HI_OP ++#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" ++ ++#undef TARGET_ASM_ALIGNED_SI_OP ++#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" ++#endif ++ + #undef TARGET_FRAME_POINTER_REQUIRED + #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required + +@@ -4148,6 +4243,9 @@ microblaze_starting_frame_offset (void) + #undef TARGET_TRAMPOLINE_INIT + #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init + ++#undef TARGET_INIT_LIBFUNCS ++#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs ++ + #undef TARGET_PROMOTE_FUNCTION_MODE + #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index f35f7075ce3..3aee003de0d 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; + + /* Generate DWARF exception handling info. */ + #define DWARF2_UNWIND_INFO 1 +- + /* Don't generate .loc operations. */ + #define DWARF2_ASM_LINE_DEBUG_INFO 0 + +@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe; + ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr) + + /* Use DWARF 2 debugging information by default. */ +-#define DWARF2_DEBUGGING_INFO ++#define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG ++#define DWARF2_ADDR_SIZE 4 + + /* Target machine storage layout */ + + #define BITS_BIG_ENDIAN 0 + #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) + #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) +-#define BITS_PER_WORD 32 +-#define UNITS_PER_WORD 4 ++//#define BITS_PER_WORD 64 ++//Revisit ++#define MAX_BITS_PER_WORD 64 ++#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define UNITS_PER_WORD 4 + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 64 ++#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32) + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 + #define LONG_DOUBLE_TYPE_SIZE 64 +-#define POINTER_SIZE 32 +-#define PARM_BOUNDARY 32 +-#define FUNCTION_BOUNDARY 32 +-#define EMPTY_FIELD_BOUNDARY 32 ++#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32) ++//#define WIDEST_HARDWARE_FP_SIZE 64 ++//#define POINTERS_EXTEND_UNSIGNED 1 ++#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32) + #define STRUCTURE_SIZE_BOUNDARY 8 +-#define BIGGEST_ALIGNMENT 32 ++#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + #define STRICT_ALIGNMENT 1 + #define PCC_BITFIELD_TYPE_MATTERS 1 + ++//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode) + #undef SIZE_TYPE +-#define SIZE_TYPE "unsigned int" ++#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #undef PTRDIFF_TYPE +-#define PTRDIFF_TYPE "int" ++#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int") ++ ++/*#undef INTPTR_TYPE ++#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/ ++#undef UINTPTR_TYPE ++#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #define DATA_ALIGNMENT(TYPE, ALIGN) \ + ((((ALIGN) < BITS_PER_WORD) \ +@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +- ++/* + #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < 4) \ +- (MODE) = SImode; +- ++ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ ++ (MODE) = TARGET_MB_64 ? DImode : SImode; ++*/ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info; + #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) + + #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 ++#define DWARF_CIE_DATA_ALIGNMENT -1 + + #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) + + #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + +-#define STACK_BOUNDARY 32 ++#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) + ++#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++ + #define NUM_OF_ARGS 6 + + #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) +@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info; + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + + #define LIBCALL_VALUE(MODE) \ ++ gen_rtx_REG (MODE,GP_RETURN) ++ ++/*#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +- ++*/ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -500,7 +518,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 32 ++#define TRAMPOLINE_ALIGNMENT 64 + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +@@ -529,13 +547,13 @@ typedef struct microblaze_args + addresses which require two reload registers. */ + #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) + +-#define CASE_VECTOR_MODE (SImode) ++#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode) + + #ifndef DEFAULT_SIGNED_CHAR + #define DEFAULT_SIGNED_CHAR 1 + #endif + +-#define MOVE_MAX 4 ++#define MOVE_MAX (TARGET_MB_64 ? 8 : 4) + #define MAX_MOVE_MAX 8 + + #define SLOW_BYTE_ACCESS 1 +@@ -545,7 +563,7 @@ typedef struct microblaze_args + + #define SHIFT_COUNT_TRUNCATED 1 + +-#define Pmode SImode ++#define Pmode (TARGET_MB_64? DImode:SImode) + + #define FUNCTION_MODE SImode + +@@ -707,6 +725,7 @@ do { \ + + #undef TARGET_ASM_OUTPUT_IDENT + #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident ++//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive + + /* Default to -G 8 */ + #ifndef MICROBLAZE_DEFAULT_GVALUE +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 3f572fe2351..97da9aad6fd 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -26,6 +26,7 @@ + ;; Constants + ;;---------------------------------------------------- + (define_constants [ ++ (R_Z 0) ;; For reg r0 + (R_SP 1) ;; Stack pointer reg + (R_SR 15) ;; Sub-routine return addr reg + (R_IR 14) ;; Interrupt return addr reg +@@ -541,6 +542,7 @@ + + ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] + ;; Leave carry as is ++ + (define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") +@@ -562,23 +564,38 @@ + + ;; Adding 2 DI operands in register or reg/imm + +-(define_insn "adddi3_long" ++(define_expand "adddi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (plus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_plus_operand" "")))] ++"" ++{ ++ if (TARGET_MB_64) ++ { ++ if (GET_CODE (operands[2]) == CONST_INT && ++ INTVAL(operands[2]) < (long)-549755813888 && ++ INTVAL(operands[2]) > (long)549755813887) ++ FAIL; ++ } ++}) ++ ++(define_insn "*adddi3_long" + [(set (match_operand:DI 0 "register_operand" "=d,d") +- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_plus_operand" "d,K")))] + "TARGET_MB_64" + "@ +- addlk\t%0,%z1,%2 +- addlik\t%0,%z1,%2" +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") ++ addlk\t%0,%1,%2 ++ addlik\t%0,%1,%2 #N10" ++ [(set_attr "type" "darith,no_delay_arith") ++ (set_attr "mode" "DI") + (set_attr "length" "4,4")]) + +-(define_insn "adddi3" ++(define_insn "*adddi3_all" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_operand" "d,i")))] +- "" ++ "!TARGET_MB_64" + "@ + add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 + addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" +@@ -605,7 +622,7 @@ + (define_insn "iprefetch" + [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) + (clobber (mem:BLK (scratch)))] +- "TARGET_PREFETCH" ++ "TARGET_PREFETCH && !TARGET_MB_64" + { + operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + return "mfs\t%2,rpc\n\twic\t%2,r0"; +@@ -618,23 +635,33 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + +-(define_insn "subdi3_long" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (minus:DI (match_operand:DI 1 "register_operand" "d,d") +- (match_operand:DI 2 "register_operand" "d,n")))] ++(define_expand "subdi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (minus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_operand" "")))] ++"" ++" ++{ ++}") ++ ++(define_insn "subsidi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,n")))] + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addlik\t%0,%z1,-%2" +- [(set_attr "type" "darith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ addik\t%0,%z1,-%2 ++ addik\t%0,%z1,-%2" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,4")]) + +-(define_insn "subdi3" ++(define_insn "subdi3_small" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "" ++ "!TARGET_MB_64" + "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" + [(set_attr "type" "darith") + (set_attr "mode" "DI") +@@ -663,7 +690,7 @@ + (mult:DI + (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -674,7 +701,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -685,7 +712,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -789,7 +816,7 @@ + (match_operand:SI 4 "arith_operand")]) + (label_ref (match_operand 5)) + (pc)))] +- "TARGET_HARD_FLOAT" ++ "TARGET_HARD_FLOAT && !TARGET_MB_64" + [(set (match_dup 1) (match_dup 3))] + + { +@@ -819,6 +846,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negsi_long" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (neg:SI (match_operand:DI 1 "register_operand" "d")))] ++ "" ++ "rsubk\t%0,%1,r0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2_long" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -847,16 +883,24 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_insn "one_cmpldi2_long" ++(define_expand "one_cmpldi2" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (not:DI (match_operand:DI 1 "register_operand" "")))] ++ "" ++ " ++{ ++}") ++ ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") +- (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ (not:DI (match_operand:DI 1 "arith_operand" "d")))] + "TARGET_MB_64" + "xorli\t%0,%1,-1" +- [(set_attr "type" "arith") ++ [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +-(define_insn "*one_cmpldi2" ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] + "" +@@ -871,7 +915,8 @@ + (not:DI (match_operand:DI 1 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) +- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" ++ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) ++ && !TARGET_MB_64" + + [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) + (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] +@@ -883,18 +928,17 @@ + ;;---------------------------------------------------------------- + + (define_insn "anddi3" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (and:DI (match_operand:DI 1 "arith_operand" "d,d") +- (match_operand:DI 2 "arith_operand" "d,K")))] ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,I")))] + "TARGET_MB_64" + "@ + andl\t%0,%1,%2 +- andli\t%0,%1,%2 #andl1" +- ;; andli\t%0,%1,%2 #andl3 +- ;; andli\t%0,%1,%2 #andl2 +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ andli\t%0,%1,%2 #andl2 ++ andli\t%0,%1,%2 #andl3" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI,DI,DI") ++ (set_attr "length" "4,4,4")]) + + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") +@@ -919,7 +963,7 @@ + "@ + orl\t%0,%1,%2 + orli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -945,7 +989,7 @@ + "@ + xorl\t%0,%1,%2 + xorli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -1018,26 +1062,6 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-;;(define_expand "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] +-;; "TARGET_MB_64" +-;; { +-;; if (GET_CODE (operands[1]) != REG) +-;; FAIL; +-;; } +-;;) +- +- +-;;(define_insn "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] +-;; "TARGET_MB_64" +-;; "sextl8\t%0,%1" +-;; [(set_attr "type" "arith") +-;; (set_attr "mode" "DI") +-;; (set_attr "length" "4")]) +- + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -1060,6 +1084,27 @@ + ;; Those for integer source operand are ordered + ;; widest source type first. + ++(define_insn "extendsidi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "sextl32\t%0,%1"; ++ case 1: ++ case 2: ++ { ++ output_asm_insn ("ll%i1\t%0,%1", operands); ++ return "sextl32\t%0,%0"; ++ } ++ } ++ } ++ [(set_attr "type" "multi,multi,multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,8,8")]) ++ + (define_insn "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] +@@ -1088,69 +1133,118 @@ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. ++;; //} + + (define_expand "movdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + { +- /* If operands[1] is a constant address illegal for pic, then we need to +- handle it just like microblaze_legitimize_address does. */ +- if (flag_pic && pic_address_needs_scratch (operands[1])) ++ if (TARGET_MB_64) + { ++ if (microblaze_expand_move (DImode, operands)) DONE; ++ } ++ else ++ { ++ /* If operands[1] is a constant address illegal for pic, then we need to ++ handle it just like microblaze_legitimize_address does. */ ++ if (flag_pic && pic_address_needs_scratch (operands[1])) ++ { + rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2)); + DONE; +- } +- +- +- if ((reload_in_progress | reload_completed) == 0 +- && !register_operand (operands[0], DImode) +- && !register_operand (operands[1], DImode) +- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) +- && operands[1] != CONST0_RTX (DImode)))) +- { ++ } + +- rtx temp = force_reg (DImode, operands[1]); +- emit_move_insn (operands[0], temp); +- DONE; ++ if ((reload_in_progress | reload_completed) == 0 ++ && !register_operand (operands[0], DImode) ++ && !register_operand (operands[1], DImode) ++ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) ++ && operands[1] != CONST0_RTX (DImode)))) ++ { ++ rtx temp = force_reg (DImode, operands[1]); ++ emit_move_insn (operands[0], temp); ++ DONE; ++ } + } + } + ) + ++;; Added for status registers ++(define_insn "movdi_status" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,z") ++ (match_operand:DI 1 "register_operand" "z,d,d"))] ++ "microblaze_is_interrupt_variant () && TARGET_MB_64" ++ "@ ++ mfs\t%0,%1 #mfs ++ addlk\t%0,%1,r0 #add movdi ++ mts\t%0,%1 #mts" ++ [(set_attr "type" "move") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) ++ ++;; This move will be not be moved to delay slot. ++(define_insn "*movdi_internal3" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") ++ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] ++ "TARGET_MB_64 && (register_operand (operands[0], DImode) && ++ (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" ++ "@ ++ addlk\t%0,r0,r0\t ++ addlik\t%0,r0,%1\t #N1 %X1 ++ addlik\t%0,r0,%1\t #N2 %X1" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) + +-(define_insn "*movdi_internal_64" +- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") +- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] +- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++;; This move may be used for PLT label operand ++(define_insn "*movdi_internal5_pltop" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (match_operand:DI 1 "call_insn_operand" ""))] ++ "TARGET_MB_64 && (register_operand (operands[0], Pmode) && ++ PLT_ADDR_P (operands[1]))" ++ { ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "load") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++(define_insn "*movdi_internal2" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64" + { + switch (which_alternative) + { + case 0: +- return "addlk\t%0,%1"; +- case 1: +- return "addlik\t%0,r0,%1"; +- case 2: +- return "addlk\t%0,r0,r0"; +- case 3: +- case 4: +- return "lli\t%0,%1"; +- case 5: +- case 6: +- return "sli\t%1,%0"; +- } +- return "unreachable"; +- } +- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") + (set_attr "mode" "DI") +- (set_attr "length" "8,8,8,8,12,8,12")]) ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + + + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +- "" ++ "!TARGET_MB_64" + { + switch (which_alternative) + { +@@ -1182,7 +1276,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))" ++ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] +@@ -1194,12 +1289,22 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") + ++(define_insn "movdi_long_int" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") ++ (match_operand:DI 1 "general_operand" "i"))] ++ "" ++ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) ++ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. +@@ -1271,6 +1376,8 @@ + (set_attr "length" "4,4,8,4,8,4,8")]) + + ++ ++ + ;; 16-bit Integer moves + + ;; Unlike most other insns, the move insns can't be split with +@@ -1303,8 +1410,8 @@ + "@ + addik\t%0,r0,%1\t# %X1 + addk\t%0,%1,r0 +- lhui\t%0,%1 +- lhui\t%0,%1 ++ lhu%i1\t%0,%1 ++ lhu%i1\t%0,%1 + sh%i0\t%z1,%0 + sh%i0\t%z1,%0" + [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") +@@ -1347,7 +1454,7 @@ + lbu%i1\t%0,%1 + lbu%i1\t%0,%1 + sb%i0\t%z1,%0 +- sbi\t%z1,%0" ++ sb%i0\t%z1,%0" + [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") + (set_attr "mode" "QI") + (set_attr "length" "4,4,8,4,8,4,8")]) +@@ -1420,7 +1527,7 @@ + addik\t%0,r0,%F1 + lw%i1\t%0,%1 + sw%i0\t%z1,%0 +- swi\t%z1,%0" ++ sw%i0\t%z1,%0" + [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") + (set_attr "mode" "SF") + (set_attr "length" "4,4,4,4,4,4,4")]) +@@ -1459,6 +1566,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") + (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] +@@ -1493,7 +1627,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] + "") +@@ -1504,7 +1639,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") +@@ -2003,6 +2139,31 @@ else + " + ) + ++ ++(define_insn "seq_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (eq:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmpleq\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "sne_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (ne:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmplne\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ + (define_insn "seq_internal_pat" + [(set (match_operand:SI 0 "register_operand" "=d") + (eq:SI +@@ -2063,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "arith_operand" "I,i")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +@@ -2076,13 +2237,13 @@ else + (define_expand "cbranchsi4_reg" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "register_operand")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "register_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" + { +- microblaze_expand_conditional_branch_reg (SImode, operands); ++ microblaze_expand_conditional_branch_reg (Pmode, operands); + DONE; + }) + +@@ -2107,6 +2268,26 @@ else + (label_ref (match_operand 1)) + (pc)))]) + ++(define_insn "branch_zero64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand 2 "pc_or_label_operand" "") ++ (match_operand 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ + (define_insn "branch_zero" + [(set (pc) + (if_then_else (match_operator:SI 0 "ordered_comparison_operator" +@@ -2127,6 +2308,47 @@ else + (set_attr "length" "4")] + ) + ++(define_insn "branch_compare64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:SI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmp\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmpu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmp\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmpu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); ++ return "bea%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2310,7 +2532,7 @@ else + ;; Indirect jumps. Jump to register values. Assuming absolute jumps + + (define_insn "indirect_jump_internal1" +- [(set (pc) (match_operand:SI 0 "register_operand" "d"))] ++ [(set (pc) (match_operand 0 "register_operand" "d"))] + "" + "bra%?\t%0" + [(set_attr "type" "jump") +@@ -2323,7 +2545,7 @@ else + (use (label_ref (match_operand 1 "" "")))] + "" + { +- gcc_assert (GET_MODE (operands[0]) == Pmode); ++ //gcc_assert (GET_MODE (operands[0]) == Pmode); + + if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +@@ -2335,7 +2557,7 @@ else + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand:SI 0 "register_operand" "d")) ++ (match_operand 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2345,9 +2567,9 @@ else + + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus:SI (match_operand:SI 0 "register_operand" "d") +- (label_ref:SI (match_operand:SI 1 "" "")))) +- (use (label_ref:SI (match_dup 1)))])] ++ (plus (match_operand 0 "register_operand" "d") ++ (label_ref (match_operand:SI 1 "" "")))) ++ (use (label_ref (match_dup 1)))])] + "" + "" + ) +@@ -2408,7 +2630,7 @@ else + (minus (reg 1) (match_operand 1 "register_operand" ""))) + (set (reg 1) + (minus (reg 1) (match_dup 1)))] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx reg = gen_reg_rtx (Pmode); +@@ -2433,7 +2655,7 @@ else + (define_expand "save_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + emit_move_insn (operands[0], operands[1]); + DONE; +@@ -2443,7 +2665,7 @@ else + (define_expand "restore_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx rtmp = gen_rtx_REG (SImode, R_TMP); +@@ -2490,7 +2712,7 @@ else + + (define_insn "_internal" + [(any_return) +- (use (match_operand:SI 0 "register_operand" ""))] ++ (use (match_operand 0 "register_operand" ""))] + "" + { + if (microblaze_is_break_handler ()) +@@ -2523,7 +2745,7 @@ else + (define_expand "call" + [(parallel [(call (match_operand 0 "memory_operand" "m") + (match_operand 1 "" "i")) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 2 "" "")) + (use (match_operand 3 "" ""))])] + "" +@@ -2544,12 +2766,12 @@ else + + if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) + emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_internal0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2559,7 +2781,7 @@ else + (define_expand "call_internal0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" ""))])] ++ (clobber (match_operand 2 "" ""))])] + "" + { + } +@@ -2568,18 +2790,34 @@ else + (define_expand "call_internal_plt0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" "")) +- (use (match_operand:SI 3 "" ""))])] ++ (clobber (match_operand 2 "" "")) ++ (use (match_operand 3 "" ""))])] + "" + { + } + ) + ++(define_insn "call_internal_plt_64" ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal_plt" +- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" "")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR)) +- (use (reg:SI R_GOT))] ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] + "flag_pic" + { + rtx target2 +@@ -2591,10 +2829,41 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_internal1_64" ++ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[0]; ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ if (GET_CODE (target) == SYMBOL_REF) { ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "breaki\tr16,%0\;%#"; ++ } ++ else { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ } else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%0\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%0\;%#"; ++ else { ++ fprintf (stderr,"Unsupported call insn\n"); ++ return NULL; ++ } ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal1" + [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR))] ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] + "" + { + rtx target = operands[0]; +@@ -2628,7 +2897,7 @@ else + [(parallel [(set (match_operand 0 "register_operand" "=d") + (call (match_operand 1 "memory_operand" "m") + (match_operand 2 "" "i"))) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 3 "" ""))])] ;; next_arg_reg + "" + { +@@ -2649,13 +2918,13 @@ else + if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) + emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_value_internal (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2667,7 +2936,7 @@ else + [(parallel [(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) ++ (clobber (match_operand 3 "" "")) + ])] + "" + {} +@@ -2677,18 +2946,35 @@ else + [(parallel[(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) +- (use (match_operand:SI 4 "" ""))])] ++ (clobber (match_operand 3 "" "")) ++ (use (match_operand 4 "" ""))])] + "flag_pic" + {} + ) + ++(define_insn "call_value_intern_plt_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ return "brealid\tr15,%1\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern_plt" + [(set (match_operand:VOID 0 "register_operand" "=d") +- (call (mem (match_operand:SI 1 "call_insn_plt_operand" "")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d")) +- (use (match_operand:SI 4 "register_operand"))] ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] + "flag_pic" + { + rtx target2 +@@ -2701,11 +2987,46 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_value_intern_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[1]; ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ if (GET_CODE (target) == SYMBOL_REF) ++ { ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) ++ return "breaki\tr16,%1\;%#"; ++ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION) ++ { ++ return "brealid\tr15,%1\;%#"; ++ } ++ else ++ { ++ return "bralid\tr15,%1\;%#"; ++ } ++ } ++ else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%1\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%1\;%#"; ++ else ++ return "Unsupported call insn\n"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern" + [(set (match_operand:VOID 0 "register_operand" "=d") + (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d"))] ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] + "" + { + rtx target = operands[1]; +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 4c25cfe15e7..965132b3513 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -2,7 +2,8 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en + MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian + MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index 0f24adb750d..1a89a0a2ffa 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -40,7 +40,7 @@ + + .align 2 + __init: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 + la r11, r0, _stack + mts rshr, r11 +@@ -51,5 +51,5 @@ __init: + .global __fini + .align 2 + __fini: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index d38d7ab9f98..29a004973ae 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -33,9 +33,9 @@ + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 + + .section .fini, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 +diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S +new file mode 100644 +index 00000000000..d37bf5165c6 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3.S +@@ -0,0 +1,98 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# divdi3.S ++# ++# Divide operation for 32 bit integers. ++# Input : Dividend in Reg r5 ++# Divisor in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __divdi3 ++ .ent __divdi3 ++ .type __divdi3,@function ++__divdi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ XORL r28,r5,r6 # Get the sign of the result ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r30,r0,0 # Clear mod ++ ADDLIK r3,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ RSUBLI r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ nop ++.end __divdi3 ++ .size __divdi3, . - __divdi3 ++#endif +diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c +new file mode 100644 +index 00000000000..80962597ea5 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3_table.c +@@ -0,0 +1,62 @@ ++/* Table for software lookup divide for Xilinx MicroBlaze. ++ ++ Copyright (C) 2009-2017 Free Software Foundation, Inc. ++ ++ Contributed by Michael Eager . ++ ++ This file is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by the ++ Free Software Foundation; either version 3, or (at your option) any ++ later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++ ++unsigned char _divdi3_table[] = ++{ ++ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7, ++ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15, ++ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ++ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15, ++ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7, ++ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15, ++ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7, ++ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15, ++ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7, ++ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15, ++ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7, ++ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15, ++ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7, ++ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15, ++ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7, ++ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15, ++ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7, ++ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15, ++ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7, ++ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15, ++ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7, ++ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15, ++ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7, ++ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15, ++ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7, ++ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15, ++ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7, ++ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15, ++ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7, ++ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15, ++ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7, ++ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15, ++}; ++ +diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S +new file mode 100644 +index 00000000000..5d3f7c03fc8 +--- /dev/null ++++ b/libgcc/config/microblaze/moddi3.S +@@ -0,0 +1,97 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# moddi3.S ++# ++# modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __moddi3 ++ .ent __moddi3 ++ .type __moddi3,@function ++__moddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,32 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r3,r0,0 # Clear mod ++ ADDLIK r30,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++ # First part try to find the first '1' in the r5 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r30 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ rsubli r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addlik r1,r1,32 ++ rtsd r15,8 ++ nop ++ .end __moddi3 ++ .size __moddi3, . - __moddi3 ++#endif +diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S +new file mode 100644 +index 00000000000..567784197d3 +--- /dev/null ++++ b/libgcc/config/microblaze/muldi3.S +@@ -0,0 +1,73 @@ ++/*###################################-*-asm*- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# muldi3.S ++# ++# Multiply operation for 32 bit integers. ++# Input : Operand1 in Reg r5 ++# Operand2 in Reg r6 ++# Output: Result [op1 * op2] in Reg r3 ++# ++#######################################*/ ++ ++#ifdef __arch64__ ++ .globl __muldi3 ++ .ent __muldi3 ++ .type __muldi3,@function ++__muldi3: ++ .frame r1,0,r15 ++ addl r3,r0,r0 ++ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ XORL r4,r5,r6 # Get the sign of the result ++ BEALGEI r5,$L_R5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEALGEI r6,$L_R6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ addl r5,r5,r5 ++$L1: ++ srll r6,r6 ++ addlc r7,r0,r0 ++ bealeqi r7,$L2 ++ addl r3,r3,r5 ++ bealnei r6,$L2 ++ beallti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rsubl r3,r3,r0 ++ rtsd r15,8 ++ nop ++$L_Result_Is_Zero: ++ addli r3,r0,0 ++ rtsd r15,8 ++ nop ++ .end __muldi3 ++ .size __muldi3, . - __muldi3 ++#endif +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 8d954a49575..35021b24b7d 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,11 +1,16 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ ++ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ ++ $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/muldi3_hard.S \ ++ $(srcdir)/config/microblaze/moddi3.S \ + $(srcdir)/config/microblaze/mulsi3.S \ ++ $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ ++ $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c ++ $(srcdir)/config/microblaze/umoddi3.S \ ++ $(srcdir)/config/microblaze/divsi3_table.c \ +diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S +new file mode 100644 +index 00000000000..c210fbc7128 +--- /dev/null ++++ b/libgcc/config/microblaze/udivdi3.S +@@ -0,0 +1,107 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# udivdi3.S ++# ++# Unsigned divide operation. ++# Input : Divisor in Reg r5 ++# Dividend in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __udivdi3 ++ .ent __udivdi3 ++ .type __udivdi3,@function ++__udivdi3: ++ .frame r1,0,r15 ++ ++ ADDlIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r30,r0,0 # Clear mod ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # Check if r6 and r5 are equal # if yes, return 1 ++ RSUBL r18,r5,r6 ++ ADDLIK r3,r0,1 ++ BEALEQI r18,$LaRETURN_HERE ++ ++ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 ++ XORL r18,r5,r6 ++ ADDL r3,r0,r0 # We would anyways clear r3 ++ BEALGEI r18,$LRSUBL ++ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++$LRSUBL: ++ RSUBL r18,r6,r5 # MICROBLAZEcmp ++ BEALLTI r18,$LaRETURN_HERE ++ ++ # If r6 [bit 31] is set, then return result as 1 ++$LCheckr6: ++ BEALGTI r6,$LaDIV0 ++ ADDLIK r3,r0,1 ++ BREAI $LaRETURN_HERE ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDLIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++ .end __udivdi3 ++ .size __udivdi3, . - __udivdi3 ++#endif +diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S +new file mode 100644 +index 00000000000..7f5cd23f9a1 +--- /dev/null ++++ b/libgcc/config/microblaze/umoddi3.S +@@ -0,0 +1,110 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# umoddi3.S ++# ++# Unsigned modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __umoddi3 ++ .ent __umoddi3 ++ .type __umoddi3,@function ++__umoddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-24 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r3,r0,0 # Clear div ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r30,r0,0 # clear mod ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++# Check if r6 and r5 are equal # if yes, return 0 ++ rsubl r18,r5,r6 ++ bealeqi r18,$LaRETURN_HERE ++ ++# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 ++ xorl r18,r5,r6 ++ addlik r3,r5,0 ++ bealgei r18,$LRSUB ++ beallti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++$LRSUB: ++ rsubl r18,r5,r6 # MICROBLAZEcmp ++ bealgti r18,$LaRETURN_HERE ++ ++# If r6 [bit 31] is set, then return result as r5-r6 ++$LCheckr6: ++ addlik r3,r0,0 ++ bealgti r6,$LaDIV0 ++ addlik r18,r0,0x7fffffff ++ andl r5,r5,r18 ++ andl r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsubl r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++.end __umoddi3 ++ .size __umoddi3, . - __umoddi3 ++#endif +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch new file mode 100644 index 00000000..448e850f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch @@ -0,0 +1,268 @@ +From 870bfd716fcddeb72660f3176fb2a68aaa5ecc0e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 14:45:15 +0530 +Subject: [PATCH 29/54] re-arrangement of the compare branches + +--- + gcc/config/microblaze/microblaze.cc | 28 ++---- + gcc/config/microblaze/microblaze.md | 141 +++++++++++++--------------- + 2 files changed, 73 insertions(+), 96 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 46bbf8a21e7..de3c95a005e 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -3707,11 +3707,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == Pmode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); +- ++ emit_jump_insn (gen_condjump (condition, label1)); + } + + else if (code == EQ || code == NE) +@@ -3722,10 +3718,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + else + emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3758,10 +3751,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), + mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else if (code == EQ) + { +@@ -3776,10 +3766,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + + } + else if (code == NE) +@@ -3795,10 +3782,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_NE (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3840,7 +3824,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); + condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); +- emit_jump_insn (gen_long_condjump (condition, operands[3])); ++ emit_jump_insn (gen_condjump (condition, operands[3])); + } + + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 97da9aad6fd..31bf04e4abd 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2268,7 +2268,27 @@ else + (label_ref (match_operand 1)) + (pc)))]) + +-(define_insn "branch_zero64" ++(define_insn "branch_zero_64" ++ [(set (pc) ++ (if_then_else (match_operator:SI 0 "ordered_comparison_operator" ++ [(match_operand:SI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:SI 2 "pc_or_label_operand" "") ++ (match_operand:SI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_zero" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand 1 "register_operand" "d") +@@ -2279,9 +2299,9 @@ else + "TARGET_MB_64" + { + if (operands[3] == pc_rtx) +- return "bea%C0i%?\t%z1,%2"; ++ return "beal%C0i%?\t%z1,%2"; + else +- return "bea%N0i%?\t%z1,%3"; ++ return "beal%N0i%?\t%z1,%3"; + } + [(set_attr "type" "branch") + (set_attr "mode" "none") +@@ -2310,9 +2330,9 @@ else + + (define_insn "branch_compare64" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:SI 0 "cmp_op" ++ [(match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2349,6 +2369,47 @@ else + (set_attr "length" "12")] + ) + ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2431,74 +2492,6 @@ else + + }) + +-;; Used to implement comparison instructions +-(define_expand "long_condjump" +- [(set (pc) +- (if_then_else (match_operand 0) +- (label_ref (match_operand 1)) +- (pc)))]) +- +-(define_insn "long_branch_zero" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "ordered_comparison_operator" +- [(match_operand:DI 1 "register_operand" "d") +- (const_int 0)]) +- (match_operand:DI 2 "pc_or_label_operand" "") +- (match_operand:DI 3 "pc_or_label_operand" ""))) +- ] +- "TARGET_MB_64" +- { +- if (operands[3] == pc_rtx) +- return "beal%C0i%?\t%z1,%2"; +- else +- return "beal%N0i%?\t%z1,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "4")] +-) +- +-(define_insn "long_branch_compare" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "cmp_op" +- [(match_operand:DI 1 "register_operand" "d") +- (match_operand:DI 2 "register_operand" "d") +- ]) +- (label_ref (match_operand 3)) +- (pc))) +- (clobber(reg:DI R_TMP))] +- "TARGET_MB_64" +- { +- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); +- enum rtx_code code = GET_CODE (operands[0]); +- +- if (code == GT || code == LE) +- { +- output_asm_insn ("cmpl\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GTU || code == LEU) +- { +- output_asm_insn ("cmplu\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GE || code == LT) +- { +- output_asm_insn ("cmpl\tr18,%z2,%z1", operands); +- } +- else if (code == GEU || code == LTU) +- { +- output_asm_insn ("cmplu\tr18,%z2,%z1", operands); +- } +- +- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); +- return "beal%C0i%?\tr18,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "12")] +-) +- + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch new file mode 100644 index 00000000..92951b08 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch @@ -0,0 +1,28 @@ +From e4713a382c1e6729cd3228284def9fa59da70028 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 8 Aug 2018 17:37:26 +0530 +Subject: [PATCH 30/54] previous commit broke the handling of SI Branch compare + for Microblaze 32-bit.. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 31bf04e4abd..e37a7704195 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2224,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand 1 "register_operand") +- (match_operand 2 "arith_operand" "I,i")]) ++ [(match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch new file mode 100644 index 00000000..40009bf0 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch @@ -0,0 +1,77 @@ +From 0673e986a5c06cba6507e0361ebdb9cf309f6a4c Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 11 Sep 2018 13:43:48 +0530 +Subject: [PATCH 31/54] Support of multilibs with m64 ... + +Conflicts: + gcc/config/microblaze/microblaze-c.c + +signed-off-by : Mahesh Bodapati +--- + gcc/config/microblaze/microblaze-c.cc | 1 + + gcc/config/microblaze/t-microblaze | 15 ++++++--------- + libgcc/config/microblaze/t-microblaze | 11 +++-------- + 3 files changed, 10 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-c.cc b/gcc/config/microblaze/microblaze-c.cc +index af73de0709c..c7cb139d25a 100644 +--- a/gcc/config/microblaze/microblaze-c.cc ++++ b/gcc/config/microblaze/microblaze-c.cc +@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) + } + if (TARGET_MB_64) + { ++ builtin_define ("__microblaze64"); + builtin_define ("__arch64__"); + builtin_define ("__microblaze64__"); + builtin_define ("__MICROBLAZE64__"); +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 965132b3513..47b869b9303 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,12 +1,9 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 +-MULTILIB_DIRNAMES = bs m mh le m64 +-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high +-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high ++MULTILIB_DIRNAMES = m64 bs le m mh ++MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \ +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 35021b24b7d..8d954a49575 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,16 +1,11 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ +- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ +- $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/moddi3.S \ ++ $(srcdir)/config/microblaze/muldi3_hard.S \ + $(srcdir)/config/microblaze/mulsi3.S \ +- $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ +- $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/umoddi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c \ ++ $(srcdir)/config/microblaze/divsi3_table.c +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch new file mode 100644 index 00000000..df7ef8da --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch @@ -0,0 +1,70 @@ +From 63e3adfb493e225c55536e72cfbf8be70977cdc8 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 15:24:25 +0530 +Subject: [PATCH 32/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign + extension issue + +--- + gcc/config/microblaze/microblaze.cc | 16 ++++++++++------ + gcc/config/microblaze/microblaze.md | 2 +- + 2 files changed, 11 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index de3c95a005e..6fbecb43e4a 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2183,9 +2183,14 @@ compute_frame_size (HOST_WIDE_INT size) + + total_size += gp_reg_size; + +- /* Add 4 bytes for MSR. */ ++ /* Add 4/8 bytes for MSR. */ + if (microblaze_is_interrupt_variant ()) +- total_size += 4; ++ { ++ if (TARGET_MB_64) ++ total_size += 8; ++ else ++ total_size += 4; ++ } + + /* No space to be allocated for link register in leaf functions with no other + stack requirements. */ +@@ -2470,7 +2475,6 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; +- int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2485,10 +2489,10 @@ print_operand (FILE * file, rtx op, int letter) + } + else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val1[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); + } + else if (code == CONST_DOUBLE) + { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index e37a7704195..72c2a9a38cd 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1096,7 +1096,7 @@ + case 1: + case 2: + { +- output_asm_insn ("ll%i1\t%0,%1", operands); ++ output_asm_insn ("lw%i1\t%0,%1", operands); + return "sextl32\t%0,%0"; + } + } +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch new file mode 100644 index 00000000..cf1076ea --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch @@ -0,0 +1,304 @@ +From 58d4d2ca4fdf90d9d21e7813a599b3491f52e34d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 15:28:58 +0530 +Subject: [PATCH 33/54] fixed below issues: - Floating point print issues in + 64bit mode - Dejagnu Jump related issues - Added dbl instruction + + Conflicts: + gcc/config/microblaze/microblaze.md +--- + gcc/config/microblaze/microblaze.cc | 12 +++- + gcc/config/microblaze/microblaze.h | 7 +++ + gcc/config/microblaze/microblaze.md | 86 ++++++++++++++++++++++++----- + libgcc/config/microblaze/crti.S | 24 +++++++- + libgcc/config/microblaze/crtn.S | 13 +++++ + 5 files changed, 125 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 6fbecb43e4a..965a041ea8c 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2479,7 +2479,12 @@ print_operand (FILE * file, rtx op, int letter) + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) +- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ { ++ if (TARGET_MB_64) ++ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ else ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ } + else + { + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); +@@ -3886,7 +3891,10 @@ microblaze_expand_divide (rtx operands[]) + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); +- jump = emit_jump_insn_after (gen_jump (div_end_label), insn); ++ if (TARGET_MB_64) ++ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn); ++ else ++ jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; + emit_barrier (); +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 3aee003de0d..145368db8b8 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -888,10 +888,17 @@ do { \ + /* We do this to save a few 10s of code space that would be taken up + by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION + definition in crtstuff.c. */ ++#ifdef __arch64__ ++#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ ++ asm ( SECTION_OP "\n" \ ++ "\tbrealid r15, " #FUNC "\n\t nop\n" \ ++ TEXT_SECTION_ASM_OP); ++#else + #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ + asm ( SECTION_OP "\n" \ + "\tbrlid r15, " #FUNC "\n\t nop\n" \ + TEXT_SECTION_ASM_OP); ++#endif + + /* We need to group -lm as well, since some Newlib math functions + reference __errno! */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 72c2a9a38cd..b3d265d9941 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -527,6 +527,15 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "floatdidf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (float:DF (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dbl\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +@@ -1299,7 +1308,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "" ++ "TARGET_MB_64" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1582,7 +1591,7 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -2371,9 +2380,9 @@ else + + (define_insn "long_branch_compare" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2495,6 +2504,20 @@ else + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- ++(define_insn "jump_64" ++ [(set (pc) ++ (label_ref (match_operand 0 "" "")))] ++ "TARGET_MB_64" ++ { ++ if (GET_CODE (operands[0]) == REG) ++ return "brea%?\t%0"; ++ else ++ return "breai%?\t%l0"; ++ } ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] +@@ -2540,17 +2563,25 @@ else + { + //gcc_assert (GET_MODE (operands[0]) == Pmode); + +- if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) +- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +- else +- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); ++ } ++ else { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); ++ } + DONE; + } + ) + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand 0 "register_operand" "d")) ++ (match_operand:SI 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2558,11 +2589,21 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "tablejump_internal2" ++ [(set (pc) ++ (match_operand:DI 0 "register_operand" "d")) ++ (use (label_ref (match_operand 1 "" "")))] ++ "TARGET_MB_64" ++ "bra%?\t%0 " ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus (match_operand 0 "register_operand" "d") +- (label_ref (match_operand:SI 1 "" "")))) +- (use (label_ref (match_dup 1)))])] ++ (plus:SI (match_operand:SI 0 "register_operand" "d") ++ (label_ref:SI (match_operand:SI 1 "" "")))) ++ (use (label_ref:SI (match_dup 1)))])] + "" + "" + ) +@@ -2593,6 +2634,23 @@ else + "" + ) + ++(define_insn "" ++ [(set (pc) ++ (plus:DI (match_operand:DI 0 "register_operand" "d") ++ (label_ref:DI (match_operand 1 "" "")))) ++ (use (label_ref:DI (match_dup 1)))] ++ "TARGET_MB_64 && NEXT_INSN (as_a (operands[1])) != 0 ++ && GET_CODE (PATTERN (NEXT_INSN (as_a (operands[1])))) == ADDR_DIFF_VEC ++ && flag_pic" ++ { ++ output_asm_insn ("addlk\t%0,%0,r20",operands); ++ return "bra%?\t%0"; ++} ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ ++ + ;;---------------------------------------------------------------- + ;; Function prologue/epilogue and stack allocation + ;;---------------------------------------------------------------- +@@ -3101,7 +3159,7 @@ else + ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference + ;; between "mfs" and "addik" instructions. + (define_insn "set_got" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))] + "" + "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index 1a89a0a2ffa..7cf5664880b 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -33,11 +33,32 @@ + .section .init, "ax" + .global __init + ++#ifdef __arch64__ + .weak _stack +- .set _stack, 0xffffffff ++ .set _stack, 0xffffffffffffffff + .weak _stack_end + .set _stack_end, 0 + ++ .align 3 ++__init: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++ addlik r11, r0, _stack ++ mts rshr, r11 ++ addlik r11, r0, _stack_end ++ mts rslr, r11 ++ ++ .section .fini, "ax" ++ .global __fini ++ .align 3 ++__fini: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++#else ++ .weak _stack ++ .set _stack, 0xffffffff ++ .weak _stack_end ++ .set _stack_end, 0 + .align 2 + __init: + addik r1, r1, -16 +@@ -53,3 +74,4 @@ __init: + __fini: + addik r1, r1, -16 + sw r15, r0, r1 ++#endif +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index 29a004973ae..9697b247b6c 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -29,7 +29,19 @@ + .section .note.GNU-stack,"",%progbits + .previous + #endif ++#ifdef __arch64__ ++ .section .init, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop + ++ .section .fini, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop ++#else + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +@@ -39,3 +51,4 @@ + lw r15, r0, r1 + rtsd r15, 8 + addik r1, r1, 16 ++#endif +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch new file mode 100644 index 00000000..ab50b599 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch @@ -0,0 +1,135 @@ +From 924a756b5c9edc5d626f68323f67ced2800c75ff Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 9 Oct 2018 10:07:08 +0530 +Subject: [PATCH 34/54] -Added double arith instructions -Fixed prologue stack + pointer decrement issue + +--- + gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++---- + gcc/config/microblaze/t-microblaze | 7 +++ + 2 files changed, 76 insertions(+), 9 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index b3d265d9941..0f769f320b2 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -527,6 +527,66 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "fix_truncsfsi2" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (fix:SI (match_operand:SF 1 "register_operand" "d")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" ++ "fint\t%0,%1" ++ [(set_attr "type" "fint") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "adddf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (plus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dadd\t%0,%1,%2" ++ [(set_attr "type" "fadd") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "subdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (minus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "drsub\t%0,%2,%1" ++ [(set_attr "type" "frsub") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "muldf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (mult:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dmul\t%0,%1,%2" ++ [(set_attr "type" "fmul") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "divdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (div:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "ddiv\t%0,%2,%1" ++ [(set_attr "type" "fdiv") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dsqrt\t%0,%1" ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +@@ -536,13 +596,13 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "fix_truncsfsi2" +- [(set (match_operand:SI 0 "register_operand" "=d") +- (fix:SI (match_operand:SF 1 "register_operand" "d")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" +- "fint\t%0,%1" +- [(set_attr "type" "fint") +- (set_attr "mode" "SF") ++(define_insn "floatdfdi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dlong\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DI") + (set_attr "length" "4")]) + + ;;---------------------------------------------------------------- +@@ -660,8 +720,8 @@ + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addik\t%0,%z1,-%2 +- addik\t%0,%z1,-%2" ++ addlik\t%0,%z1,-%2 ++ addlik\t%0,%z1,-%2" + [(set_attr "type" "arith,no_delay_arith,no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4,4,4")]) +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 47b869b9303..3522afd4831 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,6 +1,13 @@ + MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high + MULTILIB_DIRNAMES = m64 bs le m mh + MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64 ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch new file mode 100644 index 00000000..589ca998 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch @@ -0,0 +1,37 @@ +From 3ebc7f9a11d66843982544cd0f88f35cc4defb83 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 12 Oct 2018 16:07:36 +0530 +Subject: [PATCH 35/54] Fixed the issue in the delay slot with swap + instructions + +--- + gcc/config/microblaze/microblaze.md | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0f769f320b2..6ada55ac2bc 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -443,6 +443,9 @@ + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_REORDER" + "swapb %0, %1" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")] + ) + + (define_insn "bswaphi2" +@@ -451,6 +454,9 @@ + "TARGET_REORDER" + "swapb %0, %1 + swaph %0, %0" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "8")] + ) + + ;;---------------------------------------------------------------- +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch new file mode 100644 index 00000000..8431cb16 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch @@ -0,0 +1,256 @@ +From 9ea2aee3599d2f1fc9d67c7a72cd7c826272a2fa Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Sat, 13 Oct 2018 21:12:43 +0530 +Subject: [PATCH 36/54] Fixed the load store issue with the 32bit arith + libraries + +--- + libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++- + libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++- + libgcc/config/microblaze/mulsi3.S | 3 +++ + libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++- + libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++- + 5 files changed, 98 insertions(+), 4 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index a449fedd53e..9f04f59104e 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -41,6 +41,17 @@ + .globl __divsi3 + .ent __divsi3 + .type __divsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__divsi3: ++ .frame r1,0,r15 ++ ++ ADDIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++#else + __divsi3: + .frame r1,0,r15 + +@@ -49,7 +60,7 @@ __divsi3: + SWI r29,r1,4 + SWI r30,r1,8 + SWI r31,r1,12 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEID r5,$LaR5_Pos +@@ -89,6 +100,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r28,r1,0 +@@ -97,6 +119,7 @@ $LaRETURN_HERE: + LWI r31,r1,12 + RTSD r15,8 + ADDIK r1,r1,16 ++#endif + .end __divsi3 + .size __divsi3, . - __divsi3 + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 282fabfd966..d2f9dc770e4 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -41,6 +41,17 @@ + .globl __modsi3 + .ent __modsi3 + .type __modsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__modsi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,24 ++#else + __modsi3: + .frame r1,0,r15 + +@@ -49,6 +60,7 @@ __modsi3: + swi r29,r1,4 + swi r30,r1,8 + swi r31,r1,12 ++#endif + + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero +@@ -88,6 +100,18 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addik r1,r1,32 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r28,r1,0 +@@ -95,7 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 +- addik r1,r1,16 ++#endif + .end __modsi3 + .size __modsi3, . - __modsi3 + +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index 3da55416964..437e2bc309e 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -41,6 +41,9 @@ + .globl __mulsi3 + .ent __mulsi3 + .type __mulsi3,@function ++#ifdef __arch64__ ++ .align 3 ++#endif + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 7f3fe99eb12..496dd6794bf 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -41,6 +41,16 @@ + .globl __udivsi3 + .ent __udivsi3 + .type __udivsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__udivsi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++#else + __udivsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __udivsi3: + SWI r29,r1,0 + SWI r30,r1,4 + SWI r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero + ADDIK r30,r0,0 # Clear mod +@@ -98,6 +108,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r29,r1,0 +@@ -105,5 +126,6 @@ $LaRETURN_HERE: + LWI r31,r1,8 + RTSD r15,8 + ADDIK r1,r1,12 ++#endif + .end __udivsi3 + .size __udivsi3, . - __udivsi3 +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 6c7f2b3c917..fffc784b4cb 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -41,6 +41,16 @@ + .globl __umodsi3 + .ent __umodsi3 + .type __umodsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__umodsi3: ++ .frame r1,0,r15 ++ ++ addik r1,r1,-24 ++ swi r29,r1,0 ++ swi r30,r1,8 ++ swi r31,r1,16 ++#else + __umodsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __umodsi3: + swi r29,r1,0 + swi r30,r1,4 + swi r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero + ADDIK r3,r0,0 # Clear div +@@ -101,6 +111,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r29,r1,0 +@@ -108,5 +129,6 @@ $LaRETURN_HERE: + lwi r31,r1,8 + rtsd r15,8 + addik r1,r1,12 ++#endif + .end __umodsi3 + .size __umodsi3, . - __umodsi3 +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch new file mode 100644 index 00000000..8b0fa208 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch @@ -0,0 +1,25 @@ +From d2c971646ce103fa17cc32474cb942268bc59258 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Mon, 15 Oct 2018 12:00:10 +0530 +Subject: [PATCH 37/54] extending the Dwarf support to 64bit Microblaze + +--- + gcc/config/microblaze/microblaze.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 145368db8b8..4258dcde0d1 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; + /* Use DWARF 2 debugging information by default. */ + #define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +-#define DWARF2_ADDR_SIZE 4 ++#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4) + + /* Target machine storage layout */ + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch new file mode 100644 index 00000000..d7b78895 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch @@ -0,0 +1,29 @@ +From 0c0b4fb378d9035f0c5f847321b543a5c2ff70e2 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 16 Oct 2018 07:55:46 +0530 +Subject: [PATCH 38/54] fixing the typo errors in umodsi3 file + +--- + libgcc/config/microblaze/umodsi3.S | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index fffc784b4cb..a706017c634 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -47,9 +47,9 @@ __umodsi3: + .frame r1,0,r15 + + addik r1,r1,-24 +- swi r29,r1,0 +- swi r30,r1,8 +- swi r31,r1,16 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 + #else + __umodsi3: + .frame r1,0,r15 +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch new file mode 100644 index 00000000..27b6efd1 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch @@ -0,0 +1,68 @@ +From 8dfc5e76a3b0388bb5c88c5c0072256f3062f3c8 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Wed, 17 Oct 2018 16:56:14 +0530 +Subject: [PATCH 39/54] fixing the 32bit LTO related issue9(1014024) + +--- + gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- + 1 file changed, 14 insertions(+), 10 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 4258dcde0d1..4d6babfe9c4 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +-/* +-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ +- if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ +- (MODE) = TARGET_MB_64 ? DImode : SImode; +-*/ ++ ++#ifndef __arch64__ ++#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ ++ if (GET_MODE_CLASS (MODE) == MODE_INT \ ++ && GET_MODE_SIZE (MODE) < 4) \ ++ (MODE) = SImode; ++#endif ++ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info; + + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + ++#ifdef __aarch64__ + #define LIBCALL_VALUE(MODE) \ + gen_rtx_REG (MODE,GP_RETURN) +- +-/*#define LIBCALL_VALUE(MODE) \ ++#else ++#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +-*/ ++#endif ++ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -518,7 +522,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 64 ++#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch new file mode 100644 index 00000000..35251ff8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch @@ -0,0 +1,25 @@ +From 411324e0340a32b4a84094b38e5d74f38cf391bc Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 19 Oct 2018 14:26:25 +0530 +Subject: [PATCH 40/54] Fixed the missing stack adjustment in prologue of + modsi3 function + +--- + libgcc/config/microblaze/modsi3.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index d2f9dc770e4..f8684db721e 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -119,6 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 ++ addik r1,r1,16 + #endif + .end __modsi3 + .size __modsi3, . - __modsi3 +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch new file mode 100644 index 00000000..bb797a4a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch @@ -0,0 +1,28 @@ +From b03e3a75a37213823c062bb72e4f6f470c516222 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 24 Oct 2018 18:31:04 +0530 +Subject: [PATCH 41/54] corrected SPN for dlong instruction mapping. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 6ada55ac2bc..36b050670b8 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -602,9 +602,9 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "floatdfdi2" ++(define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") +- (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] + "TARGET_MB_64" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch new file mode 100644 index 00000000..cbafaafc --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -0,0 +1,59 @@ +From b926d05a0cdd32d9821a48f62eef49c5b1025f73 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 29 Nov 2018 17:55:08 +0530 +Subject: [PATCH 42/54] fixing the long & long long mingw toolchain issue + +--- + gcc/config/microblaze/constraints.md | 2 +- + gcc/config/microblaze/microblaze.md | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index 7bb1e0b4c8d..fa605831bfe 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -55,7 +55,7 @@ + (define_constraint "K" + "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) ++ (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) + + + ;; Define floating point constraints +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 36b050670b8..e123bf3a7d1 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -648,8 +648,8 @@ + if (TARGET_MB_64) + { + if (GET_CODE (operands[2]) == CONST_INT && +- INTVAL(operands[2]) < (long)-549755813888 && +- INTVAL(operands[2]) > (long)549755813887) ++ INTVAL(operands[2]) < (long long)-549755813888 && ++ INTVAL(operands[2]) > (long long)549755813887) + FAIL; + } + }) +@@ -1264,7 +1264,7 @@ + (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] + "TARGET_MB_64 && (register_operand (operands[0], DImode) && + (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" ++ (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" + "@ + addlk\t%0,r0,r0\t + addlik\t%0,r0,%1\t #N1 %X1 +@@ -1298,7 +1298,7 @@ + case 1: + case 2: + if (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) ++ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) + return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + else + return "addlik\t%0,r0,%1"; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch new file mode 100644 index 00000000..af8c684f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch @@ -0,0 +1,47 @@ +From 854371934116e5197d627cebaf274f431205b914 Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Thu, 14 Mar 2019 18:11:04 +0530 +Subject: [PATCH 43/54] Fix the MB-64 bug of handling QI objects + +--- + gcc/config/microblaze/microblaze.md | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index e123bf3a7d1..0f81b0ed58c 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2345,11 +2345,11 @@ else + + (define_insn "branch_zero_64" + [(set (pc) +- (if_then_else (match_operator:SI 0 "ordered_comparison_operator" ++ (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand:SI 1 "register_operand" "d") + (const_int 0)]) +- (match_operand:SI 2 "pc_or_label_operand" "") +- (match_operand:SI 3 "pc_or_label_operand" ""))) ++ (match_operand 2 "pc_or_label_operand" "") ++ (match_operand 3 "pc_or_label_operand" ""))) + ] + "TARGET_MB_64" + { +@@ -2365,11 +2365,11 @@ else + + (define_insn "long_branch_zero" + [(set (pc) +- (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand 1 "register_operand" "d") ++ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand" "d") + (const_int 0)]) +- (match_operand 2 "pc_or_label_operand" "") +- (match_operand 3 "pc_or_label_operand" ""))) ++ (match_operand:DI 2 "pc_or_label_operand" "") ++ (match_operand:DI 3 "pc_or_label_operand" ""))) + ] + "TARGET_MB_64" + { +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch new file mode 100644 index 00000000..277e5be2 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch @@ -0,0 +1,87 @@ +From 5527cec8136440a1edea87b2bb6dafa8e78d07b0 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Fri, 29 Mar 2019 12:08:39 +0530 +Subject: [PATCH 44/54] We will check the possibility of peephole2 + optimization,if we can then we will fix the compiler issue. + +--- + gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------ + 1 file changed, 38 insertions(+), 25 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0f81b0ed58c..f661ba1c241 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -882,31 +882,44 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_peephole2 +- [(set (match_operand:SI 0 "register_operand") +- (fix:SI (match_operand:SF 1 "register_operand"))) +- (set (pc) +- (if_then_else (match_operator 2 "ordered_comparison_operator" +- [(match_operand:SI 3 "register_operand") +- (match_operand:SI 4 "arith_operand")]) +- (label_ref (match_operand 5)) +- (pc)))] +- "TARGET_HARD_FLOAT && !TARGET_MB_64" +- [(set (match_dup 1) (match_dup 3))] +- +- { +- rtx condition; +- rtx cmp_op0 = operands[3]; +- rtx cmp_op1 = operands[4]; +- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); +- +- emit_insn (gen_cstoresf4 (comp_reg, operands[2], +- gen_rtx_REG (SFmode, REGNO (cmp_op0)), +- gen_rtx_REG (SFmode, REGNO (cmp_op1)))); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, operands[5])); +- } +-) ++;; peephole2 optimization will be done only if fint and if-then-else ++;; are dependent.added condition for the same. ++;; if they are dependent then gcc is giving "flow control insn inside a basic block" ++;; testcase: ++;; volatile float vec = 1.0; ++;; volatile int ci = 2; ++;; register int cj = (int)(vec); ++;;// ci=cj; ++;;// if (ci <0) { ++;; if (cj < 0) { ++;; ci = 0; ++;; } ++;; commenting for now.we will check the possibility of this optimization later ++ ++;;(define_peephole2 ++;; [(set (match_operand:SI 0 "register_operand") ++;; (fix:SI (match_operand:SF 1 "register_operand"))) ++;; (set (pc) ++;; (if_then_else (match_operator 2 "ordered_comparison_operator" ++;; [(match_operand:SI 3 "register_operand") ++;; (match_operand:SI 4 "arith_operand")]) ++;; (label_ref (match_operand 5)) ++;; (pc)))] ++;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" ++;; [(set (match_dup 1) (match_dup 3))] ++;; { ++;; rtx condition; ++;; rtx cmp_op0 = operands[3]; ++;; rtx cmp_op1 = operands[4]; ++;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++;; ++;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], ++;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), ++;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); ++;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++;; emit_jump_insn (gen_condjump (condition, operands[5])); ++;; } ++;;) + + ;;---------------------------------------------------------------- + ;; Negation and one's complement +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch new file mode 100644 index 00000000..4760926f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch @@ -0,0 +1,465 @@ +From 3c6f051ce41f06eab29932859be52ed864bef52f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 17 Apr 2019 12:36:16 +0530 +Subject: [PATCH 45/54] fixed typos in mul,div and mod assembly files. + +--- + libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++---- + libgcc/config/microblaze/modsi3.S | 40 ++++++++++++++++++--- + libgcc/config/microblaze/mulsi3.S | 33 ++++++++++++++++- + libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++--- + libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++--- + 5 files changed, 212 insertions(+), 20 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index 9f04f59104e..e1dfccbf257 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -46,7 +46,7 @@ + __divsi3: + .frame r1,0,r15 + +- ADDIK r1,r1,-32 ++ ADDLIK r1,r1,-32 + SLI r28,r1,0 + SLI r29,r1,8 + SLI r30,r1,16 +@@ -61,13 +61,23 @@ __divsi3: + SWI r30,r1,8 + SWI r31,r1,12 + #endif +- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error +- BEQI r5,$LaResult_Is_Zero # Result is Zero +- BGEID r5,$LaR5_Pos ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEID r5,$LaR5_Pos ++#else ++ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEQI r5,$LaResult_Is_Zero # Result is Zero ++ BGEID r5,$LaR5_Pos ++#endif + XOR r28,r5,r6 # Get the sign of the result + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r30,r0,0 # Clear mod +@@ -76,26 +86,51 @@ $LaR6_Pos: + + # First part try to find the first '1' in the r5 + $LaDIV0: +- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#else ++ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++#else + BEQi r29,$LaLOOP_END ++#endif + ADD r3,r3,r3 # Shift in the '1' into div ++#ifdef __arch64__ ++ BREAI $LaDIV2 # Div2 ++#else + BRI $LaDIV2 # Div2 ++#endif + $LaLOOP_END: ++#ifdef __arch64__ ++ BEAGEI r28,$LaRETURN_HERE ++ BREAID $LaRETURN_HERE ++#else + BGEI r28,$LaRETURN_HERE + BRID $LaRETURN_HERE ++#endif + RSUBI r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index f8684db721e..3bf9b10ec3e 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -62,40 +62,72 @@ __modsi3: + swi r31,r1,12 + #endif + ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEId r5,$LaR5_Pos ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEId r5,$LaR5_Pos ++#endif + ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r3,r0,0 # Clear mod + ADDIK r30,r0,0 # clear div +- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++#ifdef __arch64__ ++ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip + # the first bit search. ++#else ++ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++#endif + ADDIK r29,r0,32 # Initialize the loop count + # First part try to find the first '1' in the r5 + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 +- BGEID r5,$LaDIV1 # ++#ifdef __arch64__ ++ BEAGEID r5,$LaDIV1 # ++#else ++ BGEID r5,$LaDIV1 # ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r3,r3,r3 # Move that bit into the Mod register + rSUB r31,r6,r3 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTi r31,$LaMOD_TOO_SMALL ++#else + BLTi r31,$LaMOD_TOO_SMALL ++#endif + OR r3,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r30,r30,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEAGEI r28,$LaRETURN_HERE ++ BREAId $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r30,r30,r30 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BGEI r28,$LaRETURN_HERE + BRId $LaRETURN_HERE ++#endif + rsubi r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +@@ -108,7 +140,7 @@ $LaRETURN_HERE: + lli r29,r1,8 + lli r30,r1,16 + lli r31,r1,24 +- addik r1,r1,32 ++ addlik r1,r1,32 + rtsd r15,8 + nop + #else +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index 437e2bc309e..bc9ff9cdc89 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -43,7 +43,37 @@ + .type __mulsi3,@function + #ifdef __arch64__ + .align 3 +-#endif ++__mulsi3: ++ .frame r1,0,r15 ++ add r3,r0,r0 ++ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ BEAGEId r5,$L_R5_Pos ++ XOR r4,r5,r6 # Get the sign of the result ++ RSUBI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEAGEI r6,$L_R6_Pos ++ RSUBI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ add r5,r5,r5 ++$L1: ++ srl r6,r6 ++ addc r7,r0,r0 ++ beaeqi r7,$L2 ++ beaneid r6,$L2 ++ add r3,r3,r5 ++ bealti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rtsd r15,8 ++ rsub r3,r3,r0 ++$L_Result_Is_Zero: ++ rtsd r15,8 ++ addi r3,r0,0 ++#else + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +@@ -74,5 +104,6 @@ $L_NegateResult: + $L_Result_Is_Zero: + rtsd r15,8 + addi r3,r0,0 ++#endif + .end __mulsi3 + .size __mulsi3, . - __mulsi3 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 496dd6794bf..486bc8f0819 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -59,52 +59,96 @@ __udivsi3: + SWI r30,r1,4 + SWI r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQID r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r30,r0,0 # Clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 1 + RSUB r18,r5,r6 ++#ifdef __arch64__ ++ BEAEQID r18,$LaRETURN_HERE ++#else + BEQID r18,$LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 + XOR r18,r5,r6 +- BGEID r18,16 ++#ifdef __arch64__ ++ BEAGEID r18,16 ++#else ++ BGEID r18,16 ++#endif + ADD r3,r0,r0 # We would anyways clear r3 ++#ifdef __arch64__ ++ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++ RSUB r18,r6,r5 # MICROBLAZEcmp ++ BEALTI r18,$LaRETURN_HERE ++#else + BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater + BRI $LCheckr6 + RSUB r18,r6,r5 # MICROBLAZEcmp + BLTI r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as 1 + $LCheckr6: +- BGTI r6,$LaDIV0 +- BRID $LaRETURN_HERE ++#ifdef __arch64__ ++ BEAGTI r6,$LaDIV0 ++ BREAID $LaRETURN_HERE ++#else ++ BGTI r6,$LaDIV0 ++ BRID $LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # First part try to find the first '1' in the r5 + $LaDIV0: ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 ++#else + BLTI r5,$LaDIV2 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r3,r3,r3 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BRI $LaRETURN_HERE ++#endif + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 +@@ -115,7 +159,7 @@ $LaRETURN_HERE: + LLI r29,r1,0 + LLI r30,r1,8 + LLI r31,r1,16 +- ADDIK r1,r1,24 ++ ADDLIK r1,r1,24 + RTSD r15,8 + NOP + #else +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index a706017c634..1d8e2921745 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -46,7 +46,7 @@ + __umodsi3: + .frame r1,0,r15 + +- addik r1,r1,-24 ++ addlik r1,r1,-24 + sli r29,r1,0 + sli r30,r1,8 + sli r31,r1,16 +@@ -59,27 +59,77 @@ __umodsi3: + swi r30,r1,4 + swi r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQId r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r3,r0,0 # Clear div + ADDIK r30,r0,0 # clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 0 + rsub r18,r5,r6 +- beqi r18,$LaRETURN_HERE + ++#ifdef __arch64__ ++ beaeqi r18,$LaRETURN_HERE ++#else ++ beqi r18,$LaRETURN_HERE ++#endif + # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 + xor r18,r5,r6 ++#ifdef __arch64__ ++ beageid r18,16 ++ addik r3,r5,0 ++ bealti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++ rsub r18,r5,r6 # MICROBLAZEcmp ++ beagti r18,$LaRETURN_HERE ++#else + bgeid r18,16 + addik r3,r5,0 + blti r6,$LaRETURN_HERE + bri $LCheckr6 + rsub r18,r5,r6 # MICROBLAZEcmp + bgti r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as r5-r6 + $LCheckr6: ++#ifdef __arch64__ ++ beagtid r6,$LaDIV0 ++ addik r3,r0,0 ++ addik r18,r0,0x7fffffff ++ and r5,r5,r18 ++ and r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsub r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALTI r5,$LaDIV2 ++$LaDIV1: ++ ADD r5,r5,r5 # left shift logical r5 ++ BEAGEID r5,$LaDIV1 # ++ ADDIK r29,r29,-1 ++$LaDIV2: ++ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDC r3,r3,r3 # Move that bit into the Mod register ++ rSUB r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALTi r31,$LaMOD_TOO_SMALL ++ OR r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDIK r29,r29,-1 ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ or r3,r0,r0 # set result to 0 ++#else + bgtid r6,$LaDIV0 + addik r3,r0,0 + addik r18,r0,0x7fffffff +@@ -111,7 +161,7 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 +- ++#endif + #ifdef __arch64__ + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch new file mode 100644 index 00000000..5f45d03f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch @@ -0,0 +1,476 @@ +From 0776495e85a15c1ad84fd90736059902bb3ea152 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 15:59:12 +0530 +Subject: [PATCH 46/54] MB-64 removal of barrel-shift instructions from default + By default MB-64 is generatting barrel-shift instructions. It has been + removed from default. Barrel-shift instructions will be generated only if + barrel-shifter is enabled. Similarly to double instructions as well. + + Signed-off-by :Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.cc | 2 +- + gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++-- + 2 files changed, 252 insertions(+), 19 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 965a041ea8c..f949a8863d3 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -3880,7 +3880,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + + if (TARGET_MB_64) { +- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_adddi3 (regt1, regt1, operands[2])); + } + else { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index f661ba1c241..9bc9512db8e 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -547,7 +547,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (plus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dadd\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "DF") +@@ -557,7 +557,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (minus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "drsub\t%0,%2,%1" + [(set_attr "type" "frsub") + (set_attr "mode" "DF") +@@ -567,7 +567,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (mult:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dmul\t%0,%1,%2" + [(set_attr "type" "fmul") + (set_attr "mode" "DF") +@@ -577,7 +577,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (div:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "ddiv\t%0,%2,%1" + [(set_attr "type" "fdiv") + (set_attr "mode" "DF") +@@ -587,7 +587,7 @@ + (define_insn "sqrtdf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dsqrt\t%0,%1" + [(set_attr "type" "fsqrt") + (set_attr "mode" "DF") +@@ -596,7 +596,7 @@ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dbl\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") +@@ -605,7 +605,7 @@ + (define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DI") +@@ -1299,6 +1299,34 @@ + (set_attr "mode" "DI") + (set_attr "length" "4")]) + ++(define_insn "*movdi_internal2_bshift" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + (define_insn "*movdi_internal2" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") + (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] +@@ -1312,7 +1340,15 @@ + case 2: + if (GET_CODE (operands[1]) == CONST_INT && + (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) +- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ { ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,32", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; ++ } + else + return "addlik\t%0,r0,%1"; + case 3: +@@ -1387,7 +1423,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1654,6 +1690,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64_bshift" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal_64" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") + (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] +@@ -1670,7 +1733,13 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,32", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -1790,11 +1859,21 @@ + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1804,7 +1883,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashift:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bsllli\t%0,%1,%2 + bslll\t%0,%1,%2" +@@ -1812,6 +1891,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashldi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashldi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1945,11 +2069,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1959,7 +2093,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrai\t%0,%1,%2 + bslra\t%0,%1,%2" +@@ -1967,6 +2101,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2084,11 +2263,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -2098,7 +2287,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrli\t%0,%1,%2 + bslrl\t%0,%1,%2" +@@ -2107,6 +2296,50 @@ else + (set_attr "length" "4,4")] + ) + ++(define_insn "lshrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "lshrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "SI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2233,7 +2466,7 @@ else + (eq:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmpleq\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +@@ -2245,7 +2478,7 @@ else + (ne:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmplne\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch new file mode 100644 index 00000000..0272fd3c --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch @@ -0,0 +1,107 @@ +From 003f60fa4eedddd15de6e9f633bffec1a887fe45 Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Fri, 23 Aug 2019 16:16:53 +0530 +Subject: [PATCH 47/54] Added new MB-64 single register arithmetic instructions + +--- + gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++ + 1 file changed, 56 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 9bc9512db8e..9172f1bc209 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -654,6 +654,18 @@ + } + }) + ++(define_insn "adddi3_int" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (plus:DI (match_operand:DI 1 "register_operand" "%0") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ addlik\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ + (define_insn "*adddi3_long" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") +@@ -719,6 +731,18 @@ + { + }") + ++(define_insn "subdi316imm" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))" ++ "@ ++ addlik\t%0,-%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++ + (define_insn "subsidi3" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") +@@ -1015,6 +1039,17 @@ + ;; Logical + ;;---------------------------------------------------------------- + ++(define_insn "anddi3imm16" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (and:DI (match_operand:DI 1 "arith_operand" "%0") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ andli\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "anddi3" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") +@@ -1042,6 +1077,16 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "iordi3imm16" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (ior:DI (match_operand:DI 1 "arith_operand" "%0") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ orli\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) + + (define_insn "iordi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") +@@ -1069,6 +1114,17 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "xordi3imm16" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (xor:DI (match_operand:DI 1 "arith_operand" "%0") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ xorli\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "xordi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch new file mode 100644 index 00000000..0be495a8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch @@ -0,0 +1,43 @@ +From 8d20c82d95e22a42551b446c087d9e06958a3580 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 26 Aug 2019 15:55:22 +0530 +Subject: [PATCH 48/54] Added support for 64 bit Immediate values. + +--- + gcc/config/microblaze/constraints.md | 4 ++-- + gcc/config/microblaze/microblaze.md | 3 +-- + 2 files changed, 3 insertions(+), 4 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index fa605831bfe..40cd88a870c 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -53,9 +53,9 @@ + (match_test "ival > 0 && ival < 0x10000"))) + + (define_constraint "K" +- "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." ++ "A constant in the range -9223372036854775808 to 9223372036854775807 (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) ++ (match_test "ival > (long long)-9223372036854775808 && ival < (long long)9223372036854775807"))) + + + ;; Define floating point constraints +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 9172f1bc209..f41474feca6 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1332,8 +1332,7 @@ + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") + (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] + "TARGET_MB_64 && (register_operand (operands[0], DImode) && +- (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" ++ (GET_CODE (operands[1]) == CONST_INT))" + "@ + addlk\t%0,r0,r0\t + addlik\t%0,r0,%1\t #N1 %X1 +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch new file mode 100644 index 00000000..ca813796 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch @@ -0,0 +1,76 @@ +From 8107e0be46e5bdbfc353648ce5129afde5275ea9 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 16:06:10 +0530 +Subject: [PATCH 49/54] Fix Compiler crash with -freg-struct-return This patch + fixes a bug in MB GCC regarding the passing struct values in registers. + Currently we are only handling SImode With this patch all other modes are + handled properly + + Signed-off-by :Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.cc | 11 ++++++++++- + gcc/config/microblaze/microblaze.h | 19 ------------------- + 2 files changed, 10 insertions(+), 20 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index f949a8863d3..4748c8c1f0d 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -3918,7 +3918,16 @@ microblaze_function_value (const_tree valtype, + const_tree func ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) + { +- return LIBCALL_VALUE (TYPE_MODE (valtype)); ++ return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN); ++} ++ ++#undef TARGET_LIBCALL_VALUE ++#define TARGET_LIBCALL_VALUE microblaze_libcall_value ++ ++rtx ++microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) ++{ ++ return gen_rtx_REG (mode, GP_RETURN); + } + + /* Implement TARGET_SCHED_ADJUST_COST. */ +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 4d6babfe9c4..eea360fda47 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe; + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND + +-#ifndef __arch64__ +-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ +- if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < 4) \ +- (MODE) = SImode; +-#endif +- + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info; + + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + +-#ifdef __aarch64__ +-#define LIBCALL_VALUE(MODE) \ +- gen_rtx_REG (MODE,GP_RETURN) +-#else +-#define LIBCALL_VALUE(MODE) \ +- gen_rtx_REG ( \ +- ((GET_MODE_CLASS (MODE) != MODE_INT \ +- || GET_MODE_SIZE (MODE) >= 4) \ +- ? (MODE) \ +- : SImode), GP_RETURN) +-#endif +- + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch new file mode 100644 index 00000000..3b8fad81 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch @@ -0,0 +1,50 @@ +From b7fb925d6277d11e4014aa1731fc58813e30761f Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Wed, 8 May 2019 14:12:03 +0530 +Subject: [PATCH 50/54] Add TARGET_OPTION_OPTIMIZATION and disable fivopts by + default + +Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. + + * gcc/common/config/microblaze/microblaze-common.c + (microblaze_option_optimization_table): Disable fivopts by default. + +Signed-off-by: Nagaraju Mekala + Mahesh Bodapati +Conflicts: + gcc/common/config/microblaze/microblaze-common.c + +Conflicts: + gcc/common/config/microblaze/microblaze-common.c +--- + gcc/common/config/microblaze/microblaze-common.cc | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/gcc/common/config/microblaze/microblaze-common.cc b/gcc/common/config/microblaze/microblaze-common.cc +index 8750b022447..8a924e8a997 100644 +--- a/gcc/common/config/microblaze/microblaze-common.cc ++++ b/gcc/common/config/microblaze/microblaze-common.cc +@@ -24,7 +24,20 @@ + #include "common/common-target.h" + #include "common/common-target-def.h" + ++/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ ++static const struct default_options microblaze_option_optimization_table[] = ++ { ++ /* Turn off ivopts by default. It messes up cse. ++ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */ ++ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, ++ { OPT_LEVELS_NONE, 0, NULL, 0 } ++ }; ++ ++ + #undef TARGET_DEFAULT_TARGET_FLAGS + #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT + ++#undef TARGET_OPTION_OPTIMIZATION_TABLE ++#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table ++ + struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch new file mode 100644 index 00000000..648da43a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch @@ -0,0 +1,189 @@ +From a464c0e6070cac9b40b7fe760e25cbd484a615a7 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 16:35:00 +0530 +Subject: [PATCH 51/54] Reducing Stack space for arguments + + Currently in Microblaze target stack space for arguments in register is being + allocated even if there are no arguments in the function. + This patch will optimize the extra 24 bytes that are being allocated. + + Signed-off-by :Nagaraju Mekala + :Ajit Agarwal +--- + gcc/config/microblaze/microblaze-protos.h | 1 + + gcc/config/microblaze/microblaze.cc | 130 ++++++++++++++++++++++ + gcc/config/microblaze/microblaze.h | 4 +- + 3 files changed, 133 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index 0e9f783c4a4..091d8d9a51b 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx); + extern int label_mentioned_p (rtx); + extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); + extern void microblaze_eh_return (rtx op0); ++int microblaze_reg_parm_stack_space(tree fun); + #endif /* RTX_CODE */ + + /* Declare functions in microblaze-c.cc. */ +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index 4748c8c1f0d..e6d3f35370c 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2086,6 +2086,136 @@ microblaze_must_save_register (int regno) + return 0; + } + ++static bool ++microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type) ++{ ++ int unsignedp; ++ rtx entry_parm; ++ ++ /* Catch errors. */ ++ if (type == NULL || type == error_mark_node) ++ return true; ++ ++ if (TREE_CODE (type) == POINTER_TYPE) ++ return true; ++ ++ /* Handle types with no storage requirement. */ ++ if (TYPE_MODE (type) == VOIDmode) ++ return false; ++ ++ /* Handle complex types. */ ++ if (TREE_CODE (type) == COMPLEX_TYPE) ++ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)) ++ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))); ++ ++ /* Handle transparent aggregates. */ ++ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE) ++ && TYPE_TRANSPARENT_AGGR (type)) ++ type = TREE_TYPE (first_field (type)); ++ ++ /* See if this arg was passed by invisible reference. */ ++ function_arg_info arg (type, /*named=*/true); ++ apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg); ++ ++ /* Find mode as it is passed by the ABI. */ ++ unsignedp = TYPE_UNSIGNED (type); ++ arg.mode = promote_mode (arg.type, arg.mode, &unsignedp); ++ ++ /* If there is no incoming register, we need a stack. */ ++ entry_parm = microblaze_function_arg (args_so_far, arg); ++ if (entry_parm == NULL) ++ return true; ++ ++ /* Likewise if we need to pass both in registers and on the stack. */ ++ if (GET_CODE (entry_parm) == PARALLEL ++ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX) ++ return true; ++ ++ /* Also true if we're partially in registers and partially not. */ ++ if (function_arg_partial_bytes (args_so_far, arg) != 0) ++ return true; ++ ++ /* Update info on where next arg arrives in registers. */ ++ microblaze_function_arg_advance (args_so_far, arg); ++ return false; ++} ++ ++static bool ++microblaze_function_parms_need_stack (tree fun, bool incoming) ++{ ++ tree fntype, result; ++ CUMULATIVE_ARGS args_so_far_v; ++ cumulative_args_t args_so_far; ++ int num_of_args = 0; ++ ++ /* Must be a libcall, all of which only use reg parms. */ ++ if (!fun) ++ return true; ++ ++ fntype = fun; ++ if (!TYPE_P (fun)) ++ fntype = TREE_TYPE (fun); ++ ++ /* Varargs functions need the parameter save area. */ ++ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype)) ++ return true; ++ ++ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0); ++ args_so_far = pack_cumulative_args (&args_so_far_v); ++ ++ /* When incoming, we will have been passed the function decl. ++ * * It is necessary to use the decl to handle K&R style functions, ++ * * where TYPE_ARG_TYPES may not be available. */ ++ if (incoming) ++ { ++ gcc_assert (DECL_P (fun)); ++ result = DECL_RESULT (fun); ++ } ++ else ++ result = TREE_TYPE (fntype); ++ ++ if (result && aggregate_value_p (result, fntype)) ++ { ++ if (!TYPE_P (result)) ++ result = build_pointer_type (result); ++ microblaze_parm_needs_stack (args_so_far, result); ++ } ++ ++ if (incoming) ++ { ++ tree parm; ++ for (parm = DECL_ARGUMENTS (fun); ++ parm && parm != void_list_node; ++ parm = TREE_CHAIN (parm)) ++ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm))) ++ return true; ++ } ++ else ++ { ++ function_args_iterator args_iter; ++ tree arg_type; ++ ++ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter) ++ { ++ num_of_args; ++ if (microblaze_parm_needs_stack (args_so_far, arg_type)) ++ return true; ++ } ++ } ++ ++ if (num_of_args > 3) return true; ++ ++ return false; ++} ++ ++int microblaze_reg_parm_stack_space(tree fun) ++{ ++ if (microblaze_function_parms_need_stack (fun,false)) ++ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD; ++ else ++ return 0; ++} ++ + /* Return the bytes needed to compute the frame pointer from the current + stack pointer. + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index eea360fda47..f23805b1c03 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info; + #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 + #define DWARF_CIE_DATA_ALIGNMENT -1 + +-#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) ++#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL) + +-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 ++#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + + #define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) + +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch new file mode 100644 index 00000000..d0474dd9 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch @@ -0,0 +1,72 @@ +From b792943436857172e7a39e26a00602c7e6620860 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 16:38:43 +0530 +Subject: [PATCH 52/54] If we use break_handler attribute then interrupt vector + call happened to break_handler instead of interrupt_handler. this fix will + resolve the issue CR-1081780. This fix will not change the behavior of + compiler unless there is a usage of break_handler attribute. signed-off-by : + Mahesh Bodapati + +--- + gcc/config/microblaze/microblaze.cc | 13 +++++-------- + 1 file changed, 5 insertions(+), 8 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc +index e6d3f35370c..58d091fbed2 100644 +--- a/gcc/config/microblaze/microblaze.cc ++++ b/gcc/config/microblaze/microblaze.cc +@@ -2025,7 +2025,7 @@ microblaze_save_volatiles (tree func) + int + microblaze_is_interrupt_variant (void) + { +- return (interrupt_handler || fast_interrupt); ++ return (interrupt_handler || fast_interrupt || break_handler); + } + int + microblaze_is_break_handler (void) +@@ -2064,7 +2064,7 @@ microblaze_must_save_register (int regno) + { + if (df_regs_ever_live_p (regno) + || regno == MB_ABI_MSR_SAVE_REG +- || ((interrupt_handler || fast_interrupt) ++ || ((interrupt_handler || fast_interrupt || break_handler) + && (regno == MB_ABI_ASM_TEMP_REGNUM + || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM))) + return 1; +@@ -2280,9 +2280,6 @@ compute_frame_size (HOST_WIDE_INT size) + fast_interrupt = + microblaze_fast_interrupt_function_p (current_function_decl); + save_volatiles = microblaze_save_volatiles (current_function_decl); +- if (break_handler) +- interrupt_handler = break_handler; +- + gp_reg_size = 0; + mask = 0; + var_size = size; +@@ -3242,7 +3239,7 @@ microblaze_expand_prologue (void) + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + const0_rtx)); + +- if (interrupt_handler) ++ if (interrupt_handler || break_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + +@@ -3353,12 +3350,12 @@ microblaze_expand_epilogue (void) + a load-use stall cycle :) This is also important to handle alloca. + (See comments for if (frame_pointer_needed) below. */ + +- if (!crtl->is_leaf || interrupt_handler) ++ if (!crtl->is_leaf || interrupt_handler || break_handler) + { + mem_rtx = + gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); +- if (interrupt_handler) ++ if (interrupt_handler || break_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch new file mode 100644 index 00000000..52017a9d --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch @@ -0,0 +1,58 @@ +From fbf853f0b9571529dcc72fc53adf4a35abd3e050 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 13 Sep 2022 16:45:41 +0530 +Subject: [PATCH 53/54] Add Zero_extended instructions + + Due to latest changes in GCC-10.2 MB64 perforamance has reduced + We have added zero_extended instructions to get rid of left shift + and right shift loops + + [CR/TSR]: TSR-974519 + + Signed-off-by: Nagaraju Mekala + Mahesh Bodapati +--- + gcc/config/microblaze/microblaze.md | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index f41474feca6..aff98604db7 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1191,6 +1191,33 @@ + (set_attr "mode" "SI,SI,SI") + (set_attr "length" "4,4,8")]) + ++(define_insn "zero_extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0xffff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ ++(define_insn "zero_extendsidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0xffffffff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ ++(define_insn "zero_extendqidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0x00ff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ + ;;---------------------------------------------------------------- + ;; Sign extension + ;;---------------------------------------------------------------- +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch new file mode 100644 index 00000000..ec8bc0cf --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch @@ -0,0 +1,42 @@ +From 79d007fea870a3b8d72faa90238cee2cdfaf5c85 Mon Sep 17 00:00:00 2001 +From: Gopi Kumar Bulusu +Date: Fri, 28 Jun 2024 12:18:38 +0530 +Subject: [PATCH 54/54] Fix failure with gcc.c-torture/execute/ashrdi-1.c -Os + execution test + +The following tests fail with -Os option because a shift instruction +in a branch delay slot gets replaced with multiple instructions when +the processor has no barrel shifter. This fix addresses the problem +by marking the responsible instruction pattern as type multi preventing +it from being placed in a delay slot. + +> gcc.c-torture/execute/ashrdi-1.c -Os execution test +> gcc.c-torture/execute/pr40057.c -Os execution test +> gcc.c-torture/execute/pr79121.c -Os execution test +> gcc.c-torture/execute/pr82524.c -Os execution test +> c-c++-common/torture/vector-compare-1.c -Os execution test +> gcc.dg/torture/vec-cvt-1.c -Os execution test + +These tests pass with this fix. + +Signed-off-by: Gopi Kumar Bulusu +--- + gcc/config/microblaze/microblaze.md | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index aff98604db7..0e3981390c8 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2286,7 +2286,7 @@ else + output_asm_insn ("bneid\t%3,.-4", operands); + return "sra\t%0,%0"; + } +- [(set_attr "type" "arith") ++ [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "20")] + ) +-- +2.34.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch new file mode 100644 index 00000000..af8ebf3b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch @@ -0,0 +1,58 @@ +Microblaze Mulitlib hack + +Based on the patch: + +From c2081c51db589471ea713870c72f13999abda815 Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Fri, 29 Mar 2013 09:10:06 +0400 +Subject: [PATCH 04/36] 64-bit multilib hack. + +GCC has internal multilib handling code but it assumes a very specific rigid directory +layout. The build system implementation of multilib layout is very generic and allows +complete customisation of the library directories. + +This patch is a partial solution to allow any custom directories to be passed into gcc +and handled correctly. It forces gcc to use the base_libdir (which is the current +directory, "."). We need to do this for each multilib that is configured as we don't +know which compiler options may be being passed into the compiler. Since we have a compiler +per mulitlib at this point that isn't an issue. + +The one problem is the target compiler is only going to work for the default multlilib at +this point. Ideally we'd figure out which multilibs were being enabled with which paths +and be able to patch these entries with a complete set of correct paths but this we +don't have such code at this point. This is something the target gcc recipe should do +and override these platform defaults in its build config. + +Do same for riscv64 and aarch64 + +RP 15/8/11 + +Upstream-Status: Inappropriate[OE-Specific] + +Signed-off-by: Khem Raj +Signed-off-by: Elvis Dowson +Signed-off-by: Mark Hatle +Signed-off-by: Mark Hatle + +Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze +=================================================================== +--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze ++++ gcc-9.2.0/gcc/config/microblaze/t-microblaze +@@ -1,5 +1,6 @@ + MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high +-MULTILIB_DIRNAMES = m64 bs le m mh ++#MULTILIB_DIRNAMES = m64 bs le m mh ++MULTILIB_DIRNAMES = . . . . . + MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *m64 + MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift +Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux +=================================================================== +--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze-linux ++++ gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux +@@ -1,3 +1,4 @@ + MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high +-MULTILIB_DIRNAMES = bs m mh ++#MULTILIB_DIRNAMES = bs m mh ++MULTILIB_DIRNAMES = . . . + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend deleted file mode 100644 index 42bcd174..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend +++ /dev/null @@ -1,59 +0,0 @@ -# Add MicroBlaze Patches (only when using MicroBlaze) -FILESEXTRAPATHS:append := ":${THISDIR}/gcc-12" - -SRC_URI += " \ - file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ - file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \ - file://0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \ - file://0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \ - file://0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch \ - file://0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \ - file://0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \ - file://0008-Patch-microblaze-Fix-atomic-side-effects.patch \ - file://0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch \ - file://0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \ - file://0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \ - file://0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch \ - file://0013-Patch-microblaze-Removed-moddi3-routinue.patch \ - file://0014-Patch-microblaze-Add-INIT_PRIORITY-support-Added.patch \ - file://0015-Patch-microblaze-Add-optimized-lshrsi3.patch \ - file://0016-Patch-microblaze-Add-cbranchsi4_reg.patch \ - file://0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \ - file://0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \ - file://0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \ - file://0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \ - file://0021-PATCH-21-53-Patch-microblaze-Correct-the-const-high-.patch \ - file://0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \ - file://0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \ - file://0024-Patch-MicroBlaze-this-patch-has-1.Fixed-the-bug-in.patch \ - file://0025-Fixing-the-issue-with-the-builtin_alloc.patch \ - file://0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \ - file://0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch \ - file://0028-Intial-commit-for-64bit-MB-sources.patch \ - file://0029-Patch-MicroBlaze-re-arrangement-of-the-compare-branc.patch \ - file://0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch \ - file://0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch \ - file://0032-Patch-MicroBlaze-Fixed-issues-like.patch \ - file://0033-Patch-MicroBlaze.patch \ - file://0034-Added-double-arith-instructions.patch \ - file://0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \ - file://0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \ - file://0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch \ - file://0038-fixing-the-typo-errors-in-umodsi3-file.patch \ - file://0039-fixing-the-32bit-LTO-related-issue9-1014024.patch \ - file://0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ - file://0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \ - file://0042-fixing-the-long-long-long-mingw-toolchain-issue.patch \ - file://0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ - file://0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \ - file://0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \ - file://0046-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch \ - file://0047-Added-new-MB-64-single-register-arithmetic-instructi.patch \ - file://0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \ - file://0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \ - file://0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \ - file://0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \ - file://0052-Patch-MicroBlaze.patch \ - file://0053-patch-microblaze64-Add-Zero_extended-instructions.patch \ - file://microblaze-mulitlib-hack.patch \ -" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_13.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-source_13.%.bbappend new file mode 100644 index 00000000..51b08f36 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-source_13.%.bbappend @@ -0,0 +1,63 @@ +# Add MicroBlaze Patches (only when using MicroBlaze) +FILESEXTRAPATHS:append := ":${THISDIR}/gcc-13" + +# Our changes are all local, no real patch-status +ERROR_QA:remove = "patch-status" + +SRC_URI += " \ + file://0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch \ + file://0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch \ + file://0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch \ + file://0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch \ + file://0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch \ + file://0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch \ + file://0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch \ + file://0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch \ + file://0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch \ + file://0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch \ + file://0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch \ + file://0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch \ + file://0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch \ + file://0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch \ + file://0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch \ + file://0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch \ + file://0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch \ + file://0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch \ + file://0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch \ + file://0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch \ + file://0021-Correct-the-const-high-double-immediate-value-with-t.patch \ + file://0022-Fix-internal-compiler-error-with-msmall-divides-This.patch \ + file://0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch \ + file://0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch \ + file://0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch \ + file://0026-Removed-fsqrt-generation-for-double-values.patch \ + file://0027-Intial-commit-of-64-bit-Microblaze.patch \ + file://0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch \ + file://0029-re-arrangement-of-the-compare-branches.patch \ + file://0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch \ + file://0031-Support-of-multilibs-with-m64.patch \ + file://0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch \ + file://0033-fixed-below-issues-Floating-point-print-issues-in-64.patch \ + file://0034-Added-double-arith-instructions-Fixed-prologue-stack.patch \ + file://0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \ + file://0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \ + file://0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch \ + file://0038-fixing-the-typo-errors-in-umodsi3-file.patch \ + file://0039-fixing-the-32bit-LTO-related-issue9-1014024.patch \ + file://0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ + file://0041-corrected-SPN-for-dlong-instruction-mapping.patch \ + file://0042-fixing-the-long-long-long-mingw-toolchain-issue.patch \ + file://0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ + file://0044-We-will-check-the-possibility-of-peephole2-optimizat.patch \ + file://0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch \ + file://0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch \ + file://0047-Added-new-MB-64-single-register-arithmetic-instructi.patch \ + file://0048-Added-support-for-64-bit-Immediate-values.patch \ + file://0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch \ + file://0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch \ + file://0051-Reducing-Stack-space-for-arguments.patch \ + file://0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch \ + file://0053-Add-Zero_extended-instructions.patch \ + file://0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch \ + file://microblaze-mulitlib-hack.patch \ +" diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/additional-microblaze-multilibs.patch b/meta-vitis-tc/recipes-devtools/gcc/gcc-12/additional-microblaze-multilibs.patch deleted file mode 100644 index e035b8a6..00000000 --- a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/additional-microblaze-multilibs.patch +++ /dev/null @@ -1,88 +0,0 @@ -Change the multilib settings to match the expectations of Vitis and related. - -The multilib list is as follows: - -.; -le;@mlittle-endian -bs;@mxl-barrel-shift -p;@mxl-pattern-compare -m;@mno-xl-soft-mul -fpd;@mhard-float -m/fpd;@mno-xl-soft-mul@mhard-float -p/m;@mxl-pattern-compare@mno-xl-soft-mul -p/fpd;@mxl-pattern-compare@mhard-float -p/m/fpd;@mxl-pattern-compare@mno-xl-soft-mul@mhard-float -bs/p;@mxl-barrel-shift@mxl-pattern-compare -bs/m;@mxl-barrel-shift@mno-xl-soft-mul -bs/fpd;@mxl-barrel-shift@mhard-float -bs/m/fpd;@mxl-barrel-shift@mno-xl-soft-mul@mhard-float -bs/p/m;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul -bs/p/fpd;@mxl-barrel-shift@mxl-pattern-compare@mhard-float -bs/p/m/fpd;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float -le/m64;@mlittle-endian@m64 -le/bs;@mlittle-endian@mxl-barrel-shift -le/p;@mlittle-endian@mxl-pattern-compare -le/m;@mlittle-endian@mno-xl-soft-mul -le/fpd;@mlittle-endian@mhard-float -le/m/fpd;@mlittle-endian@mno-xl-soft-mul@mhard-float -le/p/m;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul -le/p/fpd;@mlittle-endian@mxl-pattern-compare@mhard-float -le/p/m/fpd;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul@mhard-float -le/bs/p;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare -le/bs/m;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul -le/bs/fpd;@mlittle-endian@mxl-barrel-shift@mhard-float -le/bs/m/fpd;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul@mhard-float -le/bs/p/m;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul -le/bs/p/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mhard-float -le/bs/p/m/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float -le/m64/bs;@mlittle-endian@m64@mxl-barrel-shift -le/m64/p;@mlittle-endian@m64@mxl-pattern-compare -le/m64/m;@mlittle-endian@m64@mno-xl-soft-mul -le/m64/fpd;@mlittle-endian@m64@mhard-float -le/m64/m/fpd;@mlittle-endian@m64@mno-xl-soft-mul@mhard-float -le/m64/p/m;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul -le/m64/p/fpd;@mlittle-endian@m64@mxl-pattern-compare@mhard-float -le/m64/p/m/fpd;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul@mhard-float -le/m64/bs/p;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare -le/m64/bs/m;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul -le/m64/bs/fpd;@mlittle-endian@m64@mxl-barrel-shift@mhard-float -le/m64/bs/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul@mhard-float -le/m64/bs/p/m;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul -le/m64/bs/p/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mhard-float -le/m64/bs/p/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float - -As part of this the order of the multilibs was changes from upstream to make -it easier to avoid big-endian m64, which is not supported by the toolchain. - -Upstream-Status: Inappropriate [AMD Microblaze specific] - -Signed-off-by: Mark Hatle - -Index: gcc-12.2.0/gcc/config/microblaze/t-microblaze -=================================================================== ---- gcc-12.2.0.orig/gcc/config/microblaze/t-microblaze -+++ gcc-12.2.0/gcc/config/microblaze/t-microblaze -@@ -1,17 +1,11 @@ --MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high --#MULTILIB_DIRNAMES = m64 bs le m mh --MULTILIB_DIRNAMES = . . . . . --MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high --MULTILIB_EXCEPTIONS += *m64 --MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift --MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul --MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul --MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul --MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high --MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high -+MULTILIB_OPTIONS = mlittle-endian m64 mxl-barrel-shift mxl-pattern-compare mno-xl-soft-mul mhard-float -+MULTILIB_DIRNAMES = le m64 bs p m fpd -+MULTILIB_EXCEPTIONS = mxl-multiply-high - MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high --MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high -+MULTILIB_EXCEPTIONS += *mxl-pattern-compare*/*mxl-multiply-high* -+# Big endian m64 is not supported -+MULTILIB_EXCEPTIONS += m64* - - # Extra files - microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \ diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/riscv-multilib-generator-python.patch b/meta-vitis-tc/recipes-devtools/gcc/gcc-12/riscv-multilib-generator-python.patch deleted file mode 100644 index 9575539e..00000000 --- a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/riscv-multilib-generator-python.patch +++ /dev/null @@ -1,14 +0,0 @@ -Use python3 instead of python when calling the mutlib-generator - -Upstream-Status: Backport - -Signed-off-by: Mark Hatle - ---- gcc-12.2.0/gcc/config/riscv/multilib-generator.orig 2024-02-22 19:23:07.166805418 -0700 -+++ gcc-12.2.0/gcc/config/riscv/multilib-generator 2024-02-22 19:18:12.803798625 -0700 -@@ -1,4 +1,4 @@ --#!/usr/bin/env python -+#!/usr/bin/env python3 - - # RISC-V multilib list generator. - # Copyright (C) 2011-2022 Free Software Foundation, Inc. diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-13/additional-microblaze-multilibs.patch b/meta-vitis-tc/recipes-devtools/gcc/gcc-13/additional-microblaze-multilibs.patch new file mode 100644 index 00000000..e035b8a6 --- /dev/null +++ b/meta-vitis-tc/recipes-devtools/gcc/gcc-13/additional-microblaze-multilibs.patch @@ -0,0 +1,88 @@ +Change the multilib settings to match the expectations of Vitis and related. + +The multilib list is as follows: + +.; +le;@mlittle-endian +bs;@mxl-barrel-shift +p;@mxl-pattern-compare +m;@mno-xl-soft-mul +fpd;@mhard-float +m/fpd;@mno-xl-soft-mul@mhard-float +p/m;@mxl-pattern-compare@mno-xl-soft-mul +p/fpd;@mxl-pattern-compare@mhard-float +p/m/fpd;@mxl-pattern-compare@mno-xl-soft-mul@mhard-float +bs/p;@mxl-barrel-shift@mxl-pattern-compare +bs/m;@mxl-barrel-shift@mno-xl-soft-mul +bs/fpd;@mxl-barrel-shift@mhard-float +bs/m/fpd;@mxl-barrel-shift@mno-xl-soft-mul@mhard-float +bs/p/m;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul +bs/p/fpd;@mxl-barrel-shift@mxl-pattern-compare@mhard-float +bs/p/m/fpd;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float +le/m64;@mlittle-endian@m64 +le/bs;@mlittle-endian@mxl-barrel-shift +le/p;@mlittle-endian@mxl-pattern-compare +le/m;@mlittle-endian@mno-xl-soft-mul +le/fpd;@mlittle-endian@mhard-float +le/m/fpd;@mlittle-endian@mno-xl-soft-mul@mhard-float +le/p/m;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul +le/p/fpd;@mlittle-endian@mxl-pattern-compare@mhard-float +le/p/m/fpd;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul@mhard-float +le/bs/p;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare +le/bs/m;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul +le/bs/fpd;@mlittle-endian@mxl-barrel-shift@mhard-float +le/bs/m/fpd;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul@mhard-float +le/bs/p/m;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul +le/bs/p/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mhard-float +le/bs/p/m/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float +le/m64/bs;@mlittle-endian@m64@mxl-barrel-shift +le/m64/p;@mlittle-endian@m64@mxl-pattern-compare +le/m64/m;@mlittle-endian@m64@mno-xl-soft-mul +le/m64/fpd;@mlittle-endian@m64@mhard-float +le/m64/m/fpd;@mlittle-endian@m64@mno-xl-soft-mul@mhard-float +le/m64/p/m;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul +le/m64/p/fpd;@mlittle-endian@m64@mxl-pattern-compare@mhard-float +le/m64/p/m/fpd;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul@mhard-float +le/m64/bs/p;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare +le/m64/bs/m;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul +le/m64/bs/fpd;@mlittle-endian@m64@mxl-barrel-shift@mhard-float +le/m64/bs/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul@mhard-float +le/m64/bs/p/m;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul +le/m64/bs/p/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mhard-float +le/m64/bs/p/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float + +As part of this the order of the multilibs was changes from upstream to make +it easier to avoid big-endian m64, which is not supported by the toolchain. + +Upstream-Status: Inappropriate [AMD Microblaze specific] + +Signed-off-by: Mark Hatle + +Index: gcc-12.2.0/gcc/config/microblaze/t-microblaze +=================================================================== +--- gcc-12.2.0.orig/gcc/config/microblaze/t-microblaze ++++ gcc-12.2.0/gcc/config/microblaze/t-microblaze +@@ -1,17 +1,11 @@ +-MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high +-#MULTILIB_DIRNAMES = m64 bs le m mh +-MULTILIB_DIRNAMES = . . . . . +-MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high +-MULTILIB_EXCEPTIONS += *m64 +-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift +-MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul +-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul +-MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul +-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high +-MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high ++MULTILIB_OPTIONS = mlittle-endian m64 mxl-barrel-shift mxl-pattern-compare mno-xl-soft-mul mhard-float ++MULTILIB_DIRNAMES = le m64 bs p m fpd ++MULTILIB_EXCEPTIONS = mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high +-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mxl-pattern-compare*/*mxl-multiply-high* ++# Big endian m64 is not supported ++MULTILIB_EXCEPTIONS += m64* + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \ diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-source_12.%.bbappend b/meta-vitis-tc/recipes-devtools/gcc/gcc-source_12.%.bbappend deleted file mode 100644 index a439407d..00000000 --- a/meta-vitis-tc/recipes-devtools/gcc/gcc-source_12.%.bbappend +++ /dev/null @@ -1,6 +0,0 @@ -# Add MicroBlaze Patches (only when using MicroBlaze) -FILESEXTRAPATHS:append := ":${THISDIR}/gcc-12" -SRC_URI += " \ - file://additional-microblaze-multilibs.patch \ - file://riscv-multilib-generator-python.patch \ -" diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-source_13.%.bbappend b/meta-vitis-tc/recipes-devtools/gcc/gcc-source_13.%.bbappend index d7b58f1e..e38dd8b3 100644 --- a/meta-vitis-tc/recipes-devtools/gcc/gcc-source_13.%.bbappend +++ b/meta-vitis-tc/recipes-devtools/gcc/gcc-source_13.%.bbappend @@ -1,4 +1,5 @@ FILESEXTRAPATHS:append := ":${THISDIR}/gcc-13" SRC_URI += " \ + file://additional-microblaze-multilibs.patch \ file://riscv-multilib-generator-python.patch \ " -- cgit v1.2.3-54-g00ecf