From 8ea75cc272182dbda8c3ac9daaed2d85f0546030 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 28 Jul 2022 21:58:26 -0500 Subject: meta-microblaze: Move to gcc-12 to match OE-Core Signed-off-by: Mark Hatle --- ...CAL-Testsuite-builtins-tests-require-fpic.patch | 35 - ...0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch | 31 - ...ejagnu-static-testing-on-qemu-suppress-wa.patch | 35 - ...uite-Add-MicroBlaze-to-target-supports-fo.patch | 35 - ...-testsuite-Update-MicroBlaze-strings-test.patch | 36 - ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch | 67 - ...uite-Add-MicroBlaze-to-check_profiling_av.patch | 28 - ...-Patch-microblaze-Fix-atomic-side-effects.patch | 68 - ...icroblaze-Fix-atomic-boolean-return-value.patch | 40 - ...blaze-Fix-the-Microblaze-crash-with-msmal.patch | 33 - ...ch-microblaze-Added-ashrsi3_with_size_opt.patch | 48 - ...-microblaze-Use-bralid-for-profiler-calls.patch | 26 - ...-Patch-microblaze-Removed-moddi3-routinue.patch | 160 -- ...atch-microblaze-Add-INIT_PRIORITY-support.patch | 101 - ...15-Patch-microblaze-Add-optimized-lshrsi3.patch | 81 - .../0016-Patch-microblaze-Add-cbranchsi4_reg.patch | 147 -- ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch | 58 - ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch | 63 - ...-microblaze-Update-ashlsi3-movsf-patterns.patch | 72 - ...icroblaze-8-stage-pipeline-for-microblaze.patch | 178 -- ...blaze-Correct-the-const-high-double-immed.patch | 58 - ...aze-Fix-internal-compiler-error-with-msma.patch | 36 - ...blaze-Fix-the-calculation-of-high-word-in.patch | 45 - .../0024-Patch-MicroBlaze-this-patch-has.patch | 372 --- ...5-Fixing-the-issue-with-the-builtin_alloc.patch | 44 - ...blaze-Removed-fsqrt-generation-for-double.patch | 38 - ...oBlaze-Intial-commit-of-64-bit-Microblaze.patch | 784 ------- .../0028-Intial-commit-for-64bit-MB-sources.patch | 2451 -------------------- ...29-re-arrangement-of-the-compare-branches.patch | 268 --- ...blaze-previous-commit-broke-the-handling-.patch | 28 - ...-Microblaze-Support-of-multilibs-with-m64.patch | 73 - .../gcc/gcc-11/0032-Fixed-issues-like.patch | 70 - .../gcc/gcc-11/0033-Fixed-below-issues.patch | 307 --- .../0034-Added-double-arith-instructions.patch | 135 -- ...ssue-in-the-delay-slot-with-swap-instruct.patch | 37 - ...oad-store-issue-with-the-32bit-arith-libr.patch | 256 -- ...ing-the-Dwarf-support-to-64bit-Microblaze.patch | 25 - ...38-fixing-the-typo-errors-in-umodsi3-file.patch | 29 - ...xing-the-32bit-LTO-related-issue9-1014024.patch | 68 - ...issing-stack-adjustment-in-prologue-of-mo.patch | 25 - ...blaze-corrected-SPN-for-dlong-instruction.patch | 29 - ...-the-long-long-long-mingw-toolchain-issue.patch | 59 - ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch | 47 - ...blaze-We-will-check-the-possibility-of-pe.patch | 87 - ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch | 466 ---- .../0046-Author-Nagaraju-nmekala-xilinx.com.patch | 479 ---- ...B-64-single-register-arithmetic-instructi.patch | 107 - ...Blaze-Added-support-for-64-bit-Immediate-.patch | 44 - ...blaze-Fix-Compiler-crash-with-freg-struct.patch | 86 - ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch | 45 - ...oblaze-Reducing-Stack-space-for-arguments.patch | 198 -- .../gcc/gcc-11/0052-Patch-MicroBlaze.patch | 72 - ...croblaze64-Add-Zero_extended-instructions.patch | 57 - .../gcc/gcc-11/microblaze-mulitlib-hack.patch | 58 - ...CAL-Testsuite-builtins-tests-require-fpic.patch | 35 + ...0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch | 31 + ...ejagnu-static-testing-on-qemu-suppress-wa.patch | 35 + ...uite-Add-MicroBlaze-to-target-supports-fo.patch | 35 + ...-testsuite-Update-MicroBlaze-strings-test.patch | 36 + ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch | 67 + ...uite-Add-MicroBlaze-to-check_profiling_av.patch | 28 + ...-Patch-microblaze-Fix-atomic-side-effects.patch | 68 + ...icroblaze-Fix-atomic-boolean-return-value.patch | 40 + ...blaze-Fix-the-Microblaze-crash-with-msmal.patch | 33 + ...ch-microblaze-Added-ashrsi3_with_size_opt.patch | 48 + ...-microblaze-Use-bralid-for-profiler-calls.patch | 26 + ...-Patch-microblaze-Removed-moddi3-routinue.patch | 160 ++ ...atch-microblaze-Add-INIT_PRIORITY-support.patch | 101 + ...15-Patch-microblaze-Add-optimized-lshrsi3.patch | 81 + .../0016-Patch-microblaze-Add-cbranchsi4_reg.patch | 147 ++ ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch | 58 + ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch | 63 + ...-microblaze-Update-ashlsi3-movsf-patterns.patch | 72 + ...icroblaze-8-stage-pipeline-for-microblaze.patch | 178 ++ ...blaze-Correct-the-const-high-double-immed.patch | 58 + ...aze-Fix-internal-compiler-error-with-msma.patch | 36 + ...blaze-Fix-the-calculation-of-high-word-in.patch | 45 + .../0024-Patch-MicroBlaze-this-patch-has.patch | 372 +++ ...5-Fixing-the-issue-with-the-builtin_alloc.patch | 44 + ...blaze-Removed-fsqrt-generation-for-double.patch | 38 + ...oBlaze-Intial-commit-of-64-bit-Microblaze.patch | 784 +++++++ .../0028-Intial-commit-for-64bit-MB-sources.patch | 2451 ++++++++++++++++++++ ...29-re-arrangement-of-the-compare-branches.patch | 268 +++ ...blaze-previous-commit-broke-the-handling-.patch | 28 + ...-Microblaze-Support-of-multilibs-with-m64.patch | 73 + .../gcc/gcc-12/0032-Fixed-issues-like.patch | 70 + .../gcc/gcc-12/0033-Fixed-below-issues.patch | 307 +++ .../0034-Added-double-arith-instructions.patch | 135 ++ ...ssue-in-the-delay-slot-with-swap-instruct.patch | 37 + ...oad-store-issue-with-the-32bit-arith-libr.patch | 256 ++ ...ing-the-Dwarf-support-to-64bit-Microblaze.patch | 25 + ...38-fixing-the-typo-errors-in-umodsi3-file.patch | 29 + ...xing-the-32bit-LTO-related-issue9-1014024.patch | 68 + ...issing-stack-adjustment-in-prologue-of-mo.patch | 25 + ...blaze-corrected-SPN-for-dlong-instruction.patch | 29 + ...-the-long-long-long-mingw-toolchain-issue.patch | 59 + ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch | 47 + ...blaze-We-will-check-the-possibility-of-pe.patch | 87 + ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch | 466 ++++ .../0046-Author-Nagaraju-nmekala-xilinx.com.patch | 479 ++++ ...B-64-single-register-arithmetic-instructi.patch | 107 + ...Blaze-Added-support-for-64-bit-Immediate-.patch | 44 + ...blaze-Fix-Compiler-crash-with-freg-struct.patch | 86 + ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch | 45 + ...oblaze-Reducing-Stack-space-for-arguments.patch | 198 ++ .../gcc/gcc-12/0052-Patch-MicroBlaze.patch | 72 + ...croblaze64-Add-Zero_extended-instructions.patch | 57 + .../gcc/gcc-12/microblaze-mulitlib-hack.patch | 58 + .../recipes-devtools/gcc/gcc-source_11.%.bbappend | 59 - .../recipes-devtools/gcc/gcc-source_12.%.bbappend | 59 + 110 files changed, 8384 insertions(+), 8384 deletions(-) delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch delete mode 100644 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meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend (limited to 'meta-microblaze/recipes-devtools/gcc') diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch deleted file mode 100644 index 9750cee8..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 89825e41d91ef04532a7a53d72f4eb33ad40d1d9 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 13:13:57 +0530 -Subject: [PATCH 01/53] LOCAL]: Testsuite - builtins tests require fpic - Signed-off-by: David Holsgrove - -Conflicts: - - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ---- - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -index baec137d9a3..ad62a7348bc 100644 ---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] - lappend additional_flags "-Wl,--allow-multiple-definition" - } - -+<<<<<<< HEAD -+======= -+if [istarget "microblaze*-*-linux*"] { -+ lappend additional_flags "-Wl,-zmuldefs" -+ lappend additional_flags "-fPIC" -+} -+ -+>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic - foreach src [lsort [find $srcdir/$subdir *.c]] { - if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { - c-torture-execute [list $src \ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch deleted file mode 100644 index bfb98bcd..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 997e53fc324c3414d09a883a7bff28e1e346c847 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 14:31:10 +0530 -Subject: [PATCH 02/53] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This - particular testcase fails with a timeout. Instead, fail it at compile-time - for microblaze. This speeds up the testsuite without removing it from the - FAIL reports. - -Signed-off-by: Edgar E. Iglesias ---- - gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C -index 3862756083d..db9f990f781 100644 ---- a/gcc/testsuite/g++.dg/opt/memcpy1.C -+++ b/gcc/testsuite/g++.dg/opt/memcpy1.C -@@ -4,6 +4,10 @@ - // { dg-do compile } - // { dg-options "-O" } - -+#if defined (__MICROBLAZE__) -+#error "too slow on mb. Investigate." -+#endif -+ - typedef unsigned char uint8_t; - typedef uint8_t uint8; - __extension__ typedef __SIZE_TYPE__ size_t; --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch deleted file mode 100644 index 6a4b907a..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 66fb54b40c49c86e8cefa94523a3f65a6779d6f2 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 15:46:28 +0530 -Subject: [PATCH 03/53] [LOCAL]: For dejagnu static testing on qemu, suppress - warnings about multiple definitions from the test function and libc in line - with method used by powerpc. Dynamic linking and using a qemu binary which - understands sysroot resolves all test failures with builtins - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ---- - 1 file changed, 4 deletions(-) - -diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -index ad62a7348bc..3a38fb1de91 100644 ---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] - lappend additional_flags "-Wl,--allow-multiple-definition" - } - --<<<<<<< HEAD --======= - if [istarget "microblaze*-*-linux*"] { - lappend additional_flags "-Wl,-zmuldefs" -- lappend additional_flags "-fPIC" - } - -->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic - foreach src [lsort [find $srcdir/$subdir *.c]] { - if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { - c-torture-execute [list $src \ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch deleted file mode 100644 index 0d907474..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch +++ /dev/null @@ -1,35 +0,0 @@ -From dd488cfaf9f909462290c85a1e30665f6252cbf1 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 15:50:35 +0530 -Subject: [PATCH 04/53] [Patch, testsuite]: Add MicroBlaze to target-supports - for atomic buil. .tin tests - -MicroBlaze added to supported targets for atomic builtin tests. - -Changelog/testsuite - -2014-02-14 David Holsgrove - - * gcc/testsuite/lib/target-supports.exp: Add microblaze to - check_effective_target_sync_int_long. - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/lib/target-supports.exp | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index 411e559f508..9e6a1480e8f 100644 ---- a/gcc/testsuite/lib/target-supports.exp -+++ b/gcc/testsuite/lib/target-supports.exp -@@ -7958,6 +7958,7 @@ proc check_effective_target_sync_int_long { } { - && [check_effective_target_arm_acq_rel]) - || [istarget bfin*-*linux*] - || [istarget hppa*-*linux*] -+ || [istarget microblaze*-*linux*] - || [istarget s390*-*-*] - || [istarget powerpc*-*-*] - || [istarget cris-*-*] --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch deleted file mode 100644 index 1714c142..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 5576c4ca7641833a91b19b36d105a6b852c1a0cc Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 11 Jan 2017 16:20:01 +0530 -Subject: [PATCH 05/53] [Patch, testsuite]: Update MicroBlaze strings test for - new scan-assembly output resulting in use of $LC label - -ChangeLog/testsuite - -2014-02-14 David Holsgrove - - * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update - to include $LC label. - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/gcc.target/microblaze/others/strings1.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c -index efaf3c660ea..347872360d3 100644 ---- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c -+++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c -@@ -3,6 +3,10 @@ - /* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ - /* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ - -+/* { dg-final { scan-assembler "\.rodata*" } } */ -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ -+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ -+ - #include - - extern void somefunc (char *); --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch deleted file mode 100644 index def6e95e..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch +++ /dev/null @@ -1,67 +0,0 @@ -From ea6a9f11d6a866fe20cca13d06c7386754543e6c Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:14:15 +0530 -Subject: [PATCH 06/53] [Patch, testsuite]: Allow MicroBlaze .weakext pattern - in regex match Extend regex pattern to include optional ext at the end of - .weak to match the MicroBlaze weak label .weakext - -ChangeLog/testsuite - -2014-02-14 David Holsgrove - - * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler - pattern to take optional ext after .weak. - * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. - -Signed-off-by: David Holsgrove - -Conflicts: - - gcc/testsuite/g++.dg/abi/rtti3.C ---- - gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++-- - gcc/testsuite/g++.dg/abi/thunk3.C | 2 +- - gcc/testsuite/g++.dg/abi/thunk4.C | 2 +- - 3 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C -index 0cc7d3e79d0..f284cd9255c 100644 ---- a/gcc/testsuite/g++.dg/abi/rtti3.C -+++ b/gcc/testsuite/g++.dg/abi/rtti3.C -@@ -3,8 +3,8 @@ - - // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } --// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } } --// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } - // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } } - // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } } - -diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C -index f2347f79ecd..dcec8a771a1 100644 ---- a/gcc/testsuite/g++.dg/abi/thunk3.C -+++ b/gcc/testsuite/g++.dg/abi/thunk3.C -@@ -1,5 +1,5 @@ - // { dg-require-weak "" } --// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } - // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } - - struct Base -diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C -index 6e8f124bc5e..d1d34fe1e4a 100644 ---- a/gcc/testsuite/g++.dg/abi/thunk4.C -+++ b/gcc/testsuite/g++.dg/abi/thunk4.C -@@ -1,6 +1,6 @@ - // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } --// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } -+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } - // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } - - struct Base --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch deleted file mode 100644 index 5f72ecd2..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch +++ /dev/null @@ -1,28 +0,0 @@ -From fe007d78e220606b220dfc452fe9564ebfecd57a Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:34:27 +0530 -Subject: [PATCH 07/53] [Patch, testsuite]: Add MicroBlaze to - check_profiling_available Testsuite, add microblaze*-*-* target in - check_profiling_available inline with other archs setting - profiling_available_saved to 0 - -Signed-off-by: David Holsgrove ---- - gcc/testsuite/lib/target-supports.exp | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index 9e6a1480e8f..7e9d0889f76 100644 ---- a/gcc/testsuite/lib/target-supports.exp -+++ b/gcc/testsuite/lib/target-supports.exp -@@ -727,6 +727,7 @@ proc check_profiling_available { test_what } { - || [istarget m68k-*-elf] - || [istarget m68k-*-uclinux*] - || [istarget mips*-*-elf*] -+ || [istarget microblaze*-*-*] - || [istarget mmix-*-*] - || [istarget mn10300-*-elf*] - || [istarget moxie-*-elf*] --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0008-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0008-Patch-microblaze-Fix-atomic-side-effects.patch deleted file mode 100644 index 78dc5dcd..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0008-Patch-microblaze-Fix-atomic-side-effects.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 63b07793addb119dfc3ec0a30225e767d8f48706 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:41:43 +0530 -Subject: [PATCH 08/53] [Patch, microblaze]: Fix atomic side effects. In - atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions - during optimization. Previously, the outputs were considered unused; this - generated assembly code with undefined side effects after invocation of the - atomic. - -Signed-off-by: Kirk Meyer -Signed-off-by: David Holsgrove - -Conflicts: - gcc/config/microblaze/microblaze.md ---- - gcc/config/microblaze/microblaze.md | 3 +++ - gcc/config/microblaze/sync.md | 21 +++++++++++++-------- - 2 files changed, 16 insertions(+), 8 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 472ef4c1d8d..b02034c9f1e 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -43,6 +43,9 @@ - (UNSPEC_TLS 106) ;; jump table - (UNSPEC_SET_TEXT 107) ;; set text start - (UNSPEC_TEXT 108) ;; data text relative -+ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool) -+ (UNSPECV_CAS_VAL 202) ;; compare and swap (val) -+ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem) - ]) - - (define_c_enum "unspec" [ -diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index 23e0f1c52e2..3b0fba1d3cf 100644 ---- a/gcc/config/microblaze/sync.md -+++ b/gcc/config/microblaze/sync.md -@@ -18,14 +18,19 @@ - ;; . - - (define_insn "atomic_compare_and_swapsi" -- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output -- (match_operand:SI 1 "register_operand" "=&d") ;; val output -- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory -- (match_operand:SI 3 "register_operand" "d") ;; expected value -- (match_operand:SI 4 "register_operand" "d") ;; desired value -- (match_operand:SI 5 "const_int_operand" "") ;; is_weak -- (match_operand:SI 6 "const_int_operand" "") ;; mod_s -- (match_operand:SI 7 "const_int_operand" "") ;; mod_f -+ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output -+ (unspec_volatile:SI -+ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory -+ (match_operand:SI 3 "register_operand" "d") ;; expected value -+ (match_operand:SI 4 "register_operand" "d")] ;; desired value -+ UNSPECV_CAS_BOOL)) -+ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output -+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL)) -+ (set (match_dup 2) -+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM)) -+ (match_operand:SI 5 "const_int_operand" "") ;; is_weak -+ (match_operand:SI 6 "const_int_operand" "") ;; mod_s -+ (match_operand:SI 7 "const_int_operand" "") ;; mod_f - (clobber (match_scratch:SI 8 "=&d"))] - "" - { --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch deleted file mode 100644 index 824b031c..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 0aa9647936673e3ff1ac0082144b196309916ddb Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:45:45 +0530 -Subject: [PATCH 09/53] [Patch, microblaze]: Fix atomic boolean return value. - In atomic_compare_and_swapsi, fix boolean return value. Previously, it - contained zero if successful and non-zero if unsuccessful. - -Signed-off-by: Kirk Meyer -Signed-off-by: David Holsgrove ---- - gcc/config/microblaze/sync.md | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index 3b0fba1d3cf..d08400af4bb 100644 ---- a/gcc/config/microblaze/sync.md -+++ b/gcc/config/microblaze/sync.md -@@ -34,15 +34,16 @@ - (clobber (match_scratch:SI 8 "=&d"))] - "" - { -- output_asm_insn ("addc \tr0,r0,r0", operands); -+ output_asm_insn ("add \t%0,r0,r0", operands); - output_asm_insn ("lwx \t%1,%y2,r0", operands); - output_asm_insn ("addic\t%8,r0,0", operands); - output_asm_insn ("bnei \t%8,.-8", operands); -- output_asm_insn ("cmp \t%0,%1,%3", operands); -- output_asm_insn ("bnei \t%0,.+16", operands); -+ output_asm_insn ("cmp \t%8,%1,%3", operands); -+ output_asm_insn ("bnei \t%8,.+20", operands); - output_asm_insn ("swx \t%4,%y2,r0", operands); - output_asm_insn ("addic\t%8,r0,0", operands); - output_asm_insn ("bnei \t%8,.-28", operands); -+ output_asm_insn ("addi \t%0,r0,1", operands); - return ""; - } - ) --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch deleted file mode 100644 index a1896298..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a950e2d4fb15e9ebabe11a5606f24a510f297d6d Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:50:17 +0530 -Subject: [PATCH 10/53] [Patch, microblaze]: Fix the Microblaze crash with - msmall-divides flag Compiler is crashing when we use msmall-divides and - mxl-barrel-shift flag. This is because when use above flags - microblaze_expand_divide function will be called for division operation. In - microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't - have subreg register due to this compiler was crashing. Changed the logic to - avoid sub_reg call - -Signed-off-by:Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index b444db17719..45405fa2160 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3709,8 +3709,7 @@ microblaze_expand_divide (rtx operands[]) - mem_rtx = gen_rtx_MEM (QImode, - gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); - -- insn = emit_insn (gen_movqi (regqi, mem_rtx)); -- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); -+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); - JUMP_LABEL (jump) = div_end_label; - LABEL_NUSES (div_end_label) = 1; --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch deleted file mode 100644 index 597e4e6e..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 3c984648f42e5fcf586c4327f108486fb8630f0d Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 16:52:56 +0530 -Subject: [PATCH 11/53] [Patch, microblaze]: Added ashrsi3_with_size_opt Added - ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os - optimization is used. lshrsi3_with_size_opt is being removed as it has - conflicts with unsigned int variables - -Signed-off-by:Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index b02034c9f1e..55477fd0a69 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1508,6 +1508,27 @@ - (set_attr "length" "4,4")] - ) - -+(define_insn "*ashrsi3_with_size_opt" -+ [(set (match_operand:SI 0 "register_operand" "=&d") -+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "immediate_operand" "I")))] -+ "(INTVAL (operands[2]) > 5 && optimize_size)" -+ { -+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("ori\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addik\t%3,%3,-1", operands); -+ output_asm_insn ("bneid\t%3,.-4", operands); -+ return "sra\t%0,%0"; -+ } -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "20")] -+) -+ - (define_insn "*ashrsi_inline" - [(set (match_operand:SI 0 "register_operand" "=&d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch deleted file mode 100644 index 917b6d70..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch +++ /dev/null @@ -1,26 +0,0 @@ -From fa6e9e4317f9adb0748ade5029cbe3a10504ab54 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 10:57:19 +0530 -Subject: [PATCH 12/53] [Patch, microblaze]: Use bralid for profiler calls - Signed-off-by: Edgar E. Iglesias - ---- - gcc/config/microblaze/microblaze.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 2ecec750526..e32ce7dbb51 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -486,7 +486,7 @@ typedef struct microblaze_args - - #define FUNCTION_PROFILER(FILE, LABELNO) { \ - { \ -- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \ -+ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \ - } \ - } - --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0013-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0013-Patch-microblaze-Removed-moddi3-routinue.patch deleted file mode 100644 index 0891750a..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0013-Patch-microblaze-Removed-moddi3-routinue.patch +++ /dev/null @@ -1,160 +0,0 @@ -From a5b58621655fa306c37157dfe3092547adce0aab Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Thu, 12 Jan 2017 17:36:16 +0530 -Subject: [PATCH 13/53] [Patch, microblaze]: Removed moddi3 routinue Using the - default moddi3 function as the existing implementation has many bugs - -Signed-off-by:Nagaraju - -Conflicts: - libgcc/config/microblaze/moddi3.S ---- - libgcc/config/microblaze/moddi3.S | 121 -------------------------- - libgcc/config/microblaze/t-microblaze | 3 +- - 2 files changed, 1 insertion(+), 123 deletions(-) - delete mode 100644 libgcc/config/microblaze/moddi3.S - -diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S -deleted file mode 100644 -index 4bac960107e..00000000000 ---- a/libgcc/config/microblaze/moddi3.S -+++ /dev/null -@@ -1,121 +0,0 @@ --################################### --# --# Copyright (C) 2009-2021 Free Software Foundation, Inc. --# --# Contributed by Michael Eager . --# --# This file is free software; you can redistribute it and/or modify it --# under the terms of the GNU General Public License as published by the --# Free Software Foundation; either version 3, or (at your option) any --# later version. --# --# GCC is distributed in the hope that it will be useful, but WITHOUT --# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public --# License for more details. --# --# Under Section 7 of GPL version 3, you are granted additional --# permissions described in the GCC Runtime Library Exception, version --# 3.1, as published by the Free Software Foundation. --# --# You should have received a copy of the GNU General Public License and --# a copy of the GCC Runtime Library Exception along with this program; --# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --# . --# --# modsi3.S --# --# modulo operation for 64 bit integers. --# --####################################### -- -- --/* An executable stack is *not* required for these functions. */ --#ifdef __linux__ --.section .note.GNU-stack,"",%progbits --.previous --#endif -- -- .globl __moddi3 -- .ent __moddi3 --__moddi3: -- .frame r1,0,r15 -- --#Change the stack pointer value and Save callee saved regs -- addik r1,r1,-24 -- swi r25,r1,0 -- swi r26,r1,4 -- swi r27,r1,8 # used for sign -- swi r28,r1,12 # used for loop count -- swi r29,r1,16 # Used for div value High -- swi r30,r1,20 # Used for div value Low -- --#Check for Zero Value in the divisor/dividend -- OR r9,r5,r6 # Check for the op1 being zero -- BEQID r9,$LaResult_Is_Zero # Result is zero -- OR r9,r7,r8 # Check for the dividend being zero -- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error -- BGEId r5,$La1_Pos -- XOR r27,r5,r7 # Get the sign of the result -- RSUBI r6,r6,0 # Make dividend positive -- RSUBIC r5,r5,0 # Make dividend positive --$La1_Pos: -- BGEI r7,$La2_Pos -- RSUBI r8,r8,0 # Make Divisor Positive -- RSUBIC r9,r9,0 # Make Divisor Positive --$La2_Pos: -- ADDIK r4,r0,0 # Clear mod low -- ADDIK r3,r0,0 # Clear mod high -- ADDIK r29,r0,0 # clear div high -- ADDIK r30,r0,0 # clear div low -- ADDIK r28,r0,64 # Initialize the loop count -- # First part try to find the first '1' in the r5/r6 --$LaDIV1: -- ADD r6,r6,r6 -- ADDC r5,r5,r5 # left shift logical r5 -- BGEID r5,$LaDIV1 -- ADDIK r28,r28,-1 --$LaDIV2: -- ADD r6,r6,r6 -- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry -- ADDC r4,r4,r4 # Move that bit into the Mod register -- ADDC r3,r3,r3 # Move carry into high mod register -- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor -- bnei r18,$L_High_EQ -- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h] --$L_High_EQ: -- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L] -- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H] -- BLTi r25,$LaMOD_TOO_SMALL -- OR r3,r0,r25 # move r25 to mod [h] -- OR r4,r0,r26 # move r26 to mod [l] -- ADDI r30,r30,1 -- ADDC r29,r29,r0 --$LaMOD_TOO_SMALL: -- ADDIK r28,r28,-1 -- BEQi r28,$LaLOOP_END -- ADD r30,r30,r30 # Shift in the '1' into div [low] -- ADDC r29,r29,r29 # Move the carry generated into high -- BRI $LaDIV2 # Div2 --$LaLOOP_END: -- BGEI r27,$LaRETURN_HERE -- rsubi r30,r30,0 -- rsubc r29,r29,r0 -- BRI $LaRETURN_HERE --$LaDiv_By_Zero: --$LaResult_Is_Zero: -- or r29,r0,r0 # set result to 0 [High] -- or r30,r0,r0 # set result to 0 [Low] --$LaRETURN_HERE: --# Restore values of CSRs and that of r29 and the divisor and the dividend -- -- lwi r25,r1,0 -- lwi r26,r1,4 -- lwi r27,r1,8 -- lwi r28,r1,12 -- lwi r29,r1,16 -- lwi r30,r1,20 -- rtsd r15,8 -- addik r1,r1,24 -- .end __moddi3 -- -diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 96959f0292b..8d954a49575 100644 ---- a/libgcc/config/microblaze/t-microblaze -+++ b/libgcc/config/microblaze/t-microblaze -@@ -1,8 +1,7 @@ --LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3 -+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 - - LIB2ADD += \ - $(srcdir)/config/microblaze/divsi3.S \ -- $(srcdir)/config/microblaze/moddi3.S \ - $(srcdir)/config/microblaze/modsi3.S \ - $(srcdir)/config/microblaze/muldi3_hard.S \ - $(srcdir)/config/microblaze/mulsi3.S \ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch deleted file mode 100644 index cbee1692..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch +++ /dev/null @@ -1,101 +0,0 @@ -From a9abf680767f4294177d716cd95a9bec5c7916a7 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 14:41:58 +0530 -Subject: [PATCH 14/53] [Patch, microblaze]: Add INIT_PRIORITY support Added - TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. - -These macros allows users to control the order of initialization -of objects defined at namespace scope with the init_priority -attribute by specifying a relative priority, a constant integral -expression currently bounded between 101 and 65535 inclusive. - -Lower numbers indicate a higher priority. - -Changelog - -2013-11-26 Nagaraju Mekala - - * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor, - microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and - TARGET_ASM_DESTRUCTOR. - -Signed-off-by:nagaraju -Signed-off-by: David Holsgrove ---- - gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++ - 1 file changed, 53 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 45405fa2160..62630aab64e 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2634,6 +2634,53 @@ print_operand_address (FILE * file, rtx addr) - } - } - -+/* Output an element in the table of global constructors. */ -+void -+microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) -+{ -+ const char *section = ".ctors"; -+ char buf[16]; -+ -+ if (priority != DEFAULT_INIT_PRIORITY) -+ { -+ sprintf (buf, ".ctors.%.5u", -+ /* Invert the numbering so the linker puts us in the proper -+ order; constructors are run from right to left, and the -+ linker sorts in increasing order. */ -+ MAX_INIT_PRIORITY - priority); -+ section = buf; -+ } -+ -+ switch_to_section (get_section (section, 0, NULL)); -+ assemble_align (POINTER_SIZE); -+ fputs ("\t.word\t", asm_out_file); -+ output_addr_const (asm_out_file, symbol); -+ fputs ("\n", asm_out_file); -+} -+ -+/* Output an element in the table of global destructors. */ -+void -+microblaze_asm_destructor (rtx symbol, int priority) -+{ -+ const char *section = ".dtors"; -+ char buf[16]; -+ if (priority != DEFAULT_INIT_PRIORITY) -+ { -+ sprintf (buf, ".dtors.%.5u", -+ /* Invert the numbering so the linker puts us in the proper -+ order; constructors are run from right to left, and the -+ linker sorts in increasing order. */ -+ MAX_INIT_PRIORITY - priority); -+ section = buf; -+ } -+ -+ switch_to_section (get_section (section, 0, NULL)); -+ assemble_align (POINTER_SIZE); -+ fputs ("\t.word\t", asm_out_file); -+ output_addr_const (asm_out_file, symbol); -+ fputs ("\n", asm_out_file); -+} -+ - /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol - is used, so that we don't emit an .extern for it in - microblaze_asm_file_end. */ -@@ -3975,6 +4022,12 @@ microblaze_starting_frame_offset (void) - #undef TARGET_ATTRIBUTE_TABLE - #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table - -+#undef TARGET_ASM_CONSTRUCTOR -+#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor -+ -+#undef TARGET_ASM_DESTRUCTOR -+#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor -+ - #undef TARGET_IN_SMALL_DATA_P - #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p - --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0015-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0015-Patch-microblaze-Add-optimized-lshrsi3.patch deleted file mode 100644 index 42d836cb..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0015-Patch-microblaze-Add-optimized-lshrsi3.patch +++ /dev/null @@ -1,81 +0,0 @@ -From fe3572f4b0cc033db305b0d67abb88632bf13887 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 15:23:57 +0530 -Subject: [PATCH 15/53] [Patch, microblaze]: Add optimized lshrsi3 When barrel - shifter is not present, the immediate value is greater than #5 and - optimization is -OS, the compiler will generate shift operation using loop. - -Changelog - -2013-11-26 David Holsgrove - - * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn - -ChangeLog/testsuite - -2014-02-12 David Holsgrove - - * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. - -Signed-off-by:Nagaraju -Signed-off-by: David Holsgrove ---- - gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++ - .../microblaze/others/lshrsi_Os_1.c | 13 ++++++++++++ - 2 files changed, 34 insertions(+) - create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 55477fd0a69..f85d8fcac8a 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1618,6 +1618,27 @@ - (set_attr "length" "4,4")] - ) - -+(define_insn "*lshrsi3_with_size_opt" -+ [(set (match_operand:SI 0 "register_operand" "=&d") -+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "immediate_operand" "I")))] -+ "(INTVAL (operands[2]) > 5 && optimize_size)" -+ { -+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("ori\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addik\t%3,%3,-1", operands); -+ output_asm_insn ("bneid\t%3,.-4", operands); -+ return "srl\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "SI") -+ (set_attr "length" "20")] -+) -+ - (define_insn "*lshrsi_inline" - [(set (match_operand:SI 0 "register_operand" "=&d") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") -diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c -new file mode 100644 -index 00000000000..32a3be7c76a ---- /dev/null -+++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c -@@ -0,0 +1,13 @@ -+/* { dg-options "-Os -mno-xl-barrel-shift" } */ -+ -+void testfunc(void) -+{ -+ unsigned volatile int z = 8192; -+ z >>= 8; -+} -+/* { dg-final { scan-assembler-not "\bsrli" } } */ -+/* { dg-final { scan-assembler "\ori\tr18,r0" } } */ -+/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */ -+/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */ -+/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ -+/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0016-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0016-Patch-microblaze-Add-cbranchsi4_reg.patch deleted file mode 100644 index 3ee98b39..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0016-Patch-microblaze-Add-cbranchsi4_reg.patch +++ /dev/null @@ -1,147 +0,0 @@ -From 3ace42f94961162022e9e7baf3e3509fc1a1bfa4 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 17:04:37 +0530 -Subject: [PATCH 16/53] [Patch, microblaze]: Add cbranchsi4_reg This patch - optimizes the generation of pcmpne/pcmpeq instruction if the compare - instruction has no immediate values.For the immediate values the xor - instruction is generated - -Signed-off-by: Nagaraju Mekala -Signed-off-by: Ajit Agarwal - -ChangeLog: -2015-01-13 Nagaraju Mekala - Ajit Agarwal - - *microblaze.md (cbranchsi4_reg): New - *microblaze.c (microblaze_expand_conditional_branch_reg): New - -Conflicts: - - gcc/config/microblaze/microblaze-protos.h ---- - gcc/config/microblaze/microblaze-protos.h | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +- - gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++------- - gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------ - 7 files changed, 18 insertions(+), 18 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index 54c26969fbd..3a5f439703c 100644 ---- a/gcc/config/microblaze/microblaze-protos.h -+++ b/gcc/config/microblaze/microblaze-protos.h -@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *); - extern bool microblaze_expand_move (machine_mode, rtx *); - extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); - extern void microblaze_expand_divide (rtx *); --extern void microblaze_expand_conditional_branch (machine_mode, rtx *); -+extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_sf (rtx *); - extern int microblaze_can_use_return_insn (void); -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c -index 4041a241391..ccc6a461cd9 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c -@@ -6,5 +6,5 @@ void float_func () - { - /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if (f2 <= f3) -- print ("le"); -+ f2 = f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c -index 3902b839db9..1dd5fe6c539 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c -@@ -6,5 +6,5 @@ void float_func () - { - /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if (f2 < f3) -- print ("lt"); -+ f2 = f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c -index 8555974dda5..d6f80fb0ec3 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c -@@ -6,5 +6,5 @@ void float_func () - { - /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if (f2 == f3) -- print ("eq"); -+ f1 = f2 + f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c -index 79cc5f9dd8e..d1177249552 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c -@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3) - /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ - if(f1==f2 && f1<=f3) -- print ("f1 eq f2 && f1 le f3"); -+ f2 = f3; - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c -index ebfb170ecee..75822977ef8 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c -@@ -5,17 +5,17 @@ volatile float f1, f2, f3; - void float_func () - { - /* { dg-final { scan-assembler-not "fcmp" } } */ -- if (f2 <= f3) -- print ("le"); -+ if (f2 <= f3) -+ f1 = f3; - else if (f2 == f3) -- print ("eq"); -+ f1 = f3; - else if (f2 < f3) -- print ("lt"); -+ f1 = f3; - else if (f2 > f3) -- print ("gt"); -+ f1 = f3; - else if (f2 >= f3) -- print ("ge"); -+ f1 = f3; - else if (f2 != f3) -- print ("ne"); -+ f1 = f3; - - } -diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c -index 1d6ba807b12..532c035adfd 100644 ---- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c -+++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c -@@ -74,16 +74,16 @@ void float_cmp_func () - { - /* { dg-final { scan-assembler-not "fcmp" } } */ - if (f2 <= f3) -- print ("le"); -+ f1 = f3; - else if (f2 == f3) -- print ("eq"); -+ f1 = f3; - else if (f2 < f3) -- print ("lt"); -+ f1 = f3; - else if (f2 > f3) -- print ("gt"); -+ f1 = f3; - else if (f2 >= f3) -- print ("ge"); -+ f1 = f3; - else if (f2 != f3) -- print ("ne"); -+ f1 = f3; - - } --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch deleted file mode 100644 index dcc8b6af..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 2c68b0e5e0307019207e54d1f2d1565053f2e50f Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 17:11:04 +0530 -Subject: [PATCH 17/53] [Patch,microblaze]: Inline Expansion of fsqrt builtin. - The changes are made in the patch for the inline expansion of the fsqrt - builtin with fqrt instruction. The sqrt math function takes double as - argument and return double as argument. The pattern is selected while - expanding the unary op through expand_unop which passes DFmode and the DFmode - pattern was not there returning zero. Thus the sqrt math function is not - inlined and expanded. The pattern with DFmode argument is added. Also the - source and destination argument is not same the DF through two different - consecutive registers with lower 32 bit is the argument passed to sqrt and - the higher 32 bit is zero. If the source and destinations are different the - DFmode 64 bits registers is not set properly giving the problem in runtime. - Such changes are taken care in the implementation of the pattern for DFmode - for inline expansion of the sqrt. - -ChangeLog: -2015-06-16 Ajit Agarwal - Nagaraju Mekala - - * config/microblaze/microblaze.md (sqrtdf2): New - pattern. - -Signed-off-by:Ajit Agarwal ajitkum@xilinx.com - Nagaraju Mekala nmekala@xilinx.com ---- - gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index f85d8fcac8a..254221482af 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -451,6 +451,20 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "sqrtdf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] -+ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" -+ { -+ if (REGNO (operands[0]) == REGNO (operands[1])) -+ return "fsqrt\t%0,%1"; -+ else -+ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; -+ } -+ [(set_attr "type" "fsqrt") -+ (set_attr "mode" "SF") -+ (set_attr "length" "4")]) -+ - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch deleted file mode 100644 index 4aa51cc9..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 9eb2e41cedc278eb16e20383b6c8caad2ce22138 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 18:07:24 +0530 -Subject: [PATCH 18/53] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' - insn definitions Change adddi3 to handle DI immediates as the second operand, - this requires modification to the output template however reduces the need to - specify seperate templates for 16-bit positive/negative immediate operands. - The use of 32-bit immediates for the addi and addic instructions is handled - by the assembler, which will emit the imm instructions when required. This - conveniently handles the optimizable cases where the immediate constant value - does not need the higher half words of the operands upper/lower words. - -Change the constraints of the subdi3 instruction definition such that it -does not match the second operand as an immediate value. This is because -there is no definition to handle this case nor is it possible to -implement purely with instructions as microblaze does not provide an -instruction to perform a forward arithmetic subtraction (it only -provides reverse 'rD = IMM - rA'). - -Signed-off-by: Nathan Rossi ---- - gcc/config/microblaze/microblaze.md | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 254221482af..d86a049355a 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -502,17 +502,16 @@ - ;; Adding 2 DI operands in register or reg/imm - - (define_insn "adddi3" -- [(set (match_operand:DI 0 "register_operand" "=d,d,d") -- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d") -- (match_operand:DI 2 "arith_operand32" "d,P,N")))] -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") -+ (match_operand:DI 2 "arith_operand" "d,i")))] - "" - "@ - add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 -- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0 -- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1" -+ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" - [(set_attr "type" "darith") - (set_attr "mode" "DI") -- (set_attr "length" "8,8,12")]) -+ (set_attr "length" "8,8")]) - - ;;---------------------------------------------------------------- - ;; Subtraction -@@ -549,7 +548,7 @@ - (define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "d") -- (match_operand:DI 2 "arith_operand32" "d")))] -+ (match_operand:DI 2 "register_operand" "d")))] - "" - "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" - [(set_attr "type" "darith") --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch deleted file mode 100644 index b67d8424..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch +++ /dev/null @@ -1,72 +0,0 @@ -From abef7f4d2ad2869c37c4fb2666b52ed700384877 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 17 Jan 2017 18:18:41 +0530 -Subject: [PATCH 19/53] [Patch, microblaze]: Update ashlsi3 & movsf patterns - This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand - of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal - patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our - instruction doesn't support so using gen_int_mode function - -Signed-off-by :Nagaraju Mekala - :Ajit Agarwal - -ChangeLog: -2016-01-07 Nagaraju Mekala - Ajit Agarwal - - *microblaze.md (ashlsi3_with_mul_nodelay, - ashlsi3_with_mul_delay, - movsf_internal): - Updated the patterns to use gen_int_mode function - *microblaze.c (print_operand): - updated the 'F' case to use "unsinged int" instead - of HOST_WIDE_INT_PRINT_HEX ---- - gcc/config/microblaze/microblaze.c | 2 +- - gcc/config/microblaze/microblaze.md | 10 ++++++++-- - 2 files changed, 9 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 62630aab64e..16f3120e415 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2468,7 +2468,7 @@ print_operand (FILE * file, rtx op, int letter) - unsigned long value_long; - REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), - value_long); -- fprintf (file, "0x%lx", value_long); -+ fprintf (file, "0x%08x", (unsigned int) value_long); - } - else - { -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index d86a049355a..986c78f592a 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1368,7 +1368,10 @@ - (match_operand:SI 2 "immediate_operand" "I")))] - "!TARGET_SOFT_MUL - && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)" -- "muli\t%0,%1,%m2" -+ { -+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); -+ return "muli\t%0,%1,%2"; -+ } - ;; This MUL will not generate an imm. Can go into a delay slot. - [(set_attr "type" "arith") - (set_attr "mode" "SI") -@@ -1380,7 +1383,10 @@ - (ashift:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "immediate_operand" "I")))] - "!TARGET_SOFT_MUL" -- "muli\t%0,%1,%m2" -+ { -+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); -+ return "muli\t%0,%1,%2"; -+ } - ;; This MUL will generate an IMM. Cannot go into a delay slot - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "SI") --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch deleted file mode 100644 index 3e19f449..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 39d009f82d0fc316b633a717f173b6195316c8ed Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 9 Nov 2020 19:54:39 +0530 -Subject: [PATCH 20/53] [Patch, microblaze]: 8-stage pipeline for microblaze - -This patch adds the support for the 8-stage pipeline. The new 8-stage -pipeline reduces the latencies of float & integer division drastically - -Signed-off-by :Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.c | 11 ++++ - gcc/config/microblaze/microblaze.h | 3 +- - gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++- - gcc/config/microblaze/microblaze.opt | 4 ++ - 4 files changed, 94 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 16f3120e415..c730faa9814 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -1840,6 +1840,17 @@ microblaze_option_override (void) - "%<-mcpu=v8.30.a%>"); - TARGET_REORDER = 0; - } -+ ver = microblaze_version_to_int("v10.0"); -+ if (ver < 0) -+ { -+ if (TARGET_AREA_OPTIMIZED_2) -+ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater"); -+ } -+ else -+ { -+ if (TARGET_AREA_OPTIMIZED_2) -+ microblaze_pipe = MICROBLAZE_PIPE_8; -+ } - - if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) - error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>"); -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index e32ce7dbb51..21560ec1618 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -27,7 +27,8 @@ - enum pipeline_type - { - MICROBLAZE_PIPE_3 = 0, -- MICROBLAZE_PIPE_5 = 1 -+ MICROBLAZE_PIPE_5 = 1, -+ MICROBLAZE_PIPE_8 = 2 - }; - - #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 986c78f592a..ce72acb9ee0 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -35,6 +35,7 @@ - (R_GOT 20) ;; GOT ptr reg - (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline - (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline -+ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline - (UNSPEC_SET_GOT 101) ;; - (UNSPEC_GOTOFF 102) ;; GOT offset - (UNSPEC_PLT 103) ;; jump table -@@ -82,7 +83,7 @@ - ;; bshift Shift operations - - (define_attr "type" -- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap" -+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap" - (const_string "unknown")) - - ;; Main data type used by the insn -@@ -224,6 +225,80 @@ - ;;----------------------------------------------------------------- - - -+ -+;;---------------------------------------------------------------- -+;; Microblaze 8-stage pipeline description (v10.0 and later) -+;;---------------------------------------------------------------- -+ -+(define_automaton "mbpipe_8") -+(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8") -+ -+(define_insn_reservation "mb8-integer" 1 -+ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu,mb8_wb") -+ -+(define_insn_reservation "mb8-special-move" 2 -+ (and (eq_attr "type" "move") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu*2,mb8_wb") -+ -+(define_insn_reservation "mb8-mem-load" 3 -+ (and (eq_attr "type" "load,no_delay_load") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu,mb8_wb") -+ -+(define_insn_reservation "mb8-mem-store" 1 -+ (and (eq_attr "type" "store,no_delay_store") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_iu,mb8_wb") -+ -+(define_insn_reservation "mb8-mul" 3 -+ (and (eq_attr "type" "imul,no_delay_imul") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb") -+ -+(define_insn_reservation "mb8-div" 30 -+ (and (eq_attr "type" "idiv") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb") -+ -+(define_insn_reservation "mb8-bs" 2 -+ (and (eq_attr "type" "bshift") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-add-sub-mul" 1 -+ (and (eq_attr "type" "fadd,frsub,fmul") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-fcmp" 3 -+ (and (eq_attr "type" "fcmp") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-div" 24 -+ (and (eq_attr "type" "fdiv") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-sqrt" 23 -+ (and (eq_attr "type" "fsqrt") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-fcvt" 1 -+ (and (eq_attr "type" "fcvt") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_wb") -+ -+(define_insn_reservation "mb8-fpu-fint" 2 -+ (and (eq_attr "type" "fint") -+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) -+ "mb8_issue,mb8_fpu,mb8_wb") -+ -+ - ;;---------------------------------------------------------------- - ;; Microblaze 5-stage pipeline description (v5.00.a and later) - ;;---------------------------------------------------------------- -@@ -470,7 +545,7 @@ - (fix:SI (match_operand:SF 1 "register_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "fint\t%0,%1" -- [(set_attr "type" "fcvt") -+ [(set_attr "type" "fint") - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt -index 8dfb134b315..2a72566372b 100644 ---- a/gcc/config/microblaze/microblaze.opt -+++ b/gcc/config/microblaze/microblaze.opt -@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE). - - mxl-mode-xilkernel - Target -+ -+mxl-frequency -+Target Mask(AREA_OPTIMIZED_2) -+Use 8 stage pipeline (frequency optimization) --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch deleted file mode 100644 index 4ef976b7..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 1c93b2ce88766f74f1f6d7e0235ffff0b7ca7b81 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 9 Nov 2020 21:14:54 +0530 -Subject: [PATCH 21/53] [Patch, microblaze]: Correct the const high double - immediate value with this patch the loading of the DI mode immediate values - will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE - functions, as CONST_DOUBLE_HIGH was returning the sign extension value even - of the unsigned long long constants also - -Signed-off-by :Nagaraju Mekala - Ajit Agarwal ---- - gcc/config/microblaze/microblaze.c | 6 ++++-- - gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++ - 2 files changed, 13 insertions(+), 2 deletions(-) - create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index c730faa9814..3b1e992fa28 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2452,14 +2452,16 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -+ long l[2]; - if (code == CONST_DOUBLE) - { - if (GET_MODE (op) == DFmode) - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); - else - { -- val[0] = CONST_DOUBLE_HIGH (op); -- val[1] = CONST_DOUBLE_LOW (op); -+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); -+ val[1] = l[WORDS_BIG_ENDIAN == 0]; -+ val[0] = l[WORDS_BIG_ENDIAN != 0]; - } - } - else if (code == CONST_INT) -diff --git a/gcc/testsuite/gcc.target/microblaze/others/long.c b/gcc/testsuite/gcc.target/microblaze/others/long.c -new file mode 100644 -index 00000000000..b6b55d5ad65 ---- /dev/null -+++ b/gcc/testsuite/gcc.target/microblaze/others/long.c -@@ -0,0 +1,9 @@ -+#define BASEADDR 0xF0000000ULL -+int main () -+{ -+ unsigned long long start; -+ start = (unsigned long long) BASEADDR; -+ return 0; -+} -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch deleted file mode 100644 index 58c4a146..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 808c5fecf0eab33e4cb66fb5170b9bf114dbc320 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 18 Jan 2017 11:49:58 +0530 -Subject: [PATCH 22/53] [Fix, microblaze]: Fix internal compiler error with - msmall-divides This patch will fix the internal error - microblaze_expand_divide function which comes because of rtx PLUS where the - mem_rtx is of type SI and the operand is of type QImode. This patch modifies - the mem_rtx as QImode and Plus as QImode to fix the error. - -Signed-off-by :Nagaraju Mekala - Ajit Agarwal -ChangeLog: - 2016-02-23 Nagaraju Mekala - Ajit Agarwal - - *microblaze.c (microblaze_expand_divide): Update ---- - gcc/config/microblaze/microblaze.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 3b1e992fa28..94aaeaa3a67 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3767,7 +3767,7 @@ microblaze_expand_divide (rtx operands[]) - emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); - emit_insn (gen_addsi3 (regt1, regt1, operands[2])); - mem_rtx = gen_rtx_MEM (QImode, -- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); -+ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - - insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch deleted file mode 100644 index 62f8f5e5..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch +++ /dev/null @@ -1,45 +0,0 @@ -From e6f5b2ba1c03ac3d0521291beb64d64a125e1481 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 18 Jan 2017 12:03:39 +0530 -Subject: [PATCH 23/53] [patch,microblaze]: Fix the calculation of high word in - a long long 6. .4-bit - -This patch will change the calculation of high word in a long long 64-bit. -Earlier to this patch the high word of long long word (0xF0000000ULL) is -coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word -should be 0x00000000 and the low word should be 0xF0000000. This patch -removes the condition of checking high word = 0 & low word < 0. -This check is not required for the correctness of calculating 32-bit high -and low words in a 64-bit long long. - -Signed-off-by :Nagaraju Mekala - Ajit Agarwal - -ChangeLog: -2016-03-01 Nagaraju Mekala - Ajit Agarwal - - *config/microblaze/microblaze.c (print_operand): Remove the condition of checking - high word = 0 & low word < 0. - *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option. ---- - gcc/config/microblaze/microblaze.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 94aaeaa3a67..84e17fc4520 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2468,9 +2468,6 @@ print_operand (FILE * file, rtx op, int letter) - { - val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; - val[1] = INTVAL (op) & 0x00000000ffffffffLL; -- if (val[0] == 0 && val[1] < 0) -- val[0] = -1; -- - } - fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); - } --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-MicroBlaze-this-patch-has.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-MicroBlaze-this-patch-has.patch deleted file mode 100644 index c5c9f416..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-MicroBlaze-this-patch-has.patch +++ /dev/null @@ -1,372 +0,0 @@ -From 5b81fec66287856abfe7def27e245fe73e60fe5e Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 26 Oct 2021 21:11:21 +0530 -Subject: [PATCH 24/53] [Patch,MicroBlaze] : this patch has 1.Fixed the bug in - version calculation. 2.Add new bitfield instructions. - ---- - gcc/config/microblaze/microblaze.c | 154 ++++++++++++++-------------- - gcc/config/microblaze/microblaze.h | 2 + - gcc/config/microblaze/microblaze.md | 69 +++++++++++++ - 3 files changed, 147 insertions(+), 78 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 84e17fc4520..9f94d015597 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay; - /* Set to one if the targeted core has the CLZ insn. */ - int microblaze_has_clz = 0; - -+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */ -+int microblaze_has_bitfield = 0; -+ - /* Which CPU pipeline do we use. We haven't really standardized on a CPU - version having only a particular type of pipeline. There can still be - options on the CPU to scale pipeline features up or down. :( -@@ -239,6 +242,63 @@ section *sdata2_section; - #define TARGET_HAVE_TLS true - #endif - -+/* Convert a version number of the form "vX.YY.Z" to an integer encoding -+ for easier range comparison. */ -+static int -+microblaze_version_to_int (const char *version) -+{ -+ const char *p, *v; -+ const char *tmpl = "vXX.YY.Z"; -+ int iver1 =0, iver2 =0, iver3 =0; -+ -+ p = version; -+ v = tmpl; -+ -+ while (*p) -+ { -+ if (*v == 'X') -+ { /* Looking for major */ -+ if (*p == '.') -+ { -+ *v++; -+ } -+ else -+ { -+ if (!(*p >= '0' && *p <= '9')) -+ return -1; -+ iver1 += (int) (*p - '0'); -+ iver1 *= 1000; -+ } -+ } -+ else if (*v == 'Y') -+ { /* Looking for minor */ -+ if (!(*p >= '0' && *p <= '9')) -+ return -1; -+ iver2 += (int) (*p - '0'); -+ iver2 *= 10; -+ } -+ else if (*v == 'Z') -+ { /* Looking for compat */ -+ if (!(*p >= 'a' && *p <= 'z')) -+ return -1; -+ iver3 = ((int) (*p)) - 96; -+ } -+ else -+ { -+ if (*p != *v) -+ return -1; -+ } -+ -+ v++; -+ p++; -+ } -+ -+ if (*p) -+ return -1; -+ -+ return iver1 + iver2 + iver3; -+} -+ - /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ - static bool - microblaze_const_double_ok (rtx op, machine_mode mode) -@@ -1338,8 +1398,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, - { - if (TARGET_BARREL_SHIFT) - { -- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") -- >= 0) -+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) - *total = COSTS_N_INSNS (1); - else - *total = COSTS_N_INSNS (2); -@@ -1400,8 +1459,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, - } - else if (!TARGET_SOFT_MUL) - { -- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") -- >= 0) -+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) - *total = COSTS_N_INSNS (1); - else - *total = COSTS_N_INSNS (3); -@@ -1674,72 +1732,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, - return 0; - } - --/* Convert a version number of the form "vX.YY.Z" to an integer encoding -- for easier range comparison. */ --static int --microblaze_version_to_int (const char *version) --{ -- const char *p, *v; -- const char *tmpl = "vXX.YY.Z"; -- int iver = 0; -- -- p = version; -- v = tmpl; -- -- while (*p) -- { -- if (*v == 'X') -- { /* Looking for major */ -- if (*p == '.') -- { -- v++; -- } -- else -- { -- if (!(*p >= '0' && *p <= '9')) -- return -1; -- iver += (int) (*p - '0'); -- iver *= 10; -- } -- } -- else if (*v == 'Y') -- { /* Looking for minor */ -- if (!(*p >= '0' && *p <= '9')) -- return -1; -- iver += (int) (*p - '0'); -- iver *= 10; -- } -- else if (*v == 'Z') -- { /* Looking for compat */ -- if (!(*p >= 'a' && *p <= 'z')) -- return -1; -- iver *= 10; -- iver += (int) (*p - 'a'); -- } -- else -- { -- if (*p != *v) -- return -1; -- } -- -- v++; -- p++; -- } -- -- if (*p) -- return -1; -- -- return iver; --} -- -- - static void - microblaze_option_override (void) - { - register int i, start; - register int regno; - register machine_mode mode; -- int ver; -+ int ver,ver_int; - - microblaze_section_threshold = (global_options_set.x_g_switch_value - ? g_switch_value -@@ -1760,13 +1759,13 @@ microblaze_option_override (void) - /* Check the MicroBlaze CPU version for any special action to be done. */ - if (microblaze_select_cpu == NULL) - microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; -- ver = microblaze_version_to_int (microblaze_select_cpu); -- if (ver == -1) -+ ver_int = microblaze_version_to_int (microblaze_select_cpu); -+ if (ver_int == -1) - { - error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu); - } - -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a"); -+ ver = ver_int - microblaze_version_to_int("v3.00.a"); - if (ver < 0) - { - /* No hardware exceptions in earlier versions. So no worries. */ -@@ -1777,8 +1776,7 @@ microblaze_option_override (void) - microblaze_pipe = MICROBLAZE_PIPE_3; - } - else if (ver == 0 -- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b") -- == 0)) -+ || (ver_int == microblaze_version_to_int("v4.00.b"))) - { - #if 0 - microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); -@@ -1795,11 +1793,9 @@ microblaze_option_override (void) - #endif - microblaze_no_unsafe_delay = 0; - microblaze_pipe = MICROBLAZE_PIPE_5; -- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0 -- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, -- "v5.00.b") == 0 -- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, -- "v5.00.c") == 0) -+ if ((ver_int == microblaze_version_to_int("v5.00.a")) -+ || (ver_int == microblaze_version_to_int("v5.00.b")) -+ || (ver_int == microblaze_version_to_int("v5.00.c"))) - { - /* Pattern compares are to be turned on by default only when - compiling for MB v5.00.'z'. */ -@@ -1807,7 +1803,7 @@ microblaze_option_override (void) - } - } - -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a"); -+ ver = ver_int - microblaze_version_to_int("v6.00.a"); - if (ver < 0) - { - if (TARGET_MULTIPLY_HIGH) -@@ -1816,7 +1812,7 @@ microblaze_option_override (void) - "%<-mcpu=v6.00.a%> or greater"); - } - -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a"); -+ ver = ver_int - microblaze_version_to_int("v8.10.a"); - microblaze_has_clz = 1; - if (ver < 0) - { -@@ -1825,7 +1821,7 @@ microblaze_option_override (void) - } - - /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ -- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a"); -+ ver = ver_int - microblaze_version_to_int("v8.30.a"); - if (ver < 0) - { - if (TARGET_REORDER == 1) -@@ -1840,7 +1836,7 @@ microblaze_option_override (void) - "%<-mcpu=v8.30.a%>"); - TARGET_REORDER = 0; - } -- ver = microblaze_version_to_int("v10.0"); -+ ver = ver_int - microblaze_version_to_int("v10.0"); - if (ver < 0) - { - if (TARGET_AREA_OPTIMIZED_2) -@@ -1850,6 +1846,8 @@ microblaze_option_override (void) - { - if (TARGET_AREA_OPTIMIZED_2) - microblaze_pipe = MICROBLAZE_PIPE_8; -+ if (TARGET_BARREL_SHIFT) -+ microblaze_has_bitfield = 1; - } - - if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 21560ec1618..6aac8a6cc2a 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; - - extern int microblaze_no_unsafe_delay; - extern int microblaze_has_clz; -+extern int microblaze_has_bitfield; - extern enum pipeline_type microblaze_pipe; - - #define OBJECT_FORMAT_ELF -@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe; - /* Do we have CLZ? */ - #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz) - -+#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield) - /* The default is to support PIC. */ - #define TARGET_SUPPORTS_PIC 1 - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index ce72acb9ee0..fc3326b2314 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2489,4 +2489,73 @@ - DONE; - }") - -+(define_expand "extvsi" -+ [(set (match_operand:SI 0 "register_operand" "r") -+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "I") -+ (match_operand:SI 3 "immediate_operand" "I")))] -+"TARGET_HAS_BITFIELD" -+" -+{ -+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); -+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); -+ -+ if ((len == 0) || (pos + len > 32) ) -+ FAIL; -+ -+ ;;if (!register_operand (operands[1], VOIDmode)) -+ ;; FAIL; -+ if (operands[0] == operands[1]) -+ FAIL; -+ if (GET_CODE (operands[1]) == ASHIFT) -+ FAIL; -+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); -+ emit_insn (gen_extv_32 (operands[0], operands[1], -+ operands[2], operands[3])); -+ DONE; -+}") -+ -+(define_insn "extv_32" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") -+ (match_operand:SI 2 "immediate_operand" "I") -+ (match_operand:SI 3 "immediate_operand" "I")))] -+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0) -+ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" -+ "bsefi %0,%1,%2,%3" -+ [(set_attr "type" "bshift") -+ (set_attr "length" "4")]) -+ -+(define_expand "insvsi" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (match_operand:SI 1 "immediate_operand" "I") -+ (match_operand:SI 2 "immediate_operand" "I")) -+ (match_operand:SI 3 "register_operand" "r"))] -+ "TARGET_HAS_BITFIELD" -+ " -+{ -+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); -+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); -+ -+ if (len <= 0 || pos + len > 32) -+ FAIL; -+ -+ ;;if (!register_operand (operands[0], VOIDmode)) -+ ;; FAIL; -+ emit_insn (gen_insv_32 (operands[0], operands[1], -+ operands[2], operands[3])); -+ DONE; -+}") -+ -+(define_insn "insv_32" -+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -+ (match_operand:SI 1 "immediate_operand" "I") -+ (match_operand:SI 2 "immediate_operand" "I")) -+ (match_operand:SI 3 "register_operand" "r"))] -+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0 -+ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" -+ "bsifi %0, %3, %1, %2" -+ [(set_attr "type" "bshift") -+ (set_attr "length" "4")]) -+ - (include "sync.md") --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0025-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0025-Fixing-the-issue-with-the-builtin_alloc.patch deleted file mode 100644 index f8c438c2..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0025-Fixing-the-issue-with-the-builtin_alloc.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 18f970e2dd79c67cefeeaa6634f959be19d1a6ad Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Thu, 23 Feb 2017 17:09:04 +0530 -Subject: [PATCH 25/53] Fixing the issue with the builtin_alloc. register r18 - was not properly handling the stack pattern which was resolved by using free - available register - -signed-off-by:nagaraju mekala ---- - gcc/config/microblaze/microblaze.md | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index fc3326b2314..0b3dbdd4a70 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2075,10 +2075,10 @@ - "" - { - rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); -- rtx rtmp = gen_rtx_REG (SImode, R_TMP); -+ rtx reg = gen_reg_rtx (Pmode); - rtx neg_op0; - -- emit_move_insn (rtmp, retaddr); -+ emit_move_insn (reg, retaddr); - if (GET_CODE (operands[1]) != CONST_INT) - { - neg_op0 = gen_reg_rtx (Pmode); -@@ -2087,9 +2087,9 @@ - neg_op0 = GEN_INT (- INTVAL (operands[1])); - - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); -- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp); -+ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg); - emit_move_insn (operands[0], virtual_stack_dynamic_rtx); -- emit_insn (gen_rtx_CLOBBER (SImode, rtmp)); -+ emit_insn (gen_rtx_CLOBBER (SImode, reg)); - DONE; - } - ) --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch deleted file mode 100644 index e895ddbd..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 45f4d3915c2194183a87ca54bd9ecf68eeccba4d Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 4 Jun 2018 10:10:18 +0530 -Subject: [PATCH 26/53] [Patch,Microblaze] : Removed fsqrt generation for - double values. - ---- - gcc/config/microblaze/microblaze.md | 14 -------------- - 1 file changed, 14 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 0b3dbdd4a70..9dd12d1011b 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -526,20 +526,6 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - --(define_insn "sqrtdf2" -- [(set (match_operand:DF 0 "register_operand" "=d") -- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] -- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" -- { -- if (REGNO (operands[0]) == REGNO (operands[1])) -- return "fsqrt\t%0,%1"; -- else -- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; -- } -- [(set_attr "type" "fsqrt") -- (set_attr "mode" "SF") -- (set_attr "length" "4")]) -- - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch deleted file mode 100644 index 140332aa..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch +++ /dev/null @@ -1,784 +0,0 @@ -From dba8e9e148812774d94f584cdff7b6e0293081b5 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 10 Nov 2020 12:52:54 +0530 -Subject: [PATCH 27/53] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze - -Conflicts: - gcc/config/microblaze/microblaze.md ---- - gcc/config/microblaze/constraints.md | 6 + - gcc/config/microblaze/microblaze-protos.h | 1 + - gcc/config/microblaze/microblaze.c | 109 +++++-- - gcc/config/microblaze/microblaze.h | 4 +- - gcc/config/microblaze/microblaze.md | 352 +++++++++++++++++++++- - gcc/config/microblaze/microblaze.opt | 7 +- - gcc/config/microblaze/t-microblaze | 7 +- - 7 files changed, 456 insertions(+), 30 deletions(-) - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index b4d7ee329b8..95b21d58f88 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -52,6 +52,12 @@ - (and (match_code "const_int") - (match_test "ival > 0 && ival < 0x10000"))) - -+(define_constraint "K" -+ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." -+ (and (match_code "const_int") -+ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) -+ -+ - ;; Define floating point constraints - - (define_constraint "G" -diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index 3a5f439703c..302f6bbda2e 100644 ---- a/gcc/config/microblaze/microblaze-protos.h -+++ b/gcc/config/microblaze/microblaze-protos.h -@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *); - extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); - extern void microblaze_expand_conditional_branch_sf (rtx *); -+extern void microblaze_expand_conditional_branch_df (rtx *); - extern int microblaze_can_use_return_insn (void); - extern void print_operand (FILE *, rtx, int); - extern void print_operand_address (FILE *, rtx); -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 9f94d015597..58d7397945e 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3432,11 +3432,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) - op0 = operands[0]; - op1 = operands[1]; - -- if (!register_operand (op0, SImode) -- && !register_operand (op1, SImode) -+ if (!register_operand (op0, mode) -+ && !register_operand (op1, mode) - && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0)) - { -- rtx temp = force_reg (SImode, op1); -+ rtx temp = force_reg (mode, op1); - emit_move_insn (op0, temp); - return true; - } -@@ -3501,12 +3501,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) - && (flag_pic == 2 || microblaze_tls_symbol_p (p0) - || !SMALL_INT (p1))))) - { -- rtx temp = force_reg (SImode, p0); -+ rtx temp = force_reg (mode, p0); - rtx temp2 = p1; - - if (flag_pic && reload_in_progress) - df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); -- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2)); -+ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2)); - return true; - } - } -@@ -3637,7 +3637,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - rtx cmp_op0 = operands[1]; - rtx cmp_op1 = operands[2]; - rtx label1 = operands[3]; -- rtx comp_reg = gen_reg_rtx (SImode); -+ rtx comp_reg = gen_reg_rtx (mode); - rtx condition; - - gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); -@@ -3646,23 +3646,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - if (cmp_op1 == const0_rtx) - { - comp_reg = cmp_op0; -- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); -+ - } - - else if (code == EQ || code == NE) - { - /* Use xor for equal/not-equal comparison. */ -- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); -- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ if (mode == SImode) -+ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); -+ else -+ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); -+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); - } - else - { - /* Generate compare and branch in single instruction. */ - cmp_op1 = force_reg (mode, cmp_op1); - condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); -- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); -+ if (mode == SImode) -+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); -+ else -+ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1)); - } - } - -@@ -3673,7 +3686,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - rtx cmp_op0 = operands[1]; - rtx cmp_op1 = operands[2]; - rtx label1 = operands[3]; -- rtx comp_reg = gen_reg_rtx (SImode); -+ rtx comp_reg = gen_reg_rtx (mode); - rtx condition; - - gcc_assert ((GET_CODE (cmp_op0) == REG) -@@ -3684,30 +3697,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - { - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), -- SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); - } - else if (code == EQ) - { -- emit_insn (gen_seq_internal_pat (comp_reg, -- cmp_op0, cmp_op1)); -- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ if (mode == SImode) -+ { -+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ else -+ { -+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); -+ - } - else if (code == NE) - { -- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, -- cmp_op1)); -- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, label1)); -+ if (mode == SImode) -+ { -+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ else -+ { -+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, -+ cmp_op1)); -+ } -+ condition = gen_rtx_NE (mode, comp_reg, const0_rtx); -+ if (mode == SImode) -+ emit_jump_insn (gen_condjump (condition, label1)); -+ else -+ emit_jump_insn (gen_long_condjump (condition, label1)); - } - else - { - /* Generate compare and branch in single instruction. */ - cmp_op1 = force_reg (mode, cmp_op1); - condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); -- emit_jump_insn (gen_branch_compare (condition, cmp_op0, -- cmp_op1, label1)); -+ if (mode == SImode) -+ emit_jump_insn (gen_branch_compare (condition, cmp_op0, -+ cmp_op1, label1)); -+ else -+ { -+ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0, -+ cmp_op1, label1)); -+ } -+ - } - } - -@@ -3724,6 +3770,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) - emit_jump_insn (gen_condjump (condition, operands[3])); - } - -+void -+microblaze_expand_conditional_branch_df (rtx operands[]) -+{ -+ rtx condition; -+ rtx cmp_op0 = XEXP (operands[0], 0); -+ rtx cmp_op1 = XEXP (operands[0], 1); -+ rtx comp_reg = gen_reg_rtx (DImode); -+ -+ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); -+ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); -+ emit_jump_insn (gen_long_condjump (condition, operands[3])); -+} -+ - /* Implement TARGET_FRAME_POINTER_REQUIRED. */ - - static bool -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 6aac8a6cc2a..22fc3509319 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; - #define ASM_SPEC "\ - %(target_asm_spec) \ - %{mbig-endian:-EB} \ -+%{m64:-m64} \ - %{mlittle-endian:-EL}" - - /* Extra switches sometimes passed to the linker. */ -@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe; - #define LINK_SPEC "%{shared:-shared} -N -relax \ - %{mbig-endian:-EB --oformat=elf32-microblaze} \ - %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ -+ %{m64:-EL --oformat=elf64-microblazeel} \ - %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ - %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ - %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ -@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe; - #define MIN_UNITS_PER_WORD 4 - #define INT_TYPE_SIZE 32 - #define SHORT_TYPE_SIZE 16 --#define LONG_TYPE_SIZE 32 -+#define LONG_TYPE_SIZE 64 - #define LONG_LONG_TYPE_SIZE 64 - #define FLOAT_TYPE_SIZE 32 - #define DOUBLE_TYPE_SIZE 64 -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 9dd12d1011b..3834725eec1 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -497,7 +497,6 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -- - (define_insn "divsf3" - [(set (match_operand:SF 0 "register_operand" "=d") - (div:SF (match_operand:SF 1 "register_operand" "d") -@@ -508,6 +507,7 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+ - (define_insn "sqrtsf2" - [(set (match_operand:SF 0 "register_operand" "=d") - (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] -@@ -562,6 +562,18 @@ - - ;; Adding 2 DI operands in register or reg/imm - -+(define_insn "adddi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") -+ (match_operand:DI 2 "arith_plus_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ addlk\t%0,%z1,%2 -+ addlik\t%0,%z1,%2" -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "adddi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (match_operand:DI 1 "register_operand" "%d,d") -@@ -606,6 +618,18 @@ - ;; Double Precision Subtraction - ;;---------------------------------------------------------------- - -+(define_insn "subdi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (minus:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "register_operand" "d,n")))] -+ "TARGET_MB_64" -+ "@ -+ rsubl\t%0,%2,%1 -+ addlik\t%0,%z1,-%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "d") -@@ -795,6 +819,15 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "negdi2_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (neg:DI (match_operand:DI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "rsubl\t%0,%1,r0" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "negdi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d")))] -@@ -814,6 +847,15 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "one_cmpldi2_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (not:DI (match_operand:DI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "xorli\t%0,%1,-1" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "*one_cmpldi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (not:DI (match_operand:DI 1 "register_operand" "d")))] -@@ -840,6 +882,20 @@ - ;; Logical - ;;---------------------------------------------------------------- - -+(define_insn "anddi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (and:DI (match_operand:DI 1 "arith_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ andl\t%0,%1,%2 -+ andli\t%0,%1,%2 #andl1" -+ ;; andli\t%0,%1,%2 #andl3 -+ ;; andli\t%0,%1,%2 #andl2 -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "andsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") - (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") -@@ -855,6 +911,18 @@ - (set_attr "length" "4,8,8,8")]) - - -+(define_insn "iordi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (ior:DI (match_operand:DI 1 "arith_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ orl\t%0,%1,%2 -+ orli\t%0,%1,%2 #andl1" -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ - (define_insn "iorsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") - (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") -@@ -869,6 +937,19 @@ - (set_attr "mode" "SI,SI,SI,SI") - (set_attr "length" "4,8,8,8")]) - -+(define_insn "xordi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") -+ (match_operand:DI 2 "arith_operand" "d,K")))] -+ "TARGET_MB_64" -+ "@ -+ xorl\t%0,%1,%2 -+ xorli\t%0,%1,%2 #andl1" -+ [(set_attr "type" "arith,arith") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")]) -+ -+ - (define_insn "xorsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d") - (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") -@@ -937,6 +1018,26 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+;;(define_expand "extendqidi2" -+;; [(set (match_operand:DI 0 "register_operand" "=d") -+;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] -+;; "TARGET_MB_64" -+;; { -+;; if (GET_CODE (operands[1]) != REG) -+;; FAIL; -+;; } -+;;) -+ -+ -+;;(define_insn "extendqidi2" -+;; [(set (match_operand:DI 0 "register_operand" "=d") -+;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] -+;; "TARGET_MB_64" -+;; "sextl8\t%0,%1" -+;; [(set_attr "type" "arith") -+;; (set_attr "mode" "DI") -+;; (set_attr "length" "4")]) -+ - (define_insn "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] -@@ -946,6 +1047,16 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "sextl16\t%0,%1" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ -+ - ;; Those for integer source operand are ordered - ;; widest source type first. - -@@ -1009,6 +1120,32 @@ - ) - - -+(define_insn "*movdi_internal_64" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") -+ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] -+ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1"; -+ case 1: -+ return "addlik\t%0,r0,%1"; -+ case 2: -+ return "addlk\t%0,r0,r0"; -+ case 3: -+ case 4: -+ return "lli\t%0,%1"; -+ case 5: -+ case 6: -+ return "sli\t%1,%0"; -+ } -+ return "unreachable"; -+ } -+ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8,8,8,8,12,8,12")]) -+ - - (define_insn "*movdi_internal" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") -@@ -1421,6 +1558,36 @@ - (set_attr "length" "4,4")] - ) - -+;; Barrel shift left -+(define_expand "ashldi3" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "")))] -+"TARGET_MB_64" -+{ -+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+ { -+ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else -+ FAIL; -+} -+) -+ -+(define_insn "ashldi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "I,d")))] -+ "TARGET_MB_64" -+ "@ -+ bsllli\t%0,%1,%2 -+ bslll\t%0,%1,%2" -+ [(set_attr "type" "bshift,bshift") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")] -+) - ;; The following patterns apply when there is no barrel shifter present - - (define_insn "*ashlsi3_with_mul_delay" -@@ -1546,6 +1713,36 @@ - ;;---------------------------------------------------------------- - ;; 32-bit right shifts - ;;---------------------------------------------------------------- -+;; Barrel shift left -+(define_expand "ashrdi3" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "")))] -+"TARGET_MB_64" -+{ -+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+ { -+ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else -+ FAIL; -+} -+) -+ -+(define_insn "ashrdi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "I,d")))] -+ "TARGET_MB_64" -+ "@ -+ bslrai\t%0,%1,%2 -+ bslra\t%0,%1,%2" -+ [(set_attr "type" "bshift,bshift") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")] -+ ) - (define_expand "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -@@ -1655,6 +1852,36 @@ - ;;---------------------------------------------------------------- - ;; 32-bit right shifts (logical) - ;;---------------------------------------------------------------- -+;; Barrel shift left -+(define_expand "lshrdi3" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "")))] -+"TARGET_MB_64" -+{ -+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+ { -+ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else -+ FAIL; -+} -+) -+ -+(define_insn "lshrdi3_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") -+ (match_operand:DI 2 "arith_operand" "I,d")))] -+ "TARGET_MB_64" -+ "@ -+ bslrli\t%0,%1,%2 -+ bslrl\t%0,%1,%2" -+ [(set_attr "type" "bshift,bshift") -+ (set_attr "mode" "DI,DI") -+ (set_attr "length" "4,4")] -+ ) - - (define_expand "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") -@@ -1800,6 +2027,8 @@ - (set_attr "length" "4")] - ) - -+ -+ - ;;---------------------------------------------------------------- - ;; Setting a register from an floating point comparison. - ;;---------------------------------------------------------------- -@@ -1815,6 +2044,18 @@ - (set_attr "length" "4")] - ) - -+(define_insn "cstoredf4" -+ [(set (match_operand:DI 0 "register_operand" "=r") -+ (match_operator:DI 1 "ordered_comparison_operator" -+ [(match_operand:DF 2 "register_operand" "r") -+ (match_operand:DF 3 "register_operand" "r")]))] -+ "TARGET_MB_64" -+ "dcmp.%C1\t%0,%3,%2" -+ [(set_attr "type" "fcmp") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")] -+) -+ - ;;---------------------------------------------------------------- - ;; Conditional branches - ;;---------------------------------------------------------------- -@@ -1927,6 +2168,115 @@ - (set_attr "length" "12")] - ) - -+ -+(define_expand "cbranchdi4" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand") -+ (match_operand:DI 2 "arith_operand" "I,i")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "TARGET_MB_64" -+{ -+ microblaze_expand_conditional_branch (DImode, operands); -+ DONE; -+}) -+ -+(define_expand "cbranchdi4_reg" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand") -+ (match_operand:DI 2 "register_operand")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "TARGET_MB_64" -+{ -+ microblaze_expand_conditional_branch_reg (DImode, operands); -+ DONE; -+}) -+ -+(define_expand "cbranchdf4" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand:DF 1 "register_operand") -+ (match_operand:DF 2 "register_operand")]) -+ (label_ref (match_operand 3 "")) -+ (pc)))] -+ "TARGET_MB_64" -+{ -+ microblaze_expand_conditional_branch_df (operands); -+ DONE; -+ -+}) -+ -+;; Used to implement comparison instructions -+(define_expand "long_condjump" -+ [(set (pc) -+ (if_then_else (match_operand 0) -+ (label_ref (match_operand 1)) -+ (pc)))]) -+ -+(define_insn "long_branch_zero" -+ [(set (pc) -+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand" "d") -+ (const_int 0)]) -+ (match_operand:DI 2 "pc_or_label_operand" "") -+ (match_operand:DI 3 "pc_or_label_operand" ""))) -+ ] -+ "TARGET_MB_64" -+ { -+ if (operands[3] == pc_rtx) -+ return "beal%C0i%?\t%z1,%2"; -+ else -+ return "beal%N0i%?\t%z1,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "long_branch_compare" -+ [(set (pc) -+ (if_then_else (match_operator:DI 0 "cmp_op" -+ [(match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d") -+ ]) -+ (label_ref (match_operand 3)) -+ (pc))) -+ (clobber(reg:DI R_TMP))] -+ "TARGET_MB_64" -+ { -+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ enum rtx_code code = GET_CODE (operands[0]); -+ -+ if (code == GT || code == LE) -+ { -+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GTU || code == LEU) -+ { -+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GE || code == LT) -+ { -+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); -+ } -+ else if (code == GEU || code == LTU) -+ { -+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); -+ } -+ -+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); -+ return "beal%C0i%?\tr18,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "12")] -+) -+ - ;;---------------------------------------------------------------- - ;; Unconditional branches - ;;---------------------------------------------------------------- -diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt -index 2a72566372b..206899c0384 100644 ---- a/gcc/config/microblaze/microblaze.opt -+++ b/gcc/config/microblaze/microblaze.opt -@@ -136,4 +136,9 @@ Target - - mxl-frequency - Target Mask(AREA_OPTIMIZED_2) --Use 8 stage pipeline (frequency optimization) -+Use 8 stage pipeline (frequency optimization). -+ -+m64 -+Target Mask(MB_64) -+MicroBlaze 64-bit mode. -+ -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index 41fa9a92081..e9a1921ae26 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -1,8 +1,11 @@ --MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian --MULTILIB_DIRNAMES = bs m mh le -+MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 -+MULTILIB_DIRNAMES = bs m mh le m64 - MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 - MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian -+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 -+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 - - # Extra files - microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0028-Intial-commit-for-64bit-MB-sources.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0028-Intial-commit-for-64bit-MB-sources.patch deleted file mode 100644 index 9d38091e..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0028-Intial-commit-for-64bit-MB-sources.patch +++ /dev/null @@ -1,2451 +0,0 @@ -From 211cfd6be4b47e1fecf95d1becb713772fd71091 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Fri, 27 Jul 2018 15:23:41 +0530 -Subject: [PATCH 28/53] Intial commit for 64bit-MB sources. Need to cleanup the - code later. - ---- - gcc/config/microblaze/constraints.md | 2 +- - gcc/config/microblaze/microblaze-c.c | 6 + - gcc/config/microblaze/microblaze.c | 218 ++++++--- - gcc/config/microblaze/microblaze.h | 63 ++- - gcc/config/microblaze/microblaze.md | 605 ++++++++++++++++++------ - gcc/config/microblaze/t-microblaze | 3 +- - libgcc/config/microblaze/crti.S | 4 +- - libgcc/config/microblaze/crtn.S | 4 +- - libgcc/config/microblaze/divdi3.S | 98 ++++ - libgcc/config/microblaze/divdi3_table.c | 62 +++ - libgcc/config/microblaze/moddi3.S | 97 ++++ - libgcc/config/microblaze/muldi3.S | 73 +++ - libgcc/config/microblaze/t-microblaze | 11 +- - libgcc/config/microblaze/udivdi3.S | 107 +++++ - libgcc/config/microblaze/umoddi3.S | 110 +++++ - 15 files changed, 1230 insertions(+), 233 deletions(-) - create mode 100644 libgcc/config/microblaze/divdi3.S - create mode 100644 libgcc/config/microblaze/divdi3_table.c - create mode 100644 libgcc/config/microblaze/moddi3.S - create mode 100644 libgcc/config/microblaze/muldi3.S - create mode 100644 libgcc/config/microblaze/udivdi3.S - create mode 100644 libgcc/config/microblaze/umoddi3.S - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index 95b21d58f88..0a4d5269314 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -55,7 +55,7 @@ - (define_constraint "K" - "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." - (and (match_code "const_int") -- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) -+ (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) - - - ;; Define floating point constraints -diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c -index e0b29bcb0b0..2dcb879992c 100644 ---- a/gcc/config/microblaze/microblaze-c.c -+++ b/gcc/config/microblaze/microblaze-c.c -@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) - builtin_define ("HAVE_HW_FPU_SQRT"); - builtin_define ("__HAVE_HW_FPU_SQRT__"); - } -+ if (TARGET_MB_64) -+ { -+ builtin_define ("__arch64__"); -+ builtin_define ("__microblaze64__"); -+ builtin_define ("__MICROBLAZE64__"); -+ } - } -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 58d7397945e..f59a71ac072 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) - { - return 1; - } -- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) -+ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) - { - return 1; -- } -+ }*/ - else - return 0; - -@@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode) - return 1; - - return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT -- ? E_SImode : E_SFmode), -+ ? Pmode : E_SFmode), - plus_constant (Pmode, addr, 4)); - } - -@@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) - /* Load the addend. */ - addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), - UNSPEC_TLS); -- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); -+ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend)); - dest = gen_rtx_PLUS (Pmode, dest, addend); - break; - -@@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) - - if (XINT (x, 1) == UNSPEC_GOTOFF) - { -- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM); -+ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); - info->type = ADDRESS_GOTOFF; - } - else if (XINT (x, 1) == UNSPEC_PLT) -@@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) - emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); - - /* Emit the test & branch. */ -- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src), -+ -+ if (TARGET_MB_64) { -+ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src), -+ src_reg, final_src, label)); -+ } -+ else { -+ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src), - src_reg, final_src, label)); -+ -+ } - - /* Mop up any left-over bytes. */ - if (leftover) -@@ -1633,14 +1641,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, - break; - - case E_DFmode: -- cum->arg_words += 2; -+ if (TARGET_MB_64) -+ cum->arg_words++; -+ else -+ cum->arg_words += 2; - if (!cum->gp_reg_found && cum->arg_number <= 2) - cum->fp_code += 2 << ((cum->arg_number - 1) * 2); - break; - - case E_DImode: - cum->gp_reg_found = 1; -- cum->arg_words += 2; -+ if (TARGET_MB_64) -+ cum->arg_words++; -+ else -+ cum->arg_words += 2; - break; - - case E_QImode: -@@ -2155,7 +2169,7 @@ compute_frame_size (HOST_WIDE_INT size) - - if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) - /* Don't account for link register. It is accounted specially below. */ -- gp_reg_size += GET_MODE_SIZE (SImode); -+ gp_reg_size += GET_MODE_SIZE (Pmode); - - mask |= (1L << (regno - GP_REG_FIRST)); - } -@@ -2424,7 +2438,7 @@ print_operand (FILE * file, rtx op, int letter) - - if ((letter == 'M' && !WORDS_BIG_ENDIAN) - || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') -- regnum++; -+ regnum++; - - fprintf (file, "%s", reg_names[regnum]); - } -@@ -2450,6 +2464,7 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -+ int val1[2]; - long l[2]; - if (code == CONST_DOUBLE) - { -@@ -2462,12 +2477,12 @@ print_operand (FILE * file, rtx op, int letter) - val[0] = l[WORDS_BIG_ENDIAN != 0]; - } - } -- else if (code == CONST_INT) -+ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) - { -- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -- val[1] = INTVAL (op) & 0x00000000ffffffffLL; -+ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -+ val1[1] = INTVAL (op) & 0x00000000ffffffffLL; - } -- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); -+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); - } - else if (code == CONST_DOUBLE) - { -@@ -2661,7 +2676,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) - - switch_to_section (get_section (section, 0, NULL)); - assemble_align (POINTER_SIZE); -- fputs ("\t.word\t", asm_out_file); -+ if (TARGET_MB_64) -+ fputs ("\t.dword\t", asm_out_file); -+ else -+ fputs ("\t.word\t", asm_out_file); - output_addr_const (asm_out_file, symbol); - fputs ("\n", asm_out_file); - } -@@ -2684,7 +2702,10 @@ microblaze_asm_destructor (rtx symbol, int priority) - - switch_to_section (get_section (section, 0, NULL)); - assemble_align (POINTER_SIZE); -- fputs ("\t.word\t", asm_out_file); -+ if (TARGET_MB_64) -+ fputs ("\t.dword\t", asm_out_file); -+ else -+ fputs ("\t.word\t", asm_out_file); - output_addr_const (asm_out_file, symbol); - fputs ("\n", asm_out_file); - } -@@ -2750,7 +2771,7 @@ save_restore_insns (int prologue) - /* For interrupt_handlers, need to save/restore the MSR. */ - if (microblaze_is_interrupt_variant ()) - { -- isr_mem_rtx = gen_rtx_MEM (SImode, -+ isr_mem_rtx = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, base_reg_rtx, - GEN_INT (current_frame_info. - gp_offset - -@@ -2758,8 +2779,8 @@ save_restore_insns (int prologue) - - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (isr_mem_rtx) = 1; -- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG); -- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG); -+ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG); -+ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG); - } - - if (microblaze_is_interrupt_variant () && !prologue) -@@ -2767,8 +2788,8 @@ save_restore_insns (int prologue) - emit_move_insn (isr_reg_rtx, isr_mem_rtx); - emit_move_insn (isr_msr_rtx, isr_reg_rtx); - /* Do not optimize in flow analysis. */ -- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); -- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); - } - - for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) -@@ -2779,9 +2800,9 @@ save_restore_insns (int prologue) - /* Don't handle here. Already handled as the first register. */ - continue; - -- reg_rtx = gen_rtx_REG (SImode, regno); -+ reg_rtx = gen_rtx_REG (Pmode, regno); - insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset)); -- mem_rtx = gen_rtx_MEM (SImode, insn); -+ mem_rtx = gen_rtx_MEM (Pmode, insn); - if (microblaze_is_interrupt_variant () || save_volatiles) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; -@@ -2796,7 +2817,7 @@ save_restore_insns (int prologue) - insn = emit_move_insn (reg_rtx, mem_rtx); - } - -- gp_offset += GET_MODE_SIZE (SImode); -+ gp_offset += GET_MODE_SIZE (Pmode); - } - } - -@@ -2806,8 +2827,8 @@ save_restore_insns (int prologue) - emit_move_insn (isr_mem_rtx, isr_reg_rtx); - - /* Do not optimize in flow analysis. */ -- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); -- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); -+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); - } - - /* Done saving and restoring */ -@@ -2897,7 +2918,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) - - switch_to_section (s); - assemble_align (POINTER_SIZE); -- fputs ("\t.word\t", asm_out_file); -+ if (TARGET_MB_64) -+ fputs ("\t.dword\t", asm_out_file); -+ else -+ fputs ("\t.word\t", asm_out_file); - output_addr_const (asm_out_file, symbol); - fputs ("\n", asm_out_file); - } -@@ -3041,10 +3065,10 @@ microblaze_expand_prologue (void) - { - if (offset != 0) - ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); -- emit_move_insn (gen_rtx_MEM (SImode, ptr), -- gen_rtx_REG (SImode, regno)); -+ emit_move_insn (gen_rtx_MEM (Pmode, ptr), -+ gen_rtx_REG (Pmode, regno)); - -- offset += GET_MODE_SIZE (SImode); -+ offset += GET_MODE_SIZE (Pmode); - } - } - -@@ -3053,15 +3077,23 @@ microblaze_expand_prologue (void) - rtx fsiz_rtx = GEN_INT (fsiz); - - rtx_insn *insn = NULL; -- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ if (TARGET_MB_64) -+ { -+ -+ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, - fsiz_rtx)); -+ } -+ else { -+ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, -+ fsiz_rtx)); -+ } - if (insn) - RTX_FRAME_RELATED_P (insn) = 1; - - /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */ - if (!crtl->is_leaf || interrupt_handler) - { -- mem_rtx = gen_rtx_MEM (SImode, -+ mem_rtx = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, stack_pointer_rtx, - const0_rtx)); - -@@ -3069,7 +3101,7 @@ microblaze_expand_prologue (void) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; - -- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); - insn = emit_move_insn (mem_rtx, reg_rtx); - RTX_FRAME_RELATED_P (insn) = 1; - } -@@ -3179,12 +3211,12 @@ microblaze_expand_epilogue (void) - if (!crtl->is_leaf || interrupt_handler) - { - mem_rtx = -- gen_rtx_MEM (SImode, -+ gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); - if (interrupt_handler) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; -- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); - emit_move_insn (reg_rtx, mem_rtx); - } - -@@ -3200,15 +3232,25 @@ microblaze_expand_epilogue (void) - /* _restore_ registers for epilogue. */ - save_restore_insns (0); - emit_insn (gen_blockage ()); -- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); -+ if (TARGET_MB_64) -+ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); -+ else -+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); - } - - if (crtl->calls_eh_return) -- emit_insn (gen_addsi3 (stack_pointer_rtx, -+ if (TARGET_MB_64) { -+ emit_insn (gen_adddi3 (stack_pointer_rtx, - stack_pointer_rtx, -- gen_raw_REG (SImode, -+ gen_raw_REG (Pmode, - MB_EH_STACKADJ_REGNUM))); -- -+ } -+ else { -+ emit_insn (gen_addsi3 (stack_pointer_rtx, -+ stack_pointer_rtx, -+ gen_raw_REG (Pmode, -+ MB_EH_STACKADJ_REGNUM))); -+ } - emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + - MB_ABI_SUB_RETURN_ADDR_REGNUM))); - } -@@ -3375,9 +3417,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, - else - this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); - -- /* Apply the constant offset, if required. */ -+ /* Apply the constant offset, if required. */ - if (delta) -- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); -+ { -+ if (TARGET_MB_64) -+ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); -+ else -+ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); -+ } - - /* Apply the offset from the vtable, if required. */ - if (vcall_offset) -@@ -3390,7 +3437,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, - rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); - emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); - -- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); -+ if (TARGET_MB_64) -+ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1)); -+ else -+ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); - } - - /* Generate a tail call to the target function. */ -@@ -3566,7 +3616,7 @@ microblaze_eh_return (rtx op0) - /* Queue an .ident string in the queue of top-level asm statements. - If the string size is below the threshold, put it into .sdata2. - If the front-end is done, we must be being called from toplev.c. -- In that case, do nothing. */ -+ In that case, do nothing. */ - void - microblaze_asm_output_ident (const char *string) - { -@@ -3621,9 +3671,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) - emit_block_move (m_tramp, assemble_trampoline_template (), - GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); - -- mem = adjust_address (m_tramp, SImode, 16); -+ mem = adjust_address (m_tramp, Pmode, 16); - emit_move_insn (mem, chain_value); -- mem = adjust_address (m_tramp, SImode, 20); -+ mem = adjust_address (m_tramp, Pmode, 20); - emit_move_insn (mem, fnaddr); - } - -@@ -3647,7 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - { - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -- if (mode == SImode) -+ if (mode == Pmode) - emit_jump_insn (gen_condjump (condition, label1)); - else - emit_jump_insn (gen_long_condjump (condition, label1)); -@@ -3766,7 +3816,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) - rtx comp_reg = gen_reg_rtx (SImode); - - emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); -- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); - emit_jump_insn (gen_condjump (condition, operands[3])); - } - -@@ -3776,10 +3826,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) - rtx condition; - rtx cmp_op0 = XEXP (operands[0], 0); - rtx cmp_op1 = XEXP (operands[0], 1); -- rtx comp_reg = gen_reg_rtx (DImode); -+ rtx comp_reg = gen_reg_rtx (Pmode); - - emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); -- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); -+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); - emit_jump_insn (gen_long_condjump (condition, operands[3])); - } - -@@ -3800,8 +3850,8 @@ microblaze_expand_divide (rtx operands[]) - { - /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ - -- rtx regt1 = gen_reg_rtx (SImode); -- rtx reg18 = gen_rtx_REG (SImode, R_TMP); -+ rtx regt1 = gen_reg_rtx (Pmode); -+ rtx reg18 = gen_rtx_REG (Pmode, R_TMP); - rtx regqi = gen_reg_rtx (QImode); - rtx_code_label *div_label = gen_label_rtx (); - rtx_code_label *div_end_label = gen_label_rtx (); -@@ -3809,17 +3859,31 @@ microblaze_expand_divide (rtx operands[]) - rtx mem_rtx; - rtx ret; - rtx_insn *jump, *cjump, *insn; -- -- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); -- cjump = emit_jump_insn_after (gen_cbranchsi4 ( -- gen_rtx_GTU (SImode, regt1, GEN_INT (15)), -+ -+ if (TARGET_MB_64) { -+ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2])); -+ cjump = emit_jump_insn_after (gen_cbranchdi4 ( -+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), -+ regt1, GEN_INT (15), div_label), insn); -+ } -+ else { -+ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); -+ cjump = emit_jump_insn_after (gen_cbranchsi4 ( -+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), - regt1, GEN_INT (15), div_label), insn); -+ } - LABEL_NUSES (div_label) = 1; - JUMP_LABEL (cjump) = div_label; -- emit_insn (gen_rtx_CLOBBER (SImode, reg18)); -+ emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); - -- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); -- emit_insn (gen_addsi3 (regt1, regt1, operands[2])); -+ if (TARGET_MB_64) { -+ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); -+ emit_insn (gen_adddi3 (regt1, regt1, operands[2])); -+ } -+ else { -+ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); -+ emit_insn (gen_addsi3 (regt1, regt1, operands[2])); -+ } - mem_rtx = gen_rtx_MEM (QImode, - gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - -@@ -3966,7 +4030,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) - { - insn = - emit_insn_before (gen_iprefetch -- (gen_int_mode (addr_offset, SImode)), -+ (gen_int_mode (addr_offset, Pmode)), - before_4); - recog_memoized (insn); - INSN_LOCATION (insn) = INSN_LOCATION (before_4); -@@ -3976,7 +4040,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) - } - } - } -- -+ -+/* Set the names for various arithmetic operations according to the -+ * MICROBLAZE ABI. */ -+static void -+microblaze_init_libfuncs (void) -+{ -+ set_optab_libfunc (smod_optab, SImode, "__modsi3"); -+ set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); -+ set_optab_libfunc (smul_optab, SImode, "__mulsi3"); -+ set_optab_libfunc (umod_optab, SImode, "__umodsi3"); -+ set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); -+ -+ if (TARGET_MB_64) -+ { -+ set_optab_libfunc (smod_optab, DImode, "__moddi3"); -+ set_optab_libfunc (sdiv_optab, DImode, "__divdi3"); -+ set_optab_libfunc (smul_optab, DImode, "__muldi3"); -+ set_optab_libfunc (umod_optab, DImode, "__umoddi3"); -+ set_optab_libfunc (udiv_optab, DImode, "__udivdi3"); -+ } -+} - /* Insert instruction prefetch instruction at the fall - through path of the function call. */ - -@@ -4129,6 +4213,17 @@ microblaze_starting_frame_offset (void) - #undef TARGET_LRA_P - #define TARGET_LRA_P hook_bool_void_false - -+#ifdef TARGET_MB_64 -+#undef TARGET_ASM_ALIGNED_DI_OP -+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" -+ -+#undef TARGET_ASM_ALIGNED_HI_OP -+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" -+ -+#undef TARGET_ASM_ALIGNED_SI_OP -+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" -+#endif -+ - #undef TARGET_FRAME_POINTER_REQUIRED - #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required - -@@ -4138,6 +4233,9 @@ microblaze_starting_frame_offset (void) - #undef TARGET_TRAMPOLINE_INIT - #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init - -+#undef TARGET_INIT_LIBFUNCS -+#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs -+ - #undef TARGET_PROMOTE_FUNCTION_MODE - #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 22fc3509319..94ac736221c 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; - - /* Generate DWARF exception handling info. */ - #define DWARF2_UNWIND_INFO 1 -- - /* Don't generate .loc operations. */ - #define DWARF2_ASM_LINE_DEBUG_INFO 0 - -@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe; - ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr) - - /* Use DWARF 2 debugging information by default. */ --#define DWARF2_DEBUGGING_INFO -+#define DWARF2_DEBUGGING_INFO 1 - #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -+#define DWARF2_ADDR_SIZE 4 - - /* Target machine storage layout */ - - #define BITS_BIG_ENDIAN 0 - #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) - #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) --#define BITS_PER_WORD 32 --#define UNITS_PER_WORD 4 -+//#define BITS_PER_WORD 64 -+//Revisit -+#define MAX_BITS_PER_WORD 64 -+#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) -+//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) -+//#define UNITS_PER_WORD 4 - #define MIN_UNITS_PER_WORD 4 - #define INT_TYPE_SIZE 32 - #define SHORT_TYPE_SIZE 16 --#define LONG_TYPE_SIZE 64 -+#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32) - #define LONG_LONG_TYPE_SIZE 64 - #define FLOAT_TYPE_SIZE 32 - #define DOUBLE_TYPE_SIZE 64 - #define LONG_DOUBLE_TYPE_SIZE 64 --#define POINTER_SIZE 32 --#define PARM_BOUNDARY 32 --#define FUNCTION_BOUNDARY 32 --#define EMPTY_FIELD_BOUNDARY 32 -+#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32) -+//#define WIDEST_HARDWARE_FP_SIZE 64 -+//#define POINTERS_EXTEND_UNSIGNED 1 -+#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32) -+#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32) -+#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32) - #define STRUCTURE_SIZE_BOUNDARY 8 --#define BIGGEST_ALIGNMENT 32 -+#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32) - #define STRICT_ALIGNMENT 1 - #define PCC_BITFIELD_TYPE_MATTERS 1 - -+//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode) - #undef SIZE_TYPE --#define SIZE_TYPE "unsigned int" -+#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") - - #undef PTRDIFF_TYPE --#define PTRDIFF_TYPE "int" -+#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int") -+ -+/*#undef INTPTR_TYPE -+#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/ -+#undef UINTPTR_TYPE -+#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") - - #define DATA_ALIGNMENT(TYPE, ALIGN) \ - ((((ALIGN) < BITS_PER_WORD) \ -@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe; - #define WORD_REGISTER_OPERATIONS 1 - - #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND -- -+/* - #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ - if (GET_MODE_CLASS (MODE) == MODE_INT \ -- && GET_MODE_SIZE (MODE) < 4) \ -- (MODE) = SImode; -- -+ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ -+ (MODE) = TARGET_MB_64 ? DImode : SImode; -+*/ - /* Standard register usage. */ - - /* On the MicroBlaze, we have 32 integer registers */ -@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info; - #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) - - #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 -+#define DWARF_CIE_DATA_ALIGNMENT -1 - - #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - - #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 - --#define STACK_BOUNDARY 32 -+#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) - -+#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) -+ - #define NUM_OF_ARGS 6 - - #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) -@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info; - #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS - - #define LIBCALL_VALUE(MODE) \ -+ gen_rtx_REG (MODE,GP_RETURN) -+ -+/*#define LIBCALL_VALUE(MODE) \ - gen_rtx_REG ( \ - ((GET_MODE_CLASS (MODE) != MODE_INT \ - || GET_MODE_SIZE (MODE) >= 4) \ - ? (MODE) \ - : SImode), GP_RETURN) -- -+*/ - /* 1 if N is a possible register number for a function value. - On the MicroBlaze, R2 R3 are the only register thus used. - Currently, R2 are only implemented here (C has no complex type) */ -@@ -500,7 +518,7 @@ typedef struct microblaze_args - /* 4 insns + 2 words of data. */ - #define TRAMPOLINE_SIZE (6 * 4) - --#define TRAMPOLINE_ALIGNMENT 32 -+#define TRAMPOLINE_ALIGNMENT 64 - - #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) - -@@ -529,13 +547,13 @@ typedef struct microblaze_args - addresses which require two reload registers. */ - #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) - --#define CASE_VECTOR_MODE (SImode) -+#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode) - - #ifndef DEFAULT_SIGNED_CHAR - #define DEFAULT_SIGNED_CHAR 1 - #endif - --#define MOVE_MAX 4 -+#define MOVE_MAX (TARGET_MB_64 ? 8 : 4) - #define MAX_MOVE_MAX 8 - - #define SLOW_BYTE_ACCESS 1 -@@ -545,7 +563,7 @@ typedef struct microblaze_args - - #define SHIFT_COUNT_TRUNCATED 1 - --#define Pmode SImode -+#define Pmode (TARGET_MB_64? DImode:SImode) - - #define FUNCTION_MODE SImode - -@@ -707,6 +725,7 @@ do { \ - - #undef TARGET_ASM_OUTPUT_IDENT - #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident -+//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive - - /* Default to -G 8 */ - #ifndef MICROBLAZE_DEFAULT_GVALUE -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 3834725eec1..7bc91602ca2 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -26,6 +26,7 @@ - ;; Constants - ;;---------------------------------------------------- - (define_constants [ -+ (R_Z 0) ;; For reg r0 - (R_SP 1) ;; Stack pointer reg - (R_SR 15) ;; Sub-routine return addr reg - (R_IR 14) ;; Interrupt return addr reg -@@ -541,6 +542,7 @@ - - ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] - ;; Leave carry as is -+ - (define_insn "addsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d") - (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") -@@ -562,23 +564,38 @@ - - ;; Adding 2 DI operands in register or reg/imm - --(define_insn "adddi3_long" -+(define_expand "adddi3" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (plus:DI (match_operand:DI 1 "register_operand" "") -+ (match_operand:DI 2 "arith_plus_operand" "")))] -+"" -+{ -+ if (TARGET_MB_64) -+ { -+ if (GET_CODE (operands[2]) == CONST_INT && -+ INTVAL(operands[2]) < (long)-549755813888 && -+ INTVAL(operands[2]) > (long)549755813887) -+ FAIL; -+ } -+}) -+ -+(define_insn "*adddi3_long" - [(set (match_operand:DI 0 "register_operand" "=d,d") -- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") -+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") - (match_operand:DI 2 "arith_plus_operand" "d,K")))] - "TARGET_MB_64" - "@ -- addlk\t%0,%z1,%2 -- addlik\t%0,%z1,%2" -- [(set_attr "type" "arith,arith") -- (set_attr "mode" "DI,DI") -+ addlk\t%0,%1,%2 -+ addlik\t%0,%1,%2 #N10" -+ [(set_attr "type" "darith,no_delay_arith") -+ (set_attr "mode" "DI") - (set_attr "length" "4,4")]) - --(define_insn "adddi3" -+(define_insn "*adddi3_all" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (match_operand:DI 1 "register_operand" "%d,d") - (match_operand:DI 2 "arith_operand" "d,i")))] -- "" -+ "!TARGET_MB_64" - "@ - add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 - addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" -@@ -605,7 +622,7 @@ - (define_insn "iprefetch" - [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) - (clobber (mem:BLK (scratch)))] -- "TARGET_PREFETCH" -+ "TARGET_PREFETCH && !TARGET_MB_64" - { - operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); - return "mfs\t%2,rpc\n\twic\t%2,r0"; -@@ -618,23 +635,33 @@ - ;; Double Precision Subtraction - ;;---------------------------------------------------------------- - --(define_insn "subdi3_long" -- [(set (match_operand:DI 0 "register_operand" "=d,d") -- (minus:DI (match_operand:DI 1 "register_operand" "d,d") -- (match_operand:DI 2 "register_operand" "d,n")))] -+(define_expand "subdi3" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (minus:DI (match_operand:DI 1 "register_operand" "") -+ (match_operand:DI 2 "arith_operand" "")))] -+"" -+" -+{ -+}") -+ -+(define_insn "subsidi3" -+ [(set (match_operand:DI 0 "register_operand" "=d,d,d") -+ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") -+ (match_operand:DI 2 "arith_operand" "d,K,n")))] - "TARGET_MB_64" - "@ - rsubl\t%0,%2,%1 -- addlik\t%0,%z1,-%2" -- [(set_attr "type" "darith") -- (set_attr "mode" "DI,DI") -- (set_attr "length" "4,4")]) -+ addik\t%0,%z1,-%2 -+ addik\t%0,%z1,-%2" -+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4,4,4")]) - --(define_insn "subdi3" -+(define_insn "subdi3_small" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] -- "" -+ "!TARGET_MB_64" - "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" - [(set_attr "type" "darith") - (set_attr "mode" "DI") -@@ -663,7 +690,7 @@ - (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] -- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" -+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" - "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -674,7 +701,7 @@ - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] -- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" -+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" - "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -685,7 +712,7 @@ - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] -- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" -+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" - "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -789,7 +816,7 @@ - (match_operand:SI 4 "arith_operand")]) - (label_ref (match_operand 5)) - (pc)))] -- "TARGET_HARD_FLOAT" -+ "TARGET_HARD_FLOAT && !TARGET_MB_64" - [(set (match_dup 1) (match_dup 3))] - - { -@@ -819,6 +846,15 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - -+(define_insn "negsi_long" -+ [(set (match_operand:SI 0 "register_operand" "=d") -+ (neg:SI (match_operand:DI 1 "register_operand" "d")))] -+ "" -+ "rsubk\t%0,%1,r0" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "4")]) -+ - (define_insn "negdi2_long" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d")))] -@@ -847,16 +883,24 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - --(define_insn "one_cmpldi2_long" -+(define_expand "one_cmpldi2" -+ [(set (match_operand:DI 0 "register_operand" "") -+ (not:DI (match_operand:DI 1 "register_operand" "")))] -+ "" -+ " -+{ -+}") -+ -+(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=d") -- (not:DI (match_operand:DI 1 "register_operand" "d")))] -+ (not:DI (match_operand:DI 1 "arith_operand" "d")))] - "TARGET_MB_64" - "xorli\t%0,%1,-1" -- [(set_attr "type" "arith") -+ [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") - (set_attr "length" "4")]) - --(define_insn "*one_cmpldi2" -+(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=d") - (not:DI (match_operand:DI 1 "register_operand" "d")))] - "" -@@ -871,7 +915,8 @@ - (not:DI (match_operand:DI 1 "register_operand" "")))] - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) -- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" -+ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -+ && !TARGET_MB_64" - - [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) - (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] -@@ -883,18 +928,17 @@ - ;;---------------------------------------------------------------- - - (define_insn "anddi3" -- [(set (match_operand:DI 0 "register_operand" "=d,d") -- (and:DI (match_operand:DI 1 "arith_operand" "d,d") -- (match_operand:DI 2 "arith_operand" "d,K")))] -+ [(set (match_operand:DI 0 "register_operand" "=d,d,d") -+ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") -+ (match_operand:DI 2 "arith_operand" "d,K,I")))] - "TARGET_MB_64" - "@ - andl\t%0,%1,%2 -- andli\t%0,%1,%2 #andl1" -- ;; andli\t%0,%1,%2 #andl3 -- ;; andli\t%0,%1,%2 #andl2 -- [(set_attr "type" "arith,arith") -- (set_attr "mode" "DI,DI") -- (set_attr "length" "4,4")]) -+ andli\t%0,%1,%2 #andl2 -+ andli\t%0,%1,%2 #andl3" -+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") -+ (set_attr "mode" "DI,DI,DI") -+ (set_attr "length" "4,4,4")]) - - (define_insn "andsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") -@@ -919,7 +963,7 @@ - "@ - orl\t%0,%1,%2 - orli\t%0,%1,%2 #andl1" -- [(set_attr "type" "arith,arith") -+ [(set_attr "type" "arith,no_delay_arith") - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")]) - -@@ -945,7 +989,7 @@ - "@ - xorl\t%0,%1,%2 - xorli\t%0,%1,%2 #andl1" -- [(set_attr "type" "arith,arith") -+ [(set_attr "type" "arith,no_delay_arith") - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")]) - -@@ -1018,26 +1062,6 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - --;;(define_expand "extendqidi2" --;; [(set (match_operand:DI 0 "register_operand" "=d") --;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] --;; "TARGET_MB_64" --;; { --;; if (GET_CODE (operands[1]) != REG) --;; FAIL; --;; } --;;) -- -- --;;(define_insn "extendqidi2" --;; [(set (match_operand:DI 0 "register_operand" "=d") --;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] --;; "TARGET_MB_64" --;; "sextl8\t%0,%1" --;; [(set_attr "type" "arith") --;; (set_attr "mode" "DI") --;; (set_attr "length" "4")]) -- - (define_insn "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] -@@ -1060,6 +1084,27 @@ - ;; Those for integer source operand are ordered - ;; widest source type first. - -+(define_insn "extendsidi2_long" -+ [(set (match_operand:DI 0 "register_operand" "=d,d,d") -+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] -+ "TARGET_MB_64" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "sextl32\t%0,%1"; -+ case 1: -+ case 2: -+ { -+ output_asm_insn ("ll%i1\t%0,%1", operands); -+ return "sextl32\t%0,%0"; -+ } -+ } -+ } -+ [(set_attr "type" "multi,multi,multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4,8,8")]) -+ - (define_insn "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] -@@ -1088,69 +1133,118 @@ - ;; Unlike most other insns, the move insns can't be split with - ;; different predicates, because register spilling and other parts of - ;; the compiler, have memoized the insn number already. -+;; //} - - (define_expand "movdi" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "" - { -- /* If operands[1] is a constant address illegal for pic, then we need to -- handle it just like microblaze_legitimize_address does. */ -- if (flag_pic && pic_address_needs_scratch (operands[1])) -+ if (TARGET_MB_64) -+ { -+ if (microblaze_expand_move (DImode, operands)) DONE; -+ } -+ else - { -+ /* If operands[1] is a constant address illegal for pic, then we need to -+ handle it just like microblaze_legitimize_address does. */ -+ if (flag_pic && pic_address_needs_scratch (operands[1])) -+ { - rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); - rtx temp2 = XEXP (XEXP (operands[1], 0), 1); - emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2)); - DONE; -- } -- -- -- if ((reload_in_progress | reload_completed) == 0 -- && !register_operand (operands[0], DImode) -- && !register_operand (operands[1], DImode) -- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) -- && operands[1] != CONST0_RTX (DImode)))) -- { -+ } - -- rtx temp = force_reg (DImode, operands[1]); -- emit_move_insn (operands[0], temp); -- DONE; -+ if ((reload_in_progress | reload_completed) == 0 -+ && !register_operand (operands[0], DImode) -+ && !register_operand (operands[1], DImode) -+ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) -+ && operands[1] != CONST0_RTX (DImode)))) -+ { -+ rtx temp = force_reg (DImode, operands[1]); -+ emit_move_insn (operands[0], temp); -+ DONE; -+ } - } - } - ) - -+;; Added for status registers -+(define_insn "movdi_status" -+ [(set (match_operand:DI 0 "register_operand" "=d,d,z") -+ (match_operand:DI 1 "register_operand" "z,d,d"))] -+ "microblaze_is_interrupt_variant () && TARGET_MB_64" -+ "@ -+ mfs\t%0,%1 #mfs -+ addlk\t%0,%1,r0 #add movdi -+ mts\t%0,%1 #mts" -+ [(set_attr "type" "move") -+ (set_attr "mode" "DI") -+ (set_attr "length" "12")]) - --(define_insn "*movdi_internal_64" -- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") -- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] -- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" -+;; This move will be not be moved to delay slot. -+(define_insn "*movdi_internal3" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") -+ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] -+ "TARGET_MB_64 && (register_operand (operands[0], DImode) && -+ (GET_CODE (operands[1]) == CONST_INT && -+ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" -+ "@ -+ addlk\t%0,r0,r0\t -+ addlik\t%0,r0,%1\t #N1 %X1 -+ addlik\t%0,r0,%1\t #N2 %X1" -+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ -+;; This move may be used for PLT label operand -+(define_insn "*movdi_internal5_pltop" -+ [(set (match_operand:DI 0 "register_operand" "=d,d") -+ (match_operand:DI 1 "call_insn_operand" ""))] -+ "TARGET_MB_64 && (register_operand (operands[0], Pmode) && -+ PLT_ADDR_P (operands[1]))" -+ { -+ gcc_unreachable (); -+ } -+ [(set_attr "type" "load") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ -+(define_insn "*movdi_internal2" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") -+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] -+ "TARGET_MB_64" - { - switch (which_alternative) - { - case 0: -- return "addlk\t%0,%1"; -- case 1: -- return "addlik\t%0,r0,%1"; -- case 2: -- return "addlk\t%0,r0,r0"; -- case 3: -- case 4: -- return "lli\t%0,%1"; -- case 5: -- case 6: -- return "sli\t%1,%0"; -- } -- return "unreachable"; -- } -- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ case 2: -+ if (GET_CODE (operands[1]) == CONST_INT && -+ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) -+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ else -+ return "addlik\t%0,r0,%1"; -+ case 3: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 5: -+ case 6: -+ return "sl%i0\t%z1,%0"; -+ } -+ } -+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") - (set_attr "mode" "DI") -- (set_attr "length" "8,8,8,8,12,8,12")]) -+ (set_attr "length" "4,4,12,4,8,4,8")]) -+ - - - (define_insn "*movdi_internal" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") - (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] -- "" -+ "!TARGET_MB_64" - { - switch (which_alternative) - { -@@ -1182,7 +1276,8 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))" -+ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1)) -+ && !(TARGET_MB_64)" - - [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) - (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] -@@ -1194,12 +1289,22 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" -+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) -+ && !(TARGET_MB_64)" - - [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) - (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] - "") - -+(define_insn "movdi_long_int" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") -+ (match_operand:DI 1 "general_operand" "i"))] -+ "" -+ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "12")]) -+ - ;; Unlike most other insns, the move insns can't be split with - ;; different predicates, because register spilling and other parts of - ;; the compiler, have memoized the insn number already. -@@ -1271,6 +1376,8 @@ - (set_attr "length" "4,4,8,4,8,4,8")]) - - -+ -+ - ;; 16-bit Integer moves - - ;; Unlike most other insns, the move insns can't be split with -@@ -1303,8 +1410,8 @@ - "@ - addik\t%0,r0,%1\t# %X1 - addk\t%0,%1,r0 -- lhui\t%0,%1 -- lhui\t%0,%1 -+ lhu%i1\t%0,%1 -+ lhu%i1\t%0,%1 - sh%i0\t%z1,%0 - sh%i0\t%z1,%0" - [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") -@@ -1347,7 +1454,7 @@ - lbu%i1\t%0,%1 - lbu%i1\t%0,%1 - sb%i0\t%z1,%0 -- sbi\t%z1,%0" -+ sb%i0\t%z1,%0" - [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") - (set_attr "mode" "QI") - (set_attr "length" "4,4,8,4,8,4,8")]) -@@ -1420,7 +1527,7 @@ - addik\t%0,r0,%F1 - lw%i1\t%0,%1 - sw%i0\t%z1,%0 -- swi\t%z1,%0" -+ sw%i0\t%z1,%0" - [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") - (set_attr "mode" "SF") - (set_attr "length" "4,4,4,4,4,4,4")]) -@@ -1459,6 +1566,33 @@ - ;; movdf_internal - ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT - ;; -+(define_insn "*movdf_internal_64" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") -+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] -+ "TARGET_MB_64" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ return "addlk\t%0,r0,r0"; -+ case 2: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 3: -+ { -+ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; -+ } -+ case 5: -+ return "sl%i0\t%1,%0"; -+ } -+ gcc_unreachable (); -+ } -+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4,4,4,16,4,4")]) -+ - (define_insn "*movdf_internal" - [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") - (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] -@@ -1493,7 +1627,8 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))" -+ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1)) -+ && !TARGET_MB_64" - [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) - (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] - "") -@@ -1504,7 +1639,8 @@ - "reload_completed - && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) - && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) -- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" -+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) -+ && !TARGET_MB_64" - [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) - (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] - "") -@@ -2003,6 +2139,31 @@ else - " - ) - -+ -+(define_insn "seq_internal_pat_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (eq:DI -+ (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "pcmpleq\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "sne_internal_pat_long" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (ne:DI -+ (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "pcmplne\t%0,%1,%2" -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")] -+) -+ - (define_insn "seq_internal_pat" - [(set (match_operand:SI 0 "register_operand" "=d") - (eq:SI -@@ -2063,8 +2224,8 @@ else - (define_expand "cbranchsi4" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand:SI 1 "register_operand") -- (match_operand:SI 2 "arith_operand" "I,i")]) -+ [(match_operand 1 "register_operand") -+ (match_operand 2 "arith_operand" "I,i")]) - (label_ref (match_operand 3 "")) - (pc)))] - "" -@@ -2076,13 +2237,13 @@ else - (define_expand "cbranchsi4_reg" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand:SI 1 "register_operand") -- (match_operand:SI 2 "register_operand")]) -+ [(match_operand 1 "register_operand") -+ (match_operand 2 "register_operand")]) - (label_ref (match_operand 3 "")) - (pc)))] - "" - { -- microblaze_expand_conditional_branch_reg (SImode, operands); -+ microblaze_expand_conditional_branch_reg (Pmode, operands); - DONE; - }) - -@@ -2107,6 +2268,26 @@ else - (label_ref (match_operand 1)) - (pc)))]) - -+(define_insn "branch_zero64" -+ [(set (pc) -+ (if_then_else (match_operator 0 "ordered_comparison_operator" -+ [(match_operand 1 "register_operand" "d") -+ (const_int 0)]) -+ (match_operand 2 "pc_or_label_operand" "") -+ (match_operand 3 "pc_or_label_operand" ""))) -+ ] -+ "TARGET_MB_64" -+ { -+ if (operands[3] == pc_rtx) -+ return "bea%C0i%?\t%z1,%2"; -+ else -+ return "bea%N0i%?\t%z1,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")] -+) -+ - (define_insn "branch_zero" - [(set (pc) - (if_then_else (match_operator:SI 0 "ordered_comparison_operator" -@@ -2127,6 +2308,47 @@ else - (set_attr "length" "4")] - ) - -+(define_insn "branch_compare64" -+ [(set (pc) -+ (if_then_else (match_operator 0 "cmp_op" -+ [(match_operand 1 "register_operand" "d") -+ (match_operand 2 "register_operand" "d") -+ ]) -+ (label_ref (match_operand 3)) -+ (pc))) -+ (clobber(reg:SI R_TMP))] -+ "TARGET_MB_64" -+ { -+ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+ enum rtx_code code = GET_CODE (operands[0]); -+ -+ if (code == GT || code == LE) -+ { -+ output_asm_insn ("cmp\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GTU || code == LEU) -+ { -+ output_asm_insn ("cmpu\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GE || code == LT) -+ { -+ output_asm_insn ("cmp\tr18,%z2,%z1", operands); -+ } -+ else if (code == GEU || code == LTU) -+ { -+ output_asm_insn ("cmpu\tr18,%z2,%z1", operands); -+ } -+ -+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); -+ return "bea%C0i%?\tr18,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "12")] -+) -+ - (define_insn "branch_compare" - [(set (pc) - (if_then_else (match_operator:SI 0 "cmp_op" -@@ -2310,7 +2532,7 @@ else - ;; Indirect jumps. Jump to register values. Assuming absolute jumps - - (define_insn "indirect_jump_internal1" -- [(set (pc) (match_operand:SI 0 "register_operand" "d"))] -+ [(set (pc) (match_operand 0 "register_operand" "d"))] - "" - "bra%?\t%0" - [(set_attr "type" "jump") -@@ -2323,7 +2545,7 @@ else - (use (label_ref (match_operand 1 "" "")))] - "" - { -- gcc_assert (GET_MODE (operands[0]) == Pmode); -+ //gcc_assert (GET_MODE (operands[0]) == Pmode); - - if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) - emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); -@@ -2335,7 +2557,7 @@ else - - (define_insn "tablejump_internal1" - [(set (pc) -- (match_operand:SI 0 "register_operand" "d")) -+ (match_operand 0 "register_operand" "d")) - (use (label_ref (match_operand 1 "" "")))] - "" - "bra%?\t%0 " -@@ -2345,9 +2567,9 @@ else - - (define_expand "tablejump_internal3" - [(parallel [(set (pc) -- (plus:SI (match_operand:SI 0 "register_operand" "d") -- (label_ref:SI (match_operand:SI 1 "" "")))) -- (use (label_ref:SI (match_dup 1)))])] -+ (plus (match_operand 0 "register_operand" "d") -+ (label_ref (match_operand:SI 1 "" "")))) -+ (use (label_ref (match_dup 1)))])] - "" - "" - ) -@@ -2408,7 +2630,7 @@ else - (minus (reg 1) (match_operand 1 "register_operand" ""))) - (set (reg 1) - (minus (reg 1) (match_dup 1)))] -- "" -+ "!TARGET_MB_64" - { - rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); - rtx reg = gen_reg_rtx (Pmode); -@@ -2433,7 +2655,7 @@ else - (define_expand "save_stack_block" - [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "")] -- "" -+ "!TARGET_MB_64" - { - emit_move_insn (operands[0], operands[1]); - DONE; -@@ -2443,7 +2665,7 @@ else - (define_expand "restore_stack_block" - [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "")] -- "" -+ "!TARGET_MB_64" - { - rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); - rtx rtmp = gen_rtx_REG (SImode, R_TMP); -@@ -2490,7 +2712,7 @@ else - - (define_insn "_internal" - [(any_return) -- (use (match_operand:SI 0 "register_operand" ""))] -+ (use (match_operand 0 "register_operand" ""))] - "" - { - if (microblaze_is_break_handler ()) -@@ -2523,7 +2745,7 @@ else - (define_expand "call" - [(parallel [(call (match_operand 0 "memory_operand" "m") - (match_operand 1 "" "i")) -- (clobber (reg:SI R_SR)) -+ (clobber (reg R_SR)) - (use (match_operand 2 "" "")) - (use (match_operand 3 "" ""))])] - "" -@@ -2544,12 +2766,12 @@ else - - if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) - emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), - pic_offset_table_rtx)); - else - emit_call_insn (gen_call_internal0 (operands[0], operands[1], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); - - DONE; -@@ -2559,7 +2781,7 @@ else - (define_expand "call_internal0" - [(parallel [(call (match_operand 0 "" "") - (match_operand 1 "" "")) -- (clobber (match_operand:SI 2 "" ""))])] -+ (clobber (match_operand 2 "" ""))])] - "" - { - } -@@ -2568,18 +2790,34 @@ else - (define_expand "call_internal_plt0" - [(parallel [(call (match_operand 0 "" "") - (match_operand 1 "" "")) -- (clobber (match_operand:SI 2 "" "")) -- (use (match_operand:SI 3 "" ""))])] -+ (clobber (match_operand 2 "" "")) -+ (use (match_operand 3 "" ""))])] - "" - { - } - ) - -+(define_insn "call_internal_plt_64" -+ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR)) -+ (use (reg R_GOT))] -+ "flag_pic && TARGET_MB_64" -+ { -+ register rtx target2 = gen_rtx_REG (Pmode, -+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ gen_rtx_CLOBBER (VOIDmode, target2); -+ return "brealid\tr15,%0\;%#"; -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_internal_plt" -- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" "")) -- (match_operand:SI 1 "" "i")) -- (clobber (reg:SI R_SR)) -- (use (reg:SI R_GOT))] -+ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR)) -+ (use (reg R_GOT))] - "flag_pic" - { - register rtx target2 = gen_rtx_REG (Pmode, -@@ -2591,10 +2829,41 @@ else - (set_attr "mode" "none") - (set_attr "length" "4")]) - -+(define_insn "call_internal1_64" -+ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR))] -+ "TARGET_MB_64" -+ { -+ register rtx target = operands[0]; -+ register rtx target2 = gen_rtx_REG (Pmode, -+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ if (GET_CODE (target) == SYMBOL_REF) { -+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) { -+ gen_rtx_CLOBBER (VOIDmode, target2); -+ return "breaki\tr16,%0\;%#"; -+ } -+ else { -+ gen_rtx_CLOBBER (VOIDmode, target2); -+ return "brealid\tr15,%0\;%#"; -+ } -+ } else if (GET_CODE (target) == CONST_INT) -+ return "la\t%@,r0,%0\;brald\tr15,%@\;%#"; -+ else if (GET_CODE (target) == REG) -+ return "brald\tr15,%0\;%#"; -+ else { -+ fprintf (stderr,"Unsupported call insn\n"); -+ return NULL; -+ } -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_internal1" - [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) -- (match_operand:SI 1 "" "i")) -- (clobber (reg:SI R_SR))] -+ (match_operand 1 "" "i")) -+ (clobber (reg R_SR))] - "" - { - register rtx target = operands[0]; -@@ -2628,7 +2897,7 @@ else - [(parallel [(set (match_operand 0 "register_operand" "=d") - (call (match_operand 1 "memory_operand" "m") - (match_operand 2 "" "i"))) -- (clobber (reg:SI R_SR)) -+ (clobber (reg R_SR)) - (use (match_operand 3 "" ""))])] ;; next_arg_reg - "" - { -@@ -2649,13 +2918,13 @@ else - if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) - emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], - operands[2], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), - pic_offset_table_rtx)); - else - emit_call_insn (gen_call_value_internal (operands[0], operands[1], - operands[2], -- gen_rtx_REG (SImode, -+ gen_rtx_REG (Pmode, - GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); - - DONE; -@@ -2667,7 +2936,7 @@ else - [(parallel [(set (match_operand 0 "" "") - (call (match_operand 1 "" "") - (match_operand 2 "" ""))) -- (clobber (match_operand:SI 3 "" "")) -+ (clobber (match_operand 3 "" "")) - ])] - "" - {} -@@ -2677,18 +2946,35 @@ else - [(parallel[(set (match_operand 0 "" "") - (call (match_operand 1 "" "") - (match_operand 2 "" ""))) -- (clobber (match_operand:SI 3 "" "")) -- (use (match_operand:SI 4 "" ""))])] -+ (clobber (match_operand 3 "" "")) -+ (use (match_operand 4 "" ""))])] - "flag_pic" - {} - ) - -+(define_insn "call_value_intern_plt_64" -+ [(set (match_operand:VOID 0 "register_operand" "=d") -+ (call (mem (match_operand 1 "call_insn_plt_operand" "")) -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d")) -+ (use (match_operand 4 "register_operand"))] -+ "flag_pic && TARGET_MB_64" -+ { -+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ -+ gen_rtx_CLOBBER (VOIDmode,target2); -+ return "brealid\tr15,%1\;%#"; -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_value_intern_plt" - [(set (match_operand:VOID 0 "register_operand" "=d") -- (call (mem (match_operand:SI 1 "call_insn_plt_operand" "")) -- (match_operand:SI 2 "" "i"))) -- (clobber (match_operand:SI 3 "register_operand" "=d")) -- (use (match_operand:SI 4 "register_operand"))] -+ (call (mem (match_operand 1 "call_insn_plt_operand" "")) -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d")) -+ (use (match_operand 4 "register_operand"))] - "flag_pic" - { - register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -@@ -2700,11 +2986,46 @@ else - (set_attr "mode" "none") - (set_attr "length" "4")]) - -+(define_insn "call_value_intern_64" -+ [(set (match_operand:VOID 0 "register_operand" "=d") -+ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d"))] -+ "TARGET_MB_64" -+ { -+ register rtx target = operands[1]; -+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); -+ -+ if (GET_CODE (target) == SYMBOL_REF) -+ { -+ gen_rtx_CLOBBER (VOIDmode,target2); -+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) -+ return "breaki\tr16,%1\;%#"; -+ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION) -+ { -+ return "brealid\tr15,%1\;%#"; -+ } -+ else -+ { -+ return "bralid\tr15,%1\;%#"; -+ } -+ } -+ else if (GET_CODE (target) == CONST_INT) -+ return "la\t%@,r0,%1\;brald\tr15,%@\;%#"; -+ else if (GET_CODE (target) == REG) -+ return "brald\tr15,%1\;%#"; -+ else -+ return "Unsupported call insn\n"; -+ } -+ [(set_attr "type" "call") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "call_value_intern" - [(set (match_operand:VOID 0 "register_operand" "=d") - (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) -- (match_operand:SI 2 "" "i"))) -- (clobber (match_operand:SI 3 "register_operand" "=d"))] -+ (match_operand 2 "" "i"))) -+ (clobber (match_operand 3 "register_operand" "=d"))] - "" - { - register rtx target = operands[1]; -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index e9a1921ae26..9fc80b142ce 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -2,7 +2,8 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en - MULTILIB_DIRNAMES = bs m mh le m64 - MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high - MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian - MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 - MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 -diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S -index f9bafaf3aa5..bc69d890370 100644 ---- a/libgcc/config/microblaze/crti.S -+++ b/libgcc/config/microblaze/crti.S -@@ -40,7 +40,7 @@ - - .align 2 - __init: -- addik r1, r1, -8 -+ addik r1, r1, -16 - sw r15, r0, r1 - la r11, r0, _stack - mts rshr, r11 -@@ -51,5 +51,5 @@ __init: - .global __fini - .align 2 - __fini: -- addik r1, r1, -8 -+ addik r1, r1, -16 - sw r15, r0, r1 -diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S -index 0260e432371..1a1f0a8e0f3 100644 ---- a/libgcc/config/microblaze/crtn.S -+++ b/libgcc/config/microblaze/crtn.S -@@ -33,9 +33,9 @@ - .section .init, "ax" - lw r15, r0, r1 - rtsd r15, 8 -- addik r1, r1, 8 -+ addik r1, r1, 16 - - .section .fini, "ax" - lw r15, r0, r1 - rtsd r15, 8 -- addik r1, r1, 8 -+ addik r1, r1, 16 -diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S -new file mode 100644 -index 00000000000..d37bf5165c6 ---- /dev/null -+++ b/libgcc/config/microblaze/divdi3.S -@@ -0,0 +1,98 @@ -+###################################- -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# divdi3.S -+# -+# Divide operation for 32 bit integers. -+# Input : Dividend in Reg r5 -+# Divisor in Reg r6 -+# Output: Result in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __divdi3 -+ .ent __divdi3 -+ .type __divdi3,@function -+__divdi3: -+ .frame r1,0,r15 -+ -+ ADDLIK r1,r1,-32 -+ SLI r28,r1,0 -+ SLI r29,r1,8 -+ SLI r30,r1,16 -+ SLI r31,r1,24 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ XORL r28,r5,r6 # Get the sign of the result -+ BEALGEI r5,$LaR5_Pos -+ RSUBLI r5,r5,0 # Make r5 positive -+$LaR5_Pos: -+ BEALGEI r6,$LaR6_Pos -+ RSUBLI r6,r6,0 # Make r6 positive -+$LaR6_Pos: -+ ADDLIK r30,r0,0 # Clear mod -+ ADDLIK r3,r0,0 # clear div -+ ADDLIK r29,r0,64 # Initialize the loop count -+ -+ # First part try to find the first '1' in the r5 -+$LaDIV0: -+ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGTI r5,$LaDIV1 -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r30,r30,r30 # Move that bit into the Mod register -+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) -+ BEALLTI r31,$LaMOD_TOO_SMALL -+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r3,r3,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r3,r3,r3 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BEALGEI r28,$LaRETURN_HERE -+ RSUBLI r3,r3,0 # Negate the result -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ ORL r3,r0,r0 # set result to 0 -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r28,r1,0 -+ LLI r29,r1,8 -+ LLI r30,r1,16 -+ LLI r31,r1,24 -+ ADDLIK r1,r1,32 -+ RTSD r15,8 -+ nop -+.end __divdi3 -+ .size __divdi3, . - __divdi3 -+#endif -diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c -new file mode 100644 -index 00000000000..80962597ea5 ---- /dev/null -+++ b/libgcc/config/microblaze/divdi3_table.c -@@ -0,0 +1,62 @@ -+/* Table for software lookup divide for Xilinx MicroBlaze. -+ -+ Copyright (C) 2009-2017 Free Software Foundation, Inc. -+ -+ Contributed by Michael Eager . -+ -+ This file is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by the -+ Free Software Foundation; either version 3, or (at your option) any -+ later version. -+ -+ GCC is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ Under Section 7 of GPL version 3, you are granted additional -+ permissions described in the GCC Runtime Library Exception, version -+ 3.1, as published by the Free Software Foundation. -+ -+ You should have received a copy of the GNU General Public License and -+ a copy of the GCC Runtime Library Exception along with this program; -+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+ . */ -+ -+ -+unsigned char _divdi3_table[] = -+{ -+ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7, -+ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15, -+ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, -+ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15, -+ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7, -+ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15, -+ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7, -+ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15, -+ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7, -+ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15, -+ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7, -+ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15, -+ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7, -+ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15, -+ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7, -+ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15, -+ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7, -+ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15, -+ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7, -+ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15, -+ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7, -+ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15, -+ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7, -+ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15, -+ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7, -+ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15, -+ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7, -+ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15, -+ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7, -+ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15, -+ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7, -+ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15, -+}; -+ -diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S -new file mode 100644 -index 00000000000..5d3f7c03fc8 ---- /dev/null -+++ b/libgcc/config/microblaze/moddi3.S -@@ -0,0 +1,97 @@ -+################################### -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# moddi3.S -+# -+# modulo operation for 32 bit integers. -+# Input : op1 in Reg r5 -+# op2 in Reg r6 -+# Output: op1 mod op2 in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __moddi3 -+ .ent __moddi3 -+ .type __moddi3,@function -+__moddi3: -+ .frame r1,0,r15 -+ -+ addlik r1,r1,-32 -+ sli r28,r1,0 -+ sli r29,r1,8 -+ sli r30,r1,16 -+ sli r31,r1,32 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] -+ BEALGEI r5,$LaR5_Pos -+ RSUBLI r5,r5,0 # Make r5 positive -+$LaR5_Pos: -+ BEALGEI r6,$LaR6_Pos -+ RSUBLI r6,r6,0 # Make r6 positive -+$LaR6_Pos: -+ ADDLIK r3,r0,0 # Clear mod -+ ADDLIK r30,r0,0 # clear div -+ ADDLIK r29,r0,64 # Initialize the loop count -+ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip -+ # the first bit search. -+ # First part try to find the first '1' in the r5 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGEI r5,$LaDIV1 # -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r3,r3,r3 # Move that bit into the Mod register -+ rSUBL r31,r6,r3 # Try to subtract (r30 a r6) -+ BEALLTi r31,$LaMOD_TOO_SMALL -+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r30,r30,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BEALGEI r28,$LaRETURN_HERE -+ rsubli r3,r3,0 # Negate the result -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0] -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r28,r1,0 -+ lli r29,r1,8 -+ lli r30,r1,16 -+ lli r31,r1,24 -+ addlik r1,r1,32 -+ rtsd r15,8 -+ nop -+ .end __moddi3 -+ .size __moddi3, . - __moddi3 -+#endif -diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S -new file mode 100644 -index 00000000000..567784197d3 ---- /dev/null -+++ b/libgcc/config/microblaze/muldi3.S -@@ -0,0 +1,73 @@ -+/*###################################-*-asm*- -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# muldi3.S -+# -+# Multiply operation for 32 bit integers. -+# Input : Operand1 in Reg r5 -+# Operand2 in Reg r6 -+# Output: Result [op1 * op2] in Reg r3 -+# -+#######################################*/ -+ -+#ifdef __arch64__ -+ .globl __muldi3 -+ .ent __muldi3 -+ .type __muldi3,@function -+__muldi3: -+ .frame r1,0,r15 -+ addl r3,r0,r0 -+ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero -+ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero -+ XORL r4,r5,r6 # Get the sign of the result -+ BEALGEI r5,$L_R5_Pos -+ RSUBLI r5,r5,0 # Make r5 positive -+$L_R5_Pos: -+ BEALGEI r6,$L_R6_Pos -+ RSUBLI r6,r6,0 # Make r6 positive -+$L_R6_Pos: -+ breai $L1 -+$L2: -+ addl r5,r5,r5 -+$L1: -+ srll r6,r6 -+ addlc r7,r0,r0 -+ bealeqi r7,$L2 -+ addl r3,r3,r5 -+ bealnei r6,$L2 -+ beallti r4,$L_NegateResult -+ rtsd r15,8 -+ nop -+$L_NegateResult: -+ rsubl r3,r3,r0 -+ rtsd r15,8 -+ nop -+$L_Result_Is_Zero: -+ addli r3,r0,0 -+ rtsd r15,8 -+ nop -+ .end __muldi3 -+ .size __muldi3, . - __muldi3 -+#endif -diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 8d954a49575..35021b24b7d 100644 ---- a/libgcc/config/microblaze/t-microblaze -+++ b/libgcc/config/microblaze/t-microblaze -@@ -1,11 +1,16 @@ --LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 -+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ -+ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 - - LIB2ADD += \ - $(srcdir)/config/microblaze/divsi3.S \ -+ $(srcdir)/config/microblaze/divdi3.S \ - $(srcdir)/config/microblaze/modsi3.S \ -- $(srcdir)/config/microblaze/muldi3_hard.S \ -+ $(srcdir)/config/microblaze/moddi3.S \ - $(srcdir)/config/microblaze/mulsi3.S \ -+ $(srcdir)/config/microblaze/muldi3.S \ - $(srcdir)/config/microblaze/stack_overflow_exit.S \ - $(srcdir)/config/microblaze/udivsi3.S \ -+ $(srcdir)/config/microblaze/udivdi3.S \ - $(srcdir)/config/microblaze/umodsi3.S \ -- $(srcdir)/config/microblaze/divsi3_table.c -+ $(srcdir)/config/microblaze/umoddi3.S \ -+ $(srcdir)/config/microblaze/divsi3_table.c \ -diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S -new file mode 100644 -index 00000000000..c210fbc7128 ---- /dev/null -+++ b/libgcc/config/microblaze/udivdi3.S -@@ -0,0 +1,107 @@ -+###################################- -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# udivdi3.S -+# -+# Unsigned divide operation. -+# Input : Divisor in Reg r5 -+# Dividend in Reg r6 -+# Output: Result in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __udivdi3 -+ .ent __udivdi3 -+ .type __udivdi3,@function -+__udivdi3: -+ .frame r1,0,r15 -+ -+ ADDlIK r1,r1,-24 -+ SLI r29,r1,0 -+ SLI r30,r1,8 -+ SLI r31,r1,16 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ ADDLIK r30,r0,0 # Clear mod -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ ADDLIK r29,r0,64 # Initialize the loop count -+ -+ # Check if r6 and r5 are equal # if yes, return 1 -+ RSUBL r18,r5,r6 -+ ADDLIK r3,r0,1 -+ BEALEQI r18,$LaRETURN_HERE -+ -+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 -+ XORL r18,r5,r6 -+ ADDL r3,r0,r0 # We would anyways clear r3 -+ BEALGEI r18,$LRSUBL -+ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater -+ BREAI $LCheckr6 -+$LRSUBL: -+ RSUBL r18,r6,r5 # MICROBLAZEcmp -+ BEALLTI r18,$LaRETURN_HERE -+ -+ # If r6 [bit 31] is set, then return result as 1 -+$LCheckr6: -+ BEALGTI r6,$LaDIV0 -+ ADDLIK r3,r0,1 -+ BREAI $LaRETURN_HERE -+ -+ # First part try to find the first '1' in the r5 -+$LaDIV0: -+ BEALLTI r5,$LaDIV2 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGTI r5,$LaDIV1 -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r30,r30,r30 # Move that bit into the Mod register -+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) -+ BEALLTI r31,$LaMOD_TOO_SMALL -+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r3,r3,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r3,r3,r3 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ ORL r3,r0,r0 # set result to 0 -+$LaRETURN_HERE: -+ # Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r29,r1,0 -+ LLI r30,r1,8 -+ LLI r31,r1,16 -+ ADDLIK r1,r1,24 -+ RTSD r15,8 -+ NOP -+ .end __udivdi3 -+ .size __udivdi3, . - __udivdi3 -+#endif -diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S -new file mode 100644 -index 00000000000..7f5cd23f9a1 ---- /dev/null -+++ b/libgcc/config/microblaze/umoddi3.S -@@ -0,0 +1,110 @@ -+################################### -+# -+# Copyright (C) 2009-2017 Free Software Foundation, Inc. -+# -+# Contributed by Michael Eager . -+# -+# This file is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License as published by the -+# Free Software Foundation; either version 3, or (at your option) any -+# later version. -+# -+# GCC is distributed in the hope that it will be useful, but WITHOUT -+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+# License for more details. -+# -+# Under Section 7 of GPL version 3, you are granted additional -+# permissions described in the GCC Runtime Library Exception, version -+# 3.1, as published by the Free Software Foundation. -+# -+# You should have received a copy of the GNU General Public License and -+# a copy of the GCC Runtime Library Exception along with this program; -+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -+# . -+# -+# umoddi3.S -+# -+# Unsigned modulo operation for 32 bit integers. -+# Input : op1 in Reg r5 -+# op2 in Reg r6 -+# Output: op1 mod op2 in Reg r3 -+# -+####################################### -+ -+#ifdef __arch64__ -+ .globl __umoddi3 -+ .ent __umoddi3 -+ .type __umoddi3,@function -+__umoddi3: -+ .frame r1,0,r15 -+ -+ addlik r1,r1,-24 -+ sli r29,r1,0 -+ sli r30,r1,8 -+ sli r31,r1,16 -+ -+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ ADDLIK r3,r0,0 # Clear div -+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero -+ ADDLIK r30,r0,0 # clear mod -+ ADDLIK r29,r0,64 # Initialize the loop count -+ -+# Check if r6 and r5 are equal # if yes, return 0 -+ rsubl r18,r5,r6 -+ bealeqi r18,$LaRETURN_HERE -+ -+# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 -+ xorl r18,r5,r6 -+ addlik r3,r5,0 -+ bealgei r18,$LRSUB -+ beallti r6,$LaRETURN_HERE -+ breai $LCheckr6 -+$LRSUB: -+ rsubl r18,r5,r6 # MICROBLAZEcmp -+ bealgti r18,$LaRETURN_HERE -+ -+# If r6 [bit 31] is set, then return result as r5-r6 -+$LCheckr6: -+ addlik r3,r0,0 -+ bealgti r6,$LaDIV0 -+ addlik r18,r0,0x7fffffff -+ andl r5,r5,r18 -+ andl r6,r6,r18 -+ breaid $LaRETURN_HERE -+ rsubl r3,r6,r5 -+# First part: try to find the first '1' in the r5 -+$LaDIV0: -+ BEALLTI r5,$LaDIV2 -+$LaDIV1: -+ ADDL r5,r5,r5 # left shift logical r5 -+ ADDLIK r29,r29,-1 -+ BEALGEI r5,$LaDIV1 # -+$LaDIV2: -+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDLC r3,r3,r3 # Move that bit into the Mod register -+ rSUBL r31,r6,r3 # Try to subtract (r3 a r6) -+ BEALLTi r31,$LaMOD_TOO_SMALL -+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive -+ ADDLIK r30,r30,1 -+$LaMOD_TOO_SMALL: -+ ADDLIK r29,r29,-1 -+ BEALEQi r29,$LaLOOP_END -+ ADDL r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ orl r3,r0,r0 # set result to 0 -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r29,r1,0 -+ lli r30,r1,8 -+ lli r31,r1,16 -+ addlik r1,r1,24 -+ rtsd r15,8 -+ nop -+.end __umoddi3 -+ .size __umoddi3, . - __umoddi3 -+#endif --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0029-re-arrangement-of-the-compare-branches.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0029-re-arrangement-of-the-compare-branches.patch deleted file mode 100644 index 19605270..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0029-re-arrangement-of-the-compare-branches.patch +++ /dev/null @@ -1,268 +0,0 @@ -From 5b31cd986c75c5f479967b8f9c1b4ac1fc322b1a Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Fri, 3 Aug 2018 15:41:39 +0530 -Subject: [PATCH 29/53] re-arrangement of the compare branches - ---- - gcc/config/microblaze/microblaze.c | 28 ++---- - gcc/config/microblaze/microblaze.md | 141 +++++++++++++--------------- - 2 files changed, 73 insertions(+), 96 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index f59a71ac072..e33e1bc1482 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3697,11 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - { - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -- if (mode == Pmode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -- -+ emit_jump_insn (gen_condjump (condition, label1)); - } - - else if (code == EQ || code == NE) -@@ -3712,10 +3708,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) - else - emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); - condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - } - else - { -@@ -3748,10 +3741,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - comp_reg = cmp_op0; - condition = gen_rtx_fmt_ee (signed_condition (code), - mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - } - else if (code == EQ) - { -@@ -3766,10 +3756,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - cmp_op1)); - } - condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - - } - else if (code == NE) -@@ -3785,10 +3772,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) - cmp_op1)); - } - condition = gen_rtx_NE (mode, comp_reg, const0_rtx); -- if (mode == SImode) -- emit_jump_insn (gen_condjump (condition, label1)); -- else -- emit_jump_insn (gen_long_condjump (condition, label1)); -+ emit_jump_insn (gen_condjump (condition, label1)); - } - else - { -@@ -3830,7 +3814,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) - - emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); - condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); -- emit_jump_insn (gen_long_condjump (condition, operands[3])); -+ emit_jump_insn (gen_condjump (condition, operands[3])); - } - - /* Implement TARGET_FRAME_POINTER_REQUIRED. */ -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 7bc91602ca2..ddf01505bd8 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2268,7 +2268,27 @@ else - (label_ref (match_operand 1)) - (pc)))]) - --(define_insn "branch_zero64" -+(define_insn "branch_zero_64" -+ [(set (pc) -+ (if_then_else (match_operator:SI 0 "ordered_comparison_operator" -+ [(match_operand:SI 1 "register_operand" "d") -+ (const_int 0)]) -+ (match_operand:SI 2 "pc_or_label_operand" "") -+ (match_operand:SI 3 "pc_or_label_operand" ""))) -+ ] -+ "TARGET_MB_64" -+ { -+ if (operands[3] == pc_rtx) -+ return "bea%C0i%?\t%z1,%2"; -+ else -+ return "bea%N0i%?\t%z1,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")] -+) -+ -+(define_insn "long_branch_zero" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" - [(match_operand 1 "register_operand" "d") -@@ -2279,9 +2299,9 @@ else - "TARGET_MB_64" - { - if (operands[3] == pc_rtx) -- return "bea%C0i%?\t%z1,%2"; -+ return "beal%C0i%?\t%z1,%2"; - else -- return "bea%N0i%?\t%z1,%3"; -+ return "beal%N0i%?\t%z1,%3"; - } - [(set_attr "type" "branch") - (set_attr "mode" "none") -@@ -2310,9 +2330,9 @@ else - - (define_insn "branch_compare64" - [(set (pc) -- (if_then_else (match_operator 0 "cmp_op" -- [(match_operand 1 "register_operand" "d") -- (match_operand 2 "register_operand" "d") -+ (if_then_else (match_operator:SI 0 "cmp_op" -+ [(match_operand:SI 1 "register_operand" "d") -+ (match_operand:SI 2 "register_operand" "d") - ]) - (label_ref (match_operand 3)) - (pc))) -@@ -2349,6 +2369,47 @@ else - (set_attr "length" "12")] - ) - -+(define_insn "long_branch_compare" -+ [(set (pc) -+ (if_then_else (match_operator 0 "cmp_op" -+ [(match_operand 1 "register_operand" "d") -+ (match_operand 2 "register_operand" "d") -+ ]) -+ (label_ref (match_operand 3)) -+ (pc))) -+ (clobber(reg:DI R_TMP))] -+ "TARGET_MB_64" -+ { -+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ enum rtx_code code = GET_CODE (operands[0]); -+ -+ if (code == GT || code == LE) -+ { -+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GTU || code == LEU) -+ { -+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); -+ code = swap_condition (code); -+ } -+ else if (code == GE || code == LT) -+ { -+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); -+ } -+ else if (code == GEU || code == LTU) -+ { -+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); -+ } -+ -+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); -+ return "beal%C0i%?\tr18,%3"; -+ } -+ [(set_attr "type" "branch") -+ (set_attr "mode" "none") -+ (set_attr "length" "12")] -+) -+ - (define_insn "branch_compare" - [(set (pc) - (if_then_else (match_operator:SI 0 "cmp_op" -@@ -2431,74 +2492,6 @@ else - - }) - --;; Used to implement comparison instructions --(define_expand "long_condjump" -- [(set (pc) -- (if_then_else (match_operand 0) -- (label_ref (match_operand 1)) -- (pc)))]) -- --(define_insn "long_branch_zero" -- [(set (pc) -- (if_then_else (match_operator:DI 0 "ordered_comparison_operator" -- [(match_operand:DI 1 "register_operand" "d") -- (const_int 0)]) -- (match_operand:DI 2 "pc_or_label_operand" "") -- (match_operand:DI 3 "pc_or_label_operand" ""))) -- ] -- "TARGET_MB_64" -- { -- if (operands[3] == pc_rtx) -- return "beal%C0i%?\t%z1,%2"; -- else -- return "beal%N0i%?\t%z1,%3"; -- } -- [(set_attr "type" "branch") -- (set_attr "mode" "none") -- (set_attr "length" "4")] --) -- --(define_insn "long_branch_compare" -- [(set (pc) -- (if_then_else (match_operator:DI 0 "cmp_op" -- [(match_operand:DI 1 "register_operand" "d") -- (match_operand:DI 2 "register_operand" "d") -- ]) -- (label_ref (match_operand 3)) -- (pc))) -- (clobber(reg:DI R_TMP))] -- "TARGET_MB_64" -- { -- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -- enum rtx_code code = GET_CODE (operands[0]); -- -- if (code == GT || code == LE) -- { -- output_asm_insn ("cmpl\tr18,%z1,%z2", operands); -- code = swap_condition (code); -- } -- else if (code == GTU || code == LEU) -- { -- output_asm_insn ("cmplu\tr18,%z1,%z2", operands); -- code = swap_condition (code); -- } -- else if (code == GE || code == LT) -- { -- output_asm_insn ("cmpl\tr18,%z2,%z1", operands); -- } -- else if (code == GEU || code == LTU) -- { -- output_asm_insn ("cmplu\tr18,%z2,%z1", operands); -- } -- -- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); -- return "beal%C0i%?\tr18,%3"; -- } -- [(set_attr "type" "branch") -- (set_attr "mode" "none") -- (set_attr "length" "12")] --) -- - ;;---------------------------------------------------------------- - ;; Unconditional branches - ;;---------------------------------------------------------------- --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch deleted file mode 100644 index 528fef0c..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 37af05f1ea7dc8476057580944a236f135babaf8 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 8 Aug 2018 17:37:26 +0530 -Subject: [PATCH 30/53] [Patch,Microblaze] : previous commit broke the - handling of SI Branch compare for Microblaze 32-bit.. - ---- - gcc/config/microblaze/microblaze.md | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index ddf01505bd8..87158066562 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2224,8 +2224,8 @@ else - (define_expand "cbranchsi4" - [(set (pc) - (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand 1 "register_operand") -- (match_operand 2 "arith_operand" "I,i")]) -+ [(match_operand:SI 1 "register_operand") -+ (match_operand:SI 2 "arith_operand" "I,i")]) - (label_ref (match_operand 3 "")) - (pc)))] - "" --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch deleted file mode 100644 index c247120b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 397a532bd80e21682ca3b5e230949f66c5b9ad30 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 11 Sep 2018 13:43:48 +0530 -Subject: [PATCH 31/53] [Patch, Microblaze] : Support of multilibs with m64 ... - ---- - gcc/config/microblaze/microblaze-c.c | 1 + - gcc/config/microblaze/t-microblaze | 15 ++++++--------- - libgcc/config/microblaze/t-microblaze | 11 +++-------- - 3 files changed, 10 insertions(+), 17 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c -index 2dcb879992c..50d01feb670 100644 ---- a/gcc/config/microblaze/microblaze-c.c -+++ b/gcc/config/microblaze/microblaze-c.c -@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) - } - if (TARGET_MB_64) - { -+ builtin_define ("__microblaze64"); - builtin_define ("__arch64__"); - builtin_define ("__microblaze64__"); - builtin_define ("__MICROBLAZE64__"); -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index 9fc80b142ce..35ab9654052 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -1,12 +1,9 @@ --MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 --MULTILIB_DIRNAMES = bs m mh le m64 --MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 --MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high --MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian --MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 --MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 -+MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high -+MULTILIB_DIRNAMES = m64 bs le m mh -+MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high - - # Extra files - microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ -diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 35021b24b7d..8d954a49575 100644 ---- a/libgcc/config/microblaze/t-microblaze -+++ b/libgcc/config/microblaze/t-microblaze -@@ -1,16 +1,11 @@ --LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ -- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 -+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 - - LIB2ADD += \ - $(srcdir)/config/microblaze/divsi3.S \ -- $(srcdir)/config/microblaze/divdi3.S \ - $(srcdir)/config/microblaze/modsi3.S \ -- $(srcdir)/config/microblaze/moddi3.S \ -+ $(srcdir)/config/microblaze/muldi3_hard.S \ - $(srcdir)/config/microblaze/mulsi3.S \ -- $(srcdir)/config/microblaze/muldi3.S \ - $(srcdir)/config/microblaze/stack_overflow_exit.S \ - $(srcdir)/config/microblaze/udivsi3.S \ -- $(srcdir)/config/microblaze/udivdi3.S \ - $(srcdir)/config/microblaze/umodsi3.S \ -- $(srcdir)/config/microblaze/umoddi3.S \ -- $(srcdir)/config/microblaze/divsi3_table.c \ -+ $(srcdir)/config/microblaze/divsi3_table.c --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0032-Fixed-issues-like.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0032-Fixed-issues-like.patch deleted file mode 100644 index 9f5381af..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0032-Fixed-issues-like.patch +++ /dev/null @@ -1,70 +0,0 @@ -From c03a994475d8894ae0913dd3534e72bfb389aa28 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Tue, 11 Sep 2018 14:58:00 +0530 -Subject: [PATCH 32/53] Fixed issues like: 1 Interrupt alignment issue 2 Sign - extension issue - ---- - gcc/config/microblaze/microblaze.c | 16 ++++++++++------ - gcc/config/microblaze/microblaze.md | 2 +- - 2 files changed, 11 insertions(+), 7 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index e33e1bc1482..64b948d6cfc 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2177,9 +2177,14 @@ compute_frame_size (HOST_WIDE_INT size) - - total_size += gp_reg_size; - -- /* Add 4 bytes for MSR. */ -+ /* Add 4/8 bytes for MSR. */ - if (microblaze_is_interrupt_variant ()) -- total_size += 4; -+ { -+ if (TARGET_MB_64) -+ total_size += 8; -+ else -+ total_size += 4; -+ } - - /* No space to be allocated for link register in leaf functions with no other - stack requirements. */ -@@ -2464,7 +2469,6 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -- int val1[2]; - long l[2]; - if (code == CONST_DOUBLE) - { -@@ -2479,10 +2483,10 @@ print_operand (FILE * file, rtx op, int letter) - } - else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) - { -- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -- val1[1] = INTVAL (op) & 0x00000000ffffffffLL; -+ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; -+ val[1] = INTVAL (op) & 0x00000000ffffffffLL; - } -- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); -+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); - } - else if (code == CONST_DOUBLE) - { -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 87158066562..b154d15c34c 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1096,7 +1096,7 @@ - case 1: - case 2: - { -- output_asm_insn ("ll%i1\t%0,%1", operands); -+ output_asm_insn ("lw%i1\t%0,%1", operands); - return "sextl32\t%0,%0"; - } - } --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0033-Fixed-below-issues.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0033-Fixed-below-issues.patch deleted file mode 100644 index 3a4b2037..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0033-Fixed-below-issues.patch +++ /dev/null @@ -1,307 +0,0 @@ -From 844daa118a8f376e5a53040fc953c86e70d34140 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 26 Nov 2019 17:26:15 +0530 -Subject: [PATCH 33/53] Fixed below issues: - -- Floating point print issues in 64bit mode -- Dejagnu Jump related issues -- Added dbl instruction - -Conflicts: - gcc/config/microblaze/microblaze.md ---- - gcc/config/microblaze/microblaze.c | 12 +++- - gcc/config/microblaze/microblaze.h | 7 +++ - gcc/config/microblaze/microblaze.md | 86 ++++++++++++++++++++++++----- - libgcc/config/microblaze/crti.S | 24 +++++++- - libgcc/config/microblaze/crtn.S | 13 +++++ - 5 files changed, 125 insertions(+), 17 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 64b948d6cfc..b2cd89a310a 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2473,7 +2473,12 @@ print_operand (FILE * file, rtx op, int letter) - if (code == CONST_DOUBLE) - { - if (GET_MODE (op) == DFmode) -- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); -+ { -+ if (TARGET_MB_64) -+ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); -+ else -+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); -+ } - else - { - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); -@@ -3876,7 +3881,10 @@ microblaze_expand_divide (rtx operands[]) - gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - - insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); -- jump = emit_jump_insn_after (gen_jump (div_end_label), insn); -+ if (TARGET_MB_64) -+ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn); -+ else -+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn); - JUMP_LABEL (jump) = div_end_label; - LABEL_NUSES (div_end_label) = 1; - emit_barrier (); -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 94ac736221c..17bf470c95b 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -888,10 +888,17 @@ do { \ - /* We do this to save a few 10s of code space that would be taken up - by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION - definition in crtstuff.c. */ -+#ifdef __arch64__ -+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ -+ asm ( SECTION_OP "\n" \ -+ "\tbrealid r15, " #FUNC "\n\t nop\n" \ -+ TEXT_SECTION_ASM_OP); -+#else - #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ - asm ( SECTION_OP "\n" \ - "\tbrlid r15, " #FUNC "\n\t nop\n" \ - TEXT_SECTION_ASM_OP); -+#endif - - /* We need to group -lm as well, since some Newlib math functions - reference __errno! */ -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index b154d15c34c..7d6cf263eb6 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -527,6 +527,15 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "floatdidf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (float:DF (match_operand:DI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dbl\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] -@@ -1299,7 +1308,7 @@ - (define_insn "movdi_long_int" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d") - (match_operand:DI 1 "general_operand" "i"))] -- "" -+ "TARGET_MB_64" - "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -1582,7 +1591,7 @@ - return "ll%i1\t%0,%1"; - case 3: - { -- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; -+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; - } - case 5: - return "sl%i0\t%1,%0"; -@@ -2371,9 +2380,9 @@ else - - (define_insn "long_branch_compare" - [(set (pc) -- (if_then_else (match_operator 0 "cmp_op" -- [(match_operand 1 "register_operand" "d") -- (match_operand 2 "register_operand" "d") -+ (if_then_else (match_operator:DI 0 "cmp_op" -+ [(match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d") - ]) - (label_ref (match_operand 3)) - (pc))) -@@ -2495,6 +2504,20 @@ else - ;;---------------------------------------------------------------- - ;; Unconditional branches - ;;---------------------------------------------------------------- -+(define_insn "jump_64" -+ [(set (pc) -+ (label_ref (match_operand 0 "" "")))] -+ "TARGET_MB_64" -+ { -+ if (GET_CODE (operands[0]) == REG) -+ return "brea%?\t%0"; -+ else -+ return "breai%?\t%l0"; -+ } -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_insn "jump" - [(set (pc) - (label_ref (match_operand 0 "" "")))] -@@ -2540,17 +2563,25 @@ else - { - //gcc_assert (GET_MODE (operands[0]) == Pmode); - -- if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) -- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); -- else -- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); -+ if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) { -+ if (!TARGET_MB_64) -+ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); -+ else -+ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); -+ } -+ else { -+ if (!TARGET_MB_64) -+ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); -+ else -+ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); -+ } - DONE; - } - ) - - (define_insn "tablejump_internal1" - [(set (pc) -- (match_operand 0 "register_operand" "d")) -+ (match_operand:SI 0 "register_operand" "d")) - (use (label_ref (match_operand 1 "" "")))] - "" - "bra%?\t%0 " -@@ -2558,11 +2589,21 @@ else - (set_attr "mode" "none") - (set_attr "length" "4")]) - -+(define_insn "tablejump_internal2" -+ [(set (pc) -+ (match_operand:DI 0 "register_operand" "d")) -+ (use (label_ref (match_operand 1 "" "")))] -+ "TARGET_MB_64" -+ "bra%?\t%0 " -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ - (define_expand "tablejump_internal3" - [(parallel [(set (pc) -- (plus (match_operand 0 "register_operand" "d") -- (label_ref (match_operand:SI 1 "" "")))) -- (use (label_ref (match_dup 1)))])] -+ (plus:SI (match_operand:SI 0 "register_operand" "d") -+ (label_ref:SI (match_operand:SI 1 "" "")))) -+ (use (label_ref:SI (match_dup 1)))])] - "" - "" - ) -@@ -2593,6 +2634,23 @@ else - "" - ) - -+(define_insn "" -+ [(set (pc) -+ (plus:DI (match_operand:DI 0 "register_operand" "d") -+ (label_ref:DI (match_operand 1 "" "")))) -+ (use (label_ref:DI (match_dup 1)))] -+ "TARGET_MB_64 && NEXT_INSN (as_a (operands[1])) != 0 -+ && GET_CODE (PATTERN (NEXT_INSN (as_a (operands[1])))) == ADDR_DIFF_VEC -+ && flag_pic" -+ { -+ output_asm_insn ("addlk\t%0,%0,r20",operands); -+ return "bra%?\t%0"; -+} -+ [(set_attr "type" "jump") -+ (set_attr "mode" "none") -+ (set_attr "length" "4")]) -+ -+ - ;;---------------------------------------------------------------- - ;; Function prologue/epilogue and stack allocation - ;;---------------------------------------------------------------- -@@ -3099,7 +3157,7 @@ else - ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference - ;; between "mfs" and "addik" instructions. - (define_insn "set_got" -- [(set (match_operand:SI 0 "register_operand" "=r") -+ [(set (match_operand 0 "register_operand" "=r") - (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))] - "" - "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" -diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S -index bc69d890370..7400eeb2e3b 100644 ---- a/libgcc/config/microblaze/crti.S -+++ b/libgcc/config/microblaze/crti.S -@@ -33,11 +33,32 @@ - .section .init, "ax" - .global __init - -+#ifdef __arch64__ - .weak _stack -- .set _stack, 0xffffffff -+ .set _stack, 0xffffffffffffffff - .weak _stack_end - .set _stack_end, 0 - -+ .align 3 -+__init: -+ addlik r1, r1, -32 -+ sl r15, r0, r1 -+ addlik r11, r0, _stack -+ mts rshr, r11 -+ addlik r11, r0, _stack_end -+ mts rslr, r11 -+ -+ .section .fini, "ax" -+ .global __fini -+ .align 3 -+__fini: -+ addlik r1, r1, -32 -+ sl r15, r0, r1 -+#else -+ .weak _stack -+ .set _stack, 0xffffffff -+ .weak _stack_end -+ .set _stack_end, 0 - .align 2 - __init: - addik r1, r1, -16 -@@ -53,3 +74,4 @@ __init: - __fini: - addik r1, r1, -16 - sw r15, r0, r1 -+#endif -diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S -index 1a1f0a8e0f3..14d9a084e3e 100644 ---- a/libgcc/config/microblaze/crtn.S -+++ b/libgcc/config/microblaze/crtn.S -@@ -29,7 +29,19 @@ - .section .note.GNU-stack,"",%progbits - .previous - #endif -+#ifdef __arch64__ -+ .section .init, "ax" -+ ll r15, r0, r1 -+ addlik r1, r1, 32 -+ rtsd r15, 8 -+ nop - -+ .section .fini, "ax" -+ ll r15, r0, r1 -+ addlik r1, r1, 32 -+ rtsd r15, 8 -+ nop -+#else - .section .init, "ax" - lw r15, r0, r1 - rtsd r15, 8 -@@ -39,3 +51,4 @@ - lw r15, r0, r1 - rtsd r15, 8 - addik r1, r1, 16 -+#endif --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0034-Added-double-arith-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0034-Added-double-arith-instructions.patch deleted file mode 100644 index 293c9f90..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0034-Added-double-arith-instructions.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 93874549e864b39689060edda456c897ea0fac4e Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Tue, 9 Oct 2018 10:07:08 +0530 -Subject: [PATCH 34/53] -Added double arith instructions -Fixed prologue stack - pointer decrement issue - ---- - gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++---- - gcc/config/microblaze/t-microblaze | 7 +++ - 2 files changed, 76 insertions(+), 9 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 7d6cf263eb6..943037336f1 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -527,6 +527,66 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "fix_truncsfsi2" -+ [(set (match_operand:SI 0 "register_operand" "=d") -+ (fix:SI (match_operand:SF 1 "register_operand" "d")))] -+ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" -+ "fint\t%0,%1" -+ [(set_attr "type" "fint") -+ (set_attr "mode" "SF") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "adddf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (plus:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dadd\t%0,%1,%2" -+ [(set_attr "type" "fadd") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+(define_insn "subdf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (minus:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "drsub\t%0,%2,%1" -+ [(set_attr "type" "frsub") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+(define_insn "muldf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (mult:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dmul\t%0,%1,%2" -+ [(set_attr "type" "fmul") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+(define_insn "divdf3" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (div:DF (match_operand:DF 1 "register_operand" "d") -+ (match_operand:DF 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "ddiv\t%0,%2,%1" -+ [(set_attr "type" "fdiv") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ -+ -+(define_insn "sqrtdf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dsqrt\t%0,%1" -+ [(set_attr "type" "fsqrt") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4")]) -+ - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "register_operand" "=d") - (float:DF (match_operand:DI 1 "register_operand" "d")))] -@@ -536,13 +596,13 @@ - (set_attr "mode" "DF") - (set_attr "length" "4")]) - --(define_insn "fix_truncsfsi2" -- [(set (match_operand:SI 0 "register_operand" "=d") -- (fix:SI (match_operand:SF 1 "register_operand" "d")))] -- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" -- "fint\t%0,%1" -- [(set_attr "type" "fint") -- (set_attr "mode" "SF") -+(define_insn "floatdfdi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (float:DI (match_operand:DF 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "dlong\t%0,%1" -+ [(set_attr "type" "fcvt") -+ (set_attr "mode" "DI") - (set_attr "length" "4")]) - - ;;---------------------------------------------------------------- -@@ -660,8 +720,8 @@ - "TARGET_MB_64" - "@ - rsubl\t%0,%2,%1 -- addik\t%0,%z1,-%2 -- addik\t%0,%z1,-%2" -+ addlik\t%0,%z1,-%2 -+ addlik\t%0,%z1,-%2" - [(set_attr "type" "arith,no_delay_arith,no_delay_arith") - (set_attr "mode" "DI") - (set_attr "length" "4,4,4")]) -diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze -index 35ab9654052..dfef45c268e 100644 ---- a/gcc/config/microblaze/t-microblaze -+++ b/gcc/config/microblaze/t-microblaze -@@ -1,6 +1,13 @@ - MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high - MULTILIB_DIRNAMES = m64 bs le m mh - MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high -+MULTILIB_EXCEPTIONS += *m64 -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift -+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul -+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul -+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high -+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high - MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch deleted file mode 100644 index 6135b952..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 8c359136e4b5ca105946b259212ed4bac0a69a9e Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Fri, 12 Oct 2018 16:07:36 +0530 -Subject: [PATCH 35/53] Fixed the issue in the delay slot with swap - instructions - ---- - gcc/config/microblaze/microblaze.md | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 943037336f1..162c6231a86 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -443,6 +443,9 @@ - (bswap:SI (match_operand:SI 1 "register_operand" "r")))] - "TARGET_REORDER" - "swapb %0, %1" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "4")] - ) - - (define_insn "bswaphi2" -@@ -451,6 +454,9 @@ - "TARGET_REORDER" - "swapb %0, %1 - swaph %0, %0" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "SI") -+ (set_attr "length" "8")] - ) - - ;;---------------------------------------------------------------- --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch deleted file mode 100644 index 23b640a6..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch +++ /dev/null @@ -1,256 +0,0 @@ -From 08ca1c1550145a8bddbd03a594620db13a259238 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Sat, 13 Oct 2018 21:12:43 +0530 -Subject: [PATCH 36/53] Fixed the load store issue with the 32bit arith - libraries - ---- - libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++- - libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++- - libgcc/config/microblaze/mulsi3.S | 3 +++ - libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++- - libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++- - 5 files changed, 98 insertions(+), 4 deletions(-) - -diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S -index 886a4f2bb36..3a7fc4d6122 100644 ---- a/libgcc/config/microblaze/divsi3.S -+++ b/libgcc/config/microblaze/divsi3.S -@@ -41,6 +41,17 @@ - .globl __divsi3 - .ent __divsi3 - .type __divsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__divsi3: -+ .frame r1,0,r15 -+ -+ ADDIK r1,r1,-32 -+ SLI r28,r1,0 -+ SLI r29,r1,8 -+ SLI r30,r1,16 -+ SLI r31,r1,24 -+#else - __divsi3: - .frame r1,0,r15 - -@@ -49,7 +60,7 @@ __divsi3: - SWI r29,r1,4 - SWI r30,r1,8 - SWI r31,r1,12 -- -+#endif - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQI r5,$LaResult_Is_Zero # Result is Zero - BGEID r5,$LaR5_Pos -@@ -89,6 +100,17 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - OR r3,r0,r0 # set result to 0 -+#ifdef __arch64__ -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r28,r1,0 -+ LLI r29,r1,8 -+ LLI r30,r1,16 -+ LLI r31,r1,24 -+ ADDLIK r1,r1,32 -+ RTSD r15,8 -+ NOP -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - LWI r28,r1,0 -@@ -97,6 +119,7 @@ $LaRETURN_HERE: - LWI r31,r1,12 - RTSD r15,8 - ADDIK r1,r1,16 -+#endif - .end __divsi3 - .size __divsi3, . - __divsi3 - -diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S -index 2c4f39a045f..3e405ea6267 100644 ---- a/libgcc/config/microblaze/modsi3.S -+++ b/libgcc/config/microblaze/modsi3.S -@@ -41,6 +41,17 @@ - .globl __modsi3 - .ent __modsi3 - .type __modsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__modsi3: -+ .frame r1,0,r15 -+ -+ addlik r1,r1,-32 -+ sli r28,r1,0 -+ sli r29,r1,8 -+ sli r30,r1,16 -+ sli r31,r1,24 -+#else - __modsi3: - .frame r1,0,r15 - -@@ -49,6 +60,7 @@ __modsi3: - swi r29,r1,4 - swi r30,r1,8 - swi r31,r1,12 -+#endif - - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQI r5,$LaResult_Is_Zero # Result is Zero -@@ -88,6 +100,18 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - or r3,r0,r0 # set result to 0 [Both mod as well as div are 0] -+ -+#ifdef __arch64__ -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r28,r1,0 -+ lli r29,r1,8 -+ lli r30,r1,16 -+ lli r31,r1,24 -+ addik r1,r1,32 -+ rtsd r15,8 -+ nop -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - lwi r28,r1,0 -@@ -95,7 +119,7 @@ $LaRETURN_HERE: - lwi r30,r1,8 - lwi r31,r1,12 - rtsd r15,8 -- addik r1,r1,16 -+#endif - .end __modsi3 - .size __modsi3, . - __modsi3 - -diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S -index c50a380177a..0329fa3037a 100644 ---- a/libgcc/config/microblaze/mulsi3.S -+++ b/libgcc/config/microblaze/mulsi3.S -@@ -41,6 +41,9 @@ - .globl __mulsi3 - .ent __mulsi3 - .type __mulsi3,@function -+#ifdef __arch64__ -+ .align 3 -+#endif - __mulsi3: - .frame r1,0,r15 - add r3,r0,r0 -diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S -index 1bf73265b98..7bdcd8873e5 100644 ---- a/libgcc/config/microblaze/udivsi3.S -+++ b/libgcc/config/microblaze/udivsi3.S -@@ -41,6 +41,16 @@ - .globl __udivsi3 - .ent __udivsi3 - .type __udivsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__udivsi3: -+ .frame r1,0,r15 -+ -+ ADDLIK r1,r1,-24 -+ SLI r29,r1,0 -+ SLI r30,r1,8 -+ SLI r31,r1,16 -+#else - __udivsi3: - .frame r1,0,r15 - -@@ -48,7 +58,7 @@ __udivsi3: - SWI r29,r1,0 - SWI r30,r1,4 - SWI r31,r1,8 -- -+#endif - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQID r5,$LaResult_Is_Zero # Result is Zero - ADDIK r30,r0,0 # Clear mod -@@ -98,6 +108,17 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - OR r3,r0,r0 # set result to 0 -+ -+#ifdef __arch64__ -+$LaRETURN_HERE: -+ # Restore values of CSRs and that of r3 and the divisor and the dividend -+ LLI r29,r1,0 -+ LLI r30,r1,8 -+ LLI r31,r1,16 -+ ADDIK r1,r1,24 -+ RTSD r15,8 -+ NOP -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - LWI r29,r1,0 -@@ -105,5 +126,6 @@ $LaRETURN_HERE: - LWI r31,r1,8 - RTSD r15,8 - ADDIK r1,r1,12 -+#endif - .end __udivsi3 - .size __udivsi3, . - __udivsi3 -diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S -index 2bc0909605f..7d1e4484a53 100644 ---- a/libgcc/config/microblaze/umodsi3.S -+++ b/libgcc/config/microblaze/umodsi3.S -@@ -41,6 +41,16 @@ - .globl __umodsi3 - .ent __umodsi3 - .type __umodsi3,@function -+#ifdef __arch64__ -+ .align 3 -+__umodsi3: -+ .frame r1,0,r15 -+ -+ addik r1,r1,-24 -+ swi r29,r1,0 -+ swi r30,r1,8 -+ swi r31,r1,16 -+#else - __umodsi3: - .frame r1,0,r15 - -@@ -48,7 +58,7 @@ __umodsi3: - swi r29,r1,0 - swi r30,r1,4 - swi r31,r1,8 -- -+#endif - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQId r5,$LaResult_Is_Zero # Result is Zero - ADDIK r3,r0,0 # Clear div -@@ -101,6 +111,17 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - or r3,r0,r0 # set result to 0 -+ -+#ifdef __arch64__ -+$LaRETURN_HERE: -+# Restore values of CSRs and that of r3 and the divisor and the dividend -+ lli r29,r1,0 -+ lli r30,r1,8 -+ lli r31,r1,16 -+ addlik r1,r1,24 -+ rtsd r15,8 -+ nop -+#else - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend - lwi r29,r1,0 -@@ -108,5 +129,6 @@ $LaRETURN_HERE: - lwi r31,r1,8 - rtsd r15,8 - addik r1,r1,12 -+#endif - .end __umodsi3 - .size __umodsi3, . - __umodsi3 --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch deleted file mode 100644 index 3f0ec920..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 3fbf3d7049cccb5ddec02e3360f1b4da0eb5a177 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Mon, 15 Oct 2018 12:00:10 +0530 -Subject: [PATCH 37/53] extending the Dwarf support to 64bit Microblaze - ---- - gcc/config/microblaze/microblaze.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 17bf470c95b..b0c44c4fd50 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; - /* Use DWARF 2 debugging information by default. */ - #define DWARF2_DEBUGGING_INFO 1 - #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG --#define DWARF2_ADDR_SIZE 4 -+#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4) - - /* Target machine storage layout */ - --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0038-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0038-fixing-the-typo-errors-in-umodsi3-file.patch deleted file mode 100644 index 0f91a572..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0038-fixing-the-typo-errors-in-umodsi3-file.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 23c8d1d396c7ae5e478c793b72fddcec80dfd083 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Tue, 16 Oct 2018 07:55:46 +0530 -Subject: [PATCH 38/53] fixing the typo errors in umodsi3 file - ---- - libgcc/config/microblaze/umodsi3.S | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S -index 7d1e4484a53..63ab1c2a357 100644 ---- a/libgcc/config/microblaze/umodsi3.S -+++ b/libgcc/config/microblaze/umodsi3.S -@@ -47,9 +47,9 @@ __umodsi3: - .frame r1,0,r15 - - addik r1,r1,-24 -- swi r29,r1,0 -- swi r30,r1,8 -- swi r31,r1,16 -+ sli r29,r1,0 -+ sli r30,r1,8 -+ sli r31,r1,16 - #else - __umodsi3: - .frame r1,0,r15 --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch deleted file mode 100644 index 6aa6937f..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch +++ /dev/null @@ -1,68 +0,0 @@ -From cc2c7e5255edc97064d29880f156d603d3ec740a Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Wed, 17 Oct 2018 16:56:14 +0530 -Subject: [PATCH 39/53] fixing the 32bit LTO related issue9(1014024) - ---- - gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- - 1 file changed, 14 insertions(+), 10 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index b0c44c4fd50..c6c3a9baa5a 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; - #define WORD_REGISTER_OPERATIONS 1 - - #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND --/* --#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -- if (GET_MODE_CLASS (MODE) == MODE_INT \ -- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ -- (MODE) = TARGET_MB_64 ? DImode : SImode; --*/ -+ -+#ifndef __arch64__ -+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -+ if (GET_MODE_CLASS (MODE) == MODE_INT \ -+ && GET_MODE_SIZE (MODE) < 4) \ -+ (MODE) = SImode; -+#endif -+ - /* Standard register usage. */ - - /* On the MicroBlaze, we have 32 integer registers */ -@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info; - - #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS - -+#ifdef __aarch64__ - #define LIBCALL_VALUE(MODE) \ - gen_rtx_REG (MODE,GP_RETURN) -- --/*#define LIBCALL_VALUE(MODE) \ -+#else -+#define LIBCALL_VALUE(MODE) \ - gen_rtx_REG ( \ - ((GET_MODE_CLASS (MODE) != MODE_INT \ - || GET_MODE_SIZE (MODE) >= 4) \ - ? (MODE) \ - : SImode), GP_RETURN) --*/ -+#endif -+ - /* 1 if N is a possible register number for a function value. - On the MicroBlaze, R2 R3 are the only register thus used. - Currently, R2 are only implemented here (C has no complex type) */ -@@ -518,7 +522,7 @@ typedef struct microblaze_args - /* 4 insns + 2 words of data. */ - #define TRAMPOLINE_SIZE (6 * 4) - --#define TRAMPOLINE_ALIGNMENT 64 -+#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32) - - #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) - --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch deleted file mode 100644 index e086a851..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 7d245c4d22c5c845666f33f19d23c075dcae2af6 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Fri, 19 Oct 2018 14:26:25 +0530 -Subject: [PATCH 40/53] Fixed the missing stack adjustment in prologue of - modsi3 function - ---- - libgcc/config/microblaze/modsi3.S | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S -index 3e405ea6267..c98442c01c2 100644 ---- a/libgcc/config/microblaze/modsi3.S -+++ b/libgcc/config/microblaze/modsi3.S -@@ -119,6 +119,7 @@ $LaRETURN_HERE: - lwi r30,r1,8 - lwi r31,r1,12 - rtsd r15,8 -+ addik r1,r1,16 - #endif - .end __modsi3 - .size __modsi3, . - __modsi3 --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch deleted file mode 100644 index b3b04ae7..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 4de570fde0740cbcfea443aea24c2cfc9df5a876 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 24 Oct 2018 18:31:04 +0530 -Subject: [PATCH 41/53] [Patch,Microblaze] : corrected SPN for dlong - instruction mapping. - ---- - gcc/config/microblaze/microblaze.md | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 162c6231a86..f62ad28130b 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -602,9 +602,9 @@ - (set_attr "mode" "DF") - (set_attr "length" "4")]) - --(define_insn "floatdfdi2" -+(define_insn "fix_truncdfdi2" - [(set (match_operand:DI 0 "register_operand" "=d") -- (float:DI (match_operand:DF 1 "register_operand" "d")))] -+ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] - "TARGET_MB_64" - "dlong\t%0,%1" - [(set_attr "type" "fcvt") --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch deleted file mode 100644 index 29e8d753..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch +++ /dev/null @@ -1,59 +0,0 @@ -From b2d05f4ad5c66fb8cec37064a77d21194db9dd32 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Thu, 29 Nov 2018 17:55:08 +0530 -Subject: [PATCH 42/53] fixing the long & long long mingw toolchain issue - ---- - gcc/config/microblaze/constraints.md | 2 +- - gcc/config/microblaze/microblaze.md | 8 ++++---- - 2 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index 0a4d5269314..e3f89491fb4 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -55,7 +55,7 @@ - (define_constraint "K" - "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." - (and (match_code "const_int") -- (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) -+ (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) - - - ;; Define floating point constraints -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index f62ad28130b..74be0728e75 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -648,8 +648,8 @@ - if (TARGET_MB_64) - { - if (GET_CODE (operands[2]) == CONST_INT && -- INTVAL(operands[2]) < (long)-549755813888 && -- INTVAL(operands[2]) > (long)549755813887) -+ INTVAL(operands[2]) < (long long)-549755813888 && -+ INTVAL(operands[2]) > (long long)549755813887) - FAIL; - } - }) -@@ -1264,7 +1264,7 @@ - (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] - "TARGET_MB_64 && (register_operand (operands[0], DImode) && - (GET_CODE (operands[1]) == CONST_INT && -- (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" -+ (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" - "@ - addlk\t%0,r0,r0\t - addlik\t%0,r0,%1\t #N1 %X1 -@@ -1298,7 +1298,7 @@ - case 1: - case 2: - if (GET_CODE (operands[1]) == CONST_INT && -- (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) -+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) - return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; - else - return "addlik\t%0,r0,%1"; --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch deleted file mode 100644 index 4fcf90c8..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 3691860b698107ce5338468cbef932c63d195961 Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Thu, 14 Mar 2019 18:11:04 +0530 -Subject: [PATCH 43/53] Fix the MB-64 bug of handling QI objects - ---- - gcc/config/microblaze/microblaze.md | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 74be0728e75..fed6f5e0234 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2345,11 +2345,11 @@ else - - (define_insn "branch_zero_64" - [(set (pc) -- (if_then_else (match_operator:SI 0 "ordered_comparison_operator" -+ (if_then_else (match_operator 0 "ordered_comparison_operator" - [(match_operand:SI 1 "register_operand" "d") - (const_int 0)]) -- (match_operand:SI 2 "pc_or_label_operand" "") -- (match_operand:SI 3 "pc_or_label_operand" ""))) -+ (match_operand 2 "pc_or_label_operand" "") -+ (match_operand 3 "pc_or_label_operand" ""))) - ] - "TARGET_MB_64" - { -@@ -2365,11 +2365,11 @@ else - - (define_insn "long_branch_zero" - [(set (pc) -- (if_then_else (match_operator 0 "ordered_comparison_operator" -- [(match_operand 1 "register_operand" "d") -+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" -+ [(match_operand:DI 1 "register_operand" "d") - (const_int 0)]) -- (match_operand 2 "pc_or_label_operand" "") -- (match_operand 3 "pc_or_label_operand" ""))) -+ (match_operand:DI 2 "pc_or_label_operand" "") -+ (match_operand:DI 3 "pc_or_label_operand" ""))) - ] - "TARGET_MB_64" - { --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch deleted file mode 100644 index 43c13b31..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch +++ /dev/null @@ -1,87 +0,0 @@ -From b26f11b38406605f1601626f9ee8267f85b4857c Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Fri, 29 Mar 2019 12:08:39 +0530 -Subject: [PATCH 44/53] [Patch,Microblaze] : We will check the possibility of - peephole2 optimization,if we can then we will fix the compiler issue. - ---- - gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------ - 1 file changed, 38 insertions(+), 25 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index fed6f5e0234..1490a522a4c 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -882,31 +882,44 @@ - (set_attr "mode" "SI") - (set_attr "length" "4")]) - --(define_peephole2 -- [(set (match_operand:SI 0 "register_operand") -- (fix:SI (match_operand:SF 1 "register_operand"))) -- (set (pc) -- (if_then_else (match_operator 2 "ordered_comparison_operator" -- [(match_operand:SI 3 "register_operand") -- (match_operand:SI 4 "arith_operand")]) -- (label_ref (match_operand 5)) -- (pc)))] -- "TARGET_HARD_FLOAT && !TARGET_MB_64" -- [(set (match_dup 1) (match_dup 3))] -- -- { -- rtx condition; -- rtx cmp_op0 = operands[3]; -- rtx cmp_op1 = operands[4]; -- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -- -- emit_insn (gen_cstoresf4 (comp_reg, operands[2], -- gen_rtx_REG (SFmode, REGNO (cmp_op0)), -- gen_rtx_REG (SFmode, REGNO (cmp_op1)))); -- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -- emit_jump_insn (gen_condjump (condition, operands[5])); -- } --) -+;; peephole2 optimization will be done only if fint and if-then-else -+;; are dependent.added condition for the same. -+;; if they are dependent then gcc is giving "flow control insn inside a basic block" -+;; testcase: -+;; volatile float vec = 1.0; -+;; volatile int ci = 2; -+;; register int cj = (int)(vec); -+;;// ci=cj; -+;;// if (ci <0) { -+;; if (cj < 0) { -+;; ci = 0; -+;; } -+;; commenting for now.we will check the possibility of this optimization later -+ -+;;(define_peephole2 -+;; [(set (match_operand:SI 0 "register_operand") -+;; (fix:SI (match_operand:SF 1 "register_operand"))) -+;; (set (pc) -+;; (if_then_else (match_operator 2 "ordered_comparison_operator" -+;; [(match_operand:SI 3 "register_operand") -+;; (match_operand:SI 4 "arith_operand")]) -+;; (label_ref (match_operand 5)) -+;; (pc)))] -+;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" -+;; [(set (match_dup 1) (match_dup 3))] -+;; { -+;; rtx condition; -+;; rtx cmp_op0 = operands[3]; -+;; rtx cmp_op1 = operands[4]; -+;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); -+;; -+;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], -+;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), -+;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); -+;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); -+;; emit_jump_insn (gen_condjump (condition, operands[5])); -+;; } -+;;) - - ;;---------------------------------------------------------------- - ;; Negation and one's complement --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch deleted file mode 100644 index 3edef57a..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch +++ /dev/null @@ -1,466 +0,0 @@ -From db8016ae6874865f57c6841ecabf9d9cdf785ece Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 17 Apr 2019 12:36:16 +0530 -Subject: [PATCH 45/53] [Patch,MicroBlaze]: fixed typos in mul,div and mod - assembly files. - ---- - libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++---- - libgcc/config/microblaze/modsi3.S | 40 ++++++++++++++++++--- - libgcc/config/microblaze/mulsi3.S | 33 ++++++++++++++++- - libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++--- - libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++--- - 5 files changed, 212 insertions(+), 20 deletions(-) - -diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S -index 3a7fc4d6122..0fd275c8702 100644 ---- a/libgcc/config/microblaze/divsi3.S -+++ b/libgcc/config/microblaze/divsi3.S -@@ -46,7 +46,7 @@ - __divsi3: - .frame r1,0,r15 - -- ADDIK r1,r1,-32 -+ ADDLIK r1,r1,-32 - SLI r28,r1,0 - SLI r29,r1,8 - SLI r30,r1,16 -@@ -61,13 +61,23 @@ __divsi3: - SWI r30,r1,8 - SWI r31,r1,12 - #endif -- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -- BEQI r5,$LaResult_Is_Zero # Result is Zero -- BGEID r5,$LaR5_Pos -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero -+ BEAGEID r5,$LaR5_Pos -+#else -+ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEQI r5,$LaResult_Is_Zero # Result is Zero -+ BGEID r5,$LaR5_Pos -+#endif - XOR r28,r5,r6 # Get the sign of the result - RSUBI r5,r5,0 # Make r5 positive - $LaR5_Pos: -- BGEI r6,$LaR6_Pos -+#ifdef __arch64__ -+ BEAGEI r6,$LaR6_Pos -+#else -+ BGEI r6,$LaR6_Pos -+#endif - RSUBI r6,r6,0 # Make r6 positive - $LaR6_Pos: - ADDIK r30,r0,0 # Clear mod -@@ -76,26 +86,51 @@ $LaR6_Pos: - - # First part try to find the first '1' in the r5 - $LaDIV0: -- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+#ifdef __arch64__ -+ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+#else -+ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 -+#endif - $LaDIV1: - ADD r5,r5,r5 # left shift logical r5 -+#ifdef __arch64__ -+ BEAGTID r5,$LaDIV1 -+#else - BGTID r5,$LaDIV1 -+#endif - ADDIK r29,r29,-1 - $LaDIV2: - ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry - ADDC r30,r30,r30 # Move that bit into the Mod register - RSUB r31,r6,r30 # Try to subtract (r30 a r6) -+#ifdef __arch64__ -+ BEALTI r31,$LaMOD_TOO_SMALL -+#else - BLTI r31,$LaMOD_TOO_SMALL -+#endif - OR r30,r0,r31 # Move the r31 to mod since the result was positive - ADDIK r3,r3,1 - $LaMOD_TOO_SMALL: - ADDIK r29,r29,-1 -+#ifdef __arch64__ -+ BEAEQi r29,$LaLOOP_END -+#else - BEQi r29,$LaLOOP_END -+#endif - ADD r3,r3,r3 # Shift in the '1' into div -+#ifdef __arch64__ -+ BREAI $LaDIV2 # Div2 -+#else - BRI $LaDIV2 # Div2 -+#endif - $LaLOOP_END: -+#ifdef __arch64__ -+ BEAGEI r28,$LaRETURN_HERE -+ BREAID $LaRETURN_HERE -+#else - BGEI r28,$LaRETURN_HERE - BRID $LaRETURN_HERE -+#endif - RSUBI r3,r3,0 # Negate the result - $LaDiv_By_Zero: - $LaResult_Is_Zero: -diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S -index c98442c01c2..28775d71ba0 100644 ---- a/libgcc/config/microblaze/modsi3.S -+++ b/libgcc/config/microblaze/modsi3.S -@@ -62,40 +62,72 @@ __modsi3: - swi r31,r1,12 - #endif - -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero -+ BEAGEId r5,$LaR5_Pos -+#else - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQI r5,$LaResult_Is_Zero # Result is Zero - BGEId r5,$LaR5_Pos -+#endif - ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] - RSUBI r5,r5,0 # Make r5 positive - $LaR5_Pos: -- BGEI r6,$LaR6_Pos -+#ifdef __arch64__ -+ BEAGEI r6,$LaR6_Pos -+#else -+ BGEI r6,$LaR6_Pos -+#endif - RSUBI r6,r6,0 # Make r6 positive - $LaR6_Pos: - ADDIK r3,r0,0 # Clear mod - ADDIK r30,r0,0 # clear div -- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip -+#ifdef __arch64__ -+ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip - # the first bit search. -+#else -+ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip -+ # the first bit search. -+#endif - ADDIK r29,r0,32 # Initialize the loop count - # First part try to find the first '1' in the r5 - $LaDIV1: - ADD r5,r5,r5 # left shift logical r5 -- BGEID r5,$LaDIV1 # -+#ifdef __arch64__ -+ BEAGEID r5,$LaDIV1 # -+#else -+ BGEID r5,$LaDIV1 # -+#endif - ADDIK r29,r29,-1 - $LaDIV2: - ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry - ADDC r3,r3,r3 # Move that bit into the Mod register - rSUB r31,r6,r3 # Try to subtract (r30 a r6) -+#ifdef __arch64__ -+ BEALTi r31,$LaMOD_TOO_SMALL -+#else - BLTi r31,$LaMOD_TOO_SMALL -+#endif - OR r3,r0,r31 # Move the r31 to mod since the result was positive - ADDIK r30,r30,1 - $LaMOD_TOO_SMALL: - ADDIK r29,r29,-1 -+#ifdef __arch64__ -+ BEAEQi r29,$LaLOOP_END -+ ADD r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BEAGEI r28,$LaRETURN_HERE -+ BREAId $LaRETURN_HERE -+#else - BEQi r29,$LaLOOP_END - ADD r30,r30,r30 # Shift in the '1' into div - BRI $LaDIV2 # Div2 - $LaLOOP_END: - BGEI r28,$LaRETURN_HERE - BRId $LaRETURN_HERE -+#endif - rsubi r3,r3,0 # Negate the result - $LaDiv_By_Zero: - $LaResult_Is_Zero: -@@ -108,7 +140,7 @@ $LaRETURN_HERE: - lli r29,r1,8 - lli r30,r1,16 - lli r31,r1,24 -- addik r1,r1,32 -+ addlik r1,r1,32 - rtsd r15,8 - nop - #else -diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S -index 0329fa3037a..7557368bc1c 100644 ---- a/libgcc/config/microblaze/mulsi3.S -+++ b/libgcc/config/microblaze/mulsi3.S -@@ -43,7 +43,37 @@ - .type __mulsi3,@function - #ifdef __arch64__ - .align 3 --#endif -+__mulsi3: -+ .frame r1,0,r15 -+ add r3,r0,r0 -+ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero -+ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero -+ BEAGEId r5,$L_R5_Pos -+ XOR r4,r5,r6 # Get the sign of the result -+ RSUBI r5,r5,0 # Make r5 positive -+$L_R5_Pos: -+ BEAGEI r6,$L_R6_Pos -+ RSUBI r6,r6,0 # Make r6 positive -+$L_R6_Pos: -+ breai $L1 -+$L2: -+ add r5,r5,r5 -+$L1: -+ srl r6,r6 -+ addc r7,r0,r0 -+ beaeqi r7,$L2 -+ beaneid r6,$L2 -+ add r3,r3,r5 -+ bealti r4,$L_NegateResult -+ rtsd r15,8 -+ nop -+$L_NegateResult: -+ rtsd r15,8 -+ rsub r3,r3,r0 -+$L_Result_Is_Zero: -+ rtsd r15,8 -+ addi r3,r0,0 -+#else - __mulsi3: - .frame r1,0,r15 - add r3,r0,r0 -@@ -74,5 +104,6 @@ $L_NegateResult: - $L_Result_Is_Zero: - rtsd r15,8 - addi r3,r0,0 -+#endif - .end __mulsi3 - .size __mulsi3, . - __mulsi3 -diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S -index 7bdcd8873e5..feff14664fb 100644 ---- a/libgcc/config/microblaze/udivsi3.S -+++ b/libgcc/config/microblaze/udivsi3.S -@@ -59,52 +59,96 @@ __udivsi3: - SWI r30,r1,4 - SWI r31,r1,8 - #endif -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQID r5,$LaResult_Is_Zero # Result is Zero -+#else - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQID r5,$LaResult_Is_Zero # Result is Zero -+#endif - ADDIK r30,r0,0 # Clear mod - ADDIK r29,r0,32 # Initialize the loop count - - # Check if r6 and r5 are equal # if yes, return 1 - RSUB r18,r5,r6 -+#ifdef __arch64__ -+ BEAEQID r18,$LaRETURN_HERE -+#else - BEQID r18,$LaRETURN_HERE -+#endif - ADDIK r3,r0,1 - - # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 - XOR r18,r5,r6 -- BGEID r18,16 -+#ifdef __arch64__ -+ BEAGEID r18,16 -+#else -+ BGEID r18,16 -+#endif - ADD r3,r0,r0 # We would anyways clear r3 -+#ifdef __arch64__ -+ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater -+ BREAI $LCheckr6 -+ RSUB r18,r6,r5 # MICROBLAZEcmp -+ BEALTI r18,$LaRETURN_HERE -+#else - BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater - BRI $LCheckr6 - RSUB r18,r6,r5 # MICROBLAZEcmp - BLTI r18,$LaRETURN_HERE -- -+#endif - # If r6 [bit 31] is set, then return result as 1 - $LCheckr6: -- BGTI r6,$LaDIV0 -- BRID $LaRETURN_HERE -+#ifdef __arch64__ -+ BEAGTI r6,$LaDIV0 -+ BREAID $LaRETURN_HERE -+#else -+ BGTI r6,$LaDIV0 -+ BRID $LaRETURN_HERE -+#endif - ADDIK r3,r0,1 - - # First part try to find the first '1' in the r5 - $LaDIV0: -+#ifdef __arch64__ -+ BEALTI r5,$LaDIV2 -+#else - BLTI r5,$LaDIV2 -+#endif - $LaDIV1: - ADD r5,r5,r5 # left shift logical r5 -+#ifdef __arch64__ -+ BEAGTID r5,$LaDIV1 -+#else - BGTID r5,$LaDIV1 -+#endif - ADDIK r29,r29,-1 - $LaDIV2: - ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry - ADDC r30,r30,r30 # Move that bit into the Mod register - RSUB r31,r6,r30 # Try to subtract (r30 a r6) -+#ifdef __arch64__ -+ BEALTI r31,$LaMOD_TOO_SMALL -+#else - BLTI r31,$LaMOD_TOO_SMALL -+#endif - OR r30,r0,r31 # Move the r31 to mod since the result was positive - ADDIK r3,r3,1 - $LaMOD_TOO_SMALL: - ADDIK r29,r29,-1 -+#ifdef __arch64__ -+ BEAEQi r29,$LaLOOP_END -+ ADD r3,r3,r3 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+#else - BEQi r29,$LaLOOP_END - ADD r3,r3,r3 # Shift in the '1' into div - BRI $LaDIV2 # Div2 - $LaLOOP_END: - BRI $LaRETURN_HERE -+#endif - $LaDiv_By_Zero: - $LaResult_Is_Zero: - OR r3,r0,r0 # set result to 0 -@@ -115,7 +159,7 @@ $LaRETURN_HERE: - LLI r29,r1,0 - LLI r30,r1,8 - LLI r31,r1,16 -- ADDIK r1,r1,24 -+ ADDLIK r1,r1,24 - RTSD r15,8 - NOP - #else -diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S -index 63ab1c2a357..f5bbb6f2d10 100644 ---- a/libgcc/config/microblaze/umodsi3.S -+++ b/libgcc/config/microblaze/umodsi3.S -@@ -46,7 +46,7 @@ - __umodsi3: - .frame r1,0,r15 - -- addik r1,r1,-24 -+ addlik r1,r1,-24 - sli r29,r1,0 - sli r30,r1,8 - sli r31,r1,16 -@@ -59,27 +59,77 @@ __umodsi3: - swi r30,r1,4 - swi r31,r1,8 - #endif -+#ifdef __arch64__ -+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error -+ BEAEQId r5,$LaResult_Is_Zero # Result is Zero -+#else - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error - BEQId r5,$LaResult_Is_Zero # Result is Zero -+#endif - ADDIK r3,r0,0 # Clear div - ADDIK r30,r0,0 # clear mod - ADDIK r29,r0,32 # Initialize the loop count - - # Check if r6 and r5 are equal # if yes, return 0 - rsub r18,r5,r6 -- beqi r18,$LaRETURN_HERE - -+#ifdef __arch64__ -+ beaeqi r18,$LaRETURN_HERE -+#else -+ beqi r18,$LaRETURN_HERE -+#endif - # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 - xor r18,r5,r6 -+#ifdef __arch64__ -+ beageid r18,16 -+ addik r3,r5,0 -+ bealti r6,$LaRETURN_HERE -+ breai $LCheckr6 -+ rsub r18,r5,r6 # MICROBLAZEcmp -+ beagti r18,$LaRETURN_HERE -+#else - bgeid r18,16 - addik r3,r5,0 - blti r6,$LaRETURN_HERE - bri $LCheckr6 - rsub r18,r5,r6 # MICROBLAZEcmp - bgti r18,$LaRETURN_HERE -- -+#endif - # If r6 [bit 31] is set, then return result as r5-r6 - $LCheckr6: -+#ifdef __arch64__ -+ beagtid r6,$LaDIV0 -+ addik r3,r0,0 -+ addik r18,r0,0x7fffffff -+ and r5,r5,r18 -+ and r6,r6,r18 -+ breaid $LaRETURN_HERE -+ rsub r3,r6,r5 -+# First part: try to find the first '1' in the r5 -+$LaDIV0: -+ BEALTI r5,$LaDIV2 -+$LaDIV1: -+ ADD r5,r5,r5 # left shift logical r5 -+ BEAGEID r5,$LaDIV1 # -+ ADDIK r29,r29,-1 -+$LaDIV2: -+ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry -+ ADDC r3,r3,r3 # Move that bit into the Mod register -+ rSUB r31,r6,r3 # Try to subtract (r3 a r6) -+ BEALTi r31,$LaMOD_TOO_SMALL -+ OR r3,r0,r31 # Move the r31 to mod since the result was positive -+ ADDIK r30,r30,1 -+$LaMOD_TOO_SMALL: -+ ADDIK r29,r29,-1 -+ BEAEQi r29,$LaLOOP_END -+ ADD r30,r30,r30 # Shift in the '1' into div -+ BREAI $LaDIV2 # Div2 -+$LaLOOP_END: -+ BREAI $LaRETURN_HERE -+$LaDiv_By_Zero: -+$LaResult_Is_Zero: -+ or r3,r0,r0 # set result to 0 -+#else - bgtid r6,$LaDIV0 - addik r3,r0,0 - addik r18,r0,0x7fffffff -@@ -111,7 +161,7 @@ $LaLOOP_END: - $LaDiv_By_Zero: - $LaResult_Is_Zero: - or r3,r0,r0 # set result to 0 -- -+#endif - #ifdef __arch64__ - $LaRETURN_HERE: - # Restore values of CSRs and that of r3 and the divisor and the dividend --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0046-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0046-Author-Nagaraju-nmekala-xilinx.com.patch deleted file mode 100644 index 456c5a48..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0046-Author-Nagaraju-nmekala-xilinx.com.patch +++ /dev/null @@ -1,479 +0,0 @@ -From 45fcd0217edf07fcb6473812cfc4ccacc8e95aac Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Thu, 18 Apr 2019 16:00:37 +0530 -Subject: [PATCH 46/53] Author: Nagaraju Date: Wed Apr - 17 14:11:00 2019 +0530 - - [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default - By default MB-64 is generatting barrel-shift instructions. It has been - removed from default. Barrel-shift instructions will be generated only if - barrel-shifter is enabled. Similarly to double instructions as well. - - Signed-off-by :Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.c | 2 +- - gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++-- - 2 files changed, 252 insertions(+), 19 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index b2cd89a310a..d1257032bfb 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3870,7 +3870,7 @@ microblaze_expand_divide (rtx operands[]) - emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); - - if (TARGET_MB_64) { -- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); -+ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); - emit_insn (gen_adddi3 (regt1, regt1, operands[2])); - } - else { -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 1490a522a4c..40328b0d39d 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -547,7 +547,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (plus:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dadd\t%0,%1,%2" - [(set_attr "type" "fadd") - (set_attr "mode" "DF") -@@ -557,7 +557,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (minus:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "drsub\t%0,%2,%1" - [(set_attr "type" "frsub") - (set_attr "mode" "DF") -@@ -567,7 +567,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (mult:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dmul\t%0,%1,%2" - [(set_attr "type" "fmul") - (set_attr "mode" "DF") -@@ -577,7 +577,7 @@ - [(set (match_operand:DF 0 "register_operand" "=d") - (div:DF (match_operand:DF 1 "register_operand" "d") - (match_operand:DF 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "ddiv\t%0,%2,%1" - [(set_attr "type" "fdiv") - (set_attr "mode" "DF") -@@ -587,7 +587,7 @@ - (define_insn "sqrtdf2" - [(set (match_operand:DF 0 "register_operand" "=d") - (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dsqrt\t%0,%1" - [(set_attr "type" "fsqrt") - (set_attr "mode" "DF") -@@ -596,7 +596,7 @@ - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "register_operand" "=d") - (float:DF (match_operand:DI 1 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dbl\t%0,%1" - [(set_attr "type" "fcvt") - (set_attr "mode" "DF") -@@ -605,7 +605,7 @@ - (define_insn "fix_truncdfdi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" - "dlong\t%0,%1" - [(set_attr "type" "fcvt") - (set_attr "mode" "DI") -@@ -1299,6 +1299,34 @@ - (set_attr "mode" "DI") - (set_attr "length" "4")]) - -+(define_insn "*movdi_internal2_bshift" -+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") -+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ case 2: -+ if (GET_CODE (operands[1]) == CONST_INT && -+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) -+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ else -+ return "addlik\t%0,r0,%1"; -+ case 3: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 5: -+ case 6: -+ return "sl%i0\t%z1,%0"; -+ } -+ } -+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4,4,12,4,8,4,8")]) -+ - (define_insn "*movdi_internal2" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") - (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] -@@ -1312,7 +1340,15 @@ - case 2: - if (GET_CODE (operands[1]) == CONST_INT && - (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) -- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; -+ { -+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("addlik\t%0,r0,%h1", operands); -+ output_asm_insn ("addlik\t%2,r0,32", operands); -+ output_asm_insn ("addlik\t%2,%2,-1", operands); -+ output_asm_insn ("beaneid\t%2,.-8", operands); -+ output_asm_insn ("addlk\t%0,%0,%0", operands); -+ return "addlik\t%0,%0,%j1 #li => la"; -+ } - else - return "addlik\t%0,r0,%1"; - case 3: -@@ -1387,7 +1423,7 @@ - (define_insn "movdi_long_int" - [(set (match_operand:DI 0 "nonimmediate_operand" "=d") - (match_operand:DI 1 "general_operand" "i"))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; - [(set_attr "type" "no_delay_arith") - (set_attr "mode" "DI") -@@ -1654,6 +1690,33 @@ - ;; movdf_internal - ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT - ;; -+(define_insn "*movdf_internal_64_bshift" -+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") -+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" -+ { -+ switch (which_alternative) -+ { -+ case 0: -+ return "addlk\t%0,%1,r0"; -+ case 1: -+ return "addlk\t%0,r0,r0"; -+ case 2: -+ case 4: -+ return "ll%i1\t%0,%1"; -+ case 3: -+ { -+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; -+ } -+ case 5: -+ return "sl%i0\t%1,%0"; -+ } -+ gcc_unreachable (); -+ } -+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") -+ (set_attr "mode" "DF") -+ (set_attr "length" "4,4,4,16,4,4")]) -+ - (define_insn "*movdf_internal_64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") - (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] -@@ -1670,7 +1733,13 @@ - return "ll%i1\t%0,%1"; - case 3: - { -- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; -+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("addlik\t%0,r0,%h1", operands); -+ output_asm_insn ("addlik\t%2,r0,32", operands); -+ output_asm_insn ("addlik\t%2,%2,-1", operands); -+ output_asm_insn ("beaneid\t%2,.-8", operands); -+ output_asm_insn ("addlk\t%0,%0,%0", operands); -+ return "addlik\t%0,%0,%j1 #li => la"; - } - case 5: - return "sl%i0\t%1,%0"; -@@ -1790,11 +1859,21 @@ - "TARGET_MB_64" - { - ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) --if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) - { - emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); - DONE; - } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) -+ { -+ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) -+ { -+ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); -+ DONE; -+ } - else - FAIL; - } -@@ -1804,7 +1883,7 @@ else - [(set (match_operand:DI 0 "register_operand" "=d,d") - (ashift:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:DI 2 "arith_operand" "I,d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "@ - bsllli\t%0,%1,%2 - bslll\t%0,%1,%2" -@@ -1812,6 +1891,51 @@ else - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")] - ) -+ -+(define_insn "ashldi3_const" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("orli\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "addlk\t%0,%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "20")] -+) -+ -+(define_insn "ashldi3_reg" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashift:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("andli\t%3,%2,31", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,r0,%1", operands); -+ /* Exit the loop if zero shift. */ -+ output_asm_insn ("beaeqid\t%3,.+24", operands); -+ /* Emit the loop. */ -+ output_asm_insn ("addlk\t%0,%0,r0", operands); -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "addlk\t%0,%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "28")] -+) -+ - ;; The following patterns apply when there is no barrel shifter present - - (define_insn "*ashlsi3_with_mul_delay" -@@ -1945,11 +2069,21 @@ else - "TARGET_MB_64" - { - ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) --if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) - { - emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); - DONE; - } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) -+ { -+ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) -+ { -+ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); -+ DONE; -+ } - else - FAIL; - } -@@ -1959,7 +2093,7 @@ else - [(set (match_operand:DI 0 "register_operand" "=d,d") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:DI 2 "arith_operand" "I,d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "@ - bslrai\t%0,%1,%2 - bslra\t%0,%1,%2" -@@ -1967,6 +2101,51 @@ else - (set_attr "mode" "DI,DI") - (set_attr "length" "4,4")] - ) -+ -+(define_insn "ashrdi3_const" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("orli\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srla\t%0,%0"; -+ } -+ [(set_attr "type" "arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "20")] -+) -+ -+(define_insn "ashrdi3_reg" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("andli\t%3,%2,31", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,r0,%1", operands); -+ /* Exit the loop if zero shift. */ -+ output_asm_insn ("beaeqid\t%3,.+24", operands); -+ /* Emit the loop. */ -+ output_asm_insn ("addlk\t%0,%0,r0", operands); -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srla\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "28")] -+) -+ - (define_expand "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -@@ -2084,11 +2263,21 @@ else - "TARGET_MB_64" - { - ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) --if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) -+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) - { - emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); - DONE; - } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) -+ { -+ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); -+ DONE; -+ } -+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) -+ { -+ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); -+ DONE; -+ } - else - FAIL; - } -@@ -2098,7 +2287,7 @@ else - [(set (match_operand:DI 0 "register_operand" "=d,d") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") - (match_operand:DI 2 "arith_operand" "I,d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_BARREL_SHIFT" - "@ - bslrli\t%0,%1,%2 - bslrl\t%0,%1,%2" -@@ -2107,6 +2296,50 @@ else - (set_attr "length" "4,4")] - ) - -+(define_insn "lshrdi3_const" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ -+ output_asm_insn ("orli\t%3,r0,%2", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,%1,r0", operands); -+ -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srll\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "DI") -+ (set_attr "length" "20")] -+) -+ -+(define_insn "lshrdi3_reg" -+ [(set (match_operand:DI 0 "register_operand" "=&d") -+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "register_operand" "d")))] -+ "TARGET_MB_64" -+ { -+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); -+ output_asm_insn ("andli\t%3,%2,31", operands); -+ if (REGNO (operands[0]) != REGNO (operands[1])) -+ output_asm_insn ("addlk\t%0,r0,%1", operands); -+ /* Exit the loop if zero shift. */ -+ output_asm_insn ("beaeqid\t%3,.+24", operands); -+ /* Emit the loop. */ -+ output_asm_insn ("addlk\t%0,%0,r0", operands); -+ output_asm_insn ("addlik\t%3,%3,-1", operands); -+ output_asm_insn ("beaneid\t%3,.-8", operands); -+ return "srll\t%0,%0"; -+ } -+ [(set_attr "type" "multi") -+ (set_attr "mode" "SI") -+ (set_attr "length" "28")] -+) -+ - (define_expand "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=&d") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") -@@ -2233,7 +2466,7 @@ else - (eq:DI - (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" - "pcmpleq\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "DI") -@@ -2245,7 +2478,7 @@ else - (ne:DI - (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")))] -- "TARGET_MB_64" -+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" - "pcmplne\t%0,%1,%2" - [(set_attr "type" "arith") - (set_attr "mode" "DI") --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch deleted file mode 100644 index 98183053..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 688fcf782b7eca82cb2e2ab6589dee843983a5d6 Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Fri, 23 Aug 2019 16:16:53 +0530 -Subject: [PATCH 47/53] Added new MB-64 single register arithmetic instructions - ---- - gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 40328b0d39d..6bd042747bf 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -654,6 +654,18 @@ - } - }) - -+(define_insn "adddi3_int" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (plus:DI (match_operand:DI 1 "register_operand" "%0") -+ (match_operand:DI 2 "immediate_operand" "I")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ addlik\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")] -+) -+ - (define_insn "*adddi3_long" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (plus:DI (match_operand:DI 1 "register_operand" "%d,d") -@@ -719,6 +731,18 @@ - { - }") - -+(define_insn "subdi316imm" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (minus:DI (match_operand:DI 1 "register_operand" "d") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))" -+ "@ -+ addlik\t%0,-%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ -+ - (define_insn "subsidi3" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") -@@ -1015,6 +1039,17 @@ - ;; Logical - ;;---------------------------------------------------------------- - -+(define_insn "anddi3imm16" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (and:DI (match_operand:DI 1 "arith_operand" "%0") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ andli\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "anddi3" - [(set (match_operand:DI 0 "register_operand" "=d,d,d") - (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") -@@ -1042,6 +1077,16 @@ - (set_attr "mode" "SI,SI,SI,SI") - (set_attr "length" "4,8,8,8")]) - -+(define_insn "iordi3imm16" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (ior:DI (match_operand:DI 1 "arith_operand" "%0") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ orli\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) - - (define_insn "iordi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") -@@ -1069,6 +1114,17 @@ - (set_attr "mode" "SI,SI,SI,SI") - (set_attr "length" "4,8,8,8")]) - -+(define_insn "xordi3imm16" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (xor:DI (match_operand:DI 1 "arith_operand" "%0") -+ (match_operand:DI 2 "arith_operand" "K")))] -+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" -+ "@ -+ xorli\t%0,%2" -+ [(set_attr "type" "darith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "4")]) -+ - (define_insn "xordi3" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch deleted file mode 100644 index 29291154..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 9098a760a10f09fefbdf438daf63b9e36576c9b2 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 26 Aug 2019 15:55:22 +0530 -Subject: [PATCH 48/53] [Patch,MicroBlaze] : Added support for 64 bit Immediate - values. - ---- - gcc/config/microblaze/constraints.md | 4 ++-- - gcc/config/microblaze/microblaze.md | 3 +-- - 2 files changed, 3 insertions(+), 4 deletions(-) - -diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md -index e3f89491fb4..ef3001764c0 100644 ---- a/gcc/config/microblaze/constraints.md -+++ b/gcc/config/microblaze/constraints.md -@@ -53,9 +53,9 @@ - (match_test "ival > 0 && ival < 0x10000"))) - - (define_constraint "K" -- "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." -+ "A constant in the range -9223372036854775808 to 9223372036854775807 (inclusive)." - (and (match_code "const_int") -- (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) -+ (match_test "ival > (long long)-9223372036854775808 && ival < (long long)9223372036854775807"))) - - - ;; Define floating point constraints -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 6bd042747bf..b89a4276c7c 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1332,8 +1332,7 @@ - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") - (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] - "TARGET_MB_64 && (register_operand (operands[0], DImode) && -- (GET_CODE (operands[1]) == CONST_INT && -- (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" -+ (GET_CODE (operands[1]) == CONST_INT))" - "@ - addlk\t%0,r0,r0\t - addlik\t%0,r0,%1\t #N1 %X1 --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch deleted file mode 100644 index 163d4925..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 2673e0dc2d75769c7cc36ca94e4e07caa28b8ef7 Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Thu, 9 Jan 2020 12:30:41 +0530 -Subject: [PATCH 49/53] [Patch, microblaze]: Fix Compiler crash with - -freg-struct-return This patch fixes a bug in MB GCC regarding the passing - struct values in registers. Currently we are only handling SImode With this - patch all other modes are handled properly - -Signed-off-by :Nagaraju Mekala - -ChangeLog: -2020-01-09 Nagaraju Mekala - - * gcc/config/microblaze/microblaze.h - (LIBCALL_Value): Remove macro - (PROMOTE_MODE): Remove macro - * gcc/config/microblaze/microblaze.c - (TARGET_LIBCALL_Value): Added new macro - (microblaze_function_value): Updated the return Value ---- - gcc/config/microblaze/microblaze.c | 11 ++++++++++- - gcc/config/microblaze/microblaze.h | 19 ------------------- - 2 files changed, 10 insertions(+), 20 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index d1257032bfb..5afac2ba8d1 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3908,7 +3908,16 @@ microblaze_function_value (const_tree valtype, - const_tree func ATTRIBUTE_UNUSED, - bool outgoing ATTRIBUTE_UNUSED) - { -- return LIBCALL_VALUE (TYPE_MODE (valtype)); -+ return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN); -+} -+ -+#undef TARGET_LIBCALL_VALUE -+#define TARGET_LIBCALL_VALUE microblaze_libcall_value -+ -+rtx -+microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) -+{ -+ return gen_rtx_REG (mode, GP_RETURN); - } - - /* Implement TARGET_SCHED_ADJUST_COST. */ -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index c6c3a9baa5a..2581d52d17a 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe; - - #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND - --#ifndef __arch64__ --#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ -- if (GET_MODE_CLASS (MODE) == MODE_INT \ -- && GET_MODE_SIZE (MODE) < 4) \ -- (MODE) = SImode; --#endif -- - /* Standard register usage. */ - - /* On the MicroBlaze, we have 32 integer registers */ -@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info; - - #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS - --#ifdef __aarch64__ --#define LIBCALL_VALUE(MODE) \ -- gen_rtx_REG (MODE,GP_RETURN) --#else --#define LIBCALL_VALUE(MODE) \ -- gen_rtx_REG ( \ -- ((GET_MODE_CLASS (MODE) != MODE_INT \ -- || GET_MODE_SIZE (MODE) >= 4) \ -- ? (MODE) \ -- : SImode), GP_RETURN) --#endif -- - /* 1 if N is a possible register number for a function value. - On the MicroBlaze, R2 R3 are the only register thus used. - Currently, R2 are only implemented here (C has no complex type) */ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch deleted file mode 100644 index 37945b65..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 009fc9cbb72f50ac73b7f58153d0d90db46b48b8 Mon Sep 17 00:00:00 2001 -From: Nagaraju -Date: Wed, 8 May 2019 14:12:03 +0530 -Subject: [PATCH 50/53] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and - disable fivopts by default - -Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. - - * gcc/common/config/microblaze/microblaze-common.c - (microblaze_option_optimization_table): Disable fivopts by default. - -Signed-off-by: Nagaraju Mekala - -Conflicts: - gcc/common/config/microblaze/microblaze-common.c ---- - gcc/common/config/microblaze/microblaze-common.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c -index 1e4abb34027..d3a74fcc99e 100644 ---- a/gcc/common/config/microblaze/microblaze-common.c -+++ b/gcc/common/config/microblaze/microblaze-common.c -@@ -24,7 +24,18 @@ - #include "common/common-target.h" - #include "common/common-target-def.h" - -+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ -+static const struct default_options microblaze_option_optimization_table[] = -+ { -+ /* Turn off ivopts by default. It messes up cse. -+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */ -+ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, -+ { OPT_LEVELS_NONE, 0, NULL, 0 } -+ }; -+ - #undef TARGET_DEFAULT_TARGET_FLAGS - #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT - -+#undef TARGET_OPTION_OPTIMIZATION_TABLE -+#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch deleted file mode 100644 index 73b170c1..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch +++ /dev/null @@ -1,198 +0,0 @@ -From f52258e89f2ea416f418b6c55fef15552a081e18 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 24 Nov 2020 12:26:32 +0530 -Subject: [PATCH 51/53] [Patch, microblaze]: Reducing Stack space for arguments - -Currently in Microblaze target stack space for arguments in register is being -allocated even if there are no arguments in the function. -This patch will optimize the extra 24 bytes that are being allocated. - -Signed-off-by :Nagaraju Mekala - :Ajit Agarwal ---- - gcc/config/microblaze/microblaze-protos.h | 1 + - gcc/config/microblaze/microblaze.c | 132 +++++++++++++++++++++- - gcc/config/microblaze/microblaze.h | 4 +- - 3 files changed, 134 insertions(+), 3 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index 302f6bbda2e..87a7093e369 100644 ---- a/gcc/config/microblaze/microblaze-protos.h -+++ b/gcc/config/microblaze/microblaze-protos.h -@@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx); - extern int label_mentioned_p (rtx); - extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); - extern void microblaze_eh_return (rtx op0); -+int microblaze_reg_parm_stack_space(tree fun); - #endif /* RTX_CODE */ - - /* Declare functions in microblaze-c.c. */ -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 5afac2ba8d1..6914eb8380c 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2080,6 +2080,136 @@ microblaze_must_save_register (int regno) - return 0; - } - -+static bool -+microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type) -+{ -+ int unsignedp; -+ rtx entry_parm; -+ -+ /* Catch errors. */ -+ if (type == NULL || type == error_mark_node) -+ return true; -+ -+ if (TREE_CODE (type) == POINTER_TYPE) -+ return true; -+ -+ /* Handle types with no storage requirement. */ -+ if (TYPE_MODE (type) == VOIDmode) -+ return false; -+ -+ /* Handle complex types. */ -+ if (TREE_CODE (type) == COMPLEX_TYPE) -+ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)) -+ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))); -+ -+ /* Handle transparent aggregates. */ -+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE) -+ && TYPE_TRANSPARENT_AGGR (type)) -+ type = TREE_TYPE (first_field (type)); -+ -+ /* See if this arg was passed by invisible reference. */ -+ function_arg_info arg (type, /*named=*/true); -+ apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg); -+ -+ /* Find mode as it is passed by the ABI. */ -+ unsignedp = TYPE_UNSIGNED (type); -+ arg.mode = promote_mode (arg.type, arg.mode, &unsignedp); -+ -+ /* If there is no incoming register, we need a stack. */ -+ entry_parm = microblaze_function_arg (args_so_far, arg); -+ if (entry_parm == NULL) -+ return true; -+ -+ /* Likewise if we need to pass both in registers and on the stack. */ -+ if (GET_CODE (entry_parm) == PARALLEL -+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX) -+ return true; -+ -+ /* Also true if we're partially in registers and partially not. */ -+ if (function_arg_partial_bytes (args_so_far, arg) != 0) -+ return true; -+ -+ /* Update info on where next arg arrives in registers. */ -+ microblaze_function_arg_advance (args_so_far, arg); -+ return false; -+} -+ -+static bool -+microblaze_function_parms_need_stack (tree fun, bool incoming) -+{ -+ tree fntype, result; -+ CUMULATIVE_ARGS args_so_far_v; -+ cumulative_args_t args_so_far; -+ int num_of_args = 0; -+ -+ /* Must be a libcall, all of which only use reg parms. */ -+ if (!fun) -+ return true; -+ -+ fntype = fun; -+ if (!TYPE_P (fun)) -+ fntype = TREE_TYPE (fun); -+ -+ /* Varargs functions need the parameter save area. */ -+ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype)) -+ return true; -+ -+ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0); -+ args_so_far = pack_cumulative_args (&args_so_far_v); -+ -+ /* When incoming, we will have been passed the function decl. -+ * * It is necessary to use the decl to handle K&R style functions, -+ * * where TYPE_ARG_TYPES may not be available. */ -+ if (incoming) -+ { -+ gcc_assert (DECL_P (fun)); -+ result = DECL_RESULT (fun); -+ } -+ else -+ result = TREE_TYPE (fntype); -+ -+ if (result && aggregate_value_p (result, fntype)) -+ { -+ if (!TYPE_P (result)) -+ result = build_pointer_type (result); -+ microblaze_parm_needs_stack (args_so_far, result); -+ } -+ -+ if (incoming) -+ { -+ tree parm; -+ for (parm = DECL_ARGUMENTS (fun); -+ parm && parm != void_list_node; -+ parm = TREE_CHAIN (parm)) -+ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm))) -+ return true; -+ } -+ else -+ { -+ function_args_iterator args_iter; -+ tree arg_type; -+ -+ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter) -+ { -+ num_of_args; -+ if (microblaze_parm_needs_stack (args_so_far, arg_type)) -+ return true; -+ } -+ } -+ -+ if (num_of_args > 3) return true; -+ -+ return false; -+} -+ -+int microblaze_reg_parm_stack_space(tree fun) -+{ -+ if (microblaze_function_parms_need_stack (fun,false)) -+ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD; -+ else -+ return 0; -+} -+ - /* Return the bytes needed to compute the frame pointer from the current - stack pointer. - -@@ -3470,7 +3600,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, - emit_insn (gen_indirect_jump (temp2)); - - /* Run just enough of rest_of_compilation. This sequence was -- "borrowed" from rs6000.c. */ -+ "borrowed" from microblaze.c */ - insn = get_insns (); - shorten_branches (insn); - assemble_start_function (thunk_fndecl, fnname); -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 2581d52d17a..9c48978d2ca 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info; - #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 - #define DWARF_CIE_DATA_ALIGNMENT -1 - --#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) -+#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL) - --#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 -+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 - - #define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) - --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0052-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0052-Patch-MicroBlaze.patch deleted file mode 100644 index 293a7486..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0052-Patch-MicroBlaze.patch +++ /dev/null @@ -1,72 +0,0 @@ -From b0ea0d18d1b353421ef7e18d496fd505cb1d5f7d Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Wed, 28 Apr 2021 16:49:18 +0530 -Subject: [PATCH 52/53] [Patch,MicroBlaze] : If we use break_handler attribute - then interrupt vector call happened to break_handler instead of - interrupt_handler. this fix will resolve the issue CR-1081780 This fix will - not change the behavior of compiler unless there is a usage of break_handler - attribute. - ---- - gcc/config/microblaze/microblaze.c | 13 +++++-------- - 1 file changed, 5 insertions(+), 8 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 6914eb8380c..d0546a164d7 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2019,7 +2019,7 @@ microblaze_save_volatiles (tree func) - int - microblaze_is_interrupt_variant (void) - { -- return (interrupt_handler || fast_interrupt); -+ return (interrupt_handler || fast_interrupt || break_handler); - } - int - microblaze_is_break_handler (void) -@@ -2058,7 +2058,7 @@ microblaze_must_save_register (int regno) - { - if (df_regs_ever_live_p (regno) - || regno == MB_ABI_MSR_SAVE_REG -- || ((interrupt_handler || fast_interrupt) -+ || ((interrupt_handler || fast_interrupt || break_handler) - && (regno == MB_ABI_ASM_TEMP_REGNUM - || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM))) - return 1; -@@ -2274,9 +2274,6 @@ compute_frame_size (HOST_WIDE_INT size) - fast_interrupt = - microblaze_fast_interrupt_function_p (current_function_decl); - save_volatiles = microblaze_save_volatiles (current_function_decl); -- if (break_handler) -- interrupt_handler = break_handler; -- - gp_reg_size = 0; - mask = 0; - var_size = size; -@@ -3236,7 +3233,7 @@ microblaze_expand_prologue (void) - gen_rtx_PLUS (Pmode, stack_pointer_rtx, - const0_rtx)); - -- if (interrupt_handler) -+ if (interrupt_handler || break_handler) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; - -@@ -3347,12 +3344,12 @@ microblaze_expand_epilogue (void) - a load-use stall cycle :) This is also important to handle alloca. - (See comments for if (frame_pointer_needed) below. */ - -- if (!crtl->is_leaf || interrupt_handler) -+ if (!crtl->is_leaf || interrupt_handler || break_handler) - { - mem_rtx = - gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); -- if (interrupt_handler) -+ if (interrupt_handler || break_handler) - /* Do not optimize in flow analysis. */ - MEM_VOLATILE_P (mem_rtx) = 1; - reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0053-patch-microblaze64-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0053-patch-microblaze64-Add-Zero_extended-instructions.patch deleted file mode 100644 index 76148d15..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0053-patch-microblaze64-Add-Zero_extended-instructions.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 7c9402f1dc641a1fe4110e92cd16a33ed4bd35cf Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Mon, 30 Aug 2021 12:13:45 +0530 -Subject: [PATCH 53/53] [patch, microblaze64]: Add Zero_extended instructions - -Due to latest changes in GCC-10.2 MB64 perforamance has reduced -We have added zero_extended instructions to get rid of left shift -and right shift loops - -[CR/TSR]: TSR-974519 - -Signed-off-by: Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.md | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index b89a4276c7c..ee078b0152a 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1191,6 +1191,33 @@ - (set_attr "mode" "SI,SI,SI") - (set_attr "length" "4,4,8")]) - -+(define_insn "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0xffff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ -+(define_insn "zero_extendsidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0xffffffff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ -+(define_insn "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0x00ff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ - ;;---------------------------------------------------------------- - ;; Sign extension - ;;---------------------------------------------------------------- --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/microblaze-mulitlib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/microblaze-mulitlib-hack.patch deleted file mode 100644 index af8ebf3b..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-11/microblaze-mulitlib-hack.patch +++ /dev/null @@ -1,58 +0,0 @@ -Microblaze Mulitlib hack - -Based on the patch: - -From c2081c51db589471ea713870c72f13999abda815 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Mar 2013 09:10:06 +0400 -Subject: [PATCH 04/36] 64-bit multilib hack. - -GCC has internal multilib handling code but it assumes a very specific rigid directory -layout. The build system implementation of multilib layout is very generic and allows -complete customisation of the library directories. - -This patch is a partial solution to allow any custom directories to be passed into gcc -and handled correctly. It forces gcc to use the base_libdir (which is the current -directory, "."). We need to do this for each multilib that is configured as we don't -know which compiler options may be being passed into the compiler. Since we have a compiler -per mulitlib at this point that isn't an issue. - -The one problem is the target compiler is only going to work for the default multlilib at -this point. Ideally we'd figure out which multilibs were being enabled with which paths -and be able to patch these entries with a complete set of correct paths but this we -don't have such code at this point. This is something the target gcc recipe should do -and override these platform defaults in its build config. - -Do same for riscv64 and aarch64 - -RP 15/8/11 - -Upstream-Status: Inappropriate[OE-Specific] - -Signed-off-by: Khem Raj -Signed-off-by: Elvis Dowson -Signed-off-by: Mark Hatle -Signed-off-by: Mark Hatle - -Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze -=================================================================== ---- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze -+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze -@@ -1,5 +1,6 @@ - MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high --MULTILIB_DIRNAMES = m64 bs le m mh -+#MULTILIB_DIRNAMES = m64 bs le m mh -+MULTILIB_DIRNAMES = . . . . . - MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high - MULTILIB_EXCEPTIONS += *m64 - MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift -Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux -=================================================================== ---- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze-linux -+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux -@@ -1,3 +1,4 @@ - MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high --MULTILIB_DIRNAMES = bs m mh -+#MULTILIB_DIRNAMES = bs m mh -+MULTILIB_DIRNAMES = . . . - MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch new file mode 100644 index 00000000..9750cee8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch @@ -0,0 +1,35 @@ +From 89825e41d91ef04532a7a53d72f4eb33ad40d1d9 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 13:13:57 +0530 +Subject: [PATCH 01/53] LOCAL]: Testsuite - builtins tests require fpic + Signed-off-by: David Holsgrove + +Conflicts: + + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index baec137d9a3..ad62a7348bc 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + ++<<<<<<< HEAD ++======= ++if [istarget "microblaze*-*-linux*"] { ++ lappend additional_flags "-Wl,-zmuldefs" ++ lappend additional_flags "-fPIC" ++} ++ ++>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch new file mode 100644 index 00000000..bfb98bcd --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch @@ -0,0 +1,31 @@ +From 997e53fc324c3414d09a883a7bff28e1e346c847 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 14:31:10 +0530 +Subject: [PATCH 02/53] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This + particular testcase fails with a timeout. Instead, fail it at compile-time + for microblaze. This speeds up the testsuite without removing it from the + FAIL reports. + +Signed-off-by: Edgar E. Iglesias +--- + gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C +index 3862756083d..db9f990f781 100644 +--- a/gcc/testsuite/g++.dg/opt/memcpy1.C ++++ b/gcc/testsuite/g++.dg/opt/memcpy1.C +@@ -4,6 +4,10 @@ + // { dg-do compile } + // { dg-options "-O" } + ++#if defined (__MICROBLAZE__) ++#error "too slow on mb. Investigate." ++#endif ++ + typedef unsigned char uint8_t; + typedef uint8_t uint8; + __extension__ typedef __SIZE_TYPE__ size_t; +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch new file mode 100644 index 00000000..6a4b907a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch @@ -0,0 +1,35 @@ +From 66fb54b40c49c86e8cefa94523a3f65a6779d6f2 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 15:46:28 +0530 +Subject: [PATCH 03/53] [LOCAL]: For dejagnu static testing on qemu, suppress + warnings about multiple definitions from the test function and libc in line + with method used by powerpc. Dynamic linking and using a qemu binary which + understands sysroot resolves all test failures with builtins + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index ad62a7348bc..3a38fb1de91 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + +-<<<<<<< HEAD +-======= + if [istarget "microblaze*-*-linux*"] { + lappend additional_flags "-Wl,-zmuldefs" +- lappend additional_flags "-fPIC" + } + +->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch new file mode 100644 index 00000000..0d907474 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch @@ -0,0 +1,35 @@ +From dd488cfaf9f909462290c85a1e30665f6252cbf1 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 15:50:35 +0530 +Subject: [PATCH 04/53] [Patch, testsuite]: Add MicroBlaze to target-supports + for atomic buil. .tin tests + +MicroBlaze added to supported targets for atomic builtin tests. + +Changelog/testsuite + +2014-02-14 David Holsgrove + + * gcc/testsuite/lib/target-supports.exp: Add microblaze to + check_effective_target_sync_int_long. + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/lib/target-supports.exp | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 411e559f508..9e6a1480e8f 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -7958,6 +7958,7 @@ proc check_effective_target_sync_int_long { } { + && [check_effective_target_arm_acq_rel]) + || [istarget bfin*-*linux*] + || [istarget hppa*-*linux*] ++ || [istarget microblaze*-*linux*] + || [istarget s390*-*-*] + || [istarget powerpc*-*-*] + || [istarget cris-*-*] +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch new file mode 100644 index 00000000..1714c142 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch @@ -0,0 +1,36 @@ +From 5576c4ca7641833a91b19b36d105a6b852c1a0cc Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 11 Jan 2017 16:20:01 +0530 +Subject: [PATCH 05/53] [Patch, testsuite]: Update MicroBlaze strings test for + new scan-assembly output resulting in use of $LC label + +ChangeLog/testsuite + +2014-02-14 David Holsgrove + + * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update + to include $LC label. + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/gcc.target/microblaze/others/strings1.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c +index efaf3c660ea..347872360d3 100644 +--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c ++++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c +@@ -3,6 +3,10 @@ + /* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ + /* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ + ++/* { dg-final { scan-assembler "\.rodata*" } } */ ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */ ++/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */ ++ + #include + + extern void somefunc (char *); +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch new file mode 100644 index 00000000..def6e95e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch @@ -0,0 +1,67 @@ +From ea6a9f11d6a866fe20cca13d06c7386754543e6c Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:14:15 +0530 +Subject: [PATCH 06/53] [Patch, testsuite]: Allow MicroBlaze .weakext pattern + in regex match Extend regex pattern to include optional ext at the end of + .weak to match the MicroBlaze weak label .weakext + +ChangeLog/testsuite + +2014-02-14 David Holsgrove + + * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler + pattern to take optional ext after .weak. + * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. + +Signed-off-by: David Holsgrove + +Conflicts: + + gcc/testsuite/g++.dg/abi/rtti3.C +--- + gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++-- + gcc/testsuite/g++.dg/abi/thunk3.C | 2 +- + gcc/testsuite/g++.dg/abi/thunk4.C | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C +index 0cc7d3e79d0..f284cd9255c 100644 +--- a/gcc/testsuite/g++.dg/abi/rtti3.C ++++ b/gcc/testsuite/g++.dg/abi/rtti3.C +@@ -3,8 +3,8 @@ + + // { dg-require-weak "" } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } +-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } } +-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } + // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } } + // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } } + +diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C +index f2347f79ecd..dcec8a771a1 100644 +--- a/gcc/testsuite/g++.dg/abi/thunk3.C ++++ b/gcc/testsuite/g++.dg/abi/thunk3.C +@@ -1,5 +1,5 @@ + // { dg-require-weak "" } +-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } + // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } + + struct Base +diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C +index 6e8f124bc5e..d1d34fe1e4a 100644 +--- a/gcc/testsuite/g++.dg/abi/thunk4.C ++++ b/gcc/testsuite/g++.dg/abi/thunk4.C +@@ -1,6 +1,6 @@ + // { dg-require-weak "" } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } +-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } ++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } + // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } + + struct Base +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch new file mode 100644 index 00000000..5f72ecd2 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch @@ -0,0 +1,28 @@ +From fe007d78e220606b220dfc452fe9564ebfecd57a Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:34:27 +0530 +Subject: [PATCH 07/53] [Patch, testsuite]: Add MicroBlaze to + check_profiling_available Testsuite, add microblaze*-*-* target in + check_profiling_available inline with other archs setting + profiling_available_saved to 0 + +Signed-off-by: David Holsgrove +--- + gcc/testsuite/lib/target-supports.exp | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 9e6a1480e8f..7e9d0889f76 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -727,6 +727,7 @@ proc check_profiling_available { test_what } { + || [istarget m68k-*-elf] + || [istarget m68k-*-uclinux*] + || [istarget mips*-*-elf*] ++ || [istarget microblaze*-*-*] + || [istarget mmix-*-*] + || [istarget mn10300-*-elf*] + || [istarget moxie-*-elf*] +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch new file mode 100644 index 00000000..78dc5dcd --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0008-Patch-microblaze-Fix-atomic-side-effects.patch @@ -0,0 +1,68 @@ +From 63b07793addb119dfc3ec0a30225e767d8f48706 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:41:43 +0530 +Subject: [PATCH 08/53] [Patch, microblaze]: Fix atomic side effects. In + atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions + during optimization. Previously, the outputs were considered unused; this + generated assembly code with undefined side effects after invocation of the + atomic. + +Signed-off-by: Kirk Meyer +Signed-off-by: David Holsgrove + +Conflicts: + gcc/config/microblaze/microblaze.md +--- + gcc/config/microblaze/microblaze.md | 3 +++ + gcc/config/microblaze/sync.md | 21 +++++++++++++-------- + 2 files changed, 16 insertions(+), 8 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 472ef4c1d8d..b02034c9f1e 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -43,6 +43,9 @@ + (UNSPEC_TLS 106) ;; jump table + (UNSPEC_SET_TEXT 107) ;; set text start + (UNSPEC_TEXT 108) ;; data text relative ++ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool) ++ (UNSPECV_CAS_VAL 202) ;; compare and swap (val) ++ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem) + ]) + + (define_c_enum "unspec" [ +diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md +index 23e0f1c52e2..3b0fba1d3cf 100644 +--- a/gcc/config/microblaze/sync.md ++++ b/gcc/config/microblaze/sync.md +@@ -18,14 +18,19 @@ + ;; . + + (define_insn "atomic_compare_and_swapsi" +- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output +- (match_operand:SI 1 "register_operand" "=&d") ;; val output +- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory +- (match_operand:SI 3 "register_operand" "d") ;; expected value +- (match_operand:SI 4 "register_operand" "d") ;; desired value +- (match_operand:SI 5 "const_int_operand" "") ;; is_weak +- (match_operand:SI 6 "const_int_operand" "") ;; mod_s +- (match_operand:SI 7 "const_int_operand" "") ;; mod_f ++ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output ++ (unspec_volatile:SI ++ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory ++ (match_operand:SI 3 "register_operand" "d") ;; expected value ++ (match_operand:SI 4 "register_operand" "d")] ;; desired value ++ UNSPECV_CAS_BOOL)) ++ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL)) ++ (set (match_dup 2) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM)) ++ (match_operand:SI 5 "const_int_operand" "") ;; is_weak ++ (match_operand:SI 6 "const_int_operand" "") ;; mod_s ++ (match_operand:SI 7 "const_int_operand" "") ;; mod_f + (clobber (match_scratch:SI 8 "=&d"))] + "" + { +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch new file mode 100644 index 00000000..824b031c --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch @@ -0,0 +1,40 @@ +From 0aa9647936673e3ff1ac0082144b196309916ddb Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:45:45 +0530 +Subject: [PATCH 09/53] [Patch, microblaze]: Fix atomic boolean return value. + In atomic_compare_and_swapsi, fix boolean return value. Previously, it + contained zero if successful and non-zero if unsuccessful. + +Signed-off-by: Kirk Meyer +Signed-off-by: David Holsgrove +--- + gcc/config/microblaze/sync.md | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md +index 3b0fba1d3cf..d08400af4bb 100644 +--- a/gcc/config/microblaze/sync.md ++++ b/gcc/config/microblaze/sync.md +@@ -34,15 +34,16 @@ + (clobber (match_scratch:SI 8 "=&d"))] + "" + { +- output_asm_insn ("addc \tr0,r0,r0", operands); ++ output_asm_insn ("add \t%0,r0,r0", operands); + output_asm_insn ("lwx \t%1,%y2,r0", operands); + output_asm_insn ("addic\t%8,r0,0", operands); + output_asm_insn ("bnei \t%8,.-8", operands); +- output_asm_insn ("cmp \t%0,%1,%3", operands); +- output_asm_insn ("bnei \t%0,.+16", operands); ++ output_asm_insn ("cmp \t%8,%1,%3", operands); ++ output_asm_insn ("bnei \t%8,.+20", operands); + output_asm_insn ("swx \t%4,%y2,r0", operands); + output_asm_insn ("addic\t%8,r0,0", operands); + output_asm_insn ("bnei \t%8,.-28", operands); ++ output_asm_insn ("addi \t%0,r0,1", operands); + return ""; + } + ) +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch new file mode 100644 index 00000000..a1896298 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch @@ -0,0 +1,33 @@ +From a950e2d4fb15e9ebabe11a5606f24a510f297d6d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:50:17 +0530 +Subject: [PATCH 10/53] [Patch, microblaze]: Fix the Microblaze crash with + msmall-divides flag Compiler is crashing when we use msmall-divides and + mxl-barrel-shift flag. This is because when use above flags + microblaze_expand_divide function will be called for division operation. In + microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't + have subreg register due to this compiler was crashing. Changed the logic to + avoid sub_reg call + +Signed-off-by:Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index b444db17719..45405fa2160 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3709,8 +3709,7 @@ microblaze_expand_divide (rtx operands[]) + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); + +- insn = emit_insn (gen_movqi (regqi, mem_rtx)); +- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); ++ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch new file mode 100644 index 00000000..597e4e6e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch @@ -0,0 +1,48 @@ +From 3c984648f42e5fcf586c4327f108486fb8630f0d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 16:52:56 +0530 +Subject: [PATCH 11/53] [Patch, microblaze]: Added ashrsi3_with_size_opt Added + ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os + optimization is used. lshrsi3_with_size_opt is being removed as it has + conflicts with unsigned int variables + +Signed-off-by:Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index b02034c9f1e..55477fd0a69 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1508,6 +1508,27 @@ + (set_attr "length" "4,4")] + ) + ++(define_insn "*ashrsi3_with_size_opt" ++ [(set (match_operand:SI 0 "register_operand" "=&d") ++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "immediate_operand" "I")))] ++ "(INTVAL (operands[2]) > 5 && optimize_size)" ++ { ++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("ori\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addik\t%3,%3,-1", operands); ++ output_asm_insn ("bneid\t%3,.-4", operands); ++ return "sra\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "20")] ++) ++ + (define_insn "*ashrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch new file mode 100644 index 00000000..917b6d70 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch @@ -0,0 +1,26 @@ +From fa6e9e4317f9adb0748ade5029cbe3a10504ab54 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 10:57:19 +0530 +Subject: [PATCH 12/53] [Patch, microblaze]: Use bralid for profiler calls + Signed-off-by: Edgar E. Iglesias + +--- + gcc/config/microblaze/microblaze.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 2ecec750526..e32ce7dbb51 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -486,7 +486,7 @@ typedef struct microblaze_args + + #define FUNCTION_PROFILER(FILE, LABELNO) { \ + { \ +- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \ ++ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \ + } \ + } + +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch new file mode 100644 index 00000000..0891750a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0013-Patch-microblaze-Removed-moddi3-routinue.patch @@ -0,0 +1,160 @@ +From a5b58621655fa306c37157dfe3092547adce0aab Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 12 Jan 2017 17:36:16 +0530 +Subject: [PATCH 13/53] [Patch, microblaze]: Removed moddi3 routinue Using the + default moddi3 function as the existing implementation has many bugs + +Signed-off-by:Nagaraju + +Conflicts: + libgcc/config/microblaze/moddi3.S +--- + libgcc/config/microblaze/moddi3.S | 121 -------------------------- + libgcc/config/microblaze/t-microblaze | 3 +- + 2 files changed, 1 insertion(+), 123 deletions(-) + delete mode 100644 libgcc/config/microblaze/moddi3.S + +diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S +deleted file mode 100644 +index 4bac960107e..00000000000 +--- a/libgcc/config/microblaze/moddi3.S ++++ /dev/null +@@ -1,121 +0,0 @@ +-################################### +-# +-# Copyright (C) 2009-2021 Free Software Foundation, Inc. +-# +-# Contributed by Michael Eager . +-# +-# This file is free software; you can redistribute it and/or modify it +-# under the terms of the GNU General Public License as published by the +-# Free Software Foundation; either version 3, or (at your option) any +-# later version. +-# +-# GCC is distributed in the hope that it will be useful, but WITHOUT +-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-# License for more details. +-# +-# Under Section 7 of GPL version 3, you are granted additional +-# permissions described in the GCC Runtime Library Exception, version +-# 3.1, as published by the Free Software Foundation. +-# +-# You should have received a copy of the GNU General Public License and +-# a copy of the GCC Runtime Library Exception along with this program; +-# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +-# . +-# +-# modsi3.S +-# +-# modulo operation for 64 bit integers. +-# +-####################################### +- +- +-/* An executable stack is *not* required for these functions. */ +-#ifdef __linux__ +-.section .note.GNU-stack,"",%progbits +-.previous +-#endif +- +- .globl __moddi3 +- .ent __moddi3 +-__moddi3: +- .frame r1,0,r15 +- +-#Change the stack pointer value and Save callee saved regs +- addik r1,r1,-24 +- swi r25,r1,0 +- swi r26,r1,4 +- swi r27,r1,8 # used for sign +- swi r28,r1,12 # used for loop count +- swi r29,r1,16 # Used for div value High +- swi r30,r1,20 # Used for div value Low +- +-#Check for Zero Value in the divisor/dividend +- OR r9,r5,r6 # Check for the op1 being zero +- BEQID r9,$LaResult_Is_Zero # Result is zero +- OR r9,r7,r8 # Check for the dividend being zero +- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error +- BGEId r5,$La1_Pos +- XOR r27,r5,r7 # Get the sign of the result +- RSUBI r6,r6,0 # Make dividend positive +- RSUBIC r5,r5,0 # Make dividend positive +-$La1_Pos: +- BGEI r7,$La2_Pos +- RSUBI r8,r8,0 # Make Divisor Positive +- RSUBIC r9,r9,0 # Make Divisor Positive +-$La2_Pos: +- ADDIK r4,r0,0 # Clear mod low +- ADDIK r3,r0,0 # Clear mod high +- ADDIK r29,r0,0 # clear div high +- ADDIK r30,r0,0 # clear div low +- ADDIK r28,r0,64 # Initialize the loop count +- # First part try to find the first '1' in the r5/r6 +-$LaDIV1: +- ADD r6,r6,r6 +- ADDC r5,r5,r5 # left shift logical r5 +- BGEID r5,$LaDIV1 +- ADDIK r28,r28,-1 +-$LaDIV2: +- ADD r6,r6,r6 +- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry +- ADDC r4,r4,r4 # Move that bit into the Mod register +- ADDC r3,r3,r3 # Move carry into high mod register +- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor +- bnei r18,$L_High_EQ +- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h] +-$L_High_EQ: +- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L] +- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H] +- BLTi r25,$LaMOD_TOO_SMALL +- OR r3,r0,r25 # move r25 to mod [h] +- OR r4,r0,r26 # move r26 to mod [l] +- ADDI r30,r30,1 +- ADDC r29,r29,r0 +-$LaMOD_TOO_SMALL: +- ADDIK r28,r28,-1 +- BEQi r28,$LaLOOP_END +- ADD r30,r30,r30 # Shift in the '1' into div [low] +- ADDC r29,r29,r29 # Move the carry generated into high +- BRI $LaDIV2 # Div2 +-$LaLOOP_END: +- BGEI r27,$LaRETURN_HERE +- rsubi r30,r30,0 +- rsubc r29,r29,r0 +- BRI $LaRETURN_HERE +-$LaDiv_By_Zero: +-$LaResult_Is_Zero: +- or r29,r0,r0 # set result to 0 [High] +- or r30,r0,r0 # set result to 0 [Low] +-$LaRETURN_HERE: +-# Restore values of CSRs and that of r29 and the divisor and the dividend +- +- lwi r25,r1,0 +- lwi r26,r1,4 +- lwi r27,r1,8 +- lwi r28,r1,12 +- lwi r29,r1,16 +- lwi r30,r1,20 +- rtsd r15,8 +- addik r1,r1,24 +- .end __moddi3 +- +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 96959f0292b..8d954a49575 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,8 +1,7 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ +- $(srcdir)/config/microblaze/moddi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ + $(srcdir)/config/microblaze/muldi3_hard.S \ + $(srcdir)/config/microblaze/mulsi3.S \ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch new file mode 100644 index 00000000..cbee1692 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch @@ -0,0 +1,101 @@ +From a9abf680767f4294177d716cd95a9bec5c7916a7 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 14:41:58 +0530 +Subject: [PATCH 14/53] [Patch, microblaze]: Add INIT_PRIORITY support Added + TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. + +These macros allows users to control the order of initialization +of objects defined at namespace scope with the init_priority +attribute by specifying a relative priority, a constant integral +expression currently bounded between 101 and 65535 inclusive. + +Lower numbers indicate a higher priority. + +Changelog + +2013-11-26 Nagaraju Mekala + + * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor, + microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and + TARGET_ASM_DESTRUCTOR. + +Signed-off-by:nagaraju +Signed-off-by: David Holsgrove +--- + gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++ + 1 file changed, 53 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 45405fa2160..62630aab64e 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2634,6 +2634,53 @@ print_operand_address (FILE * file, rtx addr) + } + } + ++/* Output an element in the table of global constructors. */ ++void ++microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) ++{ ++ const char *section = ".ctors"; ++ char buf[16]; ++ ++ if (priority != DEFAULT_INIT_PRIORITY) ++ { ++ sprintf (buf, ".ctors.%.5u", ++ /* Invert the numbering so the linker puts us in the proper ++ order; constructors are run from right to left, and the ++ linker sorts in increasing order. */ ++ MAX_INIT_PRIORITY - priority); ++ section = buf; ++ } ++ ++ switch_to_section (get_section (section, 0, NULL)); ++ assemble_align (POINTER_SIZE); ++ fputs ("\t.word\t", asm_out_file); ++ output_addr_const (asm_out_file, symbol); ++ fputs ("\n", asm_out_file); ++} ++ ++/* Output an element in the table of global destructors. */ ++void ++microblaze_asm_destructor (rtx symbol, int priority) ++{ ++ const char *section = ".dtors"; ++ char buf[16]; ++ if (priority != DEFAULT_INIT_PRIORITY) ++ { ++ sprintf (buf, ".dtors.%.5u", ++ /* Invert the numbering so the linker puts us in the proper ++ order; constructors are run from right to left, and the ++ linker sorts in increasing order. */ ++ MAX_INIT_PRIORITY - priority); ++ section = buf; ++ } ++ ++ switch_to_section (get_section (section, 0, NULL)); ++ assemble_align (POINTER_SIZE); ++ fputs ("\t.word\t", asm_out_file); ++ output_addr_const (asm_out_file, symbol); ++ fputs ("\n", asm_out_file); ++} ++ + /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol + is used, so that we don't emit an .extern for it in + microblaze_asm_file_end. */ +@@ -3975,6 +4022,12 @@ microblaze_starting_frame_offset (void) + #undef TARGET_ATTRIBUTE_TABLE + #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table + ++#undef TARGET_ASM_CONSTRUCTOR ++#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor ++ ++#undef TARGET_ASM_DESTRUCTOR ++#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor ++ + #undef TARGET_IN_SMALL_DATA_P + #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p + +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch new file mode 100644 index 00000000..42d836cb --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0015-Patch-microblaze-Add-optimized-lshrsi3.patch @@ -0,0 +1,81 @@ +From fe3572f4b0cc033db305b0d67abb88632bf13887 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 15:23:57 +0530 +Subject: [PATCH 15/53] [Patch, microblaze]: Add optimized lshrsi3 When barrel + shifter is not present, the immediate value is greater than #5 and + optimization is -OS, the compiler will generate shift operation using loop. + +Changelog + +2013-11-26 David Holsgrove + + * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn + +ChangeLog/testsuite + +2014-02-12 David Holsgrove + + * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. + +Signed-off-by:Nagaraju +Signed-off-by: David Holsgrove +--- + gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++ + .../microblaze/others/lshrsi_Os_1.c | 13 ++++++++++++ + 2 files changed, 34 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 55477fd0a69..f85d8fcac8a 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1618,6 +1618,27 @@ + (set_attr "length" "4,4")] + ) + ++(define_insn "*lshrsi3_with_size_opt" ++ [(set (match_operand:SI 0 "register_operand" "=&d") ++ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "immediate_operand" "I")))] ++ "(INTVAL (operands[2]) > 5 && optimize_size)" ++ { ++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("ori\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addik\t%3,%3,-1", operands); ++ output_asm_insn ("bneid\t%3,.-4", operands); ++ return "srl\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "SI") ++ (set_attr "length" "20")] ++) ++ + (define_insn "*lshrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") +diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c +new file mode 100644 +index 00000000000..32a3be7c76a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c +@@ -0,0 +1,13 @@ ++/* { dg-options "-Os -mno-xl-barrel-shift" } */ ++ ++void testfunc(void) ++{ ++ unsigned volatile int z = 8192; ++ z >>= 8; ++} ++/* { dg-final { scan-assembler-not "\bsrli" } } */ ++/* { dg-final { scan-assembler "\ori\tr18,r0" } } */ ++/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */ ++/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */ ++/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ ++/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch new file mode 100644 index 00000000..3ee98b39 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0016-Patch-microblaze-Add-cbranchsi4_reg.patch @@ -0,0 +1,147 @@ +From 3ace42f94961162022e9e7baf3e3509fc1a1bfa4 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 17:04:37 +0530 +Subject: [PATCH 16/53] [Patch, microblaze]: Add cbranchsi4_reg This patch + optimizes the generation of pcmpne/pcmpeq instruction if the compare + instruction has no immediate values.For the immediate values the xor + instruction is generated + +Signed-off-by: Nagaraju Mekala +Signed-off-by: Ajit Agarwal + +ChangeLog: +2015-01-13 Nagaraju Mekala + Ajit Agarwal + + *microblaze.md (cbranchsi4_reg): New + *microblaze.c (microblaze_expand_conditional_branch_reg): New + +Conflicts: + + gcc/config/microblaze/microblaze-protos.h +--- + gcc/config/microblaze/microblaze-protos.h | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++------- + gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------ + 7 files changed, 18 insertions(+), 18 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index 54c26969fbd..3a5f439703c 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *); + extern bool microblaze_expand_move (machine_mode, rtx *); + extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); + extern void microblaze_expand_divide (rtx *); +-extern void microblaze_expand_conditional_branch (machine_mode, rtx *); ++extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); + extern int microblaze_can_use_return_insn (void); +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +index 4041a241391..ccc6a461cd9 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 <= f3) +- print ("le"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +index 3902b839db9..1dd5fe6c539 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 < f3) +- print ("lt"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +index 8555974dda5..d6f80fb0ec3 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 == f3) +- print ("eq"); ++ f1 = f2 + f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +index 79cc5f9dd8e..d1177249552 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3) + /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if(f1==f2 && f1<=f3) +- print ("f1 eq f2 && f1 le f3"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +index ebfb170ecee..75822977ef8 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +@@ -5,17 +5,17 @@ volatile float f1, f2, f3; + void float_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ +- if (f2 <= f3) +- print ("le"); ++ if (f2 <= f3) ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +index 1d6ba807b12..532c035adfd 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +@@ -74,16 +74,16 @@ void float_cmp_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ + if (f2 <= f3) +- print ("le"); ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch new file mode 100644 index 00000000..dcc8b6af --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch @@ -0,0 +1,58 @@ +From 2c68b0e5e0307019207e54d1f2d1565053f2e50f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 17:11:04 +0530 +Subject: [PATCH 17/53] [Patch,microblaze]: Inline Expansion of fsqrt builtin. + The changes are made in the patch for the inline expansion of the fsqrt + builtin with fqrt instruction. The sqrt math function takes double as + argument and return double as argument. The pattern is selected while + expanding the unary op through expand_unop which passes DFmode and the DFmode + pattern was not there returning zero. Thus the sqrt math function is not + inlined and expanded. The pattern with DFmode argument is added. Also the + source and destination argument is not same the DF through two different + consecutive registers with lower 32 bit is the argument passed to sqrt and + the higher 32 bit is zero. If the source and destinations are different the + DFmode 64 bits registers is not set properly giving the problem in runtime. + Such changes are taken care in the implementation of the pattern for DFmode + for inline expansion of the sqrt. + +ChangeLog: +2015-06-16 Ajit Agarwal + Nagaraju Mekala + + * config/microblaze/microblaze.md (sqrtdf2): New + pattern. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com + Nagaraju Mekala nmekala@xilinx.com +--- + gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index f85d8fcac8a..254221482af 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -451,6 +451,20 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" ++ { ++ if (REGNO (operands[0]) == REGNO (operands[1])) ++ return "fsqrt\t%0,%1"; ++ else ++ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; ++ } ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch new file mode 100644 index 00000000..4aa51cc9 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch @@ -0,0 +1,63 @@ +From 9eb2e41cedc278eb16e20383b6c8caad2ce22138 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 18:07:24 +0530 +Subject: [PATCH 18/53] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' + insn definitions Change adddi3 to handle DI immediates as the second operand, + this requires modification to the output template however reduces the need to + specify seperate templates for 16-bit positive/negative immediate operands. + The use of 32-bit immediates for the addi and addic instructions is handled + by the assembler, which will emit the imm instructions when required. This + conveniently handles the optimizable cases where the immediate constant value + does not need the higher half words of the operands upper/lower words. + +Change the constraints of the subdi3 instruction definition such that it +does not match the second operand as an immediate value. This is because +there is no definition to handle this case nor is it possible to +implement purely with instructions as microblaze does not provide an +instruction to perform a forward arithmetic subtraction (it only +provides reverse 'rD = IMM - rA'). + +Signed-off-by: Nathan Rossi +--- + gcc/config/microblaze/microblaze.md | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 254221482af..d86a049355a 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -502,17 +502,16 @@ + ;; Adding 2 DI operands in register or reg/imm + + (define_insn "adddi3" +- [(set (match_operand:DI 0 "register_operand" "=d,d,d") +- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d") +- (match_operand:DI 2 "arith_operand32" "d,P,N")))] ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") ++ (match_operand:DI 2 "arith_operand" "d,i")))] + "" + "@ + add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 +- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0 +- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1" ++ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" + [(set_attr "type" "darith") + (set_attr "mode" "DI") +- (set_attr "length" "8,8,12")]) ++ (set_attr "length" "8,8")]) + + ;;---------------------------------------------------------------- + ;; Subtraction +@@ -549,7 +548,7 @@ + (define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") +- (match_operand:DI 2 "arith_operand32" "d")))] ++ (match_operand:DI 2 "register_operand" "d")))] + "" + "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" + [(set_attr "type" "darith") +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch new file mode 100644 index 00000000..b67d8424 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch @@ -0,0 +1,72 @@ +From abef7f4d2ad2869c37c4fb2666b52ed700384877 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 17 Jan 2017 18:18:41 +0530 +Subject: [PATCH 19/53] [Patch, microblaze]: Update ashlsi3 & movsf patterns + This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand + of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal + patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our + instruction doesn't support so using gen_int_mode function + +Signed-off-by :Nagaraju Mekala + :Ajit Agarwal + +ChangeLog: +2016-01-07 Nagaraju Mekala + Ajit Agarwal + + *microblaze.md (ashlsi3_with_mul_nodelay, + ashlsi3_with_mul_delay, + movsf_internal): + Updated the patterns to use gen_int_mode function + *microblaze.c (print_operand): + updated the 'F' case to use "unsinged int" instead + of HOST_WIDE_INT_PRINT_HEX +--- + gcc/config/microblaze/microblaze.c | 2 +- + gcc/config/microblaze/microblaze.md | 10 ++++++++-- + 2 files changed, 9 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 62630aab64e..16f3120e415 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2468,7 +2468,7 @@ print_operand (FILE * file, rtx op, int letter) + unsigned long value_long; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), + value_long); +- fprintf (file, "0x%lx", value_long); ++ fprintf (file, "0x%08x", (unsigned int) value_long); + } + else + { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index d86a049355a..986c78f592a 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1368,7 +1368,10 @@ + (match_operand:SI 2 "immediate_operand" "I")))] + "!TARGET_SOFT_MUL + && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)" +- "muli\t%0,%1,%m2" ++ { ++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); ++ return "muli\t%0,%1,%2"; ++ } + ;; This MUL will not generate an imm. Can go into a delay slot. + [(set_attr "type" "arith") + (set_attr "mode" "SI") +@@ -1380,7 +1383,10 @@ + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "!TARGET_SOFT_MUL" +- "muli\t%0,%1,%m2" ++ { ++ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode); ++ return "muli\t%0,%1,%2"; ++ } + ;; This MUL will generate an IMM. Cannot go into a delay slot + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "SI") +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch new file mode 100644 index 00000000..3e19f449 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch @@ -0,0 +1,178 @@ +From 39d009f82d0fc316b633a717f173b6195316c8ed Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 9 Nov 2020 19:54:39 +0530 +Subject: [PATCH 20/53] [Patch, microblaze]: 8-stage pipeline for microblaze + +This patch adds the support for the 8-stage pipeline. The new 8-stage +pipeline reduces the latencies of float & integer division drastically + +Signed-off-by :Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.c | 11 ++++ + gcc/config/microblaze/microblaze.h | 3 +- + gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++- + gcc/config/microblaze/microblaze.opt | 4 ++ + 4 files changed, 94 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 16f3120e415..c730faa9814 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -1840,6 +1840,17 @@ microblaze_option_override (void) + "%<-mcpu=v8.30.a%>"); + TARGET_REORDER = 0; + } ++ ver = microblaze_version_to_int("v10.0"); ++ if (ver < 0) ++ { ++ if (TARGET_AREA_OPTIMIZED_2) ++ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater"); ++ } ++ else ++ { ++ if (TARGET_AREA_OPTIMIZED_2) ++ microblaze_pipe = MICROBLAZE_PIPE_8; ++ } + + if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) + error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>"); +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index e32ce7dbb51..21560ec1618 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -27,7 +27,8 @@ + enum pipeline_type + { + MICROBLAZE_PIPE_3 = 0, +- MICROBLAZE_PIPE_5 = 1 ++ MICROBLAZE_PIPE_5 = 1, ++ MICROBLAZE_PIPE_8 = 2 + }; + + #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 986c78f592a..ce72acb9ee0 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -35,6 +35,7 @@ + (R_GOT 20) ;; GOT ptr reg + (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline + (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline ++ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline + (UNSPEC_SET_GOT 101) ;; + (UNSPEC_GOTOFF 102) ;; GOT offset + (UNSPEC_PLT 103) ;; jump table +@@ -82,7 +83,7 @@ + ;; bshift Shift operations + + (define_attr "type" +- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap" ++ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap" + (const_string "unknown")) + + ;; Main data type used by the insn +@@ -224,6 +225,80 @@ + ;;----------------------------------------------------------------- + + ++ ++;;---------------------------------------------------------------- ++;; Microblaze 8-stage pipeline description (v10.0 and later) ++;;---------------------------------------------------------------- ++ ++(define_automaton "mbpipe_8") ++(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8") ++ ++(define_insn_reservation "mb8-integer" 1 ++ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu,mb8_wb") ++ ++(define_insn_reservation "mb8-special-move" 2 ++ (and (eq_attr "type" "move") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu*2,mb8_wb") ++ ++(define_insn_reservation "mb8-mem-load" 3 ++ (and (eq_attr "type" "load,no_delay_load") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu,mb8_wb") ++ ++(define_insn_reservation "mb8-mem-store" 1 ++ (and (eq_attr "type" "store,no_delay_store") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_iu,mb8_wb") ++ ++(define_insn_reservation "mb8-mul" 3 ++ (and (eq_attr "type" "imul,no_delay_imul") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb") ++ ++(define_insn_reservation "mb8-div" 30 ++ (and (eq_attr "type" "idiv") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb") ++ ++(define_insn_reservation "mb8-bs" 2 ++ (and (eq_attr "type" "bshift") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-add-sub-mul" 1 ++ (and (eq_attr "type" "fadd,frsub,fmul") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-fcmp" 3 ++ (and (eq_attr "type" "fcmp") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-div" 24 ++ (and (eq_attr "type" "fdiv") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-sqrt" 23 ++ (and (eq_attr "type" "fsqrt") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-fcvt" 1 ++ (and (eq_attr "type" "fcvt") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_wb") ++ ++(define_insn_reservation "mb8-fpu-fint" 2 ++ (and (eq_attr "type" "fint") ++ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8))) ++ "mb8_issue,mb8_fpu,mb8_wb") ++ ++ + ;;---------------------------------------------------------------- + ;; Microblaze 5-stage pipeline description (v5.00.a and later) + ;;---------------------------------------------------------------- +@@ -470,7 +545,7 @@ + (fix:SI (match_operand:SF 1 "register_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "fint\t%0,%1" +- [(set_attr "type" "fcvt") ++ [(set_attr "type" "fint") + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt +index 8dfb134b315..2a72566372b 100644 +--- a/gcc/config/microblaze/microblaze.opt ++++ b/gcc/config/microblaze/microblaze.opt +@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE). + + mxl-mode-xilkernel + Target ++ ++mxl-frequency ++Target Mask(AREA_OPTIMIZED_2) ++Use 8 stage pipeline (frequency optimization) +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch new file mode 100644 index 00000000..4ef976b7 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch @@ -0,0 +1,58 @@ +From 1c93b2ce88766f74f1f6d7e0235ffff0b7ca7b81 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 9 Nov 2020 21:14:54 +0530 +Subject: [PATCH 21/53] [Patch, microblaze]: Correct the const high double + immediate value with this patch the loading of the DI mode immediate values + will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE + functions, as CONST_DOUBLE_HIGH was returning the sign extension value even + of the unsigned long long constants also + +Signed-off-by :Nagaraju Mekala + Ajit Agarwal +--- + gcc/config/microblaze/microblaze.c | 6 ++++-- + gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++ + 2 files changed, 13 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index c730faa9814..3b1e992fa28 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2452,14 +2452,16 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ long l[2]; + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); + else + { +- val[0] = CONST_DOUBLE_HIGH (op); +- val[1] = CONST_DOUBLE_LOW (op); ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); ++ val[1] = l[WORDS_BIG_ENDIAN == 0]; ++ val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } + else if (code == CONST_INT) +diff --git a/gcc/testsuite/gcc.target/microblaze/others/long.c b/gcc/testsuite/gcc.target/microblaze/others/long.c +new file mode 100644 +index 00000000000..b6b55d5ad65 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/microblaze/others/long.c +@@ -0,0 +1,9 @@ ++#define BASEADDR 0xF0000000ULL ++int main () ++{ ++ unsigned long long start; ++ start = (unsigned long long) BASEADDR; ++ return 0; ++} ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch new file mode 100644 index 00000000..58c4a146 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch @@ -0,0 +1,36 @@ +From 808c5fecf0eab33e4cb66fb5170b9bf114dbc320 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 18 Jan 2017 11:49:58 +0530 +Subject: [PATCH 22/53] [Fix, microblaze]: Fix internal compiler error with + msmall-divides This patch will fix the internal error + microblaze_expand_divide function which comes because of rtx PLUS where the + mem_rtx is of type SI and the operand is of type QImode. This patch modifies + the mem_rtx as QImode and Plus as QImode to fix the error. + +Signed-off-by :Nagaraju Mekala + Ajit Agarwal +ChangeLog: + 2016-02-23 Nagaraju Mekala + Ajit Agarwal + + *microblaze.c (microblaze_expand_divide): Update +--- + gcc/config/microblaze/microblaze.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 3b1e992fa28..94aaeaa3a67 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3767,7 +3767,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_addsi3 (regt1, regt1, operands[2])); + mem_rtx = gen_rtx_MEM (QImode, +- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); ++ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch new file mode 100644 index 00000000..62f8f5e5 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch @@ -0,0 +1,45 @@ +From e6f5b2ba1c03ac3d0521291beb64d64a125e1481 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 18 Jan 2017 12:03:39 +0530 +Subject: [PATCH 23/53] [patch,microblaze]: Fix the calculation of high word in + a long long 6. .4-bit + +This patch will change the calculation of high word in a long long 64-bit. +Earlier to this patch the high word of long long word (0xF0000000ULL) is +coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word +should be 0x00000000 and the low word should be 0xF0000000. This patch +removes the condition of checking high word = 0 & low word < 0. +This check is not required for the correctness of calculating 32-bit high +and low words in a 64-bit long long. + +Signed-off-by :Nagaraju Mekala + Ajit Agarwal + +ChangeLog: +2016-03-01 Nagaraju Mekala + Ajit Agarwal + + *config/microblaze/microblaze.c (print_operand): Remove the condition of checking + high word = 0 & low word < 0. + *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option. +--- + gcc/config/microblaze/microblaze.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 94aaeaa3a67..84e17fc4520 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2468,9 +2468,6 @@ print_operand (FILE * file, rtx op, int letter) + { + val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; + val[1] = INTVAL (op) & 0x00000000ffffffffLL; +- if (val[0] == 0 && val[1] < 0) +- val[0] = -1; +- + } + fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); + } +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has.patch new file mode 100644 index 00000000..c5c9f416 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0024-Patch-MicroBlaze-this-patch-has.patch @@ -0,0 +1,372 @@ +From 5b81fec66287856abfe7def27e245fe73e60fe5e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 26 Oct 2021 21:11:21 +0530 +Subject: [PATCH 24/53] [Patch,MicroBlaze] : this patch has 1.Fixed the bug in + version calculation. 2.Add new bitfield instructions. + +--- + gcc/config/microblaze/microblaze.c | 154 ++++++++++++++-------------- + gcc/config/microblaze/microblaze.h | 2 + + gcc/config/microblaze/microblaze.md | 69 +++++++++++++ + 3 files changed, 147 insertions(+), 78 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 84e17fc4520..9f94d015597 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay; + /* Set to one if the targeted core has the CLZ insn. */ + int microblaze_has_clz = 0; + ++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */ ++int microblaze_has_bitfield = 0; ++ + /* Which CPU pipeline do we use. We haven't really standardized on a CPU + version having only a particular type of pipeline. There can still be + options on the CPU to scale pipeline features up or down. :( +@@ -239,6 +242,63 @@ section *sdata2_section; + #define TARGET_HAVE_TLS true + #endif + ++/* Convert a version number of the form "vX.YY.Z" to an integer encoding ++ for easier range comparison. */ ++static int ++microblaze_version_to_int (const char *version) ++{ ++ const char *p, *v; ++ const char *tmpl = "vXX.YY.Z"; ++ int iver1 =0, iver2 =0, iver3 =0; ++ ++ p = version; ++ v = tmpl; ++ ++ while (*p) ++ { ++ if (*v == 'X') ++ { /* Looking for major */ ++ if (*p == '.') ++ { ++ *v++; ++ } ++ else ++ { ++ if (!(*p >= '0' && *p <= '9')) ++ return -1; ++ iver1 += (int) (*p - '0'); ++ iver1 *= 1000; ++ } ++ } ++ else if (*v == 'Y') ++ { /* Looking for minor */ ++ if (!(*p >= '0' && *p <= '9')) ++ return -1; ++ iver2 += (int) (*p - '0'); ++ iver2 *= 10; ++ } ++ else if (*v == 'Z') ++ { /* Looking for compat */ ++ if (!(*p >= 'a' && *p <= 'z')) ++ return -1; ++ iver3 = ((int) (*p)) - 96; ++ } ++ else ++ { ++ if (*p != *v) ++ return -1; ++ } ++ ++ v++; ++ p++; ++ } ++ ++ if (*p) ++ return -1; ++ ++ return iver1 + iver2 + iver3; ++} ++ + /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ + static bool + microblaze_const_double_ok (rtx op, machine_mode mode) +@@ -1338,8 +1398,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, + { + if (TARGET_BARREL_SHIFT) + { +- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") +- >= 0) ++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (2); +@@ -1400,8 +1459,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, + } + else if (!TARGET_SOFT_MUL) + { +- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") +- >= 0) ++ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a")) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (3); +@@ -1674,72 +1732,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, + return 0; + } + +-/* Convert a version number of the form "vX.YY.Z" to an integer encoding +- for easier range comparison. */ +-static int +-microblaze_version_to_int (const char *version) +-{ +- const char *p, *v; +- const char *tmpl = "vXX.YY.Z"; +- int iver = 0; +- +- p = version; +- v = tmpl; +- +- while (*p) +- { +- if (*v == 'X') +- { /* Looking for major */ +- if (*p == '.') +- { +- v++; +- } +- else +- { +- if (!(*p >= '0' && *p <= '9')) +- return -1; +- iver += (int) (*p - '0'); +- iver *= 10; +- } +- } +- else if (*v == 'Y') +- { /* Looking for minor */ +- if (!(*p >= '0' && *p <= '9')) +- return -1; +- iver += (int) (*p - '0'); +- iver *= 10; +- } +- else if (*v == 'Z') +- { /* Looking for compat */ +- if (!(*p >= 'a' && *p <= 'z')) +- return -1; +- iver *= 10; +- iver += (int) (*p - 'a'); +- } +- else +- { +- if (*p != *v) +- return -1; +- } +- +- v++; +- p++; +- } +- +- if (*p) +- return -1; +- +- return iver; +-} +- +- + static void + microblaze_option_override (void) + { + register int i, start; + register int regno; + register machine_mode mode; +- int ver; ++ int ver,ver_int; + + microblaze_section_threshold = (global_options_set.x_g_switch_value + ? g_switch_value +@@ -1760,13 +1759,13 @@ microblaze_option_override (void) + /* Check the MicroBlaze CPU version for any special action to be done. */ + if (microblaze_select_cpu == NULL) + microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; +- ver = microblaze_version_to_int (microblaze_select_cpu); +- if (ver == -1) ++ ver_int = microblaze_version_to_int (microblaze_select_cpu); ++ if (ver_int == -1) + { + error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu); + } + +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a"); ++ ver = ver_int - microblaze_version_to_int("v3.00.a"); + if (ver < 0) + { + /* No hardware exceptions in earlier versions. So no worries. */ +@@ -1777,8 +1776,7 @@ microblaze_option_override (void) + microblaze_pipe = MICROBLAZE_PIPE_3; + } + else if (ver == 0 +- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b") +- == 0)) ++ || (ver_int == microblaze_version_to_int("v4.00.b"))) + { + #if 0 + microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); +@@ -1795,11 +1793,9 @@ microblaze_option_override (void) + #endif + microblaze_no_unsafe_delay = 0; + microblaze_pipe = MICROBLAZE_PIPE_5; +- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0 +- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, +- "v5.00.b") == 0 +- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, +- "v5.00.c") == 0) ++ if ((ver_int == microblaze_version_to_int("v5.00.a")) ++ || (ver_int == microblaze_version_to_int("v5.00.b")) ++ || (ver_int == microblaze_version_to_int("v5.00.c"))) + { + /* Pattern compares are to be turned on by default only when + compiling for MB v5.00.'z'. */ +@@ -1807,7 +1803,7 @@ microblaze_option_override (void) + } + } + +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a"); ++ ver = ver_int - microblaze_version_to_int("v6.00.a"); + if (ver < 0) + { + if (TARGET_MULTIPLY_HIGH) +@@ -1816,7 +1812,7 @@ microblaze_option_override (void) + "%<-mcpu=v6.00.a%> or greater"); + } + +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a"); ++ ver = ver_int - microblaze_version_to_int("v8.10.a"); + microblaze_has_clz = 1; + if (ver < 0) + { +@@ -1825,7 +1821,7 @@ microblaze_option_override (void) + } + + /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ +- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a"); ++ ver = ver_int - microblaze_version_to_int("v8.30.a"); + if (ver < 0) + { + if (TARGET_REORDER == 1) +@@ -1840,7 +1836,7 @@ microblaze_option_override (void) + "%<-mcpu=v8.30.a%>"); + TARGET_REORDER = 0; + } +- ver = microblaze_version_to_int("v10.0"); ++ ver = ver_int - microblaze_version_to_int("v10.0"); + if (ver < 0) + { + if (TARGET_AREA_OPTIMIZED_2) +@@ -1850,6 +1846,8 @@ microblaze_option_override (void) + { + if (TARGET_AREA_OPTIMIZED_2) + microblaze_pipe = MICROBLAZE_PIPE_8; ++ if (TARGET_BARREL_SHIFT) ++ microblaze_has_bitfield = 1; + } + + if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 21560ec1618..6aac8a6cc2a 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; + + extern int microblaze_no_unsafe_delay; + extern int microblaze_has_clz; ++extern int microblaze_has_bitfield; + extern enum pipeline_type microblaze_pipe; + + #define OBJECT_FORMAT_ELF +@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe; + /* Do we have CLZ? */ + #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz) + ++#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield) + /* The default is to support PIC. */ + #define TARGET_SUPPORTS_PIC 1 + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index ce72acb9ee0..fc3326b2314 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2489,4 +2489,73 @@ + DONE; + }") + ++(define_expand "extvsi" ++ [(set (match_operand:SI 0 "register_operand" "r") ++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "immediate_operand" "I") ++ (match_operand:SI 3 "immediate_operand" "I")))] ++"TARGET_HAS_BITFIELD" ++" ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); ++ ++ if ((len == 0) || (pos + len > 32) ) ++ FAIL; ++ ++ ;;if (!register_operand (operands[1], VOIDmode)) ++ ;; FAIL; ++ if (operands[0] == operands[1]) ++ FAIL; ++ if (GET_CODE (operands[1]) == ASHIFT) ++ FAIL; ++;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); ++ emit_insn (gen_extv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") ++ ++(define_insn "extv_32" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "immediate_operand" "I") ++ (match_operand:SI 3 "immediate_operand" "I")))] ++ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0) ++ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" ++ "bsefi %0,%1,%2,%3" ++ [(set_attr "type" "bshift") ++ (set_attr "length" "4")]) ++ ++(define_expand "insvsi" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (match_operand:SI 1 "immediate_operand" "I") ++ (match_operand:SI 2 "immediate_operand" "I")) ++ (match_operand:SI 3 "register_operand" "r"))] ++ "TARGET_HAS_BITFIELD" ++ " ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); ++ ++ if (len <= 0 || pos + len > 32) ++ FAIL; ++ ++ ;;if (!register_operand (operands[0], VOIDmode)) ++ ;; FAIL; ++ emit_insn (gen_insv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") ++ ++(define_insn "insv_32" ++ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") ++ (match_operand:SI 1 "immediate_operand" "I") ++ (match_operand:SI 2 "immediate_operand" "I")) ++ (match_operand:SI 3 "register_operand" "r"))] ++ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0 ++ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" ++ "bsifi %0, %3, %1, %2" ++ [(set_attr "type" "bshift") ++ (set_attr "length" "4")]) ++ + (include "sync.md") +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch new file mode 100644 index 00000000..f8c438c2 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0025-Fixing-the-issue-with-the-builtin_alloc.patch @@ -0,0 +1,44 @@ +From 18f970e2dd79c67cefeeaa6634f959be19d1a6ad Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 23 Feb 2017 17:09:04 +0530 +Subject: [PATCH 25/53] Fixing the issue with the builtin_alloc. register r18 + was not properly handling the stack pattern which was resolved by using free + available register + +signed-off-by:nagaraju mekala +--- + gcc/config/microblaze/microblaze.md | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index fc3326b2314..0b3dbdd4a70 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2075,10 +2075,10 @@ + "" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); +- rtx rtmp = gen_rtx_REG (SImode, R_TMP); ++ rtx reg = gen_reg_rtx (Pmode); + rtx neg_op0; + +- emit_move_insn (rtmp, retaddr); ++ emit_move_insn (reg, retaddr); + if (GET_CODE (operands[1]) != CONST_INT) + { + neg_op0 = gen_reg_rtx (Pmode); +@@ -2087,9 +2087,9 @@ + neg_op0 = GEN_INT (- INTVAL (operands[1])); + + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); +- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp); ++ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg); + emit_move_insn (operands[0], virtual_stack_dynamic_rtx); +- emit_insn (gen_rtx_CLOBBER (SImode, rtmp)); ++ emit_insn (gen_rtx_CLOBBER (SImode, reg)); + DONE; + } + ) +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch new file mode 100644 index 00000000..e895ddbd --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch @@ -0,0 +1,38 @@ +From 45f4d3915c2194183a87ca54bd9ecf68eeccba4d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 4 Jun 2018 10:10:18 +0530 +Subject: [PATCH 26/53] [Patch,Microblaze] : Removed fsqrt generation for + double values. + +--- + gcc/config/microblaze/microblaze.md | 14 -------------- + 1 file changed, 14 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0b3dbdd4a70..9dd12d1011b 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -526,20 +526,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +-(define_insn "sqrtdf2" +- [(set (match_operand:DF 0 "register_operand" "=d") +- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" +- { +- if (REGNO (operands[0]) == REGNO (operands[1])) +- return "fsqrt\t%0,%1"; +- else +- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; +- } +- [(set_attr "type" "fsqrt") +- (set_attr "mode" "SF") +- (set_attr "length" "4")]) +- + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch new file mode 100644 index 00000000..140332aa --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch @@ -0,0 +1,784 @@ +From dba8e9e148812774d94f584cdff7b6e0293081b5 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 10 Nov 2020 12:52:54 +0530 +Subject: [PATCH 27/53] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze + +Conflicts: + gcc/config/microblaze/microblaze.md +--- + gcc/config/microblaze/constraints.md | 6 + + gcc/config/microblaze/microblaze-protos.h | 1 + + gcc/config/microblaze/microblaze.c | 109 +++++-- + gcc/config/microblaze/microblaze.h | 4 +- + gcc/config/microblaze/microblaze.md | 352 +++++++++++++++++++++- + gcc/config/microblaze/microblaze.opt | 7 +- + gcc/config/microblaze/t-microblaze | 7 +- + 7 files changed, 456 insertions(+), 30 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index b4d7ee329b8..95b21d58f88 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -52,6 +52,12 @@ + (and (match_code "const_int") + (match_test "ival > 0 && ival < 0x10000"))) + ++(define_constraint "K" ++ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." ++ (and (match_code "const_int") ++ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ ++ + ;; Define floating point constraints + + (define_constraint "G" +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index 3a5f439703c..302f6bbda2e 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *); + extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); ++extern void microblaze_expand_conditional_branch_df (rtx *); + extern int microblaze_can_use_return_insn (void); + extern void print_operand (FILE *, rtx, int); + extern void print_operand_address (FILE *, rtx); +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 9f94d015597..58d7397945e 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3432,11 +3432,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + op0 = operands[0]; + op1 = operands[1]; + +- if (!register_operand (op0, SImode) +- && !register_operand (op1, SImode) ++ if (!register_operand (op0, mode) ++ && !register_operand (op1, mode) + && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0)) + { +- rtx temp = force_reg (SImode, op1); ++ rtx temp = force_reg (mode, op1); + emit_move_insn (op0, temp); + return true; + } +@@ -3501,12 +3501,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + && (flag_pic == 2 || microblaze_tls_symbol_p (p0) + || !SMALL_INT (p1))))) + { +- rtx temp = force_reg (SImode, p0); ++ rtx temp = force_reg (mode, p0); + rtx temp2 = p1; + + if (flag_pic && reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); +- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2)); ++ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2)); + return true; + } + } +@@ -3637,7 +3637,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); +@@ -3646,23 +3646,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + if (cmp_op1 == const0_rtx) + { + comp_reg = cmp_op0; +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + + else if (code == EQ || code == NE) + { + /* Use xor for equal/not-equal comparison. */ +- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); ++ else ++ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ else ++ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1)); + } + } + +@@ -3673,7 +3686,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) +@@ -3684,30 +3697,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), +- SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else if (code == EQ) + { +- emit_insn (gen_seq_internal_pat (comp_reg, +- cmp_op0, cmp_op1)); +- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + else if (code == NE) + { +- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, +- cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_NE (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare (condition, cmp_op0, +- cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ else ++ { ++ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ } ++ + } + } + +@@ -3724,6 +3770,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + emit_jump_insn (gen_condjump (condition, operands[3])); + } + ++void ++microblaze_expand_conditional_branch_df (rtx operands[]) ++{ ++ rtx condition; ++ rtx cmp_op0 = XEXP (operands[0], 0); ++ rtx cmp_op1 = XEXP (operands[0], 1); ++ rtx comp_reg = gen_reg_rtx (DImode); ++ ++ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); ++ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ emit_jump_insn (gen_long_condjump (condition, operands[3])); ++} ++ + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ + + static bool +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 6aac8a6cc2a..22fc3509319 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; + #define ASM_SPEC "\ + %(target_asm_spec) \ + %{mbig-endian:-EB} \ ++%{m64:-m64} \ + %{mlittle-endian:-EL}" + + /* Extra switches sometimes passed to the linker. */ +@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe; + #define LINK_SPEC "%{shared:-shared} -N -relax \ + %{mbig-endian:-EB --oformat=elf32-microblaze} \ + %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ ++ %{m64:-EL --oformat=elf64-microblazeel} \ + %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ +@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe; + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 32 ++#define LONG_TYPE_SIZE 64 + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 9dd12d1011b..3834725eec1 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -497,7 +497,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +- + (define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (div:SF (match_operand:SF 1 "register_operand" "d") +@@ -508,6 +507,7 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++ + (define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] +@@ -562,6 +562,18 @@ + + ;; Adding 2 DI operands in register or reg/imm + ++(define_insn "adddi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (match_operand:DI 2 "arith_plus_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ addlk\t%0,%z1,%2 ++ addlik\t%0,%z1,%2" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "adddi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") +@@ -606,6 +618,18 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + ++(define_insn "subdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "register_operand" "d,n")))] ++ "TARGET_MB_64" ++ "@ ++ rsubl\t%0,%2,%1 ++ addlik\t%0,%z1,-%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") +@@ -795,6 +819,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negdi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (neg:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "rsubl\t%0,%1,r0" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -814,6 +847,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "one_cmpldi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "xorli\t%0,%1,-1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "*one_cmpldi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -840,6 +882,20 @@ + ;; Logical + ;;---------------------------------------------------------------- + ++(define_insn "anddi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ andl\t%0,%1,%2 ++ andli\t%0,%1,%2 #andl1" ++ ;; andli\t%0,%1,%2 #andl3 ++ ;; andli\t%0,%1,%2 #andl2 ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -855,6 +911,18 @@ + (set_attr "length" "4,8,8,8")]) + + ++(define_insn "iordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ior:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ orl\t%0,%1,%2 ++ orli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -869,6 +937,19 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "xordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ xorl\t%0,%1,%2 ++ xorli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ ++ + (define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") +@@ -937,6 +1018,26 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++;;(define_expand "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] ++;; "TARGET_MB_64" ++;; { ++;; if (GET_CODE (operands[1]) != REG) ++;; FAIL; ++;; } ++;;) ++ ++ ++;;(define_insn "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] ++;; "TARGET_MB_64" ++;; "sextl8\t%0,%1" ++;; [(set_attr "type" "arith") ++;; (set_attr "mode" "DI") ++;; (set_attr "length" "4")]) ++ + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -946,6 +1047,16 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "sextl16\t%0,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++ + ;; Those for integer source operand are ordered + ;; widest source type first. + +@@ -1009,6 +1120,32 @@ + ) + + ++(define_insn "*movdi_internal_64" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") ++ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] ++ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1"; ++ case 1: ++ return "addlik\t%0,r0,%1"; ++ case 2: ++ return "addlk\t%0,r0,r0"; ++ case 3: ++ case 4: ++ return "lli\t%0,%1"; ++ case 5: ++ case 6: ++ return "sli\t%1,%0"; ++ } ++ return "unreachable"; ++ } ++ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8,8,8,8,12,8,12")]) ++ + + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") +@@ -1421,6 +1558,36 @@ + (set_attr "length" "4,4")] + ) + ++;; Barrel shift left ++(define_expand "ashldi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashldi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bsllli\t%0,%1,%2 ++ bslll\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++) + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1546,6 +1713,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "ashrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrai\t%0,%1,%2 ++ bslra\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -1655,6 +1852,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts (logical) + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "lshrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "lshrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrli\t%0,%1,%2 ++ bslrl\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") +@@ -1800,6 +2027,8 @@ + (set_attr "length" "4")] + ) + ++ ++ + ;;---------------------------------------------------------------- + ;; Setting a register from an floating point comparison. + ;;---------------------------------------------------------------- +@@ -1815,6 +2044,18 @@ + (set_attr "length" "4")] + ) + ++(define_insn "cstoredf4" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (match_operator:DI 1 "ordered_comparison_operator" ++ [(match_operand:DF 2 "register_operand" "r") ++ (match_operand:DF 3 "register_operand" "r")]))] ++ "TARGET_MB_64" ++ "dcmp.%C1\t%0,%3,%2" ++ [(set_attr "type" "fcmp") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")] ++) ++ + ;;---------------------------------------------------------------- + ;; Conditional branches + ;;---------------------------------------------------------------- +@@ -1927,6 +2168,115 @@ + (set_attr "length" "12")] + ) + ++ ++(define_expand "cbranchdi4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "arith_operand" "I,i")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdi4_reg" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_reg (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdf4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DF 1 "register_operand") ++ (match_operand:DF 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_df (operands); ++ DONE; ++ ++}) ++ ++;; Used to implement comparison instructions ++(define_expand "long_condjump" ++ [(set (pc) ++ (if_then_else (match_operand 0) ++ (label_ref (match_operand 1)) ++ (pc)))]) ++ ++(define_insn "long_branch_zero" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:DI 2 "pc_or_label_operand" "") ++ (match_operand:DI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "beal%C0i%?\t%z1,%2"; ++ else ++ return "beal%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt +index 2a72566372b..206899c0384 100644 +--- a/gcc/config/microblaze/microblaze.opt ++++ b/gcc/config/microblaze/microblaze.opt +@@ -136,4 +136,9 @@ Target + + mxl-frequency + Target Mask(AREA_OPTIMIZED_2) +-Use 8 stage pipeline (frequency optimization) ++Use 8 stage pipeline (frequency optimization). ++ ++m64 ++Target Mask(MB_64) ++MicroBlaze 64-bit mode. ++ +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 41fa9a92081..e9a1921ae26 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,8 +1,11 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian +-MULTILIB_DIRNAMES = bs m mh le ++MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 ++MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch new file mode 100644 index 00000000..9d38091e --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0028-Intial-commit-for-64bit-MB-sources.patch @@ -0,0 +1,2451 @@ +From 211cfd6be4b47e1fecf95d1becb713772fd71091 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 27 Jul 2018 15:23:41 +0530 +Subject: [PATCH 28/53] Intial commit for 64bit-MB sources. Need to cleanup the + code later. + +--- + gcc/config/microblaze/constraints.md | 2 +- + gcc/config/microblaze/microblaze-c.c | 6 + + gcc/config/microblaze/microblaze.c | 218 ++++++--- + gcc/config/microblaze/microblaze.h | 63 ++- + gcc/config/microblaze/microblaze.md | 605 ++++++++++++++++++------ + gcc/config/microblaze/t-microblaze | 3 +- + libgcc/config/microblaze/crti.S | 4 +- + libgcc/config/microblaze/crtn.S | 4 +- + libgcc/config/microblaze/divdi3.S | 98 ++++ + libgcc/config/microblaze/divdi3_table.c | 62 +++ + libgcc/config/microblaze/moddi3.S | 97 ++++ + libgcc/config/microblaze/muldi3.S | 73 +++ + libgcc/config/microblaze/t-microblaze | 11 +- + libgcc/config/microblaze/udivdi3.S | 107 +++++ + libgcc/config/microblaze/umoddi3.S | 110 +++++ + 15 files changed, 1230 insertions(+), 233 deletions(-) + create mode 100644 libgcc/config/microblaze/divdi3.S + create mode 100644 libgcc/config/microblaze/divdi3_table.c + create mode 100644 libgcc/config/microblaze/moddi3.S + create mode 100644 libgcc/config/microblaze/muldi3.S + create mode 100644 libgcc/config/microblaze/udivdi3.S + create mode 100644 libgcc/config/microblaze/umoddi3.S + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index 95b21d58f88..0a4d5269314 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -55,7 +55,7 @@ + (define_constraint "K" + "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) + + + ;; Define floating point constraints +diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c +index e0b29bcb0b0..2dcb879992c 100644 +--- a/gcc/config/microblaze/microblaze-c.c ++++ b/gcc/config/microblaze/microblaze-c.c +@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) + builtin_define ("HAVE_HW_FPU_SQRT"); + builtin_define ("__HAVE_HW_FPU_SQRT__"); + } ++ if (TARGET_MB_64) ++ { ++ builtin_define ("__arch64__"); ++ builtin_define ("__microblaze64__"); ++ builtin_define ("__MICROBLAZE64__"); ++ } + } +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 58d7397945e..f59a71ac072 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) + { + return 1; + } +- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) ++ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) + { + return 1; +- } ++ }*/ + else + return 0; + +@@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode) + return 1; + + return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT +- ? E_SImode : E_SFmode), ++ ? Pmode : E_SFmode), + plus_constant (Pmode, addr, 4)); + } + +@@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) + /* Load the addend. */ + addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), + UNSPEC_TLS); +- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); ++ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend)); + dest = gen_rtx_PLUS (Pmode, dest, addend); + break; + +@@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) + + if (XINT (x, 1) == UNSPEC_GOTOFF) + { +- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM); ++ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); + info->type = ADDRESS_GOTOFF; + } + else if (XINT (x, 1) == UNSPEC_PLT) +@@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) + emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); + + /* Emit the test & branch. */ +- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src), ++ ++ if (TARGET_MB_64) { ++ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src), ++ src_reg, final_src, label)); ++ } ++ else { ++ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src), + src_reg, final_src, label)); ++ ++ } + + /* Mop up any left-over bytes. */ + if (leftover) +@@ -1633,14 +1641,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, + break; + + case E_DFmode: +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + if (!cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 2 << ((cum->arg_number - 1) * 2); + break; + + case E_DImode: + cum->gp_reg_found = 1; +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + break; + + case E_QImode: +@@ -2155,7 +2169,7 @@ compute_frame_size (HOST_WIDE_INT size) + + if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) + /* Don't account for link register. It is accounted specially below. */ +- gp_reg_size += GET_MODE_SIZE (SImode); ++ gp_reg_size += GET_MODE_SIZE (Pmode); + + mask |= (1L << (regno - GP_REG_FIRST)); + } +@@ -2424,7 +2438,7 @@ print_operand (FILE * file, rtx op, int letter) + + if ((letter == 'M' && !WORDS_BIG_ENDIAN) + || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') +- regnum++; ++ regnum++; + + fprintf (file, "%s", reg_names[regnum]); + } +@@ -2450,6 +2464,7 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2462,12 +2477,12 @@ print_operand (FILE * file, rtx op, int letter) + val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } +- else if (code == CONST_INT) ++ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val1[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); + } + else if (code == CONST_DOUBLE) + { +@@ -2661,7 +2676,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2684,7 +2702,10 @@ microblaze_asm_destructor (rtx symbol, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2750,7 +2771,7 @@ save_restore_insns (int prologue) + /* For interrupt_handlers, need to save/restore the MSR. */ + if (microblaze_is_interrupt_variant ()) + { +- isr_mem_rtx = gen_rtx_MEM (SImode, ++ isr_mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, base_reg_rtx, + GEN_INT (current_frame_info. + gp_offset - +@@ -2758,8 +2779,8 @@ save_restore_insns (int prologue) + + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (isr_mem_rtx) = 1; +- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG); +- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG); ++ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG); ++ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG); + } + + if (microblaze_is_interrupt_variant () && !prologue) +@@ -2767,8 +2788,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_reg_rtx, isr_mem_rtx); + emit_move_insn (isr_msr_rtx, isr_reg_rtx); + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) +@@ -2779,9 +2800,9 @@ save_restore_insns (int prologue) + /* Don't handle here. Already handled as the first register. */ + continue; + +- reg_rtx = gen_rtx_REG (SImode, regno); ++ reg_rtx = gen_rtx_REG (Pmode, regno); + insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset)); +- mem_rtx = gen_rtx_MEM (SImode, insn); ++ mem_rtx = gen_rtx_MEM (Pmode, insn); + if (microblaze_is_interrupt_variant () || save_volatiles) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +@@ -2796,7 +2817,7 @@ save_restore_insns (int prologue) + insn = emit_move_insn (reg_rtx, mem_rtx); + } + +- gp_offset += GET_MODE_SIZE (SImode); ++ gp_offset += GET_MODE_SIZE (Pmode); + } + } + +@@ -2806,8 +2827,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_mem_rtx, isr_reg_rtx); + + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + /* Done saving and restoring */ +@@ -2897,7 +2918,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) + + switch_to_section (s); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -3041,10 +3065,10 @@ microblaze_expand_prologue (void) + { + if (offset != 0) + ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); +- emit_move_insn (gen_rtx_MEM (SImode, ptr), +- gen_rtx_REG (SImode, regno)); ++ emit_move_insn (gen_rtx_MEM (Pmode, ptr), ++ gen_rtx_REG (Pmode, regno)); + +- offset += GET_MODE_SIZE (SImode); ++ offset += GET_MODE_SIZE (Pmode); + } + } + +@@ -3053,15 +3077,23 @@ microblaze_expand_prologue (void) + rtx fsiz_rtx = GEN_INT (fsiz); + + rtx_insn *insn = NULL; +- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ if (TARGET_MB_64) ++ { ++ ++ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, + fsiz_rtx)); ++ } ++ else { ++ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ fsiz_rtx)); ++ } + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + + /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */ + if (!crtl->is_leaf || interrupt_handler) + { +- mem_rtx = gen_rtx_MEM (SImode, ++ mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + const0_rtx)); + +@@ -3069,7 +3101,7 @@ microblaze_expand_prologue (void) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } +@@ -3179,12 +3211,12 @@ microblaze_expand_epilogue (void) + if (!crtl->is_leaf || interrupt_handler) + { + mem_rtx = +- gen_rtx_MEM (SImode, ++ gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); + if (interrupt_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + emit_move_insn (reg_rtx, mem_rtx); + } + +@@ -3200,15 +3232,25 @@ microblaze_expand_epilogue (void) + /* _restore_ registers for epilogue. */ + save_restore_insns (0); + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ else ++ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); + } + + if (crtl->calls_eh_return) +- emit_insn (gen_addsi3 (stack_pointer_rtx, ++ if (TARGET_MB_64) { ++ emit_insn (gen_adddi3 (stack_pointer_rtx, + stack_pointer_rtx, +- gen_raw_REG (SImode, ++ gen_raw_REG (Pmode, + MB_EH_STACKADJ_REGNUM))); +- ++ } ++ else { ++ emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ gen_raw_REG (Pmode, ++ MB_EH_STACKADJ_REGNUM))); ++ } + emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + } +@@ -3375,9 +3417,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + else + this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); + +- /* Apply the constant offset, if required. */ ++ /* Apply the constant offset, if required. */ + if (delta) +- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ { ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ } + + /* Apply the offset from the vtable, if required. */ + if (vcall_offset) +@@ -3390,7 +3437,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); + emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); + +- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1)); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); + } + + /* Generate a tail call to the target function. */ +@@ -3566,7 +3616,7 @@ microblaze_eh_return (rtx op0) + /* Queue an .ident string in the queue of top-level asm statements. + If the string size is below the threshold, put it into .sdata2. + If the front-end is done, we must be being called from toplev.c. +- In that case, do nothing. */ ++ In that case, do nothing. */ + void + microblaze_asm_output_ident (const char *string) + { +@@ -3621,9 +3671,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + emit_block_move (m_tramp, assemble_trampoline_template (), + GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); + +- mem = adjust_address (m_tramp, SImode, 16); ++ mem = adjust_address (m_tramp, Pmode, 16); + emit_move_insn (mem, chain_value); +- mem = adjust_address (m_tramp, SImode, 20); ++ mem = adjust_address (m_tramp, Pmode, 20); + emit_move_insn (mem, fnaddr); + } + +@@ -3647,7 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) ++ if (mode == Pmode) + emit_jump_insn (gen_condjump (condition, label1)); + else + emit_jump_insn (gen_long_condjump (condition, label1)); +@@ -3766,7 +3816,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + rtx comp_reg = gen_reg_rtx (SImode); + + emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, operands[3])); + } + +@@ -3776,10 +3826,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + rtx condition; + rtx cmp_op0 = XEXP (operands[0], 0); + rtx cmp_op1 = XEXP (operands[0], 1); +- rtx comp_reg = gen_reg_rtx (DImode); ++ rtx comp_reg = gen_reg_rtx (Pmode); + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_long_condjump (condition, operands[3])); + } + +@@ -3800,8 +3850,8 @@ microblaze_expand_divide (rtx operands[]) + { + /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ + +- rtx regt1 = gen_reg_rtx (SImode); +- rtx reg18 = gen_rtx_REG (SImode, R_TMP); ++ rtx regt1 = gen_reg_rtx (Pmode); ++ rtx reg18 = gen_rtx_REG (Pmode, R_TMP); + rtx regqi = gen_reg_rtx (QImode); + rtx_code_label *div_label = gen_label_rtx (); + rtx_code_label *div_end_label = gen_label_rtx (); +@@ -3809,17 +3859,31 @@ microblaze_expand_divide (rtx operands[]) + rtx mem_rtx; + rtx ret; + rtx_insn *jump, *cjump, *insn; +- +- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); +- cjump = emit_jump_insn_after (gen_cbranchsi4 ( +- gen_rtx_GTU (SImode, regt1, GEN_INT (15)), ++ ++ if (TARGET_MB_64) { ++ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchdi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), ++ regt1, GEN_INT (15), div_label), insn); ++ } ++ else { ++ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchsi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), + regt1, GEN_INT (15), div_label), insn); ++ } + LABEL_NUSES (div_label) = 1; + JUMP_LABEL (cjump) = div_label; +- emit_insn (gen_rtx_CLOBBER (SImode, reg18)); ++ emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + +- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); +- emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ if (TARGET_MB_64) { ++ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_adddi3 (regt1, regt1, operands[2])); ++ } ++ else { ++ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ } + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + +@@ -3966,7 +4030,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) + { + insn = + emit_insn_before (gen_iprefetch +- (gen_int_mode (addr_offset, SImode)), ++ (gen_int_mode (addr_offset, Pmode)), + before_4); + recog_memoized (insn); + INSN_LOCATION (insn) = INSN_LOCATION (before_4); +@@ -3976,7 +4040,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) + } + } + } +- ++ ++/* Set the names for various arithmetic operations according to the ++ * MICROBLAZE ABI. */ ++static void ++microblaze_init_libfuncs (void) ++{ ++ set_optab_libfunc (smod_optab, SImode, "__modsi3"); ++ set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); ++ set_optab_libfunc (smul_optab, SImode, "__mulsi3"); ++ set_optab_libfunc (umod_optab, SImode, "__umodsi3"); ++ set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); ++ ++ if (TARGET_MB_64) ++ { ++ set_optab_libfunc (smod_optab, DImode, "__moddi3"); ++ set_optab_libfunc (sdiv_optab, DImode, "__divdi3"); ++ set_optab_libfunc (smul_optab, DImode, "__muldi3"); ++ set_optab_libfunc (umod_optab, DImode, "__umoddi3"); ++ set_optab_libfunc (udiv_optab, DImode, "__udivdi3"); ++ } ++} + /* Insert instruction prefetch instruction at the fall + through path of the function call. */ + +@@ -4129,6 +4213,17 @@ microblaze_starting_frame_offset (void) + #undef TARGET_LRA_P + #define TARGET_LRA_P hook_bool_void_false + ++#ifdef TARGET_MB_64 ++#undef TARGET_ASM_ALIGNED_DI_OP ++#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" ++ ++#undef TARGET_ASM_ALIGNED_HI_OP ++#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" ++ ++#undef TARGET_ASM_ALIGNED_SI_OP ++#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" ++#endif ++ + #undef TARGET_FRAME_POINTER_REQUIRED + #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required + +@@ -4138,6 +4233,9 @@ microblaze_starting_frame_offset (void) + #undef TARGET_TRAMPOLINE_INIT + #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init + ++#undef TARGET_INIT_LIBFUNCS ++#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs ++ + #undef TARGET_PROMOTE_FUNCTION_MODE + #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 22fc3509319..94ac736221c 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; + + /* Generate DWARF exception handling info. */ + #define DWARF2_UNWIND_INFO 1 +- + /* Don't generate .loc operations. */ + #define DWARF2_ASM_LINE_DEBUG_INFO 0 + +@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe; + ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr) + + /* Use DWARF 2 debugging information by default. */ +-#define DWARF2_DEBUGGING_INFO ++#define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG ++#define DWARF2_ADDR_SIZE 4 + + /* Target machine storage layout */ + + #define BITS_BIG_ENDIAN 0 + #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) + #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) +-#define BITS_PER_WORD 32 +-#define UNITS_PER_WORD 4 ++//#define BITS_PER_WORD 64 ++//Revisit ++#define MAX_BITS_PER_WORD 64 ++#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define UNITS_PER_WORD 4 + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 64 ++#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32) + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 + #define LONG_DOUBLE_TYPE_SIZE 64 +-#define POINTER_SIZE 32 +-#define PARM_BOUNDARY 32 +-#define FUNCTION_BOUNDARY 32 +-#define EMPTY_FIELD_BOUNDARY 32 ++#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32) ++//#define WIDEST_HARDWARE_FP_SIZE 64 ++//#define POINTERS_EXTEND_UNSIGNED 1 ++#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32) + #define STRUCTURE_SIZE_BOUNDARY 8 +-#define BIGGEST_ALIGNMENT 32 ++#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + #define STRICT_ALIGNMENT 1 + #define PCC_BITFIELD_TYPE_MATTERS 1 + ++//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode) + #undef SIZE_TYPE +-#define SIZE_TYPE "unsigned int" ++#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #undef PTRDIFF_TYPE +-#define PTRDIFF_TYPE "int" ++#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int") ++ ++/*#undef INTPTR_TYPE ++#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/ ++#undef UINTPTR_TYPE ++#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #define DATA_ALIGNMENT(TYPE, ALIGN) \ + ((((ALIGN) < BITS_PER_WORD) \ +@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +- ++/* + #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < 4) \ +- (MODE) = SImode; +- ++ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ ++ (MODE) = TARGET_MB_64 ? DImode : SImode; ++*/ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info; + #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) + + #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 ++#define DWARF_CIE_DATA_ALIGNMENT -1 + + #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) + + #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + +-#define STACK_BOUNDARY 32 ++#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) + ++#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++ + #define NUM_OF_ARGS 6 + + #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) +@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info; + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + + #define LIBCALL_VALUE(MODE) \ ++ gen_rtx_REG (MODE,GP_RETURN) ++ ++/*#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +- ++*/ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -500,7 +518,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 32 ++#define TRAMPOLINE_ALIGNMENT 64 + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +@@ -529,13 +547,13 @@ typedef struct microblaze_args + addresses which require two reload registers. */ + #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) + +-#define CASE_VECTOR_MODE (SImode) ++#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode) + + #ifndef DEFAULT_SIGNED_CHAR + #define DEFAULT_SIGNED_CHAR 1 + #endif + +-#define MOVE_MAX 4 ++#define MOVE_MAX (TARGET_MB_64 ? 8 : 4) + #define MAX_MOVE_MAX 8 + + #define SLOW_BYTE_ACCESS 1 +@@ -545,7 +563,7 @@ typedef struct microblaze_args + + #define SHIFT_COUNT_TRUNCATED 1 + +-#define Pmode SImode ++#define Pmode (TARGET_MB_64? DImode:SImode) + + #define FUNCTION_MODE SImode + +@@ -707,6 +725,7 @@ do { \ + + #undef TARGET_ASM_OUTPUT_IDENT + #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident ++//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive + + /* Default to -G 8 */ + #ifndef MICROBLAZE_DEFAULT_GVALUE +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 3834725eec1..7bc91602ca2 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -26,6 +26,7 @@ + ;; Constants + ;;---------------------------------------------------- + (define_constants [ ++ (R_Z 0) ;; For reg r0 + (R_SP 1) ;; Stack pointer reg + (R_SR 15) ;; Sub-routine return addr reg + (R_IR 14) ;; Interrupt return addr reg +@@ -541,6 +542,7 @@ + + ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] + ;; Leave carry as is ++ + (define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") +@@ -562,23 +564,38 @@ + + ;; Adding 2 DI operands in register or reg/imm + +-(define_insn "adddi3_long" ++(define_expand "adddi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (plus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_plus_operand" "")))] ++"" ++{ ++ if (TARGET_MB_64) ++ { ++ if (GET_CODE (operands[2]) == CONST_INT && ++ INTVAL(operands[2]) < (long)-549755813888 && ++ INTVAL(operands[2]) > (long)549755813887) ++ FAIL; ++ } ++}) ++ ++(define_insn "*adddi3_long" + [(set (match_operand:DI 0 "register_operand" "=d,d") +- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_plus_operand" "d,K")))] + "TARGET_MB_64" + "@ +- addlk\t%0,%z1,%2 +- addlik\t%0,%z1,%2" +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") ++ addlk\t%0,%1,%2 ++ addlik\t%0,%1,%2 #N10" ++ [(set_attr "type" "darith,no_delay_arith") ++ (set_attr "mode" "DI") + (set_attr "length" "4,4")]) + +-(define_insn "adddi3" ++(define_insn "*adddi3_all" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_operand" "d,i")))] +- "" ++ "!TARGET_MB_64" + "@ + add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 + addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" +@@ -605,7 +622,7 @@ + (define_insn "iprefetch" + [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) + (clobber (mem:BLK (scratch)))] +- "TARGET_PREFETCH" ++ "TARGET_PREFETCH && !TARGET_MB_64" + { + operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + return "mfs\t%2,rpc\n\twic\t%2,r0"; +@@ -618,23 +635,33 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + +-(define_insn "subdi3_long" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (minus:DI (match_operand:DI 1 "register_operand" "d,d") +- (match_operand:DI 2 "register_operand" "d,n")))] ++(define_expand "subdi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (minus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_operand" "")))] ++"" ++" ++{ ++}") ++ ++(define_insn "subsidi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,n")))] + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addlik\t%0,%z1,-%2" +- [(set_attr "type" "darith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ addik\t%0,%z1,-%2 ++ addik\t%0,%z1,-%2" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,4")]) + +-(define_insn "subdi3" ++(define_insn "subdi3_small" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "" ++ "!TARGET_MB_64" + "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" + [(set_attr "type" "darith") + (set_attr "mode" "DI") +@@ -663,7 +690,7 @@ + (mult:DI + (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -674,7 +701,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -685,7 +712,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -789,7 +816,7 @@ + (match_operand:SI 4 "arith_operand")]) + (label_ref (match_operand 5)) + (pc)))] +- "TARGET_HARD_FLOAT" ++ "TARGET_HARD_FLOAT && !TARGET_MB_64" + [(set (match_dup 1) (match_dup 3))] + + { +@@ -819,6 +846,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negsi_long" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (neg:SI (match_operand:DI 1 "register_operand" "d")))] ++ "" ++ "rsubk\t%0,%1,r0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2_long" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -847,16 +883,24 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_insn "one_cmpldi2_long" ++(define_expand "one_cmpldi2" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (not:DI (match_operand:DI 1 "register_operand" "")))] ++ "" ++ " ++{ ++}") ++ ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") +- (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ (not:DI (match_operand:DI 1 "arith_operand" "d")))] + "TARGET_MB_64" + "xorli\t%0,%1,-1" +- [(set_attr "type" "arith") ++ [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +-(define_insn "*one_cmpldi2" ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] + "" +@@ -871,7 +915,8 @@ + (not:DI (match_operand:DI 1 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) +- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" ++ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) ++ && !TARGET_MB_64" + + [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) + (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] +@@ -883,18 +928,17 @@ + ;;---------------------------------------------------------------- + + (define_insn "anddi3" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (and:DI (match_operand:DI 1 "arith_operand" "d,d") +- (match_operand:DI 2 "arith_operand" "d,K")))] ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,I")))] + "TARGET_MB_64" + "@ + andl\t%0,%1,%2 +- andli\t%0,%1,%2 #andl1" +- ;; andli\t%0,%1,%2 #andl3 +- ;; andli\t%0,%1,%2 #andl2 +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ andli\t%0,%1,%2 #andl2 ++ andli\t%0,%1,%2 #andl3" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI,DI,DI") ++ (set_attr "length" "4,4,4")]) + + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") +@@ -919,7 +963,7 @@ + "@ + orl\t%0,%1,%2 + orli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -945,7 +989,7 @@ + "@ + xorl\t%0,%1,%2 + xorli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -1018,26 +1062,6 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-;;(define_expand "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] +-;; "TARGET_MB_64" +-;; { +-;; if (GET_CODE (operands[1]) != REG) +-;; FAIL; +-;; } +-;;) +- +- +-;;(define_insn "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] +-;; "TARGET_MB_64" +-;; "sextl8\t%0,%1" +-;; [(set_attr "type" "arith") +-;; (set_attr "mode" "DI") +-;; (set_attr "length" "4")]) +- + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -1060,6 +1084,27 @@ + ;; Those for integer source operand are ordered + ;; widest source type first. + ++(define_insn "extendsidi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "sextl32\t%0,%1"; ++ case 1: ++ case 2: ++ { ++ output_asm_insn ("ll%i1\t%0,%1", operands); ++ return "sextl32\t%0,%0"; ++ } ++ } ++ } ++ [(set_attr "type" "multi,multi,multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,8,8")]) ++ + (define_insn "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] +@@ -1088,69 +1133,118 @@ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. ++;; //} + + (define_expand "movdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + { +- /* If operands[1] is a constant address illegal for pic, then we need to +- handle it just like microblaze_legitimize_address does. */ +- if (flag_pic && pic_address_needs_scratch (operands[1])) ++ if (TARGET_MB_64) ++ { ++ if (microblaze_expand_move (DImode, operands)) DONE; ++ } ++ else + { ++ /* If operands[1] is a constant address illegal for pic, then we need to ++ handle it just like microblaze_legitimize_address does. */ ++ if (flag_pic && pic_address_needs_scratch (operands[1])) ++ { + rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2)); + DONE; +- } +- +- +- if ((reload_in_progress | reload_completed) == 0 +- && !register_operand (operands[0], DImode) +- && !register_operand (operands[1], DImode) +- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) +- && operands[1] != CONST0_RTX (DImode)))) +- { ++ } + +- rtx temp = force_reg (DImode, operands[1]); +- emit_move_insn (operands[0], temp); +- DONE; ++ if ((reload_in_progress | reload_completed) == 0 ++ && !register_operand (operands[0], DImode) ++ && !register_operand (operands[1], DImode) ++ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) ++ && operands[1] != CONST0_RTX (DImode)))) ++ { ++ rtx temp = force_reg (DImode, operands[1]); ++ emit_move_insn (operands[0], temp); ++ DONE; ++ } + } + } + ) + ++;; Added for status registers ++(define_insn "movdi_status" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,z") ++ (match_operand:DI 1 "register_operand" "z,d,d"))] ++ "microblaze_is_interrupt_variant () && TARGET_MB_64" ++ "@ ++ mfs\t%0,%1 #mfs ++ addlk\t%0,%1,r0 #add movdi ++ mts\t%0,%1 #mts" ++ [(set_attr "type" "move") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) + +-(define_insn "*movdi_internal_64" +- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") +- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] +- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++;; This move will be not be moved to delay slot. ++(define_insn "*movdi_internal3" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") ++ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] ++ "TARGET_MB_64 && (register_operand (operands[0], DImode) && ++ (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" ++ "@ ++ addlk\t%0,r0,r0\t ++ addlik\t%0,r0,%1\t #N1 %X1 ++ addlik\t%0,r0,%1\t #N2 %X1" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++;; This move may be used for PLT label operand ++(define_insn "*movdi_internal5_pltop" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (match_operand:DI 1 "call_insn_operand" ""))] ++ "TARGET_MB_64 && (register_operand (operands[0], Pmode) && ++ PLT_ADDR_P (operands[1]))" ++ { ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "load") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++(define_insn "*movdi_internal2" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64" + { + switch (which_alternative) + { + case 0: +- return "addlk\t%0,%1"; +- case 1: +- return "addlik\t%0,r0,%1"; +- case 2: +- return "addlk\t%0,r0,r0"; +- case 3: +- case 4: +- return "lli\t%0,%1"; +- case 5: +- case 6: +- return "sli\t%1,%0"; +- } +- return "unreachable"; +- } +- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") + (set_attr "mode" "DI") +- (set_attr "length" "8,8,8,8,12,8,12")]) ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + + + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +- "" ++ "!TARGET_MB_64" + { + switch (which_alternative) + { +@@ -1182,7 +1276,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))" ++ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] +@@ -1194,12 +1289,22 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") + ++(define_insn "movdi_long_int" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") ++ (match_operand:DI 1 "general_operand" "i"))] ++ "" ++ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) ++ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. +@@ -1271,6 +1376,8 @@ + (set_attr "length" "4,4,8,4,8,4,8")]) + + ++ ++ + ;; 16-bit Integer moves + + ;; Unlike most other insns, the move insns can't be split with +@@ -1303,8 +1410,8 @@ + "@ + addik\t%0,r0,%1\t# %X1 + addk\t%0,%1,r0 +- lhui\t%0,%1 +- lhui\t%0,%1 ++ lhu%i1\t%0,%1 ++ lhu%i1\t%0,%1 + sh%i0\t%z1,%0 + sh%i0\t%z1,%0" + [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") +@@ -1347,7 +1454,7 @@ + lbu%i1\t%0,%1 + lbu%i1\t%0,%1 + sb%i0\t%z1,%0 +- sbi\t%z1,%0" ++ sb%i0\t%z1,%0" + [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") + (set_attr "mode" "QI") + (set_attr "length" "4,4,8,4,8,4,8")]) +@@ -1420,7 +1527,7 @@ + addik\t%0,r0,%F1 + lw%i1\t%0,%1 + sw%i0\t%z1,%0 +- swi\t%z1,%0" ++ sw%i0\t%z1,%0" + [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") + (set_attr "mode" "SF") + (set_attr "length" "4,4,4,4,4,4,4")]) +@@ -1459,6 +1566,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") + (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] +@@ -1493,7 +1627,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] + "") +@@ -1504,7 +1639,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") +@@ -2003,6 +2139,31 @@ else + " + ) + ++ ++(define_insn "seq_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (eq:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmpleq\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "sne_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (ne:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmplne\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ + (define_insn "seq_internal_pat" + [(set (match_operand:SI 0 "register_operand" "=d") + (eq:SI +@@ -2063,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "arith_operand" "I,i")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +@@ -2076,13 +2237,13 @@ else + (define_expand "cbranchsi4_reg" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "register_operand")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "register_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" + { +- microblaze_expand_conditional_branch_reg (SImode, operands); ++ microblaze_expand_conditional_branch_reg (Pmode, operands); + DONE; + }) + +@@ -2107,6 +2268,26 @@ else + (label_ref (match_operand 1)) + (pc)))]) + ++(define_insn "branch_zero64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand 2 "pc_or_label_operand" "") ++ (match_operand 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ + (define_insn "branch_zero" + [(set (pc) + (if_then_else (match_operator:SI 0 "ordered_comparison_operator" +@@ -2127,6 +2308,47 @@ else + (set_attr "length" "4")] + ) + ++(define_insn "branch_compare64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:SI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmp\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmpu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmp\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmpu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); ++ return "bea%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2310,7 +2532,7 @@ else + ;; Indirect jumps. Jump to register values. Assuming absolute jumps + + (define_insn "indirect_jump_internal1" +- [(set (pc) (match_operand:SI 0 "register_operand" "d"))] ++ [(set (pc) (match_operand 0 "register_operand" "d"))] + "" + "bra%?\t%0" + [(set_attr "type" "jump") +@@ -2323,7 +2545,7 @@ else + (use (label_ref (match_operand 1 "" "")))] + "" + { +- gcc_assert (GET_MODE (operands[0]) == Pmode); ++ //gcc_assert (GET_MODE (operands[0]) == Pmode); + + if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +@@ -2335,7 +2557,7 @@ else + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand:SI 0 "register_operand" "d")) ++ (match_operand 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2345,9 +2567,9 @@ else + + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus:SI (match_operand:SI 0 "register_operand" "d") +- (label_ref:SI (match_operand:SI 1 "" "")))) +- (use (label_ref:SI (match_dup 1)))])] ++ (plus (match_operand 0 "register_operand" "d") ++ (label_ref (match_operand:SI 1 "" "")))) ++ (use (label_ref (match_dup 1)))])] + "" + "" + ) +@@ -2408,7 +2630,7 @@ else + (minus (reg 1) (match_operand 1 "register_operand" ""))) + (set (reg 1) + (minus (reg 1) (match_dup 1)))] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx reg = gen_reg_rtx (Pmode); +@@ -2433,7 +2655,7 @@ else + (define_expand "save_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + emit_move_insn (operands[0], operands[1]); + DONE; +@@ -2443,7 +2665,7 @@ else + (define_expand "restore_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx rtmp = gen_rtx_REG (SImode, R_TMP); +@@ -2490,7 +2712,7 @@ else + + (define_insn "_internal" + [(any_return) +- (use (match_operand:SI 0 "register_operand" ""))] ++ (use (match_operand 0 "register_operand" ""))] + "" + { + if (microblaze_is_break_handler ()) +@@ -2523,7 +2745,7 @@ else + (define_expand "call" + [(parallel [(call (match_operand 0 "memory_operand" "m") + (match_operand 1 "" "i")) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 2 "" "")) + (use (match_operand 3 "" ""))])] + "" +@@ -2544,12 +2766,12 @@ else + + if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) + emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_internal0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2559,7 +2781,7 @@ else + (define_expand "call_internal0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" ""))])] ++ (clobber (match_operand 2 "" ""))])] + "" + { + } +@@ -2568,18 +2790,34 @@ else + (define_expand "call_internal_plt0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" "")) +- (use (match_operand:SI 3 "" ""))])] ++ (clobber (match_operand 2 "" "")) ++ (use (match_operand 3 "" ""))])] + "" + { + } + ) + ++(define_insn "call_internal_plt_64" ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal_plt" +- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" "")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR)) +- (use (reg:SI R_GOT))] ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] + "flag_pic" + { + register rtx target2 = gen_rtx_REG (Pmode, +@@ -2591,10 +2829,41 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_internal1_64" ++ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[0]; ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ if (GET_CODE (target) == SYMBOL_REF) { ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "breaki\tr16,%0\;%#"; ++ } ++ else { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ } else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%0\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%0\;%#"; ++ else { ++ fprintf (stderr,"Unsupported call insn\n"); ++ return NULL; ++ } ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal1" + [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR))] ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] + "" + { + register rtx target = operands[0]; +@@ -2628,7 +2897,7 @@ else + [(parallel [(set (match_operand 0 "register_operand" "=d") + (call (match_operand 1 "memory_operand" "m") + (match_operand 2 "" "i"))) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 3 "" ""))])] ;; next_arg_reg + "" + { +@@ -2649,13 +2918,13 @@ else + if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) + emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_value_internal (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2667,7 +2936,7 @@ else + [(parallel [(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) ++ (clobber (match_operand 3 "" "")) + ])] + "" + {} +@@ -2677,18 +2946,35 @@ else + [(parallel[(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) +- (use (match_operand:SI 4 "" ""))])] ++ (clobber (match_operand 3 "" "")) ++ (use (match_operand 4 "" ""))])] + "flag_pic" + {} + ) + ++(define_insn "call_value_intern_plt_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ return "brealid\tr15,%1\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern_plt" + [(set (match_operand:VOID 0 "register_operand" "=d") +- (call (mem (match_operand:SI 1 "call_insn_plt_operand" "")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d")) +- (use (match_operand:SI 4 "register_operand"))] ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] + "flag_pic" + { + register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); +@@ -2700,11 +2986,46 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_value_intern_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[1]; ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ if (GET_CODE (target) == SYMBOL_REF) ++ { ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) ++ return "breaki\tr16,%1\;%#"; ++ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION) ++ { ++ return "brealid\tr15,%1\;%#"; ++ } ++ else ++ { ++ return "bralid\tr15,%1\;%#"; ++ } ++ } ++ else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%1\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%1\;%#"; ++ else ++ return "Unsupported call insn\n"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern" + [(set (match_operand:VOID 0 "register_operand" "=d") + (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d"))] ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] + "" + { + register rtx target = operands[1]; +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index e9a1921ae26..9fc80b142ce 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -2,7 +2,8 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en + MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian + MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index f9bafaf3aa5..bc69d890370 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -40,7 +40,7 @@ + + .align 2 + __init: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 + la r11, r0, _stack + mts rshr, r11 +@@ -51,5 +51,5 @@ __init: + .global __fini + .align 2 + __fini: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index 0260e432371..1a1f0a8e0f3 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -33,9 +33,9 @@ + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 + + .section .fini, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 +diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S +new file mode 100644 +index 00000000000..d37bf5165c6 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3.S +@@ -0,0 +1,98 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# divdi3.S ++# ++# Divide operation for 32 bit integers. ++# Input : Dividend in Reg r5 ++# Divisor in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __divdi3 ++ .ent __divdi3 ++ .type __divdi3,@function ++__divdi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ XORL r28,r5,r6 # Get the sign of the result ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r30,r0,0 # Clear mod ++ ADDLIK r3,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ RSUBLI r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ nop ++.end __divdi3 ++ .size __divdi3, . - __divdi3 ++#endif +diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c +new file mode 100644 +index 00000000000..80962597ea5 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3_table.c +@@ -0,0 +1,62 @@ ++/* Table for software lookup divide for Xilinx MicroBlaze. ++ ++ Copyright (C) 2009-2017 Free Software Foundation, Inc. ++ ++ Contributed by Michael Eager . ++ ++ This file is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by the ++ Free Software Foundation; either version 3, or (at your option) any ++ later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++ ++unsigned char _divdi3_table[] = ++{ ++ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7, ++ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15, ++ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ++ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15, ++ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7, ++ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15, ++ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7, ++ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15, ++ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7, ++ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15, ++ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7, ++ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15, ++ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7, ++ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15, ++ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7, ++ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15, ++ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7, ++ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15, ++ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7, ++ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15, ++ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7, ++ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15, ++ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7, ++ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15, ++ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7, ++ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15, ++ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7, ++ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15, ++ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7, ++ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15, ++ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7, ++ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15, ++}; ++ +diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S +new file mode 100644 +index 00000000000..5d3f7c03fc8 +--- /dev/null ++++ b/libgcc/config/microblaze/moddi3.S +@@ -0,0 +1,97 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# moddi3.S ++# ++# modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __moddi3 ++ .ent __moddi3 ++ .type __moddi3,@function ++__moddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,32 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r3,r0,0 # Clear mod ++ ADDLIK r30,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++ # First part try to find the first '1' in the r5 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r30 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ rsubli r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addlik r1,r1,32 ++ rtsd r15,8 ++ nop ++ .end __moddi3 ++ .size __moddi3, . - __moddi3 ++#endif +diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S +new file mode 100644 +index 00000000000..567784197d3 +--- /dev/null ++++ b/libgcc/config/microblaze/muldi3.S +@@ -0,0 +1,73 @@ ++/*###################################-*-asm*- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# muldi3.S ++# ++# Multiply operation for 32 bit integers. ++# Input : Operand1 in Reg r5 ++# Operand2 in Reg r6 ++# Output: Result [op1 * op2] in Reg r3 ++# ++#######################################*/ ++ ++#ifdef __arch64__ ++ .globl __muldi3 ++ .ent __muldi3 ++ .type __muldi3,@function ++__muldi3: ++ .frame r1,0,r15 ++ addl r3,r0,r0 ++ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ XORL r4,r5,r6 # Get the sign of the result ++ BEALGEI r5,$L_R5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEALGEI r6,$L_R6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ addl r5,r5,r5 ++$L1: ++ srll r6,r6 ++ addlc r7,r0,r0 ++ bealeqi r7,$L2 ++ addl r3,r3,r5 ++ bealnei r6,$L2 ++ beallti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rsubl r3,r3,r0 ++ rtsd r15,8 ++ nop ++$L_Result_Is_Zero: ++ addli r3,r0,0 ++ rtsd r15,8 ++ nop ++ .end __muldi3 ++ .size __muldi3, . - __muldi3 ++#endif +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 8d954a49575..35021b24b7d 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,11 +1,16 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ ++ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ ++ $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/muldi3_hard.S \ ++ $(srcdir)/config/microblaze/moddi3.S \ + $(srcdir)/config/microblaze/mulsi3.S \ ++ $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ ++ $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c ++ $(srcdir)/config/microblaze/umoddi3.S \ ++ $(srcdir)/config/microblaze/divsi3_table.c \ +diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S +new file mode 100644 +index 00000000000..c210fbc7128 +--- /dev/null ++++ b/libgcc/config/microblaze/udivdi3.S +@@ -0,0 +1,107 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# udivdi3.S ++# ++# Unsigned divide operation. ++# Input : Divisor in Reg r5 ++# Dividend in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __udivdi3 ++ .ent __udivdi3 ++ .type __udivdi3,@function ++__udivdi3: ++ .frame r1,0,r15 ++ ++ ADDlIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r30,r0,0 # Clear mod ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # Check if r6 and r5 are equal # if yes, return 1 ++ RSUBL r18,r5,r6 ++ ADDLIK r3,r0,1 ++ BEALEQI r18,$LaRETURN_HERE ++ ++ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 ++ XORL r18,r5,r6 ++ ADDL r3,r0,r0 # We would anyways clear r3 ++ BEALGEI r18,$LRSUBL ++ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++$LRSUBL: ++ RSUBL r18,r6,r5 # MICROBLAZEcmp ++ BEALLTI r18,$LaRETURN_HERE ++ ++ # If r6 [bit 31] is set, then return result as 1 ++$LCheckr6: ++ BEALGTI r6,$LaDIV0 ++ ADDLIK r3,r0,1 ++ BREAI $LaRETURN_HERE ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDLIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++ .end __udivdi3 ++ .size __udivdi3, . - __udivdi3 ++#endif +diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S +new file mode 100644 +index 00000000000..7f5cd23f9a1 +--- /dev/null ++++ b/libgcc/config/microblaze/umoddi3.S +@@ -0,0 +1,110 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager . ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# . ++# ++# umoddi3.S ++# ++# Unsigned modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __umoddi3 ++ .ent __umoddi3 ++ .type __umoddi3,@function ++__umoddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-24 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r3,r0,0 # Clear div ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r30,r0,0 # clear mod ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++# Check if r6 and r5 are equal # if yes, return 0 ++ rsubl r18,r5,r6 ++ bealeqi r18,$LaRETURN_HERE ++ ++# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 ++ xorl r18,r5,r6 ++ addlik r3,r5,0 ++ bealgei r18,$LRSUB ++ beallti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++$LRSUB: ++ rsubl r18,r5,r6 # MICROBLAZEcmp ++ bealgti r18,$LaRETURN_HERE ++ ++# If r6 [bit 31] is set, then return result as r5-r6 ++$LCheckr6: ++ addlik r3,r0,0 ++ bealgti r6,$LaDIV0 ++ addlik r18,r0,0x7fffffff ++ andl r5,r5,r18 ++ andl r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsubl r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++.end __umoddi3 ++ .size __umoddi3, . - __umoddi3 ++#endif +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-re-arrangement-of-the-compare-branches.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-re-arrangement-of-the-compare-branches.patch new file mode 100644 index 00000000..19605270 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0029-re-arrangement-of-the-compare-branches.patch @@ -0,0 +1,268 @@ +From 5b31cd986c75c5f479967b8f9c1b4ac1fc322b1a Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 3 Aug 2018 15:41:39 +0530 +Subject: [PATCH 29/53] re-arrangement of the compare branches + +--- + gcc/config/microblaze/microblaze.c | 28 ++---- + gcc/config/microblaze/microblaze.md | 141 +++++++++++++--------------- + 2 files changed, 73 insertions(+), 96 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index f59a71ac072..e33e1bc1482 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3697,11 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == Pmode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); +- ++ emit_jump_insn (gen_condjump (condition, label1)); + } + + else if (code == EQ || code == NE) +@@ -3712,10 +3708,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + else + emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3748,10 +3741,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), + mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else if (code == EQ) + { +@@ -3766,10 +3756,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + + } + else if (code == NE) +@@ -3785,10 +3772,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_NE (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3830,7 +3814,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); + condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); +- emit_jump_insn (gen_long_condjump (condition, operands[3])); ++ emit_jump_insn (gen_condjump (condition, operands[3])); + } + + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 7bc91602ca2..ddf01505bd8 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2268,7 +2268,27 @@ else + (label_ref (match_operand 1)) + (pc)))]) + +-(define_insn "branch_zero64" ++(define_insn "branch_zero_64" ++ [(set (pc) ++ (if_then_else (match_operator:SI 0 "ordered_comparison_operator" ++ [(match_operand:SI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:SI 2 "pc_or_label_operand" "") ++ (match_operand:SI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_zero" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand 1 "register_operand" "d") +@@ -2279,9 +2299,9 @@ else + "TARGET_MB_64" + { + if (operands[3] == pc_rtx) +- return "bea%C0i%?\t%z1,%2"; ++ return "beal%C0i%?\t%z1,%2"; + else +- return "bea%N0i%?\t%z1,%3"; ++ return "beal%N0i%?\t%z1,%3"; + } + [(set_attr "type" "branch") + (set_attr "mode" "none") +@@ -2310,9 +2330,9 @@ else + + (define_insn "branch_compare64" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:SI 0 "cmp_op" ++ [(match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2349,6 +2369,47 @@ else + (set_attr "length" "12")] + ) + ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2431,74 +2492,6 @@ else + + }) + +-;; Used to implement comparison instructions +-(define_expand "long_condjump" +- [(set (pc) +- (if_then_else (match_operand 0) +- (label_ref (match_operand 1)) +- (pc)))]) +- +-(define_insn "long_branch_zero" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "ordered_comparison_operator" +- [(match_operand:DI 1 "register_operand" "d") +- (const_int 0)]) +- (match_operand:DI 2 "pc_or_label_operand" "") +- (match_operand:DI 3 "pc_or_label_operand" ""))) +- ] +- "TARGET_MB_64" +- { +- if (operands[3] == pc_rtx) +- return "beal%C0i%?\t%z1,%2"; +- else +- return "beal%N0i%?\t%z1,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "4")] +-) +- +-(define_insn "long_branch_compare" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "cmp_op" +- [(match_operand:DI 1 "register_operand" "d") +- (match_operand:DI 2 "register_operand" "d") +- ]) +- (label_ref (match_operand 3)) +- (pc))) +- (clobber(reg:DI R_TMP))] +- "TARGET_MB_64" +- { +- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); +- enum rtx_code code = GET_CODE (operands[0]); +- +- if (code == GT || code == LE) +- { +- output_asm_insn ("cmpl\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GTU || code == LEU) +- { +- output_asm_insn ("cmplu\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GE || code == LT) +- { +- output_asm_insn ("cmpl\tr18,%z2,%z1", operands); +- } +- else if (code == GEU || code == LTU) +- { +- output_asm_insn ("cmplu\tr18,%z2,%z1", operands); +- } +- +- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); +- return "beal%C0i%?\tr18,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "12")] +-) +- + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch new file mode 100644 index 00000000..528fef0c --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch @@ -0,0 +1,28 @@ +From 37af05f1ea7dc8476057580944a236f135babaf8 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 8 Aug 2018 17:37:26 +0530 +Subject: [PATCH 30/53] [Patch,Microblaze] : previous commit broke the + handling of SI Branch compare for Microblaze 32-bit.. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index ddf01505bd8..87158066562 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2224,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand 1 "register_operand") +- (match_operand 2 "arith_operand" "I,i")]) ++ [(match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch new file mode 100644 index 00000000..c247120b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch @@ -0,0 +1,73 @@ +From 397a532bd80e21682ca3b5e230949f66c5b9ad30 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 11 Sep 2018 13:43:48 +0530 +Subject: [PATCH 31/53] [Patch, Microblaze] : Support of multilibs with m64 ... + +--- + gcc/config/microblaze/microblaze-c.c | 1 + + gcc/config/microblaze/t-microblaze | 15 ++++++--------- + libgcc/config/microblaze/t-microblaze | 11 +++-------- + 3 files changed, 10 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c +index 2dcb879992c..50d01feb670 100644 +--- a/gcc/config/microblaze/microblaze-c.c ++++ b/gcc/config/microblaze/microblaze-c.c +@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) + } + if (TARGET_MB_64) + { ++ builtin_define ("__microblaze64"); + builtin_define ("__arch64__"); + builtin_define ("__microblaze64__"); + builtin_define ("__MICROBLAZE64__"); +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 9fc80b142ce..35ab9654052 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,12 +1,9 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 +-MULTILIB_DIRNAMES = bs m mh le m64 +-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high +-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high ++MULTILIB_DIRNAMES = m64 bs le m mh ++MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 35021b24b7d..8d954a49575 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,16 +1,11 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ +- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ +- $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/moddi3.S \ ++ $(srcdir)/config/microblaze/muldi3_hard.S \ + $(srcdir)/config/microblaze/mulsi3.S \ +- $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ +- $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/umoddi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c \ ++ $(srcdir)/config/microblaze/divsi3_table.c +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Fixed-issues-like.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Fixed-issues-like.patch new file mode 100644 index 00000000..9f5381af --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0032-Fixed-issues-like.patch @@ -0,0 +1,70 @@ +From c03a994475d8894ae0913dd3534e72bfb389aa28 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 11 Sep 2018 14:58:00 +0530 +Subject: [PATCH 32/53] Fixed issues like: 1 Interrupt alignment issue 2 Sign + extension issue + +--- + gcc/config/microblaze/microblaze.c | 16 ++++++++++------ + gcc/config/microblaze/microblaze.md | 2 +- + 2 files changed, 11 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index e33e1bc1482..64b948d6cfc 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2177,9 +2177,14 @@ compute_frame_size (HOST_WIDE_INT size) + + total_size += gp_reg_size; + +- /* Add 4 bytes for MSR. */ ++ /* Add 4/8 bytes for MSR. */ + if (microblaze_is_interrupt_variant ()) +- total_size += 4; ++ { ++ if (TARGET_MB_64) ++ total_size += 8; ++ else ++ total_size += 4; ++ } + + /* No space to be allocated for link register in leaf functions with no other + stack requirements. */ +@@ -2464,7 +2469,6 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; +- int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2479,10 +2483,10 @@ print_operand (FILE * file, rtx op, int letter) + } + else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val1[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); + } + else if (code == CONST_DOUBLE) + { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 87158066562..b154d15c34c 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1096,7 +1096,7 @@ + case 1: + case 2: + { +- output_asm_insn ("ll%i1\t%0,%1", operands); ++ output_asm_insn ("lw%i1\t%0,%1", operands); + return "sextl32\t%0,%0"; + } + } +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Fixed-below-issues.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Fixed-below-issues.patch new file mode 100644 index 00000000..3a4b2037 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0033-Fixed-below-issues.patch @@ -0,0 +1,307 @@ +From 844daa118a8f376e5a53040fc953c86e70d34140 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 26 Nov 2019 17:26:15 +0530 +Subject: [PATCH 33/53] Fixed below issues: + +- Floating point print issues in 64bit mode +- Dejagnu Jump related issues +- Added dbl instruction + +Conflicts: + gcc/config/microblaze/microblaze.md +--- + gcc/config/microblaze/microblaze.c | 12 +++- + gcc/config/microblaze/microblaze.h | 7 +++ + gcc/config/microblaze/microblaze.md | 86 ++++++++++++++++++++++++----- + libgcc/config/microblaze/crti.S | 24 +++++++- + libgcc/config/microblaze/crtn.S | 13 +++++ + 5 files changed, 125 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 64b948d6cfc..b2cd89a310a 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2473,7 +2473,12 @@ print_operand (FILE * file, rtx op, int letter) + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) +- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ { ++ if (TARGET_MB_64) ++ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ else ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ } + else + { + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); +@@ -3876,7 +3881,10 @@ microblaze_expand_divide (rtx operands[]) + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); +- jump = emit_jump_insn_after (gen_jump (div_end_label), insn); ++ if (TARGET_MB_64) ++ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn); ++ else ++ jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; + emit_barrier (); +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 94ac736221c..17bf470c95b 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -888,10 +888,17 @@ do { \ + /* We do this to save a few 10s of code space that would be taken up + by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION + definition in crtstuff.c. */ ++#ifdef __arch64__ ++#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ ++ asm ( SECTION_OP "\n" \ ++ "\tbrealid r15, " #FUNC "\n\t nop\n" \ ++ TEXT_SECTION_ASM_OP); ++#else + #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ + asm ( SECTION_OP "\n" \ + "\tbrlid r15, " #FUNC "\n\t nop\n" \ + TEXT_SECTION_ASM_OP); ++#endif + + /* We need to group -lm as well, since some Newlib math functions + reference __errno! */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index b154d15c34c..7d6cf263eb6 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -527,6 +527,15 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "floatdidf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (float:DF (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dbl\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +@@ -1299,7 +1308,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "" ++ "TARGET_MB_64" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1582,7 +1591,7 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -2371,9 +2380,9 @@ else + + (define_insn "long_branch_compare" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2495,6 +2504,20 @@ else + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- ++(define_insn "jump_64" ++ [(set (pc) ++ (label_ref (match_operand 0 "" "")))] ++ "TARGET_MB_64" ++ { ++ if (GET_CODE (operands[0]) == REG) ++ return "brea%?\t%0"; ++ else ++ return "breai%?\t%l0"; ++ } ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] +@@ -2540,17 +2563,25 @@ else + { + //gcc_assert (GET_MODE (operands[0]) == Pmode); + +- if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) +- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +- else +- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); ++ } ++ else { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); ++ } + DONE; + } + ) + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand 0 "register_operand" "d")) ++ (match_operand:SI 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2558,11 +2589,21 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "tablejump_internal2" ++ [(set (pc) ++ (match_operand:DI 0 "register_operand" "d")) ++ (use (label_ref (match_operand 1 "" "")))] ++ "TARGET_MB_64" ++ "bra%?\t%0 " ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus (match_operand 0 "register_operand" "d") +- (label_ref (match_operand:SI 1 "" "")))) +- (use (label_ref (match_dup 1)))])] ++ (plus:SI (match_operand:SI 0 "register_operand" "d") ++ (label_ref:SI (match_operand:SI 1 "" "")))) ++ (use (label_ref:SI (match_dup 1)))])] + "" + "" + ) +@@ -2593,6 +2634,23 @@ else + "" + ) + ++(define_insn "" ++ [(set (pc) ++ (plus:DI (match_operand:DI 0 "register_operand" "d") ++ (label_ref:DI (match_operand 1 "" "")))) ++ (use (label_ref:DI (match_dup 1)))] ++ "TARGET_MB_64 && NEXT_INSN (as_a (operands[1])) != 0 ++ && GET_CODE (PATTERN (NEXT_INSN (as_a (operands[1])))) == ADDR_DIFF_VEC ++ && flag_pic" ++ { ++ output_asm_insn ("addlk\t%0,%0,r20",operands); ++ return "bra%?\t%0"; ++} ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ ++ + ;;---------------------------------------------------------------- + ;; Function prologue/epilogue and stack allocation + ;;---------------------------------------------------------------- +@@ -3099,7 +3157,7 @@ else + ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference + ;; between "mfs" and "addik" instructions. + (define_insn "set_got" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))] + "" + "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index bc69d890370..7400eeb2e3b 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -33,11 +33,32 @@ + .section .init, "ax" + .global __init + ++#ifdef __arch64__ + .weak _stack +- .set _stack, 0xffffffff ++ .set _stack, 0xffffffffffffffff + .weak _stack_end + .set _stack_end, 0 + ++ .align 3 ++__init: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++ addlik r11, r0, _stack ++ mts rshr, r11 ++ addlik r11, r0, _stack_end ++ mts rslr, r11 ++ ++ .section .fini, "ax" ++ .global __fini ++ .align 3 ++__fini: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++#else ++ .weak _stack ++ .set _stack, 0xffffffff ++ .weak _stack_end ++ .set _stack_end, 0 + .align 2 + __init: + addik r1, r1, -16 +@@ -53,3 +74,4 @@ __init: + __fini: + addik r1, r1, -16 + sw r15, r0, r1 ++#endif +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index 1a1f0a8e0f3..14d9a084e3e 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -29,7 +29,19 @@ + .section .note.GNU-stack,"",%progbits + .previous + #endif ++#ifdef __arch64__ ++ .section .init, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop + ++ .section .fini, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop ++#else + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +@@ -39,3 +51,4 @@ + lw r15, r0, r1 + rtsd r15, 8 + addik r1, r1, 16 ++#endif +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch new file mode 100644 index 00000000..293c9f90 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0034-Added-double-arith-instructions.patch @@ -0,0 +1,135 @@ +From 93874549e864b39689060edda456c897ea0fac4e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 9 Oct 2018 10:07:08 +0530 +Subject: [PATCH 34/53] -Added double arith instructions -Fixed prologue stack + pointer decrement issue + +--- + gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++---- + gcc/config/microblaze/t-microblaze | 7 +++ + 2 files changed, 76 insertions(+), 9 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 7d6cf263eb6..943037336f1 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -527,6 +527,66 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "fix_truncsfsi2" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (fix:SI (match_operand:SF 1 "register_operand" "d")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" ++ "fint\t%0,%1" ++ [(set_attr "type" "fint") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "adddf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (plus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dadd\t%0,%1,%2" ++ [(set_attr "type" "fadd") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "subdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (minus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "drsub\t%0,%2,%1" ++ [(set_attr "type" "frsub") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "muldf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (mult:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dmul\t%0,%1,%2" ++ [(set_attr "type" "fmul") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "divdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (div:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "ddiv\t%0,%2,%1" ++ [(set_attr "type" "fdiv") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dsqrt\t%0,%1" ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +@@ -536,13 +596,13 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "fix_truncsfsi2" +- [(set (match_operand:SI 0 "register_operand" "=d") +- (fix:SI (match_operand:SF 1 "register_operand" "d")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" +- "fint\t%0,%1" +- [(set_attr "type" "fint") +- (set_attr "mode" "SF") ++(define_insn "floatdfdi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dlong\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DI") + (set_attr "length" "4")]) + + ;;---------------------------------------------------------------- +@@ -660,8 +720,8 @@ + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addik\t%0,%z1,-%2 +- addik\t%0,%z1,-%2" ++ addlik\t%0,%z1,-%2 ++ addlik\t%0,%z1,-%2" + [(set_attr "type" "arith,no_delay_arith,no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4,4,4")]) +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 35ab9654052..dfef45c268e 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,6 +1,13 @@ + MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high + MULTILIB_DIRNAMES = m64 bs le m mh + MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64 ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch new file mode 100644 index 00000000..6135b952 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch @@ -0,0 +1,37 @@ +From 8c359136e4b5ca105946b259212ed4bac0a69a9e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 12 Oct 2018 16:07:36 +0530 +Subject: [PATCH 35/53] Fixed the issue in the delay slot with swap + instructions + +--- + gcc/config/microblaze/microblaze.md | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 943037336f1..162c6231a86 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -443,6 +443,9 @@ + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_REORDER" + "swapb %0, %1" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")] + ) + + (define_insn "bswaphi2" +@@ -451,6 +454,9 @@ + "TARGET_REORDER" + "swapb %0, %1 + swaph %0, %0" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "8")] + ) + + ;;---------------------------------------------------------------- +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch new file mode 100644 index 00000000..23b640a6 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch @@ -0,0 +1,256 @@ +From 08ca1c1550145a8bddbd03a594620db13a259238 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Sat, 13 Oct 2018 21:12:43 +0530 +Subject: [PATCH 36/53] Fixed the load store issue with the 32bit arith + libraries + +--- + libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++- + libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++- + libgcc/config/microblaze/mulsi3.S | 3 +++ + libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++- + libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++- + 5 files changed, 98 insertions(+), 4 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index 886a4f2bb36..3a7fc4d6122 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -41,6 +41,17 @@ + .globl __divsi3 + .ent __divsi3 + .type __divsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__divsi3: ++ .frame r1,0,r15 ++ ++ ADDIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++#else + __divsi3: + .frame r1,0,r15 + +@@ -49,7 +60,7 @@ __divsi3: + SWI r29,r1,4 + SWI r30,r1,8 + SWI r31,r1,12 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEID r5,$LaR5_Pos +@@ -89,6 +100,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r28,r1,0 +@@ -97,6 +119,7 @@ $LaRETURN_HERE: + LWI r31,r1,12 + RTSD r15,8 + ADDIK r1,r1,16 ++#endif + .end __divsi3 + .size __divsi3, . - __divsi3 + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 2c4f39a045f..3e405ea6267 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -41,6 +41,17 @@ + .globl __modsi3 + .ent __modsi3 + .type __modsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__modsi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,24 ++#else + __modsi3: + .frame r1,0,r15 + +@@ -49,6 +60,7 @@ __modsi3: + swi r29,r1,4 + swi r30,r1,8 + swi r31,r1,12 ++#endif + + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero +@@ -88,6 +100,18 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addik r1,r1,32 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r28,r1,0 +@@ -95,7 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 +- addik r1,r1,16 ++#endif + .end __modsi3 + .size __modsi3, . - __modsi3 + +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index c50a380177a..0329fa3037a 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -41,6 +41,9 @@ + .globl __mulsi3 + .ent __mulsi3 + .type __mulsi3,@function ++#ifdef __arch64__ ++ .align 3 ++#endif + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 1bf73265b98..7bdcd8873e5 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -41,6 +41,16 @@ + .globl __udivsi3 + .ent __udivsi3 + .type __udivsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__udivsi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++#else + __udivsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __udivsi3: + SWI r29,r1,0 + SWI r30,r1,4 + SWI r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero + ADDIK r30,r0,0 # Clear mod +@@ -98,6 +108,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r29,r1,0 +@@ -105,5 +126,6 @@ $LaRETURN_HERE: + LWI r31,r1,8 + RTSD r15,8 + ADDIK r1,r1,12 ++#endif + .end __udivsi3 + .size __udivsi3, . - __udivsi3 +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 2bc0909605f..7d1e4484a53 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -41,6 +41,16 @@ + .globl __umodsi3 + .ent __umodsi3 + .type __umodsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__umodsi3: ++ .frame r1,0,r15 ++ ++ addik r1,r1,-24 ++ swi r29,r1,0 ++ swi r30,r1,8 ++ swi r31,r1,16 ++#else + __umodsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __umodsi3: + swi r29,r1,0 + swi r30,r1,4 + swi r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero + ADDIK r3,r0,0 # Clear div +@@ -101,6 +111,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r29,r1,0 +@@ -108,5 +129,6 @@ $LaRETURN_HERE: + lwi r31,r1,8 + rtsd r15,8 + addik r1,r1,12 ++#endif + .end __umodsi3 + .size __umodsi3, . - __umodsi3 +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch new file mode 100644 index 00000000..3f0ec920 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch @@ -0,0 +1,25 @@ +From 3fbf3d7049cccb5ddec02e3360f1b4da0eb5a177 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Mon, 15 Oct 2018 12:00:10 +0530 +Subject: [PATCH 37/53] extending the Dwarf support to 64bit Microblaze + +--- + gcc/config/microblaze/microblaze.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 17bf470c95b..b0c44c4fd50 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; + /* Use DWARF 2 debugging information by default. */ + #define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +-#define DWARF2_ADDR_SIZE 4 ++#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4) + + /* Target machine storage layout */ + +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch new file mode 100644 index 00000000..0f91a572 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0038-fixing-the-typo-errors-in-umodsi3-file.patch @@ -0,0 +1,29 @@ +From 23c8d1d396c7ae5e478c793b72fddcec80dfd083 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Tue, 16 Oct 2018 07:55:46 +0530 +Subject: [PATCH 38/53] fixing the typo errors in umodsi3 file + +--- + libgcc/config/microblaze/umodsi3.S | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 7d1e4484a53..63ab1c2a357 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -47,9 +47,9 @@ __umodsi3: + .frame r1,0,r15 + + addik r1,r1,-24 +- swi r29,r1,0 +- swi r30,r1,8 +- swi r31,r1,16 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 + #else + __umodsi3: + .frame r1,0,r15 +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch new file mode 100644 index 00000000..6aa6937f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch @@ -0,0 +1,68 @@ +From cc2c7e5255edc97064d29880f156d603d3ec740a Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Wed, 17 Oct 2018 16:56:14 +0530 +Subject: [PATCH 39/53] fixing the 32bit LTO related issue9(1014024) + +--- + gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- + 1 file changed, 14 insertions(+), 10 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index b0c44c4fd50..c6c3a9baa5a 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +-/* +-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ +- if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ +- (MODE) = TARGET_MB_64 ? DImode : SImode; +-*/ ++ ++#ifndef __arch64__ ++#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ ++ if (GET_MODE_CLASS (MODE) == MODE_INT \ ++ && GET_MODE_SIZE (MODE) < 4) \ ++ (MODE) = SImode; ++#endif ++ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info; + + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + ++#ifdef __aarch64__ + #define LIBCALL_VALUE(MODE) \ + gen_rtx_REG (MODE,GP_RETURN) +- +-/*#define LIBCALL_VALUE(MODE) \ ++#else ++#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +-*/ ++#endif ++ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -518,7 +522,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 64 ++#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch new file mode 100644 index 00000000..e086a851 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch @@ -0,0 +1,25 @@ +From 7d245c4d22c5c845666f33f19d23c075dcae2af6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 19 Oct 2018 14:26:25 +0530 +Subject: [PATCH 40/53] Fixed the missing stack adjustment in prologue of + modsi3 function + +--- + libgcc/config/microblaze/modsi3.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 3e405ea6267..c98442c01c2 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -119,6 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 ++ addik r1,r1,16 + #endif + .end __modsi3 + .size __modsi3, . - __modsi3 +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch new file mode 100644 index 00000000..b3b04ae7 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch @@ -0,0 +1,29 @@ +From 4de570fde0740cbcfea443aea24c2cfc9df5a876 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 24 Oct 2018 18:31:04 +0530 +Subject: [PATCH 41/53] [Patch,Microblaze] : corrected SPN for dlong + instruction mapping. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 162c6231a86..f62ad28130b 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -602,9 +602,9 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "floatdfdi2" ++(define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") +- (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] + "TARGET_MB_64" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch new file mode 100644 index 00000000..29e8d753 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -0,0 +1,59 @@ +From b2d05f4ad5c66fb8cec37064a77d21194db9dd32 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Thu, 29 Nov 2018 17:55:08 +0530 +Subject: [PATCH 42/53] fixing the long & long long mingw toolchain issue + +--- + gcc/config/microblaze/constraints.md | 2 +- + gcc/config/microblaze/microblaze.md | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index 0a4d5269314..e3f89491fb4 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -55,7 +55,7 @@ + (define_constraint "K" + "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) ++ (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) + + + ;; Define floating point constraints +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index f62ad28130b..74be0728e75 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -648,8 +648,8 @@ + if (TARGET_MB_64) + { + if (GET_CODE (operands[2]) == CONST_INT && +- INTVAL(operands[2]) < (long)-549755813888 && +- INTVAL(operands[2]) > (long)549755813887) ++ INTVAL(operands[2]) < (long long)-549755813888 && ++ INTVAL(operands[2]) > (long long)549755813887) + FAIL; + } + }) +@@ -1264,7 +1264,7 @@ + (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] + "TARGET_MB_64 && (register_operand (operands[0], DImode) && + (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" ++ (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" + "@ + addlk\t%0,r0,r0\t + addlik\t%0,r0,%1\t #N1 %X1 +@@ -1298,7 +1298,7 @@ + case 1: + case 2: + if (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) ++ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) + return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + else + return "addlik\t%0,r0,%1"; +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch new file mode 100644 index 00000000..4fcf90c8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch @@ -0,0 +1,47 @@ +From 3691860b698107ce5338468cbef932c63d195961 Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Thu, 14 Mar 2019 18:11:04 +0530 +Subject: [PATCH 43/53] Fix the MB-64 bug of handling QI objects + +--- + gcc/config/microblaze/microblaze.md | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 74be0728e75..fed6f5e0234 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2345,11 +2345,11 @@ else + + (define_insn "branch_zero_64" + [(set (pc) +- (if_then_else (match_operator:SI 0 "ordered_comparison_operator" ++ (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand:SI 1 "register_operand" "d") + (const_int 0)]) +- (match_operand:SI 2 "pc_or_label_operand" "") +- (match_operand:SI 3 "pc_or_label_operand" ""))) ++ (match_operand 2 "pc_or_label_operand" "") ++ (match_operand 3 "pc_or_label_operand" ""))) + ] + "TARGET_MB_64" + { +@@ -2365,11 +2365,11 @@ else + + (define_insn "long_branch_zero" + [(set (pc) +- (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand 1 "register_operand" "d") ++ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand" "d") + (const_int 0)]) +- (match_operand 2 "pc_or_label_operand" "") +- (match_operand 3 "pc_or_label_operand" ""))) ++ (match_operand:DI 2 "pc_or_label_operand" "") ++ (match_operand:DI 3 "pc_or_label_operand" ""))) + ] + "TARGET_MB_64" + { +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch new file mode 100644 index 00000000..43c13b31 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch @@ -0,0 +1,87 @@ +From b26f11b38406605f1601626f9ee8267f85b4857c Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Fri, 29 Mar 2019 12:08:39 +0530 +Subject: [PATCH 44/53] [Patch,Microblaze] : We will check the possibility of + peephole2 optimization,if we can then we will fix the compiler issue. + +--- + gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------ + 1 file changed, 38 insertions(+), 25 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index fed6f5e0234..1490a522a4c 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -882,31 +882,44 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_peephole2 +- [(set (match_operand:SI 0 "register_operand") +- (fix:SI (match_operand:SF 1 "register_operand"))) +- (set (pc) +- (if_then_else (match_operator 2 "ordered_comparison_operator" +- [(match_operand:SI 3 "register_operand") +- (match_operand:SI 4 "arith_operand")]) +- (label_ref (match_operand 5)) +- (pc)))] +- "TARGET_HARD_FLOAT && !TARGET_MB_64" +- [(set (match_dup 1) (match_dup 3))] +- +- { +- rtx condition; +- rtx cmp_op0 = operands[3]; +- rtx cmp_op1 = operands[4]; +- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); +- +- emit_insn (gen_cstoresf4 (comp_reg, operands[2], +- gen_rtx_REG (SFmode, REGNO (cmp_op0)), +- gen_rtx_REG (SFmode, REGNO (cmp_op1)))); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, operands[5])); +- } +-) ++;; peephole2 optimization will be done only if fint and if-then-else ++;; are dependent.added condition for the same. ++;; if they are dependent then gcc is giving "flow control insn inside a basic block" ++;; testcase: ++;; volatile float vec = 1.0; ++;; volatile int ci = 2; ++;; register int cj = (int)(vec); ++;;// ci=cj; ++;;// if (ci <0) { ++;; if (cj < 0) { ++;; ci = 0; ++;; } ++;; commenting for now.we will check the possibility of this optimization later ++ ++;;(define_peephole2 ++;; [(set (match_operand:SI 0 "register_operand") ++;; (fix:SI (match_operand:SF 1 "register_operand"))) ++;; (set (pc) ++;; (if_then_else (match_operator 2 "ordered_comparison_operator" ++;; [(match_operand:SI 3 "register_operand") ++;; (match_operand:SI 4 "arith_operand")]) ++;; (label_ref (match_operand 5)) ++;; (pc)))] ++;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" ++;; [(set (match_dup 1) (match_dup 3))] ++;; { ++;; rtx condition; ++;; rtx cmp_op0 = operands[3]; ++;; rtx cmp_op1 = operands[4]; ++;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++;; ++;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], ++;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), ++;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); ++;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++;; emit_jump_insn (gen_condjump (condition, operands[5])); ++;; } ++;;) + + ;;---------------------------------------------------------------- + ;; Negation and one's complement +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch new file mode 100644 index 00000000..3edef57a --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch @@ -0,0 +1,466 @@ +From db8016ae6874865f57c6841ecabf9d9cdf785ece Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 17 Apr 2019 12:36:16 +0530 +Subject: [PATCH 45/53] [Patch,MicroBlaze]: fixed typos in mul,div and mod + assembly files. + +--- + libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++---- + libgcc/config/microblaze/modsi3.S | 40 ++++++++++++++++++--- + libgcc/config/microblaze/mulsi3.S | 33 ++++++++++++++++- + libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++--- + libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++--- + 5 files changed, 212 insertions(+), 20 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index 3a7fc4d6122..0fd275c8702 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -46,7 +46,7 @@ + __divsi3: + .frame r1,0,r15 + +- ADDIK r1,r1,-32 ++ ADDLIK r1,r1,-32 + SLI r28,r1,0 + SLI r29,r1,8 + SLI r30,r1,16 +@@ -61,13 +61,23 @@ __divsi3: + SWI r30,r1,8 + SWI r31,r1,12 + #endif +- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error +- BEQI r5,$LaResult_Is_Zero # Result is Zero +- BGEID r5,$LaR5_Pos ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEID r5,$LaR5_Pos ++#else ++ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEQI r5,$LaResult_Is_Zero # Result is Zero ++ BGEID r5,$LaR5_Pos ++#endif + XOR r28,r5,r6 # Get the sign of the result + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r30,r0,0 # Clear mod +@@ -76,26 +86,51 @@ $LaR6_Pos: + + # First part try to find the first '1' in the r5 + $LaDIV0: +- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#else ++ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++#else + BEQi r29,$LaLOOP_END ++#endif + ADD r3,r3,r3 # Shift in the '1' into div ++#ifdef __arch64__ ++ BREAI $LaDIV2 # Div2 ++#else + BRI $LaDIV2 # Div2 ++#endif + $LaLOOP_END: ++#ifdef __arch64__ ++ BEAGEI r28,$LaRETURN_HERE ++ BREAID $LaRETURN_HERE ++#else + BGEI r28,$LaRETURN_HERE + BRID $LaRETURN_HERE ++#endif + RSUBI r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index c98442c01c2..28775d71ba0 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -62,40 +62,72 @@ __modsi3: + swi r31,r1,12 + #endif + ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEId r5,$LaR5_Pos ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEId r5,$LaR5_Pos ++#endif + ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r3,r0,0 # Clear mod + ADDIK r30,r0,0 # clear div +- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++#ifdef __arch64__ ++ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip + # the first bit search. ++#else ++ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++#endif + ADDIK r29,r0,32 # Initialize the loop count + # First part try to find the first '1' in the r5 + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 +- BGEID r5,$LaDIV1 # ++#ifdef __arch64__ ++ BEAGEID r5,$LaDIV1 # ++#else ++ BGEID r5,$LaDIV1 # ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r3,r3,r3 # Move that bit into the Mod register + rSUB r31,r6,r3 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTi r31,$LaMOD_TOO_SMALL ++#else + BLTi r31,$LaMOD_TOO_SMALL ++#endif + OR r3,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r30,r30,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEAGEI r28,$LaRETURN_HERE ++ BREAId $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r30,r30,r30 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BGEI r28,$LaRETURN_HERE + BRId $LaRETURN_HERE ++#endif + rsubi r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +@@ -108,7 +140,7 @@ $LaRETURN_HERE: + lli r29,r1,8 + lli r30,r1,16 + lli r31,r1,24 +- addik r1,r1,32 ++ addlik r1,r1,32 + rtsd r15,8 + nop + #else +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index 0329fa3037a..7557368bc1c 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -43,7 +43,37 @@ + .type __mulsi3,@function + #ifdef __arch64__ + .align 3 +-#endif ++__mulsi3: ++ .frame r1,0,r15 ++ add r3,r0,r0 ++ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ BEAGEId r5,$L_R5_Pos ++ XOR r4,r5,r6 # Get the sign of the result ++ RSUBI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEAGEI r6,$L_R6_Pos ++ RSUBI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ add r5,r5,r5 ++$L1: ++ srl r6,r6 ++ addc r7,r0,r0 ++ beaeqi r7,$L2 ++ beaneid r6,$L2 ++ add r3,r3,r5 ++ bealti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rtsd r15,8 ++ rsub r3,r3,r0 ++$L_Result_Is_Zero: ++ rtsd r15,8 ++ addi r3,r0,0 ++#else + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +@@ -74,5 +104,6 @@ $L_NegateResult: + $L_Result_Is_Zero: + rtsd r15,8 + addi r3,r0,0 ++#endif + .end __mulsi3 + .size __mulsi3, . - __mulsi3 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 7bdcd8873e5..feff14664fb 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -59,52 +59,96 @@ __udivsi3: + SWI r30,r1,4 + SWI r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQID r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r30,r0,0 # Clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 1 + RSUB r18,r5,r6 ++#ifdef __arch64__ ++ BEAEQID r18,$LaRETURN_HERE ++#else + BEQID r18,$LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 + XOR r18,r5,r6 +- BGEID r18,16 ++#ifdef __arch64__ ++ BEAGEID r18,16 ++#else ++ BGEID r18,16 ++#endif + ADD r3,r0,r0 # We would anyways clear r3 ++#ifdef __arch64__ ++ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++ RSUB r18,r6,r5 # MICROBLAZEcmp ++ BEALTI r18,$LaRETURN_HERE ++#else + BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater + BRI $LCheckr6 + RSUB r18,r6,r5 # MICROBLAZEcmp + BLTI r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as 1 + $LCheckr6: +- BGTI r6,$LaDIV0 +- BRID $LaRETURN_HERE ++#ifdef __arch64__ ++ BEAGTI r6,$LaDIV0 ++ BREAID $LaRETURN_HERE ++#else ++ BGTI r6,$LaDIV0 ++ BRID $LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # First part try to find the first '1' in the r5 + $LaDIV0: ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 ++#else + BLTI r5,$LaDIV2 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r3,r3,r3 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BRI $LaRETURN_HERE ++#endif + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 +@@ -115,7 +159,7 @@ $LaRETURN_HERE: + LLI r29,r1,0 + LLI r30,r1,8 + LLI r31,r1,16 +- ADDIK r1,r1,24 ++ ADDLIK r1,r1,24 + RTSD r15,8 + NOP + #else +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 63ab1c2a357..f5bbb6f2d10 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -46,7 +46,7 @@ + __umodsi3: + .frame r1,0,r15 + +- addik r1,r1,-24 ++ addlik r1,r1,-24 + sli r29,r1,0 + sli r30,r1,8 + sli r31,r1,16 +@@ -59,27 +59,77 @@ __umodsi3: + swi r30,r1,4 + swi r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQId r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r3,r0,0 # Clear div + ADDIK r30,r0,0 # clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 0 + rsub r18,r5,r6 +- beqi r18,$LaRETURN_HERE + ++#ifdef __arch64__ ++ beaeqi r18,$LaRETURN_HERE ++#else ++ beqi r18,$LaRETURN_HERE ++#endif + # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 + xor r18,r5,r6 ++#ifdef __arch64__ ++ beageid r18,16 ++ addik r3,r5,0 ++ bealti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++ rsub r18,r5,r6 # MICROBLAZEcmp ++ beagti r18,$LaRETURN_HERE ++#else + bgeid r18,16 + addik r3,r5,0 + blti r6,$LaRETURN_HERE + bri $LCheckr6 + rsub r18,r5,r6 # MICROBLAZEcmp + bgti r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as r5-r6 + $LCheckr6: ++#ifdef __arch64__ ++ beagtid r6,$LaDIV0 ++ addik r3,r0,0 ++ addik r18,r0,0x7fffffff ++ and r5,r5,r18 ++ and r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsub r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALTI r5,$LaDIV2 ++$LaDIV1: ++ ADD r5,r5,r5 # left shift logical r5 ++ BEAGEID r5,$LaDIV1 # ++ ADDIK r29,r29,-1 ++$LaDIV2: ++ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDC r3,r3,r3 # Move that bit into the Mod register ++ rSUB r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALTi r31,$LaMOD_TOO_SMALL ++ OR r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDIK r29,r29,-1 ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ or r3,r0,r0 # set result to 0 ++#else + bgtid r6,$LaDIV0 + addik r3,r0,0 + addik r18,r0,0x7fffffff +@@ -111,7 +161,7 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 +- ++#endif + #ifdef __arch64__ + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Author-Nagaraju-nmekala-xilinx.com.patch new file mode 100644 index 00000000..456c5a48 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0046-Author-Nagaraju-nmekala-xilinx.com.patch @@ -0,0 +1,479 @@ +From 45fcd0217edf07fcb6473812cfc4ccacc8e95aac Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Thu, 18 Apr 2019 16:00:37 +0530 +Subject: [PATCH 46/53] Author: Nagaraju Date: Wed Apr + 17 14:11:00 2019 +0530 + + [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default + By default MB-64 is generatting barrel-shift instructions. It has been + removed from default. Barrel-shift instructions will be generated only if + barrel-shifter is enabled. Similarly to double instructions as well. + + Signed-off-by :Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.c | 2 +- + gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++-- + 2 files changed, 252 insertions(+), 19 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index b2cd89a310a..d1257032bfb 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3870,7 +3870,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + + if (TARGET_MB_64) { +- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_adddi3 (regt1, regt1, operands[2])); + } + else { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 1490a522a4c..40328b0d39d 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -547,7 +547,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (plus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dadd\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "DF") +@@ -557,7 +557,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (minus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "drsub\t%0,%2,%1" + [(set_attr "type" "frsub") + (set_attr "mode" "DF") +@@ -567,7 +567,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (mult:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dmul\t%0,%1,%2" + [(set_attr "type" "fmul") + (set_attr "mode" "DF") +@@ -577,7 +577,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (div:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "ddiv\t%0,%2,%1" + [(set_attr "type" "fdiv") + (set_attr "mode" "DF") +@@ -587,7 +587,7 @@ + (define_insn "sqrtdf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dsqrt\t%0,%1" + [(set_attr "type" "fsqrt") + (set_attr "mode" "DF") +@@ -596,7 +596,7 @@ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dbl\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") +@@ -605,7 +605,7 @@ + (define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DI") +@@ -1299,6 +1299,34 @@ + (set_attr "mode" "DI") + (set_attr "length" "4")]) + ++(define_insn "*movdi_internal2_bshift" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + (define_insn "*movdi_internal2" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") + (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] +@@ -1312,7 +1340,15 @@ + case 2: + if (GET_CODE (operands[1]) == CONST_INT && + (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) +- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ { ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,32", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; ++ } + else + return "addlik\t%0,r0,%1"; + case 3: +@@ -1387,7 +1423,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1654,6 +1690,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64_bshift" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal_64" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") + (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] +@@ -1670,7 +1733,13 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,32", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -1790,11 +1859,21 @@ + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1804,7 +1883,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashift:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bsllli\t%0,%1,%2 + bslll\t%0,%1,%2" +@@ -1812,6 +1891,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashldi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashldi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1945,11 +2069,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1959,7 +2093,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrai\t%0,%1,%2 + bslra\t%0,%1,%2" +@@ -1967,6 +2101,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2084,11 +2263,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -2098,7 +2287,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrli\t%0,%1,%2 + bslrl\t%0,%1,%2" +@@ -2107,6 +2296,50 @@ else + (set_attr "length" "4,4")] + ) + ++(define_insn "lshrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "lshrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "SI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2233,7 +2466,7 @@ else + (eq:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmpleq\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +@@ -2245,7 +2478,7 @@ else + (ne:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmplne\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch new file mode 100644 index 00000000..98183053 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch @@ -0,0 +1,107 @@ +From 688fcf782b7eca82cb2e2ab6589dee843983a5d6 Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Fri, 23 Aug 2019 16:16:53 +0530 +Subject: [PATCH 47/53] Added new MB-64 single register arithmetic instructions + +--- + gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++ + 1 file changed, 56 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 40328b0d39d..6bd042747bf 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -654,6 +654,18 @@ + } + }) + ++(define_insn "adddi3_int" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (plus:DI (match_operand:DI 1 "register_operand" "%0") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ addlik\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ + (define_insn "*adddi3_long" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") +@@ -719,6 +731,18 @@ + { + }") + ++(define_insn "subdi316imm" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))" ++ "@ ++ addlik\t%0,-%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++ + (define_insn "subsidi3" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") +@@ -1015,6 +1039,17 @@ + ;; Logical + ;;---------------------------------------------------------------- + ++(define_insn "anddi3imm16" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (and:DI (match_operand:DI 1 "arith_operand" "%0") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ andli\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "anddi3" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") +@@ -1042,6 +1077,16 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "iordi3imm16" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (ior:DI (match_operand:DI 1 "arith_operand" "%0") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ orli\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) + + (define_insn "iordi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") +@@ -1069,6 +1114,17 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "xordi3imm16" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (xor:DI (match_operand:DI 1 "arith_operand" "%0") ++ (match_operand:DI 2 "arith_operand" "K")))] ++ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" ++ "@ ++ xorli\t%0,%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "xordi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch new file mode 100644 index 00000000..29291154 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch @@ -0,0 +1,44 @@ +From 9098a760a10f09fefbdf438daf63b9e36576c9b2 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 26 Aug 2019 15:55:22 +0530 +Subject: [PATCH 48/53] [Patch,MicroBlaze] : Added support for 64 bit Immediate + values. + +--- + gcc/config/microblaze/constraints.md | 4 ++-- + gcc/config/microblaze/microblaze.md | 3 +-- + 2 files changed, 3 insertions(+), 4 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index e3f89491fb4..ef3001764c0 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -53,9 +53,9 @@ + (match_test "ival > 0 && ival < 0x10000"))) + + (define_constraint "K" +- "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." ++ "A constant in the range -9223372036854775808 to 9223372036854775807 (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) ++ (match_test "ival > (long long)-9223372036854775808 && ival < (long long)9223372036854775807"))) + + + ;; Define floating point constraints +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 6bd042747bf..b89a4276c7c 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1332,8 +1332,7 @@ + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") + (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] + "TARGET_MB_64 && (register_operand (operands[0], DImode) && +- (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" ++ (GET_CODE (operands[1]) == CONST_INT))" + "@ + addlk\t%0,r0,r0\t + addlik\t%0,r0,%1\t #N1 %X1 +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch new file mode 100644 index 00000000..163d4925 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch @@ -0,0 +1,86 @@ +From 2673e0dc2d75769c7cc36ca94e4e07caa28b8ef7 Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Thu, 9 Jan 2020 12:30:41 +0530 +Subject: [PATCH 49/53] [Patch, microblaze]: Fix Compiler crash with + -freg-struct-return This patch fixes a bug in MB GCC regarding the passing + struct values in registers. Currently we are only handling SImode With this + patch all other modes are handled properly + +Signed-off-by :Nagaraju Mekala + +ChangeLog: +2020-01-09 Nagaraju Mekala + + * gcc/config/microblaze/microblaze.h + (LIBCALL_Value): Remove macro + (PROMOTE_MODE): Remove macro + * gcc/config/microblaze/microblaze.c + (TARGET_LIBCALL_Value): Added new macro + (microblaze_function_value): Updated the return Value +--- + gcc/config/microblaze/microblaze.c | 11 ++++++++++- + gcc/config/microblaze/microblaze.h | 19 ------------------- + 2 files changed, 10 insertions(+), 20 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index d1257032bfb..5afac2ba8d1 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3908,7 +3908,16 @@ microblaze_function_value (const_tree valtype, + const_tree func ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) + { +- return LIBCALL_VALUE (TYPE_MODE (valtype)); ++ return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN); ++} ++ ++#undef TARGET_LIBCALL_VALUE ++#define TARGET_LIBCALL_VALUE microblaze_libcall_value ++ ++rtx ++microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) ++{ ++ return gen_rtx_REG (mode, GP_RETURN); + } + + /* Implement TARGET_SCHED_ADJUST_COST. */ +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index c6c3a9baa5a..2581d52d17a 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe; + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND + +-#ifndef __arch64__ +-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ +- if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < 4) \ +- (MODE) = SImode; +-#endif +- + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info; + + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + +-#ifdef __aarch64__ +-#define LIBCALL_VALUE(MODE) \ +- gen_rtx_REG (MODE,GP_RETURN) +-#else +-#define LIBCALL_VALUE(MODE) \ +- gen_rtx_REG ( \ +- ((GET_MODE_CLASS (MODE) != MODE_INT \ +- || GET_MODE_SIZE (MODE) >= 4) \ +- ? (MODE) \ +- : SImode), GP_RETURN) +-#endif +- + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch new file mode 100644 index 00000000..37945b65 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch @@ -0,0 +1,45 @@ +From 009fc9cbb72f50ac73b7f58153d0d90db46b48b8 Mon Sep 17 00:00:00 2001 +From: Nagaraju +Date: Wed, 8 May 2019 14:12:03 +0530 +Subject: [PATCH 50/53] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and + disable fivopts by default + +Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. + + * gcc/common/config/microblaze/microblaze-common.c + (microblaze_option_optimization_table): Disable fivopts by default. + +Signed-off-by: Nagaraju Mekala + +Conflicts: + gcc/common/config/microblaze/microblaze-common.c +--- + gcc/common/config/microblaze/microblaze-common.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c +index 1e4abb34027..d3a74fcc99e 100644 +--- a/gcc/common/config/microblaze/microblaze-common.c ++++ b/gcc/common/config/microblaze/microblaze-common.c +@@ -24,7 +24,18 @@ + #include "common/common-target.h" + #include "common/common-target-def.h" + ++/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ ++static const struct default_options microblaze_option_optimization_table[] = ++ { ++ /* Turn off ivopts by default. It messes up cse. ++ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */ ++ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, ++ { OPT_LEVELS_NONE, 0, NULL, 0 } ++ }; ++ + #undef TARGET_DEFAULT_TARGET_FLAGS + #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT + ++#undef TARGET_OPTION_OPTIMIZATION_TABLE ++#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table + struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch new file mode 100644 index 00000000..73b170c1 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch @@ -0,0 +1,198 @@ +From f52258e89f2ea416f418b6c55fef15552a081e18 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 24 Nov 2020 12:26:32 +0530 +Subject: [PATCH 51/53] [Patch, microblaze]: Reducing Stack space for arguments + +Currently in Microblaze target stack space for arguments in register is being +allocated even if there are no arguments in the function. +This patch will optimize the extra 24 bytes that are being allocated. + +Signed-off-by :Nagaraju Mekala + :Ajit Agarwal +--- + gcc/config/microblaze/microblaze-protos.h | 1 + + gcc/config/microblaze/microblaze.c | 132 +++++++++++++++++++++- + gcc/config/microblaze/microblaze.h | 4 +- + 3 files changed, 134 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index 302f6bbda2e..87a7093e369 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx); + extern int label_mentioned_p (rtx); + extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); + extern void microblaze_eh_return (rtx op0); ++int microblaze_reg_parm_stack_space(tree fun); + #endif /* RTX_CODE */ + + /* Declare functions in microblaze-c.c. */ +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 5afac2ba8d1..6914eb8380c 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2080,6 +2080,136 @@ microblaze_must_save_register (int regno) + return 0; + } + ++static bool ++microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type) ++{ ++ int unsignedp; ++ rtx entry_parm; ++ ++ /* Catch errors. */ ++ if (type == NULL || type == error_mark_node) ++ return true; ++ ++ if (TREE_CODE (type) == POINTER_TYPE) ++ return true; ++ ++ /* Handle types with no storage requirement. */ ++ if (TYPE_MODE (type) == VOIDmode) ++ return false; ++ ++ /* Handle complex types. */ ++ if (TREE_CODE (type) == COMPLEX_TYPE) ++ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)) ++ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))); ++ ++ /* Handle transparent aggregates. */ ++ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE) ++ && TYPE_TRANSPARENT_AGGR (type)) ++ type = TREE_TYPE (first_field (type)); ++ ++ /* See if this arg was passed by invisible reference. */ ++ function_arg_info arg (type, /*named=*/true); ++ apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg); ++ ++ /* Find mode as it is passed by the ABI. */ ++ unsignedp = TYPE_UNSIGNED (type); ++ arg.mode = promote_mode (arg.type, arg.mode, &unsignedp); ++ ++ /* If there is no incoming register, we need a stack. */ ++ entry_parm = microblaze_function_arg (args_so_far, arg); ++ if (entry_parm == NULL) ++ return true; ++ ++ /* Likewise if we need to pass both in registers and on the stack. */ ++ if (GET_CODE (entry_parm) == PARALLEL ++ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX) ++ return true; ++ ++ /* Also true if we're partially in registers and partially not. */ ++ if (function_arg_partial_bytes (args_so_far, arg) != 0) ++ return true; ++ ++ /* Update info on where next arg arrives in registers. */ ++ microblaze_function_arg_advance (args_so_far, arg); ++ return false; ++} ++ ++static bool ++microblaze_function_parms_need_stack (tree fun, bool incoming) ++{ ++ tree fntype, result; ++ CUMULATIVE_ARGS args_so_far_v; ++ cumulative_args_t args_so_far; ++ int num_of_args = 0; ++ ++ /* Must be a libcall, all of which only use reg parms. */ ++ if (!fun) ++ return true; ++ ++ fntype = fun; ++ if (!TYPE_P (fun)) ++ fntype = TREE_TYPE (fun); ++ ++ /* Varargs functions need the parameter save area. */ ++ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype)) ++ return true; ++ ++ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0); ++ args_so_far = pack_cumulative_args (&args_so_far_v); ++ ++ /* When incoming, we will have been passed the function decl. ++ * * It is necessary to use the decl to handle K&R style functions, ++ * * where TYPE_ARG_TYPES may not be available. */ ++ if (incoming) ++ { ++ gcc_assert (DECL_P (fun)); ++ result = DECL_RESULT (fun); ++ } ++ else ++ result = TREE_TYPE (fntype); ++ ++ if (result && aggregate_value_p (result, fntype)) ++ { ++ if (!TYPE_P (result)) ++ result = build_pointer_type (result); ++ microblaze_parm_needs_stack (args_so_far, result); ++ } ++ ++ if (incoming) ++ { ++ tree parm; ++ for (parm = DECL_ARGUMENTS (fun); ++ parm && parm != void_list_node; ++ parm = TREE_CHAIN (parm)) ++ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm))) ++ return true; ++ } ++ else ++ { ++ function_args_iterator args_iter; ++ tree arg_type; ++ ++ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter) ++ { ++ num_of_args; ++ if (microblaze_parm_needs_stack (args_so_far, arg_type)) ++ return true; ++ } ++ } ++ ++ if (num_of_args > 3) return true; ++ ++ return false; ++} ++ ++int microblaze_reg_parm_stack_space(tree fun) ++{ ++ if (microblaze_function_parms_need_stack (fun,false)) ++ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD; ++ else ++ return 0; ++} ++ + /* Return the bytes needed to compute the frame pointer from the current + stack pointer. + +@@ -3470,7 +3600,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + emit_insn (gen_indirect_jump (temp2)); + + /* Run just enough of rest_of_compilation. This sequence was +- "borrowed" from rs6000.c. */ ++ "borrowed" from microblaze.c */ + insn = get_insns (); + shorten_branches (insn); + assemble_start_function (thunk_fndecl, fnname); +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 2581d52d17a..9c48978d2ca 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info; + #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 + #define DWARF_CIE_DATA_ALIGNMENT -1 + +-#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) ++#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL) + +-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 ++#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + + #define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) + +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch new file mode 100644 index 00000000..293a7486 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0052-Patch-MicroBlaze.patch @@ -0,0 +1,72 @@ +From b0ea0d18d1b353421ef7e18d496fd505cb1d5f7d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 28 Apr 2021 16:49:18 +0530 +Subject: [PATCH 52/53] [Patch,MicroBlaze] : If we use break_handler attribute + then interrupt vector call happened to break_handler instead of + interrupt_handler. this fix will resolve the issue CR-1081780 This fix will + not change the behavior of compiler unless there is a usage of break_handler + attribute. + +--- + gcc/config/microblaze/microblaze.c | 13 +++++-------- + 1 file changed, 5 insertions(+), 8 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 6914eb8380c..d0546a164d7 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2019,7 +2019,7 @@ microblaze_save_volatiles (tree func) + int + microblaze_is_interrupt_variant (void) + { +- return (interrupt_handler || fast_interrupt); ++ return (interrupt_handler || fast_interrupt || break_handler); + } + int + microblaze_is_break_handler (void) +@@ -2058,7 +2058,7 @@ microblaze_must_save_register (int regno) + { + if (df_regs_ever_live_p (regno) + || regno == MB_ABI_MSR_SAVE_REG +- || ((interrupt_handler || fast_interrupt) ++ || ((interrupt_handler || fast_interrupt || break_handler) + && (regno == MB_ABI_ASM_TEMP_REGNUM + || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM))) + return 1; +@@ -2274,9 +2274,6 @@ compute_frame_size (HOST_WIDE_INT size) + fast_interrupt = + microblaze_fast_interrupt_function_p (current_function_decl); + save_volatiles = microblaze_save_volatiles (current_function_decl); +- if (break_handler) +- interrupt_handler = break_handler; +- + gp_reg_size = 0; + mask = 0; + var_size = size; +@@ -3236,7 +3233,7 @@ microblaze_expand_prologue (void) + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + const0_rtx)); + +- if (interrupt_handler) ++ if (interrupt_handler || break_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + +@@ -3347,12 +3344,12 @@ microblaze_expand_epilogue (void) + a load-use stall cycle :) This is also important to handle alloca. + (See comments for if (frame_pointer_needed) below. */ + +- if (!crtl->is_leaf || interrupt_handler) ++ if (!crtl->is_leaf || interrupt_handler || break_handler) + { + mem_rtx = + gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); +- if (interrupt_handler) ++ if (interrupt_handler || break_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch new file mode 100644 index 00000000..76148d15 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/0053-patch-microblaze64-Add-Zero_extended-instructions.patch @@ -0,0 +1,57 @@ +From 7c9402f1dc641a1fe4110e92cd16a33ed4bd35cf Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Mon, 30 Aug 2021 12:13:45 +0530 +Subject: [PATCH 53/53] [patch, microblaze64]: Add Zero_extended instructions + +Due to latest changes in GCC-10.2 MB64 perforamance has reduced +We have added zero_extended instructions to get rid of left shift +and right shift loops + +[CR/TSR]: TSR-974519 + +Signed-off-by: Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.md | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index b89a4276c7c..ee078b0152a 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1191,6 +1191,33 @@ + (set_attr "mode" "SI,SI,SI") + (set_attr "length" "4,4,8")]) + ++(define_insn "zero_extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0xffff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ ++(define_insn "zero_extendsidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0xffffffff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ ++(define_insn "zero_extendqidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0x00ff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ + ;;---------------------------------------------------------------- + ;; Sign extension + ;;---------------------------------------------------------------- +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch new file mode 100644 index 00000000..af8ebf3b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-12/microblaze-mulitlib-hack.patch @@ -0,0 +1,58 @@ +Microblaze Mulitlib hack + +Based on the patch: + +From c2081c51db589471ea713870c72f13999abda815 Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Fri, 29 Mar 2013 09:10:06 +0400 +Subject: [PATCH 04/36] 64-bit multilib hack. + +GCC has internal multilib handling code but it assumes a very specific rigid directory +layout. The build system implementation of multilib layout is very generic and allows +complete customisation of the library directories. + +This patch is a partial solution to allow any custom directories to be passed into gcc +and handled correctly. It forces gcc to use the base_libdir (which is the current +directory, "."). We need to do this for each multilib that is configured as we don't +know which compiler options may be being passed into the compiler. Since we have a compiler +per mulitlib at this point that isn't an issue. + +The one problem is the target compiler is only going to work for the default multlilib at +this point. Ideally we'd figure out which multilibs were being enabled with which paths +and be able to patch these entries with a complete set of correct paths but this we +don't have such code at this point. This is something the target gcc recipe should do +and override these platform defaults in its build config. + +Do same for riscv64 and aarch64 + +RP 15/8/11 + +Upstream-Status: Inappropriate[OE-Specific] + +Signed-off-by: Khem Raj +Signed-off-by: Elvis Dowson +Signed-off-by: Mark Hatle +Signed-off-by: Mark Hatle + +Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze +=================================================================== +--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze ++++ gcc-9.2.0/gcc/config/microblaze/t-microblaze +@@ -1,5 +1,6 @@ + MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high +-MULTILIB_DIRNAMES = m64 bs le m mh ++#MULTILIB_DIRNAMES = m64 bs le m mh ++MULTILIB_DIRNAMES = . . . . . + MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *m64 + MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift +Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux +=================================================================== +--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze-linux ++++ gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux +@@ -1,3 +1,4 @@ + MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high +-MULTILIB_DIRNAMES = bs m mh ++#MULTILIB_DIRNAMES = bs m mh ++MULTILIB_DIRNAMES = . . . + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend deleted file mode 100644 index ab3a1c47..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend +++ /dev/null @@ -1,59 +0,0 @@ -# Add MicroBlaze Patches (only when using MicroBlaze) -FILESEXTRAPATHS:append:microblaze := ":${THISDIR}/gcc-11" - -SRC_URI:append:microblaze = " \ - file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ - file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \ - file://0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \ - file://0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \ - file://0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch \ - file://0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \ - file://0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \ - file://0008-Patch-microblaze-Fix-atomic-side-effects.patch \ - file://0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch \ - file://0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \ - file://0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \ - file://0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch \ - file://0013-Patch-microblaze-Removed-moddi3-routinue.patch \ - file://0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch \ - file://0015-Patch-microblaze-Add-optimized-lshrsi3.patch \ - file://0016-Patch-microblaze-Add-cbranchsi4_reg.patch \ - file://0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \ - file://0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \ - file://0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \ - file://0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \ - file://0021-Patch-microblaze-Correct-the-const-high-double-immed.patch \ - file://0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \ - file://0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \ - file://0024-Patch-MicroBlaze-this-patch-has.patch \ - file://0025-Fixing-the-issue-with-the-builtin_alloc.patch \ - file://0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \ - file://0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch \ - file://0028-Intial-commit-for-64bit-MB-sources.patch \ - file://0029-re-arrangement-of-the-compare-branches.patch \ - file://0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch \ - file://0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch \ - file://0032-Fixed-issues-like.patch \ - file://0033-Fixed-below-issues.patch \ - file://0034-Added-double-arith-instructions.patch \ - file://0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \ - file://0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \ - file://0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch \ - file://0038-fixing-the-typo-errors-in-umodsi3-file.patch \ - file://0039-fixing-the-32bit-LTO-related-issue9-1014024.patch \ - file://0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ - file://0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \ - file://0042-fixing-the-long-long-long-mingw-toolchain-issue.patch \ - file://0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ - file://0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \ - file://0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \ - file://0046-Author-Nagaraju-nmekala-xilinx.com.patch \ - file://0047-Added-new-MB-64-single-register-arithmetic-instructi.patch \ - file://0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \ - file://0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \ - file://0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \ - file://0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \ - file://0052-Patch-MicroBlaze.patch \ - file://0053-patch-microblaze64-Add-Zero_extended-instructions.patch \ - file://microblaze-mulitlib-hack.patch \ -" diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend new file mode 100644 index 00000000..09217fd3 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-source_12.%.bbappend @@ -0,0 +1,59 @@ +# Add MicroBlaze Patches (only when using MicroBlaze) +FILESEXTRAPATHS:append:microblaze := ":${THISDIR}/gcc-12" + +SRC_URI:append:microblaze = " \ + file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ + file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \ + file://0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \ + file://0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \ + file://0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch \ + file://0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \ + file://0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \ + file://0008-Patch-microblaze-Fix-atomic-side-effects.patch \ + file://0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch \ + file://0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \ + file://0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \ + file://0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch \ + file://0013-Patch-microblaze-Removed-moddi3-routinue.patch \ + file://0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch \ + file://0015-Patch-microblaze-Add-optimized-lshrsi3.patch \ + file://0016-Patch-microblaze-Add-cbranchsi4_reg.patch \ + file://0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \ + file://0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \ + file://0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \ + file://0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \ + file://0021-Patch-microblaze-Correct-the-const-high-double-immed.patch \ + file://0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \ + file://0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \ + file://0024-Patch-MicroBlaze-this-patch-has.patch \ + file://0025-Fixing-the-issue-with-the-builtin_alloc.patch \ + file://0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \ + file://0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch \ + file://0028-Intial-commit-for-64bit-MB-sources.patch \ + file://0029-re-arrangement-of-the-compare-branches.patch \ + file://0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch \ + file://0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch \ + file://0032-Fixed-issues-like.patch \ + file://0033-Fixed-below-issues.patch \ + file://0034-Added-double-arith-instructions.patch \ + file://0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \ + file://0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \ + file://0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch \ + file://0038-fixing-the-typo-errors-in-umodsi3-file.patch \ + file://0039-fixing-the-32bit-LTO-related-issue9-1014024.patch \ + file://0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ + file://0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \ + file://0042-fixing-the-long-long-long-mingw-toolchain-issue.patch \ + file://0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ + file://0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \ + file://0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \ + file://0046-Author-Nagaraju-nmekala-xilinx.com.patch \ + file://0047-Added-new-MB-64-single-register-arithmetic-instructi.patch \ + file://0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \ + file://0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \ + file://0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \ + file://0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \ + file://0052-Patch-MicroBlaze.patch \ + file://0053-patch-microblaze64-Add-Zero_extended-instructions.patch \ + file://microblaze-mulitlib-hack.patch \ +" -- cgit v1.2.3-54-g00ecf