From 8542abc620bdaab0d9c6e89178dfe20baa1af10c Mon Sep 17 00:00:00 2001 From: Siva Addepalli Date: Tue, 14 Nov 2023 12:46:10 +0530 Subject: Updated SRCREV of vcu-modules for 2024.1_4743 chore: align xilinx-private and master-allegro Fix compilation issue fix: xilinx implementation of add_memory refacto setup_dma reformat feat: Use the macro defined by the kernel to initialize dmabuf export informations. Move constant in al_constants.h small fixes cdev refacto Revert Revert Add support for reserved memory with start address not aligned on 2GB feat: getter/setter encode/decode Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb index 7f2b205f..585dd629 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb @@ -13,7 +13,7 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" BRANCH = "master" REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" -SRCREV = "689c8d823b383e2a8a5249be49de627f866cfaf2" +SRCREV = "51f22c517a2c58fef4f358ffaac3e159692c5ee7" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = " \ -- cgit v1.2.3-54-g00ecf