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authorNathan Rossi <nathan.rossi@xilinx.com>2015-02-18 18:26:20 +1000
committerNathan Rossi <nathan.rossi@xilinx.com>2015-02-23 14:23:24 +1000
commit832e83185244e6461766227f666e24421f3af156 (patch)
tree7d33348e95e9c5761c33e1e4f656dd5b396fa1fd /recipes-kernel
parent0d667c6a6d5c204e894d449a2b992f1a1affdcdb (diff)
downloadmeta-xilinx-832e83185244e6461766227f666e24421f3af156.tar.gz
linux-zynqmp-mainline: Added recipe for ZynqMP Linux
* Based on mainline v3.19 kernel * Patches added to support EP108 and QEMU, some patches are not intended for upstream submission (and are only required for QEMU support) * Specify device trees for EP108 and QEMU * Add config fragments for ZynqMP Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Diffstat (limited to 'recipes-kernel')
-rw-r--r--recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp-standard.scc14
-rw-r--r--recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.cfg17
-rw-r--r--recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.scc19
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline/0001-ARM64-Add-new-Xilinx-ZynqMP-SoC.patch436
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline/0002-net-cadence-Enable-MACB-driver-for-ARM64.patch41
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline/0003-spi-Enable-Cadence-SPI-driver-for-ARM64.patch32
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline/0004-arm64-mm-Correct-check-for-EXEC-faults.patch46
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline/0005-arm64-Implement-cpu_relax-as-yield.patch33
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline/0006-arm64-spinlock-sev-when-unlocking-locks.patch28
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline/0007-kbuild-Create-directory-for-target-DTB.patch31
-rw-r--r--recipes-kernel/linux/linux-zynqmp-mainline_3.19.bb28
11 files changed, 725 insertions, 0 deletions
diff --git a/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp-standard.scc b/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp-standard.scc
new file mode 100644
index 00000000..8092ec7d
--- /dev/null
+++ b/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp-standard.scc
@@ -0,0 +1,14 @@
1define KMACHINE zynqmp
2define KTYPE standard
3define KARCH arm64
4
5include ktypes/standard/standard.scc
6
7include bsp/zynqmp/zynqmp.scc
8
9# Common board drivers
10include features/xilinx/board-common.scc
11
12# default policy for standard kernels
13#include features/latencytop/latencytop.scc
14#include features/profiling/profiling.scc
diff --git a/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.cfg b/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.cfg
new file mode 100644
index 00000000..57944f37
--- /dev/null
+++ b/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.cfg
@@ -0,0 +1,17 @@
1
2# Arch Feature Selections
3CONFIG_ARM64=y
4CONFIG_64BIT=y
5CONFIG_ARCH_ZYNQMP=y
6
7# SMP
8CONFIG_SMP=y
9
10# Debug
11CONFIG_PRINTK_TIME=y
12
13CONFIG_SERIAL_XILINX_PS_UART=y
14CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
15
16CONFIG_MACB=y
17
diff --git a/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.scc b/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.scc
new file mode 100644
index 00000000..360ba5d1
--- /dev/null
+++ b/recipes-kernel/linux/config/xilinx-common/bsp/zynqmp/zynqmp.scc
@@ -0,0 +1,19 @@
1# include arch/arm64/arm64.scc
2include cfg/timer/hz_100.scc
3
4kconf hardware zynqmp.cfg
5
6include cfg/timer/no_hz.scc
7
8# include features/xilinx/xilinx-ip.scc
9
10include cfg/usb-mass-storage.scc
11
12include features/scsi/scsi.scc
13include features/scsi/scsi-generic.scc
14include features/scsi/disk.scc
15
16include features/mtd/mtd.scc
17include features/uio/uio.scc
18
19include cfg/fs/debugfs.scc
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline/0001-ARM64-Add-new-Xilinx-ZynqMP-SoC.patch b/recipes-kernel/linux/linux-zynqmp-mainline/0001-ARM64-Add-new-Xilinx-ZynqMP-SoC.patch
new file mode 100644
index 00000000..9aed3963
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline/0001-ARM64-Add-new-Xilinx-ZynqMP-SoC.patch
@@ -0,0 +1,436 @@
1From a8de57243f95b3b2a5f858d416b084abb7049445 Mon Sep 17 00:00:00 2001
2From: Michal Simek <michal.simek@xilinx.com>
3Date: Wed, 11 Feb 2015 14:37:23 +0100
4Subject: [PATCH 1/7] ARM64: Add new Xilinx ZynqMP SoC
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Initial version of device tree for Xilinx ZynqMP SoC.
10
11Signed-off-by: Michal Simek <michal.simek@xilinx.com>
12Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
13---
14 arch/arm64/Kconfig | 5 +
15 arch/arm64/boot/dts/Makefile | 1 +
16 arch/arm64/boot/dts/xilinx/Makefile | 5 +
17 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 46 +++++
18 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 301 ++++++++++++++++++++++++++++
19 arch/arm64/configs/defconfig | 1 +
20 6 files changed, 359 insertions(+)
21 create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
22 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
23 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
24
25diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
26index b1f9a20..fd103ed 100644
27--- a/arch/arm64/Kconfig
28+++ b/arch/arm64/Kconfig
29@@ -173,6 +173,11 @@ config ARCH_XGENE
30 help
31 This enables support for AppliedMicro X-Gene SOC Family
32
33+config ARCH_ZYNQMP
34+ bool "Xilinx Zynq MP SOC Family"
35+ help
36+ This enables support for Xilinx Zynq MP SOC Family
37+
38 endmenu
39
40 menu "Bus support"
41diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
42index c62b0f4..9470c79 100644
43--- a/arch/arm64/boot/dts/Makefile
44+++ b/arch/arm64/boot/dts/Makefile
45@@ -2,5 +2,6 @@ dts-dirs += amd
46 dts-dirs += apm
47 dts-dirs += arm
48 dts-dirs += cavium
49+dts-dirs += xilinx
50
51 subdir-y := $(dts-dirs)
52diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
53new file mode 100644
54index 0000000..ae16427
55--- /dev/null
56+++ b/arch/arm64/boot/dts/xilinx/Makefile
57@@ -0,0 +1,5 @@
58+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
59+
60+always := $(dtb-y)
61+subdir-y := $(dts-dirs)
62+clean-files := *.dtb
63diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
64new file mode 100644
65index 0000000..121a47f
66--- /dev/null
67+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
68@@ -0,0 +1,46 @@
69+/*
70+ * dts file for Xilinx ZynqMP ep108 development board
71+ *
72+ * (c) Copyright 2014 - 2015, Xilinx, Inc.
73+ *
74+ * This program is free software; you can redistribute it and/or
75+ * modify it under the terms of the GNU General Public License as
76+ * published by the Free Software Foundation; either version 2 of
77+ * the License, or (at your option) any later version.
78+ */
79+
80+/dts-v1/;
81+
82+/include/ "zynqmp.dtsi"
83+
84+/ {
85+ model = "ZynqMP EP108";
86+
87+ aliases {
88+ serial0 = &uart0;
89+ };
90+
91+ chosen {
92+ stdout-path = "serial0:115200n8";
93+ };
94+
95+ memory {
96+ device_type = "memory";
97+ reg = <0x0 0x0 0x40000000>;
98+ };
99+};
100+
101+&gem0 {
102+ status = "okay";
103+ phy-handle = <&phy0>;
104+ phy-mode = "rgmii-id";
105+ phy0: phy@0{
106+ reg = <0>;
107+ max-speed = <100>;
108+ };
109+};
110+
111+&uart0 {
112+ status = "okay";
113+};
114+
115diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
116new file mode 100644
117index 0000000..d8402fd
118--- /dev/null
119+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
120@@ -0,0 +1,301 @@
121+/*
122+ * dts file for Xilinx ZynqMP
123+ *
124+ * (c) Copyright 2014 - 2015, Xilinx, Inc.
125+ *
126+ * This program is free software; you can redistribute it and/or
127+ * modify it under the terms of the GNU General Public License as
128+ * published by the Free Software Foundation; either version 2 of
129+ * the License, or (at your option) any later version.
130+ */
131+
132+/ {
133+ compatible = "xlnx,zynqmp";
134+ #address-cells = <2>;
135+ #size-cells = <1>;
136+
137+ cpus {
138+ #address-cells = <1>;
139+ #size-cells = <0>;
140+
141+ cpu@0 {
142+ compatible = "arm,cortex-a53", "arm,armv8";
143+ device_type = "cpu";
144+ enable-method = "psci";
145+ reg = <0x0>;
146+ };
147+
148+ cpu@1 {
149+ compatible = "arm,cortex-a53", "arm,armv8";
150+ device_type = "cpu";
151+ enable-method = "psci";
152+ reg = <0x1>;
153+ };
154+
155+ cpu@2 {
156+ compatible = "arm,cortex-a53", "arm,armv8";
157+ device_type = "cpu";
158+ enable-method = "psci";
159+ reg = <0x2>;
160+ };
161+
162+ cpu@3 {
163+ compatible = "arm,cortex-a53", "arm,armv8";
164+ device_type = "cpu";
165+ enable-method = "psci";
166+ reg = <0x3>;
167+ };
168+ };
169+
170+ psci {
171+ compatible = "arm,psci-0.2";
172+ method = "smc";
173+ };
174+
175+ pmu {
176+ compatible = "arm,armv8-pmuv3";
177+ interrupts = <0 143 4>,
178+ <0 144 4>,
179+ <0 145 4>,
180+ <0 146 4>;
181+ };
182+
183+ amba_apu {
184+ compatible = "simple-bus";
185+ #address-cells = <2>;
186+ #size-cells = <1>;
187+ ranges;
188+
189+ timer {
190+ compatible = "arm,armv8-timer";
191+ interrupt-parent = <&gic>;
192+ interrupts = <1 13 0xff01>,
193+ <1 14 0xff01>,
194+ <1 11 0xff01>,
195+ <1 10 0xff01>;
196+ };
197+
198+ gic: interrupt-controller@f9010000 {
199+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
200+ #interrupt-cells = <3>;
201+ reg = <0x0 0xf9010000 0x10000>,
202+ <0x0 0xf9020000 0x20000>,
203+ <0x0 0xf9040000 0x20000>,
204+ <0x0 0xf9060000 0x20000>;
205+ interrupt-controller;
206+ };
207+ };
208+
209+ amba {
210+ compatible = "simple-bus";
211+ #address-cells = <2>;
212+ #size-cells = <1>;
213+ ranges;
214+
215+ misc_clk: misc_clk {
216+ compatible = "fixed-clock";
217+ #clock-cells = <0>;
218+ clock-frequency = <25000000>;
219+ };
220+
221+ ttc0: timer@ff110000 {
222+ compatible = "cdns,ttc";
223+ status = "disabled";
224+ interrupt-parent = <&gic>;
225+ interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
226+ reg = <0x0 0xff110000 0x1000>;
227+ clocks = <&misc_clk>;
228+ timer-width = <32>;
229+ };
230+
231+ ttc1: timer@ff120000 {
232+ compatible = "cdns,ttc";
233+ status = "disabled";
234+ interrupt-parent = <&gic>;
235+ interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
236+ reg = <0x0 0xff120000 0x1000>;
237+ clocks = <&misc_clk>;
238+ timer-width = <32>;
239+ };
240+
241+ ttc2: timer@ff130000 {
242+ compatible = "cdns,ttc";
243+ status = "disabled";
244+ interrupt-parent = <&gic>;
245+ interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
246+ reg = <0x0 0xff130000 0x1000>;
247+ clocks = <&misc_clk>;
248+ timer-width = <32>;
249+ };
250+
251+ ttc3: timer@ff140000 {
252+ compatible = "cdns,ttc";
253+ status = "disabled";
254+ interrupt-parent = <&gic>;
255+ interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
256+ reg = <0x0 0xff140000 0x1000>;
257+ clocks = <&misc_clk>;
258+ timer-width = <32>;
259+ };
260+
261+ uart0: serial@ff000000 {
262+ compatible = "cdns,uart-r1p8";
263+ status = "disabled";
264+ interrupt-parent = <&gic>;
265+ interrupts = <0 21 4>;
266+ reg = <0x0 0xff000000 0x1000>;
267+ clock-names = "uart_clk", "pclk";
268+ clocks = <&misc_clk &misc_clk>;
269+ };
270+
271+ uart1: serial@ff010000 {
272+ compatible = "cdns,uart-r1p8";
273+ status = "disabled";
274+ interrupt-parent = <&gic>;
275+ interrupts = <0 22 4>;
276+ reg = <0x0 0xff010000 0x1000>;
277+ clock-names = "uart_clk", "pclk";
278+ clocks = <&misc_clk &misc_clk>;
279+ };
280+
281+ gpio: gpio@ff0a0000 {
282+ compatible = "xlnx,zynq-gpio-1.0";
283+ status = "disabled";
284+ #gpio-cells = <0x2>;
285+ clocks = <&misc_clk>;
286+ interrupt-parent = <&gic>;
287+ interrupts = <0 16 4>;
288+ reg = <0x0 0xff0a0000 0x1000>;
289+ };
290+
291+ gem0: ethernet@ff0b0000 {
292+ compatible = "cdns,gem";
293+ status = "disabled";
294+ interrupt-parent = <&gic>;
295+ interrupts = <0 57 4>;
296+ reg = <0x0 0xff0b0000 0x1000>;
297+ clock-names = "pclk", "hclk", "tx_clk";
298+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
299+ #address-cells = <1>;
300+ #size-cells = <0>;
301+ };
302+
303+ gem1: ethernet@ff0c0000 {
304+ compatible = "cdns,gem";
305+ status = "disabled";
306+ interrupt-parent = <&gic>;
307+ interrupts = <0 59 4>;
308+ reg = <0x0 0xff0c0000 0x1000>;
309+ clock-names = "pclk", "hclk", "tx_clk";
310+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
311+ #address-cells = <1>;
312+ #size-cells = <0>;
313+ };
314+
315+ gem2: ethernet@ff0d0000 {
316+ compatible = "cdns,gem";
317+ status = "disabled";
318+ interrupt-parent = <&gic>;
319+ interrupts = <0 61 4>;
320+ reg = <0x0 0xff0d0000 0x1000>;
321+ clock-names = "pclk", "hclk", "tx_clk";
322+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
323+ #address-cells = <1>;
324+ #size-cells = <0>;
325+ };
326+
327+ gem3: ethernet@ff0e0000 {
328+ compatible = "cdns,gem";
329+ status = "disabled";
330+ interrupt-parent = <&gic>;
331+ interrupts = <0 63 4>;
332+ reg = <0x0 0xff0e0000 0x1000>;
333+ clock-names = "pclk", "hclk", "tx_clk";
334+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
335+ #address-cells = <1>;
336+ #size-cells = <0>;
337+ };
338+
339+ spi0: spi@ff040000 {
340+ compatible = "cdns,spi-r1p6";
341+ status = "disabled";
342+ interrupt-parent = <&gic>;
343+ interrupts = <0 19 4>;
344+ reg = <0x0 0xff040000 0x1000>;
345+ clock-names = "ref_clk", "pclk";
346+ clocks = <&misc_clk &misc_clk>;
347+ #address-cells = <1>;
348+ #size-cells = <0>;
349+ };
350+
351+ spi1: spi@ff050000 {
352+ compatible = "cdns,spi-r1p6";
353+ status = "disabled";
354+ interrupt-parent = <&gic>;
355+ interrupts = <0 20 4>;
356+ reg = <0x0 0xff050000 0x1000>;
357+ clock-names = "ref_clk", "pclk";
358+ clocks = <&misc_clk &misc_clk>;
359+ #address-cells = <1>;
360+ #size-cells = <0>;
361+ };
362+
363+ i2c_clk: i2c_clk {
364+ compatible = "fixed-clock";
365+ #clock-cells = <0x0>;
366+ clock-frequency = <111111111>;
367+ };
368+
369+ i2c0: i2c@ff020000 {
370+ compatible = "cdns,i2c-r1p10";
371+ status = "disabled";
372+ interrupt-parent = <&gic>;
373+ interrupts = <0 17 4>;
374+ reg = <0x0 0xff020000 0x1000>;
375+ clocks = <&i2c_clk>;
376+ #address-cells = <1>;
377+ #size-cells = <0>;
378+ };
379+
380+ i2c1: i2c@ff030000 {
381+ compatible = "cdns,i2c-r1p10";
382+ status = "disabled";
383+ interrupt-parent = <&gic>;
384+ interrupts = <0 18 4>;
385+ reg = <0x0 0xff030000 0x1000>;
386+ clocks = <&i2c_clk>;
387+ #address-cells = <1>;
388+ #size-cells = <0>;
389+ };
390+
391+ sdhci0: sdhci@ff160000 {
392+ compatible = "arasan,sdhci-8.9a";
393+ status = "disabled";
394+ interrupt-parent = <&gic>;
395+ interrupts = <0 48 4>;
396+ reg = <0x0 0xff160000 0x1000>;
397+ clock-names = "clk_xin", "clk_ahb";
398+ clocks = <&misc_clk>, <&misc_clk>;
399+ };
400+
401+ sdhci1: sdhci@ff170000 {
402+ compatible = "arasan,sdhci-8.9a";
403+ status = "disabled";
404+ interrupt-parent = <&gic>;
405+ interrupts = <0 49 4>;
406+ reg = <0x0 0xff170000 0x1000>;
407+ clock-names = "clk_xin", "clk_ahb";
408+ clocks = <&misc_clk>, <&misc_clk>;
409+ };
410+
411+ watchdog0: watchdog@fd4d0000 {
412+ compatible = "cdns,wdt-r1p2";
413+ status = "disabled";
414+ clocks= <&misc_clk>;
415+ interrupt-parent = <&gic>;
416+ interrupts = <0 52 1>;
417+ reg = <0x0 0xfd4d0000 0x1000>;
418+ timeout-sec = <10>;
419+ };
420+ };
421+};
422diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
423index 5376d90..d1b5da8 100644
424--- a/arch/arm64/configs/defconfig
425+++ b/arch/arm64/configs/defconfig
426@@ -34,6 +34,7 @@ CONFIG_MODULE_UNLOAD=y
427 CONFIG_ARCH_THUNDER=y
428 CONFIG_ARCH_VEXPRESS=y
429 CONFIG_ARCH_XGENE=y
430+CONFIG_ARCH_ZYNQMP=y
431 CONFIG_PCI=y
432 CONFIG_PCI_MSI=y
433 CONFIG_PCI_XGENE=y
434--
4352.1.1
436
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline/0002-net-cadence-Enable-MACB-driver-for-ARM64.patch b/recipes-kernel/linux/linux-zynqmp-mainline/0002-net-cadence-Enable-MACB-driver-for-ARM64.patch
new file mode 100644
index 00000000..032137eb
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline/0002-net-cadence-Enable-MACB-driver-for-ARM64.patch
@@ -0,0 +1,41 @@
1From 84cf0db302640fc5b29556b1064508eaa39ab08a Mon Sep 17 00:00:00 2001
2From: Michal Simek <michal.simek@xilinx.com>
3Date: Wed, 11 Feb 2015 14:31:38 +0100
4Subject: [PATCH 2/7] net: cadence: Enable MACB driver for ARM64
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9This driver is used on new Xilinx ZynqMP SoC.
10
11Signed-off-by: Michal Simek <michal.simek@xilinx.com>
12Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
13---
14 drivers/net/ethernet/cadence/Kconfig | 4 ++--
15 1 file changed, 2 insertions(+), 2 deletions(-)
16
17diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig
18index 321d2ad..4562f90 100644
19--- a/drivers/net/ethernet/cadence/Kconfig
20+++ b/drivers/net/ethernet/cadence/Kconfig
21@@ -4,7 +4,7 @@
22
23 config NET_CADENCE
24 bool "Cadence devices"
25- depends on HAS_IOMEM && (ARM || AVR32 || MICROBLAZE || COMPILE_TEST)
26+ depends on HAS_IOMEM && (ARM || ARM64 || AVR32 || MICROBLAZE || COMPILE_TEST)
27 default y
28 ---help---
29 If you have a network (Ethernet) card belonging to this class, say Y.
30@@ -30,7 +30,7 @@ config ARM_AT91_ETHER
31
32 config MACB
33 tristate "Cadence MACB/GEM support"
34- depends on HAS_DMA && (PLATFORM_AT32AP || ARCH_AT91 || ARCH_PICOXCELL || ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST)
35+ depends on HAS_DMA && (PLATFORM_AT32AP || ARCH_AT91 || ARCH_PICOXCELL || ARCH_ZYNQ || ARM64 || MICROBLAZE || COMPILE_TEST)
36 select PHYLIB
37 ---help---
38 The Cadence MACB ethernet interface is found on many Atmel AT32 and
39--
402.1.1
41
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline/0003-spi-Enable-Cadence-SPI-driver-for-ARM64.patch b/recipes-kernel/linux/linux-zynqmp-mainline/0003-spi-Enable-Cadence-SPI-driver-for-ARM64.patch
new file mode 100644
index 00000000..9e6b9a84
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline/0003-spi-Enable-Cadence-SPI-driver-for-ARM64.patch
@@ -0,0 +1,32 @@
1From 411f7900bf4609e398bca8ae0be39bb3ab6b2642 Mon Sep 17 00:00:00 2001
2From: Michal Simek <michal.simek@xilinx.com>
3Date: Wed, 11 Feb 2015 14:34:56 +0100
4Subject: [PATCH 3/7] spi: Enable Cadence SPI driver for ARM64
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9This driver is used on new Xilinx ZynqMP SoC.
10
11Signed-off-by: Michal Simek <michal.simek@xilinx.com>
12Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
13---
14 drivers/spi/Kconfig | 2 +-
15 1 file changed, 1 insertion(+), 1 deletion(-)
16
17diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
18index 9982998..07bb370 100644
19--- a/drivers/spi/Kconfig
20+++ b/drivers/spi/Kconfig
21@@ -159,7 +159,7 @@ config SPI_BUTTERFLY
22
23 config SPI_CADENCE
24 tristate "Cadence SPI controller"
25- depends on ARM
26+ depends on ARM || ARM64
27 help
28 This selects the Cadence SPI controller master driver
29 used by Xilinx Zynq.
30--
312.1.1
32
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline/0004-arm64-mm-Correct-check-for-EXEC-faults.patch b/recipes-kernel/linux/linux-zynqmp-mainline/0004-arm64-mm-Correct-check-for-EXEC-faults.patch
new file mode 100644
index 00000000..438546da
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline/0004-arm64-mm-Correct-check-for-EXEC-faults.patch
@@ -0,0 +1,46 @@
1From 9f0f9df61d6c198528ba2fd43981b166ea337dd3 Mon Sep 17 00:00:00 2001
2From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
3Date: Mon, 28 Apr 2014 11:15:24 +1000
4Subject: [PATCH 4/7] arm64: mm: Correct check for EXEC faults
5
6ESR_LNX_EXEC doesn't match anything in the specs. Replace it
7with ESR.EC IABT based checks.
8
9Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10Signed-off-by: Michal Simek <michal.simek@xilinx.com>
11---
12 arch/arm64/mm/fault.c | 4 +++-
13 1 file changed, 3 insertions(+), 1 deletion(-)
14
15diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
16index c11cd27..276529a 100644
17--- a/arch/arm64/mm/fault.c
18+++ b/arch/arm64/mm/fault.c
19@@ -36,6 +36,7 @@
20 #include <asm/system_misc.h>
21 #include <asm/pgtable.h>
22 #include <asm/tlbflush.h>
23+#include <asm/esr.h>
24
25 static const char *fault_name(unsigned int esr);
26
27@@ -199,6 +200,7 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
28 int fault, sig, code;
29 unsigned long vm_flags = VM_READ | VM_WRITE | VM_EXEC;
30 unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
31+ unsigned long esr_ec = esr >> ESR_EL1_EC_SHIFT;
32
33 tsk = current;
34 mm = tsk->mm;
35@@ -217,7 +219,7 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
36 if (user_mode(regs))
37 mm_flags |= FAULT_FLAG_USER;
38
39- if (esr & ESR_LNX_EXEC) {
40+ if (esr_ec == ESR_EL1_EC_IABT_EL0 || esr_ec == ESR_EL1_EC_IABT_EL1) {
41 vm_flags = VM_EXEC;
42 } else if ((esr & ESR_EL1_WRITE) && !(esr & ESR_EL1_CM)) {
43 vm_flags = VM_WRITE;
44--
452.1.1
46
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline/0005-arm64-Implement-cpu_relax-as-yield.patch b/recipes-kernel/linux/linux-zynqmp-mainline/0005-arm64-Implement-cpu_relax-as-yield.patch
new file mode 100644
index 00000000..5f0c5a6d
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline/0005-arm64-Implement-cpu_relax-as-yield.patch
@@ -0,0 +1,33 @@
1From 9a7a3eb786ef4d7221c9090f2bd47933fbbdb047 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Thu, 12 Jun 2014 17:05:42 -0700
4Subject: [PATCH 5/7] arm64: Implement cpu_relax as yield
5
6ARM64 has the yield instruction which has the intended semantics of
7cpu_relax. Implement.
8
9Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
10Signed-off-by: Michal Simek <michal.simek@xilinx.com>
11---
12 arch/arm64/include/asm/processor.h | 5 ++++-
13 1 file changed, 4 insertions(+), 1 deletion(-)
14
15diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
16index f9be30e..334144d 100644
17--- a/arch/arm64/include/asm/processor.h
18+++ b/arch/arm64/include/asm/processor.h
19@@ -126,7 +126,10 @@ extern void release_thread(struct task_struct *);
20
21 unsigned long get_wchan(struct task_struct *p);
22
23-#define cpu_relax() barrier()
24+static inline void cpu_relax(void) {
25+ barrier();
26+ asm volatile("yield");
27+}
28 #define cpu_relax_lowlatency() cpu_relax()
29
30 /* Thread switching */
31--
322.1.1
33
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline/0006-arm64-spinlock-sev-when-unlocking-locks.patch b/recipes-kernel/linux/linux-zynqmp-mainline/0006-arm64-spinlock-sev-when-unlocking-locks.patch
new file mode 100644
index 00000000..bc90a758
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline/0006-arm64-spinlock-sev-when-unlocking-locks.patch
@@ -0,0 +1,28 @@
1From 761cba95ae66984cf60423190aefb3b794774033 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Thu, 12 Jun 2014 17:05:43 -0700
4Subject: [PATCH 6/7] arm64: spinlock: sev when unlocking locks
5
6Because spinners are doing a wfe in their poll of the lock.
7
8Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
9Signed-off-by: Michal Simek <michal.simek@xilinx.com>
10---
11 arch/arm64/include/asm/spinlock.h | 1 +
12 1 file changed, 1 insertion(+)
13
14diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
15index cee1287..c4df86f 100644
16--- a/arch/arm64/include/asm/spinlock.h
17+++ b/arch/arm64/include/asm/spinlock.h
18@@ -87,6 +87,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
19 {
20 asm volatile(
21 " stlrh %w1, %0\n"
22+" sev\n"
23 : "=Q" (lock->owner)
24 : "r" (lock->owner + 1)
25 : "memory");
26--
272.1.1
28
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline/0007-kbuild-Create-directory-for-target-DTB.patch b/recipes-kernel/linux/linux-zynqmp-mainline/0007-kbuild-Create-directory-for-target-DTB.patch
new file mode 100644
index 00000000..d90bdba9
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline/0007-kbuild-Create-directory-for-target-DTB.patch
@@ -0,0 +1,31 @@
1From d24f5867cd1120665c01fe001a601f335b99126b Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan.rossi@xilinx.com>
3Date: Wed, 18 Feb 2015 17:34:14 +1000
4Subject: [PATCH 7/7] kbuild: Create directory for target DTB
5
6When building specific DTBs out of the kernel tree the vendor subdirs
7(boot/dts/<vendor>) are not created, ensure that they are before
8building the DTB.
9
10Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
11---
12 scripts/Makefile.lib | 3 ++-
13 1 file changed, 2 insertions(+), 1 deletion(-)
14
15diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
16index 5117552..f195f97 100644
17--- a/scripts/Makefile.lib
18+++ b/scripts/Makefile.lib
19@@ -272,7 +272,8 @@ $(obj)/%.dtb.S: $(obj)/%.dtb
20 $(call cmd,dt_S_dtb)
21
22 quiet_cmd_dtc = DTC $@
23-cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
24+cmd_dtc = mkdir -p `dirname ${dtc-tmp}` ; \
25+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
26 $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \
27 -i $(dir $<) $(DTC_FLAGS) \
28 -d $(depfile).dtc.tmp $(dtc-tmp) ; \
29--
302.1.1
31
diff --git a/recipes-kernel/linux/linux-zynqmp-mainline_3.19.bb b/recipes-kernel/linux/linux-zynqmp-mainline_3.19.bb
new file mode 100644
index 00000000..af353bd1
--- /dev/null
+++ b/recipes-kernel/linux/linux-zynqmp-mainline_3.19.bb
@@ -0,0 +1,28 @@
1
2# Kernel version and SRCREV correspond to: xlnx_3.14 branch
3LINUX_VERSION = "3.19"
4KBRANCH ?= "master"
5SRCREV ?= "bfa76d49576599a4b9f9b7a71f23d73d6dcff735"
6
7include linux-xlnx.inc
8
9FILESEXTRAPATHS_prepend := "${THISDIR}/linux-zynqmp-mainline:"
10SRC_URI = " \
11 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git;protocol=https;branch=${KBRANCH} \
12 file://xilinx-base;type=kmeta;destsuffix=xilinx-base \
13 file://0001-ARM64-Add-new-Xilinx-ZynqMP-SoC.patch \
14 file://0002-net-cadence-Enable-MACB-driver-for-ARM64.patch \
15 file://0003-spi-Enable-Cadence-SPI-driver-for-ARM64.patch \
16 file://0004-arm64-mm-Correct-check-for-EXEC-faults.patch \
17 file://0005-arm64-Implement-cpu_relax-as-yield.patch \
18 file://0006-arm64-spinlock-sev-when-unlocking-locks.patch \
19 file://0007-kbuild-Create-directory-for-target-DTB.patch \
20 "
21
22COMPATIBLE_MACHINE_ep108-zynqmp = "ep108-zynqmp"
23COMPATIBLE_MACHINE_qemuzynqmp = "qemuzynqmp"
24KMACHINE_ep108-zynqmp ?= "zynqmp"
25KMACHINE_qemuzynqmp ?= "zynqmp"
26
27KERNEL_DEVICETREE_ep108-zynqmp = "xilinx/zynqmp-ep108.dtb"
28KERNEL_DEVICETREE_qemuzynqmp = "xilinx/zynqmp-ep108.dtb"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 16:58:56 +0000