qemu: Added patches for Zynq work-arounds

Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>

3 files changed, 72 insertions, 0 deletions

diff --git a/recipes-devtools/qemu/files/HACK_target-arm_Harcode_the_SCU_offset.patch b/recipes-devtools/qemu/files/HACK_target-arm_Harcode_the_SCU_offset.patch
new file mode 100644
index 00000000..68c8dfaa
--- /dev/null
+++ b/recipes-devtools/qemu/files/HACK_target-arm_Harcode_the_SCU_offset.patch
@@ -0,0 +1,22 @@
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Fri, 15 Feb 2013 07:08:24 +0000
+Subject: HACK: target-arm: Harcode the SCU offset
+
+Becuase the QOM framework to drive this from a property isnt there yet.
+
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+---
+diff --git a/target-arm/cpu.c b/target-arm/cpu.c
+index 496a59f..705688b 100644
+--- a/target-arm/cpu.c
++++ b/target-arm/cpu.c
+@@ -531,7 +531,7 @@ static void cortex_a9_initfn(Object *obj)
+     {
+         ARMCPRegInfo cbar = {
+             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
+-            .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
++            .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = 0xf8f00000,
+             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
+         };
+         define_one_arm_cp_reg(cpu, &cbar);
+--
diff --git a/recipes-devtools/qemu/files/HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch b/recipes-devtools/qemu/files/HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch
new file mode 100644
index 00000000..527422b5
--- /dev/null
+++ b/recipes-devtools/qemu/files/HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch
@@ -0,0 +1,48 @@
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Wed, 27 Mar 2013 02:00:09 +0000
+Subject: HACK: zynq_slcr: Bring SLCR out of reset in kernel state
+
+Reset the zynq_slcr into something more closely resembling the post
+FSBL handoff state. Needed to keep the Linux clock framework happy.
+
+I can only apply this patch (in its current form), to the workarounds
+branch but I am RFCing it, as if there are any other things I should
+be changing, let me know! I'll factor them into a real solution.
+
+Cc: sorenb@xilinx.com
+Cc: michal.simek@xilinx.com
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+---
+diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
+index 872ba3f..8f3e614 100644
+--- a/hw/misc/zynq_slcr.c
++++ b/hw/misc/zynq_slcr.c
+@@ -243,19 +243,19 @@ static void zynq_slcr_reset(DeviceState *d)
+ 
+     s->lockval = 1;
+     /* 0x100 - 0x11C */
+-    s->pll[ARM_PLL_CTRL] = 0x0001A008;
+-    s->pll[DDR_PLL_CTRL] = 0x0001A008;
+-    s->pll[IO_PLL_CTRL] = 0x0001A008;
++    s->pll[ARM_PLL_CTRL] = 0x00028008;
++    s->pll[DDR_PLL_CTRL] = 0x00020008;
++    s->pll[IO_PLL_CTRL] = 0x0001e008;
+     s->pll[PLL_STATUS] = 0x0000003F;
+-    s->pll[ARM_PPL_CFG] = 0x00014000;
+-    s->pll[DDR_PLL_CFG] = 0x00014000;
+-    s->pll[IO_PLL_CFG] = 0x00014000;
++    s->pll[ARM_PPL_CFG] = 0x000fa220;
++    s->pll[DDR_PLL_CFG] = 0x0012c220;
++    s->pll[IO_PLL_CFG] = 0x001452c0;
+ 
+     /* 0x120 - 0x16C */
+-    s->clk[ARM_CLK_CTRL] = 0x1F000400;
++    s->clk[ARM_CLK_CTRL] = 0x1F000200;
+     s->clk[DDR_CLK_CTRL] = 0x18400003;
+     s->clk[DCI_CLK_CTRL] = 0x01E03201;
+-    s->clk[APER_CLK_CTRL] = 0x01FFCCCD;
++    s->clk[APER_CLK_CTRL] = 0x01ed044d;
+     s->clk[USB0_CLK_CTRL] = s->clk[USB1_CLK_CTRL] = 0x00101941;
+     s->clk[GEM0_RCLK_CTRL] = s->clk[GEM1_RCLK_CTRL] = 0x00000001;
+     s->clk[GEM0_CLK_CTRL] = s->clk[GEM1_CLK_CTRL] = 0x00003C01;
+--
diff --git a/recipes-devtools/qemu/qemu_1.5.0.bbappend b/recipes-devtools/qemu/qemu_1.5.0.bbappend
index 28c67341..584c2540 100644
--- a/recipes-devtools/qemu/qemu_1.5.0.bbappend
+++ b/recipes-devtools/qemu/qemu_1.5.0.bbappend
@@ -3,4 +3,6 @@ QEMU_TARGETS += "microblazeel"
 FILESEXTRAPATHS_append := "${THISDIR}/files:"
 SRC_URI_append += " \
                 file://microblaze-Add-support-for-loading-initrd-images.patch \
+                file://HACK_target-arm_Harcode_the_SCU_offset.patch \
+                file://HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch \
                 "