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authorNathan Rossi <nathan@nathanrossi.com>2016-02-24 15:33:09 +1000
committerNathan Rossi <nathan@nathanrossi.com>2016-03-06 20:04:03 +1000
commit925ae9c8ef5843cba89326975572e11f61ccaf32 (patch)
tree7c35fb1f8b984711e2c47e55c6dce331f91ca636 /recipes-bsp
parentcf98526e4f837576a18e889bf9cc91e985289ebc (diff)
downloadmeta-xilinx-925ae9c8ef5843cba89326975572e11f61ccaf32.tar.gz
kc705-trd-microblazeel: Move device tree to device-tree recipe
* Move the device tree into the source files directory for the device-tree recipe * Use non-immediate set for MACHINE_DEVICETREE Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Diffstat (limited to 'recipes-bsp')
-rw-r--r--recipes-bsp/device-tree/files/kc705/kc705-trd-microblazeel.dts526
1 files changed, 526 insertions, 0 deletions
diff --git a/recipes-bsp/device-tree/files/kc705/kc705-trd-microblazeel.dts b/recipes-bsp/device-tree/files/kc705/kc705-trd-microblazeel.dts
new file mode 100644
index 00000000..c087433d
--- /dev/null
+++ b/recipes-bsp/device-tree/files/kc705/kc705-trd-microblazeel.dts
@@ -0,0 +1,526 @@
1/dts-v1/;
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "xlnx,microblaze";
6 model = "Xilinx-KC705-TRD";
7 ddr3_sdram: memory@80000000 {
8 device_type = "memory";
9 reg = < 0x80000000 0x40000000 >;
10 } ;
11 aliases {
12 ethernet0 = &soft_ethernet_mac;
13 serial0 = &rs232_uart_1;
14 } ;
15 chosen {
16 bootargs = "console=ttyS0,115200 root=/dev/ram rw udev.children-max=1";
17 linux,stdout-path = "/axi@2/serial@40400000";
18 } ;
19 cpus {
20 #address-cells = <1>;
21 #cpus = <0x1>;
22 #size-cells = <0>;
23 microblaze_0: cpu@0 {
24 bus-handle = <&axi_mm_mb>, <&axi4_0>, <&axi4lite_0>;
25 clock-frequency = <150000000>;
26 clocks = <&clk_cpu>;
27 compatible = "xlnx,microblaze-8.50.a";
28 d-cache-baseaddr = <0x80000000>;
29 d-cache-highaddr = <0xffffffff>;
30 d-cache-line-size = <0x20>;
31 d-cache-size = <0x2000>;
32 device_type = "cpu";
33 i-cache-baseaddr = <0x80000000>;
34 i-cache-highaddr = <0xffffffff>;
35 i-cache-line-size = <0x20>;
36 i-cache-size = <0x2000>;
37 model = "microblaze,8.50.a";
38 reg = <0>;
39 timebase-frequency = <150000000>;
40 xlnx,addr-tag-bits = <0x12>;
41 xlnx,allow-dcache-wr = <0x1>;
42 xlnx,allow-icache-wr = <0x1>;
43 xlnx,area-optimized = <0x0>;
44 xlnx,avoid-primitives = <0x0>;
45 xlnx,base-vectors = <0x0>;
46 xlnx,branch-target-cache-size = <0x0>;
47 xlnx,cache-byte-size = <0x2000>;
48 xlnx,d-axi = <0x1>;
49 xlnx,d-lmb = <0x1>;
50 xlnx,d-plb = <0x0>;
51 xlnx,data-size = <0x20>;
52 xlnx,dcache-addr-tag = <0x12>;
53 xlnx,dcache-always-used = <0x1>;
54 xlnx,dcache-byte-size = <0x2000>;
55 xlnx,dcache-data-width = <0x0>;
56 xlnx,dcache-force-tag-lutram = <0x1>;
57 xlnx,dcache-interface = <0x0>;
58 xlnx,dcache-line-len = <0x8>;
59 xlnx,dcache-use-fsl = <0x0>;
60 xlnx,dcache-use-writeback = <0x0>;
61 xlnx,dcache-victims = <0x0>;
62 xlnx,debug-enabled = <0x1>;
63 xlnx,div-zero-exception = <0x0>;
64 xlnx,dynamic-bus-sizing = <0x1>;
65 xlnx,ecc-use-ce-exception = <0x0>;
66 xlnx,edge-is-positive = <0x1>;
67 xlnx,endianness = <0x1>;
68 xlnx,family = "kintex7";
69 xlnx,fault-tolerant = <0x0>;
70 xlnx,fpu-exception = <0x0>;
71 xlnx,freq = <0x8f0d180>;
72 xlnx,fsl-data-size = <0x20>;
73 xlnx,fsl-exception = <0x0>;
74 xlnx,fsl-links = <0x0>;
75 xlnx,i-axi = <0x0>;
76 xlnx,i-lmb = <0x1>;
77 xlnx,i-plb = <0x0>;
78 xlnx,icache-always-used = <0x1>;
79 xlnx,icache-data-width = <0x0>;
80 xlnx,icache-force-tag-lutram = <0x1>;
81 xlnx,icache-interface = <0x0>;
82 xlnx,icache-line-len = <0x8>;
83 xlnx,icache-streams = <0x0>;
84 xlnx,icache-use-fsl = <0x0>;
85 xlnx,icache-victims = <0x0>;
86 xlnx,ill-opcode-exception = <0x1>;
87 xlnx,instance = "microblaze_0";
88 xlnx,interconnect = <0x2>;
89 xlnx,interrupt-is-edge = <0x0>;
90 xlnx,lockstep-slave = <0x0>;
91 xlnx,mmu-dtlb-size = <0x2>;
92 xlnx,mmu-itlb-size = <0x2>;
93 xlnx,mmu-privileged-instr = <0x0>;
94 xlnx,mmu-tlb-access = <0x3>;
95 xlnx,mmu-zones = <0x2>;
96 xlnx,number-of-pc-brk = <0x1>;
97 xlnx,number-of-rd-addr-brk = <0x0>;
98 xlnx,number-of-wr-addr-brk = <0x0>;
99 xlnx,opcode-0x0-illegal = <0x1>;
100 xlnx,optimization = <0x0>;
101 xlnx,pc-width = <0x20>;
102 xlnx,pvr = <0x2>;
103 xlnx,pvr-user1 = <0x0>;
104 xlnx,pvr-user2 = <0x0>;
105 xlnx,reset-msr = <0x0>;
106 xlnx,sco = <0x0>;
107 xlnx,stream-interconnect = <0x0>;
108 xlnx,unaligned-exceptions = <0x1>;
109 xlnx,use-barrel = <0x1>;
110 xlnx,use-branch-target-cache = <0x0>;
111 xlnx,use-dcache = <0x1>;
112 xlnx,use-div = <0x0>;
113 xlnx,use-ext-brk = <0x1>;
114 xlnx,use-ext-nm-brk = <0x1>;
115 xlnx,use-extended-fsl-instr = <0x0>;
116 xlnx,use-fpu = <0x0>;
117 xlnx,use-hw-mul = <0x1>;
118 xlnx,use-icache = <0x1>;
119 xlnx,use-interrupt = <0x1>;
120 xlnx,use-mmu = <0x3>;
121 xlnx,use-msr-instr = <0x1>;
122 xlnx,use-pcmp-instr = <0x1>;
123 xlnx,use-reorder-instr = <0x1>;
124 xlnx,use-stack-protection = <0x0>;
125 } ;
126 } ;
127 clocks {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 clk_bus: bus {
131 #clock-cells = <0>;
132 clock-frequency = <100000000>;
133 clock-output-names = "bus";
134 compatible = "fixed-clock";
135 reg = <1>;
136 } ;
137 clk_cpu: cpu {
138 #clock-cells = <0>;
139 clock-frequency = <150000000>;
140 clock-output-names = "cpu";
141 compatible = "fixed-clock";
142 reg = <0>;
143 } ;
144 } ;
145 axi4lite_0: axi@2 {
146 #address-cells = <1>;
147 #size-cells = <1>;
148 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
149 ranges ;
150 axi_dma_ethernet: axi-dma@50000000 {
151 axistream-connected = <&soft_ethernet_mac>;
152 axistream-control-connected = <&soft_ethernet_mac>;
153 compatible = "xlnx,axi-dma-6.03.a", "xlnx,axi-dma-1.00.a";
154 interrupt-parent = <&interrupt_cntlr>;
155 interrupts = < 0 2 1 2 >;
156 reg = < 0x50000000 0x10000 >;
157 xlnx,dlytmr-resolution = <0x4e2>;
158 xlnx,enable-multi-channel = <0x0>;
159 xlnx,family = "kintex7";
160 xlnx,generic = <0x0>;
161 xlnx,include-mm2s = <0x1>;
162 xlnx,include-mm2s-dre = <0x1>;
163 xlnx,include-mm2s-sf = <0x1>;
164 xlnx,include-s2mm = <0x1>;
165 xlnx,include-s2mm-dre = <0x1>;
166 xlnx,include-s2mm-sf = <0x1>;
167 xlnx,include-sg = <0x1>;
168 xlnx,instance = "AXI_DMA_Ethernet";
169 xlnx,mm2s-burst-size = <0x10>;
170 xlnx,num-mm2s-channels = <0x1>;
171 xlnx,num-s2mm-channels = <0x1>;
172 xlnx,prmry-is-aclk-async = <0x1>;
173 xlnx,s2mm-burst-size = <0x10>;
174 xlnx,sg-include-desc-queue = <0x1>;
175 xlnx,sg-include-stscntrl-strm = <0x1>;
176 xlnx,sg-length-width = <0x10>;
177 xlnx,sg-use-stsapp-length = <0x1>;
178 } ;
179 axi_xadc_0: axi-xadc@40d00000 {
180 clocks = <&clk_bus>;
181 compatible = "xlnx,axi-xadc-1.00.a";
182 interrupt-parent = <&interrupt_cntlr>;
183 interrupts = < 7 2 >;
184 reg = < 0x40d00000 0x10000 >;
185 xlnx,family = "kintex7";
186 xlnx,has-temp-bus = <0x1>;
187 xlnx,include-intr = <0x1>;
188 xlnx,instance = "axi_xadc_0";
189 xlnx,sim-monitor-file = "Sysmon_Design.txt";
190 } ;
191 debug_module: serial@40200000 {
192 compatible = "xlnx,mdm-2.10.a", "xlnx,xps-uartlite-1.00.a";
193 reg = < 0x40200000 0x10000 >;
194 xlnx,family = "kintex7";
195 xlnx,interconnect = <0x2>;
196 xlnx,jtag-chain = <0x2>;
197 xlnx,mb-dbg-ports = <0x1>;
198 xlnx,use-bscan = <0x0>;
199 xlnx,use-uart = <0x1>;
200 } ;
201 dip_switches_4bits: gpio@40700000 {
202 #gpio-cells = <2>;
203 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
204 gpio-controller ;
205 reg = < 0x40700000 0x10000 >;
206 xlnx,all-inputs = <0x1>;
207 xlnx,all-inputs-2 = <0x0>;
208 xlnx,dout-default = <0x0>;
209 xlnx,dout-default-2 = <0x0>;
210 xlnx,family = "kintex7";
211 xlnx,gpio-width = <0x4>;
212 xlnx,gpio2-width = <0x20>;
213 xlnx,instance = "DIP_Switches_4Bits";
214 xlnx,interrupt-present = <0x1>;
215 xlnx,is-dual = <0x0>;
216 xlnx,tri-default = <0xffffffff>;
217 xlnx,tri-default-2 = <0xffffffff>;
218 } ;
219 dual_timer_counter: system-timer@40300000 {
220 clock-frequency = <100000000>;
221 clocks = <&clk_bus>;
222 compatible = "xlnx,axi-timer-1.03.a", "xlnx,xps-timer-1.00.a";
223 interrupt-parent = <&interrupt_cntlr>;
224 interrupts = < 3 2 >;
225 reg = < 0x40300000 0x10000 >;
226 xlnx,count-width = <0x20>;
227 xlnx,family = "kintex7";
228 xlnx,gen0-assert = <0x1>;
229 xlnx,gen1-assert = <0x1>;
230 xlnx,instance = "Dual_Timer_Counter";
231 xlnx,one-timer-only = <0x0>;
232 xlnx,trig0-assert = <0x1>;
233 xlnx,trig1-assert = <0x1>;
234 } ;
235 iic_eeprom: i2c@40a00000 {
236 compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
237 interrupt-parent = <&interrupt_cntlr>;
238 interrupts = < 4 2 >;
239 reg = < 0x40a00000 0x10000 >;
240 xlnx,family = "kintex7";
241 xlnx,gpo-width = <0x1>;
242 xlnx,iic-freq = <0x186a0>;
243 xlnx,instance = "IIC_EEPROM";
244 xlnx,scl-inertial-delay = <0x0>;
245 xlnx,sda-inertial-delay = <0x0>;
246 xlnx,sda-level = <0x1>;
247 xlnx,ten-bit-adr = <0x0>;
248 } ;
249 interrupt_cntlr: interrupt-controller@40100000 {
250 #interrupt-cells = <0x2>;
251 compatible = "xlnx,axi-intc-1.03.a", "xlnx,xps-intc-1.00.a";
252 interrupt-controller ;
253 reg = < 0x40100000 0x10000 >;
254 xlnx,kind-of-intr = <0x0>;
255 xlnx,num-intr-inputs = <0x8>;
256 } ;
257 lcd_gpio: gpio@40800000 {
258 #gpio-cells = <2>;
259 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
260 gpio-controller ;
261 reg = < 0x40800000 0x10000 >;
262 xlnx,all-inputs = <0x0>;
263 xlnx,all-inputs-2 = <0x0>;
264 xlnx,dout-default = <0x0>;
265 xlnx,dout-default-2 = <0x0>;
266 xlnx,family = "kintex7";
267 xlnx,gpio-width = <0x7>;
268 xlnx,gpio2-width = <0x20>;
269 xlnx,instance = "LCD_GPIO";
270 xlnx,interrupt-present = <0x0>;
271 xlnx,is-dual = <0x0>;
272 xlnx,tri-default = <0xffffffff>;
273 xlnx,tri-default-2 = <0xffffffff>;
274 } ;
275 leds_8bits: gpio@40600000 {
276 #gpio-cells = <2>;
277 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
278 gpio-controller ;
279 reg = < 0x40600000 0x10000 >;
280 xlnx,all-inputs = <0x0>;
281 xlnx,all-inputs-2 = <0x0>;
282 xlnx,dout-default = <0x0>;
283 xlnx,dout-default-2 = <0x0>;
284 xlnx,family = "kintex7";
285 xlnx,gpio-width = <0x8>;
286 xlnx,gpio2-width = <0x20>;
287 xlnx,instance = "LEDs_8Bits";
288 xlnx,interrupt-present = <0x1>;
289 xlnx,is-dual = <0x0>;
290 xlnx,tri-default = <0xffffffff>;
291 xlnx,tri-default-2 = <0xffffffff>;
292 } ;
293 logisdhc_0: logisdhc@40b00000 {
294 compatible = "xlnx,logisdhc-1.06.c";
295 interrupt-parent = <&interrupt_cntlr>;
296 interrupts = < 6 2 >;
297 reg = < 0x40b00000 0x10000 >;
298 xlnx,byte-per-pixel = <0x4>;
299 xlnx,convert-endianess = <0x0>;
300 xlnx,dma-type = <0x1>;
301 xlnx,family = "kintex7";
302 xlnx,ip-license-type = <0x1>;
303 xlnx,ip-major-revision = <0x1>;
304 xlnx,ip-minor-revision = <0x6>;
305 xlnx,ip-patch-level = <0x2>;
306 xlnx,mem-burst = <0x4>;
307 xlnx,mem-data-bus-width = <0x20>;
308 xlnx,mem-interface = <0x1>;
309 xlnx,regs-interface = <0x2>;
310 xlnx,row-stride = <0x400>;
311 xlnx,sd-base-clock-freq = <0x64>;
312 xlnx,use-dma = <0x0>;
313 } ;
314 primary_flash: flash@48000000 {
315 #address-cells = <1>;
316 #size-cells = <1>;
317 bank-width = <2>;
318 compatible = "xlnx,axi-emc-1.03.b", "cfi-flash";
319 reg = < 0x48000000 0x8000000 >;
320 xlnx,axi-clk-period-ps = <0x2710>;
321 xlnx,family = "kintex7";
322 xlnx,include-datawidth-matching-0 = <0x1>;
323 xlnx,include-datawidth-matching-1 = <0x0>;
324 xlnx,include-datawidth-matching-2 = <0x0>;
325 xlnx,include-datawidth-matching-3 = <0x0>;
326 xlnx,include-negedge-ioregs = <0x0>;
327 xlnx,instance = "Linear_Flash";
328 xlnx,lflash-period-ps = <0x4e20>;
329 xlnx,linear-flash-sync-burst = <0x0>;
330 xlnx,max-mem-width = <0x10>;
331 xlnx,mem0-type = <0x2>;
332 xlnx,mem0-width = <0x10>;
333 xlnx,mem1-type = <0x0>;
334 xlnx,mem1-width = <0x20>;
335 xlnx,mem2-type = <0x0>;
336 xlnx,mem2-width = <0x20>;
337 xlnx,mem3-type = <0x0>;
338 xlnx,mem3-width = <0x20>;
339 xlnx,num-banks-mem = <0x1>;
340 xlnx,parity-type-mem-0 = <0x0>;
341 xlnx,parity-type-mem-1 = <0x0>;
342 xlnx,parity-type-mem-2 = <0x0>;
343 xlnx,parity-type-mem-3 = <0x0>;
344 xlnx,s-axi-en-reg = <0x0>;
345 xlnx,s-axi-mem-addr-width = <0x20>;
346 xlnx,s-axi-mem-data-width = <0x20>;
347 xlnx,s-axi-mem-id-width = <0x1>;
348 xlnx,s-axi-mem-protocol = "AXI4LITE";
349 xlnx,s-axi-reg-addr-width = <0x5>;
350 xlnx,s-axi-reg-data-width = <0x20>;
351 xlnx,s-axi-reg-protocol = "axi4";
352 xlnx,synch-pipedelay-0 = <0x2>;
353 xlnx,synch-pipedelay-1 = <0x2>;
354 xlnx,synch-pipedelay-2 = <0x2>;
355 xlnx,synch-pipedelay-3 = <0x2>;
356 xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
357 xlnx,tavdv-ps-mem-1 = <0x3a98>;
358 xlnx,tavdv-ps-mem-2 = <0x3a98>;
359 xlnx,tavdv-ps-mem-3 = <0x3a98>;
360 xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
361 xlnx,tcedv-ps-mem-1 = <0x3a98>;
362 xlnx,tcedv-ps-mem-2 = <0x3a98>;
363 xlnx,tcedv-ps-mem-3 = <0x3a98>;
364 xlnx,thzce-ps-mem-0 = <0x88b8>;
365 xlnx,thzce-ps-mem-1 = <0x1b58>;
366 xlnx,thzce-ps-mem-2 = <0x1b58>;
367 xlnx,thzce-ps-mem-3 = <0x1b58>;
368 xlnx,thzoe-ps-mem-0 = <0x1b58>;
369 xlnx,thzoe-ps-mem-1 = <0x1b58>;
370 xlnx,thzoe-ps-mem-2 = <0x1b58>;
371 xlnx,thzoe-ps-mem-3 = <0x1b58>;
372 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
373 xlnx,tlzwe-ps-mem-1 = <0x0>;
374 xlnx,tlzwe-ps-mem-2 = <0x0>;
375 xlnx,tlzwe-ps-mem-3 = <0x0>;
376 xlnx,tpacc-ps-flash-0 = <0x61a8>;
377 xlnx,tpacc-ps-flash-1 = <0x61a8>;
378 xlnx,tpacc-ps-flash-2 = <0x61a8>;
379 xlnx,tpacc-ps-flash-3 = <0x61a8>;
380 xlnx,twc-ps-mem-0 = <0x11170>;
381 xlnx,twc-ps-mem-1 = <0x3a98>;
382 xlnx,twc-ps-mem-2 = <0x3a98>;
383 xlnx,twc-ps-mem-3 = <0x3a98>;
384 xlnx,twp-ps-mem-0 = <0x11170>;
385 xlnx,twp-ps-mem-1 = <0x2ee0>;
386 xlnx,twp-ps-mem-2 = <0x2ee0>;
387 xlnx,twp-ps-mem-3 = <0x2ee0>;
388 xlnx,twph-ps-mem-0 = <0x2ee0>;
389 xlnx,twph-ps-mem-1 = <0x2ee0>;
390 xlnx,twph-ps-mem-2 = <0x2ee0>;
391 xlnx,twph-ps-mem-3 = <0x2ee0>;
392 xlnx,wr-rec-time-mem-0 = <0x186a0>;
393 xlnx,wr-rec-time-mem-1 = <0x186a0>;
394 xlnx,wr-rec-time-mem-2 = <0x186a0>;
395 xlnx,wr-rec-time-mem-3 = <0x186a0>;
396 partition@0x00000000 {
397 label = "fpga";
398 reg = <0x00000000 0x00200000>;
399 };
400 partition@0x00200000 {
401 label = "boot";
402 reg = <0x00200000 0x00040000>;
403 };
404 partition@0x00240000 {
405 label = "bootenv";
406 reg = <0x00240000 0x00020000>;
407 };
408 partition@0x00260000 {
409 label = "image";
410 reg = <0x00260000 0x00c00000>;
411 };
412 partition@0x00e60000 {
413 label = "spare";
414 reg = <0x00e60000 0x00000000>;
415 };
416 } ;
417 push_buttons_5bits: gpio@40500000 {
418 #gpio-cells = <2>;
419 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
420 gpio-controller ;
421 reg = < 0x40500000 0x10000 >;
422 xlnx,all-inputs = <0x1>;
423 xlnx,all-inputs-2 = <0x0>;
424 xlnx,dout-default = <0x0>;
425 xlnx,dout-default-2 = <0x0>;
426 xlnx,family = "kintex7";
427 xlnx,gpio-width = <0x5>;
428 xlnx,gpio2-width = <0x20>;
429 xlnx,instance = "Push_Buttons_5Bits";
430 xlnx,interrupt-present = <0x1>;
431 xlnx,is-dual = <0x0>;
432 xlnx,tri-default = <0xffffffff>;
433 xlnx,tri-default-2 = <0xffffffff>;
434 } ;
435 rotary_gpio: gpio@40900000 {
436 #gpio-cells = <2>;
437 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
438 gpio-controller ;
439 reg = < 0x40900000 0x10000 >;
440 xlnx,all-inputs = <0x1>;
441 xlnx,all-inputs-2 = <0x0>;
442 xlnx,dout-default = <0x0>;
443 xlnx,dout-default-2 = <0x0>;
444 xlnx,family = "kintex7";
445 xlnx,gpio-width = <0x3>;
446 xlnx,gpio2-width = <0x20>;
447 xlnx,instance = "ROTARY_GPIO";
448 xlnx,interrupt-present = <0x0>;
449 xlnx,is-dual = <0x0>;
450 xlnx,tri-default = <0xffffffff>;
451 xlnx,tri-default-2 = <0xffffffff>;
452 } ;
453 rs232_uart_1: serial@40400000 {
454 clock-frequency = <100000000>;
455 clocks = <&clk_bus>;
456 compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550a";
457 current-speed = <115200>;
458 device_type = "serial";
459 interrupt-parent = <&interrupt_cntlr>;
460 interrupts = < 5 2 >;
461 reg = < 0x40400000 0x10000 >;
462 reg-offset = <0x1000>;
463 reg-shift = <2>;
464 xlnx,external-xin-clk-hz = <0x17d7840>;
465 xlnx,family = "kintex7";
466 xlnx,has-external-rclk = <0x0>;
467 xlnx,has-external-xin = <0x0>;
468 xlnx,instance = "RS232_Uart_1";
469 xlnx,is-a-16550 = <0x1>;
470 xlnx,use-modem-ports = <0x0>;
471 xlnx,use-user-ports = <0x0>;
472 } ;
473 soft_ethernet_mac: axi-ethernet@50100000 {
474 axistream-connected = <&axi_dma_ethernet>;
475 axistream-control-connected = <&axi_dma_ethernet>;
476 clock-frequency = <100000000>;
477 clocks = <&clk_bus>;
478 compatible = "xlnx,axi-ethernet-3.01.a", "xlnx,axi-ethernet-1.00.a";
479 device_type = "network";
480 interrupt-parent = <&interrupt_cntlr>;
481 interrupts = < 2 2 >;
482 local-mac-address = [ 00 0a 35 00 d9 4e ];
483 phy-handle = <&phy0>;
484 reg = < 0x50100000 0x40000 >;
485 xlnx,avb = <0x0>;
486 xlnx,halfdup = <0x0>;
487 xlnx,include-io = <0x1>;
488 xlnx,mcast-extend = <0x0>;
489 xlnx,phy-type = <0x1>;
490 xlnx,phyaddr = <0x1>;
491 xlnx,rxcsum = <0x0>;
492 xlnx,rxmem = <0x1000>;
493 xlnx,rxvlan-strp = <0x0>;
494 xlnx,rxvlan-tag = <0x0>;
495 xlnx,rxvlan-tran = <0x0>;
496 xlnx,stats = <0x0>;
497 xlnx,txcsum = <0x0>;
498 xlnx,txmem = <0x1000>;
499 xlnx,txvlan-strp = <0x0>;
500 xlnx,txvlan-tag = <0x0>;
501 xlnx,txvlan-tran = <0x0>;
502 xlnx,type = <0x1>;
503 mdio {
504 #address-cells = <1>;
505 #size-cells = <0>;
506 phy0: phy@7 {
507 compatible = "marvell,88e1111";
508 device_type = "ethernet-phy";
509 reg = <7>;
510 } ;
511 } ;
512 } ;
513 } ;
514 axi_mm_mb: axi@1 {
515 #address-cells = <1>;
516 #size-cells = <1>;
517 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
518 ranges ;
519 axi4_0: axi@0 {
520 #address-cells = <1>;
521 #size-cells = <1>;
522 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
523 ranges = < 0x80000000 0x80000000 0x40000000 >;
524 } ;
525 } ;
526} ;
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 20:24:27 +0000