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authorManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2016-05-12 17:31:29 -0700
committerNathan Rossi <nathan@nathanrossi.com>2016-05-13 17:14:00 +1000
commit2660bf2ae5ad04c83dafd23f84ff6711d6a460a3 (patch)
tree377245e9300740521896e31c2d3a74b17af3517e /recipes-bsp
parent886535180b7b29a36c96004d5ed3b72c72e97ebb (diff)
downloadmeta-xilinx-2660bf2ae5ad04c83dafd23f84ff6711d6a460a3.tar.gz
kc705-microblazeel: Add u-boot patch for KC705
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Diffstat (limited to 'recipes-bsp')
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch1156
1 files changed, 1156 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch
new file mode 100644
index 00000000..05011f94
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch
@@ -0,0 +1,1156 @@
1From 5b6177a13aa531125cf5a80cfca9746ea37d98e8 Mon Sep 17 00:00:00 2001
2From: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
3Date: Tue, 26 Apr 2016 17:16:25 -0700
4Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to kc705-microblazeel
5
6This is an update to earlier kc705-trd patch done by Nathan Rossi. Starting
7from v2016.1, KC705 will no longer refer to deprecated KC705 TRD application.
8
9Change the microblaze-generic board to match the kc705-microblazeel. This patch
10is not intended for upstream and serves as an intermediate solution
11until OF support in upstream u-boot allows for easy support for custom
12microblaze boards.
13
14Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
15Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
16---
17 arch/microblaze/dts/microblaze-generic.dts | 515 ++++++++++++++++++++++++++++
18 board/xilinx/microblaze-generic/config.mk | 24 +-
19 configs/microblaze-generic_defconfig | 17 +-
20 include/configs/microblaze-generic.h | 520 +++++++++++------------------
21 4 files changed, 721 insertions(+), 355 deletions(-)
22
23diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
24index 2033309..c97cf0d 100644
25--- a/arch/microblaze/dts/microblaze-generic.dts
26+++ b/arch/microblaze/dts/microblaze-generic.dts
27@@ -2,6 +2,521 @@
28 / {
29 #address-cells = <1>;
30 #size-cells = <1>;
31+ model = "Xilinx MicroBlaze";
32+ hard-reset-gpios = <0x1 0x0 0x1>;
33+ compatible = "xlnx,microblaze";
34+
35 aliases {
36+ serial0 = "/amba_pl/serial@44a00000";
37+ ethernet0 = "/amba_pl/ethernet@40c00000";
38+ };
39+
40+ chosen {
41+ bootargs = "console=ttyS0,115200 earlyprintk";
42+ stdout-path = "serial0:115200ns";
43+ };
44+
45+ memory {
46+ device_type = "memory";
47+ reg = <0x80000000 0x40000000>;
48+ };
49+
50+ cpus {
51+ #address-cells = <0x1>;
52+ #cpus = <0x1>;
53+ #size-cells = <0x0>;
54+
55+ cpu@0 {
56+ bus-handle = <0x2>;
57+ clock-frequency = <0xbebc200>;
58+ clocks = <0x3>;
59+ compatible = "xlnx,microblaze-9.6";
60+ d-cache-baseaddr = <0x80000000>;
61+ d-cache-highaddr = <0xbfffffff>;
62+ d-cache-line-size = <0x20>;
63+ d-cache-size = <0x4000>;
64+ device_type = "cpu";
65+ i-cache-baseaddr = <0x80000000>;
66+ i-cache-highaddr = <0xbfffffff>;
67+ i-cache-line-size = <0x10>;
68+ i-cache-size = <0x4000>;
69+ interrupt-handle = <0x4>;
70+ model = "microblaze,9.6";
71+ timebase-frequency = <0xbebc200>;
72+ xlnx,addr-size = <0x20>;
73+ xlnx,addr-tag-bits = <0x10>;
74+ xlnx,allow-dcache-wr = <0x1>;
75+ xlnx,allow-icache-wr = <0x1>;
76+ xlnx,area-optimized = <0x0>;
77+ xlnx,async-interrupt = <0x1>;
78+ xlnx,async-wakeup = <0x3>;
79+ xlnx,avoid-primitives = <0x0>;
80+ xlnx,base-vectors = <0x0>;
81+ xlnx,branch-target-cache-size = <0x0>;
82+ xlnx,cache-byte-size = <0x4000>;
83+ xlnx,d-axi = <0x1>;
84+ xlnx,d-lmb = <0x1>;
85+ xlnx,d-lmb-mon = <0x0>;
86+ xlnx,daddr-size = <0x20>;
87+ xlnx,data-size = <0x20>;
88+ xlnx,dc-axi-mon = <0x0>;
89+ xlnx,dcache-addr-tag = <0x10>;
90+ xlnx,dcache-always-used = <0x1>;
91+ xlnx,dcache-byte-size = <0x4000>;
92+ xlnx,dcache-data-width = <0x0>;
93+ xlnx,dcache-force-tag-lutram = <0x0>;
94+ xlnx,dcache-line-len = <0x8>;
95+ xlnx,dcache-use-writeback = <0x0>;
96+ xlnx,dcache-victims = <0x0>;
97+ xlnx,debug-counter-width = <0x20>;
98+ xlnx,debug-enabled = <0x1>;
99+ xlnx,debug-event-counters = <0x5>;
100+ xlnx,debug-external-trace = <0x0>;
101+ xlnx,debug-latency-counters = <0x1>;
102+ xlnx,debug-profile-size = <0x0>;
103+ xlnx,debug-trace-size = <0x2000>;
104+ xlnx,div-zero-exception = <0x1>;
105+ xlnx,dp-axi-mon = <0x0>;
106+ xlnx,dynamic-bus-sizing = <0x0>;
107+ xlnx,ecc-use-ce-exception = <0x0>;
108+ xlnx,edge-is-positive = <0x1>;
109+ xlnx,enable-discrete-ports = <0x0>;
110+ xlnx,endianness = <0x1>;
111+ xlnx,fault-tolerant = <0x0>;
112+ xlnx,fpu-exception = <0x0>;
113+ xlnx,freq = <0xbebc200>;
114+ xlnx,fsl-exception = <0x0>;
115+ xlnx,fsl-links = <0x0>;
116+ xlnx,i-axi = <0x0>;
117+ xlnx,i-lmb = <0x1>;
118+ xlnx,i-lmb-mon = <0x0>;
119+ xlnx,iaddr-size = <0x20>;
120+ xlnx,ic-axi-mon = <0x0>;
121+ xlnx,icache-always-used = <0x1>;
122+ xlnx,icache-data-width = <0x0>;
123+ xlnx,icache-force-tag-lutram = <0x0>;
124+ xlnx,icache-line-len = <0x4>;
125+ xlnx,icache-streams = <0x1>;
126+ xlnx,icache-victims = <0x8>;
127+ xlnx,ill-opcode-exception = <0x1>;
128+ xlnx,imprecise-exceptions = <0x0>;
129+ xlnx,instr-size = <0x20>;
130+ xlnx,interconnect = <0x2>;
131+ xlnx,interrupt-is-edge = <0x0>;
132+ xlnx,interrupt-mon = <0x0>;
133+ xlnx,ip-axi-mon = <0x0>;
134+ xlnx,lockstep-select = <0x0>;
135+ xlnx,lockstep-slave = <0x0>;
136+ xlnx,mmu-dtlb-size = <0x4>;
137+ xlnx,mmu-itlb-size = <0x2>;
138+ xlnx,mmu-privileged-instr = <0x0>;
139+ xlnx,mmu-tlb-access = <0x3>;
140+ xlnx,mmu-zones = <0x2>;
141+ xlnx,num-sync-ff-clk = <0x2>;
142+ xlnx,num-sync-ff-clk-debug = <0x2>;
143+ xlnx,num-sync-ff-clk-irq = <0x1>;
144+ xlnx,num-sync-ff-dbg-clk = <0x1>;
145+ xlnx,number-of-pc-brk = <0x1>;
146+ xlnx,number-of-rd-addr-brk = <0x0>;
147+ xlnx,number-of-wr-addr-brk = <0x0>;
148+ xlnx,opcode-0x0-illegal = <0x1>;
149+ xlnx,optimization = <0x0>;
150+ xlnx,pc-width = <0x20>;
151+ xlnx,pvr = <0x2>;
152+ xlnx,pvr-user1 = <0x0>;
153+ xlnx,pvr-user2 = <0x0>;
154+ xlnx,reset-msr = <0x0>;
155+ xlnx,sco = <0x0>;
156+ xlnx,trace = <0x0>;
157+ xlnx,unaligned-exceptions = <0x1>;
158+ xlnx,use-barrel = <0x1>;
159+ xlnx,use-branch-target-cache = <0x0>;
160+ xlnx,use-config-reset = <0x0>;
161+ xlnx,use-dcache = <0x1>;
162+ xlnx,use-div = <0x1>;
163+ xlnx,use-ext-brk = <0x0>;
164+ xlnx,use-ext-nm-brk = <0x0>;
165+ xlnx,use-extended-fsl-instr = <0x0>;
166+ xlnx,use-fpu = <0x0>;
167+ xlnx,use-hw-mul = <0x2>;
168+ xlnx,use-icache = <0x1>;
169+ xlnx,use-interrupt = <0x2>;
170+ xlnx,use-mmu = <0x3>;
171+ xlnx,use-msr-instr = <0x1>;
172+ xlnx,use-non-secure = <0x0>;
173+ xlnx,use-pcmp-instr = <0x1>;
174+ xlnx,use-reorder-instr = <0x1>;
175+ xlnx,use-stack-protection = <0x0>;
176+ };
177+ };
178+
179+ clocks {
180+ #address-cells = <0x1>;
181+ #size-cells = <0x0>;
182+
183+ clk_cpu@0 {
184+ #clock-cells = <0x0>;
185+ clock-frequency = <0xbebc200>;
186+ clock-output-names = "clk_cpu";
187+ compatible = "fixed-clock";
188+ reg = <0x0>;
189+ linux,phandle = <0x3>;
190+ phandle = <0x3>;
191+ };
192+
193+ clk_bus_0@1 {
194+ #clock-cells = <0x0>;
195+ clock-frequency = <0xbebc200>;
196+ clock-output-names = "clk_bus_0";
197+ compatible = "fixed-clock";
198+ reg = <0x1>;
199+ linux,phandle = <0x8>;
200+ phandle = <0x8>;
201+ };
202+ };
203+
204+ amba_pl {
205+ #address-cells = <0x1>;
206+ #size-cells = <0x1>;
207+ compatible = "simple-bus";
208+ ranges;
209+ linux,phandle = <0x2>;
210+ phandle = <0x2>;
211+
212+ ethernet@40c00000 {
213+ axistream-connected = <0x5>;
214+ axistream-control-connected = <0x5>;
215+ clock-frequency = <0x5f5e100>;
216+ compatible = "xlnx,axi-ethernet-1.00.a";
217+ device_type = "network";
218+ interrupt-parent = <0x4>;
219+ interrupts = <0x4 0x2>;
220+ phy-mode = "gmii";
221+ reg = <0x40c00000 0x40000>;
222+ xlnx = <0x0>;
223+ xlnx,axiliteclkrate = <0x0>;
224+ xlnx,axisclkrate = <0x0>;
225+ xlnx,gt-type = <0x0>;
226+ xlnx,phy-type = <0x1>;
227+ xlnx,phyaddr = <0x1>;
228+ xlnx,rable = <0x0>;
229+ xlnx,rxcsum = <0x0>;
230+ xlnx,rxlane0-placement = <0x0>;
231+ xlnx,rxlane1-placement = <0x0>;
232+ xlnx,rxmem = <0x1000>;
233+ xlnx,rxnibblebitslice0used = <0x1>;
234+ xlnx,tx-in-upper-nibble = <0x1>;
235+ xlnx,txcsum = <0x0>;
236+ xlnx,txlane0-placement = <0x0>;
237+ xlnx,txlane1-placement = <0x0>;
238+ local-mac-address = [00 0a 35 00 22 01];
239+ phy-handle = <0x6>;
240+ linux,phandle = <0x7>;
241+ phandle = <0x7>;
242+
243+ mdio {
244+ #address-cells = <0x1>;
245+ #size-cells = <0x0>;
246+
247+ phy@7 {
248+ compatible = "marvell,88e1111";
249+ device_type = "ethernet-phy";
250+ reg = <0x7>;
251+ linux,phandle = <0x6>;
252+ phandle = <0x6>;
253+ };
254+ };
255+ };
256+
257+ dma@41e00000 {
258+ #dma-cells = <0x1>;
259+ axistream-connected = <0x7>;
260+ axistream-control-connected = <0x7>;
261+ compatible = "xlnx,axi-dma-1.00.a";
262+ interrupt-parent = <0x4>;
263+ interrupts = <0x3 0x2 0x2 0x2>;
264+ reg = <0x41e00000 0x10000>;
265+ linux,phandle = <0x5>;
266+ phandle = <0x5>;
267+ };
268+
269+ timer@41c00000 {
270+ clock-frequency = <0xbebc200>;
271+ clocks = <0x8>;
272+ compatible = "xlnx,xps-timer-1.00.a";
273+ interrupt-parent = <0x4>;
274+ interrupts = <0x5 0x2>;
275+ reg = <0x41c00000 0x10000>;
276+ xlnx,count-width = <0x20>;
277+ xlnx,gen0-assert = <0x1>;
278+ xlnx,gen1-assert = <0x1>;
279+ xlnx,one-timer-only = <0x0>;
280+ xlnx,trig0-assert = <0x1>;
281+ xlnx,trig1-assert = <0x1>;
282+ };
283+
284+ gpio@40010000 {
285+ #gpio-cells = <0x2>;
286+ compatible = "xlnx,xps-gpio-1.00.a";
287+ gpio-controller;
288+ reg = <0x40010000 0x10000>;
289+ xlnx,all-inputs = <0x1>;
290+ xlnx,all-inputs-2 = <0x0>;
291+ xlnx,all-outputs = <0x0>;
292+ xlnx,all-outputs-2 = <0x0>;
293+ xlnx,dout-default = <0x0>;
294+ xlnx,dout-default-2 = <0x0>;
295+ xlnx,gpio-width = <0x4>;
296+ xlnx,gpio2-width = <0x20>;
297+ xlnx,interrupt-present = <0x0>;
298+ xlnx,is-dual = <0x0>;
299+ xlnx,tri-default = <0xffffffff>;
300+ xlnx,tri-default-2 = <0xffffffff>;
301+ };
302+
303+ i2c@40800000 {
304+ #address-cells = <0x1>;
305+ #size-cells = <0x0>;
306+ compatible = "xlnx,xps-iic-2.00.a";
307+ interrupt-parent = <0x4>;
308+ interrupts = <0x1 0x2>;
309+ reg = <0x40800000 0x10000>;
310+
311+ i2cswitch@74 {
312+ compatible = "nxp,pca9548";
313+ #address-cells = <0x1>;
314+ #size-cells = <0x0>;
315+ reg = <0x74>;
316+
317+ i2c@0 {
318+ #address-cells = <0x1>;
319+ #size-cells = <0x0>;
320+ reg = <0x0>;
321+
322+ clock-generator@5d {
323+ #clock-cells = <0x0>;
324+ compatible = "silabs,si570";
325+ temperature-stability = <0x32>;
326+ reg = <0x5d>;
327+ factory-fout = <0x9502f90>;
328+ clock-frequency = <0x8d9ee20>;
329+ };
330+ };
331+
332+ i2c@3 {
333+ #address-cells = <0x1>;
334+ #size-cells = <0x0>;
335+ reg = <0x3>;
336+
337+ eeprom@54 {
338+ compatible = "at,24c08";
339+ reg = <0x54>;
340+ };
341+ };
342+ };
343+ };
344+
345+ gpio@40020000 {
346+ #gpio-cells = <0x2>;
347+ compatible = "xlnx,xps-gpio-1.00.a";
348+ gpio-controller;
349+ reg = <0x40020000 0x10000>;
350+ xlnx,all-inputs = <0x0>;
351+ xlnx,all-inputs-2 = <0x0>;
352+ xlnx,all-outputs = <0x1>;
353+ xlnx,all-outputs-2 = <0x0>;
354+ xlnx,dout-default = <0x0>;
355+ xlnx,dout-default-2 = <0x0>;
356+ xlnx,gpio-width = <0x8>;
357+ xlnx,gpio2-width = <0x20>;
358+ xlnx,interrupt-present = <0x0>;
359+ xlnx,is-dual = <0x0>;
360+ xlnx,tri-default = <0xffffffff>;
361+ xlnx,tri-default-2 = <0xffffffff>;
362+ };
363+
364+ flash@60000000 {
365+ bank-width = <0x2>;
366+ compatible = "cfi-flash";
367+ reg = <0x60000000 0x8000000>;
368+ xlnx,axi-clk-period-ps = <0x1388>;
369+ xlnx,include-datawidth-matching-0 = <0x1>;
370+ xlnx,include-datawidth-matching-1 = <0x1>;
371+ xlnx,include-datawidth-matching-2 = <0x1>;
372+ xlnx,include-datawidth-matching-3 = <0x1>;
373+ xlnx,include-negedge-ioregs = <0x0>;
374+ xlnx,lflash-period-ps = <0x1388>;
375+ xlnx,linear-flash-sync-burst = <0x0>;
376+ xlnx,max-mem-width = <0x10>;
377+ xlnx,mem-a-lsb = <0x0>;
378+ xlnx,mem-a-msb = <0x1f>;
379+ xlnx,mem0-type = <0x2>;
380+ xlnx,mem0-width = <0x10>;
381+ xlnx,mem1-type = <0x0>;
382+ xlnx,mem1-width = <0x10>;
383+ xlnx,mem2-type = <0x0>;
384+ xlnx,mem2-width = <0x10>;
385+ xlnx,mem3-type = <0x0>;
386+ xlnx,mem3-width = <0x10>;
387+ xlnx,num-banks-mem = <0x1>;
388+ xlnx,page-size = <0x10>;
389+ xlnx,parity-type-mem-0 = <0x0>;
390+ xlnx,parity-type-mem-1 = <0x0>;
391+ xlnx,parity-type-mem-2 = <0x0>;
392+ xlnx,parity-type-mem-3 = <0x0>;
393+ xlnx,port-diff = <0x0>;
394+ xlnx,s-axi-en-reg = <0x0>;
395+ xlnx,s-axi-mem-addr-width = <0x20>;
396+ xlnx,s-axi-mem-data-width = <0x20>;
397+ xlnx,s-axi-mem-id-width = <0x1>;
398+ xlnx,s-axi-reg-addr-width = <0x5>;
399+ xlnx,s-axi-reg-data-width = <0x20>;
400+ xlnx,synch-pipedelay-0 = <0x1>;
401+ xlnx,synch-pipedelay-1 = <0x1>;
402+ xlnx,synch-pipedelay-2 = <0x1>;
403+ xlnx,synch-pipedelay-3 = <0x1>;
404+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
405+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
406+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
407+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
408+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
409+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
410+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
411+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
412+ xlnx,thzce-ps-mem-0 = <0x88b8>;
413+ xlnx,thzce-ps-mem-1 = <0x1b58>;
414+ xlnx,thzce-ps-mem-2 = <0x1b58>;
415+ xlnx,thzce-ps-mem-3 = <0x1b58>;
416+ xlnx,thzoe-ps-mem-0 = <0x1b58>;
417+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
418+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
419+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
420+ xlnx,tlzwe-ps-mem-0 = <0xc350>;
421+ xlnx,tlzwe-ps-mem-1 = <0x0>;
422+ xlnx,tlzwe-ps-mem-2 = <0x0>;
423+ xlnx,tlzwe-ps-mem-3 = <0x0>;
424+ xlnx,tpacc-ps-flash-0 = <0x61a8>;
425+ xlnx,tpacc-ps-flash-1 = <0x61a8>;
426+ xlnx,tpacc-ps-flash-2 = <0x61a8>;
427+ xlnx,tpacc-ps-flash-3 = <0x61a8>;
428+ xlnx,twc-ps-mem-0 = <0x11170>;
429+ xlnx,twc-ps-mem-1 = <0x3a98>;
430+ xlnx,twc-ps-mem-2 = <0x3a98>;
431+ xlnx,twc-ps-mem-3 = <0x3a98>;
432+ xlnx,twp-ps-mem-0 = <0x13880>;
433+ xlnx,twp-ps-mem-1 = <0x2ee0>;
434+ xlnx,twp-ps-mem-2 = <0x2ee0>;
435+ xlnx,twp-ps-mem-3 = <0x2ee0>;
436+ xlnx,twph-ps-mem-0 = <0x13880>;
437+ xlnx,twph-ps-mem-1 = <0x2ee0>;
438+ xlnx,twph-ps-mem-2 = <0x2ee0>;
439+ xlnx,twph-ps-mem-3 = <0x2ee0>;
440+ xlnx,use-startup = <0x0>;
441+ xlnx,use-startup-int = <0x0>;
442+ xlnx,wr-rec-time-mem-0 = <0x186a0>;
443+ xlnx,wr-rec-time-mem-1 = <0x6978>;
444+ xlnx,wr-rec-time-mem-2 = <0x6978>;
445+ xlnx,wr-rec-time-mem-3 = <0x6978>;
446+ #address-cells = <0x1>;
447+ #size-cells = <0x1>;
448+
449+ partition@0x00000000 {
450+ label = "fpga";
451+ reg = <0x0 0xb00000>;
452+ };
453+
454+ partition@0x00b00000 {
455+ label = "boot";
456+ reg = <0xb00000 0x60000>;
457+ };
458+
459+ partition@0x00b60000 {
460+ label = "bootenv";
461+ reg = <0xb60000 0x20000>;
462+ };
463+
464+ partition@0x00b80000 {
465+ label = "kernel";
466+ reg = <0xb80000 0xc00000>;
467+ };
468+
469+ partition@0x01780000 {
470+ label = "spare";
471+ reg = <0x1780000 0x0>;
472+ };
473+ };
474+
475+ interrupt-controller@41200000 {
476+ #interrupt-cells = <0x2>;
477+ compatible = "xlnx,xps-intc-1.00.a";
478+ interrupt-controller;
479+ reg = <0x41200000 0x10000>;
480+ xlnx,kind-of-intr = <0x0>;
481+ xlnx,num-intr-inputs = <0x6>;
482+ linux,phandle = <0x4>;
483+ phandle = <0x4>;
484+ };
485+
486+ gpio@40030000 {
487+ #gpio-cells = <0x2>;
488+ compatible = "xlnx,xps-gpio-1.00.a";
489+ gpio-controller;
490+ reg = <0x40030000 0x10000>;
491+ xlnx,all-inputs = <0x1>;
492+ xlnx,all-inputs-2 = <0x0>;
493+ xlnx,all-outputs = <0x0>;
494+ xlnx,all-outputs-2 = <0x0>;
495+ xlnx,dout-default = <0x0>;
496+ xlnx,dout-default-2 = <0x0>;
497+ xlnx,gpio-width = <0x5>;
498+ xlnx,gpio2-width = <0x20>;
499+ xlnx,interrupt-present = <0x0>;
500+ xlnx,is-dual = <0x0>;
501+ xlnx,tri-default = <0xffffffff>;
502+ xlnx,tri-default-2 = <0xffffffff>;
503+ };
504+
505+ gpio@40000000 {
506+ #gpio-cells = <0x2>;
507+ compatible = "xlnx,xps-gpio-1.00.a";
508+ gpio-controller;
509+ reg = <0x40000000 0x10000>;
510+ xlnx,all-inputs = <0x0>;
511+ xlnx,all-inputs-2 = <0x0>;
512+ xlnx,all-outputs = <0x1>;
513+ xlnx,all-outputs-2 = <0x0>;
514+ xlnx,dout-default = <0x0>;
515+ xlnx,dout-default-2 = <0x0>;
516+ xlnx,gpio-width = <0x1>;
517+ xlnx,gpio2-width = <0x20>;
518+ xlnx,interrupt-present = <0x0>;
519+ xlnx,is-dual = <0x0>;
520+ xlnx,tri-default = <0xffffffff>;
521+ xlnx,tri-default-2 = <0xffffffff>;
522+ linux,phandle = <0x1>;
523+ phandle = <0x1>;
524+ };
525+
526+ serial@44a00000 {
527+ clock-frequency = <0xbebc200>;
528+ clocks = <0x8>;
529+ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
530+ current-speed = <0x1c200>;
531+ device_type = "serial";
532+ interrupt-parent = <0x4>;
533+ interrupts = <0x0 0x2>;
534+ port-number = <0x0>;
535+ reg = <0x44a00000 0x10000>;
536+ reg-offset = <0x1000>;
537+ reg-shift = <0x2>;
538+ xlnx,external-xin-clk-hz = <0x17d7840>;
539+ xlnx,external-xin-clk-hz-d = <0x19>;
540+ xlnx,has-external-rclk = <0x0>;
541+ xlnx,has-external-xin = <0x0>;
542+ xlnx,is-a-16550 = <0x1>;
543+ xlnx,s-axi-aclk-freq-hz-d = "200.0";
544+ xlnx,use-modem-ports = <0x1>;
545+ xlnx,use-user-ports = <0x1>;
546+ };
547 } ;
548 } ;
549diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
550index 36bdd96..0b301bb 100644
551--- a/board/xilinx/microblaze-generic/config.mk
552+++ b/board/xilinx/microblaze-generic/config.mk
553@@ -1,18 +1,10 @@
554-#
555-# (C) Copyright 2007 Michal Simek
556-#
557-# Michal SIMEK <monstr@monstr.eu>
558-#
559-# SPDX-License-Identifier: GPL-2.0+
560-#
561-# CAUTION: This file is a faked configuration !!!
562-# There is no real target for the microblaze-generic
563-# configuration. You have to replace this file with
564-# the generated file from your Xilinx design flow.
565-#
566+TEXT_BASE = 0x80400000
567+CONFIG_SYS_TEXT_BASE = 0x80400000
568
569-CONFIG_SYS_TEXT_BASE = 0x29000000
570-
571-PLATFORM_CPPFLAGS += -mno-xl-soft-mul
572-PLATFORM_CPPFLAGS += -mno-xl-soft-div
573 PLATFORM_CPPFLAGS += -mxl-barrel-shift
574+PLATFORM_CPPFLAGS += -mno-xl-soft-div
575+PLATFORM_CPPFLAGS += -mxl-pattern-compare
576+PLATFORM_CPPFLAGS += -mxl-multiply-high
577+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
578+PLATFORM_CPPFLAGS += -mcpu=v9.6
579+PLATFORM_CPPFLAGS += -fgnu89-inline
580diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
581index 21a7261..0d9e318 100644
582--- a/configs/microblaze-generic_defconfig
583+++ b/configs/microblaze-generic_defconfig
584@@ -1,23 +1,12 @@
585 CONFIG_MICROBLAZE=y
586-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
587-CONFIG_SPL_DM=y
588 CONFIG_TARGET_MICROBLAZE_GENERIC=y
589 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
590-CONFIG_SPL=y
591-CONFIG_FIT=y
592-CONFIG_FIT_VERBOSE=y
593-CONFIG_HUSH_PARSER=y
594-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
595-CONFIG_CMD_GPIO=y
596+CONFIG_SYS_PROMPT="U-Boot> "
597 # CONFIG_CMD_SETEXPR is not set
598-CONFIG_CMD_TFTPPUT=y
599-CONFIG_CMD_DHCP=y
600 CONFIG_CMD_PING=y
601-CONFIG_SPL_OF_CONTROL=y
602 CONFIG_OF_EMBED=y
603-CONFIG_NETCONSOLE=y
604 CONFIG_DM_ETH=y
605+CONFIG_CMD_DHCP=y
606 CONFIG_XILINX_AXIEMAC=y
607-CONFIG_XILINX_EMACLITE=y
608 CONFIG_SYS_NS16550=y
609-CONFIG_XILINX_UARTLITE=y
610+CONFIG_REQUIRE_SERIAL_CONSOLE=y
611diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
612index b424782..4a1e079 100644
613--- a/include/configs/microblaze-generic.h
614+++ b/include/configs/microblaze-generic.h
615@@ -1,343 +1,213 @@
616-/*
617- * (C) Copyright 2007-2010 Michal Simek
618- *
619- * Michal SIMEK <monstr@monstr.eu>
620- *
621- * SPDX-License-Identifier: GPL-2.0+
622- */
623-
624 #ifndef __CONFIG_H
625 #define __CONFIG_H
626
627-#include "../board/xilinx/microblaze-generic/xparameters.h"
628-
629-/* MicroBlaze CPU */
630-#define MICROBLAZE_V5 1
631-
632-/* linear and spi flash memory */
633-#ifdef XILINX_FLASH_START
634-#define FLASH
635-#undef SPIFLASH
636-#undef RAMENV /* hold environment in flash */
637-#else
638-#ifdef XILINX_SPI_FLASH_BASEADDR
639-#undef FLASH
640-#define SPIFLASH
641-#undef RAMENV /* hold environment in flash */
642-#else
643-#undef FLASH
644-#undef SPIFLASH
645-#define RAMENV /* hold environment in RAM */
646-#endif
647-#endif
648-
649-/* uart */
650-# define CONFIG_BAUDRATE 115200
651 /* The following table includes the supported baudrates */
652-# define CONFIG_SYS_BAUDRATE_TABLE \
653- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
654-
655-/* setting reset address */
656-/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
657-
658-/* gpio */
659-#ifdef XILINX_GPIO_BASEADDR
660-# define CONFIG_XILINX_GPIO
661-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
662-#endif
663-#define CONFIG_BOARD_LATE_INIT
664-
665-/* watchdog */
666-#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
667-# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
668-# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
669-# ifndef CONFIG_SPL_BUILD
670-# define CONFIG_HW_WATCHDOG
671-# define CONFIG_XILINX_TB_WATCHDOG
672-# endif
673-#endif
674-
675-#define CONFIG_SYS_MALLOC_LEN 0xC0000
676-
677-/* Stack location before relocation */
678-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
679- CONFIG_SYS_MALLOC_F_LEN)
680-
681-/*
682- * CFI flash memory layout - Example
683- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
684- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
685- *
686- * SECT_SIZE = 0x20000; 128kB is one sector
687- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
688- *
689- * 0x2200_0000 CONFIG_SYS_FLASH_BASE
690- * FREE 256kB
691- * 0x2204_0000 CONFIG_ENV_ADDR
692- * ENV_AREA 128kB
693- * 0x2206_0000
694- * FREE
695- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
696- *
697- */
698-
699-#ifdef FLASH
700-# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
701-# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
702-# define CONFIG_SYS_FLASH_CFI 1
703-# define CONFIG_FLASH_CFI_DRIVER 1
704-/* ?empty sector */
705-# define CONFIG_SYS_FLASH_EMPTY_INFO 1
706-/* max number of memory banks */
707-# define CONFIG_SYS_MAX_FLASH_BANKS 1
708-/* max number of sectors on one chip */
709-# define CONFIG_SYS_MAX_FLASH_SECT 512
710-/* hardware flash protection */
711-# define CONFIG_SYS_FLASH_PROTECTION
712-/* use buffered writes (20x faster) */
713-# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
714-# ifdef RAMENV
715-# define CONFIG_ENV_IS_NOWHERE 1
716-# define CONFIG_ENV_SIZE 0x1000
717-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
718-
719-# else /* FLASH && !RAMENV */
720-# define CONFIG_ENV_IS_IN_FLASH 1
721-/* 128K(one sector) for env */
722-# define CONFIG_ENV_SECT_SIZE 0x20000
723-# define CONFIG_ENV_ADDR \
724- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
725-# define CONFIG_ENV_SIZE 0x20000
726-# endif /* FLASH && !RAMBOOT */
727-#else /* !FLASH */
728-
729-#ifdef SPIFLASH
730-# define CONFIG_SYS_NO_FLASH 1
731-# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
732-# define CONFIG_SPI 1
733-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
734-# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
735-# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
736-
737-# ifdef RAMENV
738-# define CONFIG_ENV_IS_NOWHERE 1
739-# define CONFIG_ENV_SIZE 0x1000
740-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
741-
742-# else /* SPIFLASH && !RAMENV */
743-# define CONFIG_ENV_IS_IN_SPI_FLASH 1
744-# define CONFIG_ENV_SPI_MODE SPI_MODE_3
745-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
746-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
747-/* 128K(two sectors) for env */
748-# define CONFIG_ENV_SECT_SIZE 0x10000
749-# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
750-/* Warning: adjust the offset in respect of other flash content and size */
751-# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
752-# endif /* SPIFLASH && !RAMBOOT */
753-#else /* !SPIFLASH */
754-
755-/* ENV in RAM */
756-# define CONFIG_SYS_NO_FLASH 1
757-# define CONFIG_ENV_IS_NOWHERE 1
758-# define CONFIG_ENV_SIZE 0x1000
759-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
760-#endif /* !SPIFLASH */
761-#endif /* !FLASH */
762-
763-#if defined(XILINX_USE_ICACHE)
764-# define CONFIG_ICACHE
765-#else
766-# undef CONFIG_ICACHE
767-#endif
768-
769-#if defined(XILINX_USE_DCACHE)
770-# define CONFIG_DCACHE
771-#else
772-# undef CONFIG_DCACHE
773-#endif
774-
775-#ifndef XILINX_DCACHE_BYTE_SIZE
776-#define XILINX_DCACHE_BYTE_SIZE 32768
777-#endif
778-
779-/*
780- * BOOTP options
781- */
782+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
783+
784+/* use serial multi for all serial devices */
785+#define CONFIG_SERIAL_MULTI
786+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
787+
788+/* Board name */
789+#define XILINX_BOARD_NAME Xilinx-KC705-2016_1
790+#define CONFIG_HOSTNAME XILINX_BOARD_NAME
791+
792+/* processor - microblaze_0 */
793+#define XILINX_USE_MSR_INSTR 1
794+#define XILINX_FSL_LINKS 0
795+#define XILINX_USE_ICACHE 1
796+#define XILINX_USE_DCACHE 1
797+#define XILINX_DCACHE_BYTE_SIZE 16384
798+#define XILINX_PVR 2
799+#define MICROBLAZE_V5
800+#define CONFIG_CMD_IRQ
801+#define CONFIG_DCACHE
802+#define CONFIG_ICACHE
803+
804+/* main_memory - ddr3_sdram */
805+#define CONFIG_SYS_SDRAM_BASE 0x80000000
806+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
807+
808+/* Memory testing handling */
809+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
810+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
811+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */
812+
813+/* global pointer options */
814+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
815+
816+/* Size of malloc() pool */
817+#define SIZE 0x100000
818+#define CONFIG_SYS_MALLOC_LEN SIZE
819+#define CONFIG_SYS_MONITOR_LEN SIZE
820+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
821+#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
822+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
823+
824+/* stack */
825+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
826+
827+/* No of_control support yet*/
828+
829+/* uart - rs232_uart */
830+#define XILINX_UART16550_BASEADDR 0x44A00000
831+#define CONFIG_UART16550 1
832+#define CONFIG_CONS_INDEX 1
833+#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
834+#define CONFIG_SYS_NS16550_REG_SIZE -4
835+#define CONSOLE_ARG "console=console=ttyS0,115200\0"
836+#define CONFIG_SYS_NS16550_SERIAL
837+#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
838+#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0"
839+#define CONFIG_SYS_NS16550_CLK 200000000
840+#define CONFIG_BAUDRATE 115200
841+
842+/* ethernet - axi_ethernet */
843+#define XILINX_AXIEMAC_BASEADDR 0x40C00000
844+#define CONFIG_PHY_XILINX
845+#define CONFIG_SYS_ENET
846+#define CONFIG_MII
847+#define CONFIG_PHY_GIGE
848+#define CONFIG_PHY_MARVELL
849+#define CONFIG_PHY_NATSEMI
850+#define CONFIG_NET_MULTI
851+#define CONFIG_BOOTP_MAY_FAIL
852+#define CONFIG_NETCONSOLE 1
853+#define XILINX_AXIDMA_BASEADDR 0x41E00000
854+#define CONFIG_SERVERIP 172.19.5.102
855+#define CONFIG_IPADDR
856+
857+/* nor_flash - linear_flash */
858+#define CONFIG_SYS_FLASH_BASE 0x60000000
859+#define CONFIG_SYS_FLASH_END 0x68000000
860+#define CONFIG_SYS_MAX_FLASH_SECT 2048
861+#define CONFIG_SYS_FLASH_PROTECTION
862+#define CONFIG_SYS_FLASH_EMPTY_INFO
863+#define CONFIG_SYS_FLASH_CFI
864+#define CONFIG_FLASH_CFI_DRIVER
865+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
866+#define CONFIG_SYS_MAX_FLASH_BANKS 1
867+#define CONFIG_ENV_IS_IN_FLASH
868+#define CONFIG_ENV_ADDR 0x60b60000
869+#define CONFIG_ENV_SIZE 0x20000
870+#define CONFIG_ENV_SECT_SIZE 0x20000
871+
872+/* timer - axi_timer_0 */
873+#define CONFIG_SYS_TIMER_0_ADDR 0x41C00000
874+#define CONFIG_SYS_TIMER_0 1
875+#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
876+#define CONFIG_SYS_TIMER_0_IRQ 5
877+#define FREQUENCE 200000000
878+#define XILINX_CLOCK_FREQ 200000000
879+
880+/* gpio - reset_gpio */
881+#define XILINX_GPIO_BASEADDR 0x40000000
882+#define CONFIG_SYS_GPIO_0_ADDR 0x40000000
883+#define CONFIG_XILINX_GPIO
884+
885+/* intc - microblaze_0_axi_intc */
886+#define CONFIG_SYS_INTC_0_ADDR 0x41200000
887+#define CONFIG_SYS_INTC_0_NUM 6
888+#define CONFIG_SYS_INTC_0 1
889+
890+/* FPGA */
891+
892+/* Make the BOOTM LEN big enough for the compressed image */
893+#define CONFIG_SYS_BOOTM_LEN 0x1000000
894+
895+
896+/* BOOTP options */
897+#define CONFIG_BOOTP_SERVERIP
898 #define CONFIG_BOOTP_BOOTFILESIZE
899 #define CONFIG_BOOTP_BOOTPATH
900 #define CONFIG_BOOTP_GATEWAY
901 #define CONFIG_BOOTP_HOSTNAME
902
903-/*
904- * Command line configuration.
905- */
906+/*Command line configuration.*/
907 #define CONFIG_CMD_ASKENV
908-#define CONFIG_CMD_IRQ
909-#define CONFIG_CMD_MFSL
910-
911-#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
912-# define CONFIG_CMD_CACHE
913-#else
914-# undef CONFIG_CMD_CACHE
915-#endif
916-
917-#if defined(FLASH)
918-# define CONFIG_CMD_JFFS2
919-# define CONFIG_CMD_UBI
920-# undef CONFIG_CMD_UBIFS
921-
922-# if !defined(RAMENV)
923-# define CONFIG_CMD_SAVES
924-# endif
925-
926-#else
927-#if defined(SPIFLASH)
928-# define CONFIG_CMD_SF
929-
930-# if !defined(RAMENV)
931-# define CONFIG_CMD_SAVES
932-# endif
933-#else
934-# undef CONFIG_CMD_JFFS2
935-# undef CONFIG_CMD_UBI
936-# undef CONFIG_CMD_UBIFS
937-#endif
938-#endif
939-
940-#if defined(CONFIG_CMD_JFFS2)
941-# define CONFIG_MTD_PARTITIONS
942-#endif
943-
944-#if defined(CONFIG_CMD_UBIFS)
945-# define CONFIG_CMD_UBI
946-# define CONFIG_LZO
947-#endif
948-
949-#if defined(CONFIG_CMD_UBI)
950-# define CONFIG_MTD_PARTITIONS
951-# define CONFIG_RBTREE
952-#endif
953-
954-#if defined(CONFIG_MTD_PARTITIONS)
955-/* MTD partitions */
956-#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
957-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
958-#define CONFIG_FLASH_CFI_MTD
959-#define MTDIDS_DEFAULT "nor0=flash-0"
960-
961-/* default mtd partition table */
962-#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
963- "256k(env),3m(kernel),1m(romfs),"\
964- "1m(cramfs),-(jffs2)"
965-#endif
966-
967-/* size of console buffer */
968-#define CONFIG_SYS_CBSIZE 512
969- /* print buffer size */
970-#define CONFIG_SYS_PBSIZE \
971- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
972-/* max number of command args */
973-#define CONFIG_SYS_MAXARGS 15
974-#define CONFIG_SYS_LONGHELP
975-/* default load address */
976-#define CONFIG_SYS_LOAD_ADDR 0
977-
978-#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
979-#define CONFIG_BOOTARGS "root=romfs"
980-#define CONFIG_HOSTNAME XILINX_BOARD_NAME
981-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
982-#define CONFIG_IPADDR 192.168.0.3
983-#define CONFIG_SERVERIP 192.168.0.5
984-#define CONFIG_GATEWAYIP 192.168.0.1
985+#define CONFIG_CMDLINE_EDITING
986+#define CONFIG_CMD_SAVES
987+
988+/* Miscellaneous configurable options */
989+#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */
990+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
991+
992+/* Boot Argument Buffer Size */
993+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
994+#define CONFIG_SYS_LONGHELP
995
996 /* architecture dependent code */
997-#define CONFIG_SYS_USR_EXCEP /* user exception */
998+#define CONFIG_SYS_USR_EXCEP /* user exception */
999+#define CONFIG_SYS_HZ 1000
1000
1001-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
1002+/* Use the HUSH parser */
1003+#define CONFIG_SYS_HUSH_PARSER
1004+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1005
1006-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
1007- "nor0=flash-0\0"\
1008- "mtdparts=mtdparts=flash-0:"\
1009- "256k(u-boot),256k(env),3m(kernel),"\
1010- "1m(romfs),1m(cramfs),-(jffs2)\0"\
1011- "nc=setenv stdout nc;"\
1012- "setenv stdin nc\0" \
1013- "serial=setenv stdout serial;"\
1014- "setenv stdin serial\0"
1015+/* auto-boot delay */
1016+#define CONFIG_BOOTDELAY 4
1017
1018-#define CONFIG_CMDLINE_EDITING
1019+/* Don't define BOOTARGS, we get it from the DTB chosen fragment */
1020+#undef CONFIG_BOOTARGS
1021
1022-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
1023+#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */
1024
1025-/* Enable flat device tree support */
1026-#define CONFIG_LMB 1
1027+/* FIT image support */
1028+#define CONFIG_FIT 1
1029+#define CONFIG_LMB
1030 #define CONFIG_OF_LIBFDT 1
1031-
1032-#if defined(CONFIG_XILINX_AXIEMAC)
1033-# define CONFIG_MII 1
1034-# define CONFIG_CMD_MII 1
1035-# define CONFIG_PHY_GIGE 1
1036-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
1037-# define CONFIG_PHY_ATHEROS 1
1038-# define CONFIG_PHY_BROADCOM 1
1039-# define CONFIG_PHY_DAVICOM 1
1040-# define CONFIG_PHY_LXT 1
1041-# define CONFIG_PHY_MARVELL 1
1042-# define CONFIG_PHY_MICREL 1
1043-# define CONFIG_PHY_MICREL_KSZ9021
1044-# define CONFIG_PHY_NATSEMI 1
1045-# define CONFIG_PHY_REALTEK 1
1046-# define CONFIG_PHY_VITESSE 1
1047-#else
1048-# undef CONFIG_MII
1049-# undef CONFIG_CMD_MII
1050-#endif
1051-
1052-/* SPL part */
1053-#define CONFIG_CMD_SPL
1054-#define CONFIG_SPL_FRAMEWORK
1055-#define CONFIG_SPL_LIBCOMMON_SUPPORT
1056-#define CONFIG_SPL_LIBGENERIC_SUPPORT
1057-#define CONFIG_SPL_SERIAL_SUPPORT
1058-#define CONFIG_SPL_BOARD_INIT
1059-
1060-#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
1061-
1062-#define CONFIG_SPL_RAM_DEVICE
1063-#ifdef CONFIG_SYS_FLASH_BASE
1064-# define CONFIG_SPL_NOR_SUPPORT
1065-# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
1066-#endif
1067-
1068-/* for booting directly linux */
1069-#define CONFIG_SPL_OS_BOOT
1070-
1071-#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
1072- 0x60000)
1073-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
1074- 0x40000)
1075-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
1076- 0x1000000)
1077-
1078-/* SP location before relocation, must use scratch RAM */
1079-/* BRAM start */
1080-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
1081-/* BRAM size - will be generated */
1082-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
1083-
1084-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
1085- CONFIG_SYS_INIT_RAM_SIZE - \
1086- CONFIG_SYS_MALLOC_F_LEN)
1087-
1088-/* Just for sure that there is a space for stack */
1089-#define CONFIG_SPL_STACK_SIZE 0x100
1090-
1091-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
1092-
1093-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
1094- CONFIG_SYS_INIT_RAM_ADDR - \
1095- CONFIG_SYS_MALLOC_F_LEN - \
1096- CONFIG_SPL_STACK_SIZE)
1097-
1098-#endif /* __CONFIG_H */
1099+#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
1100+
1101+/* Initial memory map for Linux */
1102+#define CONFIG_SYS_BOOTMAPSZ 0x8000000
1103+
1104+/* PREBOOT */
1105+#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
1106+
1107+/* Extra U-Boot Env settings */
1108+#define CONFIG_EXTRA_ENV_SETTINGS \
1109+ SERIAL_MULTI \
1110+ CONSOLE_ARG \
1111+ ESERIAL0 \
1112+ "nc=setenv stdout nc;setenv stdin nc;\0" \
1113+ "ethaddr=00:0a:35:00:22:01\0" \
1114+ "autoload=no\0" \
1115+ "clobstart=0x81000000\0" \
1116+ "netstart=0x81000000\0" \
1117+ "dtbnetstart=0x82800000\0" \
1118+ "loadaddr=0x81000000\0" \
1119+ "bootsize=0x60000\0" \
1120+ "bootstart=0x60b00000\0" \
1121+ "boot_img=u-boot.bin\0" \
1122+ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \
1123+ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \
1124+ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \
1125+ "bootenvsize=0x20000\0" \
1126+ "bootenvstart=0x60b60000\0" \
1127+ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \
1128+ "kernelsize=0xc00000\0" \
1129+ "kernelstart=0x60b80000\0" \
1130+ "kernel_img=image.ub\0" \
1131+ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
1132+ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \
1133+ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \
1134+ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \
1135+ "fpgasize=0xb00000\0" \
1136+ "fpgastart=0x60000000\0" \
1137+ "fpga_img=system.bit.bin\0" \
1138+ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \
1139+ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \
1140+ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \
1141+ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
1142+ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
1143+ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
1144+ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \
1145+ "default_bootcmd=bootm ${kernelstart}\0" \
1146+""
1147+
1148+/* BOOTCOMMAND */
1149+#define CONFIG_BOOTCOMMAND "run default_bootcmd"
1150+
1151+#undef CONFIG_SPL_BUILD /* Disable SPL by default*/
1152+
1153+#endif /* __PLNX_CONFIG_H */
1154--
11552.1.4
1156
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 15:22:55 +0000